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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_gpio.c@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
154:37f96f9d4de2 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_gpio.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 /*******************************************************************************
<> 154:37f96f9d4de2 34 * Variables
<> 154:37f96f9d4de2 35 ******************************************************************************/
<> 154:37f96f9d4de2 36 static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
<> 154:37f96f9d4de2 37 static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
<> 154:37f96f9d4de2 38
<> 154:37f96f9d4de2 39 /*******************************************************************************
<> 154:37f96f9d4de2 40 * Prototypes
<> 154:37f96f9d4de2 41 ******************************************************************************/
<> 154:37f96f9d4de2 42
<> 154:37f96f9d4de2 43 /*!
<> 154:37f96f9d4de2 44 * @brief Gets the GPIO instance according to the GPIO base
<> 154:37f96f9d4de2 45 *
<> 154:37f96f9d4de2 46 * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
<> 154:37f96f9d4de2 47 * @retval GPIO instance
<> 154:37f96f9d4de2 48 */
<> 154:37f96f9d4de2 49 static uint32_t GPIO_GetInstance(GPIO_Type *base);
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 /*******************************************************************************
<> 154:37f96f9d4de2 52 * Code
<> 154:37f96f9d4de2 53 ******************************************************************************/
<> 154:37f96f9d4de2 54
<> 154:37f96f9d4de2 55 static uint32_t GPIO_GetInstance(GPIO_Type *base)
<> 154:37f96f9d4de2 56 {
<> 154:37f96f9d4de2 57 uint32_t instance;
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /* Find the instance index from base address mappings. */
<> 154:37f96f9d4de2 60 for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++)
<> 154:37f96f9d4de2 61 {
<> 154:37f96f9d4de2 62 if (s_gpioBases[instance] == base)
<> 154:37f96f9d4de2 63 {
<> 154:37f96f9d4de2 64 break;
<> 154:37f96f9d4de2 65 }
<> 154:37f96f9d4de2 66 }
<> 154:37f96f9d4de2 67
<> 154:37f96f9d4de2 68 assert(instance < FSL_FEATURE_SOC_GPIO_COUNT);
<> 154:37f96f9d4de2 69
<> 154:37f96f9d4de2 70 return instance;
<> 154:37f96f9d4de2 71 }
<> 154:37f96f9d4de2 72
<> 154:37f96f9d4de2 73 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
<> 154:37f96f9d4de2 74 {
<> 154:37f96f9d4de2 75 assert(config);
<> 154:37f96f9d4de2 76
<> 154:37f96f9d4de2 77 if (config->pinDirection == kGPIO_DigitalInput)
<> 154:37f96f9d4de2 78 {
<> 154:37f96f9d4de2 79 base->PDDR &= ~(1U << pin);
<> 154:37f96f9d4de2 80 }
<> 154:37f96f9d4de2 81 else
<> 154:37f96f9d4de2 82 {
<> 154:37f96f9d4de2 83 GPIO_WritePinOutput(base, pin, config->outputLogic);
<> 154:37f96f9d4de2 84 base->PDDR |= (1U << pin);
<> 154:37f96f9d4de2 85 }
<> 154:37f96f9d4de2 86 }
<> 154:37f96f9d4de2 87
<> 154:37f96f9d4de2 88 uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
<> 154:37f96f9d4de2 89 {
<> 154:37f96f9d4de2 90 uint8_t instance;
<> 154:37f96f9d4de2 91 PORT_Type *portBase;
<> 154:37f96f9d4de2 92 instance = GPIO_GetInstance(base);
<> 154:37f96f9d4de2 93 portBase = s_portBases[instance];
<> 154:37f96f9d4de2 94 return portBase->ISFR;
<> 154:37f96f9d4de2 95 }
<> 154:37f96f9d4de2 96
<> 154:37f96f9d4de2 97 void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 98 {
<> 154:37f96f9d4de2 99 uint8_t instance;
<> 154:37f96f9d4de2 100 PORT_Type *portBase;
<> 154:37f96f9d4de2 101 instance = GPIO_GetInstance(base);
<> 154:37f96f9d4de2 102 portBase = s_portBases[instance];
<> 154:37f96f9d4de2 103 portBase->ISFR = mask;
<> 154:37f96f9d4de2 104 }
<> 154:37f96f9d4de2 105
<> 154:37f96f9d4de2 106 #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
<> 154:37f96f9d4de2 107 void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
<> 154:37f96f9d4de2 108 {
<> 154:37f96f9d4de2 109 base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
<> 154:37f96f9d4de2 110 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
<> 154:37f96f9d4de2 111 }
<> 154:37f96f9d4de2 112 #endif
<> 154:37f96f9d4de2 113
<> 154:37f96f9d4de2 114 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
<> 154:37f96f9d4de2 115
<> 154:37f96f9d4de2 116 /*******************************************************************************
<> 154:37f96f9d4de2 117 * Variables
<> 154:37f96f9d4de2 118 ******************************************************************************/
<> 154:37f96f9d4de2 119 static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
<> 154:37f96f9d4de2 120
<> 154:37f96f9d4de2 121 /*******************************************************************************
<> 154:37f96f9d4de2 122 * Prototypes
<> 154:37f96f9d4de2 123 ******************************************************************************/
<> 154:37f96f9d4de2 124 /*!
<> 154:37f96f9d4de2 125 * @brief Gets the FGPIO instance according to the GPIO base
<> 154:37f96f9d4de2 126 *
<> 154:37f96f9d4de2 127 * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
<> 154:37f96f9d4de2 128 * @retval FGPIO instance
<> 154:37f96f9d4de2 129 */
<> 154:37f96f9d4de2 130 static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
<> 154:37f96f9d4de2 131
<> 154:37f96f9d4de2 132 /*******************************************************************************
<> 154:37f96f9d4de2 133 * Code
<> 154:37f96f9d4de2 134 ******************************************************************************/
<> 154:37f96f9d4de2 135
<> 154:37f96f9d4de2 136 static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
<> 154:37f96f9d4de2 137 {
<> 154:37f96f9d4de2 138 uint32_t instance;
<> 154:37f96f9d4de2 139
<> 154:37f96f9d4de2 140 /* Find the instance index from base address mappings. */
<> 154:37f96f9d4de2 141 for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++)
<> 154:37f96f9d4de2 142 {
<> 154:37f96f9d4de2 143 if (s_fgpioBases[instance] == base)
<> 154:37f96f9d4de2 144 {
<> 154:37f96f9d4de2 145 break;
<> 154:37f96f9d4de2 146 }
<> 154:37f96f9d4de2 147 }
<> 154:37f96f9d4de2 148
<> 154:37f96f9d4de2 149 assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT);
<> 154:37f96f9d4de2 150
<> 154:37f96f9d4de2 151 return instance;
<> 154:37f96f9d4de2 152 }
<> 154:37f96f9d4de2 153
<> 154:37f96f9d4de2 154 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
<> 154:37f96f9d4de2 155 {
<> 154:37f96f9d4de2 156 assert(config);
<> 154:37f96f9d4de2 157
<> 154:37f96f9d4de2 158 if (config->pinDirection == kGPIO_DigitalInput)
<> 154:37f96f9d4de2 159 {
<> 154:37f96f9d4de2 160 base->PDDR &= ~(1U << pin);
<> 154:37f96f9d4de2 161 }
<> 154:37f96f9d4de2 162 else
<> 154:37f96f9d4de2 163 {
<> 154:37f96f9d4de2 164 FGPIO_WritePinOutput(base, pin, config->outputLogic);
<> 154:37f96f9d4de2 165 base->PDDR |= (1U << pin);
<> 154:37f96f9d4de2 166 }
<> 154:37f96f9d4de2 167 }
<> 154:37f96f9d4de2 168
<> 154:37f96f9d4de2 169 uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
<> 154:37f96f9d4de2 170 {
<> 154:37f96f9d4de2 171 uint8_t instance;
<> 154:37f96f9d4de2 172 instance = FGPIO_GetInstance(base);
<> 154:37f96f9d4de2 173 PORT_Type *portBase;
<> 154:37f96f9d4de2 174 portBase = s_portBases[instance];
<> 154:37f96f9d4de2 175 return portBase->ISFR;
<> 154:37f96f9d4de2 176 }
<> 154:37f96f9d4de2 177
<> 154:37f96f9d4de2 178 void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 179 {
<> 154:37f96f9d4de2 180 uint8_t instance;
<> 154:37f96f9d4de2 181 instance = FGPIO_GetInstance(base);
<> 154:37f96f9d4de2 182 PORT_Type *portBase;
<> 154:37f96f9d4de2 183 portBase = s_portBases[instance];
<> 154:37f96f9d4de2 184 portBase->ISFR = mask;
<> 154:37f96f9d4de2 185 }
<> 154:37f96f9d4de2 186
<> 154:37f96f9d4de2 187 #if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
<> 154:37f96f9d4de2 188 void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
<> 154:37f96f9d4de2 189 {
<> 154:37f96f9d4de2 190 base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
<> 154:37f96f9d4de2 191 (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
<> 154:37f96f9d4de2 192 }
<> 154:37f96f9d4de2 193 #endif
<> 154:37f96f9d4de2 194
<> 154:37f96f9d4de2 195 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */