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targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /******************************************************************************
<> 149:156823d33999 2 * @file dac.h
<> 149:156823d33999 3 * @version V0.10
<> 149:156823d33999 4 * $Revision: 12 $
<> 149:156823d33999 5 * $Date: 15/08/11 10:26a $
<> 149:156823d33999 6 * @brief M451 series DAC driver header file
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 *****************************************************************************/
<> 149:156823d33999 11 #ifndef __DAC_H__
<> 149:156823d33999 12 #define __DAC_H__
<> 149:156823d33999 13
<> 149:156823d33999 14 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 15 /* Include related headers */
<> 149:156823d33999 16 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 17 #include "M451Series.h"
<> 149:156823d33999 18
<> 149:156823d33999 19
<> 149:156823d33999 20 #ifdef __cplusplus
<> 149:156823d33999 21 extern "C"
<> 149:156823d33999 22 {
<> 149:156823d33999 23 #endif
<> 149:156823d33999 24
<> 149:156823d33999 25
<> 149:156823d33999 26 /** @addtogroup Standard_Driver Standard Driver
<> 149:156823d33999 27 @{
<> 149:156823d33999 28 */
<> 149:156823d33999 29
<> 149:156823d33999 30 /** @addtogroup DAC_Driver DAC Driver
<> 149:156823d33999 31 @{
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34
<> 149:156823d33999 35 /** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
<> 149:156823d33999 36 @{
<> 149:156823d33999 37 */
<> 149:156823d33999 38
<> 149:156823d33999 39 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 40 /* DAC_CTL Constant Definitions */
<> 149:156823d33999 41 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 42 #define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. */
<> 149:156823d33999 43 #define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment */
<> 149:156823d33999 44
<> 149:156823d33999 45 #define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger */
<> 149:156823d33999 46 #define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger */
<> 149:156823d33999 47 #define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger */
<> 149:156823d33999 48 #define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger */
<> 149:156823d33999 49 #define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger */
<> 149:156823d33999 50 #define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger */
<> 149:156823d33999 51 #define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger */
<> 149:156823d33999 52 #define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger */
<> 149:156823d33999 53 #define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger */
<> 149:156823d33999 54 #define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger */
<> 149:156823d33999 55 #define DAC_PWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM0 trigger */
<> 149:156823d33999 56 #define DAC_PWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM1 trigger */
<> 149:156823d33999 57
<> 149:156823d33999 58 #define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable */
<> 149:156823d33999 59 #define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable */
<> 149:156823d33999 60
<> 149:156823d33999 61
<> 149:156823d33999 62 /*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
<> 149:156823d33999 63
<> 149:156823d33999 64
<> 149:156823d33999 65 /** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
<> 149:156823d33999 66 @{
<> 149:156823d33999 67 */
<> 149:156823d33999 68 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 69 /* DAC Macro Definitions */
<> 149:156823d33999 70 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 71
<> 149:156823d33999 72 /**
<> 149:156823d33999 73 * @brief Start the D/A conversion.
<> 149:156823d33999 74 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 75 * @return None
<> 149:156823d33999 76 * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
<> 149:156823d33999 77 */
<> 149:156823d33999 78 #define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
<> 149:156823d33999 79
<> 149:156823d33999 80 /**
<> 149:156823d33999 81 * @brief Enable DAC data left-aligned.
<> 149:156823d33999 82 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 83 * @return None
<> 149:156823d33999 84 * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
<> 149:156823d33999 85 */
<> 149:156823d33999 86 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
<> 149:156823d33999 87
<> 149:156823d33999 88 /**
<> 149:156823d33999 89 * @brief Enable DAC data right-aligned.
<> 149:156823d33999 90 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 91 * @return None
<> 149:156823d33999 92 * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
<> 149:156823d33999 93 */
<> 149:156823d33999 94 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
<> 149:156823d33999 95
<> 149:156823d33999 96 /**
<> 149:156823d33999 97 * @brief Enable output voltage buffer.
<> 149:156823d33999 98 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 99 * @return None
<> 149:156823d33999 100 * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
<> 149:156823d33999 101 * drive external loads directly without having to add an external operational amplifier.
<> 149:156823d33999 102 */
<> 149:156823d33999 103 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
<> 149:156823d33999 104
<> 149:156823d33999 105 /**
<> 149:156823d33999 106 * @brief Disable output voltage buffer.
<> 149:156823d33999 107 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 108 * @return None
<> 149:156823d33999 109 * @details This macro is used to disable output voltage buffer.
<> 149:156823d33999 110 */
<> 149:156823d33999 111 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
<> 149:156823d33999 112
<> 149:156823d33999 113 /**
<> 149:156823d33999 114 * @brief Enable the interrupt.
<> 149:156823d33999 115 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 116 * @param[in] u32Ch Not used in M451 Series DAC.
<> 149:156823d33999 117 * @return None
<> 149:156823d33999 118 * @details This macro is used to enable DAC interrupt.
<> 149:156823d33999 119 */
<> 149:156823d33999 120 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
<> 149:156823d33999 121
<> 149:156823d33999 122 /**
<> 149:156823d33999 123 * @brief Disable the interrupt.
<> 149:156823d33999 124 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 125 * @param[in] u32Ch Not used in M451 Series DAC.
<> 149:156823d33999 126 * @return None
<> 149:156823d33999 127 * @details This macro is used to disable DAC interrupt.
<> 149:156823d33999 128 */
<> 149:156823d33999 129 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
<> 149:156823d33999 130
<> 149:156823d33999 131 /**
<> 149:156823d33999 132 * @brief Enable DMA under-run interrupt.
<> 149:156823d33999 133 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 134 * @return None
<> 149:156823d33999 135 * @details This macro is used to enable DMA under-run interrupt.
<> 149:156823d33999 136 */
<> 149:156823d33999 137 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
<> 149:156823d33999 138
<> 149:156823d33999 139 /**
<> 149:156823d33999 140 * @brief Disable DMA under-run interrupt.
<> 149:156823d33999 141 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 142 * @return None
<> 149:156823d33999 143 * @details This macro is used to disable DMA under-run interrupt.
<> 149:156823d33999 144 */
<> 149:156823d33999 145 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
<> 149:156823d33999 146
<> 149:156823d33999 147 /**
<> 149:156823d33999 148 * @brief Enable PDMA mode.
<> 149:156823d33999 149 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 150 * @return None
<> 149:156823d33999 151 * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
<> 149:156823d33999 152 */
<> 149:156823d33999 153 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
<> 149:156823d33999 154
<> 149:156823d33999 155 /**
<> 149:156823d33999 156 * @brief Disable PDMA mode.
<> 149:156823d33999 157 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 158 * @return None
<> 149:156823d33999 159 * @details This macro is used to disable DMA mode.
<> 149:156823d33999 160 */
<> 149:156823d33999 161 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
<> 149:156823d33999 162
<> 149:156823d33999 163 /**
<> 149:156823d33999 164 * @brief Write data for conversion.
<> 149:156823d33999 165 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 166 * @param[in] u32Ch Not used in M451 Series DAC.
<> 149:156823d33999 167 * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
<> 149:156823d33999 168 * @return None
<> 149:156823d33999 169 * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
<> 149:156823d33999 170 * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
<> 149:156823d33999 171 */
<> 149:156823d33999 172 #define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
<> 149:156823d33999 173
<> 149:156823d33999 174 /**
<> 149:156823d33999 175 * @brief Read DAC 12-bit holding data.
<> 149:156823d33999 176 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 177 * @param[in] u32Ch Not used in M451 Series DAC.
<> 149:156823d33999 178 * @return Return DAC 12-bit holding data.
<> 149:156823d33999 179 * @details This macro is used to read DAC_DAT register.
<> 149:156823d33999 180 */
<> 149:156823d33999 181 #define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
<> 149:156823d33999 182
<> 149:156823d33999 183 /**
<> 149:156823d33999 184 * @brief Get the busy state of DAC.
<> 149:156823d33999 185 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 186 * @param[in] u32Ch Not used in M451 Series DAC.
<> 149:156823d33999 187 * @retval 0 Idle state.
<> 149:156823d33999 188 * @retval 1 Busy state.
<> 149:156823d33999 189 * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
<> 149:156823d33999 190 */
<> 149:156823d33999 191 #define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
<> 149:156823d33999 192
<> 149:156823d33999 193 /**
<> 149:156823d33999 194 * @brief Get the interrupt flag.
<> 149:156823d33999 195 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 196 * @param[in] u32Ch Not used in M451 Series DAC.
<> 149:156823d33999 197 * @retval 0 DAC is in conversion state.
<> 149:156823d33999 198 * @retval 1 DAC conversion finish.
<> 149:156823d33999 199 * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
<> 149:156823d33999 200 */
<> 149:156823d33999 201 #define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
<> 149:156823d33999 202
<> 149:156823d33999 203 /**
<> 149:156823d33999 204 * @brief Get the DMA under-run flag.
<> 149:156823d33999 205 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 206 * @retval 0 No DMA under-run error condition occurred.
<> 149:156823d33999 207 * @retval 1 DMA under-run error condition occurred.
<> 149:156823d33999 208 * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
<> 149:156823d33999 209 */
<> 149:156823d33999 210 #define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
<> 149:156823d33999 211
<> 149:156823d33999 212 /**
<> 149:156823d33999 213 * @brief This macro clear the interrupt status bit.
<> 149:156823d33999 214 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 215 * @param[in] u32Ch Not used in M451 Series DAC.
<> 149:156823d33999 216 * @return None
<> 149:156823d33999 217 * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
<> 149:156823d33999 218 */
<> 149:156823d33999 219 #define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
<> 149:156823d33999 220
<> 149:156823d33999 221 /**
<> 149:156823d33999 222 * @brief This macro clear the DMA under-run flag.
<> 149:156823d33999 223 * @param[in] dac Base address of DAC module.
<> 149:156823d33999 224 * @return None
<> 149:156823d33999 225 * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
<> 149:156823d33999 226 */
<> 149:156823d33999 227 #define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
<> 149:156823d33999 228
<> 149:156823d33999 229 void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
<> 149:156823d33999 230 void DAC_Close(DAC_T *dac, uint32_t u32Ch);
<> 149:156823d33999 231 float DAC_SetDelayTime(DAC_T *dac, uint32_t u16Delay);
<> 149:156823d33999 232
<> 149:156823d33999 233 /*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
<> 149:156823d33999 234
<> 149:156823d33999 235 /*@}*/ /* end of group DAC_Driver */
<> 149:156823d33999 236
<> 149:156823d33999 237 /*@}*/ /* end of group Standard_Driver */
<> 149:156823d33999 238
<> 149:156823d33999 239 #ifdef __cplusplus
<> 149:156823d33999 240 }
<> 149:156823d33999 241 #endif
<> 149:156823d33999 242
<> 149:156823d33999 243 #endif //__DAC_H__
<> 149:156823d33999 244
<> 149:156823d33999 245 /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/