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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_sys_on.h@174:ed647f63e28d, 2017-12-19 (annotated)
- Committer:
- Dollyparton
- Date:
- Tue Dec 19 12:50:13 2017 +0000
- Revision:
- 174:ed647f63e28d
- Parent:
- 167:e84263d55307
Added RAW socket.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 167:e84263d55307 | 1 | /******************************************************************************* |
| AnnaBridge | 167:e84263d55307 | 2 | *Copyright (c) 2013-2016 Realtek Semiconductor Corp, All Rights Reserved |
| AnnaBridge | 167:e84263d55307 | 3 | * SPDX-License-Identifier: LicenseRef-PBL |
| AnnaBridge | 167:e84263d55307 | 4 | * |
| AnnaBridge | 167:e84263d55307 | 5 | * Licensed under the Permissive Binary License, Version 1.0 (the "License"); |
| AnnaBridge | 167:e84263d55307 | 6 | * you may not use this file except in compliance with the License. |
| AnnaBridge | 167:e84263d55307 | 7 | * |
| AnnaBridge | 167:e84263d55307 | 8 | * You may obtain a copy of the License at https://www.mbed.com/licenses/PBL-1.0 |
| AnnaBridge | 167:e84263d55307 | 9 | * |
| AnnaBridge | 167:e84263d55307 | 10 | * See the License for the specific language governing permissions and limitations under the License. |
| AnnaBridge | 167:e84263d55307 | 11 | ******************************************************************************* |
| AnnaBridge | 167:e84263d55307 | 12 | */ |
| AnnaBridge | 167:e84263d55307 | 13 | #ifndef __INC_RTL8195A_SYS_ON_BIT_H |
| AnnaBridge | 167:e84263d55307 | 14 | #define __INC_RTL8195A_SYS_ON_BIT_H |
| AnnaBridge | 167:e84263d55307 | 15 | |
| AnnaBridge | 167:e84263d55307 | 16 | #define CPU_OPT_WIDTH 0x1F |
| AnnaBridge | 167:e84263d55307 | 17 | |
| AnnaBridge | 167:e84263d55307 | 18 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 19 | |
| AnnaBridge | 167:e84263d55307 | 20 | //2 REG_SYS_PWR_CTRL |
| AnnaBridge | 167:e84263d55307 | 21 | |
| AnnaBridge | 167:e84263d55307 | 22 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 23 | |
| AnnaBridge | 167:e84263d55307 | 24 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 25 | |
| AnnaBridge | 167:e84263d55307 | 26 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 27 | |
| AnnaBridge | 167:e84263d55307 | 28 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 29 | |
| AnnaBridge | 167:e84263d55307 | 30 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 31 | |
| AnnaBridge | 167:e84263d55307 | 32 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 33 | |
| AnnaBridge | 167:e84263d55307 | 34 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 35 | |
| AnnaBridge | 167:e84263d55307 | 36 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 37 | |
| AnnaBridge | 167:e84263d55307 | 38 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 39 | |
| AnnaBridge | 167:e84263d55307 | 40 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 41 | |
| AnnaBridge | 167:e84263d55307 | 42 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 43 | |
| AnnaBridge | 167:e84263d55307 | 44 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 45 | |
| AnnaBridge | 167:e84263d55307 | 46 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 47 | #define BIT_SYS_PWR_SOC_EN BIT(2) |
| AnnaBridge | 167:e84263d55307 | 48 | #define BIT_SYS_PWR_RET_MEM_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 49 | #define BIT_SYS_PWR_PEON_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 50 | |
| AnnaBridge | 167:e84263d55307 | 51 | //2 REG_SYS_ISO_CTRL |
| AnnaBridge | 167:e84263d55307 | 52 | |
| AnnaBridge | 167:e84263d55307 | 53 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 54 | |
| AnnaBridge | 167:e84263d55307 | 55 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 56 | |
| AnnaBridge | 167:e84263d55307 | 57 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 58 | |
| AnnaBridge | 167:e84263d55307 | 59 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 60 | |
| AnnaBridge | 167:e84263d55307 | 61 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 62 | |
| AnnaBridge | 167:e84263d55307 | 63 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 64 | |
| AnnaBridge | 167:e84263d55307 | 65 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 66 | |
| AnnaBridge | 167:e84263d55307 | 67 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 68 | #define BIT_SYS_ISO_SYSPLL BIT(7) |
| AnnaBridge | 167:e84263d55307 | 69 | |
| AnnaBridge | 167:e84263d55307 | 70 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 71 | |
| AnnaBridge | 167:e84263d55307 | 72 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 73 | |
| AnnaBridge | 167:e84263d55307 | 74 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 75 | |
| AnnaBridge | 167:e84263d55307 | 76 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 77 | #define BIT_SYS_ISO_SOC BIT(2) |
| AnnaBridge | 167:e84263d55307 | 78 | #define BIT_SYS_ISO_RET_MEM BIT(1) |
| AnnaBridge | 167:e84263d55307 | 79 | #define BIT_SYS_ISO_PEON BIT(0) |
| AnnaBridge | 167:e84263d55307 | 80 | |
| AnnaBridge | 167:e84263d55307 | 81 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 82 | |
| AnnaBridge | 167:e84263d55307 | 83 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 84 | |
| AnnaBridge | 167:e84263d55307 | 85 | //2 REG_SYS_FUNC_EN |
| AnnaBridge | 167:e84263d55307 | 86 | #define BIT_SYS_AMACRO_EN BIT(31) |
| AnnaBridge | 167:e84263d55307 | 87 | #define BIT_SYS_PWRON_TRAP_SHTDN_N BIT(30) |
| AnnaBridge | 167:e84263d55307 | 88 | #define BIT_SYS_FEN_SIC_MST BIT(25) |
| AnnaBridge | 167:e84263d55307 | 89 | #define BIT_SYS_FEN_SIC BIT(24) |
| AnnaBridge | 167:e84263d55307 | 90 | |
| AnnaBridge | 167:e84263d55307 | 91 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 92 | |
| AnnaBridge | 167:e84263d55307 | 93 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 94 | |
| AnnaBridge | 167:e84263d55307 | 95 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 96 | |
| AnnaBridge | 167:e84263d55307 | 97 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 98 | |
| AnnaBridge | 167:e84263d55307 | 99 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 100 | |
| AnnaBridge | 167:e84263d55307 | 101 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 102 | |
| AnnaBridge | 167:e84263d55307 | 103 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 104 | |
| AnnaBridge | 167:e84263d55307 | 105 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 106 | #define BIT_SOC_SYSPEON_EN BIT(4) |
| AnnaBridge | 167:e84263d55307 | 107 | |
| AnnaBridge | 167:e84263d55307 | 108 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 109 | |
| AnnaBridge | 167:e84263d55307 | 110 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 111 | |
| AnnaBridge | 167:e84263d55307 | 112 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 113 | #define BIT_SYS_FEN_EELDR BIT(0) |
| AnnaBridge | 167:e84263d55307 | 114 | |
| AnnaBridge | 167:e84263d55307 | 115 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 116 | |
| AnnaBridge | 167:e84263d55307 | 117 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 118 | |
| AnnaBridge | 167:e84263d55307 | 119 | //2 REG_SYS_CLK_CTRL0 |
| AnnaBridge | 167:e84263d55307 | 120 | |
| AnnaBridge | 167:e84263d55307 | 121 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 122 | #define BIT_SOC_OCP_IOBUS_CK_EN BIT(2) |
| AnnaBridge | 167:e84263d55307 | 123 | #define BIT_SYSON_CK_EELDR_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 124 | #define BIT_SYSON_CK_SYSREG_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 125 | |
| AnnaBridge | 167:e84263d55307 | 126 | //2 REG_SYS_CLK_CTRL1 |
| AnnaBridge | 167:e84263d55307 | 127 | |
| AnnaBridge | 167:e84263d55307 | 128 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 129 | |
| AnnaBridge | 167:e84263d55307 | 130 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 131 | |
| AnnaBridge | 167:e84263d55307 | 132 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 133 | |
| AnnaBridge | 167:e84263d55307 | 134 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 135 | |
| AnnaBridge | 167:e84263d55307 | 136 | #define BIT_SHIFT_PESOC_OCP_CPU_CK_SEL 4 |
| AnnaBridge | 167:e84263d55307 | 137 | #define BIT_MASK_PESOC_OCP_CPU_CK_SEL 0x7 |
| AnnaBridge | 167:e84263d55307 | 138 | #define BIT_PESOC_OCP_CPU_CK_SEL(x) (((x) & BIT_MASK_PESOC_OCP_CPU_CK_SEL) << BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) |
| AnnaBridge | 167:e84263d55307 | 139 | |
| AnnaBridge | 167:e84263d55307 | 140 | |
| AnnaBridge | 167:e84263d55307 | 141 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 142 | #define BIT_PESOC_EELDR_CK_SEL BIT(0) |
| AnnaBridge | 167:e84263d55307 | 143 | |
| AnnaBridge | 167:e84263d55307 | 144 | //2 REG_SYS_SWR_CTRL3 |
| AnnaBridge | 167:e84263d55307 | 145 | |
| AnnaBridge | 167:e84263d55307 | 146 | //2 REG_RSV_CTRL |
| AnnaBridge | 167:e84263d55307 | 147 | |
| AnnaBridge | 167:e84263d55307 | 148 | //2 REG_RF_CTRL |
| AnnaBridge | 167:e84263d55307 | 149 | |
| AnnaBridge | 167:e84263d55307 | 150 | //2 REG_SYS_EFUSE_SYSCFG0 |
| AnnaBridge | 167:e84263d55307 | 151 | |
| AnnaBridge | 167:e84263d55307 | 152 | #define BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00 24 |
| AnnaBridge | 167:e84263d55307 | 153 | #define BIT_MASK_SYS_EEROM_SWR_PAR_05_00 0x3f |
| AnnaBridge | 167:e84263d55307 | 154 | #define BIT_SYS_EEROM_SWR_PAR_05_00(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_05_00) << BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00) |
| AnnaBridge | 167:e84263d55307 | 155 | |
| AnnaBridge | 167:e84263d55307 | 156 | |
| AnnaBridge | 167:e84263d55307 | 157 | #define BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04 20 |
| AnnaBridge | 167:e84263d55307 | 158 | #define BIT_MASK_SYS_EEROM_LDO_PAR_07_04 0xf |
| AnnaBridge | 167:e84263d55307 | 159 | #define BIT_SYS_EEROM_LDO_PAR_07_04(x) (((x) & BIT_MASK_SYS_EEROM_LDO_PAR_07_04) << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04) |
| AnnaBridge | 167:e84263d55307 | 160 | |
| AnnaBridge | 167:e84263d55307 | 161 | #define BIT_SYS_CHIPPDN_EN BIT(17) |
| AnnaBridge | 167:e84263d55307 | 162 | #define BIT_SYS_EEROM_B12V_EN BIT(16) |
| AnnaBridge | 167:e84263d55307 | 163 | |
| AnnaBridge | 167:e84263d55307 | 164 | #define BIT_SHIFT_SYS_EEROM_VID1 8 |
| AnnaBridge | 167:e84263d55307 | 165 | #define BIT_MASK_SYS_EEROM_VID1 0xff |
| AnnaBridge | 167:e84263d55307 | 166 | #define BIT_SYS_EEROM_VID1(x) (((x) & BIT_MASK_SYS_EEROM_VID1) << BIT_SHIFT_SYS_EEROM_VID1) |
| AnnaBridge | 167:e84263d55307 | 167 | |
| AnnaBridge | 167:e84263d55307 | 168 | |
| AnnaBridge | 167:e84263d55307 | 169 | #define BIT_SHIFT_SYS_EEROM_VID0 0 |
| AnnaBridge | 167:e84263d55307 | 170 | #define BIT_MASK_SYS_EEROM_VID0 0xff |
| AnnaBridge | 167:e84263d55307 | 171 | #define BIT_SYS_EEROM_VID0(x) (((x) & BIT_MASK_SYS_EEROM_VID0) << BIT_SHIFT_SYS_EEROM_VID0) |
| AnnaBridge | 167:e84263d55307 | 172 | |
| AnnaBridge | 167:e84263d55307 | 173 | |
| AnnaBridge | 167:e84263d55307 | 174 | //2 REG_SYS_EFUSE_SYSCFG1 |
| AnnaBridge | 167:e84263d55307 | 175 | |
| AnnaBridge | 167:e84263d55307 | 176 | #define BIT_SHIFT_SYS_PDSPL_STL 24 |
| AnnaBridge | 167:e84263d55307 | 177 | #define BIT_MASK_SYS_PDSPL_STL 0x3 |
| AnnaBridge | 167:e84263d55307 | 178 | #define BIT_SYS_PDSPL_STL(x) (((x) & BIT_MASK_SYS_PDSPL_STL) << BIT_SHIFT_SYS_PDSPL_STL) |
| AnnaBridge | 167:e84263d55307 | 179 | |
| AnnaBridge | 167:e84263d55307 | 180 | |
| AnnaBridge | 167:e84263d55307 | 181 | #define BIT_SHIFT_SYS_PDSOC_STL 22 |
| AnnaBridge | 167:e84263d55307 | 182 | #define BIT_MASK_SYS_PDSOC_STL 0x3 |
| AnnaBridge | 167:e84263d55307 | 183 | #define BIT_SYS_PDSOC_STL(x) (((x) & BIT_MASK_SYS_PDSOC_STL) << BIT_SHIFT_SYS_PDSOC_STL) |
| AnnaBridge | 167:e84263d55307 | 184 | |
| AnnaBridge | 167:e84263d55307 | 185 | |
| AnnaBridge | 167:e84263d55307 | 186 | #define BIT_SHIFT_SYS_PDPON_STL 20 |
| AnnaBridge | 167:e84263d55307 | 187 | #define BIT_MASK_SYS_PDPON_STL 0x3 |
| AnnaBridge | 167:e84263d55307 | 188 | #define BIT_SYS_PDPON_STL(x) (((x) & BIT_MASK_SYS_PDPON_STL) << BIT_SHIFT_SYS_PDPON_STL) |
| AnnaBridge | 167:e84263d55307 | 189 | |
| AnnaBridge | 167:e84263d55307 | 190 | |
| AnnaBridge | 167:e84263d55307 | 191 | #define BIT_SHIFT_SYS_SWREG_XRT 18 |
| AnnaBridge | 167:e84263d55307 | 192 | #define BIT_MASK_SYS_SWREG_XRT 0x3 |
| AnnaBridge | 167:e84263d55307 | 193 | #define BIT_SYS_SWREG_XRT(x) (((x) & BIT_MASK_SYS_SWREG_XRT) << BIT_SHIFT_SYS_SWREG_XRT) |
| AnnaBridge | 167:e84263d55307 | 194 | |
| AnnaBridge | 167:e84263d55307 | 195 | |
| AnnaBridge | 167:e84263d55307 | 196 | #define BIT_SHIFT_SYS_SWSLC_STL 16 |
| AnnaBridge | 167:e84263d55307 | 197 | #define BIT_MASK_SYS_SWSLC_STL 0x3 |
| AnnaBridge | 167:e84263d55307 | 198 | #define BIT_SYS_SWSLC_STL(x) (((x) & BIT_MASK_SYS_SWSLC_STL) << BIT_SHIFT_SYS_SWSLC_STL) |
| AnnaBridge | 167:e84263d55307 | 199 | |
| AnnaBridge | 167:e84263d55307 | 200 | |
| AnnaBridge | 167:e84263d55307 | 201 | #define BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45 14 |
| AnnaBridge | 167:e84263d55307 | 202 | #define BIT_MASK_SYS_EEROM_SWR_PAR_46_45 0x3 |
| AnnaBridge | 167:e84263d55307 | 203 | #define BIT_SYS_EEROM_SWR_PAR_46_45(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_46_45) << BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45) |
| AnnaBridge | 167:e84263d55307 | 204 | |
| AnnaBridge | 167:e84263d55307 | 205 | |
| AnnaBridge | 167:e84263d55307 | 206 | #define BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39 12 |
| AnnaBridge | 167:e84263d55307 | 207 | #define BIT_MASK_SYS_EEROM_SWR_PAR_40_39 0x3 |
| AnnaBridge | 167:e84263d55307 | 208 | #define BIT_SYS_EEROM_SWR_PAR_40_39(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_40_39) << BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39) |
| AnnaBridge | 167:e84263d55307 | 209 | |
| AnnaBridge | 167:e84263d55307 | 210 | |
| AnnaBridge | 167:e84263d55307 | 211 | #define BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26 4 |
| AnnaBridge | 167:e84263d55307 | 212 | #define BIT_MASK_SYS_EEROM_SWR_PAR_33_26 0xff |
| AnnaBridge | 167:e84263d55307 | 213 | #define BIT_SYS_EEROM_SWR_PAR_33_26(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_33_26) << BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26) |
| AnnaBridge | 167:e84263d55307 | 214 | |
| AnnaBridge | 167:e84263d55307 | 215 | |
| AnnaBridge | 167:e84263d55307 | 216 | #define BIT_SHIFT_SYS_EEROM_SWSLD_VOL 0 |
| AnnaBridge | 167:e84263d55307 | 217 | #define BIT_MASK_SYS_EEROM_SWSLD_VOL 0x7 |
| AnnaBridge | 167:e84263d55307 | 218 | #define BIT_SYS_EEROM_SWSLD_VOL(x) (((x) & BIT_MASK_SYS_EEROM_SWSLD_VOL) << BIT_SHIFT_SYS_EEROM_SWSLD_VOL) |
| AnnaBridge | 167:e84263d55307 | 219 | |
| AnnaBridge | 167:e84263d55307 | 220 | |
| AnnaBridge | 167:e84263d55307 | 221 | //2 REG_SYS_EFUSE_SYSCFG2 |
| AnnaBridge | 167:e84263d55307 | 222 | |
| AnnaBridge | 167:e84263d55307 | 223 | #define BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15 21 |
| AnnaBridge | 167:e84263d55307 | 224 | #define BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15 0x3ff |
| AnnaBridge | 167:e84263d55307 | 225 | #define BIT_SYS_EERROM_ANAPAR_SPLL_24_15(x) (((x) & BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15) << BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15) |
| AnnaBridge | 167:e84263d55307 | 226 | |
| AnnaBridge | 167:e84263d55307 | 227 | |
| AnnaBridge | 167:e84263d55307 | 228 | #define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02 16 |
| AnnaBridge | 167:e84263d55307 | 229 | #define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02 0xf |
| AnnaBridge | 167:e84263d55307 | 230 | #define BIT_SYS_EEROM_ANAPAR_SPLL_05_02(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02) |
| AnnaBridge | 167:e84263d55307 | 231 | |
| AnnaBridge | 167:e84263d55307 | 232 | |
| AnnaBridge | 167:e84263d55307 | 233 | #define BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL 12 |
| AnnaBridge | 167:e84263d55307 | 234 | #define BIT_MASK_SYS_EEROM_XTAL_STEL_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 235 | #define BIT_SYS_EEROM_XTAL_STEL_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_STEL_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL) |
| AnnaBridge | 167:e84263d55307 | 236 | |
| AnnaBridge | 167:e84263d55307 | 237 | |
| AnnaBridge | 167:e84263d55307 | 238 | #define BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL 8 |
| AnnaBridge | 167:e84263d55307 | 239 | #define BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL 0xf |
| AnnaBridge | 167:e84263d55307 | 240 | #define BIT_SYS_EEROM_XTAL_FREQ_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL) |
| AnnaBridge | 167:e84263d55307 | 241 | |
| AnnaBridge | 167:e84263d55307 | 242 | |
| AnnaBridge | 167:e84263d55307 | 243 | //2 REG_SYS_EFUSE_SYSCFG3 |
| AnnaBridge | 167:e84263d55307 | 244 | |
| AnnaBridge | 167:e84263d55307 | 245 | #define BIT_SHIFT_SYS_DBG_PINGP_EN 28 |
| AnnaBridge | 167:e84263d55307 | 246 | #define BIT_MASK_SYS_DBG_PINGP_EN 0xf |
| AnnaBridge | 167:e84263d55307 | 247 | #define BIT_SYS_DBG_PINGP_EN(x) (((x) & BIT_MASK_SYS_DBG_PINGP_EN) << BIT_SHIFT_SYS_DBG_PINGP_EN) |
| AnnaBridge | 167:e84263d55307 | 248 | |
| AnnaBridge | 167:e84263d55307 | 249 | |
| AnnaBridge | 167:e84263d55307 | 250 | #define BIT_SHIFT_SYS_DBG_SEL 16 |
| AnnaBridge | 167:e84263d55307 | 251 | #define BIT_MASK_SYS_DBG_SEL 0xfff |
| AnnaBridge | 167:e84263d55307 | 252 | #define BIT_SYS_DBG_SEL(x) (((x) & BIT_MASK_SYS_DBG_SEL) << BIT_SHIFT_SYS_DBG_SEL) |
| AnnaBridge | 167:e84263d55307 | 253 | |
| AnnaBridge | 167:e84263d55307 | 254 | |
| AnnaBridge | 167:e84263d55307 | 255 | #define BIT_SHIFT_SYS_DBGBY3_LOC_SEL 14 |
| AnnaBridge | 167:e84263d55307 | 256 | #define BIT_MASK_SYS_DBGBY3_LOC_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 257 | #define BIT_SYS_DBGBY3_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY3_LOC_SEL) << BIT_SHIFT_SYS_DBGBY3_LOC_SEL) |
| AnnaBridge | 167:e84263d55307 | 258 | |
| AnnaBridge | 167:e84263d55307 | 259 | |
| AnnaBridge | 167:e84263d55307 | 260 | #define BIT_SHIFT_SYS_DBGBY2_LOC_SEL 12 |
| AnnaBridge | 167:e84263d55307 | 261 | #define BIT_MASK_SYS_DBGBY2_LOC_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 262 | #define BIT_SYS_DBGBY2_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY2_LOC_SEL) << BIT_SHIFT_SYS_DBGBY2_LOC_SEL) |
| AnnaBridge | 167:e84263d55307 | 263 | |
| AnnaBridge | 167:e84263d55307 | 264 | |
| AnnaBridge | 167:e84263d55307 | 265 | #define BIT_SHIFT_SYS_DBGBY1_LOC_SEL 10 |
| AnnaBridge | 167:e84263d55307 | 266 | #define BIT_MASK_SYS_DBGBY1_LOC_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 267 | #define BIT_SYS_DBGBY1_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY1_LOC_SEL) << BIT_SHIFT_SYS_DBGBY1_LOC_SEL) |
| AnnaBridge | 167:e84263d55307 | 268 | |
| AnnaBridge | 167:e84263d55307 | 269 | |
| AnnaBridge | 167:e84263d55307 | 270 | #define BIT_SHIFT_SYS_DBGBY0_LOC_SEL 8 |
| AnnaBridge | 167:e84263d55307 | 271 | #define BIT_MASK_SYS_DBGBY0_LOC_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 272 | #define BIT_SYS_DBGBY0_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY0_LOC_SEL) << BIT_SHIFT_SYS_DBGBY0_LOC_SEL) |
| AnnaBridge | 167:e84263d55307 | 273 | |
| AnnaBridge | 167:e84263d55307 | 274 | #define BIT_SYS_EEROM_ANAPAR_SPLL_49 BIT(3) |
| AnnaBridge | 167:e84263d55307 | 275 | |
| AnnaBridge | 167:e84263d55307 | 276 | #define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25 0 |
| AnnaBridge | 167:e84263d55307 | 277 | #define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25 0x7 |
| AnnaBridge | 167:e84263d55307 | 278 | #define BIT_SYS_EEROM_ANAPAR_SPLL_27_25(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25) |
| AnnaBridge | 167:e84263d55307 | 279 | |
| AnnaBridge | 167:e84263d55307 | 280 | |
| AnnaBridge | 167:e84263d55307 | 281 | //2 REG_SYS_EFUSE_SYSCFG4 |
| AnnaBridge | 167:e84263d55307 | 282 | |
| AnnaBridge | 167:e84263d55307 | 283 | #define BIT_SHIFT_SYS_GPIOA_E2 1 |
| AnnaBridge | 167:e84263d55307 | 284 | #define BIT_MASK_SYS_GPIOA_E2 0x7 |
| AnnaBridge | 167:e84263d55307 | 285 | #define BIT_SYS_GPIOA_E2(x) (((x) & BIT_MASK_SYS_GPIOA_E2) << BIT_SHIFT_SYS_GPIOA_E2) |
| AnnaBridge | 167:e84263d55307 | 286 | |
| AnnaBridge | 167:e84263d55307 | 287 | #define BIT_SYS_GPIOA_H3L1 BIT(0) |
| AnnaBridge | 167:e84263d55307 | 288 | |
| AnnaBridge | 167:e84263d55307 | 289 | //2 REG_SYS_EFUSE_SYSCFG5 |
| AnnaBridge | 167:e84263d55307 | 290 | |
| AnnaBridge | 167:e84263d55307 | 291 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 292 | |
| AnnaBridge | 167:e84263d55307 | 293 | //2 REG_SYS_EFUSE_SYSCFG6 |
| AnnaBridge | 167:e84263d55307 | 294 | |
| AnnaBridge | 167:e84263d55307 | 295 | #define BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL 26 |
| AnnaBridge | 167:e84263d55307 | 296 | #define BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 297 | #define BIT_SYS_SPIC_INIT_BAUD_RATE_SEL(x) (((x) & BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL) << BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL) |
| AnnaBridge | 167:e84263d55307 | 298 | |
| AnnaBridge | 167:e84263d55307 | 299 | |
| AnnaBridge | 167:e84263d55307 | 300 | #define BIT_SHIFT_SYS_CPU_CLK_SEL 24 |
| AnnaBridge | 167:e84263d55307 | 301 | #define BIT_MASK_SYS_CPU_CLK_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 302 | #define BIT_SYS_CPU_CLK_SEL(x) (((x) & BIT_MASK_SYS_CPU_CLK_SEL) << BIT_SHIFT_SYS_CPU_CLK_SEL) |
| AnnaBridge | 167:e84263d55307 | 303 | |
| AnnaBridge | 167:e84263d55307 | 304 | |
| AnnaBridge | 167:e84263d55307 | 305 | //2 REG_SYS_EFUSE_SYSCFG7 |
| AnnaBridge | 167:e84263d55307 | 306 | #define BIT_SYS_MEM_RMV_SIGN BIT(31) |
| AnnaBridge | 167:e84263d55307 | 307 | #define BIT_SYS_MEM_RMV_1PRF1 BIT(29) |
| AnnaBridge | 167:e84263d55307 | 308 | #define BIT_SYS_MEM_RMV_1PRF0 BIT(28) |
| AnnaBridge | 167:e84263d55307 | 309 | #define BIT_SYS_MEM_RMV_1PSR BIT(27) |
| AnnaBridge | 167:e84263d55307 | 310 | #define BIT_SYS_MEM_RMV_1PHSR BIT(26) |
| AnnaBridge | 167:e84263d55307 | 311 | #define BIT_SYS_MEM_RMV_ROM BIT(25) |
| AnnaBridge | 167:e84263d55307 | 312 | |
| AnnaBridge | 167:e84263d55307 | 313 | #define BIT_SHIFT_SYS_MEM_RME_CPU 22 |
| AnnaBridge | 167:e84263d55307 | 314 | #define BIT_MASK_SYS_MEM_RME_CPU 0x7 |
| AnnaBridge | 167:e84263d55307 | 315 | #define BIT_SYS_MEM_RME_CPU(x) (((x) & BIT_MASK_SYS_MEM_RME_CPU) << BIT_SHIFT_SYS_MEM_RME_CPU) |
| AnnaBridge | 167:e84263d55307 | 316 | |
| AnnaBridge | 167:e84263d55307 | 317 | |
| AnnaBridge | 167:e84263d55307 | 318 | #define BIT_SHIFT_SYS_MEM_RME_WLAN 19 |
| AnnaBridge | 167:e84263d55307 | 319 | #define BIT_MASK_SYS_MEM_RME_WLAN 0x7 |
| AnnaBridge | 167:e84263d55307 | 320 | #define BIT_SYS_MEM_RME_WLAN(x) (((x) & BIT_MASK_SYS_MEM_RME_WLAN) << BIT_SHIFT_SYS_MEM_RME_WLAN) |
| AnnaBridge | 167:e84263d55307 | 321 | |
| AnnaBridge | 167:e84263d55307 | 322 | #define BIT_SYS_MEM_RME_USB BIT(18) |
| AnnaBridge | 167:e84263d55307 | 323 | #define BIT_SYS_MEM_RME_SDIO BIT(17) |
| AnnaBridge | 167:e84263d55307 | 324 | |
| AnnaBridge | 167:e84263d55307 | 325 | //2 REG_SYS_REGU_CTRL0 |
| AnnaBridge | 167:e84263d55307 | 326 | |
| AnnaBridge | 167:e84263d55307 | 327 | #define BIT_SHIFT_SYS_REGU_LDO25M_ADJ 20 |
| AnnaBridge | 167:e84263d55307 | 328 | #define BIT_MASK_SYS_REGU_LDO25M_ADJ 0xf |
| AnnaBridge | 167:e84263d55307 | 329 | #define BIT_SYS_REGU_LDO25M_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25M_ADJ) << BIT_SHIFT_SYS_REGU_LDO25M_ADJ) |
| AnnaBridge | 167:e84263d55307 | 330 | |
| AnnaBridge | 167:e84263d55307 | 331 | #define BIT_SYS_REGU_ANACK_4M_EN BIT(19) |
| AnnaBridge | 167:e84263d55307 | 332 | #define BIT_SYS_REGU_ANACK_4M_SEL BIT(18) |
| AnnaBridge | 167:e84263d55307 | 333 | #define BIT_SYS_REGU_PC_EF_EN BIT(17) |
| AnnaBridge | 167:e84263d55307 | 334 | #define BIT_SYS_REGU_LDOH12_SLP_EN BIT(16) |
| AnnaBridge | 167:e84263d55307 | 335 | |
| AnnaBridge | 167:e84263d55307 | 336 | #define BIT_SHIFT_SYS_REGU_LDOH12_ADJ 12 |
| AnnaBridge | 167:e84263d55307 | 337 | #define BIT_MASK_SYS_REGU_LDOH12_ADJ 0xf |
| AnnaBridge | 167:e84263d55307 | 338 | #define BIT_SYS_REGU_LDOH12_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDOH12_ADJ) << BIT_SHIFT_SYS_REGU_LDOH12_ADJ) |
| AnnaBridge | 167:e84263d55307 | 339 | |
| AnnaBridge | 167:e84263d55307 | 340 | |
| AnnaBridge | 167:e84263d55307 | 341 | #define BIT_SHIFT_SYS_REGU_LDO25E_ADJ 8 |
| AnnaBridge | 167:e84263d55307 | 342 | #define BIT_MASK_SYS_REGU_LDO25E_ADJ 0xf |
| AnnaBridge | 167:e84263d55307 | 343 | #define BIT_SYS_REGU_LDO25E_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25E_ADJ) << BIT_SHIFT_SYS_REGU_LDO25E_ADJ) |
| AnnaBridge | 167:e84263d55307 | 344 | |
| AnnaBridge | 167:e84263d55307 | 345 | #define BIT_SYS_REGU_DSLEPM_EN BIT(7) |
| AnnaBridge | 167:e84263d55307 | 346 | #define BIT_SYS_REGU_PC_33V_EN BIT(3) |
| AnnaBridge | 167:e84263d55307 | 347 | #define BIT_SYS_REGU_PC_EF25_EN BIT(2) |
| AnnaBridge | 167:e84263d55307 | 348 | #define BIT_SYS_REGU_LDO25M_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 349 | #define BIT_SYS_REGU_LDO25E_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 350 | |
| AnnaBridge | 167:e84263d55307 | 351 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 352 | |
| AnnaBridge | 167:e84263d55307 | 353 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 354 | |
| AnnaBridge | 167:e84263d55307 | 355 | //2 REG_SYS_SWR_CTRL0 |
| AnnaBridge | 167:e84263d55307 | 356 | |
| AnnaBridge | 167:e84263d55307 | 357 | #define BIT_SHIFT_SYS_SWR12_COMP_R2 30 |
| AnnaBridge | 167:e84263d55307 | 358 | #define BIT_MASK_SYS_SWR12_COMP_R2 0x3 |
| AnnaBridge | 167:e84263d55307 | 359 | #define BIT_SYS_SWR12_COMP_R2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R2) << BIT_SHIFT_SYS_SWR12_COMP_R2) |
| AnnaBridge | 167:e84263d55307 | 360 | |
| AnnaBridge | 167:e84263d55307 | 361 | |
| AnnaBridge | 167:e84263d55307 | 362 | #define BIT_SHIFT_SYS_SWR12_COMP_R1 28 |
| AnnaBridge | 167:e84263d55307 | 363 | #define BIT_MASK_SYS_SWR12_COMP_R1 0x3 |
| AnnaBridge | 167:e84263d55307 | 364 | #define BIT_SYS_SWR12_COMP_R1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R1) << BIT_SHIFT_SYS_SWR12_COMP_R1) |
| AnnaBridge | 167:e84263d55307 | 365 | |
| AnnaBridge | 167:e84263d55307 | 366 | |
| AnnaBridge | 167:e84263d55307 | 367 | #define BIT_SHIFT_SYS_SWR12_COMP_C3 26 |
| AnnaBridge | 167:e84263d55307 | 368 | #define BIT_MASK_SYS_SWR12_COMP_C3 0x3 |
| AnnaBridge | 167:e84263d55307 | 369 | #define BIT_SYS_SWR12_COMP_C3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C3) << BIT_SHIFT_SYS_SWR12_COMP_C3) |
| AnnaBridge | 167:e84263d55307 | 370 | |
| AnnaBridge | 167:e84263d55307 | 371 | |
| AnnaBridge | 167:e84263d55307 | 372 | #define BIT_SHIFT_SYS_SWR12_COMP_C2 24 |
| AnnaBridge | 167:e84263d55307 | 373 | #define BIT_MASK_SYS_SWR12_COMP_C2 0x3 |
| AnnaBridge | 167:e84263d55307 | 374 | #define BIT_SYS_SWR12_COMP_C2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C2) << BIT_SHIFT_SYS_SWR12_COMP_C2) |
| AnnaBridge | 167:e84263d55307 | 375 | |
| AnnaBridge | 167:e84263d55307 | 376 | |
| AnnaBridge | 167:e84263d55307 | 377 | #define BIT_SHIFT_SYS_SWR12_COMP_C1 22 |
| AnnaBridge | 167:e84263d55307 | 378 | #define BIT_MASK_SYS_SWR12_COMP_C1 0x3 |
| AnnaBridge | 167:e84263d55307 | 379 | #define BIT_SYS_SWR12_COMP_C1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C1) << BIT_SHIFT_SYS_SWR12_COMP_C1) |
| AnnaBridge | 167:e84263d55307 | 380 | |
| AnnaBridge | 167:e84263d55307 | 381 | #define BIT_SYS_SWR12_COMP_TYPE_L BIT(21) |
| AnnaBridge | 167:e84263d55307 | 382 | #define BIT_SYS_SWR12_FPWM_MD BIT(20) |
| AnnaBridge | 167:e84263d55307 | 383 | |
| AnnaBridge | 167:e84263d55307 | 384 | #define BIT_SHIFT_SYS_SPSLDO_VOL 17 |
| AnnaBridge | 167:e84263d55307 | 385 | #define BIT_MASK_SYS_SPSLDO_VOL 0x7 |
| AnnaBridge | 167:e84263d55307 | 386 | #define BIT_SYS_SPSLDO_VOL(x) (((x) & BIT_MASK_SYS_SPSLDO_VOL) << BIT_SHIFT_SYS_SPSLDO_VOL) |
| AnnaBridge | 167:e84263d55307 | 387 | |
| AnnaBridge | 167:e84263d55307 | 388 | |
| AnnaBridge | 167:e84263d55307 | 389 | #define BIT_SHIFT_SYS_SWR12_IN 14 |
| AnnaBridge | 167:e84263d55307 | 390 | #define BIT_MASK_SYS_SWR12_IN 0x7 |
| AnnaBridge | 167:e84263d55307 | 391 | #define BIT_SYS_SWR12_IN(x) (((x) & BIT_MASK_SYS_SWR12_IN) << BIT_SHIFT_SYS_SWR12_IN) |
| AnnaBridge | 167:e84263d55307 | 392 | |
| AnnaBridge | 167:e84263d55307 | 393 | |
| AnnaBridge | 167:e84263d55307 | 394 | #define BIT_SHIFT_SYS_SWR12_STD 12 |
| AnnaBridge | 167:e84263d55307 | 395 | #define BIT_MASK_SYS_SWR12_STD 0x3 |
| AnnaBridge | 167:e84263d55307 | 396 | #define BIT_SYS_SWR12_STD(x) (((x) & BIT_MASK_SYS_SWR12_STD) << BIT_SHIFT_SYS_SWR12_STD) |
| AnnaBridge | 167:e84263d55307 | 397 | |
| AnnaBridge | 167:e84263d55307 | 398 | |
| AnnaBridge | 167:e84263d55307 | 399 | #define BIT_SHIFT_SYS_SWR12_VOL 8 |
| AnnaBridge | 167:e84263d55307 | 400 | #define BIT_MASK_SYS_SWR12_VOL 0xf |
| AnnaBridge | 167:e84263d55307 | 401 | #define BIT_SYS_SWR12_VOL(x) (((x) & BIT_MASK_SYS_SWR12_VOL) << BIT_SHIFT_SYS_SWR12_VOL) |
| AnnaBridge | 167:e84263d55307 | 402 | |
| AnnaBridge | 167:e84263d55307 | 403 | |
| AnnaBridge | 167:e84263d55307 | 404 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 405 | |
| AnnaBridge | 167:e84263d55307 | 406 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 407 | |
| AnnaBridge | 167:e84263d55307 | 408 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 409 | |
| AnnaBridge | 167:e84263d55307 | 410 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 411 | |
| AnnaBridge | 167:e84263d55307 | 412 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 413 | |
| AnnaBridge | 167:e84263d55307 | 414 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 415 | #define BIT_SYS_SWR_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 416 | #define BIT_SYS_SWR_LDO_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 417 | |
| AnnaBridge | 167:e84263d55307 | 418 | //2 REG_SYS_SWR_CTRL1 |
| AnnaBridge | 167:e84263d55307 | 419 | #define BIT_SYS_SW12_PFM_SEL BIT(25) |
| AnnaBridge | 167:e84263d55307 | 420 | #define BIT_SYS_SW12_AUTO_ZCD_L BIT(24) |
| AnnaBridge | 167:e84263d55307 | 421 | #define BIT_SYS_SW12_AUTO_MODE BIT(23) |
| AnnaBridge | 167:e84263d55307 | 422 | #define BIT_SYS_SW12_LDOF_L BIT(22) |
| AnnaBridge | 167:e84263d55307 | 423 | #define BIT_SYS_SW12_OCPS_L BIT(21) |
| AnnaBridge | 167:e84263d55307 | 424 | |
| AnnaBridge | 167:e84263d55307 | 425 | #define BIT_SHIFT_SYS_SW12_TBOX 17 |
| AnnaBridge | 167:e84263d55307 | 426 | #define BIT_MASK_SYS_SW12_TBOX 0x3 |
| AnnaBridge | 167:e84263d55307 | 427 | #define BIT_SYS_SW12_TBOX(x) (((x) & BIT_MASK_SYS_SW12_TBOX) << BIT_SHIFT_SYS_SW12_TBOX) |
| AnnaBridge | 167:e84263d55307 | 428 | |
| AnnaBridge | 167:e84263d55307 | 429 | |
| AnnaBridge | 167:e84263d55307 | 430 | #define BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY 15 |
| AnnaBridge | 167:e84263d55307 | 431 | #define BIT_MASK_SYS_SW12_NONOVRLAP_DLY 0x3 |
| AnnaBridge | 167:e84263d55307 | 432 | #define BIT_SYS_SW12_NONOVRLAP_DLY(x) (((x) & BIT_MASK_SYS_SW12_NONOVRLAP_DLY) << BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY) |
| AnnaBridge | 167:e84263d55307 | 433 | |
| AnnaBridge | 167:e84263d55307 | 434 | #define BIT_SYS_SW12_CLAMP_DUTY BIT(14) |
| AnnaBridge | 167:e84263d55307 | 435 | #define BIT_SYS_SWR12_BYPASS_SSR BIT(13) |
| AnnaBridge | 167:e84263d55307 | 436 | #define BIT_SYS_SWR12_ZCDOUT_EN BIT(12) |
| AnnaBridge | 167:e84263d55307 | 437 | #define BIT_SYS_SWR12_POW_ZCD BIT(11) |
| AnnaBridge | 167:e84263d55307 | 438 | #define BIT_SYS_SW12_AREN BIT(10) |
| AnnaBridge | 167:e84263d55307 | 439 | |
| AnnaBridge | 167:e84263d55307 | 440 | #define BIT_SHIFT_SYS_SWR12_OCP_CUR 7 |
| AnnaBridge | 167:e84263d55307 | 441 | #define BIT_MASK_SYS_SWR12_OCP_CUR 0x7 |
| AnnaBridge | 167:e84263d55307 | 442 | #define BIT_SYS_SWR12_OCP_CUR(x) (((x) & BIT_MASK_SYS_SWR12_OCP_CUR) << BIT_SHIFT_SYS_SWR12_OCP_CUR) |
| AnnaBridge | 167:e84263d55307 | 443 | |
| AnnaBridge | 167:e84263d55307 | 444 | #define BIT_SYS_SWR12_OCP_EN BIT(6) |
| AnnaBridge | 167:e84263d55307 | 445 | |
| AnnaBridge | 167:e84263d55307 | 446 | #define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L 4 |
| AnnaBridge | 167:e84263d55307 | 447 | #define BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L 0x3 |
| AnnaBridge | 167:e84263d55307 | 448 | #define BIT_SYS_SWR12_SAWTOOTH_CF_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L) |
| AnnaBridge | 167:e84263d55307 | 449 | |
| AnnaBridge | 167:e84263d55307 | 450 | |
| AnnaBridge | 167:e84263d55307 | 451 | #define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L 2 |
| AnnaBridge | 167:e84263d55307 | 452 | #define BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L 0x3 |
| AnnaBridge | 167:e84263d55307 | 453 | #define BIT_SYS_SWR12_SAWTOOTH_CFC_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L) |
| AnnaBridge | 167:e84263d55307 | 454 | |
| AnnaBridge | 167:e84263d55307 | 455 | |
| AnnaBridge | 167:e84263d55307 | 456 | #define BIT_SHIFT_SYS_SWR12_COMP_R3 0 |
| AnnaBridge | 167:e84263d55307 | 457 | #define BIT_MASK_SYS_SWR12_COMP_R3 0x3 |
| AnnaBridge | 167:e84263d55307 | 458 | #define BIT_SYS_SWR12_COMP_R3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R3) << BIT_SHIFT_SYS_SWR12_COMP_R3) |
| AnnaBridge | 167:e84263d55307 | 459 | |
| AnnaBridge | 167:e84263d55307 | 460 | |
| AnnaBridge | 167:e84263d55307 | 461 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 462 | |
| AnnaBridge | 167:e84263d55307 | 463 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 464 | |
| AnnaBridge | 167:e84263d55307 | 465 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 466 | |
| AnnaBridge | 167:e84263d55307 | 467 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 468 | |
| AnnaBridge | 167:e84263d55307 | 469 | //2 REG_SYS_XTAL_CTRL0 |
| AnnaBridge | 167:e84263d55307 | 470 | #define BIT_SYS_XTAL_XQSEL BIT(31) |
| AnnaBridge | 167:e84263d55307 | 471 | #define BIT_SYS_XTAL_XQSEL_RF BIT(30) |
| AnnaBridge | 167:e84263d55307 | 472 | |
| AnnaBridge | 167:e84263d55307 | 473 | #define BIT_SHIFT_SYS_XTAL_SC_XO 24 |
| AnnaBridge | 167:e84263d55307 | 474 | #define BIT_MASK_SYS_XTAL_SC_XO 0x3f |
| AnnaBridge | 167:e84263d55307 | 475 | #define BIT_SYS_XTAL_SC_XO(x) (((x) & BIT_MASK_SYS_XTAL_SC_XO) << BIT_SHIFT_SYS_XTAL_SC_XO) |
| AnnaBridge | 167:e84263d55307 | 476 | |
| AnnaBridge | 167:e84263d55307 | 477 | |
| AnnaBridge | 167:e84263d55307 | 478 | #define BIT_SHIFT_SYS_XTAL_SC_XI 18 |
| AnnaBridge | 167:e84263d55307 | 479 | #define BIT_MASK_SYS_XTAL_SC_XI 0x3f |
| AnnaBridge | 167:e84263d55307 | 480 | #define BIT_SYS_XTAL_SC_XI(x) (((x) & BIT_MASK_SYS_XTAL_SC_XI) << BIT_SHIFT_SYS_XTAL_SC_XI) |
| AnnaBridge | 167:e84263d55307 | 481 | |
| AnnaBridge | 167:e84263d55307 | 482 | |
| AnnaBridge | 167:e84263d55307 | 483 | #define BIT_SHIFT_SYS_XTAL_GMN 13 |
| AnnaBridge | 167:e84263d55307 | 484 | #define BIT_MASK_SYS_XTAL_GMN 0x1f |
| AnnaBridge | 167:e84263d55307 | 485 | #define BIT_SYS_XTAL_GMN(x) (((x) & BIT_MASK_SYS_XTAL_GMN) << BIT_SHIFT_SYS_XTAL_GMN) |
| AnnaBridge | 167:e84263d55307 | 486 | |
| AnnaBridge | 167:e84263d55307 | 487 | |
| AnnaBridge | 167:e84263d55307 | 488 | #define BIT_SHIFT_SYS_XTAL_GMP 8 |
| AnnaBridge | 167:e84263d55307 | 489 | #define BIT_MASK_SYS_XTAL_GMP 0x1f |
| AnnaBridge | 167:e84263d55307 | 490 | #define BIT_SYS_XTAL_GMP(x) (((x) & BIT_MASK_SYS_XTAL_GMP) << BIT_SHIFT_SYS_XTAL_GMP) |
| AnnaBridge | 167:e84263d55307 | 491 | |
| AnnaBridge | 167:e84263d55307 | 492 | #define BIT_SYS_XTAL_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 493 | #define BIT_SYS_XTAL_BGMB_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 494 | |
| AnnaBridge | 167:e84263d55307 | 495 | //2 REG_SYS_XTAL_CTRL1 |
| AnnaBridge | 167:e84263d55307 | 496 | |
| AnnaBridge | 167:e84263d55307 | 497 | #define BIT_SHIFT_SYS_XTAL_COUNTER_MUX 25 |
| AnnaBridge | 167:e84263d55307 | 498 | #define BIT_MASK_SYS_XTAL_COUNTER_MUX 0x3 |
| AnnaBridge | 167:e84263d55307 | 499 | #define BIT_SYS_XTAL_COUNTER_MUX(x) (((x) & BIT_MASK_SYS_XTAL_COUNTER_MUX) << BIT_SHIFT_SYS_XTAL_COUNTER_MUX) |
| AnnaBridge | 167:e84263d55307 | 500 | |
| AnnaBridge | 167:e84263d55307 | 501 | #define BIT_SYS_XTAL_DELAY_SYSPLL BIT(24) |
| AnnaBridge | 167:e84263d55307 | 502 | #define BIT_SYS_XTAL_DELAY_USB BIT(23) |
| AnnaBridge | 167:e84263d55307 | 503 | #define BIT_SYS_XTAL_DELAY_WLAFE BIT(22) |
| AnnaBridge | 167:e84263d55307 | 504 | #define BIT_SYS_XTAL_AGPIO_SEL BIT(21) |
| AnnaBridge | 167:e84263d55307 | 505 | |
| AnnaBridge | 167:e84263d55307 | 506 | #define BIT_SHIFT_SYS_XTAL_DRV_AGPIO 19 |
| AnnaBridge | 167:e84263d55307 | 507 | #define BIT_MASK_SYS_XTAL_DRV_AGPIO 0x3 |
| AnnaBridge | 167:e84263d55307 | 508 | #define BIT_SYS_XTAL_DRV_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_DRV_AGPIO) << BIT_SHIFT_SYS_XTAL_DRV_AGPIO) |
| AnnaBridge | 167:e84263d55307 | 509 | |
| AnnaBridge | 167:e84263d55307 | 510 | |
| AnnaBridge | 167:e84263d55307 | 511 | #define BIT_SHIFT_SYS_XTAL_AGPIO 16 |
| AnnaBridge | 167:e84263d55307 | 512 | #define BIT_MASK_SYS_XTAL_AGPIO 0x7 |
| AnnaBridge | 167:e84263d55307 | 513 | #define BIT_SYS_XTAL_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_AGPIO) << BIT_SHIFT_SYS_XTAL_AGPIO) |
| AnnaBridge | 167:e84263d55307 | 514 | |
| AnnaBridge | 167:e84263d55307 | 515 | |
| AnnaBridge | 167:e84263d55307 | 516 | #define BIT_SHIFT_SYS_XTAL_DRV_SYSPLL 14 |
| AnnaBridge | 167:e84263d55307 | 517 | #define BIT_MASK_SYS_XTAL_DRV_SYSPLL 0x3 |
| AnnaBridge | 167:e84263d55307 | 518 | #define BIT_SYS_XTAL_DRV_SYSPLL(x) (((x) & BIT_MASK_SYS_XTAL_DRV_SYSPLL) << BIT_SHIFT_SYS_XTAL_DRV_SYSPLL) |
| AnnaBridge | 167:e84263d55307 | 519 | |
| AnnaBridge | 167:e84263d55307 | 520 | #define BIT_SYS_XTAL_GATE_SYSPLL BIT(13) |
| AnnaBridge | 167:e84263d55307 | 521 | |
| AnnaBridge | 167:e84263d55307 | 522 | #define BIT_SHIFT_SYS_XTAL_DRV_USB 11 |
| AnnaBridge | 167:e84263d55307 | 523 | #define BIT_MASK_SYS_XTAL_DRV_USB 0x3 |
| AnnaBridge | 167:e84263d55307 | 524 | #define BIT_SYS_XTAL_DRV_USB(x) (((x) & BIT_MASK_SYS_XTAL_DRV_USB) << BIT_SHIFT_SYS_XTAL_DRV_USB) |
| AnnaBridge | 167:e84263d55307 | 525 | |
| AnnaBridge | 167:e84263d55307 | 526 | #define BIT_SYS_XTAL_GATE_USB BIT(10) |
| AnnaBridge | 167:e84263d55307 | 527 | |
| AnnaBridge | 167:e84263d55307 | 528 | #define BIT_SHIFT_SYS_XTAL_DRV_WLAFE 8 |
| AnnaBridge | 167:e84263d55307 | 529 | #define BIT_MASK_SYS_XTAL_DRV_WLAFE 0x3 |
| AnnaBridge | 167:e84263d55307 | 530 | #define BIT_SYS_XTAL_DRV_WLAFE(x) (((x) & BIT_MASK_SYS_XTAL_DRV_WLAFE) << BIT_SHIFT_SYS_XTAL_DRV_WLAFE) |
| AnnaBridge | 167:e84263d55307 | 531 | |
| AnnaBridge | 167:e84263d55307 | 532 | #define BIT_SYS_XTAL_GATE_WLAFE BIT(7) |
| AnnaBridge | 167:e84263d55307 | 533 | |
| AnnaBridge | 167:e84263d55307 | 534 | #define BIT_SHIFT_SYS_XTAL_DRV_RF2 5 |
| AnnaBridge | 167:e84263d55307 | 535 | #define BIT_MASK_SYS_XTAL_DRV_RF2 0x3 |
| AnnaBridge | 167:e84263d55307 | 536 | #define BIT_SYS_XTAL_DRV_RF2(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF2) << BIT_SHIFT_SYS_XTAL_DRV_RF2) |
| AnnaBridge | 167:e84263d55307 | 537 | |
| AnnaBridge | 167:e84263d55307 | 538 | #define BIT_SYS_XTAL_GATE_RF2 BIT(4) |
| AnnaBridge | 167:e84263d55307 | 539 | |
| AnnaBridge | 167:e84263d55307 | 540 | #define BIT_SHIFT_SYS_XTAL_DRV_RF1 3 |
| AnnaBridge | 167:e84263d55307 | 541 | #define BIT_MASK_SYS_XTAL_DRV_RF1 0x3 |
| AnnaBridge | 167:e84263d55307 | 542 | #define BIT_SYS_XTAL_DRV_RF1(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF1) << BIT_SHIFT_SYS_XTAL_DRV_RF1) |
| AnnaBridge | 167:e84263d55307 | 543 | |
| AnnaBridge | 167:e84263d55307 | 544 | #define BIT_SYS_XTAL_GATE_RF1 BIT(1) |
| AnnaBridge | 167:e84263d55307 | 545 | |
| AnnaBridge | 167:e84263d55307 | 546 | #define BIT_SHIFT_SYS_XTAL_LDO 0 |
| AnnaBridge | 167:e84263d55307 | 547 | #define BIT_MASK_SYS_XTAL_LDO 0x3 |
| AnnaBridge | 167:e84263d55307 | 548 | #define BIT_SYS_XTAL_LDO(x) (((x) & BIT_MASK_SYS_XTAL_LDO) << BIT_SHIFT_SYS_XTAL_LDO) |
| AnnaBridge | 167:e84263d55307 | 549 | |
| AnnaBridge | 167:e84263d55307 | 550 | |
| AnnaBridge | 167:e84263d55307 | 551 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 552 | |
| AnnaBridge | 167:e84263d55307 | 553 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 554 | |
| AnnaBridge | 167:e84263d55307 | 555 | //2 REG_SYS_SYSPLL_CTRL0 |
| AnnaBridge | 167:e84263d55307 | 556 | |
| AnnaBridge | 167:e84263d55307 | 557 | #define BIT_SHIFT_SYS_SYSPLL_LPF_R3 29 |
| AnnaBridge | 167:e84263d55307 | 558 | #define BIT_MASK_SYS_SYSPLL_LPF_R3 0x7 |
| AnnaBridge | 167:e84263d55307 | 559 | #define BIT_SYS_SYSPLL_LPF_R3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_R3) << BIT_SHIFT_SYS_SYSPLL_LPF_R3) |
| AnnaBridge | 167:e84263d55307 | 560 | |
| AnnaBridge | 167:e84263d55307 | 561 | |
| AnnaBridge | 167:e84263d55307 | 562 | #define BIT_SHIFT_SYS_SYSPLL_LPF_CS 27 |
| AnnaBridge | 167:e84263d55307 | 563 | #define BIT_MASK_SYS_SYSPLL_LPF_CS 0x3 |
| AnnaBridge | 167:e84263d55307 | 564 | #define BIT_SYS_SYSPLL_LPF_CS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CS) << BIT_SHIFT_SYS_SYSPLL_LPF_CS) |
| AnnaBridge | 167:e84263d55307 | 565 | |
| AnnaBridge | 167:e84263d55307 | 566 | |
| AnnaBridge | 167:e84263d55307 | 567 | #define BIT_SHIFT_SYS_SYSPLL_LPF_CP 25 |
| AnnaBridge | 167:e84263d55307 | 568 | #define BIT_MASK_SYS_SYSPLL_LPF_CP 0x3 |
| AnnaBridge | 167:e84263d55307 | 569 | #define BIT_SYS_SYSPLL_LPF_CP(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CP) << BIT_SHIFT_SYS_SYSPLL_LPF_CP) |
| AnnaBridge | 167:e84263d55307 | 570 | |
| AnnaBridge | 167:e84263d55307 | 571 | |
| AnnaBridge | 167:e84263d55307 | 572 | #define BIT_SHIFT_SYS_SYSPLL_LPF_C3 23 |
| AnnaBridge | 167:e84263d55307 | 573 | #define BIT_MASK_SYS_SYSPLL_LPF_C3 0x3 |
| AnnaBridge | 167:e84263d55307 | 574 | #define BIT_SYS_SYSPLL_LPF_C3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_C3) << BIT_SHIFT_SYS_SYSPLL_LPF_C3) |
| AnnaBridge | 167:e84263d55307 | 575 | |
| AnnaBridge | 167:e84263d55307 | 576 | #define BIT_SYS_SYSPLL_WDOG_ENB BIT(22) |
| AnnaBridge | 167:e84263d55307 | 577 | #define BIT_SYS_SYSPLL_CKTST_EN BIT(21) |
| AnnaBridge | 167:e84263d55307 | 578 | |
| AnnaBridge | 167:e84263d55307 | 579 | #define BIT_SHIFT_SYS_SYSPLL_MONCK_SEL 18 |
| AnnaBridge | 167:e84263d55307 | 580 | #define BIT_MASK_SYS_SYSPLL_MONCK_SEL 0x7 |
| AnnaBridge | 167:e84263d55307 | 581 | #define BIT_SYS_SYSPLL_MONCK_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_MONCK_SEL) << BIT_SHIFT_SYS_SYSPLL_MONCK_SEL) |
| AnnaBridge | 167:e84263d55307 | 582 | |
| AnnaBridge | 167:e84263d55307 | 583 | |
| AnnaBridge | 167:e84263d55307 | 584 | #define BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET 13 |
| AnnaBridge | 167:e84263d55307 | 585 | #define BIT_MASK_SYS_SYSPLL_CP_IOFFSET 0x1f |
| AnnaBridge | 167:e84263d55307 | 586 | #define BIT_SYS_SYSPLL_CP_IOFFSET(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_IOFFSET) << BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET) |
| AnnaBridge | 167:e84263d55307 | 587 | |
| AnnaBridge | 167:e84263d55307 | 588 | #define BIT_SYS_SYSPLL_CP_IDOUBLE BIT(12) |
| AnnaBridge | 167:e84263d55307 | 589 | |
| AnnaBridge | 167:e84263d55307 | 590 | #define BIT_SHIFT_SYS_SYSPLL_CP_BIAS 9 |
| AnnaBridge | 167:e84263d55307 | 591 | #define BIT_MASK_SYS_SYSPLL_CP_BIAS 0x7 |
| AnnaBridge | 167:e84263d55307 | 592 | #define BIT_SYS_SYSPLL_CP_BIAS(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_BIAS) << BIT_SHIFT_SYS_SYSPLL_CP_BIAS) |
| AnnaBridge | 167:e84263d55307 | 593 | |
| AnnaBridge | 167:e84263d55307 | 594 | #define BIT_SYS_SYSPLL_FREF_EDGE BIT(8) |
| AnnaBridge | 167:e84263d55307 | 595 | #define BIT_SYS_SYSPLL_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 596 | #define BIT_SYS_SYSPLL_LVPC_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 597 | |
| AnnaBridge | 167:e84263d55307 | 598 | //2 REG_SYS_SYSPLL_CTRL1 |
| AnnaBridge | 167:e84263d55307 | 599 | #define BIT_SYS_SYSPLL_CK500K_SEL BIT(15) |
| AnnaBridge | 167:e84263d55307 | 600 | #define BIT_SYS_SYSPLL_CK200M_EN BIT(14) |
| AnnaBridge | 167:e84263d55307 | 601 | #define BIT_SYS_SYSPLL_CKSDR_EN BIT(13) |
| AnnaBridge | 167:e84263d55307 | 602 | |
| AnnaBridge | 167:e84263d55307 | 603 | #define BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV 11 |
| AnnaBridge | 167:e84263d55307 | 604 | #define BIT_MASK_SYS_SYSPLL_CKSDR_DIV 0x3 |
| AnnaBridge | 167:e84263d55307 | 605 | #define BIT_SYS_SYSPLL_CKSDR_DIV(x) (((x) & BIT_MASK_SYS_SYSPLL_CKSDR_DIV) << BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV) |
| AnnaBridge | 167:e84263d55307 | 606 | |
| AnnaBridge | 167:e84263d55307 | 607 | #define BIT_SYS_SYSPLL_CK24P576_EN BIT(9) |
| AnnaBridge | 167:e84263d55307 | 608 | #define BIT_SYS_SYSPLL_CK22P5792_EN BIT(8) |
| AnnaBridge | 167:e84263d55307 | 609 | #define BIT_SYS_SYSPLL_CK_PS_EN BIT(6) |
| AnnaBridge | 167:e84263d55307 | 610 | |
| AnnaBridge | 167:e84263d55307 | 611 | #define BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL 3 |
| AnnaBridge | 167:e84263d55307 | 612 | #define BIT_MASK_SYS_SYSPLL_CK_PS_SEL 0x7 |
| AnnaBridge | 167:e84263d55307 | 613 | #define BIT_SYS_SYSPLL_CK_PS_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_CK_PS_SEL) << BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL) |
| AnnaBridge | 167:e84263d55307 | 614 | |
| AnnaBridge | 167:e84263d55307 | 615 | |
| AnnaBridge | 167:e84263d55307 | 616 | #define BIT_SHIFT_SYS_SYSPLL_LPF_RS 0 |
| AnnaBridge | 167:e84263d55307 | 617 | #define BIT_MASK_SYS_SYSPLL_LPF_RS 0x7 |
| AnnaBridge | 167:e84263d55307 | 618 | #define BIT_SYS_SYSPLL_LPF_RS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_RS) << BIT_SHIFT_SYS_SYSPLL_LPF_RS) |
| AnnaBridge | 167:e84263d55307 | 619 | |
| AnnaBridge | 167:e84263d55307 | 620 | |
| AnnaBridge | 167:e84263d55307 | 621 | //2 REG_SYS_SYSPLL_CTRL2 |
| AnnaBridge | 167:e84263d55307 | 622 | |
| AnnaBridge | 167:e84263d55307 | 623 | #define BIT_SHIFT_XTAL_DRV_RF_LATCH 0 |
| AnnaBridge | 167:e84263d55307 | 624 | #define BIT_MASK_XTAL_DRV_RF_LATCH 0xffffffffL |
| AnnaBridge | 167:e84263d55307 | 625 | #define BIT_XTAL_DRV_RF_LATCH(x) (((x) & BIT_MASK_XTAL_DRV_RF_LATCH) << BIT_SHIFT_XTAL_DRV_RF_LATCH) |
| AnnaBridge | 167:e84263d55307 | 626 | |
| AnnaBridge | 167:e84263d55307 | 627 | |
| AnnaBridge | 167:e84263d55307 | 628 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 629 | |
| AnnaBridge | 167:e84263d55307 | 630 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 631 | |
| AnnaBridge | 167:e84263d55307 | 632 | #define BIT_SHIFT_PESOC_CPU_OCP_CK_SEL 0 |
| AnnaBridge | 167:e84263d55307 | 633 | #define BIT_MASK_PESOC_CPU_OCP_CK_SEL 0x7 |
| AnnaBridge | 167:e84263d55307 | 634 | #define BIT_PESOC_CPU_OCP_CK_SEL(x) (((x) & BIT_MASK_PESOC_CPU_OCP_CK_SEL) << BIT_SHIFT_PESOC_CPU_OCP_CK_SEL) |
| AnnaBridge | 167:e84263d55307 | 635 | |
| AnnaBridge | 167:e84263d55307 | 636 | |
| AnnaBridge | 167:e84263d55307 | 637 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 638 | |
| AnnaBridge | 167:e84263d55307 | 639 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 640 | |
| AnnaBridge | 167:e84263d55307 | 641 | //2 REG_ |
| AnnaBridge | 167:e84263d55307 | 642 | |
| AnnaBridge | 167:e84263d55307 | 643 | //2 REG_SYS_ANA_TIM_CTRL |
| AnnaBridge | 167:e84263d55307 | 644 | |
| AnnaBridge | 167:e84263d55307 | 645 | #define BIT_SHIFT_SYS_ANACK_TU_TIME 16 |
| AnnaBridge | 167:e84263d55307 | 646 | #define BIT_MASK_SYS_ANACK_TU_TIME 0x3f |
| AnnaBridge | 167:e84263d55307 | 647 | #define BIT_SYS_ANACK_TU_TIME(x) (((x) & BIT_MASK_SYS_ANACK_TU_TIME) << BIT_SHIFT_SYS_ANACK_TU_TIME) |
| AnnaBridge | 167:e84263d55307 | 648 | |
| AnnaBridge | 167:e84263d55307 | 649 | #define BIT_SYS_DSBYCNT_EN BIT(15) |
| AnnaBridge | 167:e84263d55307 | 650 | |
| AnnaBridge | 167:e84263d55307 | 651 | #define BIT_SHIFT_SYS_DSTDY_TIM_SCAL 8 |
| AnnaBridge | 167:e84263d55307 | 652 | #define BIT_MASK_SYS_DSTDY_TIM_SCAL 0xf |
| AnnaBridge | 167:e84263d55307 | 653 | #define BIT_SYS_DSTDY_TIM_SCAL(x) (((x) & BIT_MASK_SYS_DSTDY_TIM_SCAL) << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) |
| AnnaBridge | 167:e84263d55307 | 654 | |
| AnnaBridge | 167:e84263d55307 | 655 | |
| AnnaBridge | 167:e84263d55307 | 656 | #define BIT_SHIFT_SYS_DSTBY_TIM_PERIOD 0 |
| AnnaBridge | 167:e84263d55307 | 657 | #define BIT_MASK_SYS_DSTBY_TIM_PERIOD 0xff |
| AnnaBridge | 167:e84263d55307 | 658 | #define BIT_SYS_DSTBY_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSTBY_TIM_PERIOD) << BIT_SHIFT_SYS_DSTBY_TIM_PERIOD) |
| AnnaBridge | 167:e84263d55307 | 659 | |
| AnnaBridge | 167:e84263d55307 | 660 | |
| AnnaBridge | 167:e84263d55307 | 661 | //2 REG_SYS_DSLP_TIM_CTRL |
| AnnaBridge | 167:e84263d55307 | 662 | |
| AnnaBridge | 167:e84263d55307 | 663 | #define BIT_SHIFT_SYS_REGU_ASIF_EN 24 |
| AnnaBridge | 167:e84263d55307 | 664 | #define BIT_MASK_SYS_REGU_ASIF_EN 0xff |
| AnnaBridge | 167:e84263d55307 | 665 | #define BIT_SYS_REGU_ASIF_EN(x) (((x) & BIT_MASK_SYS_REGU_ASIF_EN) << BIT_SHIFT_SYS_REGU_ASIF_EN) |
| AnnaBridge | 167:e84263d55307 | 666 | |
| AnnaBridge | 167:e84263d55307 | 667 | |
| AnnaBridge | 167:e84263d55307 | 668 | #define BIT_SHIFT_SYS_REGU_ASIF_THP_DA 20 |
| AnnaBridge | 167:e84263d55307 | 669 | #define BIT_MASK_SYS_REGU_ASIF_THP_DA 0x3 |
| AnnaBridge | 167:e84263d55307 | 670 | #define BIT_SYS_REGU_ASIF_THP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_THP_DA) << BIT_SHIFT_SYS_REGU_ASIF_THP_DA) |
| AnnaBridge | 167:e84263d55307 | 671 | |
| AnnaBridge | 167:e84263d55307 | 672 | |
| AnnaBridge | 167:e84263d55307 | 673 | #define BIT_SHIFT_SYS_REGU_ASIF_TPD_CK 18 |
| AnnaBridge | 167:e84263d55307 | 674 | #define BIT_MASK_SYS_REGU_ASIF_TPD_CK 0x3 |
| AnnaBridge | 167:e84263d55307 | 675 | #define BIT_SYS_REGU_ASIF_TPD_CK(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TPD_CK) << BIT_SHIFT_SYS_REGU_ASIF_TPD_CK) |
| AnnaBridge | 167:e84263d55307 | 676 | |
| AnnaBridge | 167:e84263d55307 | 677 | |
| AnnaBridge | 167:e84263d55307 | 678 | #define BIT_SHIFT_SYS_REGU_ASIF_TSP_DA 16 |
| AnnaBridge | 167:e84263d55307 | 679 | #define BIT_MASK_SYS_REGU_ASIF_TSP_DA 0x3 |
| AnnaBridge | 167:e84263d55307 | 680 | #define BIT_SYS_REGU_ASIF_TSP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TSP_DA) << BIT_SHIFT_SYS_REGU_ASIF_TSP_DA) |
| AnnaBridge | 167:e84263d55307 | 681 | |
| AnnaBridge | 167:e84263d55307 | 682 | #define BIT_SYS_REGU_ASIF_POLL BIT(15) |
| AnnaBridge | 167:e84263d55307 | 683 | #define BIT_SYS_REGU_ASIF_MODE BIT(14) |
| AnnaBridge | 167:e84263d55307 | 684 | #define BIT_SYS_REGU_ASIF_WE BIT(12) |
| AnnaBridge | 167:e84263d55307 | 685 | |
| AnnaBridge | 167:e84263d55307 | 686 | #define BIT_SHIFT_SYS_REGU_ASIF_AD 8 |
| AnnaBridge | 167:e84263d55307 | 687 | #define BIT_MASK_SYS_REGU_ASIF_AD 0xf |
| AnnaBridge | 167:e84263d55307 | 688 | #define BIT_SYS_REGU_ASIF_AD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_AD) << BIT_SHIFT_SYS_REGU_ASIF_AD) |
| AnnaBridge | 167:e84263d55307 | 689 | |
| AnnaBridge | 167:e84263d55307 | 690 | |
| AnnaBridge | 167:e84263d55307 | 691 | #define BIT_SHIFT_SYS_REGU_ASIF_WD 0 |
| AnnaBridge | 167:e84263d55307 | 692 | #define BIT_MASK_SYS_REGU_ASIF_WD 0xff |
| AnnaBridge | 167:e84263d55307 | 693 | #define BIT_SYS_REGU_ASIF_WD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_WD) << BIT_SHIFT_SYS_REGU_ASIF_WD) |
| AnnaBridge | 167:e84263d55307 | 694 | |
| AnnaBridge | 167:e84263d55307 | 695 | |
| AnnaBridge | 167:e84263d55307 | 696 | //2 REG_SYS_DSLP_TIM_CAL_CTRL |
| AnnaBridge | 167:e84263d55307 | 697 | #define BIT_SYS_DSLP_TIM_EN BIT(24) |
| AnnaBridge | 167:e84263d55307 | 698 | |
| AnnaBridge | 167:e84263d55307 | 699 | #define BIT_SHIFT_SYS_DSLP_TIM_PERIOD 0 |
| AnnaBridge | 167:e84263d55307 | 700 | #define BIT_MASK_SYS_DSLP_TIM_PERIOD 0x7fffff |
| AnnaBridge | 167:e84263d55307 | 701 | #define BIT_SYS_DSLP_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSLP_TIM_PERIOD) << BIT_SHIFT_SYS_DSLP_TIM_PERIOD) |
| AnnaBridge | 167:e84263d55307 | 702 | |
| AnnaBridge | 167:e84263d55307 | 703 | |
| AnnaBridge | 167:e84263d55307 | 704 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 705 | |
| AnnaBridge | 167:e84263d55307 | 706 | //2 REG_SYS_DEBUG_CTRL |
| AnnaBridge | 167:e84263d55307 | 707 | #define BIT_SYS_DBG_PIN_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 708 | |
| AnnaBridge | 167:e84263d55307 | 709 | //2 REG_SYS_PINMUX_CTRL |
| AnnaBridge | 167:e84263d55307 | 710 | #define BIT_EEPROM_PIN_EN BIT(4) |
| AnnaBridge | 167:e84263d55307 | 711 | #define BIT_SIC_PIN_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 712 | |
| AnnaBridge | 167:e84263d55307 | 713 | //2 REG_SYS_GPIO_DSTBY_WAKE_CTRL0 |
| AnnaBridge | 167:e84263d55307 | 714 | #define BIT_SYS_GPIOE3_WEVENT_STS BIT(27) |
| AnnaBridge | 167:e84263d55307 | 715 | #define BIT_SYS_GPIOD5_WEVENT_STS BIT(26) |
| AnnaBridge | 167:e84263d55307 | 716 | #define BIT_SYS_GPIOC7_WEVENT_STS BIT(25) |
| AnnaBridge | 167:e84263d55307 | 717 | #define BIT_SYS_GPIOA5_WEVENT_STS BIT(24) |
| AnnaBridge | 167:e84263d55307 | 718 | #define BIT_SYS_GPIO_GPE3_PULL_CTRL_EN BIT(19) |
| AnnaBridge | 167:e84263d55307 | 719 | #define BIT_SYS_GPIO_GPD5_PULL_CTRL_EN BIT(18) |
| AnnaBridge | 167:e84263d55307 | 720 | #define BIT_SYS_GPIO_GPC7_PULL_CTRL_EN BIT(17) |
| AnnaBridge | 167:e84263d55307 | 721 | #define BIT_SYS_GPIO_GPA5_PULL_CTRL_EN BIT(16) |
| AnnaBridge | 167:e84263d55307 | 722 | #define BIT_SYS_GPIOE3_WINT_MODE BIT(11) |
| AnnaBridge | 167:e84263d55307 | 723 | #define BIT_SYS_GPIOD5_WINT_MODE BIT(10) |
| AnnaBridge | 167:e84263d55307 | 724 | #define BIT_SYS_GPIOC7_WINT_MODE BIT(9) |
| AnnaBridge | 167:e84263d55307 | 725 | #define BIT_SYS_GPIOA5_WINT_MODE BIT(8) |
| AnnaBridge | 167:e84263d55307 | 726 | #define BIT_SYS_GPIOE3_PIN_EN BIT(3) |
| AnnaBridge | 167:e84263d55307 | 727 | #define BIT_SYS_GPIOD5_PIN_EN BIT(2) |
| AnnaBridge | 167:e84263d55307 | 728 | #define BIT_SYS_GPIOC7_PIN_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 729 | #define BIT_SYS_GPIOA5_PIN_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 730 | |
| AnnaBridge | 167:e84263d55307 | 731 | //2 REG_SYS_GPIO_DSTBY_WAKE_CTRL1 |
| AnnaBridge | 167:e84263d55307 | 732 | #define BIT_SYS_GPIOE3_SHTDN_N BIT(19) |
| AnnaBridge | 167:e84263d55307 | 733 | #define BIT_SYS_GPIOD5_SHTDN_N BIT(18) |
| AnnaBridge | 167:e84263d55307 | 734 | #define BIT_SYS_GPIOC7_SHTDN_N BIT(17) |
| AnnaBridge | 167:e84263d55307 | 735 | #define BIT_SYS_GPIOA5_SHTDN_N BIT(16) |
| AnnaBridge | 167:e84263d55307 | 736 | |
| AnnaBridge | 167:e84263d55307 | 737 | #define BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL 8 |
| AnnaBridge | 167:e84263d55307 | 738 | #define BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL 0x3 |
| AnnaBridge | 167:e84263d55307 | 739 | #define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL(x) (((x) & BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL) << BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL) |
| AnnaBridge | 167:e84263d55307 | 740 | |
| AnnaBridge | 167:e84263d55307 | 741 | #define BIT_SYS_GPIOE3_WINT_DEBOUNCE_EN BIT(3) |
| AnnaBridge | 167:e84263d55307 | 742 | #define BIT_SYS_GPIOD5_WINT_DEBOUNCE_EN BIT(2) |
| AnnaBridge | 167:e84263d55307 | 743 | #define BIT_SYS_GPIOC7_WINT_DEBOUNCE_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 744 | #define BIT_SYS_GPIOA5_WINT_DEBOUNCE_EN BIT(0) |
| AnnaBridge | 167:e84263d55307 | 745 | |
| AnnaBridge | 167:e84263d55307 | 746 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 747 | |
| AnnaBridge | 167:e84263d55307 | 748 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 749 | |
| AnnaBridge | 167:e84263d55307 | 750 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 751 | |
| AnnaBridge | 167:e84263d55307 | 752 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 753 | |
| AnnaBridge | 167:e84263d55307 | 754 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 755 | |
| AnnaBridge | 167:e84263d55307 | 756 | //2 REG_SYS_DEBUG_REG |
| AnnaBridge | 167:e84263d55307 | 757 | |
| AnnaBridge | 167:e84263d55307 | 758 | #define BIT_SHIFT_SYS_DBG_VALUE 0 |
| AnnaBridge | 167:e84263d55307 | 759 | #define BIT_MASK_SYS_DBG_VALUE 0xffffffffL |
| AnnaBridge | 167:e84263d55307 | 760 | #define BIT_SYS_DBG_VALUE(x) (((x) & BIT_MASK_SYS_DBG_VALUE) << BIT_SHIFT_SYS_DBG_VALUE) |
| AnnaBridge | 167:e84263d55307 | 761 | |
| AnnaBridge | 167:e84263d55307 | 762 | |
| AnnaBridge | 167:e84263d55307 | 763 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 764 | |
| AnnaBridge | 167:e84263d55307 | 765 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 766 | |
| AnnaBridge | 167:e84263d55307 | 767 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 768 | |
| AnnaBridge | 167:e84263d55307 | 769 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 770 | |
| AnnaBridge | 167:e84263d55307 | 771 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 772 | |
| AnnaBridge | 167:e84263d55307 | 773 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 774 | |
| AnnaBridge | 167:e84263d55307 | 775 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 776 | |
| AnnaBridge | 167:e84263d55307 | 777 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 778 | |
| AnnaBridge | 167:e84263d55307 | 779 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 780 | |
| AnnaBridge | 167:e84263d55307 | 781 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 782 | |
| AnnaBridge | 167:e84263d55307 | 783 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 784 | |
| AnnaBridge | 167:e84263d55307 | 785 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 786 | |
| AnnaBridge | 167:e84263d55307 | 787 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 788 | |
| AnnaBridge | 167:e84263d55307 | 789 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 790 | |
| AnnaBridge | 167:e84263d55307 | 791 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 792 | |
| AnnaBridge | 167:e84263d55307 | 793 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 794 | |
| AnnaBridge | 167:e84263d55307 | 795 | //2 REG_SYS_EEPROM_CTRL0 |
| AnnaBridge | 167:e84263d55307 | 796 | |
| AnnaBridge | 167:e84263d55307 | 797 | #define BIT_SHIFT_EFUSE_UNLOCK 24 |
| AnnaBridge | 167:e84263d55307 | 798 | #define BIT_MASK_EFUSE_UNLOCK 0xff |
| AnnaBridge | 167:e84263d55307 | 799 | #define BIT_EFUSE_UNLOCK(x) (((x) & BIT_MASK_EFUSE_UNLOCK) << BIT_SHIFT_EFUSE_UNLOCK) |
| AnnaBridge | 167:e84263d55307 | 800 | |
| AnnaBridge | 167:e84263d55307 | 801 | |
| AnnaBridge | 167:e84263d55307 | 802 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 803 | #define BIT_SYS_EFUSE_LDALL BIT(16) |
| AnnaBridge | 167:e84263d55307 | 804 | |
| AnnaBridge | 167:e84263d55307 | 805 | #define BIT_SHIFT_SYS_EEPROM_VPDIDX 8 |
| AnnaBridge | 167:e84263d55307 | 806 | #define BIT_MASK_SYS_EEPROM_VPDIDX 0xff |
| AnnaBridge | 167:e84263d55307 | 807 | #define BIT_SYS_EEPROM_VPDIDX(x) (((x) & BIT_MASK_SYS_EEPROM_VPDIDX) << BIT_SHIFT_SYS_EEPROM_VPDIDX) |
| AnnaBridge | 167:e84263d55307 | 808 | |
| AnnaBridge | 167:e84263d55307 | 809 | |
| AnnaBridge | 167:e84263d55307 | 810 | #define BIT_SHIFT_SYS_EEPROM_MD 6 |
| AnnaBridge | 167:e84263d55307 | 811 | #define BIT_MASK_SYS_EEPROM_MD 0x3 |
| AnnaBridge | 167:e84263d55307 | 812 | #define BIT_SYS_EEPROM_MD(x) (((x) & BIT_MASK_SYS_EEPROM_MD) << BIT_SHIFT_SYS_EEPROM_MD) |
| AnnaBridge | 167:e84263d55307 | 813 | |
| AnnaBridge | 167:e84263d55307 | 814 | #define BIT_SYS_AUTOLOAD_SUS BIT(5) |
| AnnaBridge | 167:e84263d55307 | 815 | #define BIT_SYS_EEPROM_SEL BIT(4) |
| AnnaBridge | 167:e84263d55307 | 816 | #define BIT_SYS_EEPROM_EECS BIT(3) |
| AnnaBridge | 167:e84263d55307 | 817 | #define BIT_SYS_EEPROM_EESK BIT(2) |
| AnnaBridge | 167:e84263d55307 | 818 | #define BIT_SYS_EEPROM_EEDI BIT(1) |
| AnnaBridge | 167:e84263d55307 | 819 | #define BIT_SYS_EEPROM_EEDO BIT(0) |
| AnnaBridge | 167:e84263d55307 | 820 | |
| AnnaBridge | 167:e84263d55307 | 821 | //2 REG_SYS_EEPROM_CTRL1 |
| AnnaBridge | 167:e84263d55307 | 822 | |
| AnnaBridge | 167:e84263d55307 | 823 | #define BIT_SHIFT_SYS_EEPROM_VPD 0 |
| AnnaBridge | 167:e84263d55307 | 824 | #define BIT_MASK_SYS_EEPROM_VPD 0xffffffffL |
| AnnaBridge | 167:e84263d55307 | 825 | #define BIT_SYS_EEPROM_VPD(x) (((x) & BIT_MASK_SYS_EEPROM_VPD) << BIT_SHIFT_SYS_EEPROM_VPD) |
| AnnaBridge | 167:e84263d55307 | 826 | |
| AnnaBridge | 167:e84263d55307 | 827 | |
| AnnaBridge | 167:e84263d55307 | 828 | //2 REG_SYS_EFUSE_CTRL |
| AnnaBridge | 167:e84263d55307 | 829 | #define BIT_SYS_EF_RWFLAG BIT(31) |
| AnnaBridge | 167:e84263d55307 | 830 | |
| AnnaBridge | 167:e84263d55307 | 831 | #define BIT_SHIFT_SYS_EF_PGPD 28 |
| AnnaBridge | 167:e84263d55307 | 832 | #define BIT_MASK_SYS_EF_PGPD 0x7 |
| AnnaBridge | 167:e84263d55307 | 833 | #define BIT_SYS_EF_PGPD(x) (((x) & BIT_MASK_SYS_EF_PGPD) << BIT_SHIFT_SYS_EF_PGPD) |
| AnnaBridge | 167:e84263d55307 | 834 | |
| AnnaBridge | 167:e84263d55307 | 835 | |
| AnnaBridge | 167:e84263d55307 | 836 | #define BIT_SHIFT_SYS_EF_RDT 24 |
| AnnaBridge | 167:e84263d55307 | 837 | #define BIT_MASK_SYS_EF_RDT 0xf |
| AnnaBridge | 167:e84263d55307 | 838 | #define BIT_SYS_EF_RDT(x) (((x) & BIT_MASK_SYS_EF_RDT) << BIT_SHIFT_SYS_EF_RDT) |
| AnnaBridge | 167:e84263d55307 | 839 | |
| AnnaBridge | 167:e84263d55307 | 840 | |
| AnnaBridge | 167:e84263d55307 | 841 | #define BIT_SHIFT_SYS_EF_PGTS 20 |
| AnnaBridge | 167:e84263d55307 | 842 | #define BIT_MASK_SYS_EF_PGTS 0xf |
| AnnaBridge | 167:e84263d55307 | 843 | #define BIT_SYS_EF_PGTS(x) (((x) & BIT_MASK_SYS_EF_PGTS) << BIT_SHIFT_SYS_EF_PGTS) |
| AnnaBridge | 167:e84263d55307 | 844 | |
| AnnaBridge | 167:e84263d55307 | 845 | #define BIT_SYS_EF_PDWN BIT(19) |
| AnnaBridge | 167:e84263d55307 | 846 | #define BIT_SYS_EF_ALDEN BIT(18) |
| AnnaBridge | 167:e84263d55307 | 847 | |
| AnnaBridge | 167:e84263d55307 | 848 | #define BIT_SHIFT_SYS_EF_ADDR 8 |
| AnnaBridge | 167:e84263d55307 | 849 | #define BIT_MASK_SYS_EF_ADDR 0x3ff |
| AnnaBridge | 167:e84263d55307 | 850 | #define BIT_SYS_EF_ADDR(x) (((x) & BIT_MASK_SYS_EF_ADDR) << BIT_SHIFT_SYS_EF_ADDR) |
| AnnaBridge | 167:e84263d55307 | 851 | |
| AnnaBridge | 167:e84263d55307 | 852 | |
| AnnaBridge | 167:e84263d55307 | 853 | #define BIT_SHIFT_SYS_EF_DATA 0 |
| AnnaBridge | 167:e84263d55307 | 854 | #define BIT_MASK_SYS_EF_DATA 0xff |
| AnnaBridge | 167:e84263d55307 | 855 | #define BIT_SYS_EF_DATA(x) (((x) & BIT_MASK_SYS_EF_DATA) << BIT_SHIFT_SYS_EF_DATA) |
| AnnaBridge | 167:e84263d55307 | 856 | |
| AnnaBridge | 167:e84263d55307 | 857 | |
| AnnaBridge | 167:e84263d55307 | 858 | //2 REG_SYS_EFUSE_TEST |
| AnnaBridge | 167:e84263d55307 | 859 | #define BIT_SYS_EF_CRES_SEL BIT(26) |
| AnnaBridge | 167:e84263d55307 | 860 | |
| AnnaBridge | 167:e84263d55307 | 861 | #define BIT_SHIFT_SYS_EF_SCAN_START 16 |
| AnnaBridge | 167:e84263d55307 | 862 | #define BIT_MASK_SYS_EF_SCAN_START 0x1ff |
| AnnaBridge | 167:e84263d55307 | 863 | #define BIT_SYS_EF_SCAN_START(x) (((x) & BIT_MASK_SYS_EF_SCAN_START) << BIT_SHIFT_SYS_EF_SCAN_START) |
| AnnaBridge | 167:e84263d55307 | 864 | |
| AnnaBridge | 167:e84263d55307 | 865 | |
| AnnaBridge | 167:e84263d55307 | 866 | #define BIT_SHIFT_SYS_EF_SCAN_END 12 |
| AnnaBridge | 167:e84263d55307 | 867 | #define BIT_MASK_SYS_EF_SCAN_END 0xf |
| AnnaBridge | 167:e84263d55307 | 868 | #define BIT_SYS_EF_SCAN_END(x) (((x) & BIT_MASK_SYS_EF_SCAN_END) << BIT_SHIFT_SYS_EF_SCAN_END) |
| AnnaBridge | 167:e84263d55307 | 869 | |
| AnnaBridge | 167:e84263d55307 | 870 | #define BIT_SYS_EF_FORCE_PGMEN BIT(11) |
| AnnaBridge | 167:e84263d55307 | 871 | |
| AnnaBridge | 167:e84263d55307 | 872 | #define BIT_SHIFT_SYS_EF_CELL_SEL 8 |
| AnnaBridge | 167:e84263d55307 | 873 | #define BIT_MASK_SYS_EF_CELL_SEL 0x3 |
| AnnaBridge | 167:e84263d55307 | 874 | #define BIT_SYS_EF_CELL_SEL(x) (((x) & BIT_MASK_SYS_EF_CELL_SEL) << BIT_SHIFT_SYS_EF_CELL_SEL) |
| AnnaBridge | 167:e84263d55307 | 875 | |
| AnnaBridge | 167:e84263d55307 | 876 | #define BIT_SYS_EF_TRPT BIT(7) |
| AnnaBridge | 167:e84263d55307 | 877 | |
| AnnaBridge | 167:e84263d55307 | 878 | #define BIT_SHIFT_SYS_EF_SCAN_TTHD 0 |
| AnnaBridge | 167:e84263d55307 | 879 | #define BIT_MASK_SYS_EF_SCAN_TTHD 0x7f |
| AnnaBridge | 167:e84263d55307 | 880 | #define BIT_SYS_EF_SCAN_TTHD(x) (((x) & BIT_MASK_SYS_EF_SCAN_TTHD) << BIT_SHIFT_SYS_EF_SCAN_TTHD) |
| AnnaBridge | 167:e84263d55307 | 881 | |
| AnnaBridge | 167:e84263d55307 | 882 | |
| AnnaBridge | 167:e84263d55307 | 883 | //2 REG_SYS_DSTBY_INFO0 |
| AnnaBridge | 167:e84263d55307 | 884 | |
| AnnaBridge | 167:e84263d55307 | 885 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 886 | |
| AnnaBridge | 167:e84263d55307 | 887 | //2 REG_SYS_DSTBY_INFO1 |
| AnnaBridge | 167:e84263d55307 | 888 | |
| AnnaBridge | 167:e84263d55307 | 889 | //2 REG_SYS_DSTBY_INFO2 |
| AnnaBridge | 167:e84263d55307 | 890 | |
| AnnaBridge | 167:e84263d55307 | 891 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 892 | |
| AnnaBridge | 167:e84263d55307 | 893 | //2 REG_SYS_DSTBY_INFO3 |
| AnnaBridge | 167:e84263d55307 | 894 | |
| AnnaBridge | 167:e84263d55307 | 895 | //2 REG_SYS_SLP_WAKE_EVENT_MSK0 |
| AnnaBridge | 167:e84263d55307 | 896 | #define BIT_SYSON_WEVT_GPIO_DSTBY_MSK BIT(29) |
| AnnaBridge | 167:e84263d55307 | 897 | #define BIT_SYSON_WEVT_A33_MSK BIT(28) |
| AnnaBridge | 167:e84263d55307 | 898 | #define BIT_SYSON_WEVT_ADC_MSK BIT(26) |
| AnnaBridge | 167:e84263d55307 | 899 | #define BIT_SYSON_WEVT_I2C_MSK BIT(24) |
| AnnaBridge | 167:e84263d55307 | 900 | #define BIT_SYSON_WEVT_SPI_MSK BIT(22) |
| AnnaBridge | 167:e84263d55307 | 901 | #define BIT_SYSON_WEVT_UART_MSK BIT(20) |
| AnnaBridge | 167:e84263d55307 | 902 | #define BIT_SYSON_WEVT_USB_MSK BIT(16) |
| AnnaBridge | 167:e84263d55307 | 903 | #define BIT_SYSON_WEVT_SDIO_MSK BIT(14) |
| AnnaBridge | 167:e84263d55307 | 904 | #define BIT_SYSON_WEVT_NFC_MSK BIT(9) |
| AnnaBridge | 167:e84263d55307 | 905 | #define BIT_SYSON_WEVT_WLAN_MSK BIT(8) |
| AnnaBridge | 167:e84263d55307 | 906 | #define BIT_SYSON_WEVT_GPIO_MSK BIT(4) |
| AnnaBridge | 167:e84263d55307 | 907 | #define BIT_SYSON_WEVT_CHIP_EN_MSK BIT(3) |
| AnnaBridge | 167:e84263d55307 | 908 | #define BIT_SYSON_WEVT_OVER_CURRENT_MSK BIT(2) |
| AnnaBridge | 167:e84263d55307 | 909 | #define BIT_SYSON_WEVT_GTIM_MSK BIT(1) |
| AnnaBridge | 167:e84263d55307 | 910 | #define BIT_SYSON_WEVT_SYSTIM_MSK BIT(0) |
| AnnaBridge | 167:e84263d55307 | 911 | |
| AnnaBridge | 167:e84263d55307 | 912 | //2 REG_SYS_SLP_WAKE_EVENT_MSK1 |
| AnnaBridge | 167:e84263d55307 | 913 | |
| AnnaBridge | 167:e84263d55307 | 914 | //2 REG_SYS_SLP_WAKE_EVENT_STATUS0 |
| AnnaBridge | 167:e84263d55307 | 915 | #define BIT_SYSON_WEVT_GPIO_DSTBY_STS BIT(29) |
| AnnaBridge | 167:e84263d55307 | 916 | #define BIT_SYSON_WEVT_A33_STS BIT(28) |
| AnnaBridge | 167:e84263d55307 | 917 | #define BIT_SYSON_WEVT_ADC_STS BIT(26) |
| AnnaBridge | 167:e84263d55307 | 918 | #define BIT_SYSON_WEVT_I2C_STS BIT(24) |
| AnnaBridge | 167:e84263d55307 | 919 | #define BIT_SYSON_WEVT_SPI_STS BIT(22) |
| AnnaBridge | 167:e84263d55307 | 920 | #define BIT_SYSON_WEVT_UART_STS BIT(20) |
| AnnaBridge | 167:e84263d55307 | 921 | #define BIT_SYSON_WEVT_USB_STS BIT(16) |
| AnnaBridge | 167:e84263d55307 | 922 | #define BIT_SYSON_WEVT_SDIO_STS BIT(14) |
| AnnaBridge | 167:e84263d55307 | 923 | #define BIT_SYSON_WEVT_NFC_STS BIT(9) |
| AnnaBridge | 167:e84263d55307 | 924 | #define BIT_SYSON_WEVT_WLAN_STS BIT(8) |
| AnnaBridge | 167:e84263d55307 | 925 | #define BIT_SYSON_WEVT_GPIO_STS BIT(4) |
| AnnaBridge | 167:e84263d55307 | 926 | #define BIT_SYSON_WEVT_CHIP_EN_STS BIT(3) |
| AnnaBridge | 167:e84263d55307 | 927 | #define BIT_SYSON_WEVT_OVER_CURRENT_STS BIT(2) |
| AnnaBridge | 167:e84263d55307 | 928 | #define BIT_SYSON_WEVT_GTIM_STS BIT(1) |
| AnnaBridge | 167:e84263d55307 | 929 | #define BIT_SYSON_WEVT_SYSTIM_STS BIT(0) |
| AnnaBridge | 167:e84263d55307 | 930 | |
| AnnaBridge | 167:e84263d55307 | 931 | //2 REG_SYS_SLP_WAKE_EVENT_STATUS1 |
| AnnaBridge | 167:e84263d55307 | 932 | |
| AnnaBridge | 167:e84263d55307 | 933 | //2 REG_SYS_SNF_WAKE_EVENT_MSK0 |
| AnnaBridge | 167:e84263d55307 | 934 | |
| AnnaBridge | 167:e84263d55307 | 935 | #define BIT_SHIFT_SYS_WKPERI_IMR0 1 |
| AnnaBridge | 167:e84263d55307 | 936 | #define BIT_MASK_SYS_WKPERI_IMR0 0x7fffffffL |
| AnnaBridge | 167:e84263d55307 | 937 | #define BIT_SYS_WKPERI_IMR0(x) (((x) & BIT_MASK_SYS_WKPERI_IMR0) << BIT_SHIFT_SYS_WKPERI_IMR0) |
| AnnaBridge | 167:e84263d55307 | 938 | |
| AnnaBridge | 167:e84263d55307 | 939 | #define BIT_SYSON_SNFEVT_ADC_MSK BIT(0) |
| AnnaBridge | 167:e84263d55307 | 940 | |
| AnnaBridge | 167:e84263d55307 | 941 | //2 REG_SYS_SNF_WAKE_EVENT_STATUS |
| AnnaBridge | 167:e84263d55307 | 942 | |
| AnnaBridge | 167:e84263d55307 | 943 | #define BIT_SHIFT_SYS_WKPERI_ISR0 1 |
| AnnaBridge | 167:e84263d55307 | 944 | #define BIT_MASK_SYS_WKPERI_ISR0 0x7fffffffL |
| AnnaBridge | 167:e84263d55307 | 945 | #define BIT_SYS_WKPERI_ISR0(x) (((x) & BIT_MASK_SYS_WKPERI_ISR0) << BIT_SHIFT_SYS_WKPERI_ISR0) |
| AnnaBridge | 167:e84263d55307 | 946 | |
| AnnaBridge | 167:e84263d55307 | 947 | #define BIT_SYSON_SNFEVT_ADC_STS BIT(0) |
| AnnaBridge | 167:e84263d55307 | 948 | |
| AnnaBridge | 167:e84263d55307 | 949 | //2 REG_SYS_PWRMGT_CTRL |
| AnnaBridge | 167:e84263d55307 | 950 | #define BIT_SYSON_REGU_DSLP BIT(7) |
| AnnaBridge | 167:e84263d55307 | 951 | |
| AnnaBridge | 167:e84263d55307 | 952 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 953 | #define BIT_SYSON_PM_CMD_SLP BIT(2) |
| AnnaBridge | 167:e84263d55307 | 954 | #define BIT_SYSON_PM_CMD_DSTBY BIT(1) |
| AnnaBridge | 167:e84263d55307 | 955 | #define BIT_SYSON_PM_CMD_DSLP BIT(0) |
| AnnaBridge | 167:e84263d55307 | 956 | |
| AnnaBridge | 167:e84263d55307 | 957 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 958 | |
| AnnaBridge | 167:e84263d55307 | 959 | //2 REG_SYS_PWRMGT_OPTION |
| AnnaBridge | 167:e84263d55307 | 960 | #define BIT_SYSON_PMOPT_NORM_SYSCLK_SEL BIT(30) |
| AnnaBridge | 167:e84263d55307 | 961 | #define BIT_SYSON_PMOPT_NORM_SYSPLL_EN BIT(29) |
| AnnaBridge | 167:e84263d55307 | 962 | #define BIT_SYSON_PMOPT_NORM_XTAL_EN BIT(28) |
| AnnaBridge | 167:e84263d55307 | 963 | #define BIT_SYSON_PMOPT_NORM_EN_SOC BIT(27) |
| AnnaBridge | 167:e84263d55307 | 964 | #define BIT_SYSON_PMOPT_NORM_EN_PWM BIT(26) |
| AnnaBridge | 167:e84263d55307 | 965 | #define BIT_SYSON_PMOPT_NORM_EN_SWR BIT(25) |
| AnnaBridge | 167:e84263d55307 | 966 | #define BIT_SYSON_PMOPT_NORM_LPLDO_SEL BIT(24) |
| AnnaBridge | 167:e84263d55307 | 967 | #define BIT_SYSON_PMOPT_SNZ_SYSCLK_SEL BIT(22) |
| AnnaBridge | 167:e84263d55307 | 968 | #define BIT_SYSON_PMOPT_SNZ_SYSPLL_EN BIT(21) |
| AnnaBridge | 167:e84263d55307 | 969 | #define BIT_SYSON_PMOPT_SNZ_XTAL_EN BIT(20) |
| AnnaBridge | 167:e84263d55307 | 970 | #define BIT_SYSON_PMOPT_SNZ_EN_SOC BIT(19) |
| AnnaBridge | 167:e84263d55307 | 971 | #define BIT_SYSON_PMOPT_SNZ_EN_PWM BIT(18) |
| AnnaBridge | 167:e84263d55307 | 972 | #define BIT_SYSON_PMOPT_SNZ_EN_SWR BIT(17) |
| AnnaBridge | 167:e84263d55307 | 973 | #define BIT_SYSON_PMOPT_SNZ_LPLDO_SEL BIT(16) |
| AnnaBridge | 167:e84263d55307 | 974 | #define BIT_SYSON_PMOPT_SLP_SYSCLK_SEL BIT(14) |
| AnnaBridge | 167:e84263d55307 | 975 | #define BIT_SYSON_PMOPT_SLP_SYSPLL_EN BIT(13) |
| AnnaBridge | 167:e84263d55307 | 976 | #define BIT_SYSON_PMOPT_SLP_XTAL_EN BIT(12) |
| AnnaBridge | 167:e84263d55307 | 977 | #define BIT_SYSON_PMOPT_SLP_EN_SOC BIT(11) |
| AnnaBridge | 167:e84263d55307 | 978 | #define BIT_SYSON_PMOPT_SLP_EN_PWM BIT(10) |
| AnnaBridge | 167:e84263d55307 | 979 | #define BIT_SYSON_PMOPT_SLP_EN_SWR BIT(9) |
| AnnaBridge | 167:e84263d55307 | 980 | #define BIT_SYSON_PMOPT_SLP_LPLDO_SEL BIT(8) |
| AnnaBridge | 167:e84263d55307 | 981 | #define BIT_SYSON_PMOPT_DSTBY_SYSCLK_SEL BIT(6) |
| AnnaBridge | 167:e84263d55307 | 982 | #define BIT_SYSON_PMOPT_DSTBY_SYSPLL_EN BIT(5) |
| AnnaBridge | 167:e84263d55307 | 983 | #define BIT_SYSON_PMOPT_DSTBY_XTAL_EN BIT(4) |
| AnnaBridge | 167:e84263d55307 | 984 | #define BIT_SYSON_PMOPT_DSTBY_EN_SOC BIT(3) |
| AnnaBridge | 167:e84263d55307 | 985 | #define BIT_SYSON_PMOPT_DSTBY_EN_PWM BIT(2) |
| AnnaBridge | 167:e84263d55307 | 986 | #define BIT_SYSON_PMOPT_DSTBY_EN_SWR BIT(1) |
| AnnaBridge | 167:e84263d55307 | 987 | #define BIT_SYSON_PMOPT_DSTBY_LPLDO_SEL BIT(0) |
| AnnaBridge | 167:e84263d55307 | 988 | |
| AnnaBridge | 167:e84263d55307 | 989 | //2 REG_SYS_PWRMGT_OPTION_EXT |
| AnnaBridge | 167:e84263d55307 | 990 | #define BIT_SYSON_PMOPT_SLP_ANACK_SEL BIT(2) |
| AnnaBridge | 167:e84263d55307 | 991 | #define BIT_SYSON_PMOPT_SLP_ANACK_EN BIT(1) |
| AnnaBridge | 167:e84263d55307 | 992 | #define BIT_SYSON_PMOPT_SLP_SWR_ADJ BIT(0) |
| AnnaBridge | 167:e84263d55307 | 993 | |
| AnnaBridge | 167:e84263d55307 | 994 | //2 REG_SYS_DSLP_WEVENT |
| AnnaBridge | 167:e84263d55307 | 995 | #define BIT_SYSON_DSLP_GPIO BIT(2) |
| AnnaBridge | 167:e84263d55307 | 996 | #define BIT_SYSON_DSLP_NFC BIT(1) |
| AnnaBridge | 167:e84263d55307 | 997 | #define BIT_SYSON_DSLP_WTIMER33 BIT(0) |
| AnnaBridge | 167:e84263d55307 | 998 | |
| AnnaBridge | 167:e84263d55307 | 999 | //2 REG_SYS_PERI_MONITOR |
| AnnaBridge | 167:e84263d55307 | 1000 | #define BIT_SYSON_ISO33_NFC BIT(0) |
| AnnaBridge | 167:e84263d55307 | 1001 | |
| AnnaBridge | 167:e84263d55307 | 1002 | //2 REG_SYS_SYSTEM_CFG0 |
| AnnaBridge | 167:e84263d55307 | 1003 | #define BIT_SYSCFG_BD_PKG_SEL BIT(31) |
| AnnaBridge | 167:e84263d55307 | 1004 | |
| AnnaBridge | 167:e84263d55307 | 1005 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 1006 | |
| AnnaBridge | 167:e84263d55307 | 1007 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 1008 | |
| AnnaBridge | 167:e84263d55307 | 1009 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 1010 | |
| AnnaBridge | 167:e84263d55307 | 1011 | #define BIT_SHIFT_VENDOR_ID 8 |
| AnnaBridge | 167:e84263d55307 | 1012 | #define BIT_MASK_VENDOR_ID 0xf |
| AnnaBridge | 167:e84263d55307 | 1013 | #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) |
| AnnaBridge | 167:e84263d55307 | 1014 | |
| AnnaBridge | 167:e84263d55307 | 1015 | |
| AnnaBridge | 167:e84263d55307 | 1016 | #define BIT_SHIFT_CHIP_VER 4 |
| AnnaBridge | 167:e84263d55307 | 1017 | #define BIT_MASK_CHIP_VER 0xf |
| AnnaBridge | 167:e84263d55307 | 1018 | #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) |
| AnnaBridge | 167:e84263d55307 | 1019 | |
| AnnaBridge | 167:e84263d55307 | 1020 | |
| AnnaBridge | 167:e84263d55307 | 1021 | #define BIT_SHIFT_RF_RL_ID 0 |
| AnnaBridge | 167:e84263d55307 | 1022 | #define BIT_MASK_RF_RL_ID 0xf |
| AnnaBridge | 167:e84263d55307 | 1023 | #define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) |
| AnnaBridge | 167:e84263d55307 | 1024 | |
| AnnaBridge | 167:e84263d55307 | 1025 | |
| AnnaBridge | 167:e84263d55307 | 1026 | //2 REG_SYS_SYSTEM_CFG1 |
| AnnaBridge | 167:e84263d55307 | 1027 | |
| AnnaBridge | 167:e84263d55307 | 1028 | #define BIT_SHIFT_SYSCFG_TRP_ICFG 28 |
| AnnaBridge | 167:e84263d55307 | 1029 | #define BIT_MASK_SYSCFG_TRP_ICFG 0xf |
| AnnaBridge | 167:e84263d55307 | 1030 | #define BIT_SYSCFG_TRP_ICFG(x) (((x) & BIT_MASK_SYSCFG_TRP_ICFG) << BIT_SHIFT_SYSCFG_TRP_ICFG) |
| AnnaBridge | 167:e84263d55307 | 1031 | |
| AnnaBridge | 167:e84263d55307 | 1032 | #define BIT_SYSCFG_TRP_BOOT_SEL_ BIT(27) |
| AnnaBridge | 167:e84263d55307 | 1033 | #define BIT_SysCFG_TRP_SPSLDO_SEL BIT(26) |
| AnnaBridge | 167:e84263d55307 | 1034 | #define BIT_V15_VLD BIT(16) |
| AnnaBridge | 167:e84263d55307 | 1035 | #define BIT_SYS_SYSPLL_CLK_RDY BIT(9) |
| AnnaBridge | 167:e84263d55307 | 1036 | #define BIT_SYS_XCLK_VLD BIT(8) |
| AnnaBridge | 167:e84263d55307 | 1037 | #define BIT_SYSCFG_ALDN_STS BIT(0) |
| AnnaBridge | 167:e84263d55307 | 1038 | |
| AnnaBridge | 167:e84263d55307 | 1039 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 1040 | |
| AnnaBridge | 167:e84263d55307 | 1041 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 1042 | |
| AnnaBridge | 167:e84263d55307 | 1043 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 1044 | |
| AnnaBridge | 167:e84263d55307 | 1045 | //2 REG_RSVD |
| AnnaBridge | 167:e84263d55307 | 1046 | |
| AnnaBridge | 167:e84263d55307 | 1047 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 1048 | |
| AnnaBridge | 167:e84263d55307 | 1049 | //2 REG_NOT_VALID |
| AnnaBridge | 167:e84263d55307 | 1050 | |
| AnnaBridge | 167:e84263d55307 | 1051 | |
| AnnaBridge | 167:e84263d55307 | 1052 | //================= Register Address Definition =====================// |
| AnnaBridge | 167:e84263d55307 | 1053 | #define REG_SYS_PWR_CTRL 0x0000 |
| AnnaBridge | 167:e84263d55307 | 1054 | #define REG_SYS_ISO_CTRL 0x0002 |
| AnnaBridge | 167:e84263d55307 | 1055 | #define REG_SYS_FUNC_EN 0x0008 |
| AnnaBridge | 167:e84263d55307 | 1056 | #define REG_SYS_CLK_CTRL0 0x0010 |
| AnnaBridge | 167:e84263d55307 | 1057 | #define REG_SYS_CLK_CTRL1 0x0014 |
| AnnaBridge | 167:e84263d55307 | 1058 | #define REG_SYS_EFUSE_SYSCFG0 0x0020 |
| AnnaBridge | 167:e84263d55307 | 1059 | #define REG_SYS_EFUSE_SYSCFG1 0x0024 |
| AnnaBridge | 167:e84263d55307 | 1060 | #define REG_SYS_EFUSE_SYSCFG2 0x0028 |
| AnnaBridge | 167:e84263d55307 | 1061 | #define REG_SYS_EFUSE_SYSCFG3 0x002C |
| AnnaBridge | 167:e84263d55307 | 1062 | #define REG_SYS_EFUSE_SYSCFG4 0x0030 |
| AnnaBridge | 167:e84263d55307 | 1063 | #define REG_SYS_EFUSE_SYSCFG5 0x0034 |
| AnnaBridge | 167:e84263d55307 | 1064 | #define REG_SYS_EFUSE_SYSCFG6 0x0038 |
| AnnaBridge | 167:e84263d55307 | 1065 | #define REG_SYS_EFUSE_SYSCFG7 0x003C |
| AnnaBridge | 167:e84263d55307 | 1066 | #define REG_SYS_REGU_CTRL0 0x0040 |
| AnnaBridge | 167:e84263d55307 | 1067 | #define REG_SYS_SWR_CTRL0 0x0048 |
| AnnaBridge | 167:e84263d55307 | 1068 | #define REG_SYS_SWR_CTRL1 0x004C |
| AnnaBridge | 167:e84263d55307 | 1069 | #define REG_SYS_XTAL_CTRL0 0x0060 |
| AnnaBridge | 167:e84263d55307 | 1070 | #define REG_SYS_XTAL_CTRL1 0x0064 |
| AnnaBridge | 167:e84263d55307 | 1071 | #define REG_SYS_SYSPLL_CTRL0 0x0070 |
| AnnaBridge | 167:e84263d55307 | 1072 | #define REG_SYS_SYSPLL_CTRL1 0x0074 |
| AnnaBridge | 167:e84263d55307 | 1073 | #define REG_SYS_SYSPLL_CTRL2 0x0078 |
| AnnaBridge | 167:e84263d55307 | 1074 | #define REG_SYS_ANA_TIM_CTRL 0x0090 |
| AnnaBridge | 167:e84263d55307 | 1075 | #define REG_SYS_DSLP_TIM_CTRL 0x0094 |
| AnnaBridge | 167:e84263d55307 | 1076 | #define REG_SYS_DSLP_TIM_CAL_CTRL 0x0098 |
| AnnaBridge | 167:e84263d55307 | 1077 | #define REG_SYS_DEBUG_CTRL 0x00A0 |
| AnnaBridge | 167:e84263d55307 | 1078 | #define REG_SYS_PINMUX_CTRL 0x00A4 |
| AnnaBridge | 167:e84263d55307 | 1079 | #define REG_SYS_GPIO_DSTBY_WAKE_CTRL0 0x00A8 |
| AnnaBridge | 167:e84263d55307 | 1080 | #define REG_SYS_GPIO_DSTBY_WAKE_CTRL1 0x00AC |
| AnnaBridge | 167:e84263d55307 | 1081 | #define REG_SYS_DEBUG_REG 0x00BC |
| AnnaBridge | 167:e84263d55307 | 1082 | #define REG_SYS_EEPROM_CTRL0 0x00E0 |
| AnnaBridge | 167:e84263d55307 | 1083 | #define REG_SYS_EEPROM_CTRL1 0x00E4 |
| AnnaBridge | 167:e84263d55307 | 1084 | #define REG_SYS_EFUSE_CTRL 0x00E8 |
| AnnaBridge | 167:e84263d55307 | 1085 | #define REG_SYS_EFUSE_TEST 0x00EC |
| AnnaBridge | 167:e84263d55307 | 1086 | #define REG_SYS_DSTBY_INFO0 0x00F0 |
| AnnaBridge | 167:e84263d55307 | 1087 | #define REG_SYS_DSTBY_INFO1 0x00F4 |
| AnnaBridge | 167:e84263d55307 | 1088 | #define REG_SYS_DSTBY_INFO2 0x00F8 |
| AnnaBridge | 167:e84263d55307 | 1089 | #define REG_SYS_DSTBY_INFO3 0x00FC |
| AnnaBridge | 167:e84263d55307 | 1090 | #define REG_SYS_SLP_WAKE_EVENT_MSK0 0x0100 |
| AnnaBridge | 167:e84263d55307 | 1091 | #define REG_SYS_SLP_WAKE_EVENT_MSK1 0x0104 |
| AnnaBridge | 167:e84263d55307 | 1092 | #define REG_SYS_SLP_WAKE_EVENT_STATUS0 0x0108 |
| AnnaBridge | 167:e84263d55307 | 1093 | #define REG_SYS_SLP_WAKE_EVENT_STATUS1 0x010C |
| AnnaBridge | 167:e84263d55307 | 1094 | #define REG_SYS_SNF_WAKE_EVENT_MSK0 0x0110 |
| AnnaBridge | 167:e84263d55307 | 1095 | #define REG_SYS_SNF_WAKE_EVENT_STATUS 0x0114 |
| AnnaBridge | 167:e84263d55307 | 1096 | #define REG_SYS_PWRMGT_CTRL 0x0118 |
| AnnaBridge | 167:e84263d55307 | 1097 | #define REG_SYS_PWRMGT_OPTION 0x0120 |
| AnnaBridge | 167:e84263d55307 | 1098 | #define REG_SYS_PWRMGT_OPTION_EXT 0x0124 |
| AnnaBridge | 167:e84263d55307 | 1099 | #define REG_SYS_DSLP_WEVENT 0x0130 |
| AnnaBridge | 167:e84263d55307 | 1100 | #define REG_SYS_PERI_MONITOR 0x0134 |
| AnnaBridge | 167:e84263d55307 | 1101 | #define REG_SYS_SYSTEM_CFG0 0x01F0 |
| AnnaBridge | 167:e84263d55307 | 1102 | #define REG_SYS_SYSTEM_CFG1 0x01F4 |
| AnnaBridge | 167:e84263d55307 | 1103 | #define REG_SYS_SYSTEM_CFG2 0x01F8 |
| AnnaBridge | 167:e84263d55307 | 1104 | |
| AnnaBridge | 167:e84263d55307 | 1105 | #endif |