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targets/TARGET_Maxim/TARGET_MAX32630/device/maa_regs.h@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
157:ff67d9f36b67 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 *
<> 157:ff67d9f36b67 38 * $Date: 2016-10-10 19:20:13 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 39 * $Revision: 24665 $
<> 157:ff67d9f36b67 40 *
<> 157:ff67d9f36b67 41 *************************************************************************** */
<> 157:ff67d9f36b67 42
<> 157:ff67d9f36b67 43 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 44 #ifndef _MXC_MAA_REGS_H_
<> 157:ff67d9f36b67 45 #define _MXC_MAA_REGS_H_
<> 157:ff67d9f36b67 46
<> 157:ff67d9f36b67 47 /* **** Includes **** */
<> 157:ff67d9f36b67 48 #include <stdint.h>
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 #ifdef __cplusplus
<> 157:ff67d9f36b67 51 extern "C" {
<> 157:ff67d9f36b67 52 #endif
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54 ///@cond
<> 157:ff67d9f36b67 55 /*
<> 157:ff67d9f36b67 56 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 57 */
<> 157:ff67d9f36b67 58 #ifndef __IO
<> 157:ff67d9f36b67 59 #define __IO volatile
<> 157:ff67d9f36b67 60 #endif
<> 157:ff67d9f36b67 61 #ifndef __I
<> 157:ff67d9f36b67 62 #define __I volatile const
<> 157:ff67d9f36b67 63 #endif
<> 157:ff67d9f36b67 64 #ifndef __O
<> 157:ff67d9f36b67 65 #define __O volatile
<> 157:ff67d9f36b67 66 #endif
<> 157:ff67d9f36b67 67 #ifndef __RO
<> 157:ff67d9f36b67 68 #define __RO volatile const
<> 157:ff67d9f36b67 69 #endif
<> 157:ff67d9f36b67 70 ///@endcond
<> 157:ff67d9f36b67 71
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73
<> 157:ff67d9f36b67 74 /**
<> 157:ff67d9f36b67 75 * @ingroup icc_registers
<> 157:ff67d9f36b67 76 * @defgroup maa_registers Registers
<> 157:ff67d9f36b67 77 * @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module.
<> 157:ff67d9f36b67 78 x * @{
<> 157:ff67d9f36b67 79 */
<> 157:ff67d9f36b67 80
<> 157:ff67d9f36b67 81 /**
<> 157:ff67d9f36b67 82 * Structure type to access the MAA Peripheral Module Registers.
<> 157:ff67d9f36b67 83 */
<> 157:ff67d9f36b67 84 typedef struct {
<> 157:ff67d9f36b67 85 __IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> MAA_CTRL - MAA Control, Configuration and Status */
<> 157:ff67d9f36b67 86 __IO uint32_t maws; /**< <tt>\b 0x0004</tt> MAA_MAWS - MAA Word (Operand) Size, Big/Little Endian Mode Select */
<> 157:ff67d9f36b67 87 } mxc_maa_regs_t;
<> 157:ff67d9f36b67 88 /**@} end of maa_registers group */
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90
<> 157:ff67d9f36b67 91 /**
<> 157:ff67d9f36b67 92 * @ingroup maa
<> 157:ff67d9f36b67 93 * @defgroup maa_mem_segments Memory Segment Registers
<> 157:ff67d9f36b67 94 * @brief Registers, Bit Masks and Bit Positions for the MAA Memory Mapped Segments
<> 157:ff67d9f36b67 95 * @{
<> 157:ff67d9f36b67 96 */
<> 157:ff67d9f36b67 97 /**
<> 157:ff67d9f36b67 98 * Structure type to access the MAA Peripheral Module Memory Mapped Registers.
<> 157:ff67d9f36b67 99 */
<> 157:ff67d9f36b67 100 typedef struct {
<> 157:ff67d9f36b67 101 __IO uint32_t seg0[32]; /* 0x0000-0x007C [128 bytes] MAA Memory Segment 0 */
<> 157:ff67d9f36b67 102 __IO uint32_t seg1[32]; /* 0x0080-0x00FC [128 bytes] MAA Memory Segment 1 */
<> 157:ff67d9f36b67 103 __IO uint32_t seg2[32]; /* 0x0100-0x017C [128 bytes] MAA Memory Segment 2 */
<> 157:ff67d9f36b67 104 __IO uint32_t seg3[32]; /* 0x0180-0x01FC [128 bytes] MAA Memory Segment 3 */
<> 157:ff67d9f36b67 105 __IO uint32_t seg4[32]; /* 0x0200-0x027C [128 bytes] MAA Memory Segment 4 */
<> 157:ff67d9f36b67 106 __IO uint32_t seg5[32]; /* 0x0280-0x02FC [128 bytes] MAA Memory Segment 5 */
<> 157:ff67d9f36b67 107 } mxc_maa_mem_regs_t;
<> 157:ff67d9f36b67 108 /**@} end of maa_mem_segments group */
<> 157:ff67d9f36b67 109
<> 157:ff67d9f36b67 110 /**
<> 157:ff67d9f36b67 111 * @ingroup maa_registers
<> 157:ff67d9f36b67 112 * @defgroup MAA_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 113 * @brief MAA Register Offsets from the MAA Peripheral Module Base Address.
<> 157:ff67d9f36b67 114 * @{
<> 157:ff67d9f36b67 115 */
<> 157:ff67d9f36b67 116 #define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 117 #define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) /**< Offset from MAA Base Peripheral Address: <tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 118 /**@} end of group MAA_Register_Offsets */
<> 157:ff67d9f36b67 119 /**
<> 157:ff67d9f36b67 120 * @ingroup maa_mem_segments
<> 157:ff67d9f36b67 121 * @defgroup MAA_Register_Mem_Offsets Register Offsets
<> 157:ff67d9f36b67 122 * @brief MAA Memory Mapped Register Offsets from the MAA Peripheral Module Base Memory Mapped Address.
<> 157:ff67d9f36b67 123 * @{
<> 157:ff67d9f36b67 124 */
<> 157:ff67d9f36b67 125 #define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 126 #define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000080UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0080</tt> */
<> 157:ff67d9f36b67 127 #define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000100UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0100</tt> */
<> 157:ff67d9f36b67 128 #define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x00000180UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0180</tt> */
<> 157:ff67d9f36b67 129 #define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000200UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0200</tt> */
<> 157:ff67d9f36b67 130 #define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000280UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0280</tt> */
<> 157:ff67d9f36b67 131 /**@} end of group MAA_Register_Mem_Offsets */
<> 157:ff67d9f36b67 132
<> 157:ff67d9f36b67 133 /*
<> 157:ff67d9f36b67 134 Field positions and masks for module MAA.
<> 157:ff67d9f36b67 135 */
<> 157:ff67d9f36b67 136 /**
<> 157:ff67d9f36b67 137 * @ingroup maa_registers
<> 157:ff67d9f36b67 138 * @defgroup maa_ctrl MAA_CTRL
<> 157:ff67d9f36b67 139 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 140 */
<> 157:ff67d9f36b67 141 #define MXC_F_MAA_CTRL_START_POS 0 /**< START Position */
<> 157:ff67d9f36b67 142 #define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) /**< START Mask */
<> 157:ff67d9f36b67 143 #define MXC_F_MAA_CTRL_OPSEL_POS 1 /**< OPSEL Position */
<> 157:ff67d9f36b67 144 #define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< OPSEL Mask */
<> 157:ff67d9f36b67 145 #define MXC_F_MAA_CTRL_OCALC_POS 4 /**< OCALC Position */
<> 157:ff67d9f36b67 146 #define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) /**< OCALC Mask */
<> 157:ff67d9f36b67 147 #define MXC_F_MAA_CTRL_IF_DONE_POS 5 /**< IF_DONE Position */
<> 157:ff67d9f36b67 148 #define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) /**< IF_DONE Mask */
<> 157:ff67d9f36b67 149 #define MXC_F_MAA_CTRL_INTEN_POS 6 /**< INTEN Position */
<> 157:ff67d9f36b67 150 #define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) /**< INTEN Mask */
<> 157:ff67d9f36b67 151 #define MXC_F_MAA_CTRL_IF_ERROR_POS 7 /**< IF_ERROR Position */
<> 157:ff67d9f36b67 152 #define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) /**< IF_ERROR Mask */
<> 157:ff67d9f36b67 153 #define MXC_F_MAA_CTRL_OFS_A_POS 8 /**< OFS_A Position */
<> 157:ff67d9f36b67 154 #define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) /**< OFS_A Mask */
<> 157:ff67d9f36b67 155 #define MXC_F_MAA_CTRL_OFS_B_POS 10 /**< OFS_B Position */
<> 157:ff67d9f36b67 156 #define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) /**< OFS_B Mask */
<> 157:ff67d9f36b67 157 #define MXC_F_MAA_CTRL_OFS_EXP_POS 12 /**< OFS_EXP Position */
<> 157:ff67d9f36b67 158 #define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) /**< OFS_EXP Mask */
<> 157:ff67d9f36b67 159 #define MXC_F_MAA_CTRL_OFS_MOD_POS 14 /**< OFS_MOD Position */
<> 157:ff67d9f36b67 160 #define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) /**< OFS_MOD Mask */
<> 157:ff67d9f36b67 161 #define MXC_F_MAA_CTRL_SEG_A_POS 16 /**< SEG_A Position */
<> 157:ff67d9f36b67 162 #define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) /**< SEG_A Mask */
<> 157:ff67d9f36b67 163 #define MXC_F_MAA_CTRL_SEG_B_POS 20 /**< SEG_B Position */
<> 157:ff67d9f36b67 164 #define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) /**< SEG_B Mask */
<> 157:ff67d9f36b67 165 #define MXC_F_MAA_CTRL_SEG_RES_POS 24 /**< SEG_RES Position */
<> 157:ff67d9f36b67 166 #define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) /**< SEG_RES Mask */
<> 157:ff67d9f36b67 167 #define MXC_F_MAA_CTRL_SEG_TMP_POS 28 /**< SEG_TMP Position */
<> 157:ff67d9f36b67 168 #define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) /**< SEG_TMP Mask */
<> 157:ff67d9f36b67 169 /**@} end of maa_ctrl group */
<> 157:ff67d9f36b67 170
<> 157:ff67d9f36b67 171 /**
<> 157:ff67d9f36b67 172 * @ingroup maa_registers
<> 157:ff67d9f36b67 173 * @defgroup maa_maws MAA_MAWS
<> 157:ff67d9f36b67 174 * @brief Field Positions and Masks
<> 157:ff67d9f36b67 175 */
<> 157:ff67d9f36b67 176 #define MXC_F_MAA_MAWS_MODLEN_POS 0 /**< MODLEN Position */
<> 157:ff67d9f36b67 177 #define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000007FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) /**< MODLEN Mask */
<> 157:ff67d9f36b67 178 #define MXC_F_MAA_MAWS_BYTESWAP_POS 15 /**< BYTESWAP Position */
<> 157:ff67d9f36b67 179 #define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) /**< BYTESWAP Mask */
<> 157:ff67d9f36b67 180 /**@} end of group MAA_MAWS */
<> 157:ff67d9f36b67 181
<> 157:ff67d9f36b67 182
<> 157:ff67d9f36b67 183 /*
<> 157:ff67d9f36b67 184 Field values and shifted values for module MAA.
<> 157:ff67d9f36b67 185 */
<> 157:ff67d9f36b67 186 /**
<> 157:ff67d9f36b67 187 * @ingroup maa_ctrl
<> 157:ff67d9f36b67 188 * @defgroup maa_oppsel MAA_OPSEL
<> 157:ff67d9f36b67 189 * @brief MAA Operation Select - Field Values and Shifted Field Values.
<> 157:ff67d9f36b67 190 */
<> 157:ff67d9f36b67 191 #define MXC_V_MAA_OPSEL_EXP ((uint32_t)(0x00000000UL)) /**< Field Value: OPSEL_EXP */
<> 157:ff67d9f36b67 192 #define MXC_V_MAA_OPSEL_SQR ((uint32_t)(0x00000001UL)) /**< Field Value: OPSEL_SQR */
<> 157:ff67d9f36b67 193 #define MXC_V_MAA_OPSEL_MUL ((uint32_t)(0x00000002UL)) /**< Field Value: OPSEL_MUL */
<> 157:ff67d9f36b67 194 #define MXC_V_MAA_OPSEL_SQRMUL ((uint32_t)(0x00000003UL)) /**< Field Value: OPSEL_SQRMUL */
<> 157:ff67d9f36b67 195 #define MXC_V_MAA_OPSEL_ADD ((uint32_t)(0x00000004UL)) /**< Field Value: OPSEL_ADD */
<> 157:ff67d9f36b67 196 #define MXC_V_MAA_OPSEL_SUB ((uint32_t)(0x00000005UL)) /**< Field Value: OPSEL_SUB */
<> 157:ff67d9f36b67 197
<> 157:ff67d9f36b67 198 #define MXC_S_MAA_OPSEL_EXP ((uint32_t)(MXC_V_MAA_OPSEL_EXP << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_EXP */
<> 157:ff67d9f36b67 199 #define MXC_S_MAA_OPSEL_SQR ((uint32_t)(MXC_V_MAA_OPSEL_SQR << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQR */
<> 157:ff67d9f36b67 200 #define MXC_S_MAA_OPSEL_MUL ((uint32_t)(MXC_V_MAA_OPSEL_MUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_MUL */
<> 157:ff67d9f36b67 201 #define MXC_S_MAA_OPSEL_SQRMUL ((uint32_t)(MXC_V_MAA_OPSEL_SQRMUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQRMUL */
<> 157:ff67d9f36b67 202 #define MXC_S_MAA_OPSEL_ADD ((uint32_t)(MXC_V_MAA_OPSEL_ADD << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_ADD */
<> 157:ff67d9f36b67 203 #define MXC_S_MAA_OPSEL_SUB ((uint32_t)(MXC_V_MAA_OPSEL_SUB << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SUB */
<> 157:ff67d9f36b67 204 /**@} end of group maa_opsel_values */
<> 157:ff67d9f36b67 205
<> 157:ff67d9f36b67 206
<> 157:ff67d9f36b67 207 #ifdef __cplusplus
<> 157:ff67d9f36b67 208 }
<> 157:ff67d9f36b67 209 #endif
<> 157:ff67d9f36b67 210
<> 157:ff67d9f36b67 211 #endif /* _MXC_MAA_REGS_H_ */
<> 157:ff67d9f36b67 212