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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_rnga.c@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
154:37f96f9d4de2 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_rnga.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 #if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*******************************************************************************
<> 154:37f96f9d4de2 36 * Definitions
<> 154:37f96f9d4de2 37 *******************************************************************************/
<> 154:37f96f9d4de2 38
<> 154:37f96f9d4de2 39 /*******************************************************************************
<> 154:37f96f9d4de2 40 * RNG_CR - RNGA Control Register
<> 154:37f96f9d4de2 41 ******************************************************************************/
<> 154:37f96f9d4de2 42 /*!
<> 154:37f96f9d4de2 43 * @brief RNG_CR - RNGA Control Register (RW)
<> 154:37f96f9d4de2 44 *
<> 154:37f96f9d4de2 45 * Reset value: 0x00000000U
<> 154:37f96f9d4de2 46 *
<> 154:37f96f9d4de2 47 * Controls the operation of RNGA.
<> 154:37f96f9d4de2 48 */
<> 154:37f96f9d4de2 49 /*!
<> 154:37f96f9d4de2 50 * @name Constants and macros for entire RNG_CR register
<> 154:37f96f9d4de2 51 */
<> 154:37f96f9d4de2 52 /*@{*/
<> 154:37f96f9d4de2 53 #define RNG_CR_REG(base) ((base)->CR)
<> 154:37f96f9d4de2 54 #define RNG_RD_CR(base) (RNG_CR_REG(base))
<> 154:37f96f9d4de2 55 #define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value))
<> 154:37f96f9d4de2 56 #define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
<> 154:37f96f9d4de2 57 /*@}*/
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /*!
<> 154:37f96f9d4de2 60 * @name Register RNG_CR, field GO[0] (RW)
<> 154:37f96f9d4de2 61 *
<> 154:37f96f9d4de2 62 * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
<> 154:37f96f9d4de2 63 * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
<> 154:37f96f9d4de2 64 * OR[RANDOUT] with data.
<> 154:37f96f9d4de2 65 *
<> 154:37f96f9d4de2 66 * Values:
<> 154:37f96f9d4de2 67 * - 0b0 - Disabled
<> 154:37f96f9d4de2 68 * - 0b1 - Enabled
<> 154:37f96f9d4de2 69 */
<> 154:37f96f9d4de2 70 /*@{*/
<> 154:37f96f9d4de2 71 /*! @brief Read current value of the RNG_CR_GO field. */
<> 154:37f96f9d4de2 72 #define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
<> 154:37f96f9d4de2 73
<> 154:37f96f9d4de2 74 /*! @brief Set the GO field to a new value. */
<> 154:37f96f9d4de2 75 #define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
<> 154:37f96f9d4de2 76 /*@}*/
<> 154:37f96f9d4de2 77
<> 154:37f96f9d4de2 78 /*!
<> 154:37f96f9d4de2 79 * @name Register RNG_CR, field SLP[4] (RW)
<> 154:37f96f9d4de2 80 *
<> 154:37f96f9d4de2 81 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
<> 154:37f96f9d4de2 82 * mode by asserting the DOZE signal.
<> 154:37f96f9d4de2 83 *
<> 154:37f96f9d4de2 84 * Values:
<> 154:37f96f9d4de2 85 * - 0b0 - Normal mode
<> 154:37f96f9d4de2 86 * - 0b1 - Sleep (low-power) mode
<> 154:37f96f9d4de2 87 */
<> 154:37f96f9d4de2 88 /*@{*/
<> 154:37f96f9d4de2 89 /*! @brief Read current value of the RNG_CR_SLP field. */
<> 154:37f96f9d4de2 90 #define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
<> 154:37f96f9d4de2 91
<> 154:37f96f9d4de2 92 /*! @brief Set the SLP field to a new value. */
<> 154:37f96f9d4de2 93 #define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
<> 154:37f96f9d4de2 94 /*@}*/
<> 154:37f96f9d4de2 95
<> 154:37f96f9d4de2 96 /*******************************************************************************
<> 154:37f96f9d4de2 97 * RNG_SR - RNGA Status Register
<> 154:37f96f9d4de2 98 ******************************************************************************/
<> 154:37f96f9d4de2 99 #define RNG_SR_REG(base) ((base)->SR)
<> 154:37f96f9d4de2 100
<> 154:37f96f9d4de2 101 /*!
<> 154:37f96f9d4de2 102 * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
<> 154:37f96f9d4de2 103 *
<> 154:37f96f9d4de2 104 * Indicates the number of random-data words that are in OR[RANDOUT], which
<> 154:37f96f9d4de2 105 * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
<> 154:37f96f9d4de2 106 * is not 0, then the contents of a random number contained in OR[RANDOUT] are
<> 154:37f96f9d4de2 107 * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
<> 154:37f96f9d4de2 108 *
<> 154:37f96f9d4de2 109 * Values:
<> 154:37f96f9d4de2 110 * - 0b00000000 - No words (empty)
<> 154:37f96f9d4de2 111 * - 0b00000001 - One word (valid)
<> 154:37f96f9d4de2 112 */
<> 154:37f96f9d4de2 113 /*@{*/
<> 154:37f96f9d4de2 114 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
<> 154:37f96f9d4de2 115 #define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
<> 154:37f96f9d4de2 116 /*@}*/
<> 154:37f96f9d4de2 117
<> 154:37f96f9d4de2 118 /*!
<> 154:37f96f9d4de2 119 * @name Register RNG_SR, field SLP[4] (RO)
<> 154:37f96f9d4de2 120 *
<> 154:37f96f9d4de2 121 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
<> 154:37f96f9d4de2 122 * mode by asserting the DOZE signal.
<> 154:37f96f9d4de2 123 *
<> 154:37f96f9d4de2 124 * Values:
<> 154:37f96f9d4de2 125 * - 0b0 - Normal mode
<> 154:37f96f9d4de2 126 * - 0b1 - Sleep (low-power) mode
<> 154:37f96f9d4de2 127 */
<> 154:37f96f9d4de2 128 /*@{*/
<> 154:37f96f9d4de2 129 /*! @brief Read current value of the RNG_SR_SLP field. */
<> 154:37f96f9d4de2 130 #define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
<> 154:37f96f9d4de2 131 /*@}*/
<> 154:37f96f9d4de2 132
<> 154:37f96f9d4de2 133 /*******************************************************************************
<> 154:37f96f9d4de2 134 * RNG_OR - RNGA Output Register
<> 154:37f96f9d4de2 135 ******************************************************************************/
<> 154:37f96f9d4de2 136 /*!
<> 154:37f96f9d4de2 137 * @brief RNG_OR - RNGA Output Register (RO)
<> 154:37f96f9d4de2 138 *
<> 154:37f96f9d4de2 139 * Reset value: 0x00000000U
<> 154:37f96f9d4de2 140 *
<> 154:37f96f9d4de2 141 * Stores a random-data word generated by RNGA.
<> 154:37f96f9d4de2 142 */
<> 154:37f96f9d4de2 143 /*!
<> 154:37f96f9d4de2 144 * @name Constants and macros for entire RNG_OR register
<> 154:37f96f9d4de2 145 */
<> 154:37f96f9d4de2 146 /*@{*/
<> 154:37f96f9d4de2 147 #define RNG_OR_REG(base) ((base)->OR)
<> 154:37f96f9d4de2 148 #define RNG_RD_OR(base) (RNG_OR_REG(base))
<> 154:37f96f9d4de2 149 /*@}*/
<> 154:37f96f9d4de2 150
<> 154:37f96f9d4de2 151 /*******************************************************************************
<> 154:37f96f9d4de2 152 * RNG_ER - RNGA Entropy Register
<> 154:37f96f9d4de2 153 ******************************************************************************/
<> 154:37f96f9d4de2 154 /*!
<> 154:37f96f9d4de2 155 * @brief RNG_ER - RNGA Entropy Register (WORZ)
<> 154:37f96f9d4de2 156 *
<> 154:37f96f9d4de2 157 * Reset value: 0x00000000U
<> 154:37f96f9d4de2 158 *
<> 154:37f96f9d4de2 159 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
<> 154:37f96f9d4de2 160 * to seed its pseudorandom algorithm. This is a write-only register; reads
<> 154:37f96f9d4de2 161 * return all zeros.
<> 154:37f96f9d4de2 162 */
<> 154:37f96f9d4de2 163 /*!
<> 154:37f96f9d4de2 164 * @name Constants and macros for entire RNG_ER register
<> 154:37f96f9d4de2 165 */
<> 154:37f96f9d4de2 166 /*@{*/
<> 154:37f96f9d4de2 167 #define RNG_ER_REG(base) ((base)->ER)
<> 154:37f96f9d4de2 168 #define RNG_RD_ER(base) (RNG_ER_REG(base))
<> 154:37f96f9d4de2 169 #define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value))
<> 154:37f96f9d4de2 170 /*@}*/
<> 154:37f96f9d4de2 171
<> 154:37f96f9d4de2 172 /*******************************************************************************
<> 154:37f96f9d4de2 173 * Prototypes
<> 154:37f96f9d4de2 174 *******************************************************************************/
<> 154:37f96f9d4de2 175
<> 154:37f96f9d4de2 176 static uint32_t rnga_ReadEntropy(RNG_Type *base);
<> 154:37f96f9d4de2 177
<> 154:37f96f9d4de2 178 /*******************************************************************************
<> 154:37f96f9d4de2 179 * Code
<> 154:37f96f9d4de2 180 ******************************************************************************/
<> 154:37f96f9d4de2 181
<> 154:37f96f9d4de2 182 void RNGA_Init(RNG_Type *base)
<> 154:37f96f9d4de2 183 {
<> 154:37f96f9d4de2 184 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 185 /* Enable the clock gate. */
<> 154:37f96f9d4de2 186 CLOCK_EnableClock(kCLOCK_Rnga0);
<> 154:37f96f9d4de2 187 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 188 CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */
<> 154:37f96f9d4de2 189 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 190 CLOCK_EnableClock(kCLOCK_Rnga0);
<> 154:37f96f9d4de2 191 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 192
<> 154:37f96f9d4de2 193 /* Reset the registers for RNGA module to reset state. */
<> 154:37f96f9d4de2 194 RNG_WR_CR(base, 0);
<> 154:37f96f9d4de2 195 /* Enables the RNGA random data generation and loading.*/
<> 154:37f96f9d4de2 196 RNG_WR_CR_GO(base, 1);
<> 154:37f96f9d4de2 197 }
<> 154:37f96f9d4de2 198
<> 154:37f96f9d4de2 199 void RNGA_Deinit(RNG_Type *base)
<> 154:37f96f9d4de2 200 {
<> 154:37f96f9d4de2 201 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 202 /* Disable the clock for RNGA module.*/
<> 154:37f96f9d4de2 203 CLOCK_DisableClock(kCLOCK_Rnga0);
<> 154:37f96f9d4de2 204 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 205 }
<> 154:37f96f9d4de2 206
<> 154:37f96f9d4de2 207 /*!
<> 154:37f96f9d4de2 208 * @brief Get a random data from RNGA.
<> 154:37f96f9d4de2 209 *
<> 154:37f96f9d4de2 210 * @param base RNGA base address
<> 154:37f96f9d4de2 211 */
<> 154:37f96f9d4de2 212 static uint32_t rnga_ReadEntropy(RNG_Type *base)
<> 154:37f96f9d4de2 213 {
<> 154:37f96f9d4de2 214 uint32_t data = 0;
<> 154:37f96f9d4de2 215 if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/
<> 154:37f96f9d4de2 216 {
<> 154:37f96f9d4de2 217 /* Wait for valid random-data.*/
<> 154:37f96f9d4de2 218 while (RNG_RD_SR_OREG_LVL(base) == 0)
<> 154:37f96f9d4de2 219 {
<> 154:37f96f9d4de2 220 }
<> 154:37f96f9d4de2 221 data = RNG_RD_OR(base);
<> 154:37f96f9d4de2 222 }
<> 154:37f96f9d4de2 223 /* Get random-data word generated by RNGA.*/
<> 154:37f96f9d4de2 224 return data;
<> 154:37f96f9d4de2 225 }
<> 154:37f96f9d4de2 226
<> 154:37f96f9d4de2 227 status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size)
<> 154:37f96f9d4de2 228 {
<> 154:37f96f9d4de2 229 status_t result = kStatus_Success;
<> 154:37f96f9d4de2 230 uint32_t random_32;
<> 154:37f96f9d4de2 231 uint8_t *random_p;
<> 154:37f96f9d4de2 232 uint32_t random_size;
<> 154:37f96f9d4de2 233 uint8_t *data_p = (uint8_t *)data;
<> 154:37f96f9d4de2 234 uint32_t i;
<> 154:37f96f9d4de2 235
<> 154:37f96f9d4de2 236 /* Check input parameters.*/
<> 154:37f96f9d4de2 237 if (base && data && data_size)
<> 154:37f96f9d4de2 238 {
<> 154:37f96f9d4de2 239 do
<> 154:37f96f9d4de2 240 {
<> 154:37f96f9d4de2 241 /* Read Entropy.*/
<> 154:37f96f9d4de2 242 random_32 = rnga_ReadEntropy(base);
<> 154:37f96f9d4de2 243
<> 154:37f96f9d4de2 244 random_p = (uint8_t *)&random_32;
<> 154:37f96f9d4de2 245
<> 154:37f96f9d4de2 246 if (data_size < sizeof(random_32))
<> 154:37f96f9d4de2 247 {
<> 154:37f96f9d4de2 248 random_size = data_size;
<> 154:37f96f9d4de2 249 }
<> 154:37f96f9d4de2 250 else
<> 154:37f96f9d4de2 251 {
<> 154:37f96f9d4de2 252 random_size = sizeof(random_32);
<> 154:37f96f9d4de2 253 }
<> 154:37f96f9d4de2 254
<> 154:37f96f9d4de2 255 for (i = 0; i < random_size; i++)
<> 154:37f96f9d4de2 256 {
<> 154:37f96f9d4de2 257 *data_p++ = *random_p++;
<> 154:37f96f9d4de2 258 }
<> 154:37f96f9d4de2 259
<> 154:37f96f9d4de2 260 data_size -= random_size;
<> 154:37f96f9d4de2 261 } while (data_size > 0);
<> 154:37f96f9d4de2 262 }
<> 154:37f96f9d4de2 263 else
<> 154:37f96f9d4de2 264 {
<> 154:37f96f9d4de2 265 result = kStatus_InvalidArgument;
<> 154:37f96f9d4de2 266 }
<> 154:37f96f9d4de2 267
<> 154:37f96f9d4de2 268 return result;
<> 154:37f96f9d4de2 269 }
<> 154:37f96f9d4de2 270
<> 154:37f96f9d4de2 271 void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode)
<> 154:37f96f9d4de2 272 {
<> 154:37f96f9d4de2 273 RNG_WR_CR_SLP(base, (uint32_t)mode);
<> 154:37f96f9d4de2 274 }
<> 154:37f96f9d4de2 275
<> 154:37f96f9d4de2 276 rnga_mode_t RNGA_GetMode(RNG_Type *base)
<> 154:37f96f9d4de2 277 {
<> 154:37f96f9d4de2 278 return (rnga_mode_t)RNG_RD_SR_SLP(base);
<> 154:37f96f9d4de2 279 }
<> 154:37f96f9d4de2 280
<> 154:37f96f9d4de2 281 void RNGA_Seed(RNG_Type *base, uint32_t seed)
<> 154:37f96f9d4de2 282 {
<> 154:37f96f9d4de2 283 /* Write to RNGA Entropy Register.*/
<> 154:37f96f9d4de2 284 RNG_WR_ER(base, seed);
<> 154:37f96f9d4de2 285 }
<> 154:37f96f9d4de2 286
<> 154:37f96f9d4de2 287 #endif /* FSL_FEATURE_SOC_RNG_COUNT */