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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/drivers/fsl_adc16.h@174:ed647f63e28d, 2017-12-19 (annotated)

Committer:
Dollyparton
Date:
Tue Dec 19 12:50:13 2017 +0000
Revision:
174:ed647f63e28d
Parent:
154:37f96f9d4de2 
Added RAW socket.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #ifndef _FSL_ADC16_H_
<> 154:37f96f9d4de2 32 #define _FSL_ADC16_H_
<> 154:37f96f9d4de2 33
<> 154:37f96f9d4de2 34 #include "fsl_common.h"
<> 154:37f96f9d4de2 35
<> 154:37f96f9d4de2 36 /*!
<> 154:37f96f9d4de2 37 * @addtogroup adc16
<> 154:37f96f9d4de2 38 * @{
<> 154:37f96f9d4de2 39 */
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /*! @file */
<> 154:37f96f9d4de2 42
<> 154:37f96f9d4de2 43 /*******************************************************************************
<> 154:37f96f9d4de2 44 * Definitions
<> 154:37f96f9d4de2 45 ******************************************************************************/
<> 154:37f96f9d4de2 46
<> 154:37f96f9d4de2 47 /*! @name Driver version */
<> 154:37f96f9d4de2 48 /*@{*/
<> 154:37f96f9d4de2 49 /*! @brief ADC16 driver version 2.0.0. */
<> 154:37f96f9d4de2 50 #define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 154:37f96f9d4de2 51 /*@}*/
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 /*!
<> 154:37f96f9d4de2 54 * @brief Channel status flags.
<> 154:37f96f9d4de2 55 */
<> 154:37f96f9d4de2 56 enum _adc16_channel_status_flags
<> 154:37f96f9d4de2 57 {
<> 154:37f96f9d4de2 58 kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */
<> 154:37f96f9d4de2 59 };
<> 154:37f96f9d4de2 60
<> 154:37f96f9d4de2 61 /*!
<> 154:37f96f9d4de2 62 * @brief Converter status flags.
<> 154:37f96f9d4de2 63 */
<> 154:37f96f9d4de2 64 enum _adc16_status_flags
<> 154:37f96f9d4de2 65 {
<> 154:37f96f9d4de2 66 kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */
<> 154:37f96f9d4de2 67 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 154:37f96f9d4de2 68 kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */
<> 154:37f96f9d4de2 69 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 154:37f96f9d4de2 70 };
<> 154:37f96f9d4de2 71
<> 154:37f96f9d4de2 72 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
<> 154:37f96f9d4de2 73 /*!
<> 154:37f96f9d4de2 74 * @brief Channel multiplexer mode for each channel.
<> 154:37f96f9d4de2 75 *
<> 154:37f96f9d4de2 76 * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
<> 154:37f96f9d4de2 77 * are the different channels but share the same channel number.
<> 154:37f96f9d4de2 78 */
<> 154:37f96f9d4de2 79 typedef enum _adc_channel_mux_mode
<> 154:37f96f9d4de2 80 {
<> 154:37f96f9d4de2 81 kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */
<> 154:37f96f9d4de2 82 kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */
<> 154:37f96f9d4de2 83 } adc16_channel_mux_mode_t;
<> 154:37f96f9d4de2 84 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
<> 154:37f96f9d4de2 85
<> 154:37f96f9d4de2 86 /*!
<> 154:37f96f9d4de2 87 * @brief Clock divider for the converter.
<> 154:37f96f9d4de2 88 */
<> 154:37f96f9d4de2 89 typedef enum _adc16_clock_divider
<> 154:37f96f9d4de2 90 {
<> 154:37f96f9d4de2 91 kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */
<> 154:37f96f9d4de2 92 kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */
<> 154:37f96f9d4de2 93 kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */
<> 154:37f96f9d4de2 94 kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */
<> 154:37f96f9d4de2 95 } adc16_clock_divider_t;
<> 154:37f96f9d4de2 96
<> 154:37f96f9d4de2 97 /*!
<> 154:37f96f9d4de2 98 *@brief Converter's resolution.
<> 154:37f96f9d4de2 99 */
<> 154:37f96f9d4de2 100 typedef enum _adc16_resolution
<> 154:37f96f9d4de2 101 {
<> 154:37f96f9d4de2 102 /* This group of enumeration is for internal use which is related to register setting. */
<> 154:37f96f9d4de2 103 kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */
<> 154:37f96f9d4de2 104 kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
<> 154:37f96f9d4de2 105 kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
<> 154:37f96f9d4de2 106
<> 154:37f96f9d4de2 107 /* This group of enumeration is for public user. */
<> 154:37f96f9d4de2 108 kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */
<> 154:37f96f9d4de2 109 kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
<> 154:37f96f9d4de2 110 kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
<> 154:37f96f9d4de2 111 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 154:37f96f9d4de2 112 kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */
<> 154:37f96f9d4de2 113 kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */
<> 154:37f96f9d4de2 114 kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */
<> 154:37f96f9d4de2 115 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 154:37f96f9d4de2 116
<> 154:37f96f9d4de2 117 #if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
<> 154:37f96f9d4de2 118 /* 16-bit is supported by default. */
<> 154:37f96f9d4de2 119 kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */
<> 154:37f96f9d4de2 120 kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */
<> 154:37f96f9d4de2 121 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 154:37f96f9d4de2 122 kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */
<> 154:37f96f9d4de2 123 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 154:37f96f9d4de2 124 #endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */
<> 154:37f96f9d4de2 125 } adc16_resolution_t;
<> 154:37f96f9d4de2 126
<> 154:37f96f9d4de2 127 /*!
<> 154:37f96f9d4de2 128 * @brief Clock source.
<> 154:37f96f9d4de2 129 */
<> 154:37f96f9d4de2 130 typedef enum _adc16_clock_source
<> 154:37f96f9d4de2 131 {
<> 154:37f96f9d4de2 132 kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */
<> 154:37f96f9d4de2 133 kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */
<> 154:37f96f9d4de2 134 kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */
<> 154:37f96f9d4de2 135 kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */
<> 154:37f96f9d4de2 136
<> 154:37f96f9d4de2 137 /* Chip defined clock source */
<> 154:37f96f9d4de2 138 kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */
<> 154:37f96f9d4de2 139 } adc16_clock_source_t;
<> 154:37f96f9d4de2 140
<> 154:37f96f9d4de2 141 /*!
<> 154:37f96f9d4de2 142 * @brief Long sample mode.
<> 154:37f96f9d4de2 143 */
<> 154:37f96f9d4de2 144 typedef enum _adc16_long_sample_mode
<> 154:37f96f9d4de2 145 {
<> 154:37f96f9d4de2 146 kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
<> 154:37f96f9d4de2 147 kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
<> 154:37f96f9d4de2 148 kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
<> 154:37f96f9d4de2 149 kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
<> 154:37f96f9d4de2 150 kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */
<> 154:37f96f9d4de2 151 } adc16_long_sample_mode_t;
<> 154:37f96f9d4de2 152
<> 154:37f96f9d4de2 153 /*!
<> 154:37f96f9d4de2 154 * @brief Reference voltage source.
<> 154:37f96f9d4de2 155 */
<> 154:37f96f9d4de2 156 typedef enum _adc16_reference_voltage_source
<> 154:37f96f9d4de2 157 {
<> 154:37f96f9d4de2 158 kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
<> 154:37f96f9d4de2 159 kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */
<> 154:37f96f9d4de2 160 } adc16_reference_voltage_source_t;
<> 154:37f96f9d4de2 161
<> 154:37f96f9d4de2 162 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
<> 154:37f96f9d4de2 163 /*!
<> 154:37f96f9d4de2 164 * @brief Hardware average mode.
<> 154:37f96f9d4de2 165 */
<> 154:37f96f9d4de2 166 typedef enum _adc16_hardware_average_mode
<> 154:37f96f9d4de2 167 {
<> 154:37f96f9d4de2 168 kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
<> 154:37f96f9d4de2 169 kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
<> 154:37f96f9d4de2 170 kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
<> 154:37f96f9d4de2 171 kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
<> 154:37f96f9d4de2 172 kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/
<> 154:37f96f9d4de2 173 } adc16_hardware_average_mode_t;
<> 154:37f96f9d4de2 174 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
<> 154:37f96f9d4de2 175
<> 154:37f96f9d4de2 176 /*!
<> 154:37f96f9d4de2 177 * @brief Hardware compare mode.
<> 154:37f96f9d4de2 178 */
<> 154:37f96f9d4de2 179 typedef enum _adc16_hardware_compare_mode
<> 154:37f96f9d4de2 180 {
<> 154:37f96f9d4de2 181 kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */
<> 154:37f96f9d4de2 182 kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */
<> 154:37f96f9d4de2 183 kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2;
<> 154:37f96f9d4de2 184 else, value1 > x > value2. */
<> 154:37f96f9d4de2 185 kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2;
<> 154:37f96f9d4de2 186 else x >= value1 || x <= value2. */
<> 154:37f96f9d4de2 187 } adc16_hardware_compare_mode_t;
<> 154:37f96f9d4de2 188
<> 154:37f96f9d4de2 189 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 154:37f96f9d4de2 190 /*!
<> 154:37f96f9d4de2 191 * @brief PGA's Gain mode.
<> 154:37f96f9d4de2 192 */
<> 154:37f96f9d4de2 193 typedef enum _adc16_pga_gain
<> 154:37f96f9d4de2 194 {
<> 154:37f96f9d4de2 195 kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */
<> 154:37f96f9d4de2 196 kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */
<> 154:37f96f9d4de2 197 kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */
<> 154:37f96f9d4de2 198 kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */
<> 154:37f96f9d4de2 199 kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */
<> 154:37f96f9d4de2 200 kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */
<> 154:37f96f9d4de2 201 kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */
<> 154:37f96f9d4de2 202 } adc16_pga_gain_t;
<> 154:37f96f9d4de2 203 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 154:37f96f9d4de2 204
<> 154:37f96f9d4de2 205 /*!
<> 154:37f96f9d4de2 206 * @brief ADC16 converter configuration .
<> 154:37f96f9d4de2 207 */
<> 154:37f96f9d4de2 208 typedef struct _adc16_config
<> 154:37f96f9d4de2 209 {
<> 154:37f96f9d4de2 210 adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
<> 154:37f96f9d4de2 211 adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */
<> 154:37f96f9d4de2 212 bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */
<> 154:37f96f9d4de2 213 adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */
<> 154:37f96f9d4de2 214 adc16_resolution_t resolution; /*!< Select the sample resolution mode. */
<> 154:37f96f9d4de2 215 adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */
<> 154:37f96f9d4de2 216 bool enableHighSpeed; /*!< Enable the high-speed mode. */
<> 154:37f96f9d4de2 217 bool enableLowPower; /*!< Enable low power. */
<> 154:37f96f9d4de2 218 bool enableContinuousConversion; /*!< Enable continuous conversion mode. */
<> 154:37f96f9d4de2 219 } adc16_config_t;
<> 154:37f96f9d4de2 220
<> 154:37f96f9d4de2 221 /*!
<> 154:37f96f9d4de2 222 * @brief ADC16 Hardware compare configuration.
<> 154:37f96f9d4de2 223 */
<> 154:37f96f9d4de2 224 typedef struct _adc16_hardware_compare_config
<> 154:37f96f9d4de2 225 {
<> 154:37f96f9d4de2 226 adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
<> 154:37f96f9d4de2 227 See "adc16_hardware_compare_mode_t". */
<> 154:37f96f9d4de2 228 int16_t value1; /*!< Setting value1 for hardware compare mode. */
<> 154:37f96f9d4de2 229 int16_t value2; /*!< Setting value2 for hardware compare mode. */
<> 154:37f96f9d4de2 230 } adc16_hardware_compare_config_t;
<> 154:37f96f9d4de2 231
<> 154:37f96f9d4de2 232 /*!
<> 154:37f96f9d4de2 233 * @brief ADC16 channel conversion configuration.
<> 154:37f96f9d4de2 234 */
<> 154:37f96f9d4de2 235 typedef struct _adc16_channel_config
<> 154:37f96f9d4de2 236 {
<> 154:37f96f9d4de2 237 uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
<> 154:37f96f9d4de2 238 See channel connection information for each chip in Reference
<> 154:37f96f9d4de2 239 Manual document. */
<> 154:37f96f9d4de2 240 bool enableInterruptOnConversionCompleted; /*!< Generate a interrupt request once the conversion is completed. */
<> 154:37f96f9d4de2 241 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 154:37f96f9d4de2 242 bool enableDifferentialConversion; /*!< Using Differential sample mode. */
<> 154:37f96f9d4de2 243 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 154:37f96f9d4de2 244 } adc16_channel_config_t;
<> 154:37f96f9d4de2 245
<> 154:37f96f9d4de2 246 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 154:37f96f9d4de2 247 /*!
<> 154:37f96f9d4de2 248 * @brief ADC16 programmable gain amplifier configuration.
<> 154:37f96f9d4de2 249 */
<> 154:37f96f9d4de2 250 typedef struct _adc16_pga_config
<> 154:37f96f9d4de2 251 {
<> 154:37f96f9d4de2 252 adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */
<> 154:37f96f9d4de2 253 bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */
<> 154:37f96f9d4de2 254 #if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
<> 154:37f96f9d4de2 255 bool disablePgaChopping; /*!< Disable the PGA chopping function.
<> 154:37f96f9d4de2 256 The PGA employs chopping to remove/reduce offset and 1/f noise and offers
<> 154:37f96f9d4de2 257 an offset measurement configuration that aids the offset calibration. */
<> 154:37f96f9d4de2 258 #endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
<> 154:37f96f9d4de2 259 #if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
<> 154:37f96f9d4de2 260 bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode.
<> 154:37f96f9d4de2 261 When this feature is enabled, the PGA disconnects itself from the external
<> 154:37f96f9d4de2 262 inputs and auto-configures into offset measurement mode. With this field
<> 154:37f96f9d4de2 263 set, run the ADC in the recommended settings and enable the maximum hardware
<> 154:37f96f9d4de2 264 averaging to get the PGA offset number. The output is the
<> 154:37f96f9d4de2 265 (PGA offset * (64+1)) for the given PGA setting. */
<> 154:37f96f9d4de2 266 #endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
<> 154:37f96f9d4de2 267 } adc16_pga_config_t;
<> 154:37f96f9d4de2 268 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 154:37f96f9d4de2 269
<> 154:37f96f9d4de2 270 #if defined(__cplusplus)
<> 154:37f96f9d4de2 271 extern "C" {
<> 154:37f96f9d4de2 272 #endif
<> 154:37f96f9d4de2 273
<> 154:37f96f9d4de2 274 /*******************************************************************************
<> 154:37f96f9d4de2 275 * API
<> 154:37f96f9d4de2 276 ******************************************************************************/
<> 154:37f96f9d4de2 277
<> 154:37f96f9d4de2 278 /*!
<> 154:37f96f9d4de2 279 * @name Initialization
<> 154:37f96f9d4de2 280 * @{
<> 154:37f96f9d4de2 281 */
<> 154:37f96f9d4de2 282
<> 154:37f96f9d4de2 283 /*!
<> 154:37f96f9d4de2 284 * @brief Initializes the ADC16 module.
<> 154:37f96f9d4de2 285 *
<> 154:37f96f9d4de2 286 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 287 * @param config Pointer to configuration structure. See "adc16_config_t".
<> 154:37f96f9d4de2 288 */
<> 154:37f96f9d4de2 289 void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
<> 154:37f96f9d4de2 290
<> 154:37f96f9d4de2 291 /*!
<> 154:37f96f9d4de2 292 * @brief De-initializes the ADC16 module.
<> 154:37f96f9d4de2 293 *
<> 154:37f96f9d4de2 294 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 295 */
<> 154:37f96f9d4de2 296 void ADC16_Deinit(ADC_Type *base);
<> 154:37f96f9d4de2 297
<> 154:37f96f9d4de2 298 /*!
<> 154:37f96f9d4de2 299 * @brief Gets an available pre-defined settings for converter's configuration.
<> 154:37f96f9d4de2 300 *
<> 154:37f96f9d4de2 301 * This function initializes the converter configuration structure with an available settings. The default values are:
<> 154:37f96f9d4de2 302 * @code
<> 154:37f96f9d4de2 303 * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
<> 154:37f96f9d4de2 304 * config->clockSource = kADC16_ClockSourceAsynchronousClock;
<> 154:37f96f9d4de2 305 * config->enableAsynchronousClock = true;
<> 154:37f96f9d4de2 306 * config->clockDivider = kADC16_ClockDivider8;
<> 154:37f96f9d4de2 307 * config->resolution = kADC16_ResolutionSE12Bit;
<> 154:37f96f9d4de2 308 * config->longSampleMode = kADC16_LongSampleDisabled;
<> 154:37f96f9d4de2 309 * config->enableHighSpeed = false;
<> 154:37f96f9d4de2 310 * config->enableLowPower = false;
<> 154:37f96f9d4de2 311 * config->enableContinuousConversion = false;
<> 154:37f96f9d4de2 312 * @endcode
<> 154:37f96f9d4de2 313 * @param config Pointer to configuration structure.
<> 154:37f96f9d4de2 314 */
<> 154:37f96f9d4de2 315 void ADC16_GetDefaultConfig(adc16_config_t *config);
<> 154:37f96f9d4de2 316
<> 154:37f96f9d4de2 317 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 154:37f96f9d4de2 318 /*!
<> 154:37f96f9d4de2 319 * @brief Automates the hardware calibration.
<> 154:37f96f9d4de2 320 *
<> 154:37f96f9d4de2 321 * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation.
<> 154:37f96f9d4de2 322 * Execute the calibration before using the converter. Note that the hardware trigger should be used
<> 154:37f96f9d4de2 323 * during calibration.
<> 154:37f96f9d4de2 324 *
<> 154:37f96f9d4de2 325 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 326 *
<> 154:37f96f9d4de2 327 * @return Execution status.
<> 154:37f96f9d4de2 328 * @retval kStatus_Success Calibration is done successfully.
<> 154:37f96f9d4de2 329 * @retval kStatus_Fail Calibration is failed.
<> 154:37f96f9d4de2 330 */
<> 154:37f96f9d4de2 331 status_t ADC16_DoAutoCalibration(ADC_Type *base);
<> 154:37f96f9d4de2 332 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 154:37f96f9d4de2 333
<> 154:37f96f9d4de2 334 #if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
<> 154:37f96f9d4de2 335 /*!
<> 154:37f96f9d4de2 336 * @brief Sets the offset value for the conversion result.
<> 154:37f96f9d4de2 337 *
<> 154:37f96f9d4de2 338 * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result
<> 154:37f96f9d4de2 339 * is subtracted by it. Note, the hardware calibration fills the offset value automatically.
<> 154:37f96f9d4de2 340 *
<> 154:37f96f9d4de2 341 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 342 * @param value Setting offset value.
<> 154:37f96f9d4de2 343 */
<> 154:37f96f9d4de2 344 static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
<> 154:37f96f9d4de2 345 {
<> 154:37f96f9d4de2 346 base->OFS = (uint32_t)(value);
<> 154:37f96f9d4de2 347 }
<> 154:37f96f9d4de2 348 #endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
<> 154:37f96f9d4de2 349
<> 154:37f96f9d4de2 350 /* @} */
<> 154:37f96f9d4de2 351
<> 154:37f96f9d4de2 352 /*!
<> 154:37f96f9d4de2 353 * @name Advanced Feature
<> 154:37f96f9d4de2 354 * @{
<> 154:37f96f9d4de2 355 */
<> 154:37f96f9d4de2 356
<> 154:37f96f9d4de2 357 #if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
<> 154:37f96f9d4de2 358 /*!
<> 154:37f96f9d4de2 359 * @brief Enables generating the DMA trigger when conversion is completed.
<> 154:37f96f9d4de2 360 *
<> 154:37f96f9d4de2 361 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 362 * @param enable Switcher of DMA feature. "true" means to enable, "false" means not.
<> 154:37f96f9d4de2 363 */
<> 154:37f96f9d4de2 364 static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
<> 154:37f96f9d4de2 365 {
<> 154:37f96f9d4de2 366 if (enable)
<> 154:37f96f9d4de2 367 {
<> 154:37f96f9d4de2 368 base->SC2 |= ADC_SC2_DMAEN_MASK;
<> 154:37f96f9d4de2 369 }
<> 154:37f96f9d4de2 370 else
<> 154:37f96f9d4de2 371 {
<> 154:37f96f9d4de2 372 base->SC2 &= ~ADC_SC2_DMAEN_MASK;
<> 154:37f96f9d4de2 373 }
<> 154:37f96f9d4de2 374 }
<> 154:37f96f9d4de2 375 #endif /* FSL_FEATURE_ADC16_HAS_DMA */
<> 154:37f96f9d4de2 376
<> 154:37f96f9d4de2 377 /*!
<> 154:37f96f9d4de2 378 * @brief Enables the hardware trigger mode.
<> 154:37f96f9d4de2 379 *
<> 154:37f96f9d4de2 380 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 381 * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not.
<> 154:37f96f9d4de2 382 */
<> 154:37f96f9d4de2 383 static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
<> 154:37f96f9d4de2 384 {
<> 154:37f96f9d4de2 385 if (enable)
<> 154:37f96f9d4de2 386 {
<> 154:37f96f9d4de2 387 base->SC2 |= ADC_SC2_ADTRG_MASK;
<> 154:37f96f9d4de2 388 }
<> 154:37f96f9d4de2 389 else
<> 154:37f96f9d4de2 390 {
<> 154:37f96f9d4de2 391 base->SC2 &= ~ADC_SC2_ADTRG_MASK;
<> 154:37f96f9d4de2 392 }
<> 154:37f96f9d4de2 393 }
<> 154:37f96f9d4de2 394
<> 154:37f96f9d4de2 395 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
<> 154:37f96f9d4de2 396 /*!
<> 154:37f96f9d4de2 397 * @brief Sets the channel mux mode.
<> 154:37f96f9d4de2 398 *
<> 154:37f96f9d4de2 399 * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
<> 154:37f96f9d4de2 400 * indicated channel.
<> 154:37f96f9d4de2 401 *
<> 154:37f96f9d4de2 402 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 403 * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
<> 154:37f96f9d4de2 404 */
<> 154:37f96f9d4de2 405 void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
<> 154:37f96f9d4de2 406 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
<> 154:37f96f9d4de2 407
<> 154:37f96f9d4de2 408 /*!
<> 154:37f96f9d4de2 409 * @brief Configures the hardware compare mode.
<> 154:37f96f9d4de2 410 *
<> 154:37f96f9d4de2 411 * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result
<> 154:37f96f9d4de2 412 * in
<> 154:37f96f9d4de2 413 * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference
<> 154:37f96f9d4de2 414 * manual document for more detailed information.
<> 154:37f96f9d4de2 415 *
<> 154:37f96f9d4de2 416 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 417 * @param config Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature.
<> 154:37f96f9d4de2 418 */
<> 154:37f96f9d4de2 419 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
<> 154:37f96f9d4de2 420
<> 154:37f96f9d4de2 421 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
<> 154:37f96f9d4de2 422 /*!
<> 154:37f96f9d4de2 423 * @brief Sets the hardware average mode.
<> 154:37f96f9d4de2 424 *
<> 154:37f96f9d4de2 425 * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple
<> 154:37f96f9d4de2 426 * conversion results are accumulated and averaged internally. This aids reading results.
<> 154:37f96f9d4de2 427 *
<> 154:37f96f9d4de2 428 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 429 * @param mode Setting hardware average mode. See "adc16_hardware_average_mode_t".
<> 154:37f96f9d4de2 430 */
<> 154:37f96f9d4de2 431 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
<> 154:37f96f9d4de2 432 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
<> 154:37f96f9d4de2 433
<> 154:37f96f9d4de2 434 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 154:37f96f9d4de2 435 /*!
<> 154:37f96f9d4de2 436 * @brief Configures the PGA for converter's front end.
<> 154:37f96f9d4de2 437 *
<> 154:37f96f9d4de2 438 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 439 * @param config Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature.
<> 154:37f96f9d4de2 440 */
<> 154:37f96f9d4de2 441 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
<> 154:37f96f9d4de2 442 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 154:37f96f9d4de2 443
<> 154:37f96f9d4de2 444 /*!
<> 154:37f96f9d4de2 445 * @brief Gets the status flags of the converter.
<> 154:37f96f9d4de2 446 *
<> 154:37f96f9d4de2 447 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 448 *
<> 154:37f96f9d4de2 449 * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
<> 154:37f96f9d4de2 450 */
<> 154:37f96f9d4de2 451 uint32_t ADC16_GetStatusFlags(ADC_Type *base);
<> 154:37f96f9d4de2 452
<> 154:37f96f9d4de2 453 /*!
<> 154:37f96f9d4de2 454 * @brief Clears the status flags of the converter.
<> 154:37f96f9d4de2 455 *
<> 154:37f96f9d4de2 456 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 457 * @param mask Mask value for the cleared flags. See "_adc16_status_flags".
<> 154:37f96f9d4de2 458 */
<> 154:37f96f9d4de2 459 void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 460
<> 154:37f96f9d4de2 461 /* @} */
<> 154:37f96f9d4de2 462
<> 154:37f96f9d4de2 463 /*!
<> 154:37f96f9d4de2 464 * @name Conversion Channel
<> 154:37f96f9d4de2 465 * @{
<> 154:37f96f9d4de2 466 */
<> 154:37f96f9d4de2 467
<> 154:37f96f9d4de2 468 /*!
<> 154:37f96f9d4de2 469 * @brief Configures the conversion channel.
<> 154:37f96f9d4de2 470 *
<> 154:37f96f9d4de2 471 * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API
<> 154:37f96f9d4de2 472 * configures the channel while the external trigger source helps to trigger the conversion.
<> 154:37f96f9d4de2 473 *
<> 154:37f96f9d4de2 474 * Note that the "Channel Group" has a detailed description.
<> 154:37f96f9d4de2 475 * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one
<> 154:37f96f9d4de2 476 * group of status and control register, one for each conversion. The channel group parameter indicates which group of
<> 154:37f96f9d4de2 477 * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers. The
<> 154:37f96f9d4de2 478 * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
<> 154:37f96f9d4de2 479 * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware
<> 154:37f96f9d4de2 480 * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for
<> 154:37f96f9d4de2 481 * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the
<> 154:37f96f9d4de2 482 * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
<> 154:37f96f9d4de2 483 * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion.
<> 154:37f96f9d4de2 484 * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and
<> 154:37f96f9d4de2 485 * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
<> 154:37f96f9d4de2 486 * conversion aborts the current conversion.
<> 154:37f96f9d4de2 487 *
<> 154:37f96f9d4de2 488 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 489 * @param channelGroup Channel group index.
<> 154:37f96f9d4de2 490 * @param config Pointer to "adc16_channel_config_t" structure for conversion channel.
<> 154:37f96f9d4de2 491 */
<> 154:37f96f9d4de2 492 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
<> 154:37f96f9d4de2 493
<> 154:37f96f9d4de2 494 /*!
<> 154:37f96f9d4de2 495 * @brief Gets the conversion value.
<> 154:37f96f9d4de2 496 *
<> 154:37f96f9d4de2 497 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 498 * @param channelGroup Channel group index.
<> 154:37f96f9d4de2 499 *
<> 154:37f96f9d4de2 500 * @return Conversion value.
<> 154:37f96f9d4de2 501 */
<> 154:37f96f9d4de2 502 static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
<> 154:37f96f9d4de2 503 {
<> 154:37f96f9d4de2 504 assert(channelGroup < ADC_R_COUNT);
<> 154:37f96f9d4de2 505
<> 154:37f96f9d4de2 506 return base->R[channelGroup];
<> 154:37f96f9d4de2 507 }
<> 154:37f96f9d4de2 508
<> 154:37f96f9d4de2 509 /*!
<> 154:37f96f9d4de2 510 * @brief Gets the status flags of channel.
<> 154:37f96f9d4de2 511 *
<> 154:37f96f9d4de2 512 * @param base ADC16 peripheral base address.
<> 154:37f96f9d4de2 513 * @param channelGroup Channel group index.
<> 154:37f96f9d4de2 514 *
<> 154:37f96f9d4de2 515 * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
<> 154:37f96f9d4de2 516 */
<> 154:37f96f9d4de2 517 uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup);
<> 154:37f96f9d4de2 518
<> 154:37f96f9d4de2 519 /* @} */
<> 154:37f96f9d4de2 520
<> 154:37f96f9d4de2 521 #if defined(__cplusplus)
<> 154:37f96f9d4de2 522 }
<> 154:37f96f9d4de2 523 #endif
<> 154:37f96f9d4de2 524 /*!
<> 154:37f96f9d4de2 525 * @}
<> 154:37f96f9d4de2 526 */
<> 154:37f96f9d4de2 527 #endif /* _FSL_ADC16_H_ */