W7500x_toe.cpp

00001 /* Copyright (C) 2012 mbed.org, MIT License
00002  *
00003  * and associated documentation files (the "Software"), to deal in the Software without restriction,
00004  * including without limitation the rights to use, copy, modify, merge, publish, distribute,
00005  * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
00006  * furnished to do so, subject to the following conditions:
00007  *
00008  * The above copyright notice and this permission notice shall be included in all copies or
00009  * substantial portions of the Software.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
00012  * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
00013  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
00014  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00015  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00016  */
00017 #include "eth_arch.h"
00018 #if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500P) || defined(TARGET_WIZwiki_W7500ECO)
00019 
00020 
00021 #include "mbed.h"
00022 #include "mbed_debug.h"
00023 #include "DNSClient.h"
00024 
00025 
00026 /*
00027  * MDIO via GPIO
00028  * mdio via gpio is supported and related functions as follows.
00029  *  - mdio_init(),mdio_read(),mdio_write()
00030  *  - input_MDIO(),output_MDIO(),turnaroud_MDIO(),idle_MDIO()
00031  * called by ethernet_link() and ethernet_set_link()
00032  */
00033  
00034 #if defined (TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO)
00035 
00036 #define MDIO            GPIO_Pin_14
00037 #define MDC             GPIO_Pin_15
00038 #define GPIO_MDC        GPIOB
00039 #define PHY_ADDR_IP101G 0x07 
00040 #define PHY_ADDR        PHY_ADDR_IP101G
00041 #define SVAL            0x2 //right shift val = 2 
00042 #define PHYREG_CONTROL  0x0 //Control Register address (Contorl basic register)
00043 #define PHYREG_STATUS   0x1 //Status Register address (Status basic register)
00044 #define CNTL_DUPLEX     (0x01ul<< 7)
00045 #define CNTL_AUTONEGO   (0x01ul<<11)
00046 #define CNTL_SPEED      (0x01ul<<12)
00047 #define MDC_WAIT        (1)
00048 
00049 #elif defined (TARGET_WIZwiki_W7500P) 
00050 
00051 #define MDIO            GPIO_Pin_15
00052 #define MDC             GPIO_Pin_14
00053 #define GPIO_MDC        GPIOB
00054 #define PHY_ADDR_IP101G 0x01 
00055 #define PHY_ADDR        PHY_ADDR_IP101G
00056 #define SVAL            0x2 //right shift val = 2 
00057 #define PHYREG_CONTROL  0x0 //Control Register address (Contorl basic register)
00058 #define PHYREG_STATUS   0x1 //Status Register address (Status basic register)
00059 #define CNTL_DUPLEX     (0x01ul<< 7)
00060 #define CNTL_AUTONEGO   (0x01ul<<11)
00061 #define CNTL_SPEED      (0x01ul<<12)
00062 #define MDC_WAIT        (1)
00063 
00064 #endif
00065 
00066 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO);
00067 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val);
00068 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr);
00069 
00070 WIZnet_Chip* WIZnet_Chip::inst;
00071 
00072 WIZnet_Chip::WIZnet_Chip()
00073 {
00074     inst = this;
00075 }
00076 
00077 bool WIZnet_Chip::setmac()
00078 {
00079     reg_wr_mac(SHAR, mac);
00080     return true;
00081 }
00082 
00083 // Set the IP
00084 bool WIZnet_Chip::setip()
00085 {
00086     reg_wr<uint32_t>(SIPR, ip);
00087     reg_wr<uint32_t>(GAR, gateway);
00088     reg_wr<uint32_t>(SUBR, netmask);
00089     return true;
00090 }
00091 
00092 bool WIZnet_Chip::setProtocol(int socket, Protocol p)
00093 {
00094     if (socket < 0) {
00095         return false;
00096     }
00097     sreg<uint8_t>(socket, Sn_MR, p);
00098     return true;
00099 }
00100 
00101 bool WIZnet_Chip::connect(int socket, const char * host, int port, int timeout_ms)
00102 {
00103     if (socket < 0) {
00104         return false;
00105     }
00106     sreg<uint8_t>(socket, Sn_MR, TCP);
00107     scmd(socket, OPEN);
00108     sreg_ip(socket, Sn_DIPR, host);
00109     sreg<uint16_t>(socket, Sn_DPORT, port);
00110     sreg<uint16_t>(socket, Sn_PORT, new_port());
00111     scmd(socket, CONNECT);
00112     Timer t;
00113     t.reset();
00114     t.start();
00115     //timeout_ms=700;
00116     //printf("waiting %d\r\n", timeout_ms);
00117     while(!is_connected(socket)) {
00118         if (t.read_ms() > timeout_ms) {
00119             return false;
00120         }
00121     }
00122     return true;
00123 }
00124 
00125 bool WIZnet_Chip::gethostbyname(const char* host, uint32_t* ip)
00126 {
00127     uint32_t addr = str_to_ip(host);
00128     char buf[17];
00129     snprintf(buf, sizeof(buf), "%d.%d.%d.%d", 
00130             (uint8_t)((addr>>24)&0xff), 
00131             (uint8_t)((addr>>16)&0xff), 
00132             (uint8_t)((addr>>8)&0xff), 
00133             (uint8_t)(addr&0xff));
00134     if (strcmp(buf, host) == 0) {
00135         *ip = addr;
00136         return true;
00137     }
00138     DNSClient client;
00139     if(client.lookup(host)) {
00140         *ip = client.ip;
00141         return true;
00142     }
00143     return false;
00144 }
00145 
00146 // Geminate Changes.
00147 int WIZnet_Chip::get_DHAR0(int socket)
00148 {
00149     //sreg<uint32_t>(socket, Sn_RCR, 0x0000000);
00150     //reg_wr<uint32_t>(Sn_RCR, 0x00000008);
00151     
00152     return( sreg<uint32_t>(socket, Sn_DHAR0));
00153 }
00154 
00155 
00156 int WIZnet_Chip::get_DHAR1(int socket)
00157 {
00158     return( sreg<uint32_t>(socket, Sn_DHAR1));
00159 }
00160 
00161 // End Changes.
00162 
00163 
00164 bool WIZnet_Chip::is_connected(int socket)
00165 {
00166     /*
00167        if (sreg<uint8_t>(socket, Sn_SR) == SOCK_ESTABLISHED) {
00168        return true;
00169        }
00170      */
00171     uint8_t tmpSn_SR;
00172     tmpSn_SR = sreg<uint8_t>(socket, Sn_SR);
00173     // packet sending is possible, when state is SOCK_CLOSE_WAIT.
00174     if ((tmpSn_SR == SOCK_ESTABLISHED) || (tmpSn_SR == SOCK_CLOSE_WAIT)) {
00175         return true;
00176     }
00177     return false;
00178 }
00179 // Reset the chip & set the buffer
00180 void WIZnet_Chip::reset()
00181 {
00182     /* S/W Reset PHY */
00183     mdio_write(GPIO_MDC, PHYREG_CONTROL, 0x8000);
00184     wait_ms(10);//for S/W reset
00185     wait_ms(10);//for MDC I/F RDY
00186 
00187     mdio_init(GPIO_MDC, MDC, MDIO);
00188     
00189     /* S/W Reset WZTOE */
00190     reg_wr<uint8_t>(MR, MR_RST);
00191     // set PAD strengh and pull-up for TXD[3:0] and TXE 
00192 #ifdef __DEF_USED_IC101AG__ //For using IC+101AG
00193 
00194 #if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO)
00195 
00196     *(volatile uint32_t *)(0x41003068) = 0x64; //TXD0 
00197     *(volatile uint32_t *)(0x4100306C) = 0x64; //TXD1
00198     *(volatile uint32_t *)(0x41003070) = 0x64; //TXD2
00199     *(volatile uint32_t *)(0x41003074) = 0x64; //TXD3
00200     *(volatile uint32_t *)(0x41003050) = 0x64; //TXE
00201 #endif
00202 
00203 #endif  
00204 
00205     // set ticker counter
00206     reg_wr<uint32_t>(TIC100US, (SystemCoreClock/10000));
00207     // write MAC address inside the WZTOE MAC address register
00208     reg_wr_mac(SHAR, mac);
00209     /*
00210      * set RX and TX buffer size */
00211     // Geminate Change!
00212     //for (int socket = 0; socket < MAX_SOCK_NUM; socket++) {
00213     for (int socket = 0; socket < 2; socket++)
00214     {
00215         sreg<uint8_t>(socket, Sn_RXBUF_SIZE, 8);
00216         sreg<uint8_t>(socket, Sn_TXBUF_SIZE, 8);
00217     }
00218     
00219     for (int socket = 2; socket < MAX_SOCK_NUM; socket++)
00220     {
00221         sreg<uint8_t>(socket, Sn_RXBUF_SIZE, 0);
00222         sreg<uint8_t>(socket, Sn_TXBUF_SIZE, 0);
00223     }
00224 }
00225 
00226 
00227 bool WIZnet_Chip::close(int socket)
00228 {
00229     if (socket < 0) {
00230         return false;
00231     }
00232     // if SOCK_CLOSED, return
00233     if (sreg<uint8_t>(socket, Sn_SR) == SOCK_CLOSED) {
00234         return true;
00235     }
00236     // if SOCK_ESTABLISHED, send FIN-Packet to peer 
00237     if (sreg<uint8_t>(socket, Sn_MR) == TCP) {
00238         scmd(socket, DISCON);
00239     }
00240     // close socket
00241     scmd(socket, CLOSE);
00242     // clear Socket Interrupt Register
00243     sreg<uint8_t>(socket, Sn_ICR, 0xff);
00244     return true;
00245 }
00246 
00247 int WIZnet_Chip::wait_readable(int socket, int wait_time_ms, int req_size)
00248 {
00249     if (socket < 0) {
00250         return -1;
00251     }
00252     Timer t;
00253     t.reset();
00254     t.start();
00255     while(1) {
00256         int size = sreg<uint16_t>(socket, Sn_RX_RSR);
00257         if (size > req_size) {
00258             return size;
00259         }
00260         if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
00261             break;
00262         }
00263     }
00264     return -1;
00265 }
00266 
00267 int WIZnet_Chip::wait_writeable(int socket, int wait_time_ms, int req_size)
00268 {
00269     if (socket < 0) {
00270         return -1;
00271     }
00272     Timer t;
00273     t.reset();
00274     t.start();
00275     while(1) {
00276         int size = sreg<uint16_t>(socket, Sn_TX_FSR);
00277         if (size > req_size) {
00278             return size;
00279         }
00280         if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
00281             break;
00282         }
00283     }
00284     return -1;
00285 }
00286 
00287 int WIZnet_Chip::send(int socket, const char * str, int len)
00288 {   
00289     if (socket < 0) {
00290         return -1;
00291     }
00292 
00293     uint16_t ptr = sreg<uint16_t>(socket, Sn_TX_WR);
00294     uint32_t sn_tx_base = W7500x_TXMEM_BASE + (uint32_t)(socket<<18); 
00295 
00296     for(int i=0; i<len; i++)
00297         *(volatile uint8_t *)(sn_tx_base + ((ptr+i)&0xFFFF)) = str[i];
00298 
00299     sreg<uint16_t>(socket, Sn_TX_WR, ptr + len);
00300     scmd(socket, SEND);
00301 
00302     uint8_t tmp_Sn_IR;
00303     while (( (tmp_Sn_IR = sreg<uint8_t>(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) {
00304         // @Jul.10, 2014 fix contant name, and udp sendto function.
00305         switch (sreg<uint8_t>(socket, Sn_SR)) {
00306             case SOCK_CLOSED :
00307                 close(socket);
00308                 return 0;
00309                 //break;
00310             case SOCK_UDP :
00311                 // ARP timeout is possible.
00312                 if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) {
00313                     sreg<uint8_t>(socket, Sn_ICR, INT_TIMEOUT);
00314                     return 0;
00315                 }
00316                 break;
00317             default :
00318                 break;
00319         }
00320     }
00321 
00322     sreg<uint8_t>(socket, Sn_ICR, INT_SEND_OK);
00323 
00324     return len;
00325 }
00326 
00327 
00328 int WIZnet_Chip::sendRaw(int socket, const char * str, int len)
00329 {
00330     if (socket < 0) {
00331         return -1;
00332     }
00333 
00334     uint16_t ptr = sreg<uint16_t>(socket, Sn_TX_WR);
00335     uint32_t sn_tx_base = W7500x_TXMEM_BASE + (uint32_t)(socket<<18); 
00336 
00337     for(int i=0; i<len; i++)
00338         *(volatile uint8_t *)(sn_tx_base + ((ptr+i)&0xFFFF)) = str[i];
00339 
00340     sreg<uint16_t>(socket, Sn_TX_WR, ptr + len);
00341 
00342     scmd(socket, SEND_MAC);
00343 
00344     uint8_t tmp_Sn_IR;
00345     while (( (tmp_Sn_IR = sreg<uint8_t>(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) {
00346         // @Jul.10, 2014 fix contant name, and udp sendto function.
00347         switch (sreg<uint8_t>(socket, Sn_SR)) {
00348             case SOCK_CLOSED :
00349                 close(socket);
00350                 return 0;
00351                 //break;
00352             case SOCK_UDP :
00353                 // ARP timeout is possible.
00354                 if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) {
00355                     sreg<uint8_t>(socket, Sn_ICR, INT_TIMEOUT);
00356                     return 0;
00357                 }
00358                 break;
00359             default :
00360                 break;
00361         }
00362     }
00363 
00364     sreg<uint8_t>(socket, Sn_ICR, INT_SEND_OK);
00365 
00366     return len;
00367 }
00368 
00369 int WIZnet_Chip::recv(int socket, char* buf, int len)
00370 {
00371     if (socket < 0) {
00372         return -1;
00373     }
00374     uint16_t ptr = sreg<uint16_t>(socket, Sn_RX_RD);
00375     uint32_t sn_rx_base = W7500x_RXMEM_BASE + (uint32_t)(socket<<18); 
00376 
00377     for(int i=0; i<len; i++)
00378         buf[i] = *(volatile uint8_t *)(sn_rx_base + ((ptr+i)&0xFFFF));
00379 
00380     sreg<uint16_t>(socket, Sn_RX_RD, ptr + len);
00381     scmd(socket, RECV);
00382 
00383     return len;
00384 }
00385 
00386 int WIZnet_Chip::new_socket()
00387 {
00388     for(int s = 0; s < MAX_SOCK_NUM; s++) {
00389         if (sreg<uint8_t>(s, Sn_SR) == SOCK_CLOSED) {
00390             return s;
00391         }
00392     }
00393     return -1;
00394 }
00395 
00396 uint16_t WIZnet_Chip::new_port()
00397 {
00398     uint16_t port = rand();
00399     port |= 49152;
00400     return port;
00401 }
00402 
00403 bool WIZnet_Chip::link(int wait_time_ms)
00404 {
00405     Timer t;
00406     t.reset();
00407     t.start();
00408     while(1) {
00409         int is_link = ethernet_link();
00410         
00411         if (is_link) {
00412             return true;
00413         }
00414         if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
00415             break;
00416         }
00417     }
00418     return 0;
00419 }
00420 
00421 void WIZnet_Chip::set_link(PHYMode phymode)
00422 {
00423     int speed = -1;
00424     int duplex = 0;
00425 
00426     switch(phymode) {
00427         case AutoNegotiate : speed = -1; duplex = 0; break;
00428         case HalfDuplex10  : speed = 0;  duplex = 0; break;
00429         case FullDuplex10  : speed = 0;  duplex = 1; break;
00430         case HalfDuplex100 : speed = 1;  duplex = 0; break;
00431         case FullDuplex100 : speed = 1;  duplex = 1; break;
00432     }
00433 
00434     ethernet_set_link(speed, duplex);
00435 }
00436 
00437 uint32_t str_to_ip(const char* str)
00438 {
00439     uint32_t ip = 0;
00440     char* p = (char*)str;
00441     for(int i = 0; i < 4; i++) {
00442         ip |= atoi(p);
00443         p = strchr(p, '.');
00444         if (p == NULL) {
00445             break;
00446         }
00447         ip <<= 8;
00448         p++;
00449     }
00450     return ip;
00451 }
00452 
00453 void printfBytes(char* str, uint8_t* buf, int len)
00454 {
00455     printf("%s %d:", str, len);
00456     for(int i = 0; i < len; i++) {
00457         printf(" %02x", buf[i]);
00458     }
00459     printf("\n");
00460 }
00461 
00462 void printHex(uint8_t* buf, int len)
00463 {
00464     for(int i = 0; i < len; i++) {
00465         if ((i%16) == 0) {
00466             printf("%p", buf+i);
00467         }
00468         printf(" %02x", buf[i]);
00469         if ((i%16) == 15) {
00470             printf("\n");
00471         }
00472     }
00473     printf("\n");
00474 }
00475 
00476 void debug_hex(uint8_t* buf, int len)
00477 {
00478     for(int i = 0; i < len; i++) {
00479         if ((i%16) == 0) {
00480             debug("%p", buf+i);
00481         }
00482         debug(" %02x", buf[i]);
00483         if ((i%16) == 15) {
00484             debug("\n");
00485         }
00486     }
00487     debug("\n");
00488 }
00489 
00490 void WIZnet_Chip::scmd(int socket, Command cmd)
00491 {
00492     sreg<uint8_t>(socket, Sn_CR, cmd);
00493     while(sreg<uint8_t>(socket, Sn_CR));
00494 }
00495 
00496 
00497 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO)
00498 {
00499     /* Set GPIOs for MDIO and MDC */
00500     GPIO_InitTypeDef MDIO_InitDef;  
00501     HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDIO, PAD_AF1);  
00502     HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDC, PAD_AF1);  
00503     MDIO_InitDef.GPIO_Pin = GPIO_Pin_MDC | GPIO_Pin_MDIO;
00504     MDIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
00505     HAL_GPIO_Init(GPIOx, &MDIO_InitDef);
00506 }
00507 
00508 void output_MDIO(GPIO_TypeDef* GPIOx, uint32_t val, uint32_t n)
00509 {
00510     for(val <<= (32-n); n; val<<=1, n--)
00511     {
00512         if(val & 0x80000000)
00513             HAL_GPIO_SetBits(GPIOx, MDIO); 
00514         else
00515             HAL_GPIO_ResetBits(GPIOx, MDIO);
00516 
00517         wait_ms(MDC_WAIT);
00518         HAL_GPIO_SetBits(GPIOx, MDC); 
00519         wait_ms(MDC_WAIT);
00520         HAL_GPIO_ResetBits(GPIOx, MDC);
00521     }
00522 }
00523 
00524 uint32_t input_MDIO( GPIO_TypeDef* GPIOx )
00525 {
00526     uint32_t i, val=0; 
00527     for(i=0; i<16; i++)
00528     {
00529         val <<=1;
00530         HAL_GPIO_SetBits(GPIOx, MDC); 
00531         wait_ms(MDC_WAIT);
00532         HAL_GPIO_ResetBits(GPIOx, MDC);
00533         wait_ms(MDC_WAIT);
00534         val |= HAL_GPIO_ReadInputDataBit(GPIOx, MDIO);
00535     }
00536     return (val);
00537 }
00538 
00539 void turnaround_MDIO( GPIO_TypeDef* GPIOx)
00540 {
00541     GPIOx->OUTENCLR = MDIO ;
00542     HAL_GPIO_SetBits(GPIOx, MDC); 
00543     wait_ms(MDC_WAIT);
00544     HAL_GPIO_ResetBits(GPIOx, MDC);
00545     wait_ms(MDC_WAIT);
00546 }
00547 
00548 void idle_MDIO( GPIO_TypeDef* GPIOx )
00549 {
00550     GPIOx->OUTENSET = MDIO ;
00551     HAL_GPIO_SetBits(GPIOx,MDC); 
00552     wait_ms(MDC_WAIT);
00553     HAL_GPIO_ResetBits(GPIOx, MDC);
00554     wait_ms(MDC_WAIT);
00555 }
00556 
00557 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr)
00558 {
00559     output_MDIO(GPIOx, 0xFFFFFFFF, 32);
00560     output_MDIO(GPIOx, 0x06, 4);
00561     output_MDIO(GPIOx, PHY_ADDR, 5);
00562     output_MDIO(GPIOx, PhyRegAddr, 5);
00563     turnaround_MDIO(GPIOx);
00564     uint32_t val = input_MDIO(GPIOx );
00565     idle_MDIO(GPIOx);
00566     return val;
00567 }
00568 
00569 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val)
00570 {
00571     output_MDIO(GPIOx, 0xFFFFFFFF, 32);
00572     output_MDIO(GPIOx, 0x05, 4);
00573     output_MDIO(GPIOx, PHY_ADDR, 5);
00574     output_MDIO(GPIOx, PhyRegAddr, 5);
00575     output_MDIO(GPIOx, 0x02, 2);
00576     output_MDIO(GPIOx, val, 16);
00577     idle_MDIO(GPIOx);
00578 }
00579 
00580 int WIZnet_Chip::ethernet_link(void) {
00581     return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01); 
00582 }
00583 
00584 void WIZnet_Chip::ethernet_set_link(int speed, int duplex) {
00585     uint32_t val=0;
00586     if((speed < 0) || (speed > 1)) {
00587         val = CNTL_AUTONEGO; 
00588     } else {
00589         val = ((CNTL_SPEED&(speed<<11))|(CNTL_DUPLEX&(duplex<<7))); 
00590     }
00591     mdio_write(GPIO_MDC, PHYREG_CONTROL, val);
00592 }
00593 
00594    void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data) 
00595    {
00596         data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));
00597         data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));
00598         data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));
00599         data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));
00600         data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));
00601         data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));
00602     }
00603 
00604     void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip)
00605     {
00606         uint8_t buf[4]={0,};
00607         uint32_t wr_ip = 0;
00608         char* p = (char*)ip;
00609         
00610         for(int i = 0; i < 4; i++) {
00611             wr_ip = (wr_ip<<8);
00612             buf[i] = atoi(p);
00613             wr_ip |= buf[i];
00614             p = strchr(p, '.');
00615             if (p == NULL) break;
00616             p++;
00617         }
00618         *(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;
00619     }
00620 
00621     void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {
00622         reg_wr_ip(addr,  (uint8_t)(0x01+(socket<<2)), ip);
00623     }
00624 
00625 #endif
00626 
00627