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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
168:9672193075cf 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_sdram.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 168:9672193075cf 5 * @version V1.2.2
AnnaBridge 168:9672193075cf 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SDRAM HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 168:9672193075cf 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_SDRAM_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_SDRAM_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_ll_fmc.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SDRAM
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported typedef ----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL SDRAM State structure definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 69 HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */
<> 144:ef7eb2e8f9f7 70 HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */
<> 144:ef7eb2e8f9f7 71 HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */
<> 144:ef7eb2e8f9f7 72 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
<> 144:ef7eb2e8f9f7 73 HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 }HAL_SDRAM_StateTypeDef;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /**
<> 144:ef7eb2e8f9f7 78 * @brief SDRAM handle Structure definition
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80 typedef struct
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 HAL_LockTypeDef Lock; /*!< SDRAM locking object */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 }SDRAM_HandleTypeDef;
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @}
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
<> 144:ef7eb2e8f9f7 101 * @{
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** @brief Reset SDRAM handle state
<> 144:ef7eb2e8f9f7 105 * @param __HANDLE__: specifies the SDRAM handle.
<> 144:ef7eb2e8f9f7 106 * @retval None
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @}
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** @addtogroup SDRAM_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* Initialization/de-initialization functions *********************************/
<> 144:ef7eb2e8f9f7 125 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
<> 144:ef7eb2e8f9f7 126 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 127 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 128 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 131 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 132 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 133 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @}
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** @addtogroup SDRAM_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 /* I/O operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 143 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 144 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 145 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 146 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 147 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 148 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 151 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @}
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @addtogroup SDRAM_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160 /* SDRAM Control functions *****************************************************/
<> 144:ef7eb2e8f9f7 161 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 162 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 163 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 164 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
<> 144:ef7eb2e8f9f7 165 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
<> 144:ef7eb2e8f9f7 166 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** @addtogroup SDRAM_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 173 * @{
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 /* SDRAM State functions ********************************************************/
<> 144:ef7eb2e8f9f7 176 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @}
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @}
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195 #endif
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #endif /* __STM32F7xx_HAL_SDRAM_H */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/