John Karatka / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
168:9672193075cf 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 168:9672193075cf 5 * @version V1.2.2
AnnaBridge 168:9672193075cf 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### RCC specific features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 After reset the device is running from Internal High Speed oscillator
<> 144:ef7eb2e8f9f7 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
<> 144:ef7eb2e8f9f7 20 and I-Cache are disabled, and all peripherals are off except internal
<> 144:ef7eb2e8f9f7 21 SRAM, Flash and JTAG.
<> 144:ef7eb2e8f9f7 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
<> 144:ef7eb2e8f9f7 23 all peripherals mapped on these busses are running at HSI speed.
<> 144:ef7eb2e8f9f7 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
<> 144:ef7eb2e8f9f7 25 (+) All GPIOs are in input floating state, except the JTAG pins which
<> 144:ef7eb2e8f9f7 26 are assigned to be used for debug purpose.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 [..]
<> 144:ef7eb2e8f9f7 29 Once the device started from reset, the user application has to:
<> 144:ef7eb2e8f9f7 30 (+) Configure the clock source to be used to drive the System clock
<> 144:ef7eb2e8f9f7 31 (if the application needs higher frequency/performance)
<> 144:ef7eb2e8f9f7 32 (+) Configure the System clock frequency and Flash settings
<> 144:ef7eb2e8f9f7 33 (+) Configure the AHB and APB busses prescalers
<> 144:ef7eb2e8f9f7 34 (+) Enable the clock for the peripheral(s) to be used
<> 144:ef7eb2e8f9f7 35 (+) Configure the clock source(s) for peripherals which clocks are not
<> 144:ef7eb2e8f9f7 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 ##### RCC Limitations #####
<> 144:ef7eb2e8f9f7 39 ==============================================================================
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 A delay between an RCC peripheral clock enable and the effective peripheral
<> 144:ef7eb2e8f9f7 42 enabling should be taken into account in order to manage the peripheral read/write
<> 144:ef7eb2e8f9f7 43 from/to registers.
<> 144:ef7eb2e8f9f7 44 (+) This delay depends on the peripheral mapping.
<> 144:ef7eb2e8f9f7 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
<> 144:ef7eb2e8f9f7 46 after the clock enable bit is set on the hardware register
<> 144:ef7eb2e8f9f7 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
<> 144:ef7eb2e8f9f7 48 after the clock enable bit is set on the hardware register
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 Implemented Workaround:
<> 144:ef7eb2e8f9f7 52 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 144:ef7eb2e8f9f7 53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 @endverbatim
<> 144:ef7eb2e8f9f7 56 ******************************************************************************
<> 144:ef7eb2e8f9f7 57 * @attention
<> 144:ef7eb2e8f9f7 58 *
AnnaBridge 168:9672193075cf 59 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 60 *
<> 144:ef7eb2e8f9f7 61 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 62 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 63 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 64 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 65 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 66 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 67 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 69 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 70 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 82 *
<> 144:ef7eb2e8f9f7 83 ******************************************************************************
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 87 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /** @defgroup RCC RCC
<> 144:ef7eb2e8f9f7 94 * @brief RCC HAL module driver
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 102 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 /** @defgroup RCC_Private_Macros RCC Private Macros
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 108 #define MCO1_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 109 #define MCO1_PIN GPIO_PIN_8
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 112 #define MCO2_GPIO_PORT GPIOC
<> 144:ef7eb2e8f9f7 113 #define MCO2_PIN GPIO_PIN_9
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @}
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup RCC_Private_Variables RCC Private Variables
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup RCC_Exported_Functions RCC Exported Functions
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 135 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 136 *
<> 144:ef7eb2e8f9f7 137 @verbatim
<> 144:ef7eb2e8f9f7 138 ===============================================================================
<> 144:ef7eb2e8f9f7 139 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 140 ===============================================================================
<> 144:ef7eb2e8f9f7 141 [..]
<> 144:ef7eb2e8f9f7 142 This section provides functions allowing to configure the internal/external oscillators
<> 144:ef7eb2e8f9f7 143 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
<> 144:ef7eb2e8f9f7 144 and APB2).
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 [..] Internal/external clock and PLL configuration
<> 144:ef7eb2e8f9f7 147 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
<> 144:ef7eb2e8f9f7 148 the PLL as System clock source.
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
<> 144:ef7eb2e8f9f7 151 clock source.
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
<> 144:ef7eb2e8f9f7 154 through the PLL as System clock source. Can be used also as RTC clock source.
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
<> 144:ef7eb2e8f9f7 159 (++) The first output is used to generate the high speed system clock (up to 216 MHz)
<> 144:ef7eb2e8f9f7 160 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
<> 144:ef7eb2e8f9f7 161 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
<> 144:ef7eb2e8f9f7 164 and if a HSE clock failure occurs(HSE used directly or through PLL as System
<> 144:ef7eb2e8f9f7 165 clock source), the System clock is automatically switched to HSI and an interrupt
<> 144:ef7eb2e8f9f7 166 is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
<> 144:ef7eb2e8f9f7 167 (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
<> 144:ef7eb2e8f9f7 170 clock (through a configurable prescaler) on PA8 pin.
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
<> 144:ef7eb2e8f9f7 173 clock (through a configurable prescaler) on PC9 pin.
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 [..] System, AHB and APB busses clocks configuration
<> 144:ef7eb2e8f9f7 176 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
<> 144:ef7eb2e8f9f7 177 HSE and PLL.
<> 144:ef7eb2e8f9f7 178 The AHB clock (HCLK) is derived from System clock through configurable
<> 144:ef7eb2e8f9f7 179 prescaler and used to clock the CPU, memory and peripherals mapped
<> 144:ef7eb2e8f9f7 180 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
<> 144:ef7eb2e8f9f7 181 from AHB clock through configurable prescalers and used to clock
<> 144:ef7eb2e8f9f7 182 the peripherals mapped on these busses. You can use
<> 144:ef7eb2e8f9f7 183 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
<> 144:ef7eb2e8f9f7 186 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
<> 144:ef7eb2e8f9f7 187 from an external clock mapped on the I2S_CKIN pin.
<> 144:ef7eb2e8f9f7 188 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
<> 144:ef7eb2e8f9f7 189 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
<> 144:ef7eb2e8f9f7 190 from an external clock mapped on the I2S_CKIN pin.
<> 144:ef7eb2e8f9f7 191 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
<> 144:ef7eb2e8f9f7 192 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
<> 144:ef7eb2e8f9f7 193 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
<> 144:ef7eb2e8f9f7 194 macros to configure this clock.
<> 144:ef7eb2e8f9f7 195 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
<> 144:ef7eb2e8f9f7 196 to work correctly, while the SDIO require a frequency equal or lower than
<> 144:ef7eb2e8f9f7 197 to 48. This clock is derived of the main PLL through PLLQ divider.
<> 144:ef7eb2e8f9f7 198 (+@) IWDG clock which is always the LSI clock.
<> 144:ef7eb2e8f9f7 199 @endverbatim
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @brief Resets the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 205 * @note The default reset state of the clock configuration is given below:
<> 144:ef7eb2e8f9f7 206 * - HSI ON and used as system clock source
<> 144:ef7eb2e8f9f7 207 * - HSE, PLL and PLLI2S OFF
<> 144:ef7eb2e8f9f7 208 * - AHB, APB1 and APB2 prescaler set to 1.
<> 144:ef7eb2e8f9f7 209 * - CSS, MCO1 and MCO2 OFF
<> 144:ef7eb2e8f9f7 210 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 211 * @note This function doesn't modify the configuration of the
<> 144:ef7eb2e8f9f7 212 * - Peripheral clocks
<> 144:ef7eb2e8f9f7 213 * - LSI, LSE and RTC clocks
<> 144:ef7eb2e8f9f7 214 * @retval None
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 void HAL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 219 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 222 CLEAR_REG(RCC->CFGR);
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Reset HSEON, CSSON, PLLON, PLLI2S */
<> 144:ef7eb2e8f9f7 225 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 228 CLEAR_REG(RCC->PLLCFGR);
<> 144:ef7eb2e8f9f7 229 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U));
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Reset PLLI2SCFGR register */
<> 144:ef7eb2e8f9f7 232 CLEAR_REG(RCC->PLLI2SCFGR);
<> 144:ef7eb2e8f9f7 233 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 236 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 239 CLEAR_REG(RCC->CIR);
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 242 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @brief Initializes the RCC Oscillators according to the specified parameters in the
<> 144:ef7eb2e8f9f7 247 * RCC_OscInitTypeDef.
<> 144:ef7eb2e8f9f7 248 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 249 * contains the configuration information for the RCC Oscillators.
<> 144:ef7eb2e8f9f7 250 * @note The PLL is not disabled when used as system clock.
<> 144:ef7eb2e8f9f7 251 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<> 144:ef7eb2e8f9f7 252 * supported by this function. User should request a transition to LSE Off
<> 144:ef7eb2e8f9f7 253 * first and then LSE On or LSE Bypass.
<> 144:ef7eb2e8f9f7 254 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 255 * supported by this function. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 256 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 257 * @retval HAL status
<> 144:ef7eb2e8f9f7 258 */
<> 157:ff67d9f36b67 259 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 260 {
<> 161:2cc1468da177 261 uint32_t tickstart = 0;
<> 161:2cc1468da177 262 FlagStatus pwrclkchanged = RESET;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Check the parameters */
<> 144:ef7eb2e8f9f7 265 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /*------------------------------- HSE Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 268 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Check the parameters */
<> 144:ef7eb2e8f9f7 271 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<> 144:ef7eb2e8f9f7 272 /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
<> 144:ef7eb2e8f9f7 273 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 274 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281 else
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 /* Set the new HSE configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 284 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Check the HSE State */
<> 144:ef7eb2e8f9f7 287 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 290 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Wait till HSE is ready */
<> 144:ef7eb2e8f9f7 293 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 else
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 304 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Wait till HSE is bypassed or disabled */
<> 144:ef7eb2e8f9f7 307 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317 /*----------------------------- HSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 318 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 /* Check the parameters */
<> 144:ef7eb2e8f9f7 321 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<> 144:ef7eb2e8f9f7 322 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<> 144:ef7eb2e8f9f7 325 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 326 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* When HSI is used as system clock it will not disabled */
<> 144:ef7eb2e8f9f7 329 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333 /* Otherwise, just the calibration is allowed */
<> 144:ef7eb2e8f9f7 334 else
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 337 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340 else
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 /* Check the HSI State */
<> 144:ef7eb2e8f9f7 343 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 /* Enable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 346 __HAL_RCC_HSI_ENABLE();
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 349 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 352 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 361 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363 else
<> 144:ef7eb2e8f9f7 364 {
<> 144:ef7eb2e8f9f7 365 /* Disable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 366 __HAL_RCC_HSI_DISABLE();
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 369 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 372 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 375 {
<> 144:ef7eb2e8f9f7 376 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382 /*------------------------------ LSI Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 383 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 /* Check the parameters */
<> 144:ef7eb2e8f9f7 386 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Check the LSI State */
<> 144:ef7eb2e8f9f7 389 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 /* Enable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 392 __HAL_RCC_LSI_ENABLE();
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 395 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 398 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 else
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 /* Disable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 409 __HAL_RCC_LSI_DISABLE();
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 412 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 415 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 420 }
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 /*------------------------------ LSE Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 425 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 /* Check the parameters */
<> 144:ef7eb2e8f9f7 428 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<> 144:ef7eb2e8f9f7 429
<> 161:2cc1468da177 430 /* Update LSE configuration in Backup Domain control register */
<> 161:2cc1468da177 431 /* Requires to enable write access to Backup Domain of necessary */
<> 161:2cc1468da177 432 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
<> 161:2cc1468da177 433 {
<> 161:2cc1468da177 434 /* Enable Power Clock*/
<> 161:2cc1468da177 435 __HAL_RCC_PWR_CLK_ENABLE();
<> 161:2cc1468da177 436 pwrclkchanged = SET;
<> 161:2cc1468da177 437 }
<> 144:ef7eb2e8f9f7 438
<> 161:2cc1468da177 439 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
<> 161:2cc1468da177 440 {
<> 161:2cc1468da177 441 /* Enable write access to Backup domain */
<> 161:2cc1468da177 442 PWR->CR1 |= PWR_CR1_DBP;
<> 161:2cc1468da177 443
<> 161:2cc1468da177 444 /* Wait for Backup domain Write protection disable */
<> 161:2cc1468da177 445 tickstart = HAL_GetTick();
<> 161:2cc1468da177 446
<> 161:2cc1468da177 447 while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
<> 144:ef7eb2e8f9f7 448 {
<> 161:2cc1468da177 449 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
<> 161:2cc1468da177 450 {
<> 161:2cc1468da177 451 return HAL_TIMEOUT;
<> 161:2cc1468da177 452 }
<> 161:2cc1468da177 453 }
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Set the new LSE configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 457 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<> 144:ef7eb2e8f9f7 458 /* Check the LSE State */
<> 144:ef7eb2e8f9f7 459 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 462 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 465 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471 }
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473 else
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 476 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 479 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486 }
<> 161:2cc1468da177 487
<> 161:2cc1468da177 488 /* Restore clock configuration if changed */
<> 161:2cc1468da177 489 if(pwrclkchanged == SET)
<> 161:2cc1468da177 490 {
<> 161:2cc1468da177 491 __HAL_RCC_PWR_CLK_DISABLE();
<> 161:2cc1468da177 492 }
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494 /*-------------------------------- PLL Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 495 /* Check the parameters */
<> 144:ef7eb2e8f9f7 496 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<> 144:ef7eb2e8f9f7 497 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 500 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 /* Check the parameters */
<> 144:ef7eb2e8f9f7 505 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<> 144:ef7eb2e8f9f7 506 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
<> 144:ef7eb2e8f9f7 507 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
<> 144:ef7eb2e8f9f7 508 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
<> 144:ef7eb2e8f9f7 509 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
<> 157:ff67d9f36b67 510 #if defined (RCC_PLLCFGR_PLLR)
<> 157:ff67d9f36b67 511 assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
<> 157:ff67d9f36b67 512 #endif
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 515 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 518 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 521 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Configure the main PLL clock source, multiplication and division factors. */
<> 157:ff67d9f36b67 530 #if defined (RCC_PLLCFGR_PLLR)
<> 157:ff67d9f36b67 531 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 157:ff67d9f36b67 532 RCC_OscInitStruct->PLL.PLLM,
<> 157:ff67d9f36b67 533 RCC_OscInitStruct->PLL.PLLN,
<> 157:ff67d9f36b67 534 RCC_OscInitStruct->PLL.PLLP,
<> 157:ff67d9f36b67 535 RCC_OscInitStruct->PLL.PLLQ,
<> 157:ff67d9f36b67 536 RCC_OscInitStruct->PLL.PLLR);
<> 157:ff67d9f36b67 537 #else
<> 157:ff67d9f36b67 538 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 157:ff67d9f36b67 539 RCC_OscInitStruct->PLL.PLLM,
<> 157:ff67d9f36b67 540 RCC_OscInitStruct->PLL.PLLN,
<> 157:ff67d9f36b67 541 RCC_OscInitStruct->PLL.PLLP,
<> 157:ff67d9f36b67 542 RCC_OscInitStruct->PLL.PLLQ);
<> 157:ff67d9f36b67 543 #endif
<> 157:ff67d9f36b67 544
<> 144:ef7eb2e8f9f7 545 /* Enable the main PLL. */
<> 144:ef7eb2e8f9f7 546 __HAL_RCC_PLL_ENABLE();
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 549 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 552 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560 else
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 563 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 566 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 569 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 else
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 return HAL_OK;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
<> 144:ef7eb2e8f9f7 588 * parameters in the RCC_ClkInitStruct.
<> 144:ef7eb2e8f9f7 589 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 590 * contains the configuration information for the RCC peripheral.
<> 144:ef7eb2e8f9f7 591 * @param FLatency: FLASH Latency, this parameter depend on device selected
<> 144:ef7eb2e8f9f7 592 *
<> 144:ef7eb2e8f9f7 593 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 594 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
<> 144:ef7eb2e8f9f7 595 *
<> 144:ef7eb2e8f9f7 596 * @note The HSI is used (enabled by hardware) as system clock source after
<> 144:ef7eb2e8f9f7 597 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
<> 144:ef7eb2e8f9f7 598 * of failure of the HSE used directly or indirectly as system clock
<> 144:ef7eb2e8f9f7 599 * (if the Clock Security System CSS is enabled).
<> 144:ef7eb2e8f9f7 600 *
<> 144:ef7eb2e8f9f7 601 * @note A switch from one clock source to another occurs only if the target
<> 144:ef7eb2e8f9f7 602 * clock source is ready (clock stable after startup delay or PLL locked).
<> 144:ef7eb2e8f9f7 603 * If a clock source which is not yet ready is selected, the switch will
<> 144:ef7eb2e8f9f7 604 * occur when the clock source will be ready.
<> 144:ef7eb2e8f9f7 605 * You can use HAL_RCC_GetClockConfig() function to know which clock is
<> 144:ef7eb2e8f9f7 606 * currently used as system clock source.
<> 144:ef7eb2e8f9f7 607 * @note Depending on the device voltage range, the software has to set correctly
<> 144:ef7eb2e8f9f7 608 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
<> 144:ef7eb2e8f9f7 609 * (for more details refer to section above "Initialization/de-initialization functions")
<> 144:ef7eb2e8f9f7 610 * @retval None
<> 144:ef7eb2e8f9f7 611 */
<> 144:ef7eb2e8f9f7 612 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<> 144:ef7eb2e8f9f7 613 {
<> 144:ef7eb2e8f9f7 614 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Check the parameters */
<> 144:ef7eb2e8f9f7 617 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<> 144:ef7eb2e8f9f7 618 assert_param(IS_FLASH_LATENCY(FLatency));
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
<> 144:ef7eb2e8f9f7 621 must be correctly programmed according to the frequency of the CPU clock
<> 144:ef7eb2e8f9f7 622 (HCLK) and the supply voltage of the device. */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Increasing the CPU frequency */
<> 144:ef7eb2e8f9f7 625 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 628 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 631 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 632 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636 }
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /*-------------------------- HCLK Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 639 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 642 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /*------------------------- SYSCLK Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 646 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* HSE is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 651 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 /* Check the HSE ready flag */
<> 144:ef7eb2e8f9f7 654 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659 /* PLL is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 660 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 /* Check the PLL ready flag */
<> 144:ef7eb2e8f9f7 663 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668 /* HSI is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 669 else
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Check the HSI ready flag */
<> 144:ef7eb2e8f9f7 672 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
<> 144:ef7eb2e8f9f7 679 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 680 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702 else
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Decreasing the number of wait states because of lower CPU frequency */
<> 144:ef7eb2e8f9f7 715 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 718 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 721 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 722 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /*-------------------------- PCLK1 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 729 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 732 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /*-------------------------- PCLK2 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 736 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
<> 144:ef7eb2e8f9f7 737 {
<> 144:ef7eb2e8f9f7 738 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
<> 144:ef7eb2e8f9f7 739 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 743 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 746 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 return HAL_OK;
<> 144:ef7eb2e8f9f7 749 }
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /**
<> 144:ef7eb2e8f9f7 752 * @}
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 756 * @brief RCC clocks control functions
<> 144:ef7eb2e8f9f7 757 *
<> 144:ef7eb2e8f9f7 758 @verbatim
<> 144:ef7eb2e8f9f7 759 ===============================================================================
<> 144:ef7eb2e8f9f7 760 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 761 ===============================================================================
<> 144:ef7eb2e8f9f7 762 [..]
<> 144:ef7eb2e8f9f7 763 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 764 frequencies.
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 @endverbatim
<> 144:ef7eb2e8f9f7 767 * @{
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /**
<> 144:ef7eb2e8f9f7 771 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
<> 144:ef7eb2e8f9f7 772 * @note PA8/PC9 should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 773 * @param RCC_MCOx: specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 774 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 775 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 776 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
<> 144:ef7eb2e8f9f7 777 * @param RCC_MCOSource: specifies the clock source to output.
<> 144:ef7eb2e8f9f7 778 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 779 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 780 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 781 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 782 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 783 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
<> 144:ef7eb2e8f9f7 784 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
<> 144:ef7eb2e8f9f7 785 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
<> 144:ef7eb2e8f9f7 786 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
<> 144:ef7eb2e8f9f7 787 * @param RCC_MCODiv: specifies the MCOx prescaler.
<> 144:ef7eb2e8f9f7 788 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 789 * @arg RCC_MCODIV_1: no division applied to MCOx clock
<> 144:ef7eb2e8f9f7 790 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<> 144:ef7eb2e8f9f7 791 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<> 144:ef7eb2e8f9f7 792 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<> 144:ef7eb2e8f9f7 793 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<> 144:ef7eb2e8f9f7 794 * @retval None
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 GPIO_InitTypeDef GPIO_InitStruct;
<> 144:ef7eb2e8f9f7 799 /* Check the parameters */
<> 144:ef7eb2e8f9f7 800 assert_param(IS_RCC_MCO(RCC_MCOx));
<> 144:ef7eb2e8f9f7 801 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<> 144:ef7eb2e8f9f7 802 /* RCC_MCO1 */
<> 144:ef7eb2e8f9f7 803 if(RCC_MCOx == RCC_MCO1)
<> 144:ef7eb2e8f9f7 804 {
<> 144:ef7eb2e8f9f7 805 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* MCO1 Clock Enable */
<> 144:ef7eb2e8f9f7 808 MCO1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Configure the MCO1 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 811 GPIO_InitStruct.Pin = MCO1_PIN;
<> 144:ef7eb2e8f9f7 812 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 813 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
<> 144:ef7eb2e8f9f7 814 GPIO_InitStruct.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 815 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
<> 144:ef7eb2e8f9f7 816 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
<> 144:ef7eb2e8f9f7 819 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821 else
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* MCO2 Clock Enable */
<> 144:ef7eb2e8f9f7 826 MCO2_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Configure the MCO2 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 829 GPIO_InitStruct.Pin = MCO2_PIN;
<> 144:ef7eb2e8f9f7 830 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 831 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
<> 144:ef7eb2e8f9f7 832 GPIO_InitStruct.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 833 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
<> 144:ef7eb2e8f9f7 834 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
<> 144:ef7eb2e8f9f7 837 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /**
<> 144:ef7eb2e8f9f7 842 * @brief Enables the Clock Security System.
<> 144:ef7eb2e8f9f7 843 * @note If a failure is detected on the HSE oscillator clock, this oscillator
<> 144:ef7eb2e8f9f7 844 * is automatically disabled and an interrupt is generated to inform the
<> 144:ef7eb2e8f9f7 845 * software about the failure (Clock Security System Interrupt, CSSI),
<> 144:ef7eb2e8f9f7 846 * allowing the MCU to perform rescue operations. The CSSI is linked to
<> 144:ef7eb2e8f9f7 847 * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 848 * @retval None
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850 void HAL_RCC_EnableCSS(void)
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 SET_BIT(RCC->CR, RCC_CR_CSSON);
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /**
<> 144:ef7eb2e8f9f7 856 * @brief Disables the Clock Security System.
<> 144:ef7eb2e8f9f7 857 * @retval None
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 void HAL_RCC_DisableCSS(void)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /**
<> 144:ef7eb2e8f9f7 865 * @brief Returns the SYSCLK frequency
<> 144:ef7eb2e8f9f7 866 *
<> 144:ef7eb2e8f9f7 867 * @note The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 868 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 869 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 870 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 871 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 872 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 873 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 874 * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 875 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 876 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 877 * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 878 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 879 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 880 * have wrong result.
<> 144:ef7eb2e8f9f7 881 *
<> 144:ef7eb2e8f9f7 882 * @note The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 883 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 884 *
<> 144:ef7eb2e8f9f7 885 * @note This function can be used by the user application to compute the
<> 144:ef7eb2e8f9f7 886 * baudrate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 887 *
<> 144:ef7eb2e8f9f7 888 * @note Each time SYSCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 889 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 890 *
<> 144:ef7eb2e8f9f7 891 *
<> 144:ef7eb2e8f9f7 892 * @retval SYSCLK frequency
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 uint32_t HAL_RCC_GetSysClockFreq(void)
<> 144:ef7eb2e8f9f7 895 {
<> 144:ef7eb2e8f9f7 896 uint32_t pllm = 0, pllvco = 0, pllp = 0;
<> 144:ef7eb2e8f9f7 897 uint32_t sysclockfreq = 0;
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 900 switch (RCC->CFGR & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 905 break;
<> 144:ef7eb2e8f9f7 906 }
<> 144:ef7eb2e8f9f7 907 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 sysclockfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 910 break;
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
<> 144:ef7eb2e8f9f7 915 SYSCLK = PLL_VCO / PLLP */
<> 144:ef7eb2e8f9f7 916 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
<> 144:ef7eb2e8f9f7 917 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
<> 144:ef7eb2e8f9f7 918 {
<> 144:ef7eb2e8f9f7 919 /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 920 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922 else
<> 144:ef7eb2e8f9f7 923 {
<> 144:ef7eb2e8f9f7 924 /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 925 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 sysclockfreq = pllvco/pllp;
<> 144:ef7eb2e8f9f7 930 break;
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932 default:
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 935 break;
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938 return sysclockfreq;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /**
<> 144:ef7eb2e8f9f7 942 * @brief Returns the HCLK frequency
<> 144:ef7eb2e8f9f7 943 * @note Each time HCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 944 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 945 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
<> 144:ef7eb2e8f9f7 946 * @retval HCLK frequency
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948 uint32_t HAL_RCC_GetHCLKFreq(void)
<> 144:ef7eb2e8f9f7 949 {
<> 144:ef7eb2e8f9f7 950 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /**
<> 144:ef7eb2e8f9f7 954 * @brief Returns the PCLK1 frequency
<> 144:ef7eb2e8f9f7 955 * @note Each time PCLK1 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 956 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 957 * @retval PCLK1 frequency
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959 uint32_t HAL_RCC_GetPCLK1Freq(void)
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 962 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /**
<> 144:ef7eb2e8f9f7 966 * @brief Returns the PCLK2 frequency
<> 144:ef7eb2e8f9f7 967 * @note Each time PCLK2 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 968 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 969 * @retval PCLK2 frequency
<> 144:ef7eb2e8f9f7 970 */
<> 144:ef7eb2e8f9f7 971 uint32_t HAL_RCC_GetPCLK2Freq(void)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 974 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 979 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 980 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 981 * will be configured.
<> 144:ef7eb2e8f9f7 982 * @retval None
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 /* Set all possible values for the Oscillator type parameter ---------------*/
<> 144:ef7eb2e8f9f7 987 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 /* Get the HSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 990 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998 else
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Get the HSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1004 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 1005 {
<> 144:ef7eb2e8f9f7 1006 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 1007 }
<> 144:ef7eb2e8f9f7 1008 else
<> 144:ef7eb2e8f9f7 1009 {
<> 144:ef7eb2e8f9f7 1010 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Get the LSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1016 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
<> 144:ef7eb2e8f9f7 1017 {
<> 144:ef7eb2e8f9f7 1018 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
<> 144:ef7eb2e8f9f7 1021 {
<> 144:ef7eb2e8f9f7 1022 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024 else
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 1027 }
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Get the LSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1030 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034 else
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /* Get the PLL configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1040 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044 else
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
<> 144:ef7eb2e8f9f7 1049 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
<> 144:ef7eb2e8f9f7 1050 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
<> 144:ef7eb2e8f9f7 1051 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
<> 144:ef7eb2e8f9f7 1052 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /**
<> 144:ef7eb2e8f9f7 1056 * @brief Configures the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1057 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1058 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1059 * will be configured.
<> 144:ef7eb2e8f9f7 1060 * @param pFLatency: Pointer on the Flash Latency.
<> 144:ef7eb2e8f9f7 1061 * @retval None
<> 144:ef7eb2e8f9f7 1062 */
<> 144:ef7eb2e8f9f7 1063 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
<> 144:ef7eb2e8f9f7 1064 {
<> 144:ef7eb2e8f9f7 1065 /* Set all possible values for the Clock type parameter --------------------*/
<> 144:ef7eb2e8f9f7 1066 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 /* Get the SYSCLK configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1069 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* Get the HCLK configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1072 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /* Get the APB1 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1075 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Get the APB2 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1078 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /* Get the Flash Wait State (Latency) configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1081 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /**
<> 144:ef7eb2e8f9f7 1085 * @brief This function handles the RCC CSS interrupt request.
<> 144:ef7eb2e8f9f7 1086 * @note This API should be called under the NMI_Handler().
<> 144:ef7eb2e8f9f7 1087 * @retval None
<> 144:ef7eb2e8f9f7 1088 */
<> 144:ef7eb2e8f9f7 1089 void HAL_RCC_NMI_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1090 {
<> 144:ef7eb2e8f9f7 1091 /* Check RCC CSSF flag */
<> 144:ef7eb2e8f9f7 1092 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* RCC Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 1095 HAL_RCC_CSSCallback();
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Clear RCC CSS pending bit */
<> 144:ef7eb2e8f9f7 1098 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<> 144:ef7eb2e8f9f7 1099 }
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /**
<> 144:ef7eb2e8f9f7 1103 * @brief RCC Clock Security System interrupt callback
<> 144:ef7eb2e8f9f7 1104 * @retval None
<> 144:ef7eb2e8f9f7 1105 */
<> 144:ef7eb2e8f9f7 1106 __weak void HAL_RCC_CSSCallback(void)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1109 the HAL_RCC_CSSCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1110 */
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /**
<> 144:ef7eb2e8f9f7 1114 * @}
<> 144:ef7eb2e8f9f7 1115 */
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /**
<> 144:ef7eb2e8f9f7 1118 * @}
<> 144:ef7eb2e8f9f7 1119 */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1122 /**
<> 144:ef7eb2e8f9f7 1123 * @}
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /**
<> 144:ef7eb2e8f9f7 1127 * @}
<> 144:ef7eb2e8f9f7 1128 */
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/