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mbed-dev
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targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CMSDK_CM3DS.h@182:57724642e740, 2018-02-16 (annotated)
- Committer:
- AnnaBridge
- Date:
- Fri Feb 16 16:09:33 2018 +0000
- Revision:
- 182:57724642e740
- Parent:
- 168:9672193075cf
mbed-dev library. Release version 159.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 167:e84263d55307 | 1 | /* |
| AnnaBridge | 167:e84263d55307 | 2 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
| AnnaBridge | 167:e84263d55307 | 3 | * |
| AnnaBridge | 167:e84263d55307 | 4 | * SPDX-License-Identifier: Apache-2.0 |
| AnnaBridge | 167:e84263d55307 | 5 | * |
| AnnaBridge | 167:e84263d55307 | 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| AnnaBridge | 167:e84263d55307 | 7 | * not use this file except in compliance with the License. |
| AnnaBridge | 167:e84263d55307 | 8 | * You may obtain a copy of the License at |
| AnnaBridge | 167:e84263d55307 | 9 | * |
| AnnaBridge | 167:e84263d55307 | 10 | * http://www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 167:e84263d55307 | 11 | * |
| AnnaBridge | 167:e84263d55307 | 12 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 167:e84263d55307 | 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| AnnaBridge | 167:e84263d55307 | 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 167:e84263d55307 | 15 | * See the License for the specific language governing permissions and |
| AnnaBridge | 167:e84263d55307 | 16 | * limitations under the License. |
| AnnaBridge | 167:e84263d55307 | 17 | * |
| AnnaBridge | 167:e84263d55307 | 18 | * This file is derivative of CMSIS V5.00 ARMCM3.h |
| AnnaBridge | 167:e84263d55307 | 19 | */ |
| AnnaBridge | 167:e84263d55307 | 20 | |
| AnnaBridge | 167:e84263d55307 | 21 | #ifndef CMSDK_CM3DS_H |
| AnnaBridge | 167:e84263d55307 | 22 | #define CMSDK_CM3DS_H |
| AnnaBridge | 167:e84263d55307 | 23 | |
| AnnaBridge | 167:e84263d55307 | 24 | #ifdef __cplusplus |
| AnnaBridge | 167:e84263d55307 | 25 | extern "C" { |
| AnnaBridge | 167:e84263d55307 | 26 | #endif |
| AnnaBridge | 167:e84263d55307 | 27 | |
| AnnaBridge | 167:e84263d55307 | 28 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
| AnnaBridge | 167:e84263d55307 | 29 | |
| AnnaBridge | 167:e84263d55307 | 30 | typedef enum IRQn |
| AnnaBridge | 167:e84263d55307 | 31 | { |
| AnnaBridge | 167:e84263d55307 | 32 | /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ |
| AnnaBridge | 167:e84263d55307 | 33 | NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 34 | HardFault_IRQn = -13, /* 3 HardFault Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 35 | MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 36 | BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 37 | UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 38 | SVCall_IRQn = -5, /* 11 SV Call Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 39 | DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 40 | PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 41 | SysTick_IRQn = -1, /* 15 System Tick Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 42 | |
| AnnaBridge | 167:e84263d55307 | 43 | /* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */ |
| AnnaBridge | 167:e84263d55307 | 44 | UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 45 | Spare_IRQn = 1, /* Undefined */ |
| AnnaBridge | 167:e84263d55307 | 46 | UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 47 | APB_SLAVE_0_IRQ = 3, /* Reserved for APB Slave */ |
| AnnaBridge | 167:e84263d55307 | 48 | APB_SLAVE_1_IRQ = 4, /* Reserved for APB Slave */ |
| AnnaBridge | 167:e84263d55307 | 49 | RTC_IRQn = 5, /* RTC Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 50 | PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 51 | PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 52 | TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 53 | TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 54 | DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 55 | APB_SLAVE_2_IRQ = 11, /* Reserved for APB Slave */ |
| AnnaBridge | 167:e84263d55307 | 56 | UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 57 | APB_SLAVE_3_IRQ = 13, /* Reserved for APB Slave */ |
| AnnaBridge | 167:e84263d55307 | 58 | RESERVED0_IRQn = 14, /* Reserved */ |
| AnnaBridge | 167:e84263d55307 | 59 | TSC_IRQn = 15, /* Touch Screen Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 60 | PORT0_0_IRQn = 16, /* GPIO Port 0 pin 0 Handler */ |
| AnnaBridge | 167:e84263d55307 | 61 | PORT0_1_IRQn = 17, /* GPIO Port 0 pin 1 Handler */ |
| AnnaBridge | 167:e84263d55307 | 62 | PORT0_2_IRQn = 18, /* GPIO Port 0 pin 2 Handler */ |
| AnnaBridge | 167:e84263d55307 | 63 | PORT0_3_IRQn = 19, /* GPIO Port 0 pin 3 Handler */ |
| AnnaBridge | 167:e84263d55307 | 64 | PORT0_4_IRQn = 20, /* GPIO Port 0 pin 4 Handler */ |
| AnnaBridge | 167:e84263d55307 | 65 | PORT0_5_IRQn = 21, /* GPIO Port 0 pin 5 Handler */ |
| AnnaBridge | 167:e84263d55307 | 66 | PORT0_6_IRQn = 22, /* GPIO Port 0 pin 6 Handler */ |
| AnnaBridge | 167:e84263d55307 | 67 | PORT0_7_IRQn = 23, /* GPIO Port 0 pin 7 Handler */ |
| AnnaBridge | 167:e84263d55307 | 68 | PORT0_8_IRQn = 24, /* GPIO Port 0 pin 8 Handler */ |
| AnnaBridge | 167:e84263d55307 | 69 | PORT0_9_IRQn = 25, /* GPIO Port 0 pin 9 Handler */ |
| AnnaBridge | 167:e84263d55307 | 70 | PORT0_10_IRQn = 26, /* GPIO Port 0 pin 10 Handler */ |
| AnnaBridge | 167:e84263d55307 | 71 | PORT0_11_IRQn = 27, /* GPIO Port 0 pin 11 Handler */ |
| AnnaBridge | 167:e84263d55307 | 72 | PORT0_12_IRQn = 28, /* GPIO Port 0 pin 12 Handler */ |
| AnnaBridge | 167:e84263d55307 | 73 | PORT0_13_IRQn = 29, /* GPIO Port 0 pin 13 Handler */ |
| AnnaBridge | 167:e84263d55307 | 74 | PORT0_14_IRQn = 30, /* GPIO Port 0 pin 14 Handler */ |
| AnnaBridge | 167:e84263d55307 | 75 | PORT0_15_IRQn = 31, /* GPIO Port 0 pin 15 Handler */ |
| AnnaBridge | 167:e84263d55307 | 76 | FLASH0_IRQn = 32, /* Reserved for Flash */ |
| AnnaBridge | 167:e84263d55307 | 77 | FLASH1_IRQn = 33, /* Reserved for Flash */ |
| AnnaBridge | 167:e84263d55307 | 78 | RESERVED1_IRQn = 34, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 79 | RESERVED2_IRQn = 35, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 80 | RESERVED3_IRQn = 36, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 81 | RESERVED4_IRQn = 37, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 82 | RESERVED5_IRQn = 38, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 83 | RESERVED6_IRQn = 39, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 84 | RESERVED7_IRQn = 40, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 85 | RESERVED8_IRQn = 41, /* Reserved for Cordio */ |
| AnnaBridge | 167:e84263d55307 | 86 | PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 87 | PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 88 | TRNG_IRQn = 44, /* Random number generator Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 89 | UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 90 | UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 91 | ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */ |
| AnnaBridge | 167:e84263d55307 | 92 | I2S_IRQn = 48, /* I2S Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 93 | MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */ |
| AnnaBridge | 167:e84263d55307 | 94 | MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */ |
| AnnaBridge | 167:e84263d55307 | 95 | MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */ |
| AnnaBridge | 168:9672193075cf | 96 | MPS2_SPI3_IRQn = 52, /* SPI Interrupt (shield 0) */ |
| AnnaBridge | 168:9672193075cf | 97 | MPS2_SPI4_IRQn = 53, /* SPI Interrupt (shield 1) */ |
| AnnaBridge | 167:e84263d55307 | 98 | PORT4_ALL_IRQn = 54, /* GPIO Port 4 combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 99 | PORT5_ALL_IRQn = 55, /* GPIO Port 5 combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 100 | UART4_IRQn = 56 /* UART 4 RX and TX Combined Interrupt */ |
| AnnaBridge | 167:e84263d55307 | 101 | } IRQn_Type; |
| AnnaBridge | 167:e84263d55307 | 102 | |
| AnnaBridge | 167:e84263d55307 | 103 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 104 | /* ================ Processor and Core Peripheral Section ================ */ |
| AnnaBridge | 167:e84263d55307 | 105 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 106 | |
| AnnaBridge | 167:e84263d55307 | 107 | /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ |
| AnnaBridge | 167:e84263d55307 | 108 | #define __CM3DS_REV 0x0201U /* Core revision r2p1 */ |
| AnnaBridge | 167:e84263d55307 | 109 | #define __MPU_PRESENT 1 /* MPU present or not */ |
| AnnaBridge | 167:e84263d55307 | 110 | #define __VTOR_PRESENT 1 /* VTOR present or not */ |
| AnnaBridge | 167:e84263d55307 | 111 | #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ |
| AnnaBridge | 167:e84263d55307 | 112 | #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ |
| AnnaBridge | 167:e84263d55307 | 113 | |
| AnnaBridge | 167:e84263d55307 | 114 | #include <core_cm3.h> /* Processor and core peripherals */ |
| AnnaBridge | 167:e84263d55307 | 115 | #include "system_CMSDK_CM3DS.h" /* System Header */ |
| AnnaBridge | 167:e84263d55307 | 116 | |
| AnnaBridge | 167:e84263d55307 | 117 | |
| AnnaBridge | 167:e84263d55307 | 118 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 119 | /* ================ Device Specific Peripheral Section ================ */ |
| AnnaBridge | 167:e84263d55307 | 120 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 121 | |
| AnnaBridge | 167:e84263d55307 | 122 | /* ------------------- Start of section using anonymous unions ------------------ */ |
| AnnaBridge | 167:e84263d55307 | 123 | #if defined ( __CC_ARM ) |
| AnnaBridge | 167:e84263d55307 | 124 | #pragma push |
| AnnaBridge | 167:e84263d55307 | 125 | #pragma anon_unions |
| AnnaBridge | 167:e84263d55307 | 126 | #elif defined(__ICCARM__) |
| AnnaBridge | 167:e84263d55307 | 127 | #pragma language=extended |
| AnnaBridge | 167:e84263d55307 | 128 | #elif defined(__GNUC__) |
| AnnaBridge | 167:e84263d55307 | 129 | /* anonymous unions are enabled by default */ |
| AnnaBridge | 167:e84263d55307 | 130 | #elif defined(__TMS470__) |
| AnnaBridge | 167:e84263d55307 | 131 | /* anonymous unions are enabled by default */ |
| AnnaBridge | 167:e84263d55307 | 132 | #elif defined(__TASKING__) |
| AnnaBridge | 167:e84263d55307 | 133 | #pragma warning 586 |
| AnnaBridge | 167:e84263d55307 | 134 | #else |
| AnnaBridge | 167:e84263d55307 | 135 | #warning Not supported compiler type |
| AnnaBridge | 167:e84263d55307 | 136 | #endif |
| AnnaBridge | 167:e84263d55307 | 137 | |
| AnnaBridge | 167:e84263d55307 | 138 | /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ |
| AnnaBridge | 167:e84263d55307 | 139 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 140 | { |
| AnnaBridge | 167:e84263d55307 | 141 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ |
| AnnaBridge | 167:e84263d55307 | 142 | __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ |
| AnnaBridge | 167:e84263d55307 | 143 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ |
| AnnaBridge | 167:e84263d55307 | 144 | union { |
| AnnaBridge | 167:e84263d55307 | 145 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
| AnnaBridge | 167:e84263d55307 | 146 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 147 | }; |
| AnnaBridge | 167:e84263d55307 | 148 | __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ |
| AnnaBridge | 167:e84263d55307 | 149 | |
| AnnaBridge | 167:e84263d55307 | 150 | } CMSDK_UART_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 151 | |
| AnnaBridge | 167:e84263d55307 | 152 | /* CMSDK_UART DATA Register Definitions */ |
| AnnaBridge | 167:e84263d55307 | 153 | |
| AnnaBridge | 167:e84263d55307 | 154 | #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ |
| AnnaBridge | 167:e84263d55307 | 155 | #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ |
| AnnaBridge | 167:e84263d55307 | 156 | |
| AnnaBridge | 167:e84263d55307 | 157 | #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ |
| AnnaBridge | 167:e84263d55307 | 158 | #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ |
| AnnaBridge | 167:e84263d55307 | 159 | |
| AnnaBridge | 167:e84263d55307 | 160 | #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ |
| AnnaBridge | 167:e84263d55307 | 161 | #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ |
| AnnaBridge | 167:e84263d55307 | 162 | |
| AnnaBridge | 167:e84263d55307 | 163 | #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ |
| AnnaBridge | 167:e84263d55307 | 164 | #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ |
| AnnaBridge | 167:e84263d55307 | 165 | |
| AnnaBridge | 167:e84263d55307 | 166 | #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ |
| AnnaBridge | 167:e84263d55307 | 167 | #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ |
| AnnaBridge | 167:e84263d55307 | 168 | |
| AnnaBridge | 167:e84263d55307 | 169 | #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ |
| AnnaBridge | 167:e84263d55307 | 170 | #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ |
| AnnaBridge | 167:e84263d55307 | 171 | |
| AnnaBridge | 167:e84263d55307 | 172 | #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ |
| AnnaBridge | 167:e84263d55307 | 173 | #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 174 | |
| AnnaBridge | 167:e84263d55307 | 175 | #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ |
| AnnaBridge | 167:e84263d55307 | 176 | #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 177 | |
| AnnaBridge | 167:e84263d55307 | 178 | #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ |
| AnnaBridge | 167:e84263d55307 | 179 | #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 180 | |
| AnnaBridge | 167:e84263d55307 | 181 | #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ |
| AnnaBridge | 167:e84263d55307 | 182 | #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 183 | |
| AnnaBridge | 167:e84263d55307 | 184 | #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ |
| AnnaBridge | 167:e84263d55307 | 185 | #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 186 | |
| AnnaBridge | 167:e84263d55307 | 187 | #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ |
| AnnaBridge | 167:e84263d55307 | 188 | #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 189 | |
| AnnaBridge | 167:e84263d55307 | 190 | #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ |
| AnnaBridge | 167:e84263d55307 | 191 | #define CMSDK_UART_INTSTATUS_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ |
| AnnaBridge | 167:e84263d55307 | 192 | |
| AnnaBridge | 167:e84263d55307 | 193 | #define CMSDK_UART_INTSTATUS_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ |
| AnnaBridge | 167:e84263d55307 | 194 | #define CMSDK_UART_INTSTATUS_TXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ |
| AnnaBridge | 167:e84263d55307 | 195 | |
| AnnaBridge | 167:e84263d55307 | 196 | #define CMSDK_UART_INTSTATUS_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ |
| AnnaBridge | 167:e84263d55307 | 197 | #define CMSDK_UART_INTSTATUS_RXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ |
| AnnaBridge | 167:e84263d55307 | 198 | |
| AnnaBridge | 167:e84263d55307 | 199 | #define CMSDK_UART_INTSTATUS_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ |
| AnnaBridge | 167:e84263d55307 | 200 | #define CMSDK_UART_INTSTATUS_TXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ |
| AnnaBridge | 167:e84263d55307 | 201 | |
| AnnaBridge | 167:e84263d55307 | 202 | #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ |
| AnnaBridge | 167:e84263d55307 | 203 | #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ |
| AnnaBridge | 167:e84263d55307 | 204 | |
| AnnaBridge | 167:e84263d55307 | 205 | |
| AnnaBridge | 167:e84263d55307 | 206 | /*----------------------------- Timer (TIMER) -------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 207 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 208 | { |
| AnnaBridge | 167:e84263d55307 | 209 | __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ |
| AnnaBridge | 167:e84263d55307 | 210 | __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ |
| AnnaBridge | 167:e84263d55307 | 211 | __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ |
| AnnaBridge | 167:e84263d55307 | 212 | union { |
| AnnaBridge | 167:e84263d55307 | 213 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
| AnnaBridge | 167:e84263d55307 | 214 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 215 | }; |
| AnnaBridge | 167:e84263d55307 | 216 | |
| AnnaBridge | 167:e84263d55307 | 217 | } CMSDK_TIMER_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 218 | |
| AnnaBridge | 167:e84263d55307 | 219 | /* CMSDK_TIMER CTRL Register Definitions */ |
| AnnaBridge | 167:e84263d55307 | 220 | |
| AnnaBridge | 167:e84263d55307 | 221 | #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ |
| AnnaBridge | 167:e84263d55307 | 222 | #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 223 | |
| AnnaBridge | 167:e84263d55307 | 224 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ |
| AnnaBridge | 167:e84263d55307 | 225 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ |
| AnnaBridge | 167:e84263d55307 | 226 | |
| AnnaBridge | 167:e84263d55307 | 227 | #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ |
| AnnaBridge | 167:e84263d55307 | 228 | #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 229 | |
| AnnaBridge | 167:e84263d55307 | 230 | #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ |
| AnnaBridge | 167:e84263d55307 | 231 | #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ |
| AnnaBridge | 167:e84263d55307 | 232 | |
| AnnaBridge | 167:e84263d55307 | 233 | #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ |
| AnnaBridge | 167:e84263d55307 | 234 | #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ |
| AnnaBridge | 167:e84263d55307 | 235 | |
| AnnaBridge | 167:e84263d55307 | 236 | #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ |
| AnnaBridge | 167:e84263d55307 | 237 | #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ |
| AnnaBridge | 167:e84263d55307 | 238 | |
| AnnaBridge | 167:e84263d55307 | 239 | #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ |
| AnnaBridge | 167:e84263d55307 | 240 | #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ |
| AnnaBridge | 167:e84263d55307 | 241 | |
| AnnaBridge | 167:e84263d55307 | 242 | #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ |
| AnnaBridge | 167:e84263d55307 | 243 | #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ |
| AnnaBridge | 167:e84263d55307 | 244 | |
| AnnaBridge | 167:e84263d55307 | 245 | |
| AnnaBridge | 167:e84263d55307 | 246 | /*------------- Timer (TIM) --------------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 247 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 248 | { |
| AnnaBridge | 167:e84263d55307 | 249 | __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ |
| AnnaBridge | 167:e84263d55307 | 250 | __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ |
| AnnaBridge | 167:e84263d55307 | 251 | __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ |
| AnnaBridge | 167:e84263d55307 | 252 | __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ |
| AnnaBridge | 167:e84263d55307 | 253 | __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ |
| AnnaBridge | 167:e84263d55307 | 254 | __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ |
| AnnaBridge | 167:e84263d55307 | 255 | __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ |
| AnnaBridge | 167:e84263d55307 | 256 | uint32_t RESERVED0; |
| AnnaBridge | 167:e84263d55307 | 257 | __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ |
| AnnaBridge | 167:e84263d55307 | 258 | __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ |
| AnnaBridge | 167:e84263d55307 | 259 | __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ |
| AnnaBridge | 167:e84263d55307 | 260 | __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ |
| AnnaBridge | 167:e84263d55307 | 261 | __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ |
| AnnaBridge | 167:e84263d55307 | 262 | __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ |
| AnnaBridge | 167:e84263d55307 | 263 | __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ |
| AnnaBridge | 167:e84263d55307 | 264 | uint32_t RESERVED1[945]; |
| AnnaBridge | 167:e84263d55307 | 265 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ |
| AnnaBridge | 167:e84263d55307 | 266 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ |
| AnnaBridge | 167:e84263d55307 | 267 | } CMSDK_DUALTIMER_BOTH_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 268 | |
| AnnaBridge | 167:e84263d55307 | 269 | #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ |
| AnnaBridge | 167:e84263d55307 | 270 | #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ |
| AnnaBridge | 167:e84263d55307 | 271 | |
| AnnaBridge | 167:e84263d55307 | 272 | #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ |
| AnnaBridge | 167:e84263d55307 | 273 | #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ |
| AnnaBridge | 167:e84263d55307 | 274 | |
| AnnaBridge | 167:e84263d55307 | 275 | #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ |
| AnnaBridge | 167:e84263d55307 | 276 | #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 277 | |
| AnnaBridge | 167:e84263d55307 | 278 | #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ |
| AnnaBridge | 167:e84263d55307 | 279 | #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ |
| AnnaBridge | 167:e84263d55307 | 280 | |
| AnnaBridge | 167:e84263d55307 | 281 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ |
| AnnaBridge | 167:e84263d55307 | 282 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 283 | |
| AnnaBridge | 167:e84263d55307 | 284 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ |
| AnnaBridge | 167:e84263d55307 | 285 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| AnnaBridge | 167:e84263d55307 | 286 | |
| AnnaBridge | 167:e84263d55307 | 287 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ |
| AnnaBridge | 167:e84263d55307 | 288 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ |
| AnnaBridge | 167:e84263d55307 | 289 | |
| AnnaBridge | 167:e84263d55307 | 290 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| AnnaBridge | 167:e84263d55307 | 291 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| AnnaBridge | 167:e84263d55307 | 292 | |
| AnnaBridge | 167:e84263d55307 | 293 | #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ |
| AnnaBridge | 167:e84263d55307 | 294 | #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ |
| AnnaBridge | 167:e84263d55307 | 295 | |
| AnnaBridge | 167:e84263d55307 | 296 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ |
| AnnaBridge | 167:e84263d55307 | 297 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 298 | |
| AnnaBridge | 167:e84263d55307 | 299 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ |
| AnnaBridge | 167:e84263d55307 | 300 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 301 | |
| AnnaBridge | 167:e84263d55307 | 302 | #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ |
| AnnaBridge | 167:e84263d55307 | 303 | #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ |
| AnnaBridge | 167:e84263d55307 | 304 | |
| AnnaBridge | 167:e84263d55307 | 305 | #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ |
| AnnaBridge | 167:e84263d55307 | 306 | #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ |
| AnnaBridge | 167:e84263d55307 | 307 | |
| AnnaBridge | 167:e84263d55307 | 308 | #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ |
| AnnaBridge | 167:e84263d55307 | 309 | #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ |
| AnnaBridge | 167:e84263d55307 | 310 | |
| AnnaBridge | 167:e84263d55307 | 311 | #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ |
| AnnaBridge | 167:e84263d55307 | 312 | #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 313 | |
| AnnaBridge | 167:e84263d55307 | 314 | #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ |
| AnnaBridge | 167:e84263d55307 | 315 | #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ |
| AnnaBridge | 167:e84263d55307 | 316 | |
| AnnaBridge | 167:e84263d55307 | 317 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ |
| AnnaBridge | 167:e84263d55307 | 318 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 319 | |
| AnnaBridge | 167:e84263d55307 | 320 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ |
| AnnaBridge | 167:e84263d55307 | 321 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| AnnaBridge | 167:e84263d55307 | 322 | |
| AnnaBridge | 167:e84263d55307 | 323 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ |
| AnnaBridge | 167:e84263d55307 | 324 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ |
| AnnaBridge | 167:e84263d55307 | 325 | |
| AnnaBridge | 167:e84263d55307 | 326 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| AnnaBridge | 167:e84263d55307 | 327 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| AnnaBridge | 167:e84263d55307 | 328 | |
| AnnaBridge | 167:e84263d55307 | 329 | #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ |
| AnnaBridge | 167:e84263d55307 | 330 | #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ |
| AnnaBridge | 167:e84263d55307 | 331 | |
| AnnaBridge | 167:e84263d55307 | 332 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ |
| AnnaBridge | 167:e84263d55307 | 333 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 334 | |
| AnnaBridge | 167:e84263d55307 | 335 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ |
| AnnaBridge | 167:e84263d55307 | 336 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 337 | |
| AnnaBridge | 167:e84263d55307 | 338 | #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ |
| AnnaBridge | 167:e84263d55307 | 339 | #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ |
| AnnaBridge | 167:e84263d55307 | 340 | |
| AnnaBridge | 167:e84263d55307 | 341 | |
| AnnaBridge | 167:e84263d55307 | 342 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 343 | { |
| AnnaBridge | 167:e84263d55307 | 344 | __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ |
| AnnaBridge | 167:e84263d55307 | 345 | __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ |
| AnnaBridge | 167:e84263d55307 | 346 | __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ |
| AnnaBridge | 167:e84263d55307 | 347 | __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ |
| AnnaBridge | 167:e84263d55307 | 348 | __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ |
| AnnaBridge | 167:e84263d55307 | 349 | __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ |
| AnnaBridge | 167:e84263d55307 | 350 | __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ |
| AnnaBridge | 167:e84263d55307 | 351 | } CMSDK_DUALTIMER_SINGLE_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 352 | |
| AnnaBridge | 167:e84263d55307 | 353 | #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ |
| AnnaBridge | 167:e84263d55307 | 354 | #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ |
| AnnaBridge | 167:e84263d55307 | 355 | |
| AnnaBridge | 167:e84263d55307 | 356 | #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ |
| AnnaBridge | 167:e84263d55307 | 357 | #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ |
| AnnaBridge | 167:e84263d55307 | 358 | |
| AnnaBridge | 167:e84263d55307 | 359 | #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ |
| AnnaBridge | 167:e84263d55307 | 360 | #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 361 | |
| AnnaBridge | 167:e84263d55307 | 362 | #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ |
| AnnaBridge | 167:e84263d55307 | 363 | #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ |
| AnnaBridge | 167:e84263d55307 | 364 | |
| AnnaBridge | 167:e84263d55307 | 365 | #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ |
| AnnaBridge | 167:e84263d55307 | 366 | #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 367 | |
| AnnaBridge | 167:e84263d55307 | 368 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ |
| AnnaBridge | 167:e84263d55307 | 369 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| AnnaBridge | 167:e84263d55307 | 370 | |
| AnnaBridge | 167:e84263d55307 | 371 | #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ |
| AnnaBridge | 167:e84263d55307 | 372 | #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ |
| AnnaBridge | 167:e84263d55307 | 373 | |
| AnnaBridge | 167:e84263d55307 | 374 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| AnnaBridge | 167:e84263d55307 | 375 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| AnnaBridge | 167:e84263d55307 | 376 | |
| AnnaBridge | 167:e84263d55307 | 377 | #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ |
| AnnaBridge | 167:e84263d55307 | 378 | #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ |
| AnnaBridge | 167:e84263d55307 | 379 | |
| AnnaBridge | 167:e84263d55307 | 380 | #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ |
| AnnaBridge | 167:e84263d55307 | 381 | #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 382 | |
| AnnaBridge | 167:e84263d55307 | 383 | #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ |
| AnnaBridge | 167:e84263d55307 | 384 | #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 385 | |
| AnnaBridge | 167:e84263d55307 | 386 | #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ |
| AnnaBridge | 167:e84263d55307 | 387 | #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ |
| AnnaBridge | 167:e84263d55307 | 388 | |
| AnnaBridge | 167:e84263d55307 | 389 | |
| AnnaBridge | 167:e84263d55307 | 390 | /*-------------------- General Purpose Input Output (GPIO) -------------------*/ |
| AnnaBridge | 167:e84263d55307 | 391 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 392 | { |
| AnnaBridge | 167:e84263d55307 | 393 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ |
| AnnaBridge | 167:e84263d55307 | 394 | __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ |
| AnnaBridge | 167:e84263d55307 | 395 | uint32_t RESERVED0[2]; |
| AnnaBridge | 167:e84263d55307 | 396 | __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ |
| AnnaBridge | 167:e84263d55307 | 397 | __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 398 | __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ |
| AnnaBridge | 167:e84263d55307 | 399 | __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 400 | __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ |
| AnnaBridge | 167:e84263d55307 | 401 | __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 402 | __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ |
| AnnaBridge | 167:e84263d55307 | 403 | __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 404 | __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ |
| AnnaBridge | 167:e84263d55307 | 405 | __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 406 | union { |
| AnnaBridge | 167:e84263d55307 | 407 | __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ |
| AnnaBridge | 167:e84263d55307 | 408 | __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 409 | }; |
| AnnaBridge | 167:e84263d55307 | 410 | uint32_t RESERVED1[241]; |
| AnnaBridge | 167:e84263d55307 | 411 | __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ |
| AnnaBridge | 167:e84263d55307 | 412 | __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ |
| AnnaBridge | 167:e84263d55307 | 413 | } CMSDK_GPIO_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 414 | |
| AnnaBridge | 167:e84263d55307 | 415 | #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ |
| AnnaBridge | 167:e84263d55307 | 416 | #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ |
| AnnaBridge | 167:e84263d55307 | 417 | |
| AnnaBridge | 167:e84263d55307 | 418 | #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ |
| AnnaBridge | 167:e84263d55307 | 419 | #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ |
| AnnaBridge | 167:e84263d55307 | 420 | |
| AnnaBridge | 167:e84263d55307 | 421 | #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
| AnnaBridge | 167:e84263d55307 | 422 | #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 423 | |
| AnnaBridge | 167:e84263d55307 | 424 | #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
| AnnaBridge | 167:e84263d55307 | 425 | #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 426 | |
| AnnaBridge | 167:e84263d55307 | 427 | #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
| AnnaBridge | 167:e84263d55307 | 428 | #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
| AnnaBridge | 167:e84263d55307 | 429 | |
| AnnaBridge | 167:e84263d55307 | 430 | #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
| AnnaBridge | 167:e84263d55307 | 431 | #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
| AnnaBridge | 167:e84263d55307 | 432 | |
| AnnaBridge | 167:e84263d55307 | 433 | #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
| AnnaBridge | 167:e84263d55307 | 434 | #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 435 | |
| AnnaBridge | 167:e84263d55307 | 436 | #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
| AnnaBridge | 167:e84263d55307 | 437 | #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
| AnnaBridge | 167:e84263d55307 | 438 | |
| AnnaBridge | 167:e84263d55307 | 439 | #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
| AnnaBridge | 167:e84263d55307 | 440 | #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
| AnnaBridge | 167:e84263d55307 | 441 | |
| AnnaBridge | 167:e84263d55307 | 442 | #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
| AnnaBridge | 167:e84263d55307 | 443 | #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
| AnnaBridge | 167:e84263d55307 | 444 | |
| AnnaBridge | 167:e84263d55307 | 445 | #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
| AnnaBridge | 167:e84263d55307 | 446 | #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
| AnnaBridge | 167:e84263d55307 | 447 | |
| AnnaBridge | 167:e84263d55307 | 448 | #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
| AnnaBridge | 167:e84263d55307 | 449 | #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
| AnnaBridge | 167:e84263d55307 | 450 | |
| AnnaBridge | 167:e84263d55307 | 451 | #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ |
| AnnaBridge | 167:e84263d55307 | 452 | #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ |
| AnnaBridge | 167:e84263d55307 | 453 | |
| AnnaBridge | 167:e84263d55307 | 454 | #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ |
| AnnaBridge | 167:e84263d55307 | 455 | #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ |
| AnnaBridge | 167:e84263d55307 | 456 | |
| AnnaBridge | 167:e84263d55307 | 457 | #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ |
| AnnaBridge | 167:e84263d55307 | 458 | #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ |
| AnnaBridge | 167:e84263d55307 | 459 | |
| AnnaBridge | 167:e84263d55307 | 460 | #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ |
| AnnaBridge | 167:e84263d55307 | 461 | #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ |
| AnnaBridge | 167:e84263d55307 | 462 | |
| AnnaBridge | 167:e84263d55307 | 463 | /* GPIO Alternate function pin numbers */ |
| AnnaBridge | 167:e84263d55307 | 464 | #define CMSDK_GPIO_ALTFUNC_SH0_UART2_RX 0 /* Shield 0 UART 2 Rx */ |
| AnnaBridge | 167:e84263d55307 | 465 | #define CMSDK_GPIO_ALTFUNC_SH0_UART2_RX_SET (CMSDK_GPIO_ALTFUNC_SH0_UART2_RX % 16) |
| AnnaBridge | 167:e84263d55307 | 466 | #define CMSDK_GPIO_SH0_UART2_RX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_UART2_RX / 16) |
| AnnaBridge | 167:e84263d55307 | 467 | |
| AnnaBridge | 167:e84263d55307 | 468 | #define CMSDK_GPIO_ALTFUNC_SH0_UART2_TX 4 /* Shield 0 UART 2 Tx */ |
| AnnaBridge | 167:e84263d55307 | 469 | #define CMSDK_GPIO_ALTFUNC_SH0_UART2_TX_SET (CMSDK_GPIO_ALTFUNC_SH0_UART2_TX % 16) |
| AnnaBridge | 167:e84263d55307 | 470 | #define CMSDK_GPIO_SH0_UART2_TX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_UART2_TX / 16) |
| AnnaBridge | 167:e84263d55307 | 471 | |
| AnnaBridge | 167:e84263d55307 | 472 | #define CMSDK_GPIO_ALTFUNC_SH1_UART3_RX 26 /* Shield 1 UART 3 Rx */ |
| AnnaBridge | 167:e84263d55307 | 473 | #define CMSDK_GPIO_ALTFUNC_SH1_UART3_RX_SET (CMSDK_GPIO_ALTFUNC_SH1_UART3_RX % 16) |
| AnnaBridge | 167:e84263d55307 | 474 | #define CMSDK_GPIO_SH1_UART3_RX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_UART3_RX / 16) |
| AnnaBridge | 167:e84263d55307 | 475 | |
| AnnaBridge | 167:e84263d55307 | 476 | #define CMSDK_GPIO_ALTFUNC_SH1_UART3_TX 30 /* Shield 1 UART 3 Tx */ |
| AnnaBridge | 167:e84263d55307 | 477 | #define CMSDK_GPIO_ALTFUNC_SH1_UART3_TX_SET (CMSDK_GPIO_ALTFUNC_SH1_UART3_TX % 16) |
| AnnaBridge | 167:e84263d55307 | 478 | #define CMSDK_GPIO_SH1_UART3_TX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_UART3_TX / 16) |
| AnnaBridge | 167:e84263d55307 | 479 | |
| AnnaBridge | 167:e84263d55307 | 480 | #define CMSDK_GPIO_ALTFUNC_UART4_RX 23 /* UART 4 Rx */ |
| AnnaBridge | 167:e84263d55307 | 481 | #define CMSDK_GPIO_ALTFUNC_UART4_RX_SET (CMSDK_GPIO_ALTFUNC_UART4_RX % 16) |
| AnnaBridge | 167:e84263d55307 | 482 | #define CMSDK_GPIO_UART4_RX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_UART4_RX / 16) |
| AnnaBridge | 167:e84263d55307 | 483 | |
| AnnaBridge | 167:e84263d55307 | 484 | #define CMSDK_GPIO_ALTFUNC_UART4_TX 24 /* UART 4 Tx */ |
| AnnaBridge | 167:e84263d55307 | 485 | #define CMSDK_GPIO_ALTFUNC_UART4_TX_SET (CMSDK_GPIO_ALTFUNC_UART4_TX % 16) |
| AnnaBridge | 167:e84263d55307 | 486 | #define CMSDK_GPIO_UART4_TX_GPIO_NUM (CMSDK_GPIO_ALTFUNC_UART4_TX / 16) |
| AnnaBridge | 167:e84263d55307 | 487 | |
| AnnaBridge | 167:e84263d55307 | 488 | #define CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C 5 /* Shield 0 SCL I2S */ |
| AnnaBridge | 167:e84263d55307 | 489 | #define CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C_SET (CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C % 16) |
| AnnaBridge | 167:e84263d55307 | 490 | #define CMSDK_GPIO_SH0_SCL_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C / 16) |
| AnnaBridge | 167:e84263d55307 | 491 | |
| AnnaBridge | 167:e84263d55307 | 492 | #define CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C 15 /* Shield 0 SDA I2S */ |
| AnnaBridge | 167:e84263d55307 | 493 | #define CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C_SET (CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C % 16) |
| AnnaBridge | 167:e84263d55307 | 494 | #define CMSDK_GPIO_SH0_SDA_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C / 16) |
| AnnaBridge | 167:e84263d55307 | 495 | |
| AnnaBridge | 167:e84263d55307 | 496 | #define CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C 31 /* Shield 1 SCL I2S */ |
| AnnaBridge | 167:e84263d55307 | 497 | #define CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C_SET (CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C % 16) |
| AnnaBridge | 167:e84263d55307 | 498 | #define CMSDK_GPIO_SH1_SCL_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C / 16) |
| AnnaBridge | 167:e84263d55307 | 499 | |
| AnnaBridge | 167:e84263d55307 | 500 | #define CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C 41 /* Shield 1 SDA I2S */ |
| AnnaBridge | 167:e84263d55307 | 501 | #define CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C_SET (CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C % 16) |
| AnnaBridge | 167:e84263d55307 | 502 | #define CMSDK_GPIO_SH1_SDA_I2C_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C / 16) |
| AnnaBridge | 167:e84263d55307 | 503 | |
| AnnaBridge | 167:e84263d55307 | 504 | #define CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI 11 /* Shield 0 SCK SPI */ |
| AnnaBridge | 167:e84263d55307 | 505 | #define CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 506 | #define CMSDK_GPIO_SH0_SCK_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 507 | |
| AnnaBridge | 167:e84263d55307 | 508 | #define CMSDK_GPIO_ALTFUNC_SH0_CS_SPI 12 /* Shield 0 CS SPI */ |
| AnnaBridge | 167:e84263d55307 | 509 | #define CMSDK_GPIO_ALTFUNC_SH0_CS_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_CS_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 510 | #define CMSDK_GPIO_SH0_CS_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_CS_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 511 | |
| AnnaBridge | 167:e84263d55307 | 512 | #define CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI 13 /* Shield 0 MOSI SPI */ |
| AnnaBridge | 167:e84263d55307 | 513 | #define CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 514 | #define CMSDK_GPIO_SH0_MOSI_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 515 | |
| AnnaBridge | 167:e84263d55307 | 516 | #define CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI 14 /* Shield 0 MISO SPI */ |
| AnnaBridge | 167:e84263d55307 | 517 | #define CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI_SET (CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 518 | #define CMSDK_GPIO_SH0_MISO_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 519 | |
| AnnaBridge | 167:e84263d55307 | 520 | #define CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI 44 /* Shield 1 SCK SPI */ |
| AnnaBridge | 167:e84263d55307 | 521 | #define CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 522 | #define CMSDK_GPIO_SH1_SCK_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 523 | |
| AnnaBridge | 167:e84263d55307 | 524 | #define CMSDK_GPIO_ALTFUNC_SH1_CS_SPI 38 /* Shield 1 CS SPI */ |
| AnnaBridge | 167:e84263d55307 | 525 | #define CMSDK_GPIO_ALTFUNC_SH1_CS_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_CS_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 526 | #define CMSDK_GPIO_SH1_CS_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_CS_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 527 | |
| AnnaBridge | 167:e84263d55307 | 528 | #define CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI 39 /* Shield 1 MOSI SPI */ |
| AnnaBridge | 167:e84263d55307 | 529 | #define CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 530 | #define CMSDK_GPIO_SH1_MOSI_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 531 | |
| AnnaBridge | 167:e84263d55307 | 532 | #define CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI 40 /* Shield 1 MISO SPI */ |
| AnnaBridge | 167:e84263d55307 | 533 | #define CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI_SET (CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 534 | #define CMSDK_GPIO_SH1_MISO_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 535 | |
| AnnaBridge | 167:e84263d55307 | 536 | #define CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI 19 /* Shield ADC SCK SPI */ |
| AnnaBridge | 167:e84263d55307 | 537 | #define CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 538 | #define CMSDK_GPIO_ADC_SCK_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 539 | |
| AnnaBridge | 167:e84263d55307 | 540 | #define CMSDK_GPIO_ALTFUNC_ADC_CS_SPI 16 /* Shield ADC CS SPI */ |
| AnnaBridge | 167:e84263d55307 | 541 | #define CMSDK_GPIO_ALTFUNC_ADC_CS_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_CS_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 542 | #define CMSDK_GPIO_ADC_CS_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_CS_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 543 | |
| AnnaBridge | 167:e84263d55307 | 544 | #define CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI 18 /* Shield ADC MOSI SPI */ |
| AnnaBridge | 167:e84263d55307 | 545 | #define CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 546 | #define CMSDK_GPIO_ADC_MOSI_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 547 | |
| AnnaBridge | 167:e84263d55307 | 548 | #define CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI 17 /* Shield ADC MISO SPI */ |
| AnnaBridge | 167:e84263d55307 | 549 | #define CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI_SET (CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI % 16) |
| AnnaBridge | 167:e84263d55307 | 550 | #define CMSDK_GPIO_ADC_MISO_SPI_GPIO_NUM (CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI / 16) |
| AnnaBridge | 167:e84263d55307 | 551 | |
| AnnaBridge | 167:e84263d55307 | 552 | /*------------- System Control (SYSCON) --------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 553 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 554 | { |
| AnnaBridge | 167:e84263d55307 | 555 | __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ |
| AnnaBridge | 167:e84263d55307 | 556 | __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ |
| AnnaBridge | 167:e84263d55307 | 557 | __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ |
| AnnaBridge | 167:e84263d55307 | 558 | __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ |
| AnnaBridge | 167:e84263d55307 | 559 | __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ |
| AnnaBridge | 167:e84263d55307 | 560 | uint32_t RESERVED0[3]; |
| AnnaBridge | 167:e84263d55307 | 561 | __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */ |
| AnnaBridge | 167:e84263d55307 | 562 | __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */ |
| AnnaBridge | 167:e84263d55307 | 563 | uint32_t RESERVED1[2]; |
| AnnaBridge | 167:e84263d55307 | 564 | __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */ |
| AnnaBridge | 167:e84263d55307 | 565 | __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */ |
| AnnaBridge | 167:e84263d55307 | 566 | uint32_t RESERVED2[2]; |
| AnnaBridge | 167:e84263d55307 | 567 | __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */ |
| AnnaBridge | 167:e84263d55307 | 568 | __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */ |
| AnnaBridge | 167:e84263d55307 | 569 | __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */ |
| AnnaBridge | 167:e84263d55307 | 570 | __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */ |
| AnnaBridge | 167:e84263d55307 | 571 | __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */ |
| AnnaBridge | 167:e84263d55307 | 572 | __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */ |
| AnnaBridge | 167:e84263d55307 | 573 | uint32_t RESERVED3[10]; |
| AnnaBridge | 167:e84263d55307 | 574 | __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */ |
| AnnaBridge | 167:e84263d55307 | 575 | __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */ |
| AnnaBridge | 167:e84263d55307 | 576 | __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 577 | __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 578 | __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 579 | __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 580 | uint32_t RESERVED4[2]; |
| AnnaBridge | 167:e84263d55307 | 581 | __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */ |
| AnnaBridge | 167:e84263d55307 | 582 | __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */ |
| AnnaBridge | 167:e84263d55307 | 583 | __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 584 | __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 585 | __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 586 | __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */ |
| AnnaBridge | 167:e84263d55307 | 587 | uint32_t RESERVED5[2]; |
| AnnaBridge | 167:e84263d55307 | 588 | __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */ |
| AnnaBridge | 167:e84263d55307 | 589 | __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */ |
| AnnaBridge | 167:e84263d55307 | 590 | __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */ |
| AnnaBridge | 167:e84263d55307 | 591 | __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */ |
| AnnaBridge | 167:e84263d55307 | 592 | __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */ |
| AnnaBridge | 167:e84263d55307 | 593 | __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */ |
| AnnaBridge | 167:e84263d55307 | 594 | __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */ |
| AnnaBridge | 167:e84263d55307 | 595 | __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */ |
| AnnaBridge | 167:e84263d55307 | 596 | __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */ |
| AnnaBridge | 167:e84263d55307 | 597 | __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */ |
| AnnaBridge | 167:e84263d55307 | 598 | uint32_t RESERVED6[2]; |
| AnnaBridge | 167:e84263d55307 | 599 | __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */ |
| AnnaBridge | 167:e84263d55307 | 600 | __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */ |
| AnnaBridge | 167:e84263d55307 | 601 | __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */ |
| AnnaBridge | 167:e84263d55307 | 602 | uint32_t RESERVED7[1]; |
| AnnaBridge | 167:e84263d55307 | 603 | __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */ |
| AnnaBridge | 167:e84263d55307 | 604 | __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */ |
| AnnaBridge | 167:e84263d55307 | 605 | __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */ |
| AnnaBridge | 167:e84263d55307 | 606 | } CMSDK_SYSCON_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 607 | |
| AnnaBridge | 167:e84263d55307 | 608 | #define CMSDK_SYSCON_REMAP_Pos 0 |
| AnnaBridge | 167:e84263d55307 | 609 | #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ |
| AnnaBridge | 167:e84263d55307 | 610 | |
| AnnaBridge | 167:e84263d55307 | 611 | #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 |
| AnnaBridge | 167:e84263d55307 | 612 | #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ |
| AnnaBridge | 167:e84263d55307 | 613 | |
| AnnaBridge | 167:e84263d55307 | 614 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 |
| AnnaBridge | 167:e84263d55307 | 615 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ |
| AnnaBridge | 167:e84263d55307 | 616 | |
| AnnaBridge | 167:e84263d55307 | 617 | #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 |
| AnnaBridge | 167:e84263d55307 | 618 | #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ |
| AnnaBridge | 167:e84263d55307 | 619 | |
| AnnaBridge | 167:e84263d55307 | 620 | #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 |
| AnnaBridge | 167:e84263d55307 | 621 | #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ |
| AnnaBridge | 167:e84263d55307 | 622 | |
| AnnaBridge | 167:e84263d55307 | 623 | #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 |
| AnnaBridge | 167:e84263d55307 | 624 | #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ |
| AnnaBridge | 167:e84263d55307 | 625 | |
| AnnaBridge | 167:e84263d55307 | 626 | #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 |
| AnnaBridge | 167:e84263d55307 | 627 | #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ |
| AnnaBridge | 167:e84263d55307 | 628 | |
| AnnaBridge | 167:e84263d55307 | 629 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 |
| AnnaBridge | 167:e84263d55307 | 630 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ |
| AnnaBridge | 167:e84263d55307 | 631 | |
| AnnaBridge | 167:e84263d55307 | 632 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 |
| AnnaBridge | 167:e84263d55307 | 633 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ |
| AnnaBridge | 167:e84263d55307 | 634 | |
| AnnaBridge | 167:e84263d55307 | 635 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 |
| AnnaBridge | 167:e84263d55307 | 636 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ |
| AnnaBridge | 167:e84263d55307 | 637 | |
| AnnaBridge | 168:9672193075cf | 638 | /*------------------- WATCHDOG ----------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 639 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 640 | { |
| AnnaBridge | 167:e84263d55307 | 641 | |
| AnnaBridge | 167:e84263d55307 | 642 | __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ |
| AnnaBridge | 167:e84263d55307 | 643 | __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ |
| AnnaBridge | 167:e84263d55307 | 644 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ |
| AnnaBridge | 167:e84263d55307 | 645 | __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ |
| AnnaBridge | 167:e84263d55307 | 646 | __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ |
| AnnaBridge | 167:e84263d55307 | 647 | __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ |
| AnnaBridge | 167:e84263d55307 | 648 | uint32_t RESERVED0[762]; |
| AnnaBridge | 167:e84263d55307 | 649 | __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ |
| AnnaBridge | 167:e84263d55307 | 650 | uint32_t RESERVED1[191]; |
| AnnaBridge | 167:e84263d55307 | 651 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ |
| AnnaBridge | 167:e84263d55307 | 652 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ |
| AnnaBridge | 167:e84263d55307 | 653 | }CMSDK_WATCHDOG_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 654 | |
| AnnaBridge | 168:9672193075cf | 655 | #define CMSDK_WATCHDOG_LOAD_Pos 0 /* CMSDK_WATCHDOG LOAD: LOAD Position */ |
| AnnaBridge | 168:9672193075cf | 656 | #define CMSDK_WATCHDOG_LOAD_Msk (0xFFFFFFFFul << CMSDK_WATCHDOG_LOAD_Pos) /* CMSDK_WATCHDOG LOAD: LOAD Mask */ |
| AnnaBridge | 167:e84263d55307 | 657 | |
| AnnaBridge | 168:9672193075cf | 658 | #define CMSDK_WATCHDOG_VALUE_Pos 0 /* CMSDK_WATCHDOG VALUE: VALUE Position */ |
| AnnaBridge | 168:9672193075cf | 659 | #define CMSDK_WATCHDOG_VALUE_Msk (0xFFFFFFFFul << CMSDK_WATCHDOG_VALUE_Pos) /* CMSDK_WATCHDOG VALUE: VALUE Mask */ |
| AnnaBridge | 167:e84263d55307 | 660 | |
| AnnaBridge | 168:9672193075cf | 661 | #define CMSDK_WATCHDOG_CTRL_RESEN_Pos 1 /* CMSDK_WATCHDOG CTRL_RESEN: Enable Reset Output Position */ |
| AnnaBridge | 168:9672193075cf | 662 | #define CMSDK_WATCHDOG_CTRL_RESEN_Msk (0x1ul << CMSDK_WATCHDOG_CTRL_RESEN_Pos) /* CMSDK_WATCHDOG CTRL_RESEN: Enable Reset Output Mask */ |
| AnnaBridge | 167:e84263d55307 | 663 | |
| AnnaBridge | 168:9672193075cf | 664 | #define CMSDK_WATCHDOG_CTRL_INTEN_Pos 0 /* CMSDK_WATCHDOG CTRL_INTEN: Int Enable Position */ |
| AnnaBridge | 168:9672193075cf | 665 | #define CMSDK_WATCHDOG_CTRL_INTEN_Msk (0x1ul << CMSDK_WATCHDOG_CTRL_INTEN_Pos) /* CMSDK_WATCHDOG CTRL_INTEN: Int Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 666 | |
| AnnaBridge | 168:9672193075cf | 667 | #define CMSDK_WATCHDOG_INTCLR_Pos 0 /* CMSDK_WATCHDOG INTCLR: Int Clear Position */ |
| AnnaBridge | 168:9672193075cf | 668 | #define CMSDK_WATCHDOG_INTCLR_Msk (0x1ul << CMSDK_WATCHDOG_INTCLR_Pos) /* CMSDK_WATCHDOG INTCLR: Int Clear Mask */ |
| AnnaBridge | 167:e84263d55307 | 669 | |
| AnnaBridge | 168:9672193075cf | 670 | #define CMSDK_WATCHDOG_RAWINTSTAT_Pos 0 /* CMSDK_WATCHDOG RAWINTSTAT: Raw Int Status Position */ |
| AnnaBridge | 168:9672193075cf | 671 | #define CMSDK_WATCHDOG_RAWINTSTAT_Msk (0x1ul << CMSDK_WATCHDOG_RAWINTSTAT_Pos) /* CMSDK_WATCHDOG RAWINTSTAT: Raw Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 672 | |
| AnnaBridge | 168:9672193075cf | 673 | #define CMSDK_WATCHDOG_MASKINTSTAT_Pos 0 /* CMSDK_WATCHDOG MASKINTSTAT: Mask Int Status Position */ |
| AnnaBridge | 168:9672193075cf | 674 | #define CMSDK_WATCHDOG_MASKINTSTAT_Msk (0x1ul << CMSDK_WATCHDOG_MASKINTSTAT_Pos) /* CMSDK_WATCHDOG MASKINTSTAT: Mask Int Status Mask */ |
| AnnaBridge | 167:e84263d55307 | 675 | |
| AnnaBridge | 168:9672193075cf | 676 | #define CMSDK_WATCHDOG_LOCK_Pos 0 /* CMSDK_WATCHDOG LOCK: LOCK Position */ |
| AnnaBridge | 168:9672193075cf | 677 | #define CMSDK_WATCHDOG_LOCK_Msk (0x1ul << CMSDK_WATCHDOG_LOCK_Pos) /* CMSDK_WATCHDOG LOCK: LOCK Mask */ |
| AnnaBridge | 167:e84263d55307 | 678 | |
| AnnaBridge | 168:9672193075cf | 679 | #define CMSDK_WATCHDOG_INTEGTESTEN_Pos 0 /* CMSDK_WATCHDOG INTEGTESTEN: Integration Test Enable Position */ |
| AnnaBridge | 168:9672193075cf | 680 | #define CMSDK_WATCHDOG_INTEGTESTEN_Msk (0x1ul << CMSDK_WATCHDOG_INTEGTESTEN_Pos) /* CMSDK_WATCHDOG INTEGTESTEN: Integration Test Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 681 | |
| AnnaBridge | 168:9672193075cf | 682 | #define CMSDK_WATCHDOG_INTEGTESTOUTSET_Pos 1 /* CMSDK_WATCHDOG INTEGTESTOUTSET: Integration Test Output Set Position */ |
| AnnaBridge | 168:9672193075cf | 683 | #define CMSDK_WATCHDOG_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_WATCHDOG_INTEGTESTOUTSET_Pos) /* CMSDK_WATCHDOG INTEGTESTOUTSET: Integration Test Output Set Mask */ |
| AnnaBridge | 167:e84263d55307 | 684 | |
| AnnaBridge | 167:e84263d55307 | 685 | /*------------------------- Real Time Clock(RTC) ----------------------------------------------*/ |
| AnnaBridge | 167:e84263d55307 | 686 | typedef struct |
| AnnaBridge | 167:e84263d55307 | 687 | { |
| AnnaBridge | 167:e84263d55307 | 688 | __I uint32_t RTCDR; /* 0x00 RO RTC Data Register */ |
| AnnaBridge | 167:e84263d55307 | 689 | __IO uint32_t RTCMR; /* 0x04 RW RTC Match Register */ |
| AnnaBridge | 167:e84263d55307 | 690 | __IO uint32_t RTCLR; /* 0x08 RW RTC Load Register */ |
| AnnaBridge | 167:e84263d55307 | 691 | __IO uint32_t RTCCR; /* 0x0C RW RTC Control Register */ |
| AnnaBridge | 167:e84263d55307 | 692 | __IO uint32_t RTCIMSC; /* 0x10 RW RTC Inerrupt Mask Set and Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 693 | __I uint32_t RTCRIS; /* 0x14 RO RTC Raw Inerrupt Status Register */ |
| AnnaBridge | 167:e84263d55307 | 694 | __I uint32_t RTCMIS; /* 0x18 RO RTC Masked Inerrupt Status Register */ |
| AnnaBridge | 167:e84263d55307 | 695 | __O uint32_t RTCICR; /* 0x1C WO RTC Interrupt Clear Register */ |
| AnnaBridge | 167:e84263d55307 | 696 | } CMSDK_RTC_TypeDef; |
| AnnaBridge | 167:e84263d55307 | 697 | |
| AnnaBridge | 168:9672193075cf | 698 | #define CMSDK_RTC_ENABLE_Pos 0 /* CMSDK_RTC Enable: Real Time Clock Enable Position */ |
| AnnaBridge | 168:9672193075cf | 699 | #define CMSDK_RTC_ENABLE_Msk (0x1ul << CMSDK_RTC_ENABLE_Pos) /* CMSDK_RTC Enable: Real Time Clock Enable Mask */ |
| AnnaBridge | 167:e84263d55307 | 700 | |
| AnnaBridge | 167:e84263d55307 | 701 | /* -------------------- End of section using anonymous unions ------------------- */ |
| AnnaBridge | 167:e84263d55307 | 702 | #if defined ( __CC_ARM ) |
| AnnaBridge | 167:e84263d55307 | 703 | #pragma pop |
| AnnaBridge | 167:e84263d55307 | 704 | #elif defined(__ICCARM__) |
| AnnaBridge | 167:e84263d55307 | 705 | /* leave anonymous unions enabled */ |
| AnnaBridge | 167:e84263d55307 | 706 | #elif defined(__GNUC__) |
| AnnaBridge | 167:e84263d55307 | 707 | /* anonymous unions are enabled by default */ |
| AnnaBridge | 167:e84263d55307 | 708 | #elif defined(__TMS470__) |
| AnnaBridge | 167:e84263d55307 | 709 | /* anonymous unions are enabled by default */ |
| AnnaBridge | 167:e84263d55307 | 710 | #elif defined(__TASKING__) |
| AnnaBridge | 167:e84263d55307 | 711 | #pragma warning restore |
| AnnaBridge | 167:e84263d55307 | 712 | #else |
| AnnaBridge | 167:e84263d55307 | 713 | #warning Not supported compiler type |
| AnnaBridge | 167:e84263d55307 | 714 | #endif |
| AnnaBridge | 167:e84263d55307 | 715 | |
| AnnaBridge | 167:e84263d55307 | 716 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 717 | /* ================ Peripheral memory map ================ */ |
| AnnaBridge | 167:e84263d55307 | 718 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 719 | |
| AnnaBridge | 167:e84263d55307 | 720 | /* Peripheral and SRAM base address */ |
| AnnaBridge | 167:e84263d55307 | 721 | #define CMSDK_FLASH_BASE (0x00000000UL) |
| AnnaBridge | 167:e84263d55307 | 722 | #define CMSDK_SRAM_BASE (0x20000000UL) |
| AnnaBridge | 167:e84263d55307 | 723 | #define CMSDK_PERIPH_BASE (0x40000000UL) |
| AnnaBridge | 167:e84263d55307 | 724 | |
| AnnaBridge | 167:e84263d55307 | 725 | #define CMSDK_RAM_BASE (0x20000000UL) |
| AnnaBridge | 167:e84263d55307 | 726 | #define CMSDK_APB_BASE (0x40000000UL) |
| AnnaBridge | 167:e84263d55307 | 727 | #define CMSDK_AHB_BASE (0x40010000UL) |
| AnnaBridge | 167:e84263d55307 | 728 | |
| AnnaBridge | 167:e84263d55307 | 729 | /* APB peripherals */ |
| AnnaBridge | 167:e84263d55307 | 730 | #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) |
| AnnaBridge | 167:e84263d55307 | 731 | #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) |
| AnnaBridge | 167:e84263d55307 | 732 | #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) |
| AnnaBridge | 167:e84263d55307 | 733 | #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) |
| AnnaBridge | 167:e84263d55307 | 734 | #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) |
| AnnaBridge | 167:e84263d55307 | 735 | #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) |
| AnnaBridge | 167:e84263d55307 | 736 | #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) |
| AnnaBridge | 167:e84263d55307 | 737 | #define CMSDK_UART2_BASE (0x4002C000UL) |
| AnnaBridge | 167:e84263d55307 | 738 | #define CMSDK_UART3_BASE (0x4002D000UL) |
| AnnaBridge | 167:e84263d55307 | 739 | #define CMSDK_UART4_BASE (0x4002E000UL) |
| AnnaBridge | 167:e84263d55307 | 740 | #define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0x6000UL) |
| AnnaBridge | 167:e84263d55307 | 741 | #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) |
| AnnaBridge | 167:e84263d55307 | 742 | |
| AnnaBridge | 167:e84263d55307 | 743 | /* AHB peripherals */ |
| AnnaBridge | 167:e84263d55307 | 744 | #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) |
| AnnaBridge | 167:e84263d55307 | 745 | #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) |
| AnnaBridge | 167:e84263d55307 | 746 | #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) |
| AnnaBridge | 167:e84263d55307 | 747 | #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) |
| AnnaBridge | 167:e84263d55307 | 748 | #define CMSDK_GPIO4_BASE (0x40030000UL) |
| AnnaBridge | 167:e84263d55307 | 749 | #define CMSDK_GPIO5_BASE (0x40031000UL) |
| AnnaBridge | 167:e84263d55307 | 750 | #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) |
| AnnaBridge | 167:e84263d55307 | 751 | |
| AnnaBridge | 167:e84263d55307 | 752 | |
| AnnaBridge | 167:e84263d55307 | 753 | |
| AnnaBridge | 167:e84263d55307 | 754 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 755 | /* ================ Peripheral declaration ================ */ |
| AnnaBridge | 167:e84263d55307 | 756 | /* ================================================================================ */ |
| AnnaBridge | 167:e84263d55307 | 757 | |
| AnnaBridge | 168:9672193075cf | 758 | #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) |
| AnnaBridge | 168:9672193075cf | 759 | #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) |
| AnnaBridge | 168:9672193075cf | 760 | #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) |
| AnnaBridge | 168:9672193075cf | 761 | #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) |
| AnnaBridge | 168:9672193075cf | 762 | #define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE ) |
| AnnaBridge | 168:9672193075cf | 763 | #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) |
| AnnaBridge | 168:9672193075cf | 764 | #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) |
| AnnaBridge | 167:e84263d55307 | 765 | #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) |
| AnnaBridge | 167:e84263d55307 | 766 | #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) |
| AnnaBridge | 167:e84263d55307 | 767 | #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) |
| AnnaBridge | 167:e84263d55307 | 768 | #define CMSDK_RTC ((CMSDK_RTC_TypeDef *) CMSDK_RTC_BASE ) |
| AnnaBridge | 168:9672193075cf | 769 | #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) |
| AnnaBridge | 168:9672193075cf | 770 | #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) |
| AnnaBridge | 168:9672193075cf | 771 | #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) |
| AnnaBridge | 167:e84263d55307 | 772 | #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) |
| AnnaBridge | 167:e84263d55307 | 773 | #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) |
| AnnaBridge | 167:e84263d55307 | 774 | #define CMSDK_GPIO4 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO4_BASE ) |
| AnnaBridge | 167:e84263d55307 | 775 | #define CMSDK_GPIO5 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO5_BASE ) |
| AnnaBridge | 167:e84263d55307 | 776 | #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) |
| AnnaBridge | 167:e84263d55307 | 777 | |
| AnnaBridge | 167:e84263d55307 | 778 | #ifdef __cplusplus |
| AnnaBridge | 167:e84263d55307 | 779 | } |
| AnnaBridge | 167:e84263d55307 | 780 | #endif |
| AnnaBridge | 167:e84263d55307 | 781 | |
| AnnaBridge | 167:e84263d55307 | 782 | #endif /* CMSDK_BEETLE_H */ |