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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_spi_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended SPI HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities SPI extension peripheral:
<> 144:ef7eb2e8f9f7 11 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 ******************************************************************************
<> 144:ef7eb2e8f9f7 14 * @attention
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 44 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @defgroup SPI_Private_Variables SPI Private Variables
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58 /* Variable used to determine if device is impacted by implementation of workaround
<> 144:ef7eb2e8f9f7 59 related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
<> 144:ef7eb2e8f9f7 60 - STM32F101CDE/STM32F103CDE
<> 144:ef7eb2e8f9f7 61 - Revision ID : Z
<> 144:ef7eb2e8f9f7 62 - SPI2
<> 144:ef7eb2e8f9f7 63 - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
<> 144:ef7eb2e8f9f7 64 the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
<> 144:ef7eb2e8f9f7 65 + If the value is 0, the complete data transfer is successful.
<> 144:ef7eb2e8f9f7 66 + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
<> 144:ef7eb2e8f9f7 67 If CRCERR is found reset, the complete data transfer is considered successful.
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69 uint8_t uCRCErrorWorkaroundCheck = 0;
<> 144:ef7eb2e8f9f7 70 /**
<> 144:ef7eb2e8f9f7 71 * @}
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @addtogroup SPI_Exported_Functions
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @addtogroup SPI_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @brief Initializes the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 93 * in the SPI_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 94 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 95 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 96 * @retval HAL status
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 /* Check the SPI handle allocation */
<> 144:ef7eb2e8f9f7 101 if(hspi == NULL)
<> 144:ef7eb2e8f9f7 102 {
<> 144:ef7eb2e8f9f7 103 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* Check the parameters */
<> 144:ef7eb2e8f9f7 107 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 108 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 109 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 110 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 111 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 144:ef7eb2e8f9f7 112 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 144:ef7eb2e8f9f7 113 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 114 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 115 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 116 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 117 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 144:ef7eb2e8f9f7 118 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 if(hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 121 {
<> 144:ef7eb2e8f9f7 122 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 123 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Disble the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 129 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 132 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
<> 144:ef7eb2e8f9f7 133 Communication speed, First bit and CRC calculation state */
<> 144:ef7eb2e8f9f7 134 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
<> 144:ef7eb2e8f9f7 135 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 144:ef7eb2e8f9f7 136 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Configure : NSS management */
<> 144:ef7eb2e8f9f7 139 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 142 /* Configure : CRC Polynomial */
<> 144:ef7eb2e8f9f7 143 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 #if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 146 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 144:ef7eb2e8f9f7 147 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 144:ef7eb2e8f9f7 148 #endif
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #if defined (STM32F101xE) || defined (STM32F103xE)
<> 144:ef7eb2e8f9f7 151 /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
<> 144:ef7eb2e8f9f7 152 CRC errors wrongly detected */
<> 144:ef7eb2e8f9f7 153 /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
<> 144:ef7eb2e8f9f7 154 Revision ID information is only available in Debug mode, so Workaround could not be implemented
<> 144:ef7eb2e8f9f7 155 to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
<> 144:ef7eb2e8f9f7 156 So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
<> 144:ef7eb2e8f9f7 157 uCRCErrorWorkaroundCheck = 0;
<> 144:ef7eb2e8f9f7 158 #else
<> 144:ef7eb2e8f9f7 159 uCRCErrorWorkaroundCheck = 0;
<> 144:ef7eb2e8f9f7 160 #endif
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 163 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 return HAL_OK;
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @addtogroup SPI_Private_Functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
<> 144:ef7eb2e8f9f7 182 * according to SPI instance, Device type, and revision ID.
<> 144:ef7eb2e8f9f7 183 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 184 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 185 * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 #if defined (STM32F101xE) || defined (STM32F103xE)
<> 144:ef7eb2e8f9f7 190 /* Check how to handle this CRC error (workaround to be applied or not) */
<> 144:ef7eb2e8f9f7 191 /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
<> 144:ef7eb2e8f9f7 192 if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) )
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 if (hspi->Instance->RXCRCR == 0)
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 return (SPI_INVALID_CRC_ERROR);
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199 return (SPI_VALID_CRC_ERROR);
<> 144:ef7eb2e8f9f7 200 #else
<> 144:ef7eb2e8f9f7 201 return (SPI_VALID_CRC_ERROR);
<> 144:ef7eb2e8f9f7 202 #endif
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @}
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @}
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/