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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 20 (except for internal SRAM / FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 21 necessary) please refer to Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 22 and DMA requests.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) For a given Channel, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 25 Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 26 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
<> 144:ef7eb2e8f9f7 27 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 30 detection.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 35 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 36 =================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 39 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 40 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 41 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 44 ===================================
<> 144:ef7eb2e8f9f7 45 [..]
<> 144:ef7eb2e8f9f7 46 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 47 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 48 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 49 Source address and destination address and the Length of data to be transferred.
<> 144:ef7eb2e8f9f7 50 In this case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 51 (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 52 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 53 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 54 XferErrorCallback (i.e a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 57 =============================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 62 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 63 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 64 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 65 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 66 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 67 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 [..]
<> 144:ef7eb2e8f9f7 70 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 @endverbatim
<> 144:ef7eb2e8f9f7 73 ******************************************************************************
<> 144:ef7eb2e8f9f7 74 * @attention
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 79 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 80 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 81 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 82 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 83 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 84 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 85 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 86 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 87 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 90 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 91 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 92 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 93 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 94 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 95 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 96 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 97 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 98 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 ******************************************************************************
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 104 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 111 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 112 * @{
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup DMA_Private_Constants DMA Private Constants
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 145 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 @verbatim
<> 144:ef7eb2e8f9f7 148 ===============================================================================
<> 144:ef7eb2e8f9f7 149 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 150 ===============================================================================
<> 144:ef7eb2e8f9f7 151 [..]
<> 144:ef7eb2e8f9f7 152 This section provides functions allowing to initialize the DMA Channel source
<> 144:ef7eb2e8f9f7 153 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 154 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 155 [..]
<> 144:ef7eb2e8f9f7 156 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 157 reference manual.
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 @endverbatim
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief Initializes the DMA according to the specified
<> 144:ef7eb2e8f9f7 165 * parameters in the DMA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 166 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 167 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 168 * @retval HAL status
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 175 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Check the parameters */
<> 144:ef7eb2e8f9f7 181 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 183 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 if(hdma->State == HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 193 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 197 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 200 tmp = hdma->Instance->CCR;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 144:ef7eb2e8f9f7 203 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 204 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 205 DMA_CCR_DIR));
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 208 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 209 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 210 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 211 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Write to DMA Channel CR register */
<> 144:ef7eb2e8f9f7 214 hdma->Instance->CCR = tmp;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 217 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Initialize the DMA state*/
<> 144:ef7eb2e8f9f7 220 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 return HAL_OK;
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @brief DeInitializes the DMA peripheral
<> 144:ef7eb2e8f9f7 227 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 228 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 229 * @retval HAL status
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 234 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Check the parameters */
<> 144:ef7eb2e8f9f7 240 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 243 if(hdma->State == HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Disable the selected DMA Channelx */
<> 144:ef7eb2e8f9f7 249 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Reset DMA Channel control register */
<> 144:ef7eb2e8f9f7 252 hdma->Instance->CCR = 0;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Reset DMA Channel Number of Data to Transfer register */
<> 144:ef7eb2e8f9f7 255 hdma->Instance->CNDTR = 0;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Reset DMA Channel peripheral address register */
<> 144:ef7eb2e8f9f7 258 hdma->Instance->CPAR = 0;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Reset DMA Channel memory address register */
<> 144:ef7eb2e8f9f7 261 hdma->Instance->CMAR = 0;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Clear all flags */
<> 144:ef7eb2e8f9f7 264 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 265 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 266 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 269 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 272 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Release Lock */
<> 144:ef7eb2e8f9f7 275 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 return HAL_OK;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @}
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 285 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 286 *
<> 144:ef7eb2e8f9f7 287 @verbatim
<> 144:ef7eb2e8f9f7 288 ===============================================================================
<> 144:ef7eb2e8f9f7 289 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 290 ===============================================================================
<> 144:ef7eb2e8f9f7 291 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 292 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 293 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 294 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 295 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 296 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 297 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 @endverbatim
<> 144:ef7eb2e8f9f7 300 * @{
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @brief Starts the DMA Transfer.
<> 144:ef7eb2e8f9f7 305 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 306 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 307 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 308 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 309 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 310 * @retval HAL status
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* Process locked */
<> 144:ef7eb2e8f9f7 315 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 318 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Check the parameters */
<> 144:ef7eb2e8f9f7 321 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 324 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 327 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 330 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 return HAL_OK;
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 337 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 338 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 339 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 340 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 341 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 342 * @retval HAL status
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 /* Process locked */
<> 144:ef7eb2e8f9f7 347 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 350 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Check the parameters */
<> 144:ef7eb2e8f9f7 353 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 356 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 359 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Enable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 362 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Enable the Half transfer complete interrupt */
<> 144:ef7eb2e8f9f7 365 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Enable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 368 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 371 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 return HAL_OK;
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 * @brief Aborts the DMA Transfer.
<> 144:ef7eb2e8f9f7 378 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 379 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 380 *
<> 144:ef7eb2e8f9f7 381 * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
<> 144:ef7eb2e8f9f7 382 * effectively disabled is added. If a Channel is disabled
<> 144:ef7eb2e8f9f7 383 * while a data transfer is ongoing, the current data will be transferred
<> 144:ef7eb2e8f9f7 384 * and the Channel will be effectively disabled only after the transfer of
<> 144:ef7eb2e8f9f7 385 * this single data is finished.
<> 144:ef7eb2e8f9f7 386 * @retval HAL status
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 uint32_t tickstart = 0x00;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Disable the channel */
<> 144:ef7eb2e8f9f7 393 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Get tick */
<> 144:ef7eb2e8f9f7 396 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Check if the DMA Channel is effectively disabled */
<> 144:ef7eb2e8f9f7 399 while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 402 if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 /* Update error code */
<> 144:ef7eb2e8f9f7 405 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 408 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 411 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 417 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 420 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 return HAL_OK;
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /**
<> 144:ef7eb2e8f9f7 426 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 427 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 428 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 429 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 430 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 431 * @retval HAL status
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 uint32_t temp;
<> 144:ef7eb2e8f9f7 436 uint32_t tickstart = 0x00;
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 439 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 442 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444 else
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 447 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Get tick */
<> 144:ef7eb2e8f9f7 451 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 /* Clear the transfer error flags */
<> 144:ef7eb2e8f9f7 458 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Update error code */
<> 144:ef7eb2e8f9f7 461 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 464 hdma->State= HAL_DMA_STATE_ERROR;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 467 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 472 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 /* Update error code */
<> 144:ef7eb2e8f9f7 477 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 480 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 483 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 493 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 496 all transfers are complete) */
<> 144:ef7eb2e8f9f7 497 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 else
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 503 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 506 all transfers of half buffer are complete) */
<> 144:ef7eb2e8f9f7 507 hdma->State = HAL_DMA_STATE_READY_HALF;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Process unlocked */
<> 144:ef7eb2e8f9f7 511 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 return HAL_OK;
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @brief Handles DMA interrupt request.
<> 144:ef7eb2e8f9f7 518 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 519 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 520 * @retval None
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* Transfer Error Interrupt management ***************************************/
<> 144:ef7eb2e8f9f7 525 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 526 {
<> 144:ef7eb2e8f9f7 527 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* Disable the transfer error interrupt */
<> 144:ef7eb2e8f9f7 530 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 533 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Update error code */
<> 144:ef7eb2e8f9f7 536 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 539 hdma->State = HAL_DMA_STATE_ERROR;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 542 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 if (hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 547 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 553 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 558 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 561 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 564 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 567 hdma->State = HAL_DMA_STATE_READY_HALF;
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 572 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 578 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 /* Disable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 585 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 588 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* Update error code */
<> 144:ef7eb2e8f9f7 591 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 594 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 597 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 602 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604 }
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @}
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
<> 144:ef7eb2e8f9f7 613 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 614 *
<> 144:ef7eb2e8f9f7 615 @verbatim
<> 144:ef7eb2e8f9f7 616 ===============================================================================
<> 144:ef7eb2e8f9f7 617 ##### State and Errors functions #####
<> 144:ef7eb2e8f9f7 618 ===============================================================================
<> 144:ef7eb2e8f9f7 619 [..]
<> 144:ef7eb2e8f9f7 620 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 621 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 622 (+) Get error code
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 @endverbatim
<> 144:ef7eb2e8f9f7 625 * @{
<> 144:ef7eb2e8f9f7 626 */
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @brief Returns the DMA state.
<> 144:ef7eb2e8f9f7 630 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 631 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 632 * @retval HAL state
<> 144:ef7eb2e8f9f7 633 */
<> 144:ef7eb2e8f9f7 634 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 return hdma->State;
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @brief Return the DMA error code
<> 144:ef7eb2e8f9f7 641 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 642 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 643 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /**
<> 144:ef7eb2e8f9f7 651 * @}
<> 144:ef7eb2e8f9f7 652 */
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /**
<> 144:ef7eb2e8f9f7 655 * @}
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /** @addtogroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 659 * @{
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /**
<> 144:ef7eb2e8f9f7 663 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 664 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 665 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 666 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 667 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 668 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 669 * @retval HAL status
<> 144:ef7eb2e8f9f7 670 */
<> 144:ef7eb2e8f9f7 671 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 674 hdma->Instance->CNDTR = DataLength;
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 677 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 680 hdma->Instance->CPAR = DstAddress;
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 683 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 686 else
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 689 hdma->Instance->CPAR = SrcAddress;
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 692 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @}
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @}
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @}
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/