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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
154:37f96f9d4de2 
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 8 * module driver.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @attention
<> 144:ef7eb2e8f9f7 11 *
AnnaBridge 165:e614a9f1c9e2 12 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 15 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 20 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 22 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 23 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 ******************************************************************************
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #ifndef __STM32F1xx_HAL_H
<> 144:ef7eb2e8f9f7 41 #define __STM32F1xx_HAL_H
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f1xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup HAL
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 67 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 68 * Note: On devices STM32F10xx8 and STM32F10xxB,
<> 144:ef7eb2e8f9f7 69 * STM32F101xC/D/E and STM32F103xC/D/E,
<> 144:ef7eb2e8f9f7 70 * STM32F101xF/G and STM32F103xF/G
<> 144:ef7eb2e8f9f7 71 * STM32F10xx4 and STM32F10xx6
<> 144:ef7eb2e8f9f7 72 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
<> 144:ef7eb2e8f9f7 73 * debug mode (not accessible by the user software in normal mode).
<> 144:ef7eb2e8f9f7 74 * Refer to errata sheet of these devices for more details.
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /* Peripherals on APB1 */
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @brief TIM2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 83 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /**
<> 144:ef7eb2e8f9f7 86 * @brief TIM3 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 89 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #if defined (DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @brief TIM4 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 96 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 97 #endif
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #if defined (DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @brief TIM5 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 104 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 105 #endif
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #if defined (DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 108 /**
<> 144:ef7eb2e8f9f7 109 * @brief TIM6 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 112 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 113 #endif
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #if defined (DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief TIM7 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 120 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 121 #endif
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 #if defined (DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief TIM12 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 128 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 129 #endif
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 #if defined (DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief TIM13 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 136 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 137 #endif
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #if defined (DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @brief TIM14 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 144 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @brief WWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 151 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @brief IWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 157 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief I2C1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 163 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @brief I2C2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 170 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 171 #endif
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #if defined (DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @brief CAN1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 178 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 179 #endif
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #if defined (DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @brief CAN2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 186 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 187 #endif
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Peripherals on APB2 */
<> 144:ef7eb2e8f9f7 190 #if defined (DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief TIM1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 195 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 196 #endif
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 #if defined (DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @brief TIM8 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 203 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 204 #endif
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 #if defined (DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief TIM9 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 211 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 212 #endif
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 #if defined (DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief TIM10 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 219 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 220 #endif
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #if defined (DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief TIM11 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 227 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 228 #endif
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 #if defined (DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @brief TIM15 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 236 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 237 #endif
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 #if defined (DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief TIM16 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 244 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 245 #endif
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 #if defined (DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief TIM17 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 252 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 253 #endif
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 264 /** @addtogroup HAL_Exported_Functions
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 /** @addtogroup HAL_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 271 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 272 HAL_StatusTypeDef HAL_DeInit(void);
AnnaBridge 165:e614a9f1c9e2 273 void HAL_MspInit(void);
AnnaBridge 165:e614a9f1c9e2 274 void HAL_MspDeInit(void);
<> 144:ef7eb2e8f9f7 275 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @addtogroup HAL_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 281 * @{
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 /* Peripheral Control functions ************************************************/
AnnaBridge 165:e614a9f1c9e2 284 void HAL_IncTick(void);
AnnaBridge 165:e614a9f1c9e2 285 void HAL_Delay(__IO uint32_t Delay);
AnnaBridge 165:e614a9f1c9e2 286 uint32_t HAL_GetTick(void);
AnnaBridge 165:e614a9f1c9e2 287 void HAL_SuspendTick(void);
AnnaBridge 165:e614a9f1c9e2 288 void HAL_ResumeTick(void);
AnnaBridge 165:e614a9f1c9e2 289 uint32_t HAL_GetHalVersion(void);
AnnaBridge 165:e614a9f1c9e2 290 uint32_t HAL_GetREVID(void);
AnnaBridge 165:e614a9f1c9e2 291 uint32_t HAL_GetDEVID(void);
AnnaBridge 165:e614a9f1c9e2 292 void HAL_DBGMCU_EnableDBGSleepMode(void);
AnnaBridge 165:e614a9f1c9e2 293 void HAL_DBGMCU_DisableDBGSleepMode(void);
AnnaBridge 165:e614a9f1c9e2 294 void HAL_DBGMCU_EnableDBGStopMode(void);
AnnaBridge 165:e614a9f1c9e2 295 void HAL_DBGMCU_DisableDBGStopMode(void);
AnnaBridge 165:e614a9f1c9e2 296 void HAL_DBGMCU_EnableDBGStandbyMode(void);
AnnaBridge 165:e614a9f1c9e2 297 void HAL_DBGMCU_DisableDBGStandbyMode(void);
AnnaBridge 165:e614a9f1c9e2 298 void HAL_GetUID(uint32_t *UID);
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
AnnaBridge 165:e614a9f1c9e2 306 /* Private types -------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 307 /* Private variables ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 308 /** @defgroup HAL_Private_Variables HAL Private Variables
AnnaBridge 165:e614a9f1c9e2 309 * @{
AnnaBridge 165:e614a9f1c9e2 310 */
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
AnnaBridge 165:e614a9f1c9e2 313 */
AnnaBridge 165:e614a9f1c9e2 314 /* Private constants ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 315 /** @defgroup HAL_Private_Constants HAL Private Constants
AnnaBridge 165:e614a9f1c9e2 316 * @{
AnnaBridge 165:e614a9f1c9e2 317 */
AnnaBridge 165:e614a9f1c9e2 318 /**
AnnaBridge 165:e614a9f1c9e2 319 * @}
AnnaBridge 165:e614a9f1c9e2 320 */
AnnaBridge 165:e614a9f1c9e2 321 /* Private macros ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 322 /* Private functions ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 323 /**
AnnaBridge 165:e614a9f1c9e2 324 * @}
AnnaBridge 165:e614a9f1c9e2 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @}
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333 #endif
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 #endif /* __STM32F1xx_HAL_H */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/