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targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.S@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
158:b23ee177fd68 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;********************** COPYRIGHT(c) 2016 STMicroelectronics ******************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32l476xx.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
<> 144:ef7eb2e8f9f7 4 ;* Version : V1.1.1
<> 144:ef7eb2e8f9f7 5 ;* Date : 29-April-2016
<> 144:ef7eb2e8f9f7 6 ;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 7 ;* This module performs:
<> 144:ef7eb2e8f9f7 8 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 9 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 10 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 11 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 12 ;* calls main()).
<> 144:ef7eb2e8f9f7 13 ;* After Reset the Cortex-M4 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 14 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 15 ;* <<< Use Configuration Wizard in Context Menu >>>
<> 144:ef7eb2e8f9f7 16 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 17 ;*
<> 144:ef7eb2e8f9f7 18 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 ;*
<> 144:ef7eb2e8f9f7 29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 ;
<> 144:ef7eb2e8f9f7 40 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 43 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 __initial_sp EQU 0x20018000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 48 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 49 ; </h>
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 Heap_Size EQU 0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler)
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 54 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 55 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 __heap_base
<> 144:ef7eb2e8f9f7 58 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 59 __heap_limit
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 PRESERVE8
<> 144:ef7eb2e8f9f7 62 THUMB
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 66 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 67 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 68 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 69 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 72 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 73 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 74 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 75 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 76 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 77 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 78 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 79 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 80 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 81 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 82 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 83 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 84 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 85 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 86 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 ; External Interrupts
<> 144:ef7eb2e8f9f7 89 DCD WWDG_IRQHandler ; Window WatchDog
<> 144:ef7eb2e8f9f7 90 DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
<> 144:ef7eb2e8f9f7 91 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
<> 144:ef7eb2e8f9f7 92 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
<> 144:ef7eb2e8f9f7 93 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 94 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 95 DCD EXTI0_IRQHandler ; EXTI Line0
<> 144:ef7eb2e8f9f7 96 DCD EXTI1_IRQHandler ; EXTI Line1
<> 144:ef7eb2e8f9f7 97 DCD EXTI2_IRQHandler ; EXTI Line2
<> 144:ef7eb2e8f9f7 98 DCD EXTI3_IRQHandler ; EXTI Line3
<> 144:ef7eb2e8f9f7 99 DCD EXTI4_IRQHandler ; EXTI Line4
<> 144:ef7eb2e8f9f7 100 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
<> 144:ef7eb2e8f9f7 101 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
<> 144:ef7eb2e8f9f7 102 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
<> 144:ef7eb2e8f9f7 103 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
<> 144:ef7eb2e8f9f7 104 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
<> 144:ef7eb2e8f9f7 105 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
<> 144:ef7eb2e8f9f7 106 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
<> 144:ef7eb2e8f9f7 107 DCD ADC1_2_IRQHandler ; ADC1, ADC2
<> 144:ef7eb2e8f9f7 108 DCD CAN1_TX_IRQHandler ; CAN1 TX
<> 144:ef7eb2e8f9f7 109 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
<> 144:ef7eb2e8f9f7 110 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
<> 144:ef7eb2e8f9f7 111 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
<> 144:ef7eb2e8f9f7 112 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
<> 144:ef7eb2e8f9f7 113 DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
<> 144:ef7eb2e8f9f7 114 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
<> 144:ef7eb2e8f9f7 115 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
<> 144:ef7eb2e8f9f7 116 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
<> 144:ef7eb2e8f9f7 117 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 118 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 119 DCD TIM4_IRQHandler ; TIM4
<> 144:ef7eb2e8f9f7 120 DCD I2C1_EV_IRQHandler ; I2C1 Event
<> 144:ef7eb2e8f9f7 121 DCD I2C1_ER_IRQHandler ; I2C1 Error
<> 144:ef7eb2e8f9f7 122 DCD I2C2_EV_IRQHandler ; I2C2 Event
<> 144:ef7eb2e8f9f7 123 DCD I2C2_ER_IRQHandler ; I2C2 Error
<> 144:ef7eb2e8f9f7 124 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 125 DCD SPI2_IRQHandler ; SPI2
<> 144:ef7eb2e8f9f7 126 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 127 DCD USART2_IRQHandler ; USART2
<> 144:ef7eb2e8f9f7 128 DCD USART3_IRQHandler ; USART3
<> 144:ef7eb2e8f9f7 129 DCD EXTI15_10_IRQHandler ; External Line[15:10]
<> 144:ef7eb2e8f9f7 130 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
<> 144:ef7eb2e8f9f7 131 DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
<> 144:ef7eb2e8f9f7 132 DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
<> 144:ef7eb2e8f9f7 133 DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
<> 144:ef7eb2e8f9f7 134 DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
<> 144:ef7eb2e8f9f7 135 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
<> 144:ef7eb2e8f9f7 136 DCD ADC3_IRQHandler ; ADC3 global Interrupt
<> 144:ef7eb2e8f9f7 137 DCD FMC_IRQHandler ; FMC
<> 144:ef7eb2e8f9f7 138 DCD SDMMC1_IRQHandler ; SDMMC1
<> 144:ef7eb2e8f9f7 139 DCD TIM5_IRQHandler ; TIM5
<> 144:ef7eb2e8f9f7 140 DCD SPI3_IRQHandler ; SPI3
<> 144:ef7eb2e8f9f7 141 DCD UART4_IRQHandler ; UART4
<> 144:ef7eb2e8f9f7 142 DCD UART5_IRQHandler ; UART5
<> 144:ef7eb2e8f9f7 143 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
<> 144:ef7eb2e8f9f7 144 DCD TIM7_IRQHandler ; TIM7
<> 144:ef7eb2e8f9f7 145 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
<> 144:ef7eb2e8f9f7 146 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
<> 144:ef7eb2e8f9f7 147 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
<> 144:ef7eb2e8f9f7 148 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
<> 144:ef7eb2e8f9f7 149 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
<> 144:ef7eb2e8f9f7 150 DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
<> 144:ef7eb2e8f9f7 151 DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
<> 144:ef7eb2e8f9f7 152 DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
<> 144:ef7eb2e8f9f7 153 DCD COMP_IRQHandler ; COMP Interrupt
<> 144:ef7eb2e8f9f7 154 DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
<> 144:ef7eb2e8f9f7 155 DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
<> 144:ef7eb2e8f9f7 156 DCD OTG_FS_IRQHandler ; USB OTG FS
<> 144:ef7eb2e8f9f7 157 DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
<> 144:ef7eb2e8f9f7 158 DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
<> 144:ef7eb2e8f9f7 159 DCD LPUART1_IRQHandler ; LP UART1 interrupt
<> 144:ef7eb2e8f9f7 160 DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
<> 144:ef7eb2e8f9f7 161 DCD I2C3_EV_IRQHandler ; I2C3 event
<> 144:ef7eb2e8f9f7 162 DCD I2C3_ER_IRQHandler ; I2C3 error
<> 144:ef7eb2e8f9f7 163 DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
<> 144:ef7eb2e8f9f7 164 DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
<> 144:ef7eb2e8f9f7 165 DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
<> 144:ef7eb2e8f9f7 166 DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
<> 144:ef7eb2e8f9f7 167 DCD LCD_IRQHandler ; LCD global interrupt
<> 144:ef7eb2e8f9f7 168 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 169 DCD RNG_IRQHandler ; RNG global interrupt
<> 144:ef7eb2e8f9f7 170 DCD FPU_IRQHandler ; FPU
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 __Vectors_End
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 ; Reset handler
<> 144:ef7eb2e8f9f7 179 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 180 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 181 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 182 IMPORT __main
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 185 BLX R0
<> 144:ef7eb2e8f9f7 186 LDR R0, =__main
<> 144:ef7eb2e8f9f7 187 BX R0
<> 144:ef7eb2e8f9f7 188 ENDP
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 193 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 194 B .
<> 144:ef7eb2e8f9f7 195 ENDP
<> 144:ef7eb2e8f9f7 196 HardFault_Handler\
<> 144:ef7eb2e8f9f7 197 PROC
<> 144:ef7eb2e8f9f7 198 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 199 B .
<> 144:ef7eb2e8f9f7 200 ENDP
<> 144:ef7eb2e8f9f7 201 MemManage_Handler\
<> 144:ef7eb2e8f9f7 202 PROC
<> 144:ef7eb2e8f9f7 203 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 204 B .
<> 144:ef7eb2e8f9f7 205 ENDP
<> 144:ef7eb2e8f9f7 206 BusFault_Handler\
<> 144:ef7eb2e8f9f7 207 PROC
<> 144:ef7eb2e8f9f7 208 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 209 B .
<> 144:ef7eb2e8f9f7 210 ENDP
<> 144:ef7eb2e8f9f7 211 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 212 PROC
<> 144:ef7eb2e8f9f7 213 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 214 B .
<> 144:ef7eb2e8f9f7 215 ENDP
<> 144:ef7eb2e8f9f7 216 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 217 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 218 B .
<> 144:ef7eb2e8f9f7 219 ENDP
<> 144:ef7eb2e8f9f7 220 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 221 PROC
<> 144:ef7eb2e8f9f7 222 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 223 B .
<> 144:ef7eb2e8f9f7 224 ENDP
<> 144:ef7eb2e8f9f7 225 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 226 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 227 B .
<> 144:ef7eb2e8f9f7 228 ENDP
<> 144:ef7eb2e8f9f7 229 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 230 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 231 B .
<> 144:ef7eb2e8f9f7 232 ENDP
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 Default_Handler PROC
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 237 EXPORT PVD_PVM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 238 EXPORT TAMP_STAMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 239 EXPORT RTC_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 240 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 241 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 242 EXPORT EXTI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 243 EXPORT EXTI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 244 EXPORT EXTI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 245 EXPORT EXTI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 246 EXPORT EXTI4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 247 EXPORT DMA1_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 248 EXPORT DMA1_Channel2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 249 EXPORT DMA1_Channel3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 250 EXPORT DMA1_Channel4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 251 EXPORT DMA1_Channel5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 252 EXPORT DMA1_Channel6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 253 EXPORT DMA1_Channel7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 254 EXPORT ADC1_2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 255 EXPORT CAN1_TX_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 256 EXPORT CAN1_RX0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 257 EXPORT CAN1_RX1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 258 EXPORT CAN1_SCE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 259 EXPORT EXTI9_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 260 EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 261 EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 262 EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 263 EXPORT TIM1_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 264 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 265 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 266 EXPORT TIM4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 267 EXPORT I2C1_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 268 EXPORT I2C1_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 269 EXPORT I2C2_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 270 EXPORT I2C2_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 271 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 272 EXPORT SPI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 273 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 274 EXPORT USART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 275 EXPORT USART3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 276 EXPORT EXTI15_10_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 277 EXPORT RTC_Alarm_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 278 EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 279 EXPORT TIM8_BRK_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 280 EXPORT TIM8_UP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 281 EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 282 EXPORT TIM8_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 283 EXPORT ADC3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 284 EXPORT FMC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 285 EXPORT SDMMC1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 286 EXPORT TIM5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 287 EXPORT SPI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 288 EXPORT UART4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 289 EXPORT UART5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 290 EXPORT TIM6_DAC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 291 EXPORT TIM7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 292 EXPORT DMA2_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 293 EXPORT DMA2_Channel2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 294 EXPORT DMA2_Channel3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 295 EXPORT DMA2_Channel4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 296 EXPORT DMA2_Channel5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 297 EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 298 EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 299 EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 300 EXPORT COMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 301 EXPORT LPTIM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 302 EXPORT LPTIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 303 EXPORT OTG_FS_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 304 EXPORT DMA2_Channel6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 305 EXPORT DMA2_Channel7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 306 EXPORT LPUART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 307 EXPORT QUADSPI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 308 EXPORT I2C3_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 309 EXPORT I2C3_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 310 EXPORT SAI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 311 EXPORT SAI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 312 EXPORT SWPMI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 313 EXPORT TSC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 314 EXPORT LCD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 315 EXPORT RNG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 316 EXPORT FPU_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 319 PVD_PVM_IRQHandler
<> 144:ef7eb2e8f9f7 320 TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 321 RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 322 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 323 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 324 EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 325 EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 326 EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 327 EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 328 EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 329 DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 330 DMA1_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 331 DMA1_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 332 DMA1_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 333 DMA1_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 334 DMA1_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 335 DMA1_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 336 ADC1_2_IRQHandler
<> 144:ef7eb2e8f9f7 337 CAN1_TX_IRQHandler
<> 144:ef7eb2e8f9f7 338 CAN1_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 339 CAN1_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 340 CAN1_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 341 EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 342 TIM1_BRK_TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 343 TIM1_UP_TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 344 TIM1_TRG_COM_TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 345 TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 346 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 347 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 348 TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 349 I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 350 I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 351 I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 352 I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 353 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 354 SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 355 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 356 USART2_IRQHandler
<> 144:ef7eb2e8f9f7 357 USART3_IRQHandler
<> 144:ef7eb2e8f9f7 358 EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 359 RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 360 DFSDM1_FLT3_IRQHandler
<> 144:ef7eb2e8f9f7 361 TIM8_BRK_IRQHandler
<> 144:ef7eb2e8f9f7 362 TIM8_UP_IRQHandler
<> 144:ef7eb2e8f9f7 363 TIM8_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 364 TIM8_CC_IRQHandler
<> 144:ef7eb2e8f9f7 365 ADC3_IRQHandler
<> 144:ef7eb2e8f9f7 366 FMC_IRQHandler
<> 144:ef7eb2e8f9f7 367 SDMMC1_IRQHandler
<> 144:ef7eb2e8f9f7 368 TIM5_IRQHandler
<> 144:ef7eb2e8f9f7 369 SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 370 UART4_IRQHandler
<> 144:ef7eb2e8f9f7 371 UART5_IRQHandler
<> 144:ef7eb2e8f9f7 372 TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 373 TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 374 DMA2_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 375 DMA2_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 376 DMA2_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 377 DMA2_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 378 DMA2_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 379 DFSDM1_FLT0_IRQHandler
<> 144:ef7eb2e8f9f7 380 DFSDM1_FLT1_IRQHandler
<> 144:ef7eb2e8f9f7 381 DFSDM1_FLT2_IRQHandler
<> 144:ef7eb2e8f9f7 382 COMP_IRQHandler
<> 144:ef7eb2e8f9f7 383 LPTIM1_IRQHandler
<> 144:ef7eb2e8f9f7 384 LPTIM2_IRQHandler
<> 144:ef7eb2e8f9f7 385 OTG_FS_IRQHandler
<> 144:ef7eb2e8f9f7 386 DMA2_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 387 DMA2_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 388 LPUART1_IRQHandler
<> 144:ef7eb2e8f9f7 389 QUADSPI_IRQHandler
<> 144:ef7eb2e8f9f7 390 I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 391 I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 392 SAI1_IRQHandler
<> 144:ef7eb2e8f9f7 393 SAI2_IRQHandler
<> 144:ef7eb2e8f9f7 394 SWPMI1_IRQHandler
<> 144:ef7eb2e8f9f7 395 TSC_IRQHandler
<> 144:ef7eb2e8f9f7 396 LCD_IRQHandler
<> 144:ef7eb2e8f9f7 397 RNG_IRQHandler
<> 144:ef7eb2e8f9f7 398 FPU_IRQHandler
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 B .
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 ENDP
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 ALIGN
<> 144:ef7eb2e8f9f7 405 END
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
<> 144:ef7eb2e8f9f7 408