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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_lpuart.h@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
154:37f96f9d4de2 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30 #ifndef _FSL_LPUART_H_
<> 154:37f96f9d4de2 31 #define _FSL_LPUART_H_
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 #include "fsl_common.h"
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*!
<> 154:37f96f9d4de2 36 * @addtogroup lpuart_driver
<> 154:37f96f9d4de2 37 * @{
<> 154:37f96f9d4de2 38 */
<> 154:37f96f9d4de2 39
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /*******************************************************************************
<> 154:37f96f9d4de2 42 * Definitions
<> 154:37f96f9d4de2 43 ******************************************************************************/
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /*! @name Driver version */
<> 154:37f96f9d4de2 46 /*@{*/
<> 154:37f96f9d4de2 47 /*! @brief LPUART driver version 2.2.1. */
<> 154:37f96f9d4de2 48 #define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
<> 154:37f96f9d4de2 49 /*@}*/
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 /*! @brief Error codes for the LPUART driver. */
<> 154:37f96f9d4de2 52 enum _lpuart_status
<> 154:37f96f9d4de2 53 {
<> 154:37f96f9d4de2 54 kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */
<> 154:37f96f9d4de2 55 kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */
<> 154:37f96f9d4de2 56 kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */
<> 154:37f96f9d4de2 57 kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */
<> 154:37f96f9d4de2 58 kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */
<> 154:37f96f9d4de2 59 kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */
<> 154:37f96f9d4de2 60 kStatus_LPUART_FlagCannotClearManually =
<> 154:37f96f9d4de2 61 MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
<> 154:37f96f9d4de2 62 kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
<> 154:37f96f9d4de2 63 kStatus_LPUART_RxRingBufferOverrun =
<> 154:37f96f9d4de2 64 MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
<> 154:37f96f9d4de2 65 kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
<> 154:37f96f9d4de2 66 kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */
<> 154:37f96f9d4de2 67 kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */
<> 154:37f96f9d4de2 68 kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */
<> 154:37f96f9d4de2 69 kStatus_LPUART_BaudrateNotSupport =
<> 154:37f96f9d4de2 70 MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
<> 154:37f96f9d4de2 71 };
<> 154:37f96f9d4de2 72
<> 154:37f96f9d4de2 73 /*! @brief LPUART parity mode. */
<> 154:37f96f9d4de2 74 typedef enum _lpuart_parity_mode
<> 154:37f96f9d4de2 75 {
<> 154:37f96f9d4de2 76 kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
<> 154:37f96f9d4de2 77 kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
<> 154:37f96f9d4de2 78 kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
<> 154:37f96f9d4de2 79 } lpuart_parity_mode_t;
<> 154:37f96f9d4de2 80
<> 154:37f96f9d4de2 81 /*! @brief LPUART data bits count. */
<> 154:37f96f9d4de2 82 typedef enum _lpuart_data_bits
<> 154:37f96f9d4de2 83 {
<> 154:37f96f9d4de2 84 kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
<> 154:37f96f9d4de2 85 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 86 kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
<> 154:37f96f9d4de2 87 #endif
<> 154:37f96f9d4de2 88 } lpuart_data_bits_t;
<> 154:37f96f9d4de2 89
<> 154:37f96f9d4de2 90 /*! @brief LPUART stop bit count. */
<> 154:37f96f9d4de2 91 typedef enum _lpuart_stop_bit_count
<> 154:37f96f9d4de2 92 {
<> 154:37f96f9d4de2 93 kLPUART_OneStopBit = 0U, /*!< One stop bit */
<> 154:37f96f9d4de2 94 kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
<> 154:37f96f9d4de2 95 } lpuart_stop_bit_count_t;
<> 154:37f96f9d4de2 96
<> 154:37f96f9d4de2 97 /*!
<> 154:37f96f9d4de2 98 * @brief LPUART interrupt configuration structure, default settings all disabled.
<> 154:37f96f9d4de2 99 *
<> 154:37f96f9d4de2 100 * This structure contains the settings for all LPUART interrupt configurations.
<> 154:37f96f9d4de2 101 */
<> 154:37f96f9d4de2 102 enum _lpuart_interrupt_enable
<> 154:37f96f9d4de2 103 {
<> 154:37f96f9d4de2 104 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 105 kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
<> 154:37f96f9d4de2 106 #endif
<> 154:37f96f9d4de2 107 kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
<> 154:37f96f9d4de2 108 kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */
<> 154:37f96f9d4de2 109 kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
<> 154:37f96f9d4de2 110 kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */
<> 154:37f96f9d4de2 111 kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */
<> 154:37f96f9d4de2 112 kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */
<> 154:37f96f9d4de2 113 kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */
<> 154:37f96f9d4de2 114 kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */
<> 154:37f96f9d4de2 115 kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */
<> 154:37f96f9d4de2 116 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 117 kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */
<> 154:37f96f9d4de2 118 kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
<> 154:37f96f9d4de2 119 #endif
<> 154:37f96f9d4de2 120 };
<> 154:37f96f9d4de2 121
<> 154:37f96f9d4de2 122 /*!
<> 154:37f96f9d4de2 123 * @brief LPUART status flags.
<> 154:37f96f9d4de2 124 *
<> 154:37f96f9d4de2 125 * This provides constants for the LPUART status flags for use in the LPUART functions.
<> 154:37f96f9d4de2 126 */
<> 154:37f96f9d4de2 127 enum _lpuart_flags
<> 154:37f96f9d4de2 128 {
<> 154:37f96f9d4de2 129 kLPUART_TxDataRegEmptyFlag =
<> 154:37f96f9d4de2 130 (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
<> 154:37f96f9d4de2 131 kLPUART_TransmissionCompleteFlag =
<> 154:37f96f9d4de2 132 (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
<> 154:37f96f9d4de2 133 kLPUART_RxDataRegFullFlag =
<> 154:37f96f9d4de2 134 (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
<> 154:37f96f9d4de2 135 kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
<> 154:37f96f9d4de2 136 kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is
<> 154:37f96f9d4de2 137 read from receive register */
<> 154:37f96f9d4de2 138 kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these
<> 154:37f96f9d4de2 139 samples differ, noise flag sets */
<> 154:37f96f9d4de2 140 kLPUART_FramingErrorFlag =
<> 154:37f96f9d4de2 141 (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
<> 154:37f96f9d4de2 142 kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
<> 154:37f96f9d4de2 143 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
<> 154:37f96f9d4de2 144 kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
<> 154:37f96f9d4de2 145 detected and LIN circuit enabled */
<> 154:37f96f9d4de2 146 #endif
<> 154:37f96f9d4de2 147 kLPUART_RxActiveEdgeFlag =
<> 154:37f96f9d4de2 148 (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
<> 154:37f96f9d4de2 149 kLPUART_RxActiveFlag =
<> 154:37f96f9d4de2 150 (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
<> 154:37f96f9d4de2 151 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
<> 154:37f96f9d4de2 152 kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
<> 154:37f96f9d4de2 153 kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
<> 154:37f96f9d4de2 154 #endif
<> 154:37f96f9d4de2 155 #if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
<> 154:37f96f9d4de2 156 kLPUART_NoiseErrorInRxDataRegFlag =
<> 154:37f96f9d4de2 157 (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
<> 154:37f96f9d4de2 158 kLPUART_ParityErrorInRxDataRegFlag =
<> 154:37f96f9d4de2 159 (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
<> 154:37f96f9d4de2 160 #endif
<> 154:37f96f9d4de2 161 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 162 kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
<> 154:37f96f9d4de2 163 kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
<> 154:37f96f9d4de2 164 kLPUART_TxFifoOverflowFlag =
<> 154:37f96f9d4de2 165 (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
<> 154:37f96f9d4de2 166 kLPUART_RxFifoUnderflowFlag =
<> 154:37f96f9d4de2 167 (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
<> 154:37f96f9d4de2 168 #endif
<> 154:37f96f9d4de2 169 };
<> 154:37f96f9d4de2 170
<> 154:37f96f9d4de2 171 /*! @brief LPUART configure structure. */
<> 154:37f96f9d4de2 172 typedef struct _lpuart_config
<> 154:37f96f9d4de2 173 {
<> 154:37f96f9d4de2 174 uint32_t baudRate_Bps; /*!< LPUART baud rate */
<> 154:37f96f9d4de2 175 lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
<> 154:37f96f9d4de2 176 lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
<> 154:37f96f9d4de2 177 bool isMsb; /*!< Data bits order, LSB (default), MSB */
<> 154:37f96f9d4de2 178 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 154:37f96f9d4de2 179 lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
<> 154:37f96f9d4de2 180 #endif
<> 154:37f96f9d4de2 181 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
<> 154:37f96f9d4de2 182 uint8_t txFifoWatermark; /*!< TX FIFO watermark */
<> 154:37f96f9d4de2 183 uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
<> 154:37f96f9d4de2 184 #endif
<> 154:37f96f9d4de2 185 bool enableTx; /*!< Enable TX */
<> 154:37f96f9d4de2 186 bool enableRx; /*!< Enable RX */
<> 154:37f96f9d4de2 187 } lpuart_config_t;
<> 154:37f96f9d4de2 188
<> 154:37f96f9d4de2 189 /*! @brief LPUART transfer structure. */
<> 154:37f96f9d4de2 190 typedef struct _lpuart_transfer
<> 154:37f96f9d4de2 191 {
<> 154:37f96f9d4de2 192 uint8_t *data; /*!< The buffer of data to be transfer.*/
<> 154:37f96f9d4de2 193 size_t dataSize; /*!< The byte count to be transfer. */
<> 154:37f96f9d4de2 194 } lpuart_transfer_t;
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 /* Forward declaration of the handle typedef. */
<> 154:37f96f9d4de2 197 typedef struct _lpuart_handle lpuart_handle_t;
<> 154:37f96f9d4de2 198
<> 154:37f96f9d4de2 199 /*! @brief LPUART transfer callback function. */
<> 154:37f96f9d4de2 200 typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
<> 154:37f96f9d4de2 201
<> 154:37f96f9d4de2 202 /*! @brief LPUART handle structure. */
<> 154:37f96f9d4de2 203 struct _lpuart_handle
<> 154:37f96f9d4de2 204 {
<> 154:37f96f9d4de2 205 uint8_t *volatile txData; /*!< Address of remaining data to send. */
<> 154:37f96f9d4de2 206 volatile size_t txDataSize; /*!< Size of the remaining data to send. */
<> 154:37f96f9d4de2 207 size_t txDataSizeAll; /*!< Size of the data to send out. */
<> 154:37f96f9d4de2 208 uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
<> 154:37f96f9d4de2 209 volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
<> 154:37f96f9d4de2 210 size_t rxDataSizeAll; /*!< Size of the data to receive. */
<> 154:37f96f9d4de2 211
<> 154:37f96f9d4de2 212 uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
<> 154:37f96f9d4de2 213 size_t rxRingBufferSize; /*!< Size of the ring buffer. */
<> 154:37f96f9d4de2 214 volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
<> 154:37f96f9d4de2 215 volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
<> 154:37f96f9d4de2 216
<> 154:37f96f9d4de2 217 lpuart_transfer_callback_t callback; /*!< Callback function. */
<> 154:37f96f9d4de2 218 void *userData; /*!< LPUART callback function parameter.*/
<> 154:37f96f9d4de2 219
<> 154:37f96f9d4de2 220 volatile uint8_t txState; /*!< TX transfer state. */
<> 154:37f96f9d4de2 221 volatile uint8_t rxState; /*!< RX transfer state. */
<> 154:37f96f9d4de2 222
<> 154:37f96f9d4de2 223 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 224 bool isSevenDataBits; /*!< Seven data bits flag. */
<> 154:37f96f9d4de2 225 #endif
<> 154:37f96f9d4de2 226 };
<> 154:37f96f9d4de2 227
<> 154:37f96f9d4de2 228 /*******************************************************************************
<> 154:37f96f9d4de2 229 * API
<> 154:37f96f9d4de2 230 ******************************************************************************/
<> 154:37f96f9d4de2 231
<> 154:37f96f9d4de2 232 #if defined(__cplusplus)
<> 154:37f96f9d4de2 233 extern "C" {
<> 154:37f96f9d4de2 234 #endif /* _cplusplus */
<> 154:37f96f9d4de2 235
<> 154:37f96f9d4de2 236 /*!
<> 154:37f96f9d4de2 237 * @name Initialization and deinitialization
<> 154:37f96f9d4de2 238 * @{
<> 154:37f96f9d4de2 239 */
<> 154:37f96f9d4de2 240
<> 154:37f96f9d4de2 241 /*!
<> 154:37f96f9d4de2 242 * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
<> 154:37f96f9d4de2 243 *
<> 154:37f96f9d4de2 244 * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
<> 154:37f96f9d4de2 245 * to configure the configuration structure and get the default configuration.
<> 154:37f96f9d4de2 246 * The example below shows how to use this API to configure the LPUART.
<> 154:37f96f9d4de2 247 * @code
<> 154:37f96f9d4de2 248 * lpuart_config_t lpuartConfig;
<> 154:37f96f9d4de2 249 * lpuartConfig.baudRate_Bps = 115200U;
<> 154:37f96f9d4de2 250 * lpuartConfig.parityMode = kLPUART_ParityDisabled;
<> 154:37f96f9d4de2 251 * lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
<> 154:37f96f9d4de2 252 * lpuartConfig.isMsb = false;
<> 154:37f96f9d4de2 253 * lpuartConfig.stopBitCount = kLPUART_OneStopBit;
<> 154:37f96f9d4de2 254 * lpuartConfig.txFifoWatermark = 0;
<> 154:37f96f9d4de2 255 * lpuartConfig.rxFifoWatermark = 1;
<> 154:37f96f9d4de2 256 * LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
<> 154:37f96f9d4de2 257 * @endcode
<> 154:37f96f9d4de2 258 *
<> 154:37f96f9d4de2 259 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 260 * @param config Pointer to a user-defined configuration structure.
<> 154:37f96f9d4de2 261 * @param srcClock_Hz LPUART clock source frequency in HZ.
<> 154:37f96f9d4de2 262 * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
<> 154:37f96f9d4de2 263 * @retval kStatus_Success LPUART initialize succeed
<> 154:37f96f9d4de2 264 */
<> 154:37f96f9d4de2 265 status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
<> 154:37f96f9d4de2 266
<> 154:37f96f9d4de2 267 /*!
<> 154:37f96f9d4de2 268 * @brief Deinitializes a LPUART instance.
<> 154:37f96f9d4de2 269 *
<> 154:37f96f9d4de2 270 * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
<> 154:37f96f9d4de2 271 *
<> 154:37f96f9d4de2 272 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 273 */
<> 154:37f96f9d4de2 274 void LPUART_Deinit(LPUART_Type *base);
<> 154:37f96f9d4de2 275
<> 154:37f96f9d4de2 276 /*!
<> 154:37f96f9d4de2 277 * @brief Gets the default configuration structure.
<> 154:37f96f9d4de2 278 *
<> 154:37f96f9d4de2 279 * This function initializes the LPUART configuration structure to a default value. The default
<> 154:37f96f9d4de2 280 * values are:
<> 154:37f96f9d4de2 281 * lpuartConfig->baudRate_Bps = 115200U;
<> 154:37f96f9d4de2 282 * lpuartConfig->parityMode = kLPUART_ParityDisabled;
<> 154:37f96f9d4de2 283 * lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
<> 154:37f96f9d4de2 284 * lpuartConfig->isMsb = false;
<> 154:37f96f9d4de2 285 * lpuartConfig->stopBitCount = kLPUART_OneStopBit;
<> 154:37f96f9d4de2 286 * lpuartConfig->txFifoWatermark = 0;
<> 154:37f96f9d4de2 287 * lpuartConfig->rxFifoWatermark = 1;
<> 154:37f96f9d4de2 288 * lpuartConfig->enableTx = false;
<> 154:37f96f9d4de2 289 * lpuartConfig->enableRx = false;
<> 154:37f96f9d4de2 290 *
<> 154:37f96f9d4de2 291 * @param config Pointer to a configuration structure.
<> 154:37f96f9d4de2 292 */
<> 154:37f96f9d4de2 293 void LPUART_GetDefaultConfig(lpuart_config_t *config);
<> 154:37f96f9d4de2 294
<> 154:37f96f9d4de2 295 /*!
<> 154:37f96f9d4de2 296 * @brief Sets the LPUART instance baudrate.
<> 154:37f96f9d4de2 297 *
<> 154:37f96f9d4de2 298 * This function configures the LPUART module baudrate. This function is used to update
<> 154:37f96f9d4de2 299 * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
<> 154:37f96f9d4de2 300 * @code
<> 154:37f96f9d4de2 301 * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
<> 154:37f96f9d4de2 302 * @endcode
<> 154:37f96f9d4de2 303 *
<> 154:37f96f9d4de2 304 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 305 * @param baudRate_Bps LPUART baudrate to be set.
<> 154:37f96f9d4de2 306 * @param srcClock_Hz LPUART clock source frequency in HZ.
<> 154:37f96f9d4de2 307 * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
<> 154:37f96f9d4de2 308 * @retval kStatus_Success Set baudrate succeeded.
<> 154:37f96f9d4de2 309 */
<> 154:37f96f9d4de2 310 status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
<> 154:37f96f9d4de2 311
<> 154:37f96f9d4de2 312 /* @} */
<> 154:37f96f9d4de2 313
<> 154:37f96f9d4de2 314 /*!
<> 154:37f96f9d4de2 315 * @name Status
<> 154:37f96f9d4de2 316 * @{
<> 154:37f96f9d4de2 317 */
<> 154:37f96f9d4de2 318
<> 154:37f96f9d4de2 319 /*!
<> 154:37f96f9d4de2 320 * @brief Gets LPUART status flags.
<> 154:37f96f9d4de2 321 *
<> 154:37f96f9d4de2 322 * This function gets all LPUART status flags. The flags are returned as the logical
<> 154:37f96f9d4de2 323 * OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
<> 154:37f96f9d4de2 324 * compare the return value with enumerators in the @ref _lpuart_flags.
<> 154:37f96f9d4de2 325 * For example, to check whether the TX is empty:
<> 154:37f96f9d4de2 326 * @code
<> 154:37f96f9d4de2 327 * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
<> 154:37f96f9d4de2 328 * {
<> 154:37f96f9d4de2 329 * ...
<> 154:37f96f9d4de2 330 * }
<> 154:37f96f9d4de2 331 * @endcode
<> 154:37f96f9d4de2 332 *
<> 154:37f96f9d4de2 333 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 334 * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
<> 154:37f96f9d4de2 335 */
<> 154:37f96f9d4de2 336 uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
<> 154:37f96f9d4de2 337
<> 154:37f96f9d4de2 338 /*!
<> 154:37f96f9d4de2 339 * @brief Clears status flags with a provided mask.
<> 154:37f96f9d4de2 340 *
<> 154:37f96f9d4de2 341 * This function clears LPUART status flags with a provided mask. Automatically cleared flags
<> 154:37f96f9d4de2 342 * can't be cleared by this function.
<> 154:37f96f9d4de2 343 * Flags that can only cleared or set by hardware are:
<> 154:37f96f9d4de2 344 * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
<> 154:37f96f9d4de2 345 * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
<> 154:37f96f9d4de2 346 * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
<> 154:37f96f9d4de2 347 * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
<> 154:37f96f9d4de2 348 *
<> 154:37f96f9d4de2 349 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 350 * @param mask the status flags to be cleared. The user can use the enumerators in the
<> 154:37f96f9d4de2 351 * _lpuart_status_flag_t to do the OR operation and get the mask.
<> 154:37f96f9d4de2 352 * @return 0 succeed, others failed.
<> 154:37f96f9d4de2 353 * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
<> 154:37f96f9d4de2 354 * it is cleared automatically by hardware.
<> 154:37f96f9d4de2 355 * @retval kStatus_Success Status in the mask are cleared.
<> 154:37f96f9d4de2 356 */
<> 154:37f96f9d4de2 357 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 358
<> 154:37f96f9d4de2 359 /* @} */
<> 154:37f96f9d4de2 360
<> 154:37f96f9d4de2 361 /*!
<> 154:37f96f9d4de2 362 * @name Interrupts
<> 154:37f96f9d4de2 363 * @{
<> 154:37f96f9d4de2 364 */
<> 154:37f96f9d4de2 365
<> 154:37f96f9d4de2 366 /*!
<> 154:37f96f9d4de2 367 * @brief Enables LPUART interrupts according to a provided mask.
<> 154:37f96f9d4de2 368 *
<> 154:37f96f9d4de2 369 * This function enables the LPUART interrupts according to a provided mask. The mask
<> 154:37f96f9d4de2 370 * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
<> 154:37f96f9d4de2 371 * This examples shows how to enable TX empty interrupt and RX full interrupt:
<> 154:37f96f9d4de2 372 * @code
<> 154:37f96f9d4de2 373 * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
<> 154:37f96f9d4de2 374 * @endcode
<> 154:37f96f9d4de2 375 *
<> 154:37f96f9d4de2 376 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 377 * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
<> 154:37f96f9d4de2 378 */
<> 154:37f96f9d4de2 379 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 380
<> 154:37f96f9d4de2 381 /*!
<> 154:37f96f9d4de2 382 * @brief Disables LPUART interrupts according to a provided mask.
<> 154:37f96f9d4de2 383 *
<> 154:37f96f9d4de2 384 * This function disables the LPUART interrupts according to a provided mask. The mask
<> 154:37f96f9d4de2 385 * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
<> 154:37f96f9d4de2 386 * This example shows how to disable the TX empty interrupt and RX full interrupt:
<> 154:37f96f9d4de2 387 * @code
<> 154:37f96f9d4de2 388 * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
<> 154:37f96f9d4de2 389 * @endcode
<> 154:37f96f9d4de2 390 *
<> 154:37f96f9d4de2 391 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 392 * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
<> 154:37f96f9d4de2 393 */
<> 154:37f96f9d4de2 394 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 395
<> 154:37f96f9d4de2 396 /*!
<> 154:37f96f9d4de2 397 * @brief Gets enabled LPUART interrupts.
<> 154:37f96f9d4de2 398 *
<> 154:37f96f9d4de2 399 * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
<> 154:37f96f9d4de2 400 * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
<> 154:37f96f9d4de2 401 * a specific interrupt enable status, compare the return value with enumerators
<> 154:37f96f9d4de2 402 * in @ref _lpuart_interrupt_enable.
<> 154:37f96f9d4de2 403 * For example, to check whether the TX empty interrupt is enabled:
<> 154:37f96f9d4de2 404 * @code
<> 154:37f96f9d4de2 405 * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
<> 154:37f96f9d4de2 406 *
<> 154:37f96f9d4de2 407 * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
<> 154:37f96f9d4de2 408 * {
<> 154:37f96f9d4de2 409 * ...
<> 154:37f96f9d4de2 410 * }
<> 154:37f96f9d4de2 411 * @endcode
<> 154:37f96f9d4de2 412 *
<> 154:37f96f9d4de2 413 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 414 * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
<> 154:37f96f9d4de2 415 */
<> 154:37f96f9d4de2 416 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
<> 154:37f96f9d4de2 417
<> 154:37f96f9d4de2 418 #if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
<> 154:37f96f9d4de2 419 /*!
<> 154:37f96f9d4de2 420 * @brief Gets the LPUART data register address.
<> 154:37f96f9d4de2 421 *
<> 154:37f96f9d4de2 422 * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
<> 154:37f96f9d4de2 423 *
<> 154:37f96f9d4de2 424 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 425 * @return LPUART data register addresses which are used both by the transmitter and receiver.
<> 154:37f96f9d4de2 426 */
<> 154:37f96f9d4de2 427 static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
<> 154:37f96f9d4de2 428 {
<> 154:37f96f9d4de2 429 return (uint32_t) & (base->DATA);
<> 154:37f96f9d4de2 430 }
<> 154:37f96f9d4de2 431
<> 154:37f96f9d4de2 432 /*!
<> 154:37f96f9d4de2 433 * @brief Enables or disables the LPUART transmitter DMA request.
<> 154:37f96f9d4de2 434 *
<> 154:37f96f9d4de2 435 * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
<> 154:37f96f9d4de2 436 *
<> 154:37f96f9d4de2 437 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 438 * @param enable True to enable, false to disable.
<> 154:37f96f9d4de2 439 */
<> 154:37f96f9d4de2 440 static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
<> 154:37f96f9d4de2 441 {
<> 154:37f96f9d4de2 442 if (enable)
<> 154:37f96f9d4de2 443 {
<> 154:37f96f9d4de2 444 base->BAUD |= LPUART_BAUD_TDMAE_MASK;
<> 154:37f96f9d4de2 445 base->CTRL |= LPUART_CTRL_TIE_MASK;
<> 154:37f96f9d4de2 446 }
<> 154:37f96f9d4de2 447 else
<> 154:37f96f9d4de2 448 {
<> 154:37f96f9d4de2 449 base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
<> 154:37f96f9d4de2 450 base->CTRL &= ~LPUART_CTRL_TIE_MASK;
<> 154:37f96f9d4de2 451 }
<> 154:37f96f9d4de2 452 }
<> 154:37f96f9d4de2 453
<> 154:37f96f9d4de2 454 /*!
<> 154:37f96f9d4de2 455 * @brief Enables or disables the LPUART receiver DMA.
<> 154:37f96f9d4de2 456 *
<> 154:37f96f9d4de2 457 * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
<> 154:37f96f9d4de2 458 *
<> 154:37f96f9d4de2 459 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 460 * @param enable True to enable, false to disable.
<> 154:37f96f9d4de2 461 */
<> 154:37f96f9d4de2 462 static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
<> 154:37f96f9d4de2 463 {
<> 154:37f96f9d4de2 464 if (enable)
<> 154:37f96f9d4de2 465 {
<> 154:37f96f9d4de2 466 base->BAUD |= LPUART_BAUD_RDMAE_MASK;
<> 154:37f96f9d4de2 467 base->CTRL |= LPUART_CTRL_RIE_MASK;
<> 154:37f96f9d4de2 468 }
<> 154:37f96f9d4de2 469 else
<> 154:37f96f9d4de2 470 {
<> 154:37f96f9d4de2 471 base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
<> 154:37f96f9d4de2 472 base->CTRL &= ~LPUART_CTRL_RIE_MASK;
<> 154:37f96f9d4de2 473 }
<> 154:37f96f9d4de2 474 }
<> 154:37f96f9d4de2 475
<> 154:37f96f9d4de2 476 /* @} */
<> 154:37f96f9d4de2 477 #endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
<> 154:37f96f9d4de2 478
<> 154:37f96f9d4de2 479 /*!
<> 154:37f96f9d4de2 480 * @name Bus Operations
<> 154:37f96f9d4de2 481 * @{
<> 154:37f96f9d4de2 482 */
<> 154:37f96f9d4de2 483
<> 154:37f96f9d4de2 484 /*!
<> 154:37f96f9d4de2 485 * @brief Enables or disables the LPUART transmitter.
<> 154:37f96f9d4de2 486 *
<> 154:37f96f9d4de2 487 * This function enables or disables the LPUART transmitter.
<> 154:37f96f9d4de2 488 *
<> 154:37f96f9d4de2 489 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 490 * @param enable True to enable, false to disable.
<> 154:37f96f9d4de2 491 */
<> 154:37f96f9d4de2 492 static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
<> 154:37f96f9d4de2 493 {
<> 154:37f96f9d4de2 494 if (enable)
<> 154:37f96f9d4de2 495 {
<> 154:37f96f9d4de2 496 base->CTRL |= LPUART_CTRL_TE_MASK;
<> 154:37f96f9d4de2 497 }
<> 154:37f96f9d4de2 498 else
<> 154:37f96f9d4de2 499 {
<> 154:37f96f9d4de2 500 base->CTRL &= ~LPUART_CTRL_TE_MASK;
<> 154:37f96f9d4de2 501 }
<> 154:37f96f9d4de2 502 }
<> 154:37f96f9d4de2 503
<> 154:37f96f9d4de2 504 /*!
<> 154:37f96f9d4de2 505 * @brief Enables or disables the LPUART receiver.
<> 154:37f96f9d4de2 506 *
<> 154:37f96f9d4de2 507 * This function enables or disables the LPUART receiver.
<> 154:37f96f9d4de2 508 *
<> 154:37f96f9d4de2 509 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 510 * @param enable True to enable, false to disable.
<> 154:37f96f9d4de2 511 */
<> 154:37f96f9d4de2 512 static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
<> 154:37f96f9d4de2 513 {
<> 154:37f96f9d4de2 514 if (enable)
<> 154:37f96f9d4de2 515 {
<> 154:37f96f9d4de2 516 base->CTRL |= LPUART_CTRL_RE_MASK;
<> 154:37f96f9d4de2 517 }
<> 154:37f96f9d4de2 518 else
<> 154:37f96f9d4de2 519 {
<> 154:37f96f9d4de2 520 base->CTRL &= ~LPUART_CTRL_RE_MASK;
<> 154:37f96f9d4de2 521 }
<> 154:37f96f9d4de2 522 }
<> 154:37f96f9d4de2 523
<> 154:37f96f9d4de2 524 /*!
<> 154:37f96f9d4de2 525 * @brief Writes to the transmitter register.
<> 154:37f96f9d4de2 526 *
<> 154:37f96f9d4de2 527 * This function writes data to the transmitter register directly. The upper layer must
<> 154:37f96f9d4de2 528 * ensure that the TX register is empty or that the TX FIFO has room before calling this function.
<> 154:37f96f9d4de2 529 *
<> 154:37f96f9d4de2 530 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 531 * @param data Data write to the TX register.
<> 154:37f96f9d4de2 532 */
<> 154:37f96f9d4de2 533 static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
<> 154:37f96f9d4de2 534 {
<> 154:37f96f9d4de2 535 base->DATA = data;
<> 154:37f96f9d4de2 536 }
<> 154:37f96f9d4de2 537
<> 154:37f96f9d4de2 538 /*!
<> 154:37f96f9d4de2 539 * @brief Reads the RX register.
<> 154:37f96f9d4de2 540 *
<> 154:37f96f9d4de2 541 * This function reads data from the receiver register directly. The upper layer must
<> 154:37f96f9d4de2 542 * ensure that the RX register is full or that the RX FIFO has data before calling this function.
<> 154:37f96f9d4de2 543 *
<> 154:37f96f9d4de2 544 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 545 * @return Data read from data register.
<> 154:37f96f9d4de2 546 */
<> 154:37f96f9d4de2 547 static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
<> 154:37f96f9d4de2 548 {
<> 154:37f96f9d4de2 549 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
<> 154:37f96f9d4de2 550 uint32_t ctrl = base->CTRL;
<> 154:37f96f9d4de2 551 bool isSevenDataBits = ((ctrl & LPUART_CTRL_M7_MASK) ||
<> 154:37f96f9d4de2 552 ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
<> 154:37f96f9d4de2 553
<> 154:37f96f9d4de2 554 if (isSevenDataBits)
<> 154:37f96f9d4de2 555 {
<> 154:37f96f9d4de2 556 return (base->DATA & 0x7F);
<> 154:37f96f9d4de2 557 }
<> 154:37f96f9d4de2 558 else
<> 154:37f96f9d4de2 559 {
<> 154:37f96f9d4de2 560 return base->DATA;
<> 154:37f96f9d4de2 561 }
<> 154:37f96f9d4de2 562 #else
<> 154:37f96f9d4de2 563 return base->DATA;
<> 154:37f96f9d4de2 564 #endif
<> 154:37f96f9d4de2 565 }
<> 154:37f96f9d4de2 566
<> 154:37f96f9d4de2 567 /*!
<> 154:37f96f9d4de2 568 * @brief Writes to transmitter register using a blocking method.
<> 154:37f96f9d4de2 569 *
<> 154:37f96f9d4de2 570 * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have
<> 154:37f96f9d4de2 571 * room and then writes data to the transmitter buffer.
<> 154:37f96f9d4de2 572 *
<> 154:37f96f9d4de2 573 * @note This function does not check whether all data has been sent out to the bus.
<> 154:37f96f9d4de2 574 * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
<> 154:37f96f9d4de2 575 * finished.
<> 154:37f96f9d4de2 576 *
<> 154:37f96f9d4de2 577 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 578 * @param data Start address of the data to write.
<> 154:37f96f9d4de2 579 * @param length Size of the data to write.
<> 154:37f96f9d4de2 580 */
<> 154:37f96f9d4de2 581 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
<> 154:37f96f9d4de2 582
<> 154:37f96f9d4de2 583 /*!
<> 154:37f96f9d4de2 584 * @brief Reads the RX data register using a blocking method.
<> 154:37f96f9d4de2 585 *
<> 154:37f96f9d4de2 586 * This function polls the RX register, waits for the RX register full or RX FIFO
<> 154:37f96f9d4de2 587 * has data then reads data from the TX register.
<> 154:37f96f9d4de2 588 *
<> 154:37f96f9d4de2 589 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 590 * @param data Start address of the buffer to store the received data.
<> 154:37f96f9d4de2 591 * @param length Size of the buffer.
<> 154:37f96f9d4de2 592 * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
<> 154:37f96f9d4de2 593 * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
<> 154:37f96f9d4de2 594 * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
<> 154:37f96f9d4de2 595 * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
<> 154:37f96f9d4de2 596 * @retval kStatus_Success Successfully received all data.
<> 154:37f96f9d4de2 597 */
<> 154:37f96f9d4de2 598 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
<> 154:37f96f9d4de2 599
<> 154:37f96f9d4de2 600 /* @} */
<> 154:37f96f9d4de2 601
<> 154:37f96f9d4de2 602 /*!
<> 154:37f96f9d4de2 603 * @name Transactional
<> 154:37f96f9d4de2 604 * @{
<> 154:37f96f9d4de2 605 */
<> 154:37f96f9d4de2 606
<> 154:37f96f9d4de2 607 /*!
<> 154:37f96f9d4de2 608 * @brief Initializes the LPUART handle.
<> 154:37f96f9d4de2 609 *
<> 154:37f96f9d4de2 610 * This function initializes the LPUART handle, which can be used for other LPUART
<> 154:37f96f9d4de2 611 * transactional APIs. Usually, for a specified LPUART instance,
<> 154:37f96f9d4de2 612 * call this API once to get the initialized handle.
<> 154:37f96f9d4de2 613 *
<> 154:37f96f9d4de2 614 * The LPUART driver supports the "background" receiving, which means that user can set up
<> 154:37f96f9d4de2 615 * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
<> 154:37f96f9d4de2 616 * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
<> 154:37f96f9d4de2 617 * in the ring buffer, the user can get the received data from the ring buffer directly.
<> 154:37f96f9d4de2 618 * The ring buffer is disabled if passing NULL as @p ringBuffer.
<> 154:37f96f9d4de2 619 *
<> 154:37f96f9d4de2 620 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 621 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 622 * @param callback Callback function.
<> 154:37f96f9d4de2 623 * @param userData User data.
<> 154:37f96f9d4de2 624 */
<> 154:37f96f9d4de2 625 void LPUART_TransferCreateHandle(LPUART_Type *base,
<> 154:37f96f9d4de2 626 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 627 lpuart_transfer_callback_t callback,
<> 154:37f96f9d4de2 628 void *userData);
<> 154:37f96f9d4de2 629 /*!
<> 154:37f96f9d4de2 630 * @brief Transmits a buffer of data using the interrupt method.
<> 154:37f96f9d4de2 631 *
<> 154:37f96f9d4de2 632 * This function send data using an interrupt method. This is a non-blocking function, which
<> 154:37f96f9d4de2 633 * returns directly without waiting for all data written to the transmitter register. When
<> 154:37f96f9d4de2 634 * all data is written to the TX register in the ISR, the LPUART driver calls the callback
<> 154:37f96f9d4de2 635 * function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
<> 154:37f96f9d4de2 636 *
<> 154:37f96f9d4de2 637 * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
<> 154:37f96f9d4de2 638 * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
<> 154:37f96f9d4de2 639 * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
<> 154:37f96f9d4de2 640 *
<> 154:37f96f9d4de2 641 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 642 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 643 * @param xfer LPUART transfer structure, see #lpuart_transfer_t.
<> 154:37f96f9d4de2 644 * @retval kStatus_Success Successfully start the data transmission.
<> 154:37f96f9d4de2 645 * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
<> 154:37f96f9d4de2 646 * @retval kStatus_InvalidArgument Invalid argument.
<> 154:37f96f9d4de2 647 */
<> 154:37f96f9d4de2 648 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
<> 154:37f96f9d4de2 649
<> 154:37f96f9d4de2 650 /*!
<> 154:37f96f9d4de2 651 * @brief Sets up the RX ring buffer.
<> 154:37f96f9d4de2 652 *
<> 154:37f96f9d4de2 653 * This function sets up the RX ring buffer to a specific UART handle.
<> 154:37f96f9d4de2 654 *
<> 154:37f96f9d4de2 655 * When the RX ring buffer is used, data received is stored into the ring buffer even when
<> 154:37f96f9d4de2 656 * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
<> 154:37f96f9d4de2 657 * in the ring buffer, the user can get the received data from the ring buffer directly.
<> 154:37f96f9d4de2 658 *
<> 154:37f96f9d4de2 659 * @note When using RX ring buffer, one byte is reserved for internal use. In other
<> 154:37f96f9d4de2 660 * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
<> 154:37f96f9d4de2 661 *
<> 154:37f96f9d4de2 662 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 663 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 664 * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
<> 154:37f96f9d4de2 665 * @param ringBufferSize size of the ring buffer.
<> 154:37f96f9d4de2 666 */
<> 154:37f96f9d4de2 667 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
<> 154:37f96f9d4de2 668 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 669 uint8_t *ringBuffer,
<> 154:37f96f9d4de2 670 size_t ringBufferSize);
<> 154:37f96f9d4de2 671
<> 154:37f96f9d4de2 672 /*!
<> 154:37f96f9d4de2 673 * @brief Abort the background transfer and uninstall the ring buffer.
<> 154:37f96f9d4de2 674 *
<> 154:37f96f9d4de2 675 * This function aborts the background transfer and uninstalls the ring buffer.
<> 154:37f96f9d4de2 676 *
<> 154:37f96f9d4de2 677 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 678 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 679 */
<> 154:37f96f9d4de2 680 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 681
<> 154:37f96f9d4de2 682 /*!
<> 154:37f96f9d4de2 683 * @brief Aborts the interrupt-driven data transmit.
<> 154:37f96f9d4de2 684 *
<> 154:37f96f9d4de2 685 * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
<> 154:37f96f9d4de2 686 * how many bytes are still not sent out.
<> 154:37f96f9d4de2 687 *
<> 154:37f96f9d4de2 688 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 689 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 690 */
<> 154:37f96f9d4de2 691 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 692
<> 154:37f96f9d4de2 693 /*!
<> 154:37f96f9d4de2 694 * @brief Get the number of bytes that have been written to LPUART TX register.
<> 154:37f96f9d4de2 695 *
<> 154:37f96f9d4de2 696 * This function gets the number of bytes that have been written to LPUART TX
<> 154:37f96f9d4de2 697 * register by interrupt method.
<> 154:37f96f9d4de2 698 *
<> 154:37f96f9d4de2 699 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 700 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 701 * @param count Send bytes count.
<> 154:37f96f9d4de2 702 * @retval kStatus_NoTransferInProgress No send in progress.
<> 154:37f96f9d4de2 703 * @retval kStatus_InvalidArgument Parameter is invalid.
<> 154:37f96f9d4de2 704 * @retval kStatus_Success Get successfully through the parameter \p count;
<> 154:37f96f9d4de2 705 */
<> 154:37f96f9d4de2 706 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
<> 154:37f96f9d4de2 707
<> 154:37f96f9d4de2 708 /*!
<> 154:37f96f9d4de2 709 * @brief Receives a buffer of data using the interrupt method.
<> 154:37f96f9d4de2 710 *
<> 154:37f96f9d4de2 711 * This function receives data using an interrupt method. This is a non-blocking function
<> 154:37f96f9d4de2 712 * which returns without waiting to ensure that all data are received.
<> 154:37f96f9d4de2 713 * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
<> 154:37f96f9d4de2 714 * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
<> 154:37f96f9d4de2 715 * After copying, if the data in the ring buffer is not enough for read, the receive
<> 154:37f96f9d4de2 716 * request is saved by the LPUART driver. When the new data arrives, the receive request
<> 154:37f96f9d4de2 717 * is serviced first. When all data is received, the LPUART driver notifies the upper layer
<> 154:37f96f9d4de2 718 * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
<> 154:37f96f9d4de2 719 * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
<> 154:37f96f9d4de2 720 * The 5 bytes are copied to xfer->data, which returns with the
<> 154:37f96f9d4de2 721 * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
<> 154:37f96f9d4de2 722 * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
<> 154:37f96f9d4de2 723 * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
<> 154:37f96f9d4de2 724 * to receive data to xfer->data. When all data is received, the upper layer is notified.
<> 154:37f96f9d4de2 725 *
<> 154:37f96f9d4de2 726 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 727 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 728 * @param xfer LPUART transfer structure, see #uart_transfer_t.
<> 154:37f96f9d4de2 729 * @param receivedBytes Bytes received from the ring buffer directly.
<> 154:37f96f9d4de2 730 * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
<> 154:37f96f9d4de2 731 * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
<> 154:37f96f9d4de2 732 * @retval kStatus_InvalidArgument Invalid argument.
<> 154:37f96f9d4de2 733 */
<> 154:37f96f9d4de2 734 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
<> 154:37f96f9d4de2 735 lpuart_handle_t *handle,
<> 154:37f96f9d4de2 736 lpuart_transfer_t *xfer,
<> 154:37f96f9d4de2 737 size_t *receivedBytes);
<> 154:37f96f9d4de2 738
<> 154:37f96f9d4de2 739 /*!
<> 154:37f96f9d4de2 740 * @brief Aborts the interrupt-driven data receiving.
<> 154:37f96f9d4de2 741 *
<> 154:37f96f9d4de2 742 * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
<> 154:37f96f9d4de2 743 * how many bytes not received yet.
<> 154:37f96f9d4de2 744 *
<> 154:37f96f9d4de2 745 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 746 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 747 */
<> 154:37f96f9d4de2 748 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 749
<> 154:37f96f9d4de2 750 /*!
<> 154:37f96f9d4de2 751 * @brief Get the number of bytes that have been received.
<> 154:37f96f9d4de2 752 *
<> 154:37f96f9d4de2 753 * This function gets the number of bytes that have been received.
<> 154:37f96f9d4de2 754 *
<> 154:37f96f9d4de2 755 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 756 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 757 * @param count Receive bytes count.
<> 154:37f96f9d4de2 758 * @retval kStatus_NoTransferInProgress No receive in progress.
<> 154:37f96f9d4de2 759 * @retval kStatus_InvalidArgument Parameter is invalid.
<> 154:37f96f9d4de2 760 * @retval kStatus_Success Get successfully through the parameter \p count;
<> 154:37f96f9d4de2 761 */
<> 154:37f96f9d4de2 762 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
<> 154:37f96f9d4de2 763
<> 154:37f96f9d4de2 764 /*!
<> 154:37f96f9d4de2 765 * @brief LPUART IRQ handle function.
<> 154:37f96f9d4de2 766 *
<> 154:37f96f9d4de2 767 * This function handles the LPUART transmit and receive IRQ request.
<> 154:37f96f9d4de2 768 *
<> 154:37f96f9d4de2 769 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 770 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 771 */
<> 154:37f96f9d4de2 772 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 773
<> 154:37f96f9d4de2 774 /*!
<> 154:37f96f9d4de2 775 * @brief LPUART Error IRQ handle function.
<> 154:37f96f9d4de2 776 *
<> 154:37f96f9d4de2 777 * This function handles the LPUART error IRQ request.
<> 154:37f96f9d4de2 778 *
<> 154:37f96f9d4de2 779 * @param base LPUART peripheral base address.
<> 154:37f96f9d4de2 780 * @param handle LPUART handle pointer.
<> 154:37f96f9d4de2 781 */
<> 154:37f96f9d4de2 782 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
<> 154:37f96f9d4de2 783
<> 154:37f96f9d4de2 784 /* @} */
<> 154:37f96f9d4de2 785
<> 154:37f96f9d4de2 786 #if defined(__cplusplus)
<> 154:37f96f9d4de2 787 }
<> 154:37f96f9d4de2 788 #endif
<> 154:37f96f9d4de2 789
<> 154:37f96f9d4de2 790 /*! @}*/
<> 154:37f96f9d4de2 791
<> 154:37f96f9d4de2 792 #endif /* _FSL_LPUART_H_ */