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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_clock.h@182:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
182:57724642e740
Parent:
154:37f96f9d4de2 
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #ifndef _FSL_CLOCK_H_
<> 154:37f96f9d4de2 32 #define _FSL_CLOCK_H_
<> 154:37f96f9d4de2 33
<> 154:37f96f9d4de2 34 #include "fsl_common.h"
<> 154:37f96f9d4de2 35
<> 154:37f96f9d4de2 36 /*! @addtogroup clock */
<> 154:37f96f9d4de2 37 /*! @{ */
<> 154:37f96f9d4de2 38
<> 154:37f96f9d4de2 39 /*! @file */
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /*******************************************************************************
<> 154:37f96f9d4de2 42 * Definitions
<> 154:37f96f9d4de2 43 ******************************************************************************/
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /*! @name Driver version */
<> 154:37f96f9d4de2 46 /*@{*/
<> 154:37f96f9d4de2 47 /*! @brief CLOCK driver version 2.2.0. */
<> 154:37f96f9d4de2 48 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
<> 154:37f96f9d4de2 49 /*@}*/
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 /*! @brief External XTAL0 (OSC0) clock frequency.
<> 154:37f96f9d4de2 52 *
<> 154:37f96f9d4de2 53 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
<> 154:37f96f9d4de2 54 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
<> 154:37f96f9d4de2 55 * if XTAL0 is 8 MHz:
<> 154:37f96f9d4de2 56 * @code
<> 154:37f96f9d4de2 57 * CLOCK_InitOsc0(...); // Set up the OSC0
<> 154:37f96f9d4de2 58 * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
<> 154:37f96f9d4de2 59 * @endcode
<> 154:37f96f9d4de2 60 *
<> 154:37f96f9d4de2 61 * This is important for the multicore platforms where only one core needs to set up the
<> 154:37f96f9d4de2 62 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
<> 154:37f96f9d4de2 63 * to get a valid clock frequency.
<> 154:37f96f9d4de2 64 */
<> 154:37f96f9d4de2 65 extern uint32_t g_xtal0Freq;
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
<> 154:37f96f9d4de2 68 *
<> 154:37f96f9d4de2 69 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
<> 154:37f96f9d4de2 70 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
<> 154:37f96f9d4de2 71 *
<> 154:37f96f9d4de2 72 * This is important for the multicore platforms where only one core needs to set up
<> 154:37f96f9d4de2 73 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
<> 154:37f96f9d4de2 74 * to get a valid clock frequency.
<> 154:37f96f9d4de2 75 */
<> 154:37f96f9d4de2 76 extern uint32_t g_xtal32Freq;
<> 154:37f96f9d4de2 77
<> 154:37f96f9d4de2 78 #if (defined(OSC) && !(defined(OSC0)))
<> 154:37f96f9d4de2 79 #define OSC0 OSC
<> 154:37f96f9d4de2 80 #endif
<> 154:37f96f9d4de2 81
<> 154:37f96f9d4de2 82 /*! @brief Clock ip name array for DMAMUX. */
<> 154:37f96f9d4de2 83 #define DMAMUX_CLOCKS \
<> 154:37f96f9d4de2 84 { \
<> 154:37f96f9d4de2 85 kCLOCK_Dmamux0 \
<> 154:37f96f9d4de2 86 }
<> 154:37f96f9d4de2 87
<> 154:37f96f9d4de2 88 /*! @brief Clock ip name array for RTC. */
<> 154:37f96f9d4de2 89 #define RTC_CLOCKS \
<> 154:37f96f9d4de2 90 { \
<> 154:37f96f9d4de2 91 kCLOCK_Rtc0 \
<> 154:37f96f9d4de2 92 }
<> 154:37f96f9d4de2 93
<> 154:37f96f9d4de2 94 /*! @brief Clock ip name array for PIT. */
<> 154:37f96f9d4de2 95 #define PIT_CLOCKS \
<> 154:37f96f9d4de2 96 { \
<> 154:37f96f9d4de2 97 kCLOCK_Pit0 \
<> 154:37f96f9d4de2 98 }
<> 154:37f96f9d4de2 99
<> 154:37f96f9d4de2 100 /*! @brief Clock ip name array for PORT. */
<> 154:37f96f9d4de2 101 #define PORT_CLOCKS \
<> 154:37f96f9d4de2 102 { \
<> 154:37f96f9d4de2 103 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC \
<> 154:37f96f9d4de2 104 }
<> 154:37f96f9d4de2 105
<> 154:37f96f9d4de2 106 /*! @brief Clock ip name array for TSI. */
<> 154:37f96f9d4de2 107 #define TSI_CLOCKS \
<> 154:37f96f9d4de2 108 { \
<> 154:37f96f9d4de2 109 kCLOCK_Tsi0 \
<> 154:37f96f9d4de2 110 }
<> 154:37f96f9d4de2 111
<> 154:37f96f9d4de2 112 /*! @brief Clock ip name array for DSPI. */
<> 154:37f96f9d4de2 113 #define DSPI_CLOCKS \
<> 154:37f96f9d4de2 114 { \
<> 154:37f96f9d4de2 115 kCLOCK_Spi0, kCLOCK_Spi1 \
<> 154:37f96f9d4de2 116 }
<> 154:37f96f9d4de2 117
<> 154:37f96f9d4de2 118 /*! @brief Clock ip name array for LPUART. */
<> 154:37f96f9d4de2 119 #define LPUART_CLOCKS \
<> 154:37f96f9d4de2 120 { \
<> 154:37f96f9d4de2 121 kCLOCK_Lpuart0 \
<> 154:37f96f9d4de2 122 }
<> 154:37f96f9d4de2 123
<> 154:37f96f9d4de2 124 /*! @brief Clock ip name array for DAC. */
<> 154:37f96f9d4de2 125 #define DAC_CLOCKS \
<> 154:37f96f9d4de2 126 { \
<> 154:37f96f9d4de2 127 kCLOCK_Dac0 \
<> 154:37f96f9d4de2 128 }
<> 154:37f96f9d4de2 129
<> 154:37f96f9d4de2 130 /*! @brief Clock ip name array for LPTMR. */
<> 154:37f96f9d4de2 131 #define LPTMR_CLOCKS \
<> 154:37f96f9d4de2 132 { \
<> 154:37f96f9d4de2 133 kCLOCK_Lptmr0 \
<> 154:37f96f9d4de2 134 }
<> 154:37f96f9d4de2 135
<> 154:37f96f9d4de2 136 /*! @brief Clock ip name array for ADC16. */
<> 154:37f96f9d4de2 137 #define ADC16_CLOCKS \
<> 154:37f96f9d4de2 138 { \
<> 154:37f96f9d4de2 139 kCLOCK_Adc0 \
<> 154:37f96f9d4de2 140 }
<> 154:37f96f9d4de2 141
<> 154:37f96f9d4de2 142 /*! @brief Clock ip name array for TRNG. */
<> 154:37f96f9d4de2 143 #define TRNG_CLOCKS \
<> 154:37f96f9d4de2 144 { \
<> 154:37f96f9d4de2 145 kCLOCK_Trng0 \
<> 154:37f96f9d4de2 146 }
<> 154:37f96f9d4de2 147
<> 154:37f96f9d4de2 148 /*! @brief Clock ip name array for DMA. */
<> 154:37f96f9d4de2 149 #define EDMA_CLOCKS \
<> 154:37f96f9d4de2 150 { \
<> 154:37f96f9d4de2 151 kCLOCK_Dma0 \
<> 154:37f96f9d4de2 152 }
<> 154:37f96f9d4de2 153
<> 154:37f96f9d4de2 154 /*! @brief Clock ip name array for CMT. */
<> 154:37f96f9d4de2 155 #define CMT_CLOCKS \
<> 154:37f96f9d4de2 156 { \
<> 154:37f96f9d4de2 157 kCLOCK_Cmt0 \
<> 154:37f96f9d4de2 158 }
<> 154:37f96f9d4de2 159
<> 154:37f96f9d4de2 160 /*! @brief Clock ip name array for TPM. */
<> 154:37f96f9d4de2 161 #define TPM_CLOCKS \
<> 154:37f96f9d4de2 162 { \
<> 154:37f96f9d4de2 163 kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
<> 154:37f96f9d4de2 164 }
<> 154:37f96f9d4de2 165
<> 154:37f96f9d4de2 166 /*! @brief Clock ip name array for LTC. */
<> 154:37f96f9d4de2 167 #define LTC_CLOCKS \
<> 154:37f96f9d4de2 168 { \
<> 154:37f96f9d4de2 169 kCLOCK_Ltc0 \
<> 154:37f96f9d4de2 170 }
<> 154:37f96f9d4de2 171
<> 154:37f96f9d4de2 172 /*! @brief Clock ip name array for I2C. */
<> 154:37f96f9d4de2 173 #define I2C_CLOCKS \
<> 154:37f96f9d4de2 174 { \
<> 154:37f96f9d4de2 175 kCLOCK_I2c0, kCLOCK_I2c1 \
<> 154:37f96f9d4de2 176 }
<> 154:37f96f9d4de2 177
<> 154:37f96f9d4de2 178 /*! @brief Clock ip name array for CMP. */
<> 154:37f96f9d4de2 179 #define CMP_CLOCKS \
<> 154:37f96f9d4de2 180 { \
<> 154:37f96f9d4de2 181 kCLOCK_Cmp0 \
<> 154:37f96f9d4de2 182 }
<> 154:37f96f9d4de2 183
<> 154:37f96f9d4de2 184 /*! @brief Clock ip name array for VREF. */
<> 154:37f96f9d4de2 185 #define VREF_CLOCKS \
<> 154:37f96f9d4de2 186 { \
<> 154:37f96f9d4de2 187 kCLOCK_Vref0 \
<> 154:37f96f9d4de2 188 }
<> 154:37f96f9d4de2 189
<> 154:37f96f9d4de2 190 /*! @brief Clock ip name array for DCDC. */
<> 154:37f96f9d4de2 191 #define DCDC_CLOCKS \
<> 154:37f96f9d4de2 192 { \
<> 154:37f96f9d4de2 193 kCLOCK_Dcdc0 \
<> 154:37f96f9d4de2 194 }
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 /*!
<> 154:37f96f9d4de2 197 * @brief LPO clock frequency.
<> 154:37f96f9d4de2 198 */
<> 154:37f96f9d4de2 199 #define LPO_CLK_FREQ 1000U
<> 154:37f96f9d4de2 200
<> 154:37f96f9d4de2 201 /*! @brief Prepherials clock source definition. */
<> 154:37f96f9d4de2 202 #define SYS_CLK kCLOCK_CoreSysClk
<> 154:37f96f9d4de2 203 #define BUS_CLK kCLOCK_BusClk
<> 154:37f96f9d4de2 204
<> 154:37f96f9d4de2 205 #define I2C0_CLK_SRC BUS_CLK
<> 154:37f96f9d4de2 206 #define I2C1_CLK_SRC SYS_CLK
<> 154:37f96f9d4de2 207 #define DSPI0_CLK_SRC BUS_CLK
<> 154:37f96f9d4de2 208 #define DSPI1_CLK_SRC BUS_CLK
<> 154:37f96f9d4de2 209
<> 154:37f96f9d4de2 210 /*! @brief Clock name used to get clock frequency. */
<> 154:37f96f9d4de2 211 typedef enum _clock_name
<> 154:37f96f9d4de2 212 {
<> 154:37f96f9d4de2 213 /* ----------------------------- System layer clock -------------------------------*/
<> 154:37f96f9d4de2 214 kCLOCK_CoreSysClk, /*!< Core/system clock */
<> 154:37f96f9d4de2 215 kCLOCK_PlatClk, /*!< Platform clock */
<> 154:37f96f9d4de2 216 kCLOCK_BusClk, /*!< Bus clock */
<> 154:37f96f9d4de2 217 kCLOCK_FlashClk, /*!< Flash clock */
<> 154:37f96f9d4de2 218
<> 154:37f96f9d4de2 219 /* ---------------------------------- OSC clock -----------------------------------*/
<> 154:37f96f9d4de2 220 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
<> 154:37f96f9d4de2 221 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
<> 154:37f96f9d4de2 222
<> 154:37f96f9d4de2 223 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
<> 154:37f96f9d4de2 224 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
<> 154:37f96f9d4de2 225 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
<> 154:37f96f9d4de2 226 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
<> 154:37f96f9d4de2 227 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
<> 154:37f96f9d4de2 228
<> 154:37f96f9d4de2 229 /* --------------------------------- Other clock ----------------------------------*/
<> 154:37f96f9d4de2 230 kCLOCK_LpoClk, /*!< LPO clock */
<> 154:37f96f9d4de2 231
<> 154:37f96f9d4de2 232 } clock_name_t;
<> 154:37f96f9d4de2 233
<> 154:37f96f9d4de2 234 /*------------------------------------------------------------------------------
<> 154:37f96f9d4de2 235
<> 154:37f96f9d4de2 236 clock_gate_t definition:
<> 154:37f96f9d4de2 237
<> 154:37f96f9d4de2 238 31 16 0
<> 154:37f96f9d4de2 239 -----------------------------------------------------------------
<> 154:37f96f9d4de2 240 | SIM_SCGC register offset | control bit offset in SCGC |
<> 154:37f96f9d4de2 241 -----------------------------------------------------------------
<> 154:37f96f9d4de2 242
<> 154:37f96f9d4de2 243 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
<> 154:37f96f9d4de2 244 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
<> 154:37f96f9d4de2 245
<> 154:37f96f9d4de2 246 kClockGateSdhc0 = (0x1030 << 16) | 17;
<> 154:37f96f9d4de2 247
<> 154:37f96f9d4de2 248 ------------------------------------------------------------------------------*/
<> 154:37f96f9d4de2 249
<> 154:37f96f9d4de2 250 #define CLK_GATE_REG_OFFSET_SHIFT 16U
<> 154:37f96f9d4de2 251 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
<> 154:37f96f9d4de2 252 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
<> 154:37f96f9d4de2 253 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
<> 154:37f96f9d4de2 254
<> 154:37f96f9d4de2 255 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
<> 154:37f96f9d4de2 256 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
<> 154:37f96f9d4de2 257 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
<> 154:37f96f9d4de2 258
<> 154:37f96f9d4de2 259 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
<> 154:37f96f9d4de2 260 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
<> 154:37f96f9d4de2 261
<> 154:37f96f9d4de2 262 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
<> 154:37f96f9d4de2 263 typedef enum _clock_ip_name
<> 154:37f96f9d4de2 264 {
<> 154:37f96f9d4de2 265 kCLOCK_IpInvalid = 0U,
<> 154:37f96f9d4de2 266
<> 154:37f96f9d4de2 267 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
<> 154:37f96f9d4de2 268 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
<> 154:37f96f9d4de2 269 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
<> 154:37f96f9d4de2 270 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
<> 154:37f96f9d4de2 271 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
<> 154:37f96f9d4de2 272
<> 154:37f96f9d4de2 273 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
<> 154:37f96f9d4de2 274 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
<> 154:37f96f9d4de2 275 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
<> 154:37f96f9d4de2 276 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
<> 154:37f96f9d4de2 277 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
<> 154:37f96f9d4de2 278 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
<> 154:37f96f9d4de2 279 kCLOCK_Aesa = CLK_GATE_DEFINE(0x1038U, 24U),
<> 154:37f96f9d4de2 280 kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x1038U, 24U),
<> 154:37f96f9d4de2 281 kCLOCK_Rsim = CLK_GATE_DEFINE(0x1038U, 25U),
<> 154:37f96f9d4de2 282 kCLOCK_Dcdc0 = CLK_GATE_DEFINE(0x1038U, 26U),
<> 154:37f96f9d4de2 283 kCLOCK_Btll = CLK_GATE_DEFINE(0x1038U, 27U),
<> 154:37f96f9d4de2 284 kCLOCK_PhyDig = CLK_GATE_DEFINE(0x1038U, 28U),
<> 154:37f96f9d4de2 285 kCLOCK_ZigBee = CLK_GATE_DEFINE(0x1038U, 29U),
<> 154:37f96f9d4de2 286 kCLOCK_GenFsk = CLK_GATE_DEFINE(0x1038U, 31U),
<> 154:37f96f9d4de2 287
<> 154:37f96f9d4de2 288 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
<> 154:37f96f9d4de2 289 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
<> 154:37f96f9d4de2 290 kCLOCK_Trng0 = CLK_GATE_DEFINE(0x103CU, 9U),
<> 154:37f96f9d4de2 291 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
<> 154:37f96f9d4de2 292 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
<> 154:37f96f9d4de2 293 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
<> 154:37f96f9d4de2 294 kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U),
<> 154:37f96f9d4de2 295 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U),
<> 154:37f96f9d4de2 296 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U),
<> 154:37f96f9d4de2 297 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
<> 154:37f96f9d4de2 298 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
<> 154:37f96f9d4de2 299 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
<> 154:37f96f9d4de2 300
<> 154:37f96f9d4de2 301 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
<> 154:37f96f9d4de2 302 } clock_ip_name_t;
<> 154:37f96f9d4de2 303
<> 154:37f96f9d4de2 304 /*!@brief SIM configuration structure for clock setting. */
<> 154:37f96f9d4de2 305 typedef struct _sim_clock_config
<> 154:37f96f9d4de2 306 {
<> 154:37f96f9d4de2 307 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
<> 154:37f96f9d4de2 308 uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
<> 154:37f96f9d4de2 309 uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
<> 154:37f96f9d4de2 310 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
<> 154:37f96f9d4de2 311 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
<> 154:37f96f9d4de2 312 } sim_clock_config_t;
<> 154:37f96f9d4de2 313
<> 154:37f96f9d4de2 314 /*! @brief OSC work mode. */
<> 154:37f96f9d4de2 315 typedef enum _osc_mode
<> 154:37f96f9d4de2 316 {
<> 154:37f96f9d4de2 317 kOSC_ModeExt = 0U, /*!< Use an external clock. */
<> 154:37f96f9d4de2 318 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
<> 154:37f96f9d4de2 319 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
<> 154:37f96f9d4de2 320 #else
<> 154:37f96f9d4de2 321 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
<> 154:37f96f9d4de2 322 #endif
<> 154:37f96f9d4de2 323 kOSC_ModeOscHighGain = 0U
<> 154:37f96f9d4de2 324 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
<> 154:37f96f9d4de2 325 |
<> 154:37f96f9d4de2 326 MCG_C2_EREFS_MASK
<> 154:37f96f9d4de2 327 #else
<> 154:37f96f9d4de2 328 |
<> 154:37f96f9d4de2 329 MCG_C2_EREFS0_MASK
<> 154:37f96f9d4de2 330 #endif
<> 154:37f96f9d4de2 331 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
<> 154:37f96f9d4de2 332 |
<> 154:37f96f9d4de2 333 MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
<> 154:37f96f9d4de2 334 #else
<> 154:37f96f9d4de2 335 |
<> 154:37f96f9d4de2 336 MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
<> 154:37f96f9d4de2 337 #endif
<> 154:37f96f9d4de2 338 } osc_mode_t;
<> 154:37f96f9d4de2 339
<> 154:37f96f9d4de2 340 /*!
<> 154:37f96f9d4de2 341 * @brief OSC Initialization Configuration Structure
<> 154:37f96f9d4de2 342 *
<> 154:37f96f9d4de2 343 * Defines the configuration data structure to initialize the OSC.
<> 154:37f96f9d4de2 344 * When porting to a new board, set the following members
<> 154:37f96f9d4de2 345 * according to the board setting:
<> 154:37f96f9d4de2 346 * 1. freq: The external frequency.
<> 154:37f96f9d4de2 347 * 2. workMode: The OSC module mode.
<> 154:37f96f9d4de2 348 */
<> 154:37f96f9d4de2 349 typedef struct _osc_config
<> 154:37f96f9d4de2 350 {
<> 154:37f96f9d4de2 351 uint32_t freq; /*!< External clock frequency. */
<> 154:37f96f9d4de2 352 osc_mode_t workMode; /*!< OSC work mode setting. */
<> 154:37f96f9d4de2 353 } osc_config_t;
<> 154:37f96f9d4de2 354
<> 154:37f96f9d4de2 355 /*! @brief MCG FLL reference clock source select. */
<> 154:37f96f9d4de2 356 typedef enum _mcg_fll_src
<> 154:37f96f9d4de2 357 {
<> 154:37f96f9d4de2 358 kMCG_FllSrcExternal, /*!< External reference clock is selected */
<> 154:37f96f9d4de2 359 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
<> 154:37f96f9d4de2 360 } mcg_fll_src_t;
<> 154:37f96f9d4de2 361
<> 154:37f96f9d4de2 362 /*! @brief MCG internal reference clock select */
<> 154:37f96f9d4de2 363 typedef enum _mcg_irc_mode
<> 154:37f96f9d4de2 364 {
<> 154:37f96f9d4de2 365 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
<> 154:37f96f9d4de2 366 kMCG_IrcFast /*!< Fast internal reference clock selected */
<> 154:37f96f9d4de2 367 } mcg_irc_mode_t;
<> 154:37f96f9d4de2 368
<> 154:37f96f9d4de2 369 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
<> 154:37f96f9d4de2 370 typedef enum _mcg_dmx32
<> 154:37f96f9d4de2 371 {
<> 154:37f96f9d4de2 372 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
<> 154:37f96f9d4de2 373 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
<> 154:37f96f9d4de2 374 } mcg_dmx32_t;
<> 154:37f96f9d4de2 375
<> 154:37f96f9d4de2 376 /*! @brief MCG DCO range select */
<> 154:37f96f9d4de2 377 typedef enum _mcg_drs
<> 154:37f96f9d4de2 378 {
<> 154:37f96f9d4de2 379 kMCG_DrsLow, /*!< Low frequency range */
<> 154:37f96f9d4de2 380 kMCG_DrsMid, /*!< Mid frequency range */
<> 154:37f96f9d4de2 381 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
<> 154:37f96f9d4de2 382 kMCG_DrsHigh /*!< High frequency range */
<> 154:37f96f9d4de2 383 } mcg_drs_t;
<> 154:37f96f9d4de2 384
<> 154:37f96f9d4de2 385 /*! @brief MCG PLL reference clock select */
<> 154:37f96f9d4de2 386 typedef enum _mcg_pll_ref_src
<> 154:37f96f9d4de2 387 {
<> 154:37f96f9d4de2 388 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
<> 154:37f96f9d4de2 389 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
<> 154:37f96f9d4de2 390 } mcg_pll_ref_src_t;
<> 154:37f96f9d4de2 391
<> 154:37f96f9d4de2 392 /*! @brief MCGOUT clock source. */
<> 154:37f96f9d4de2 393 typedef enum _mcg_clkout_src
<> 154:37f96f9d4de2 394 {
<> 154:37f96f9d4de2 395 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
<> 154:37f96f9d4de2 396 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
<> 154:37f96f9d4de2 397 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
<> 154:37f96f9d4de2 398 } mcg_clkout_src_t;
<> 154:37f96f9d4de2 399
<> 154:37f96f9d4de2 400 /*! @brief MCG Automatic Trim Machine Select */
<> 154:37f96f9d4de2 401 typedef enum _mcg_atm_select
<> 154:37f96f9d4de2 402 {
<> 154:37f96f9d4de2 403 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
<> 154:37f96f9d4de2 404 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
<> 154:37f96f9d4de2 405 } mcg_atm_select_t;
<> 154:37f96f9d4de2 406
<> 154:37f96f9d4de2 407 /*! @brief MCG OSC Clock Select */
<> 154:37f96f9d4de2 408 typedef enum _mcg_oscsel
<> 154:37f96f9d4de2 409 {
<> 154:37f96f9d4de2 410 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
<> 154:37f96f9d4de2 411 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
<> 154:37f96f9d4de2 412 } mcg_oscsel_t;
<> 154:37f96f9d4de2 413
<> 154:37f96f9d4de2 414 /*! @brief MCG PLLCS select */
<> 154:37f96f9d4de2 415 typedef enum _mcg_pll_clk_select
<> 154:37f96f9d4de2 416 {
<> 154:37f96f9d4de2 417 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
<> 154:37f96f9d4de2 418 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
<> 154:37f96f9d4de2 419 } mcg_pll_clk_select_t;
<> 154:37f96f9d4de2 420
<> 154:37f96f9d4de2 421 /*! @brief MCG clock monitor mode. */
<> 154:37f96f9d4de2 422 typedef enum _mcg_monitor_mode
<> 154:37f96f9d4de2 423 {
<> 154:37f96f9d4de2 424 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
<> 154:37f96f9d4de2 425 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
<> 154:37f96f9d4de2 426 kMCG_MonitorReset /*!< System reset when clock lost. */
<> 154:37f96f9d4de2 427 } mcg_monitor_mode_t;
<> 154:37f96f9d4de2 428
<> 154:37f96f9d4de2 429 /*! @brief MCG status. */
<> 154:37f96f9d4de2 430 enum _mcg_status
<> 154:37f96f9d4de2 431 {
<> 154:37f96f9d4de2 432 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */
<> 154:37f96f9d4de2 433 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
<> 154:37f96f9d4de2 434 function. */
<> 154:37f96f9d4de2 435 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */
<> 154:37f96f9d4de2 436 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
<> 154:37f96f9d4de2 437 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */
<> 154:37f96f9d4de2 438 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */
<> 154:37f96f9d4de2 439 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
<> 154:37f96f9d4de2 440 it is in use. */
<> 154:37f96f9d4de2 441 };
<> 154:37f96f9d4de2 442
<> 154:37f96f9d4de2 443 /*! @brief MCG status flags. */
<> 154:37f96f9d4de2 444 enum _mcg_status_flags_t
<> 154:37f96f9d4de2 445 {
<> 154:37f96f9d4de2 446 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
<> 154:37f96f9d4de2 447 };
<> 154:37f96f9d4de2 448
<> 154:37f96f9d4de2 449 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
<> 154:37f96f9d4de2 450 enum _mcg_irclk_enable_mode
<> 154:37f96f9d4de2 451 {
<> 154:37f96f9d4de2 452 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
<> 154:37f96f9d4de2 453 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
<> 154:37f96f9d4de2 454 };
<> 154:37f96f9d4de2 455
<> 154:37f96f9d4de2 456 /*! @brief MCG mode definitions */
<> 154:37f96f9d4de2 457 typedef enum _mcg_mode
<> 154:37f96f9d4de2 458 {
<> 154:37f96f9d4de2 459 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
<> 154:37f96f9d4de2 460 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
<> 154:37f96f9d4de2 461 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
<> 154:37f96f9d4de2 462 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
<> 154:37f96f9d4de2 463 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
<> 154:37f96f9d4de2 464 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
<> 154:37f96f9d4de2 465 kMCG_ModeError /*!< Unknown mode */
<> 154:37f96f9d4de2 466 } mcg_mode_t;
<> 154:37f96f9d4de2 467
<> 154:37f96f9d4de2 468 /*! @brief MCG mode change configuration structure
<> 154:37f96f9d4de2 469 *
<> 154:37f96f9d4de2 470 * When porting to a new board, set the following members
<> 154:37f96f9d4de2 471 * according to the board setting:
<> 154:37f96f9d4de2 472 * 1. frdiv: If the FLL uses the external reference clock, set this
<> 154:37f96f9d4de2 473 * value to ensure that the external reference clock divided by frdiv is
<> 154:37f96f9d4de2 474 * in the 31.25 kHz to 39.0625 kHz range.
<> 154:37f96f9d4de2 475 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
<> 154:37f96f9d4de2 476 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
<> 154:37f96f9d4de2 477 * FSL_FEATURE_MCG_PLL_REF_MAX range.
<> 154:37f96f9d4de2 478 */
<> 154:37f96f9d4de2 479 typedef struct _mcg_config
<> 154:37f96f9d4de2 480 {
<> 154:37f96f9d4de2 481 mcg_mode_t mcgMode; /*!< MCG mode. */
<> 154:37f96f9d4de2 482
<> 154:37f96f9d4de2 483 /* ----------------------- MCGIRCCLK settings ------------------------ */
<> 154:37f96f9d4de2 484 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
<> 154:37f96f9d4de2 485 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
<> 154:37f96f9d4de2 486 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
<> 154:37f96f9d4de2 487
<> 154:37f96f9d4de2 488 /* ------------------------ MCG FLL settings ------------------------- */
<> 154:37f96f9d4de2 489 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
<> 154:37f96f9d4de2 490 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
<> 154:37f96f9d4de2 491 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
<> 154:37f96f9d4de2 492 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
<> 154:37f96f9d4de2 493
<> 154:37f96f9d4de2 494 /* ------------------------ MCG PLL settings ------------------------- */
<> 154:37f96f9d4de2 495 } mcg_config_t;
<> 154:37f96f9d4de2 496
<> 154:37f96f9d4de2 497 /*******************************************************************************
<> 154:37f96f9d4de2 498 * API
<> 154:37f96f9d4de2 499 ******************************************************************************/
<> 154:37f96f9d4de2 500
<> 154:37f96f9d4de2 501 #if defined(__cplusplus)
<> 154:37f96f9d4de2 502 extern "C" {
<> 154:37f96f9d4de2 503 #endif /* __cplusplus */
<> 154:37f96f9d4de2 504
<> 154:37f96f9d4de2 505 /*!
<> 154:37f96f9d4de2 506 * @brief Enable the clock for specific IP.
<> 154:37f96f9d4de2 507 *
<> 154:37f96f9d4de2 508 * @param name Which clock to enable, see \ref clock_ip_name_t.
<> 154:37f96f9d4de2 509 */
<> 154:37f96f9d4de2 510 static inline void CLOCK_EnableClock(clock_ip_name_t name)
<> 154:37f96f9d4de2 511 {
<> 154:37f96f9d4de2 512 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
<> 154:37f96f9d4de2 513 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
<> 154:37f96f9d4de2 514 }
<> 154:37f96f9d4de2 515
<> 154:37f96f9d4de2 516 /*!
<> 154:37f96f9d4de2 517 * @brief Disable the clock for specific IP.
<> 154:37f96f9d4de2 518 *
<> 154:37f96f9d4de2 519 * @param name Which clock to disable, see \ref clock_ip_name_t.
<> 154:37f96f9d4de2 520 */
<> 154:37f96f9d4de2 521 static inline void CLOCK_DisableClock(clock_ip_name_t name)
<> 154:37f96f9d4de2 522 {
<> 154:37f96f9d4de2 523 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
<> 154:37f96f9d4de2 524 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
<> 154:37f96f9d4de2 525 }
<> 154:37f96f9d4de2 526
<> 154:37f96f9d4de2 527 /*!
<> 154:37f96f9d4de2 528 * @brief Set ERCLK32K source.
<> 154:37f96f9d4de2 529 *
<> 154:37f96f9d4de2 530 * @param src The value to set ERCLK32K clock source.
<> 154:37f96f9d4de2 531 */
<> 154:37f96f9d4de2 532 static inline void CLOCK_SetEr32kClock(uint32_t src)
<> 154:37f96f9d4de2 533 {
<> 154:37f96f9d4de2 534 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
<> 154:37f96f9d4de2 535 }
<> 154:37f96f9d4de2 536
<> 154:37f96f9d4de2 537 /*!
<> 154:37f96f9d4de2 538 * @brief Set LPUART clock source.
<> 154:37f96f9d4de2 539 *
<> 154:37f96f9d4de2 540 * @param src The value to set LPUART clock source.
<> 154:37f96f9d4de2 541 */
<> 154:37f96f9d4de2 542 static inline void CLOCK_SetLpuartClock(uint32_t src)
<> 154:37f96f9d4de2 543 {
<> 154:37f96f9d4de2 544 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src));
<> 154:37f96f9d4de2 545 }
<> 154:37f96f9d4de2 546
<> 154:37f96f9d4de2 547 /*!
<> 154:37f96f9d4de2 548 * @brief Set TPM clock source.
<> 154:37f96f9d4de2 549 *
<> 154:37f96f9d4de2 550 * @param src The value to set TPM clock source.
<> 154:37f96f9d4de2 551 */
<> 154:37f96f9d4de2 552 static inline void CLOCK_SetTpmClock(uint32_t src)
<> 154:37f96f9d4de2 553 {
<> 154:37f96f9d4de2 554 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
<> 154:37f96f9d4de2 555 }
<> 154:37f96f9d4de2 556
<> 154:37f96f9d4de2 557 /*!
<> 154:37f96f9d4de2 558 * @brief Set CLKOUT source.
<> 154:37f96f9d4de2 559 *
<> 154:37f96f9d4de2 560 * @param src The value to set CLKOUT source.
<> 154:37f96f9d4de2 561 */
<> 154:37f96f9d4de2 562 static inline void CLOCK_SetClkOutClock(uint32_t src)
<> 154:37f96f9d4de2 563 {
<> 154:37f96f9d4de2 564 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
<> 154:37f96f9d4de2 565 }
<> 154:37f96f9d4de2 566
<> 154:37f96f9d4de2 567 /*!
<> 154:37f96f9d4de2 568 * @brief System clock divider
<> 154:37f96f9d4de2 569 *
<> 154:37f96f9d4de2 570 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4].
<> 154:37f96f9d4de2 571 *
<> 154:37f96f9d4de2 572 * @param outdiv1 Clock 1 output divider value.
<> 154:37f96f9d4de2 573 *
<> 154:37f96f9d4de2 574 * @param outdiv4 Clock 4 output divider value.
<> 154:37f96f9d4de2 575 */
<> 154:37f96f9d4de2 576 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4)
<> 154:37f96f9d4de2 577 {
<> 154:37f96f9d4de2 578 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4);
<> 154:37f96f9d4de2 579 }
<> 154:37f96f9d4de2 580
<> 154:37f96f9d4de2 581 /*!
<> 154:37f96f9d4de2 582 * @brief Gets the clock frequency for a specific clock name.
<> 154:37f96f9d4de2 583 *
<> 154:37f96f9d4de2 584 * This function checks the current clock configurations and then calculates
<> 154:37f96f9d4de2 585 * the clock frequency for a specific clock name defined in clock_name_t.
<> 154:37f96f9d4de2 586 * The MCG must be properly configured before using this function.
<> 154:37f96f9d4de2 587 *
<> 154:37f96f9d4de2 588 * @param clockName Clock names defined in clock_name_t
<> 154:37f96f9d4de2 589 * @return Clock frequency value in Hertz
<> 154:37f96f9d4de2 590 */
<> 154:37f96f9d4de2 591 uint32_t CLOCK_GetFreq(clock_name_t clockName);
<> 154:37f96f9d4de2 592
<> 154:37f96f9d4de2 593 /*!
<> 154:37f96f9d4de2 594 * @brief Get the core clock or system clock frequency.
<> 154:37f96f9d4de2 595 *
<> 154:37f96f9d4de2 596 * @return Clock frequency in Hz.
<> 154:37f96f9d4de2 597 */
<> 154:37f96f9d4de2 598 uint32_t CLOCK_GetCoreSysClkFreq(void);
<> 154:37f96f9d4de2 599
<> 154:37f96f9d4de2 600 /*!
<> 154:37f96f9d4de2 601 * @brief Get the platform clock frequency.
<> 154:37f96f9d4de2 602 *
<> 154:37f96f9d4de2 603 * @return Clock frequency in Hz.
<> 154:37f96f9d4de2 604 */
<> 154:37f96f9d4de2 605 uint32_t CLOCK_GetPlatClkFreq(void);
<> 154:37f96f9d4de2 606
<> 154:37f96f9d4de2 607 /*!
<> 154:37f96f9d4de2 608 * @brief Get the bus clock frequency.
<> 154:37f96f9d4de2 609 *
<> 154:37f96f9d4de2 610 * @return Clock frequency in Hz.
<> 154:37f96f9d4de2 611 */
<> 154:37f96f9d4de2 612 uint32_t CLOCK_GetBusClkFreq(void);
<> 154:37f96f9d4de2 613
<> 154:37f96f9d4de2 614 /*!
<> 154:37f96f9d4de2 615 * @brief Get the flash clock frequency.
<> 154:37f96f9d4de2 616 *
<> 154:37f96f9d4de2 617 * @return Clock frequency in Hz.
<> 154:37f96f9d4de2 618 */
<> 154:37f96f9d4de2 619 uint32_t CLOCK_GetFlashClkFreq(void);
<> 154:37f96f9d4de2 620
<> 154:37f96f9d4de2 621 /*!
<> 154:37f96f9d4de2 622 * @brief Get the external reference 32K clock frequency (ERCLK32K).
<> 154:37f96f9d4de2 623 *
<> 154:37f96f9d4de2 624 * @return Clock frequency in Hz.
<> 154:37f96f9d4de2 625 */
<> 154:37f96f9d4de2 626 uint32_t CLOCK_GetEr32kClkFreq(void);
<> 154:37f96f9d4de2 627
<> 154:37f96f9d4de2 628 /*!
<> 154:37f96f9d4de2 629 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
<> 154:37f96f9d4de2 630 *
<> 154:37f96f9d4de2 631 * @return Clock frequency in Hz.
<> 154:37f96f9d4de2 632 */
<> 154:37f96f9d4de2 633 uint32_t CLOCK_GetOsc0ErClkFreq(void);
<> 154:37f96f9d4de2 634
<> 154:37f96f9d4de2 635 /*!
<> 154:37f96f9d4de2 636 * @brief Set the clock configure in SIM module.
<> 154:37f96f9d4de2 637 *
<> 154:37f96f9d4de2 638 * This function sets system layer clock settings in SIM module.
<> 154:37f96f9d4de2 639 *
<> 154:37f96f9d4de2 640 * @param config Pointer to the configure structure.
<> 154:37f96f9d4de2 641 */
<> 154:37f96f9d4de2 642 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
<> 154:37f96f9d4de2 643
<> 154:37f96f9d4de2 644 /*!
<> 154:37f96f9d4de2 645 * @brief Set the system clock dividers in SIM to safe value.
<> 154:37f96f9d4de2 646 *
<> 154:37f96f9d4de2 647 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
<> 154:37f96f9d4de2 648 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
<> 154:37f96f9d4de2 649 * changes then the system level clocks may be out of range. This function could
<> 154:37f96f9d4de2 650 * be used before MCG mode change, to make sure system level clocks are in allowed
<> 154:37f96f9d4de2 651 * range.
<> 154:37f96f9d4de2 652 *
<> 154:37f96f9d4de2 653 * @param config Pointer to the configure structure.
<> 154:37f96f9d4de2 654 */
<> 154:37f96f9d4de2 655 static inline void CLOCK_SetSimSafeDivs(void)
<> 154:37f96f9d4de2 656 {
<> 154:37f96f9d4de2 657 SIM->CLKDIV1 = 0x00040000U;
<> 154:37f96f9d4de2 658 }
<> 154:37f96f9d4de2 659
<> 154:37f96f9d4de2 660 /*! @name MCG frequency functions. */
<> 154:37f96f9d4de2 661 /*@{*/
<> 154:37f96f9d4de2 662
<> 154:37f96f9d4de2 663 /*!
<> 154:37f96f9d4de2 664 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
<> 154:37f96f9d4de2 665 *
<> 154:37f96f9d4de2 666 * This function gets the MCG output clock frequency in Hz based on the current MCG
<> 154:37f96f9d4de2 667 * register value.
<> 154:37f96f9d4de2 668 *
<> 154:37f96f9d4de2 669 * @return The frequency of MCGOUTCLK.
<> 154:37f96f9d4de2 670 */
<> 154:37f96f9d4de2 671 uint32_t CLOCK_GetOutClkFreq(void);
<> 154:37f96f9d4de2 672
<> 154:37f96f9d4de2 673 /*!
<> 154:37f96f9d4de2 674 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
<> 154:37f96f9d4de2 675 *
<> 154:37f96f9d4de2 676 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
<> 154:37f96f9d4de2 677 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
<> 154:37f96f9d4de2 678 * disabled in low power state in other modes.
<> 154:37f96f9d4de2 679 *
<> 154:37f96f9d4de2 680 * @return The frequency of MCGFLLCLK.
<> 154:37f96f9d4de2 681 */
<> 154:37f96f9d4de2 682 uint32_t CLOCK_GetFllFreq(void);
<> 154:37f96f9d4de2 683
<> 154:37f96f9d4de2 684 /*!
<> 154:37f96f9d4de2 685 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
<> 154:37f96f9d4de2 686 *
<> 154:37f96f9d4de2 687 * This function gets the MCG internal reference clock frequency in Hz based
<> 154:37f96f9d4de2 688 * on the current MCG register value.
<> 154:37f96f9d4de2 689 *
<> 154:37f96f9d4de2 690 * @return The frequency of MCGIRCLK.
<> 154:37f96f9d4de2 691 */
<> 154:37f96f9d4de2 692 uint32_t CLOCK_GetInternalRefClkFreq(void);
<> 154:37f96f9d4de2 693
<> 154:37f96f9d4de2 694 /*!
<> 154:37f96f9d4de2 695 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
<> 154:37f96f9d4de2 696 *
<> 154:37f96f9d4de2 697 * This function gets the MCG fixed frequency clock frequency in Hz based
<> 154:37f96f9d4de2 698 * on the current MCG register value.
<> 154:37f96f9d4de2 699 *
<> 154:37f96f9d4de2 700 * @return The frequency of MCGFFCLK.
<> 154:37f96f9d4de2 701 */
<> 154:37f96f9d4de2 702 uint32_t CLOCK_GetFixedFreqClkFreq(void);
<> 154:37f96f9d4de2 703
<> 154:37f96f9d4de2 704 /*@}*/
<> 154:37f96f9d4de2 705
<> 154:37f96f9d4de2 706 /*! @name MCG clock configuration. */
<> 154:37f96f9d4de2 707 /*@{*/
<> 154:37f96f9d4de2 708
<> 154:37f96f9d4de2 709 /*!
<> 154:37f96f9d4de2 710 * @brief Enables or disables the MCG low power.
<> 154:37f96f9d4de2 711 *
<> 154:37f96f9d4de2 712 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
<> 154:37f96f9d4de2 713 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
<> 154:37f96f9d4de2 714 * PBI modes, enabling low power sets the MCG to BLPI mode.
<> 154:37f96f9d4de2 715 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
<> 154:37f96f9d4de2 716 *
<> 154:37f96f9d4de2 717 * @param enable True to enable MCG low power, false to disable MCG low power.
<> 154:37f96f9d4de2 718 */
<> 154:37f96f9d4de2 719 static inline void CLOCK_SetLowPowerEnable(bool enable)
<> 154:37f96f9d4de2 720 {
<> 154:37f96f9d4de2 721 if (enable)
<> 154:37f96f9d4de2 722 {
<> 154:37f96f9d4de2 723 MCG->C2 |= MCG_C2_LP_MASK;
<> 154:37f96f9d4de2 724 }
<> 154:37f96f9d4de2 725 else
<> 154:37f96f9d4de2 726 {
<> 154:37f96f9d4de2 727 MCG->C2 &= ~MCG_C2_LP_MASK;
<> 154:37f96f9d4de2 728 }
<> 154:37f96f9d4de2 729 }
<> 154:37f96f9d4de2 730
<> 154:37f96f9d4de2 731 /*!
<> 154:37f96f9d4de2 732 * @brief Configures the Internal Reference clock (MCGIRCLK).
<> 154:37f96f9d4de2 733 *
<> 154:37f96f9d4de2 734 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
<> 154:37f96f9d4de2 735 * source. If the fast IRC is used, this function sets the fast IRC divider.
<> 154:37f96f9d4de2 736 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
<> 154:37f96f9d4de2 737 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
<> 154:37f96f9d4de2 738 * using the function in these modes it is not allowed.
<> 154:37f96f9d4de2 739 *
<> 154:37f96f9d4de2 740 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
<> 154:37f96f9d4de2 741 * @param ircs MCGIRCLK clock source, choose fast or slow.
<> 154:37f96f9d4de2 742 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
<> 154:37f96f9d4de2 743 * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
<> 154:37f96f9d4de2 744 * the confuration should not be changed. Otherwise, a glitch occurs.
<> 154:37f96f9d4de2 745 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
<> 154:37f96f9d4de2 746 */
<> 154:37f96f9d4de2 747 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
<> 154:37f96f9d4de2 748
<> 154:37f96f9d4de2 749 /*!
<> 154:37f96f9d4de2 750 * @brief Selects the MCG external reference clock.
<> 154:37f96f9d4de2 751 *
<> 154:37f96f9d4de2 752 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
<> 154:37f96f9d4de2 753 * and waits for the clock source to be stable. Because the external reference
<> 154:37f96f9d4de2 754 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
<> 154:37f96f9d4de2 755 *
<> 154:37f96f9d4de2 756 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
<> 154:37f96f9d4de2 757 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
<> 154:37f96f9d4de2 758 * the confuration should not be changed. Otherwise, a glitch occurs.
<> 154:37f96f9d4de2 759 * @retval kStatus_Success External reference clock set successfully.
<> 154:37f96f9d4de2 760 */
<> 154:37f96f9d4de2 761 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
<> 154:37f96f9d4de2 762
<> 154:37f96f9d4de2 763 /*!
<> 154:37f96f9d4de2 764 * @brief Set the FLL external reference clock divider value.
<> 154:37f96f9d4de2 765 *
<> 154:37f96f9d4de2 766 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
<> 154:37f96f9d4de2 767 *
<> 154:37f96f9d4de2 768 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
<> 154:37f96f9d4de2 769 */
<> 154:37f96f9d4de2 770 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
<> 154:37f96f9d4de2 771 {
<> 154:37f96f9d4de2 772 MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv);
<> 154:37f96f9d4de2 773 }
<> 154:37f96f9d4de2 774
<> 154:37f96f9d4de2 775 /*@}*/
<> 154:37f96f9d4de2 776
<> 154:37f96f9d4de2 777 /*! @name MCG clock lock monitor functions. */
<> 154:37f96f9d4de2 778 /*@{*/
<> 154:37f96f9d4de2 779
<> 154:37f96f9d4de2 780 /*!
<> 154:37f96f9d4de2 781 * @brief Sets the RTC OSC clock monitor mode.
<> 154:37f96f9d4de2 782 *
<> 154:37f96f9d4de2 783 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
<> 154:37f96f9d4de2 784 *
<> 154:37f96f9d4de2 785 * @param mode Monitor mode to set.
<> 154:37f96f9d4de2 786 */
<> 154:37f96f9d4de2 787 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
<> 154:37f96f9d4de2 788
<> 154:37f96f9d4de2 789 /*!
<> 154:37f96f9d4de2 790 * @brief Gets the MCG status flags.
<> 154:37f96f9d4de2 791 *
<> 154:37f96f9d4de2 792 * This function gets the MCG clock status flags. All status flags are
<> 154:37f96f9d4de2 793 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
<> 154:37f96f9d4de2 794 * check a specific flag, compare the return value with the flag.
<> 154:37f96f9d4de2 795 *
<> 154:37f96f9d4de2 796 * Example:
<> 154:37f96f9d4de2 797 * @code
<> 154:37f96f9d4de2 798 // To check the clock lost lock status of OSC0 and PLL0.
<> 154:37f96f9d4de2 799 uint32_t mcgFlags;
<> 154:37f96f9d4de2 800
<> 154:37f96f9d4de2 801 mcgFlags = CLOCK_GetStatusFlags();
<> 154:37f96f9d4de2 802
<> 154:37f96f9d4de2 803 if (mcgFlags & kMCG_Osc0LostFlag)
<> 154:37f96f9d4de2 804 {
<> 154:37f96f9d4de2 805 // OSC0 clock lock lost. Do something.
<> 154:37f96f9d4de2 806 }
<> 154:37f96f9d4de2 807 if (mcgFlags & kMCG_Pll0LostFlag)
<> 154:37f96f9d4de2 808 {
<> 154:37f96f9d4de2 809 // PLL0 clock lock lost. Do something.
<> 154:37f96f9d4de2 810 }
<> 154:37f96f9d4de2 811 @endcode
<> 154:37f96f9d4de2 812 *
<> 154:37f96f9d4de2 813 * @return Logical OR value of the @ref _mcg_status_flags_t.
<> 154:37f96f9d4de2 814 */
<> 154:37f96f9d4de2 815 uint32_t CLOCK_GetStatusFlags(void);
<> 154:37f96f9d4de2 816
<> 154:37f96f9d4de2 817 /*!
<> 154:37f96f9d4de2 818 * @brief Clears the MCG status flags.
<> 154:37f96f9d4de2 819 *
<> 154:37f96f9d4de2 820 * This function clears the MCG clock lock lost status. The parameter is a logical
<> 154:37f96f9d4de2 821 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
<> 154:37f96f9d4de2 822 *
<> 154:37f96f9d4de2 823 * Example:
<> 154:37f96f9d4de2 824 * @code
<> 154:37f96f9d4de2 825 // To clear the clock lost lock status flags of OSC0 and PLL0.
<> 154:37f96f9d4de2 826
<> 154:37f96f9d4de2 827 CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
<> 154:37f96f9d4de2 828 @endcode
<> 154:37f96f9d4de2 829 *
<> 154:37f96f9d4de2 830 * @param mask The status flags to clear. This is a logical OR of members of the
<> 154:37f96f9d4de2 831 * enumeration @ref _mcg_status_flags_t.
<> 154:37f96f9d4de2 832 */
<> 154:37f96f9d4de2 833 void CLOCK_ClearStatusFlags(uint32_t mask);
<> 154:37f96f9d4de2 834
<> 154:37f96f9d4de2 835 /*@}*/
<> 154:37f96f9d4de2 836
<> 154:37f96f9d4de2 837 /*!
<> 154:37f96f9d4de2 838 * @name OSC configuration
<> 154:37f96f9d4de2 839 * @{
<> 154:37f96f9d4de2 840 */
<> 154:37f96f9d4de2 841
<> 154:37f96f9d4de2 842 /*!
<> 154:37f96f9d4de2 843 * @brief Initializes the OSC0.
<> 154:37f96f9d4de2 844 *
<> 154:37f96f9d4de2 845 * This function initializes the OSC0 according to the board configuration.
<> 154:37f96f9d4de2 846 *
<> 154:37f96f9d4de2 847 * @param config Pointer to the OSC0 configuration structure.
<> 154:37f96f9d4de2 848 */
<> 154:37f96f9d4de2 849 void CLOCK_InitOsc0(osc_config_t const *config);
<> 154:37f96f9d4de2 850
<> 154:37f96f9d4de2 851 /*!
<> 154:37f96f9d4de2 852 * @brief Deinitializes the OSC0.
<> 154:37f96f9d4de2 853 *
<> 154:37f96f9d4de2 854 * This function deinitializes the OSC0.
<> 154:37f96f9d4de2 855 */
<> 154:37f96f9d4de2 856 void CLOCK_DeinitOsc0(void);
<> 154:37f96f9d4de2 857
<> 154:37f96f9d4de2 858 /* @} */
<> 154:37f96f9d4de2 859
<> 154:37f96f9d4de2 860 /*!
<> 154:37f96f9d4de2 861 * @name External clock frequency
<> 154:37f96f9d4de2 862 * @{
<> 154:37f96f9d4de2 863 */
<> 154:37f96f9d4de2 864
<> 154:37f96f9d4de2 865 /*!
<> 154:37f96f9d4de2 866 * @brief Sets the XTAL0 frequency based on board settings.
<> 154:37f96f9d4de2 867 *
<> 154:37f96f9d4de2 868 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
<> 154:37f96f9d4de2 869 */
<> 154:37f96f9d4de2 870 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
<> 154:37f96f9d4de2 871 {
<> 154:37f96f9d4de2 872 g_xtal0Freq = freq;
<> 154:37f96f9d4de2 873 }
<> 154:37f96f9d4de2 874
<> 154:37f96f9d4de2 875 /*!
<> 154:37f96f9d4de2 876 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
<> 154:37f96f9d4de2 877 *
<> 154:37f96f9d4de2 878 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
<> 154:37f96f9d4de2 879 */
<> 154:37f96f9d4de2 880 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
<> 154:37f96f9d4de2 881 {
<> 154:37f96f9d4de2 882 g_xtal32Freq = freq;
<> 154:37f96f9d4de2 883 }
<> 154:37f96f9d4de2 884 /* @} */
<> 154:37f96f9d4de2 885
<> 154:37f96f9d4de2 886 /*!
<> 154:37f96f9d4de2 887 * @name MCG auto-trim machine.
<> 154:37f96f9d4de2 888 * @{
<> 154:37f96f9d4de2 889 */
<> 154:37f96f9d4de2 890
<> 154:37f96f9d4de2 891 /*!
<> 154:37f96f9d4de2 892 * @brief Auto trims the internal reference clock.
<> 154:37f96f9d4de2 893 *
<> 154:37f96f9d4de2 894 * This function trims the internal reference clock by using the external clock. If
<> 154:37f96f9d4de2 895 * successful, it returns the kStatus_Success and the frequency after
<> 154:37f96f9d4de2 896 * trimming is received in the parameter @p actualFreq. If an error occurs,
<> 154:37f96f9d4de2 897 * the error code is returned.
<> 154:37f96f9d4de2 898 *
<> 154:37f96f9d4de2 899 * @param extFreq External clock frequency, which should be a bus clock.
<> 154:37f96f9d4de2 900 * @param desireFreq Frequency to trim to.
<> 154:37f96f9d4de2 901 * @param actualFreq Actual frequency after trimming.
<> 154:37f96f9d4de2 902 * @param atms Trim fast or slow internal reference clock.
<> 154:37f96f9d4de2 903 * @retval kStatus_Success ATM success.
<> 154:37f96f9d4de2 904 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
<> 154:37f96f9d4de2 905 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
<> 154:37f96f9d4de2 906 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
<> 154:37f96f9d4de2 907 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
<> 154:37f96f9d4de2 908 */
<> 154:37f96f9d4de2 909 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
<> 154:37f96f9d4de2 910 /* @} */
<> 154:37f96f9d4de2 911
<> 154:37f96f9d4de2 912 /*! @name MCG mode functions. */
<> 154:37f96f9d4de2 913 /*@{*/
<> 154:37f96f9d4de2 914
<> 154:37f96f9d4de2 915 /*!
<> 154:37f96f9d4de2 916 * @brief Gets the current MCG mode.
<> 154:37f96f9d4de2 917 *
<> 154:37f96f9d4de2 918 * This function checks the MCG registers and determines the current MCG mode.
<> 154:37f96f9d4de2 919 *
<> 154:37f96f9d4de2 920 * @return Current MCG mode or error code; See @ref mcg_mode_t.
<> 154:37f96f9d4de2 921 */
<> 154:37f96f9d4de2 922 mcg_mode_t CLOCK_GetMode(void);
<> 154:37f96f9d4de2 923
<> 154:37f96f9d4de2 924 /*!
<> 154:37f96f9d4de2 925 * @brief Sets the MCG to FEI mode.
<> 154:37f96f9d4de2 926 *
<> 154:37f96f9d4de2 927 * This function sets the MCG to FEI mode. If setting to FEI mode fails
<> 154:37f96f9d4de2 928 * from the current mode, this function returns an error.
<> 154:37f96f9d4de2 929 *
<> 154:37f96f9d4de2 930 * @param dmx32 DMX32 in FEI mode.
<> 154:37f96f9d4de2 931 * @param drs The DCO range selection.
<> 154:37f96f9d4de2 932 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
<> 154:37f96f9d4de2 933 * NULL does not cause a delay.
<> 154:37f96f9d4de2 934 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 935 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 936 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
<> 154:37f96f9d4de2 937 * to a frequency above 32768 Hz.
<> 154:37f96f9d4de2 938 */
<> 154:37f96f9d4de2 939 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
<> 154:37f96f9d4de2 940
<> 154:37f96f9d4de2 941 /*!
<> 154:37f96f9d4de2 942 * @brief Sets the MCG to FEE mode.
<> 154:37f96f9d4de2 943 *
<> 154:37f96f9d4de2 944 * This function sets the MCG to FEE mode. If setting to FEE mode fails
<> 154:37f96f9d4de2 945 * from the current mode, this function returns an error.
<> 154:37f96f9d4de2 946 *
<> 154:37f96f9d4de2 947 * @param frdiv FLL reference clock divider setting, FRDIV.
<> 154:37f96f9d4de2 948 * @param dmx32 DMX32 in FEE mode.
<> 154:37f96f9d4de2 949 * @param drs The DCO range selection.
<> 154:37f96f9d4de2 950 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
<> 154:37f96f9d4de2 951 * NULL does not cause a delay.
<> 154:37f96f9d4de2 952 *
<> 154:37f96f9d4de2 953 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 954 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 955 */
<> 154:37f96f9d4de2 956 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
<> 154:37f96f9d4de2 957
<> 154:37f96f9d4de2 958 /*!
<> 154:37f96f9d4de2 959 * @brief Sets the MCG to FBI mode.
<> 154:37f96f9d4de2 960 *
<> 154:37f96f9d4de2 961 * This function sets the MCG to FBI mode. If setting to FBI mode fails
<> 154:37f96f9d4de2 962 * from the current mode, this function returns an error.
<> 154:37f96f9d4de2 963 *
<> 154:37f96f9d4de2 964 * @param dmx32 DMX32 in FBI mode.
<> 154:37f96f9d4de2 965 * @param drs The DCO range selection.
<> 154:37f96f9d4de2 966 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
<> 154:37f96f9d4de2 967 * is not used in FBI mode, this parameter can be NULL. Passing
<> 154:37f96f9d4de2 968 * NULL does not cause a delay.
<> 154:37f96f9d4de2 969 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 970 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 971 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
<> 154:37f96f9d4de2 972 * to frequency above 32768 Hz.
<> 154:37f96f9d4de2 973 */
<> 154:37f96f9d4de2 974 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
<> 154:37f96f9d4de2 975
<> 154:37f96f9d4de2 976 /*!
<> 154:37f96f9d4de2 977 * @brief Sets the MCG to FBE mode.
<> 154:37f96f9d4de2 978 *
<> 154:37f96f9d4de2 979 * This function sets the MCG to FBE mode. If setting to FBE mode fails
<> 154:37f96f9d4de2 980 * from the current mode, this function returns an error.
<> 154:37f96f9d4de2 981 *
<> 154:37f96f9d4de2 982 * @param frdiv FLL reference clock divider setting, FRDIV.
<> 154:37f96f9d4de2 983 * @param dmx32 DMX32 in FBE mode.
<> 154:37f96f9d4de2 984 * @param drs The DCO range selection.
<> 154:37f96f9d4de2 985 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
<> 154:37f96f9d4de2 986 * is not used in FBE mode, this parameter can be NULL. Passing NULL
<> 154:37f96f9d4de2 987 * does not cause a delay.
<> 154:37f96f9d4de2 988 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 989 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 990 */
<> 154:37f96f9d4de2 991 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
<> 154:37f96f9d4de2 992
<> 154:37f96f9d4de2 993 /*!
<> 154:37f96f9d4de2 994 * @brief Sets the MCG to BLPI mode.
<> 154:37f96f9d4de2 995 *
<> 154:37f96f9d4de2 996 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
<> 154:37f96f9d4de2 997 * from the current mode, this function returns an error.
<> 154:37f96f9d4de2 998 *
<> 154:37f96f9d4de2 999 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 1000 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 1001 */
<> 154:37f96f9d4de2 1002 status_t CLOCK_SetBlpiMode(void);
<> 154:37f96f9d4de2 1003
<> 154:37f96f9d4de2 1004 /*!
<> 154:37f96f9d4de2 1005 * @brief Sets the MCG to BLPE mode.
<> 154:37f96f9d4de2 1006 *
<> 154:37f96f9d4de2 1007 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
<> 154:37f96f9d4de2 1008 * from the current mode, this function returns an error.
<> 154:37f96f9d4de2 1009 *
<> 154:37f96f9d4de2 1010 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 1011 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 1012 */
<> 154:37f96f9d4de2 1013 status_t CLOCK_SetBlpeMode(void);
<> 154:37f96f9d4de2 1014
<> 154:37f96f9d4de2 1015 /*!
<> 154:37f96f9d4de2 1016 * @brief Switches the MCG to FBE mode from the external mode.
<> 154:37f96f9d4de2 1017 *
<> 154:37f96f9d4de2 1018 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
<> 154:37f96f9d4de2 1019 * The external clock is used as the system clock souce and PLL is disabled. However,
<> 154:37f96f9d4de2 1020 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
<> 154:37f96f9d4de2 1021 * during the mode switch. For example, to switch from PEE mode to FEI mode:
<> 154:37f96f9d4de2 1022 *
<> 154:37f96f9d4de2 1023 * @code
<> 154:37f96f9d4de2 1024 * CLOCK_ExternalModeToFbeModeQuick();
<> 154:37f96f9d4de2 1025 * CLOCK_SetFeiMode(...);
<> 154:37f96f9d4de2 1026 * @endcode
<> 154:37f96f9d4de2 1027 *
<> 154:37f96f9d4de2 1028 * @retval kStatus_Success Switched successfully.
<> 154:37f96f9d4de2 1029 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
<> 154:37f96f9d4de2 1030 */
<> 154:37f96f9d4de2 1031 status_t CLOCK_ExternalModeToFbeModeQuick(void);
<> 154:37f96f9d4de2 1032
<> 154:37f96f9d4de2 1033 /*!
<> 154:37f96f9d4de2 1034 * @brief Switches the MCG to FBI mode from internal modes.
<> 154:37f96f9d4de2 1035 *
<> 154:37f96f9d4de2 1036 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
<> 154:37f96f9d4de2 1037 * The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
<> 154:37f96f9d4de2 1038 * FLL settings are not configured. This is a lite function with a small code size, which is useful
<> 154:37f96f9d4de2 1039 * during the mode switch. For example, to switch from PEI mode to FEE mode:
<> 154:37f96f9d4de2 1040 *
<> 154:37f96f9d4de2 1041 * @code
<> 154:37f96f9d4de2 1042 * CLOCK_InternalModeToFbiModeQuick();
<> 154:37f96f9d4de2 1043 * CLOCK_SetFeeMode(...);
<> 154:37f96f9d4de2 1044 * @endcode
<> 154:37f96f9d4de2 1045 *
<> 154:37f96f9d4de2 1046 * @retval kStatus_Success Switched successfully.
<> 154:37f96f9d4de2 1047 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
<> 154:37f96f9d4de2 1048 */
<> 154:37f96f9d4de2 1049 status_t CLOCK_InternalModeToFbiModeQuick(void);
<> 154:37f96f9d4de2 1050
<> 154:37f96f9d4de2 1051 /*!
<> 154:37f96f9d4de2 1052 * @brief Sets the MCG to FEI mode during system boot up.
<> 154:37f96f9d4de2 1053 *
<> 154:37f96f9d4de2 1054 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
<> 154:37f96f9d4de2 1055 * set up MCG during system boot up.
<> 154:37f96f9d4de2 1056 *
<> 154:37f96f9d4de2 1057 * @param dmx32 DMX32 in FEI mode.
<> 154:37f96f9d4de2 1058 * @param drs The DCO range selection.
<> 154:37f96f9d4de2 1059 * @param fllStableDelay Delay function to ensure that the FLL is stable.
<> 154:37f96f9d4de2 1060 *
<> 154:37f96f9d4de2 1061 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 1062 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 1063 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
<> 154:37f96f9d4de2 1064 * to frequency above 32768 Hz.
<> 154:37f96f9d4de2 1065 */
<> 154:37f96f9d4de2 1066 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
<> 154:37f96f9d4de2 1067
<> 154:37f96f9d4de2 1068 /*!
<> 154:37f96f9d4de2 1069 * @brief Sets the MCG to FEE mode during system bootup.
<> 154:37f96f9d4de2 1070 *
<> 154:37f96f9d4de2 1071 * This function sets MCG to FEE mode from the reset mode. It can also be used to
<> 154:37f96f9d4de2 1072 * set up the MCG during system boot up.
<> 154:37f96f9d4de2 1073 *
<> 154:37f96f9d4de2 1074 * @param oscsel OSC clock select, OSCSEL.
<> 154:37f96f9d4de2 1075 * @param frdiv FLL reference clock divider setting, FRDIV.
<> 154:37f96f9d4de2 1076 * @param dmx32 DMX32 in FEE mode.
<> 154:37f96f9d4de2 1077 * @param drs The DCO range selection.
<> 154:37f96f9d4de2 1078 * @param fllStableDelay Delay function to ensure that the FLL is stable.
<> 154:37f96f9d4de2 1079 *
<> 154:37f96f9d4de2 1080 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 1081 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 1082 */
<> 154:37f96f9d4de2 1083 status_t CLOCK_BootToFeeMode(
<> 154:37f96f9d4de2 1084 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
<> 154:37f96f9d4de2 1085
<> 154:37f96f9d4de2 1086 /*!
<> 154:37f96f9d4de2 1087 * @brief Sets the MCG to BLPI mode during system boot up.
<> 154:37f96f9d4de2 1088 *
<> 154:37f96f9d4de2 1089 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
<> 154:37f96f9d4de2 1090 * set up the MCG during sytem boot up.
<> 154:37f96f9d4de2 1091 *
<> 154:37f96f9d4de2 1092 * @param fcrdiv Fast IRC divider, FCRDIV.
<> 154:37f96f9d4de2 1093 * @param ircs The internal reference clock to select, IRCS.
<> 154:37f96f9d4de2 1094 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
<> 154:37f96f9d4de2 1095 *
<> 154:37f96f9d4de2 1096 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
<> 154:37f96f9d4de2 1097 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 1098 */
<> 154:37f96f9d4de2 1099 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
<> 154:37f96f9d4de2 1100
<> 154:37f96f9d4de2 1101 /*!
<> 154:37f96f9d4de2 1102 * @brief Sets the MCG to BLPE mode during sytem boot up.
<> 154:37f96f9d4de2 1103 *
<> 154:37f96f9d4de2 1104 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
<> 154:37f96f9d4de2 1105 * set up the MCG during sytem boot up.
<> 154:37f96f9d4de2 1106 *
<> 154:37f96f9d4de2 1107 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
<> 154:37f96f9d4de2 1108 *
<> 154:37f96f9d4de2 1109 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
<> 154:37f96f9d4de2 1110 * @retval kStatus_Success Switched to the target mode successfully.
<> 154:37f96f9d4de2 1111 */
<> 154:37f96f9d4de2 1112 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
<> 154:37f96f9d4de2 1113
<> 154:37f96f9d4de2 1114 /*!
<> 154:37f96f9d4de2 1115 * @brief Sets the MCG to a target mode.
<> 154:37f96f9d4de2 1116 *
<> 154:37f96f9d4de2 1117 * This function sets MCG to a target mode defined by the configuration
<> 154:37f96f9d4de2 1118 * structure. If switching to the target mode fails, this function
<> 154:37f96f9d4de2 1119 * chooses the correct path.
<> 154:37f96f9d4de2 1120 *
<> 154:37f96f9d4de2 1121 * @param config Pointer to the target MCG mode configuration structure.
<> 154:37f96f9d4de2 1122 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
<> 154:37f96f9d4de2 1123 *
<> 154:37f96f9d4de2 1124 * @note If the external clock is used in the target mode, ensure that it is
<> 154:37f96f9d4de2 1125 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
<> 154:37f96f9d4de2 1126 * function.
<> 154:37f96f9d4de2 1127 */
<> 154:37f96f9d4de2 1128 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
<> 154:37f96f9d4de2 1129
<> 154:37f96f9d4de2 1130 /*@}*/
<> 154:37f96f9d4de2 1131
<> 154:37f96f9d4de2 1132 #if defined(__cplusplus)
<> 154:37f96f9d4de2 1133 }
<> 154:37f96f9d4de2 1134 #endif /* __cplusplus */
<> 154:37f96f9d4de2 1135
<> 154:37f96f9d4de2 1136 /*! @} */
<> 154:37f96f9d4de2 1137
<> 154:37f96f9d4de2 1138 #endif /* _FSL_CLOCK_H_ */