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Revision 140:6f18478c63fa, committed 2016-05-24
- Comitter:
- mbed_official
- Date:
- Tue May 24 11:30:12 2016 +0100
- Parent:
- 139:533daf166656
- Child:
- 141:a2b798ec44f6
- Commit message:
- Synchronized with git revision 24136afd3f87e9580dd3d3fcae28e9b9f166af3e
Full URL: https://github.com/mbedmicro/mbed/commit/24136afd3f87e9580dd3d3fcae28e9b9f166af3e/
Fix timer #816 issue for STM32F0 and STM32F1
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/hal_tick.c Mon May 23 16:00:17 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/hal_tick.c Tue May 24 11:30:12 2016 +0100 @@ -43,6 +43,7 @@ extern volatile uint32_t SlaveCounter; extern volatile uint32_t oc_int_part; extern volatile uint16_t oc_rem_part; +extern volatile uint16_t cnt_val; // Used to increment the slave counter void timer_update_irq_handler(void) @@ -59,7 +60,7 @@ // Used for mbed timeout (channel 1) and HAL tick (channel 2) void timer_oc_irq_handler(void) { - uint16_t cval = TIM_MST->CNT; + cnt_val = TIM_MST->CNT; TimMasterHandle.Instance = TIM_MST; // Channel 1 for mbed timeout @@ -71,7 +72,7 @@ } else { if (oc_int_part > 0) { set_compare(0xFFFF); - oc_rem_part = cval; // To finish the counter loop the next time + oc_rem_part = cnt_val; // To finish the counter loop the next time oc_int_part--; } else { us_ticker_irq_handler();
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c Mon May 23 16:00:17 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c Tue May 24 11:30:12 2016 +0100 @@ -43,6 +43,7 @@ extern volatile uint32_t SlaveCounter; extern volatile uint32_t oc_int_part; extern volatile uint16_t oc_rem_part; +extern volatile uint16_t cnt_val; // Used to increment the slave counter void timer_update_irq_handler(void) @@ -59,7 +60,7 @@ // Used for mbed timeout (channel 1) and HAL tick (channel 2) void timer_oc_irq_handler(void) { - uint16_t cval = TIM_MST->CNT; + cnt_val = TIM_MST->CNT; TimMasterHandle.Instance = TIM_MST; // Channel 1 for mbed timeout @@ -71,7 +72,7 @@ } else { if (oc_int_part > 0) { set_compare(0xFFFF); - oc_rem_part = cval; // To finish the counter loop the next time + oc_rem_part = cnt_val; // To finish the counter loop the next time oc_int_part--; } else { us_ticker_irq_handler();
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c Mon May 23 16:00:17 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c Tue May 24 11:30:12 2016 +0100 @@ -43,9 +43,10 @@ extern volatile uint32_t SlaveCounter; extern volatile uint32_t oc_int_part; extern volatile uint16_t oc_rem_part; +extern volatile uint16_t cnt_val; void timer_irq_handler(void) { - uint16_t cval = TIM_MST->CNT; + cnt_val= TIM_MST->CNT; TimMasterHandle.Instance = TIM_MST; @@ -64,7 +65,7 @@ } else { if (oc_int_part > 0) { set_compare(0xFFFF); - oc_rem_part = cval; // To finish the counter loop the next time + oc_rem_part = cnt_val; // To finish the counter loop the next time oc_int_part--; } else { us_ticker_irq_handler();
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c Mon May 23 16:00:17 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c Tue May 24 11:30:12 2016 +0100 @@ -41,6 +41,7 @@ volatile uint32_t SlaveCounter = 0; volatile uint32_t oc_int_part = 0; volatile uint16_t oc_rem_part = 0; +volatile uint16_t cnt_val = 0; void set_compare(uint16_t count) { TimMasterHandle.Instance = TIM_MST; @@ -58,24 +59,15 @@ } uint32_t us_ticker_read() { - uint32_t counter, counter2; + uint32_t counter; if (!us_ticker_inited) us_ticker_init(); - // A situation might appear when Master overflows right after Slave is read and before the - // new (overflowed) value of Master is read. Which would make the code below consider the - // previous (incorrect) value of Slave and the new value of Master, which would return a - // value in the past. Avoid this by computing consecutive values of the timer until they - // are properly ordered. + + //Current value of TIM_MST->CNT is stored in cnt_val and is + //updated in interrupt context counter = (uint32_t)(SlaveCounter << 16); - counter += TIM_MST->CNT; - while (1) { - counter2 = (uint32_t)(SlaveCounter << 16); - counter2 += TIM_MST->CNT; - if (counter2 > counter) { - break; - } - counter = counter2; - } - return counter2; + counter += cnt_val; + + return counter; } void us_ticker_set_interrupt(timestamp_t timestamp) {
--- a/targets/hal/TARGET_STM/TARGET_STM32F1/us_ticker.c Mon May 23 16:00:17 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F1/us_ticker.c Tue May 24 11:30:12 2016 +0100 @@ -38,6 +38,7 @@ volatile uint32_t SlaveCounter = 0; volatile uint32_t oc_int_part = 0; volatile uint16_t oc_rem_part = 0; +volatile uint16_t cnt_val = 0; void set_compare(uint16_t count) { @@ -58,24 +59,15 @@ uint32_t us_ticker_read() { - uint32_t counter, counter2; + uint32_t counter; if (!us_ticker_inited) us_ticker_init(); - // A situation might appear when Master overflows right after Slave is read and before the - // new (overflowed) value of Master is read. Which would make the code below consider the - // previous (incorrect) value of Slave and the new value of Master, which would return a - // value in the past. Avoid this by computing consecutive values of the timer until they - // are properly ordered. + + //Current value of TIM_MST->CNT is stored in cnt_val and is + //updated in interrupt context counter = (uint32_t)(SlaveCounter << 16); - counter += TIM_MST->CNT; - while (1) { - counter2 = (uint32_t)(SlaveCounter << 16); - counter2 += TIM_MST->CNT; - if (counter2 > counter) { - break; - } - counter = counter2; - } - return counter2; + counter += cnt_val; + + return counter; } void us_ticker_set_interrupt(timestamp_t timestamp)