Revision 171:19eb464bc2be, committed 2017-08-03

Comitter:

Kojto

Date:

Thu Aug 03 13:13:39 2017 +0100

Parent:

169:e3b6fe271b81

Child:

172:89b338f31ef1

Commit message:

This updates the lib to the mbed lib v 148

Changed in this revision

--- a/drivers/SPI.cpp	Wed Jul 19 17:31:21 2017 +0100
+++ b/drivers/SPI.cpp	Thu Aug 03 13:13:39 2017 +0100
@@ -32,7 +32,8 @@
 #endif
         _bits(8),
         _mode(0),
-        _hz(1000000) {
+        _hz(1000000),
+        _write_fill(SPI_FILL_CHAR) {
     // No lock needed in the constructor
 
     spi_init(&_spi, mosi, miso, sclk, ssel);
@@ -102,7 +103,7 @@
 int SPI::write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
     lock();
     _acquire();
-    int ret = spi_master_block_write(&_spi, tx_buffer, tx_length, rx_buffer, rx_length);
+    int ret = spi_master_block_write(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, _write_fill);
     unlock();
     return ret;
 }
@@ -115,6 +116,12 @@
     _mutex->unlock();
 }
 
+void SPI::set_default_write_value(char data) {
+    lock();
+    _write_fill = data;
+    unlock();
+}
+
 #if DEVICE_SPI_ASYNCH
 
 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)

--- a/drivers/SPI.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/drivers/SPI.h	Thu Aug 03 13:13:39 2017 +0100
@@ -143,6 +143,15 @@
      */
     virtual void unlock(void);
 
+    /** Set default write data
+      * SPI requires the master to send some data during a read operation.
+      * Different devices may require different default byte values.
+      * For example: A SD Card requires default bytes to be 0xFF.
+      *
+      * @param data    Default character to be transmitted while read operation
+      */
+    void set_default_write_value(char data);
+
 #if DEVICE_SPI_ASYNCH
 
     /** Start non-blocking SPI transfer using 8bit buffers.
@@ -271,6 +280,7 @@
     int _bits;
     int _mode;
     int _hz;
+    char _write_fill;
 
 private:
     /* Private acquire function without locking/unlocking

--- a/drivers/UARTSerial.cpp	Wed Jul 19 17:31:21 2017 +0100
+++ b/drivers/UARTSerial.cpp	Thu Aug 03 13:13:39 2017 +0100
@@ -43,6 +43,11 @@
     wake();
 }
 
+void UARTSerial::set_baud(int baud)
+{
+    SerialBase::baud(baud);
+}
+
 void UARTSerial::set_data_carrier_detect(PinName dcd_pin, bool active_high)
 {
      delete _dcd_irq;

--- a/drivers/UARTSerial.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/drivers/UARTSerial.h	Thu Aug 03 13:13:39 2017 +0100
@@ -152,6 +152,12 @@
      */
     void set_data_carrier_detect(PinName dcd_pin, bool active_high = false);
 
+    /** Set the baud rate
+     *
+     *  @param baud   The baud rate
+     */
+    void set_baud(int baud);
+
 private:
 
     /** SerialBase lock override */

--- a/hal/spi_api.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/hal/spi_api.h	Thu Aug 03 13:13:39 2017 +0100
@@ -33,6 +33,7 @@
 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
 
 #define SPI_FILL_WORD         (0xFFFF)
+#define SPI_FILL_CHAR         (0xFF)
 
 #if DEVICE_SPI_ASYNCH
 /** Asynch SPI HAL structure
@@ -122,16 +123,17 @@
  *  tx_length and rx_length. The bytes written will be padded with the
  *  value 0xff.
  *
- * @param[in] obj       The SPI peripheral to use for sending
- * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
- * @param[in] tx_length Number of bytes to write, may be zero
- * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
- * @param[in] rx_length Number of bytes to read, may be zero
+ * @param[in] obj        The SPI peripheral to use for sending
+ * @param[in] tx_buffer  Pointer to the byte-array of data to write to the device
+ * @param[in] tx_length  Number of bytes to write, may be zero
+ * @param[in] rx_buffer  Pointer to the byte-array of data to read from the device
+ * @param[in] rx_length  Number of bytes to read, may be zero
+ * @param[in] write_fill Default data transmitted while performing a read
  * @returns
  *      The number of bytes written and read from the device. This is
  *      maximum of tx_length and rx_length.
  */
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length);
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
 
 /** Check if a value is available to read
  *

--- a/mbed.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/mbed.h	Thu Aug 03 13:13:39 2017 +0100
@@ -16,13 +16,13 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 147
+#define MBED_LIBRARY_VERSION 148
 
 #if MBED_CONF_RTOS_PRESENT
 // RTOS present, this is valid only for mbed OS 5
 #define MBED_MAJOR_VERSION 5
 #define MBED_MINOR_VERSION 5
-#define MBED_PATCH_VERSION 3
+#define MBED_PATCH_VERSION 4
 
 #else
 // mbed 2

--- a/platform/ATCmdParser.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/platform/ATCmdParser.h	Thu Aug 03 13:13:39 2017 +0100
@@ -29,7 +29,8 @@
  *
  * Here are some examples:
  * @code
- * ATCmdParser at = ATCmdParser(serial, "\r\n");
+ * UARTSerial serial = UARTSerial(D1, D0);
+ * ATCmdParser at = ATCmdParser(&serial, "\r\n");
  * int value;
  * char buffer[100];
  *

--- a/platform/mbed_application.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/platform/mbed_application.h	Thu Aug 03 13:13:39 2017 +0100
@@ -21,7 +21,12 @@
 
 #include<stdint.h>
 
-#define MBED_APPLICATION_SUPPORT defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7)
+#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7)
+#define MBED_APPLICATION_SUPPORT 1
+#else
+#define MBED_APPLICATION_SUPPORT 0
+#endif
+
 #if MBED_APPLICATION_SUPPORT
 #ifdef __cplusplus
 extern "C" {

--- a/platform/mbed_critical.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/platform/mbed_critical.c	Thu Aug 03 13:13:39 2017 +0100
@@ -23,7 +23,11 @@
 #include "platform/mbed_assert.h"
 #include "platform/mbed_toolchain.h"
 
-#define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
+#if !defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS)
+#define EXCLUSIVE_ACCESS 1
+#else
+#define EXCLUSIVE_ACCESS 0
+#endif
 
 static volatile uint32_t interrupt_enable_counter = 0;
 static volatile bool critical_interrupts_disabled = false;

--- a/platform/mbed_stats.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/platform/mbed_stats.h	Thu Aug 03 13:13:39 2017 +0100
@@ -42,22 +42,22 @@
 void mbed_stats_heap_get(mbed_stats_heap_t *stats);
 
 typedef struct {
-    uint32_t thread_id;         /**< Identifier for thread that owns the stack. */
-    uint32_t max_size;          /**< Sum of the maximum number of bytes used in each stack. */
-    uint32_t reserved_size;     /**< Current number of bytes allocated for all stacks. */
-    uint32_t stack_cnt;         /**< Number of stacks currently allocated. */
+    uint32_t thread_id;         /**< Identifier for thread that owns the stack or 0 if multiple threads. */
+    uint32_t max_size;          /**< Maximum number of bytes used on the stack. */
+    uint32_t reserved_size;     /**< Current number of bytes allocated for the stack. */
+    uint32_t stack_cnt;         /**< Number of stacks stats accumulated in the structure. */
 } mbed_stats_stack_t;
 
 /**
- *  Fill the passed in structure with stack stats.
+ *  Fill the passed in structure with stack stats accumulated for all threads. The thread_id will be 0
+ *  and stack_cnt will represent number of threads.
  *
  *  @param stats    A pointer to the mbed_stats_stack_t structure to fill
  */
 void mbed_stats_stack_get(mbed_stats_stack_t *stats);
 
 /**
- *  Fill the passed array of stat structures with the stack stats
- *  for each available stack.
+ *  Fill the passed array of stat structures with the stack stats for each available thread.
  *
  *  @param stats    A pointer to an array of mbed_stats_stack_t structures to fill
  *  @param count    The number of mbed_stats_stack_t structures in the provided array

--- a/platform/mbed_toolchain.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/platform/mbed_toolchain.h	Thu Aug 03 13:13:39 2017 +0100
@@ -94,9 +94,15 @@
 
 /** MBED_WEAK
  *  Mark a function as being weak.
+ *
+ *  @note
+ *  Functions should only be marked as weak in the source file. The header file
+ *  should contain a regular function declaration to insure the function is emitted.
+ *  A function marked weak will not be emitted if an alternative non-weak
+ *  implementation is defined.
  *  
  *  @note
- *  weak functions are not friendly to making code re-usable, as they can only
+ *  Weak functions are not friendly to making code re-usable, as they can only
  *  be overridden once (and if they are multiply overridden the linker will emit
  *  no warning). You should not normally use weak symbols as part of the API to
  *  re-usable modules.

--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -262,11 +262,12 @@
     return data;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -256,13 +256,13 @@
 }
 
 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
-                           char *rx_buffer, int rx_length)
+                           char *rx_buffer, int rx_length, char write_fill)
 {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
     char out, in;
 
     for (int i = 0; i < total; i++) {
-        out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        out = (i < tx_length) ? tx_buffer[i] : write_fill;
         in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -268,11 +268,12 @@
     return (ssp_read(obj));
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -268,11 +268,12 @@
     return (ssp_read(obj));
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -555,11 +555,12 @@
     return rx_data;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -296,11 +296,12 @@
     return 0;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char _write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : _write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_K20XX/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_K20XX/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -140,11 +140,12 @@
     return obj->spi->POPR;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -141,11 +141,12 @@
     return obj->spi->D & 0xff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -120,11 +120,12 @@
     return obj->spi->D & 0xff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -199,11 +199,12 @@
     return ret;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -199,11 +199,12 @@
     return ret;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -118,11 +118,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -118,11 +118,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -115,11 +115,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -115,11 +115,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -117,11 +117,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -117,11 +117,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -117,11 +117,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -117,11 +117,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -127,11 +127,12 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -127,17 +127,17 @@
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
-    DSPI_MasterTransferBlocking(spi_address[obj->spi.instance], &(dspi_transfer_t){
-        .txData = (uint8_t *)tx_buffer,
-        .rxData = (uint8_t *)rx_buffer,
-        .dataSize = total,
-        .configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
-    });
-
-    DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
+    for (int i = 0; i < total; i++) {
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+        char in = spi_master_write(obj, out);
+        if (i < rx_length) {
+            rx_buffer[i] = in;
+        }
+    }
 
     return total;
 }

--- a/targets/TARGET_Maxim/TARGET_MAX32600/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -179,11 +179,12 @@
     return result;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Maxim/TARGET_MAX32610/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -179,11 +179,12 @@
     return result;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -231,11 +231,12 @@
     return spi_master_transaction(obj, value, MXC_S_SPI_FIFO_DIR_BOTH);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -167,11 +167,12 @@
     return *req.rx_data;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -100,26 +100,26 @@
 };
 
 const PinMap PinMap_UART_CTS[] = {
-    { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
-    { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
-    { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
-    { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
-    { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
-    { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
-    { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
-    { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
+    { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
+    { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
+    { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
+    { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
+    { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
+    { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
+    { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
+    { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
     { NC,   NC,     0 }
 };
 
 const PinMap PinMap_UART_RTS[] = {
-    { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
-    { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
-    { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
-    { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
-    { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
-    { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
-    { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
-    { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
+    { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
+    { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
+    { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
+    { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_A << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
+    { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
+    { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
+    { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
+    { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)(IOMAN_MAP_B << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS) | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
     { NC,   NC,     0 }
 };
 

--- a/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -180,6 +180,10 @@
 //******************************************************************************
 void uart_handler(serial_t *obj)
 {
+    // clear interrupts
+    volatile uint32_t flags = obj->uart->intfl;
+    obj->uart->intfl = flags;
+
     if (obj && obj->id) {
         irq_handler(obj->id, RxIrq);
     }
@@ -200,6 +204,9 @@
 //******************************************************************************
 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
 {
+    MBED_ASSERT(obj->index < MXC_CFG_UART_INSTANCES);
+    objs[obj->index] = obj;
+
     switch (obj->index) {
         case 0:
             NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);

--- a/targets/TARGET_Maxim/TARGET_MAX32630/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -167,11 +167,12 @@
     return *req.rx_data;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -263,11 +263,12 @@
     return spi_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_VBLUNO52/PinNames.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,253 @@
+/* 
+ * Copyright (c) 2017 VNG IoT Lab, Vietnam
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/*
+ * PinNames for the VBLUno52 board
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+typedef enum {
+    p0  = 0,
+    p1  = 1,
+    p2  = 2,
+    p3  = 3,
+    p4  = 4,
+    p5  = 5,
+    p6  = 6,
+    p7  = 7,
+    p8  = 8,
+    p9  = 9,
+    p10 = 10,
+    p11 = 11,
+    p12 = 12,
+    p13 = 13,
+    p14 = 14,
+    p15 = 15,
+    p16 = 16,
+    p17 = 17,
+    p18 = 18,
+    p19 = 19,
+    p20 = 20,
+    p21 = 21,
+    p22 = 22,
+    p23 = 23,
+    p24 = 24,
+    p25 = 25,
+    p26 = 26,
+    p27 = 27,
+    p28 = 28,
+    p29 = 29,
+    p30 = 30,
+    p31 = 31,
+
+    P0_0  = p0,
+    P0_1  = p1,
+    P0_2  = p2,
+    P0_3  = p3,
+    P0_4  = p4,
+    P0_5  = p5,
+    P0_6  = p6,
+    P0_7  = p7,
+
+    P0_8  = p8,
+    P0_9  = p9,
+    P0_10 = p10,
+    P0_11 = p11,
+    P0_12 = p12,
+    P0_13 = p13,
+    P0_14 = p14,
+    P0_15 = p15,
+
+    P0_16 = p16,
+    P0_17 = p17,
+    P0_18 = p18,
+    P0_19 = p19,
+    P0_20 = p20,
+    P0_21 = p21,
+    P0_22 = p22,
+    P0_23 = p23,
+
+    P0_24 = p24,
+    P0_25 = p25,
+    P0_26 = p26,
+    P0_27 = p27,
+    P0_28 = p28,
+    P0_29 = p29,
+    P0_30 = p30,
+    P0_31 = p31,
+    
+    //only for mbed test suite
+    LED1    = p12,
+    LED2    = p18,
+    LED3    = p19,
+    LED4    = p20,
+
+    //only for mbed test suite
+    BUTTON1 = p17,
+    BUTTON2 = p3,
+    BUTTON3 = p4,
+    BUTTON4 = p28,
+
+    RX_PIN_NUMBER  = p8,
+    TX_PIN_NUMBER  = p6,
+    CTS_PIN_NUMBER = p7,          //not on Header
+    RTS_PIN_NUMBER = p5,          //not on Header
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    SPI_PSELMOSI0 = p13,
+    SPI_PSELMISO0 = p14,
+    SPI_PSELSS0   = p11,
+    SPI_PSELSCK0  = p15,
+
+    SPI_PSELMOSI1 = p13,
+    SPI_PSELMISO1 = p14,
+    SPI_PSELSS1   = p11,
+    SPI_PSELSCK1  = p15,
+
+    SPIS_PSELMOSI = p13,
+    SPIS_PSELMISO = p14,
+    SPIS_PSELSS   = p11,
+    SPIS_PSELSCK  = p15,
+
+    I2C_SDA = p26,
+    I2C_SCL = p27,
+    
+    I2C_SDA0 = p26,
+    I2C_SCL0 = p27,
+    
+    I2C_SDA1 = p30,
+    I2C_SCL1 = p31,
+    
+    RESET = p21,
+    
+    NFC1 = p9,
+    NFC2 = p10,
+    
+    //Adruino interface pins
+    D0 = p8,
+    D1 = p6,
+    D2 = p24,
+    D3 = p23,
+    D4 = p22,
+    D5 = p18,
+    D6 = p19,
+    D7 = p20,
+
+    D8 = p9,
+    D9 = p10,
+    D10 = p11,
+    D11 = p13,
+    D12 = p14,
+    D13 = p15,
+
+    D14 = p3,
+    D15 = p4,
+    D16 = p28,
+    D17 = p29,
+    D18 = p30,
+    D19 = p31,
+    
+    D20 = p26,
+    D21 = p27,
+    
+    D22 = p12,
+    D23 = p17,
+    
+    D24 = p5,
+    D25 = p7,
+    
+    A0 = D14,
+    A1 = D15,
+    A2 = D16,
+    A3 = D17,
+    A4 = D18,
+    A5 = D19,
+    
+    SS = D10,
+    MOSI = D11,
+    MISO = D12,
+    SCK  = D13,
+
+    SDA0 = D20,
+    SCL0 = D21,
+    SDA1 = D18,
+    SCL1 = D19,
+    SDA = SDA0,
+    SCL = SCL0,
+
+    RX = D0,
+    TX = D1,
+    RTS = D24,                    //not on Header
+    CTS = D25,                    //not on Header
+
+    LED = D22,                    //not on Header
+    BUT = D23,                    //not on Header
+        
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_VBLUNO52/device.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,23 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#include "objects.h"
+
+#endif

--- a/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -487,11 +487,12 @@
     return p_spi_info->rx_buf;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -241,11 +241,12 @@
     return value2;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -244,11 +244,12 @@
     return value2;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -190,11 +190,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,17 +0,0 @@
-
-LR_IROM1 0x00000000 0xC000  {    ; load region size_region (48k)
-  ER_IROM1 0x00000000 0xC000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-  ; 8KB - 0xC0 = 0x1F40
-  RW_IRAM1 0x100000C0 0x1F40  {
-   .ANY (+RW +ZI)
-  }
-  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
-   .ANY (USBRAM)
-  }
-}
-

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.S	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,325 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC11xx.s
-; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
-; *           for the NXP LPC11xx Device Series 
-; * @version: V1.0
-; * @date:    25. Nov. 2008
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2008 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-
-Stack_Mem       SPACE   Stack_Size
-__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
-
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-				; for LPC11Uxx (With USB)
-                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
-                DCD     FLEX_INT1_IRQHandler          
-                DCD     FLEX_INT2_IRQHandler                       
-                DCD     FLEX_INT3_IRQHandler                         
-                DCD     FLEX_INT4_IRQHandler                        
-                DCD     FLEX_INT5_IRQHandler
-                DCD     FLEX_INT6_IRQHandler
-                DCD     FLEX_INT7_IRQHandler                       
-                DCD     GINT0_IRQHandler                         
-                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
-                DCD     Reserved_IRQHandler	      ; Reserved
-                DCD     Reserved_IRQHandler
-                DCD     Reserved_IRQHandler       
-                DCD     Reserved_IRQHandler                       
-                DCD     SSP1_IRQHandler           ; SSP1               
-                DCD     I2C_IRQHandler            ; I2C
-                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
-                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
-                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
-                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
-                DCD     SSP0_IRQHandler           ; SSP0
-                DCD     UART_IRQHandler           ; UART
-                DCD     USB_IRQHandler            ; USB IRQ
-                DCD     USB_FIQHandler            ; USB FIQ
-                DCD     ADC_IRQHandler            ; A/D Converter
-                DCD     WDT_IRQHandler            ; Watchdog timer
-                DCD     BOD_IRQHandler            ; Brown Out Detect
-                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
-                DCD     Reserved_IRQHandler	    ; Reserved
-                DCD     Reserved_IRQHandler       ; Reserved
-                DCD     USBWakeup_IRQHandler      ; USB wake up
-                DCD     Reserved_IRQHandler       ; Reserved
-	
-	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
-                
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-	
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-	
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
-; for particular peripheral.
-;NMI_Handler     PROC
-;                EXPORT  NMI_Handler               [WEAK]
-;                B       .
-;                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-Reserved_IRQHandler PROC
-                EXPORT  Reserved_IRQHandler       [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-; for LPC11Uxx (With USB)
-                EXPORT  NMI_Handler               [WEAK]
-                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
-                EXPORT  GINT0_IRQHandler          [WEAK]
-                EXPORT  GINT1_IRQHandler          [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  TIMER16_0_IRQHandler      [WEAK]
-                EXPORT  TIMER16_1_IRQHandler      [WEAK]
-                EXPORT  TIMER32_0_IRQHandler      [WEAK]
-                EXPORT  TIMER32_1_IRQHandler      [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  UART_IRQHandler           [WEAK]
-
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  USB_FIQHandler            [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  FMC_IRQHandler            [WEAK]
-                EXPORT	USBWakeup_IRQHandler      [WEAK]
-
-NMI_Handler
-FLEX_INT0_IRQHandler
-FLEX_INT1_IRQHandler
-FLEX_INT2_IRQHandler
-FLEX_INT3_IRQHandler
-FLEX_INT4_IRQHandler
-FLEX_INT5_IRQHandler
-FLEX_INT6_IRQHandler
-FLEX_INT7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-SSP1_IRQHandler
-I2C_IRQHandler
-TIMER16_0_IRQHandler
-TIMER16_1_IRQHandler
-TIMER32_0_IRQHandler
-TIMER32_1_IRQHandler
-SSP0_IRQHandler
-UART_IRQHandler
-USB_IRQHandler
-USB_FIQHandler
-ADC_IRQHandler
-WDT_IRQHandler
-BOD_IRQHandler
-FMC_IRQHandler
-USBWakeup_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,17 +0,0 @@
-
-LR_IROM1 0x00000000 0xC000  {    ; load region size_region (48k)
-  ER_IROM1 0x00000000 0xC000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-  ; 8KB - 0xC0 = 0x1F40
-  RW_IRAM1 0x100000C0 0x1F40  {
-   .ANY (+RW +ZI)
-  }
-  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
-   .ANY (USBRAM)
-  }
-}
-

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.S	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,308 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC11xx.s
-; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
-; *           for the NXP LPC11xx Device Series 
-; * @version: V1.0
-; * @date:    25. Nov. 2008
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2008 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-				; for LPC11Uxx (With USB)
-                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
-                DCD     FLEX_INT1_IRQHandler          
-                DCD     FLEX_INT2_IRQHandler                       
-                DCD     FLEX_INT3_IRQHandler                         
-                DCD     FLEX_INT4_IRQHandler                        
-                DCD     FLEX_INT5_IRQHandler
-                DCD     FLEX_INT6_IRQHandler
-                DCD     FLEX_INT7_IRQHandler                       
-                DCD     GINT0_IRQHandler                         
-                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
-                DCD     Reserved_IRQHandler	      ; Reserved
-                DCD     Reserved_IRQHandler
-                DCD     Reserved_IRQHandler       
-                DCD     Reserved_IRQHandler                       
-                DCD     SSP1_IRQHandler           ; SSP1               
-                DCD     I2C_IRQHandler            ; I2C
-                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
-                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
-                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
-                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
-                DCD     SSP0_IRQHandler           ; SSP0
-                DCD     UART_IRQHandler           ; UART
-                DCD     USB_IRQHandler            ; USB IRQ
-                DCD     USB_FIQHandler            ; USB FIQ
-                DCD     ADC_IRQHandler            ; A/D Converter
-                DCD     WDT_IRQHandler            ; Watchdog timer
-                DCD     BOD_IRQHandler            ; Brown Out Detect
-                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
-                DCD     Reserved_IRQHandler	    ; Reserved
-                DCD     Reserved_IRQHandler       ; Reserved
-                DCD     USBWakeup_IRQHandler      ; USB wake up
-                DCD     Reserved_IRQHandler       ; Reserved
-	
-	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
-                
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-	
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-	
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
-; for particular peripheral.
-;NMI_Handler     PROC
-;                EXPORT  NMI_Handler               [WEAK]
-;                B       .
-;                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-Reserved_IRQHandler PROC
-                EXPORT  Reserved_IRQHandler       [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-; for LPC11Uxx (With USB)
-                EXPORT  NMI_Handler               [WEAK]
-                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
-                EXPORT  GINT0_IRQHandler          [WEAK]
-                EXPORT  GINT1_IRQHandler          [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  TIMER16_0_IRQHandler      [WEAK]
-                EXPORT  TIMER16_1_IRQHandler      [WEAK]
-                EXPORT  TIMER32_0_IRQHandler      [WEAK]
-                EXPORT  TIMER32_1_IRQHandler      [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  UART_IRQHandler           [WEAK]
-
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  USB_FIQHandler            [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  FMC_IRQHandler            [WEAK]
-                EXPORT	USBWakeup_IRQHandler      [WEAK]
-
-NMI_Handler
-FLEX_INT0_IRQHandler
-FLEX_INT1_IRQHandler
-FLEX_INT2_IRQHandler
-FLEX_INT3_IRQHandler
-FLEX_INT4_IRQHandler
-FLEX_INT5_IRQHandler
-FLEX_INT6_IRQHandler
-FLEX_INT7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-SSP1_IRQHandler
-I2C_IRQHandler
-TIMER16_0_IRQHandler
-TIMER16_1_IRQHandler
-TIMER32_0_IRQHandler
-TIMER32_1_IRQHandler
-SSP0_IRQHandler
-UART_IRQHandler
-USB_IRQHandler
-USB_FIQHandler
-ADC_IRQHandler
-WDT_IRQHandler
-BOD_IRQHandler
-FMC_IRQHandler
-USBWakeup_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,151 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
-  RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
-  USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- * 
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text.Reset_Handler)
-        
-        /* Only vectors and code running at reset are safe to be in first 512
-           bytes since RAM can be mapped into this area for RAM based interrupt
-           vectors. */
-        . = 0x00000200;
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-        
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE (__fini_array_end = .);
-
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-
-    } > RAM
-
-    .bss :
-    {
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > RAM
-    
-    .heap :
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy :
-    {
-        *(.stack)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -156,11 +156,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -192,11 +192,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC13XX/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC13XX/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -184,11 +184,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC15XX/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC15XX/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -248,11 +248,12 @@
     return spi_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer,
+                           int tx_length, char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -190,11 +190,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -197,11 +197,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -177,11 +177,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -196,11 +196,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC81X/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC81X/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -178,11 +178,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_NXP/TARGET_LPC82X/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC82X/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -174,11 +174,12 @@
     return spi_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralNames.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+    UART_0 = Flexcomm0,
+    UART_1 = Flexcomm2
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+typedef enum {
+    I2C_0 = Flexcomm1,
+    I2C_1 = Flexcomm4
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // FTM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // FTM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // FTM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // FTM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // FTM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // FTM0 CH5
+    PWM_7  = (0 << TPM_SHIFT) | (6),  // FTM0 CH6
+    PWM_8  = (0 << TPM_SHIFT) | (7),  // FTM0 CH7
+    PWM_9  = (1 << TPM_SHIFT) | (0),  // FTM1 CH0
+    PWM_10 = (1 << TPM_SHIFT) | (1),  // FTM1 CH1
+    PWM_11 = (1 << TPM_SHIFT) | (2),  // FTM1 CH2
+    PWM_12 = (1 << TPM_SHIFT) | (3),  // FTM1 CH3
+    PWM_13 = (1 << TPM_SHIFT) | (4),  // FTM1 CH4
+    PWM_14 = (1 << TPM_SHIFT) | (5),  // FTM1 CH5
+    PWM_15 = (1 << TPM_SHIFT) | (6),  // FTM1 CH6
+    PWM_16 = (1 << TPM_SHIFT) | (7),  // FTM1 CH7
+    PWM_17 = (2 << TPM_SHIFT) | (0),  // FTM2 CH0
+    PWM_18 = (2 << TPM_SHIFT) | (1),  // FTM2 CH1
+    PWM_19 = (2 << TPM_SHIFT) | (2),  // FTM2 CH2
+    PWM_20 = (2 << TPM_SHIFT) | (3),  // FTM2 CH3
+    PWM_21 = (2 << TPM_SHIFT) | (4),  // FTM2 CH4
+    PWM_22 = (2 << TPM_SHIFT) | (5),  // FTM2 CH5
+    PWM_23 = (2 << TPM_SHIFT) | (6),  // FTM2 CH6
+    PWM_24 = (2 << TPM_SHIFT) | (7),  // FTM2 CH7
+    PWM_25 = (3 << TPM_SHIFT) | (0),  // FTM3 CH0
+    PWM_26 = (3 << TPM_SHIFT) | (1),  // FTM3 CH1
+    PWM_27 = (3 << TPM_SHIFT) | (2),  // FTM3 CH2
+    PWM_28 = (3 << TPM_SHIFT) | (3),  // FTM3 CH3
+    PWM_29 = (3 << TPM_SHIFT) | (4),  // FTM3 CH4
+    PWM_30 = (3 << TPM_SHIFT) | (5),  // FTM3 CH5
+    PWM_31 = (3 << TPM_SHIFT) | (6),  // FTM3 CH6
+    PWM_32 = (3 << TPM_SHIFT) | (7),  // FTM3 CH7
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT           8
+#define ADC_B_CHANNEL_SHIFT        5
+typedef enum {
+    ADC0_SE0  = 0,
+    ADC0_SE1  = 1,
+    ADC0_SE2  = 2,
+    ADC0_SE3  = 3,
+    ADC0_SE4  = 4,
+    ADC0_SE5  = 5,
+    ADC0_SE6  = 6,
+    ADC0_SE7  = 7,
+    ADC0_SE8  = 8,
+    ADC0_SE9  = 9,
+    ADC0_SE10 = 10,
+    ADC0_SE11 = 11,
+} ADCName;
+
+
+typedef enum {
+    SPI_0 = Flexcomm3,
+    SPI_1 = Flexcomm5
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P0_30, ADC0_SE1,  0},
+    {P1_4,  ADC0_SE7,  0},
+    {P1_5,  ADC0_SE8,  0},
+    {P1_8,  ADC0_SE11, 0},
+    {NC   , NC      ,  0}
+};
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+    {NC      , NC   , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_24, I2C_0, 1},
+    {P0_26, I2C_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_23, I2C_0, 1},
+    {P0_25, I2C_1, 1},
+    {NC   , NC   , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_1, UART_0, 1},
+    {P0_9, UART_1, 1},
+    {NC  ,  NC    , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_0, UART_0, 1},
+    {P0_8, UART_1, 1},
+    {NC  ,  NC   , 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {NC   , NC    , 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {NC   , NC    , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P0_11, SPI_0, 1},
+    {P0_19, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P0_12, SPI_0, 1},
+    {P0_20, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P0_13, SPI_0, 1},
+    {P0_18, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_14, SPI_0, 1},
+    {P1_1,  SPI_1, 4},
+    {P1_2,  SPI_1, 4},
+    {NC  ,  NC   , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {NC   , NC    , 0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PinNames.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,146 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    P0_0 = 0,
+    P0_1 = 1,
+    P0_2 = 2,
+    P0_3 = 3,
+    P0_4 = 4,
+    P0_5 = 5,
+    P0_6 = 6,
+    P0_7 = 7,
+    P0_8 = 8,
+    P0_9 = 9,
+    P0_10 = 10,
+    P0_11 = 11,
+    P0_12 = 12,
+    P0_13 = 13,
+    P0_14 = 14,
+    P0_15 = 15,
+    P0_16 = 16,
+    P0_17 = 17,
+    P0_18 = 18,
+    P0_19 = 19,
+    P0_20 = 20,
+    P0_21 = 21,
+    P0_22 = 22,
+    P0_23 = 23,
+    P0_24 = 24,
+    P0_25 = 25,
+    P0_26 = 26,
+    P0_29 = 29,
+    P0_30 = 30,
+    P0_31 = 31,
+
+    P1_0 = 32,
+    P1_1 = 33,
+    P1_2 = 34,
+    P1_3 = 35,
+    P1_4 = 36,
+    P1_5 = 37,
+    P1_6 = 38,
+    P1_7 = 39,
+    P1_8 = 40,
+    P1_9 = 41,
+    P1_10 = 42,
+    P1_11 = 43,
+    P1_12 = 44,
+    P1_13 = 45,
+    P1_14 = 46,
+    P1_15 = 47,
+    P1_16 = 48,
+    P1_17 = 49,
+
+    LED_RED   = P0_29,
+    LED_GREEN = P1_10,
+    LED_BLUE  = P1_9,
+
+    // mbed original LED naming
+    LED1 = LED_RED,
+    LED2 = LED_GREEN,
+    LED3 = LED_BLUE,
+    LED4 = LED_RED,
+
+    //Push buttons
+    SW1 = P0_24,
+    SW2 = P0_31,
+    SW3 = P0_4,
+
+    // USB Pins
+    USBTX = P0_1,
+    USBRX = P0_0,
+
+    // Arduino Headers
+    D0 = P0_8,
+    D1 = P0_9,
+    D2 = P0_10,
+    D3 = P1_12,
+    D4 = P1_13,
+    D5 = P0_29,
+    D6 = P1_0,
+    D7 = P1_14,
+    D8 = P1_16,
+    D9 = P1_15,
+    D10 = P1_1,
+    D11 = P0_20,
+    D12 = P0_18,
+    D13 = P0_19,
+    D14 = P0_26,
+    D15 = P0_25,
+
+    I2C_SCL = D15,
+    I2C_SDA = D14,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+
+    A0 = P0_30,
+    A1 = NC,
+    A2 = P1_8,
+    A3 = P1_10,
+    A4 = P1_4,
+    A5 = P1_5
+} PinName;
+
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp   = 2,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/clock_config.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: LPC54114J256
+package_id: LPC54114J256BD64
+mcu_data: ksdk2_0
+processor_version: 1.1.0
+board: LPCXpresso54114
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);                   /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                  /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                                                being below the voltage for current speed */
+    CLOCK_SetupFROClocking(12000000U);                    /*!< Set up FRO to the 12 MHz, just for sure */
+    POWER_SetVoltageForFreq(12000000U);             /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);   /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);                  /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                  /*!< Switch MAIN_CLK to FRO12M */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);                   /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                  /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                                                being below the voltage for current speed */
+    POWER_SetVoltageForFreq(48000000U);             /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(48000000U);   /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(48000000U);              /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);                  /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                  /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);                   /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                  /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                                                being below the voltage for current speed */
+    POWER_SetVoltageForFreq(96000000U);             /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);   /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(96000000U);              /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);                  /*!< Set AHBCLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                  /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/clock_config.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+#define BOARD_BootClockRUN BOARD_BootClockFROHF48M
+
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK             12000000U  /*!< Core clock frequency: 12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK            96000000U  /*!< Core clock frequency: 96000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/device.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,43 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#if defined(TARGET_LPC54114_M4)
+#define NUMBER_OF_GPIO_INTS    8
+#elif defined(TARGET_LPC54114_M0)
+#define NUMBER_OF_GPIO_INTS    4
+#endif
+
+#define APP_EXCLUDE_FROM_DEEPSLEEP                                                                        \
+    (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK |  SYSCON_PDRUNCFG_PDEN_SRAMX_MASK |                               \
+     SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_MASK | SYSCON_PDRUNCFG_PDEN_SRAM2_MASK)
+
+/* Defines used by the sleep code */
+#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M
+#define LPC_CLOCK_RUN          BOARD_BootClockFROHF48M
+
+#define DEVICE_ID_LENGTH       24
+
+
+
+
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "clock_config.h"
+#include "fsl_power.h"
+
+// called before main
+void mbed_sdk_init()
+{
+    BOARD_BootClockFROHF48M();
+}
+
+// Change the NMI pin to an input. This allows NMI pin to
+//  be used as a low power mode wakeup.  The application will
+//  need to change the pin back to NMI_b or wakeup only occurs once!
+void NMI_Handler(void)
+{
+    //gpio_t gpio;
+    //gpio_init_in(&gpio, PTA4);
+}
+
+void ADC_ClockPower_Configuration(void)
+{
+    /* SYSCON power. */
+    POWER_DisablePD(kPDRUNCFG_PD_ADC0);     /* Power on the ADC converter. */
+    POWER_DisablePD(kPDRUNCFG_PD_VD7_ENA);  /* Power on the analog power supply. */
+    POWER_DisablePD(kPDRUNCFG_PD_VREFP_SW); /* Power on the reference voltage source. */
+    POWER_DisablePD(kPDRUNCFG_PD_TEMPS);    /* Power on the temperature sensor. */
+
+    /* Enable the clock. */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+    CLOCK_EnableClock(kCLOCK_Adc0);
+}
+
+// Enable the RTC oscillator if available on the board
+void rtc_setup_oscillator(void)
+{
+    /* Enable the RTC 32K Oscillator */
+    SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/LPC54114_cm4.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,6429 @@
+/*
+** ###################################################################
+**     Processors:          LPC54114J256BD64_cm4
+**                          LPC54114J256UK49_cm4
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    LPC5411x User manual Rev. 1.1 25 May 2016
+**     Version:             rev. 1.0, 2016-04-29
+**     Build:               b160922
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPC54114_cm4
+**
+**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-04-29)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54114_cm4.h
+ * @version 1.0
+ * @date 2016-04-29
+ * @brief CMSIS Peripheral Access Layer for LPC54114_cm4
+ *
+ * CMSIS Peripheral Access Layer for LPC54114_cm4
+ */
+
+#ifndef _LPC54114_CM4_H_
+#define _LPC54114_CM4_H_                         /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 56                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
+  DMA0_IRQn                    = 1,                /**< DMA controller */
+  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
+  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
+  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C) */
+  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C) */
+  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C) */
+  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */
+  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */
+  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
+  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
+  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
+  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
+  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
+  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
+  USB0_IRQn                    = 28,               /**< USB device */
+  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
+  IOH_IRQn                     = 30,               /**< IOH */
+  MAILBOX_IRQn                 = 31,               /**< Mailbox interrupt (present on selected devices) */
+  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
+  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
+  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
+  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
+  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
+  Reserved54_IRQn              = 38,               /**< Reserved interrupt */
+  SPIFI0_IRQn                  = 39                /**< SPI flash interface */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_LPC54114_cm4.h"       /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
+  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
+#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
+#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK                      (0x600U)
+#define ADC_CTRL_RESOL_SHIFT                     (9U)
+#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
+#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT                     (12U)
+#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+#define ADC_INSEL_SEL_MASK                       (0x3U)
+#define ADC_INSEL_SEL_SHIFT                      (0U)
+#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
+#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
+#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
+#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
+#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
+#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
+#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
+#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
+#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
+#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
+#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT                       (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
+#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
+#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
+#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
+#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
+#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
+#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT                       (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT                     (4U)
+#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
+#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
+#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT                    (26U)
+#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT                    (30U)
+#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT                  (31U)
+#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT                            (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
+#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
+#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
+#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
+#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
+#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
+#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
+#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
+#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
+#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
+#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
+#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
+#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
+#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
+#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
+#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
+#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
+#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
+#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
+#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
+#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
+#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
+#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
+#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
+#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
+#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
+#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
+#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
+#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
+#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
+#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
+#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
+#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
+#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
+#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
+#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
+#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
+#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
+#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
+#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
+#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
+#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
+#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
+#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
+#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
+#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
+#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
+#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
+#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
+#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+
+/*! @name STARTUP - ADC Startup register. */
+#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
+#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
+#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+
+/*! @name CALIB - ADC Calibration register. */
+#define ADC_CALIB_CALIB_MASK                     (0x1U)
+#define ADC_CALIB_CALIB_SHIFT                    (0U)
+#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK                   (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT                  (1U)
+#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
+#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
+  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
+  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE                        (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+
+/*! @name SEED - CRC seed register */
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+
+/*! @name SUM - CRC checksum register */
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+
+/*! @name WR_DATA - CRC data register */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE                          (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+
+/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+
+/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+
+/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+
+/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE                             (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE                             (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x5C */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+         uint8_t RESERVED_0[4];
+    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+         uint8_t RESERVED_1[4];
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+         uint8_t RESERVED_2[4];
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+         uint8_t RESERVED_3[4];
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+         uint8_t RESERVED_4[4];
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+         uint8_t RESERVED_5[4];
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+         uint8_t RESERVED_6[4];
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+         uint8_t RESERVED_7[4];
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+         uint8_t RESERVED_8[4];
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+         uint8_t RESERVED_9[4];
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+         uint8_t RESERVED_10[4];
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+  } COMMON[1];
+       uint8_t RESERVED_1[900];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[20];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+
+/*! @name INTSTAT - Interrupt status. */
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
+#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
+#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
+#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
+#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
+#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
+#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
+#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
+#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
+#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
+#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
+#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
+#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT                    (20U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
+#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT                (20U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
+#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
+#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
+#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
+#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
+#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
+#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT                (20U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS                                 { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t OSR;                               /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+    __IO uint32_t PREAC2FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+    __IO uint32_t PREAC4FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_0[108];
+    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+    __IO uint32_t FIFO_DATA;                         /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+    __IO uint32_t PHY_CTRL;                          /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+    __IO uint32_t DC_CTRL;                           /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+         uint8_t RESERVED_1[108];
+  } CHANNEL[2];
+       uint8_t RESERVED_0[3328];
+  __IO uint32_t CHANEN;                            /**< Channel Enable register, offset: 0xF00 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t IOCFG;                             /**< I/O Configuration register, offset: 0xF0C */
+  __IO uint32_t USE2FS;                            /**< Use 2FS register, offset: 0xF10 */
+       uint8_t RESERVED_2[108];
+  __IO uint32_t HWVADGAIN;                         /**< HWVAD input gain register, offset: 0xF80 */
+  __IO uint32_t HWVADHPFS;                         /**< HWVAD filter control register, offset: 0xF84 */
+  __IO uint32_t HWVADST10;                         /**< HWVAD control register, offset: 0xF88 */
+  __IO uint32_t HWVADRSTT;                         /**< HWVAD filter reset register, offset: 0xF8C */
+  __IO uint32_t HWVADTHGN;                         /**< HWVAD noise estimator gain register, offset: 0xF90 */
+  __IO uint32_t HWVADTHGS;                         /**< HWVAD signal estimator gain register, offset: 0xF94 */
+  __I  uint32_t HWVADLOWZ;                         /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+       uint8_t RESERVED_3[96];
+  __I  uint32_t ID;                                /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
+#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT                   (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)
+
+/*! @name CHANEN - Channel Enable register */
+#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
+#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
+#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+
+/*! @name IOCFG - I/O Configuration register */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK              (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT             (0U)
+#define DMIC_IOCFG_CLK_BYPASS0(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK              (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT             (1U)
+#define DMIC_IOCFG_CLK_BYPASS1(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK             (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT            (2U)
+#define DMIC_IOCFG_STEREO_DATA0(x)               (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+
+/*! @name USE2FS - Use 2FS register */
+#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
+#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
+#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
+#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+
+/*! @name HWVADST10 - HWVAD control register */
+#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT                (0U)
+#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+#define DMIC_HWVADRSTT_RSTT_MASK                 (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT                (0U)
+#define DMIC_HWVADRSTT_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
+#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
+#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
+#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+
+/*! @name ID - Module Identification register */
+#define DMIC_ID_ID_MASK                          (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT                         (0U)
+#define DMIC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE                               (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS                           { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS                                { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4088];
+  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+  __I  uint32_t PID;                               /**< Peripheral identification register., offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
+#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
+#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
+#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
+#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
+#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
+#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
+#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
+#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+
+/*! @name PID - Peripheral identification register. */
+#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
+#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
+#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT                    (16U)
+#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+/** Peripheral FLEXCOMM0 base address */
+#define FLEXCOMM0_BASE                           (0x40086000u)
+/** Peripheral FLEXCOMM0 base pointer */
+#define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+/** Peripheral FLEXCOMM1 base address */
+#define FLEXCOMM1_BASE                           (0x40087000u)
+/** Peripheral FLEXCOMM1 base pointer */
+#define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+/** Peripheral FLEXCOMM2 base address */
+#define FLEXCOMM2_BASE                           (0x40088000u)
+/** Peripheral FLEXCOMM2 base pointer */
+#define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+/** Peripheral FLEXCOMM3 base address */
+#define FLEXCOMM3_BASE                           (0x40089000u)
+/** Peripheral FLEXCOMM3 base pointer */
+#define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+/** Peripheral FLEXCOMM4 base address */
+#define FLEXCOMM4_BASE                           (0x4008A000u)
+/** Peripheral FLEXCOMM4 base pointer */
+#define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+/** Peripheral FLEXCOMM5 base address */
+#define FLEXCOMM5_BASE                           (0x40096000u)
+/** Peripheral FLEXCOMM5 base pointer */
+#define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+/** Peripheral FLEXCOMM6 base address */
+#define FLEXCOMM6_BASE                           (0x40097000u)
+/** Peripheral FLEXCOMM6 base pointer */
+#define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+/** Peripheral FLEXCOMM7 base address */
+#define FLEXCOMM7_BASE                           (0x40098000u)
+/** Peripheral FLEXCOMM7 base pointer */
+#define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+/** Array initializer of FLEXCOMM peripheral base addresses */
+#define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE }
+/** Array initializer of FLEXCOMM peripheral base pointers */
+#define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 }
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
+ * @{
+ */
+
+/** GINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PORT_POL[2];                       /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+} GINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Register_Masks GINT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - GPIO grouped interrupt control register */
+#define GINT_CTRL_INT_MASK                       (0x1U)
+#define GINT_CTRL_INT_SHIFT                      (0U)
+#define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+#define GINT_CTRL_COMB_MASK                      (0x2U)
+#define GINT_CTRL_COMB_SHIFT                     (1U)
+#define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+#define GINT_CTRL_TRIG_MASK                      (0x4U)
+#define GINT_CTRL_TRIG_SHIFT                     (2U)
+#define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
+#define GINT_PORT_POL_POL_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT                  (0U)
+#define GINT_PORT_POL_POL(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+
+/* The count of GINT_PORT_POL */
+#define GINT_PORT_POL_COUNT                      (2U)
+
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
+#define GINT_PORT_ENA_ENA_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT                  (0U)
+#define GINT_PORT_ENA_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+
+/* The count of GINT_PORT_ENA */
+#define GINT_PORT_ENA_COUNT                      (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GINT_Register_Masks */
+
+
+/* GINT - Peripheral instance base addresses */
+/** Peripheral GINT0 base address */
+#define GINT0_BASE                               (0x40002000u)
+/** Peripheral GINT0 base pointer */
+#define GINT0                                    ((GINT_Type *)GINT0_BASE)
+/** Peripheral GINT1 base address */
+#define GINT1_BASE                               (0x40003000u)
+/** Peripheral GINT1 base pointer */
+#define GINT1                                    ((GINT_Type *)GINT1_BASE)
+/** Array initializer of GINT peripheral base addresses */
+#define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
+/** Array initializer of GINT peripheral base pointers */
+#define GINT_BASE_PTRS                           { GINT0, GINT1 }
+/** Interrupt vectors for the GINT peripheral type */
+#define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t B[2][32];                           /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+       uint8_t RESERVED_0[4032];
+  __IO uint32_t W[2][32];                          /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+       uint8_t RESERVED_1[3840];
+  __IO uint32_t DIR[2];                            /**< Direction registers, array offset: 0x2000, array step: 0x4 */
+       uint8_t RESERVED_2[120];
+  __IO uint32_t MASK[2];                           /**< Mask register, array offset: 0x2080, array step: 0x4 */
+       uint8_t RESERVED_3[120];
+  __IO uint32_t PIN[2];                            /**< Port pin register, array offset: 0x2100, array step: 0x4 */
+       uint8_t RESERVED_4[120];
+  __IO uint32_t MPIN[2];                           /**< Masked port register, array offset: 0x2180, array step: 0x4 */
+       uint8_t RESERVED_5[120];
+  __IO uint32_t SET[2];                            /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+       uint8_t RESERVED_6[120];
+  __O  uint32_t CLR[2];                            /**< Clear port, array offset: 0x2280, array step: 0x4 */
+       uint8_t RESERVED_7[120];
+  __O  uint32_t NOT[2];                            /**< Toggle port, array offset: 0x2300, array step: 0x4 */
+       uint8_t RESERVED_8[120];
+  __O  uint32_t DIRSET[2];                         /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+       uint8_t RESERVED_9[120];
+  __O  uint32_t DIRCLR[2];                         /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+       uint8_t RESERVED_10[120];
+  __O  uint32_t DIRNOT[2];                         /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_B_PBYTE_MASK                        (0x1U)
+#define GPIO_B_PBYTE_SHIFT                       (0U)
+#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT                             (2U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2                            (32U)
+
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT                       (0U)
+#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT                             (2U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2                            (32U)
+
+/*! @name DIR - Direction registers */
+#define GPIO_DIR_DIRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT                      (0U)
+#define GPIO_DIR_DIRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT                           (2U)
+
+/*! @name MASK - Mask register */
+#define GPIO_MASK_MASKP_MASK                     (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT                    (0U)
+#define GPIO_MASK_MASKP(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT                          (2U)
+
+/*! @name PIN - Port pin register */
+#define GPIO_PIN_PORT_MASK                       (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT                      (0U)
+#define GPIO_PIN_PORT(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT                           (2U)
+
+/*! @name MPIN - Masked port register */
+#define GPIO_MPIN_MPORTP_MASK                    (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT                   (0U)
+#define GPIO_MPIN_MPORTP(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT                          (2U)
+
+/*! @name SET - Write: Set register for port Read: output bits for port */
+#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT                      (0U)
+#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT                           (2U)
+
+/*! @name CLR - Clear port */
+#define GPIO_CLR_CLRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT                      (0U)
+#define GPIO_CLR_CLRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT                           (2U)
+
+/*! @name NOT - Toggle port */
+#define GPIO_NOT_NOTP_MASK                       (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT                      (0U)
+#define GPIO_NOT_NOTP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT                           (2U)
+
+/*! @name DIRSET - Set pin direction bits for port */
+#define GPIO_DIRSET_DIRSETP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT                (0U)
+#define GPIO_DIRSET_DIRSETP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT                        (2U)
+
+/*! @name DIRCLR - Clear pin direction bits for port */
+#define GPIO_DIRCLR_DIRCLRP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT                (0U)
+#define GPIO_DIRCLR_DIRCLRP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT                        (2U)
+
+/*! @name DIRNOT - Toggle pin direction bits for port */
+#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
+#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT                        (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE                                (0x4008C000u)
+/** Peripheral GPIO base pointer */
+#define GPIO                                     ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIO }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2048];
+  __IO uint32_t CFG;                               /**< Configuration for shared functions., offset: 0x800 */
+  __IO uint32_t STAT;                              /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set and read register., offset: 0x808 */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register., offset: 0x80C */
+  __IO uint32_t TIMEOUT;                           /**< Time-out value register., offset: 0x810 */
+  __IO uint32_t CLKDIV;                            /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t MSTCTL;                            /**< Master control register., offset: 0x820 */
+  __IO uint32_t MSTTIME;                           /**< Master timing configuration., offset: 0x824 */
+  __IO uint32_t MSTDAT;                            /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t SLVCTL;                            /**< Slave control register., offset: 0x840 */
+  __IO uint32_t SLVDAT;                            /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+  __IO uint32_t SLVADR[4];                         /**< Slave address register., array offset: 0x848, array step: 0x4 */
+  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for address 0., offset: 0x858 */
+       uint8_t RESERVED_3[36];
+  __I  uint32_t MONRXDAT;                          /**< Monitor receiver data register., offset: 0x880 */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration for shared functions. */
+#define I2C_CFG_MSTEN_MASK                       (0x1U)
+#define I2C_CFG_MSTEN_SHIFT                      (0U)
+#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK                       (0x2U)
+#define I2C_CFG_SLVEN_SHIFT                      (1U)
+#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK                       (0x4U)
+#define I2C_CFG_MONEN_SHIFT                      (2U)
+#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
+#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
+#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
+#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
+#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT                (0U)
+#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
+#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
+#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
+#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT                (8U)
+#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
+#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
+#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT                    (12U)
+#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT                    (14U)
+#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
+#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK                     (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT                    (16U)
+#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK                      (0x20000U)
+#define I2C_STAT_MONOV_SHIFT                     (17U)
+#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
+#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT                   (19U)
+#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
+#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
+#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+
+/*! @name INTENSET - Interrupt Enable Set and read register. */
+#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
+#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
+#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
+#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
+#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
+#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
+#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
+#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
+#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
+#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
+#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
+#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
+#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
+#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
+#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
+#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
+#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
+#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
+#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
+#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+
+/*! @name TIMEOUT - Time-out value register. */
+#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
+#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT                     (4U)
+#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
+#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
+#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
+#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
+#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
+#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
+#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
+#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
+#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
+#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
+#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
+#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
+#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
+#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
+#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+
+/*! @name MSTCTL - Master control register. */
+#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
+#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
+#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
+#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
+#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+
+/*! @name MSTTIME - Master timing configuration. */
+#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
+#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
+#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
+#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT                    (0U)
+#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+
+/*! @name SLVCTL - Slave control register. */
+#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
+#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
+#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
+#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
+#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
+#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
+#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT                    (0U)
+#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+
+/*! @name SLVADR - Slave address register. */
+#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
+#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
+#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
+#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT                         (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */
+#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
+#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
+#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+
+/*! @name MONRXDAT - Monitor receiver data register. */
+#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
+#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
+#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
+#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
+#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40086000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40087000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x40088000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE                                (0x40089000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3                                     ((I2C_Type *)I2C3_BASE)
+/** Peripheral I2C4 base address */
+#define I2C4_BASE                                (0x4008A000u)
+/** Peripheral I2C4 base pointer */
+#define I2C4                                     ((I2C_Type *)I2C4_BASE)
+/** Peripheral I2C5 base address */
+#define I2C5_BASE                                (0x40096000u)
+/** Peripheral I2C5 base pointer */
+#define I2C5                                     ((I2C_Type *)I2C5_BASE)
+/** Peripheral I2C6 base address */
+#define I2C6_BASE                                (0x40097000u)
+/** Peripheral I2C6 base pointer */
+#define I2C6                                     ((I2C_Type *)I2C6_BASE)
+/** Peripheral I2C7 base address */
+#define I2C7_BASE                                (0x40098000u)
+/** Peripheral I2C7 base pointer */
+#define I2C7                                     ((I2C_Type *)I2C7_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[3072];
+  __IO uint32_t CFG1;                              /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
+  __IO uint32_t CFG2;                              /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
+  __IO uint32_t STAT;                              /**< Status register for the primary channel pair., offset: 0xC08 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< Clock divider, used by all channel pairs., offset: 0xC1C */
+       uint8_t RESERVED_2[480];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+  __O  uint32_t FIFOWR48H;                         /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
+       uint8_t RESERVED_5[8];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+  __I  uint32_t FIFORD48H;                         /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
+       uint8_t RESERVED_6[8];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
+#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
+#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
+#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
+#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
+#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+#define I2S_CFG1_MODE_MASK                       (0xC0U)
+#define I2S_CFG1_MODE_SHIFT                      (6U)
+#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
+#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
+#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
+#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
+#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
+#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT                    (13U)
+#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT                   (16U)
+#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
+#define I2S_CFG2_FRAMELEN_MASK                   (0x1FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
+#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+#define I2S_CFG2_POSITION_MASK                   (0x1FF0000U)
+#define I2S_CFG2_POSITION_SHIFT                  (16U)
+#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+
+/*! @name STAT - Status register for the primary channel pair. */
+#define I2S_STAT_BUSY_MASK                       (0x1U)
+#define I2S_STAT_BUSY_SHIFT                      (0U)
+#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
+#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+#define I2S_STAT_LR_MASK                         (0x4U)
+#define I2S_STAT_LR_SHIFT                        (2U)
+#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
+#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+
+/*! @name DIV - Clock divider, used by all channel pairs. */
+#define I2S_DIV_DIV_MASK                         (0xFFFU)
+#define I2S_DIV_DIV_SHIFT                        (0U)
+#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
+#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
+#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+#define I2S_FIFOCFG_TXI2SSE0_MASK                (0x4U)
+#define I2S_FIFOCFG_TXI2SSE0_SHIFT               (2U)
+#define I2S_FIFOCFG_TXI2SSE0(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
+#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
+#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
+#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
+#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
+#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
+#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
+#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
+#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+#define I2S_FIFOCFG_POPDBG_MASK                  (0x40000U)
+#define I2S_FIFOCFG_POPDBG_SHIFT                 (18U)
+#define I2S_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
+#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
+#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
+#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
+#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
+#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
+#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
+#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
+#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
+#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
+#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
+#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
+#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
+#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
+#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
+#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
+#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
+#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
+#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
+#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
+#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
+#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
+#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x40097000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Peripheral I2S1 base address */
+#define I2S1_BASE                                (0x40098000u)
+/** Peripheral I2S1 base pointer */
+#define I2S1                                     ((I2S_Type *)I2S1_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0, I2S1 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS                                 { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[192];
+  __IO uint32_t PINTSEL[8];                        /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
+  __IO uint32_t DMA_ITRIG_INMUX[22];               /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
+       uint8_t RESERVED_1[40];
+  __IO uint32_t DMA_OTRIG_INMUX[4];                /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
+  __IO uint32_t FREQMEAS_TARGET;                   /**< Selection for frequency measurement target clock, offset: 0x184 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name PINTSEL - Pin interrupt select register */
+#define INPUTMUX_PINTSEL_INTPIN_MASK             (0xFFU)
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT            (0U)
+#define INPUTMUX_PINTSEL_INTPIN(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
+
+/* The count of INPUTMUX_PINTSEL */
+#define INPUTMUX_PINTSEL_COUNT                   (8U)
+
+/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT       (0U)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_ITRIG_INMUX */
+#define INPUTMUX_DMA_ITRIG_INMUX_COUNT           (22U)
+
+/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT       (0U)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_OTRIG_INMUX */
+#define INPUTMUX_DMA_OTRIG_INMUX_COUNT           (4U)
+
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
+
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK      (0x1FU)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT     (0U)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX base address */
+#define INPUTMUX_BASE                            (0x40005000u)
+/** Peripheral INPUTMUX base pointer */
+#define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS                       { INPUTMUX }
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
+ * @{
+ */
+
+/** IOCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PIO[2][32];                        /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
+} IOCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks
+ * @{
+ */
+
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */
+#define IOCON_PIO_FUNC_MASK                      (0x7U)
+#define IOCON_PIO_FUNC_SHIFT                     (0U)
+#define IOCON_PIO_FUNC(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
+#define IOCON_PIO_MODE_MASK                      (0x18U)
+#define IOCON_PIO_MODE_SHIFT                     (3U)
+#define IOCON_PIO_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
+#define IOCON_PIO_I2CSLEW_MASK                   (0x20U)
+#define IOCON_PIO_I2CSLEW_SHIFT                  (5U)
+#define IOCON_PIO_I2CSLEW(x)                     (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
+#define IOCON_PIO_INVERT_MASK                    (0x40U)
+#define IOCON_PIO_INVERT_SHIFT                   (6U)
+#define IOCON_PIO_INVERT(x)                      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
+#define IOCON_PIO_DIGIMODE_MASK                  (0x80U)
+#define IOCON_PIO_DIGIMODE_SHIFT                 (7U)
+#define IOCON_PIO_DIGIMODE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
+#define IOCON_PIO_FILTEROFF_MASK                 (0x100U)
+#define IOCON_PIO_FILTEROFF_SHIFT                (8U)
+#define IOCON_PIO_FILTEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
+#define IOCON_PIO_I2CDRIVE_MASK                  (0x200U)
+#define IOCON_PIO_I2CDRIVE_SHIFT                 (9U)
+#define IOCON_PIO_I2CDRIVE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
+#define IOCON_PIO_SLEW_MASK                      (0x200U)
+#define IOCON_PIO_SLEW_SHIFT                     (9U)
+#define IOCON_PIO_SLEW(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
+#define IOCON_PIO_OD_MASK                        (0x400U)
+#define IOCON_PIO_OD_SHIFT                       (10U)
+#define IOCON_PIO_OD(x)                          (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
+#define IOCON_PIO_I2CFILTER_MASK                 (0x400U)
+#define IOCON_PIO_I2CFILTER_SHIFT                (10U)
+#define IOCON_PIO_I2CFILTER(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT                          (2U)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT2                         (32U)
+
+
+/*!
+ * @}
+ */ /* end of group IOCON_Register_Masks */
+
+
+/* IOCON - Peripheral instance base addresses */
+/** Peripheral IOCON base address */
+#define IOCON_BASE                               (0x40001000u)
+/** Peripheral IOCON base pointer */
+#define IOCON                                    ((IOCON_Type *)IOCON_BASE)
+/** Array initializer of IOCON peripheral base addresses */
+#define IOCON_BASE_ADDRS                         { IOCON_BASE }
+/** Array initializer of IOCON peripheral base pointers */
+#define IOCON_BASE_PTRS                          { IOCON }
+
+/*!
+ * @}
+ */ /* end of group IOCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MAILBOX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer
+ * @{
+ */
+
+/** MAILBOX - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x10 */
+    __IO uint32_t IRQ;                               /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */
+    __O  uint32_t IRQSET;                            /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */
+    __O  uint32_t IRQCLR;                            /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } MBOXIRQ[2];
+       uint8_t RESERVED_0[216];
+  __IO uint32_t MUTEX;                             /**< Mutual exclusion register[1], offset: 0xF8 */
+} MAILBOX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MAILBOX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks
+ * @{
+ */
+
+/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK          (0xFFFFFFFFU)
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT         (0U)
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x)            (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK)
+
+/* The count of MAILBOX_MBOXIRQ_IRQ */
+#define MAILBOX_MBOXIRQ_IRQ_COUNT                (2U)
+
+/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK    (0xFFFFFFFFU)
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT   (0U)
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x)      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK)
+
+/* The count of MAILBOX_MBOXIRQ_IRQSET */
+#define MAILBOX_MBOXIRQ_IRQSET_COUNT             (2U)
+
+/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK    (0xFFFFFFFFU)
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT   (0U)
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x)      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK)
+
+/* The count of MAILBOX_MBOXIRQ_IRQCLR */
+#define MAILBOX_MBOXIRQ_IRQCLR_COUNT             (2U)
+
+/*! @name MUTEX - Mutual exclusion register[1] */
+#define MAILBOX_MUTEX_EX_MASK                    (0x1U)
+#define MAILBOX_MUTEX_EX_SHIFT                   (0U)
+#define MAILBOX_MUTEX_EX(x)                      (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MAILBOX_Register_Masks */
+
+
+/* MAILBOX - Peripheral instance base addresses */
+/** Peripheral MAILBOX base address */
+#define MAILBOX_BASE                             (0x4008B000u)
+/** Peripheral MAILBOX base pointer */
+#define MAILBOX                                  ((MAILBOX_Type *)MAILBOX_BASE)
+/** Array initializer of MAILBOX peripheral base addresses */
+#define MAILBOX_BASE_ADDRS                       { MAILBOX_BASE }
+/** Array initializer of MAILBOX peripheral base pointers */
+#define MAILBOX_BASE_PTRS                        { MAILBOX }
+/** Interrupt vectors for the MAILBOX peripheral type */
+#define MAILBOX_IRQS                             { MAILBOX_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MAILBOX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MRT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x10 */
+    __IO uint32_t INTVAL;                            /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
+    __I  uint32_t TIMER;                             /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
+    __IO uint32_t CTRL;                              /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
+    __IO uint32_t STAT;                              /**< MRT Status register., array offset: 0xC, array step: 0x10 */
+  } CHANNEL[4];
+       uint8_t RESERVED_0[176];
+  __IO uint32_t MODCFG;                            /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
+  __I  uint32_t IDLE_CH;                           /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
+  __IO uint32_t IRQ_FLAG;                          /**< Global interrupt flag register, offset: 0xF8 */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MRT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
+#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
+#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT                 (4U)
+
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
+#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
+#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT                  (4U)
+
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
+#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
+#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
+#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT                   (4U)
+
+/*! @name CHANNEL_STAT - MRT Status register. */
+#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
+#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
+#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
+#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT                   (4U)
+
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
+#define MRT_MODCFG_NOC_MASK                      (0xFU)
+#define MRT_MODCFG_NOC_SHIFT                     (0U)
+#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT                     (4U)
+#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
+#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
+#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
+#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+
+/*! @name IRQ_FLAG - Global interrupt flag register */
+#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
+#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
+#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
+#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
+#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+/** Peripheral MRT0 base address */
+#define MRT0_BASE                                (0x4000D000u)
+/** Peripheral MRT0 base pointer */
+#define MRT0                                     ((MRT_Type *)MRT0_BASE)
+/** Array initializer of MRT peripheral base addresses */
+#define MRT_BASE_ADDRS                           { MRT0_BASE }
+/** Array initializer of MRT peripheral base pointers */
+#define MRT_BASE_PTRS                            { MRT0 }
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS                                 { MRT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode register, offset: 0x0 */
+  __IO uint32_t IENR;                              /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
+  __O  uint32_t SIENR;                             /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
+  __O  uint32_t CIENR;                             /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
+  __IO uint32_t IENF;                              /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
+  __O  uint32_t SIENF;                             /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
+  __O  uint32_t CIENF;                             /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
+  __IO uint32_t RISE;                              /**< Pin interrupt rising edge register, offset: 0x1C */
+  __IO uint32_t FALL;                              /**< Pin interrupt falling edge register, offset: 0x20 */
+  __IO uint32_t IST;                               /**< Pin interrupt status register, offset: 0x24 */
+  __IO uint32_t PMCTRL;                            /**< Pattern match interrupt control register, offset: 0x28 */
+  __IO uint32_t PMSRC;                             /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
+  __IO uint32_t PMCFG;                             /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode register */
+#define PINT_ISEL_PMODE_MASK                     (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT                    (0U)
+#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
+#define PINT_IENR_ENRL_MASK                      (0xFFU)
+#define PINT_IENR_ENRL_SHIFT                     (0U)
+#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
+#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT                 (0U)
+#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
+#define PINT_CIENR_CENRL_MASK                    (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT                   (0U)
+#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
+#define PINT_IENF_ENAF_MASK                      (0xFFU)
+#define PINT_IENF_ENAF_SHIFT                     (0U)
+#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
+#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT                 (0U)
+#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
+#define PINT_CIENF_CENAF_MASK                    (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT                   (0U)
+#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+
+/*! @name RISE - Pin interrupt rising edge register */
+#define PINT_RISE_RDET_MASK                      (0xFFU)
+#define PINT_RISE_RDET_SHIFT                     (0U)
+#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+
+/*! @name FALL - Pin interrupt falling edge register */
+#define PINT_FALL_FDET_MASK                      (0xFFU)
+#define PINT_FALL_FDET_SHIFT                     (0U)
+#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+
+/*! @name IST - Pin interrupt status register */
+#define PINT_IST_PSTAT_MASK                      (0xFFU)
+#define PINT_IST_PSTAT_SHIFT                     (0U)
+#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+
+/*! @name PMCTRL - Pattern match interrupt control register */
+#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
+#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
+#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
+#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */
+#define PINT_PMSRC_SRC0_MASK                     (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT                    (8U)
+#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT                    (11U)
+#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT                    (14U)
+#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT                    (17U)
+#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT                    (20U)
+#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT                    (23U)
+#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT                    (26U)
+#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT                    (29U)
+#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
+#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
+#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
+#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
+#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
+#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
+#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
+#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
+#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+#define PINT_PMCFG_CFG0_MASK                     (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT                    (8U)
+#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT                    (11U)
+#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT                    (14U)
+#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT                    (17U)
+#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT                    (20U)
+#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT                    (23U)
+#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT                    (26U)
+#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT                    (29U)
+#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+/** Peripheral PINT base address */
+#define PINT_BASE                                (0x40004000u)
+/** Peripheral PINT base pointer */
+#define PINT                                     ((PINT_Type *)PINT_BASE)
+/** Array initializer of PINT peripheral base addresses */
+#define PINT_BASE_ADDRS                          { PINT_BASE }
+/** Array initializer of PINT peripheral base pointers */
+#define PINT_BASE_PTRS                           { PINT }
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< RTC control register, offset: 0x0 */
+  __IO uint32_t MATCH;                             /**< RTC match register, offset: 0x4 */
+  __IO uint32_t COUNT;                             /**< RTC counter register, offset: 0x8 */
+  __IO uint32_t WAKE;                              /**< High-resolution/wake-up timer control register, offset: 0xC */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC control register */
+#define RTC_CTRL_SWRESET_MASK                    (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT                   (0U)
+#define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+#define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
+#define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+#define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
+#define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+#define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
+#define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+#define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
+#define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+#define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
+#define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+#define RTC_CTRL_RTC_EN_MASK                     (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT                    (7U)
+#define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+#define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
+#define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+#define RTC_CTRL_RTC_OSC_BYPASS_MASK             (0x200U)
+#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT            (9U)
+#define RTC_CTRL_RTC_OSC_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK)
+
+/*! @name MATCH - RTC match register */
+#define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT                   (0U)
+#define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+
+/*! @name COUNT - RTC counter register */
+#define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT                      (0U)
+#define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+
+/*! @name WAKE - High-resolution/wake-up timer control register */
+#define RTC_WAKE_VAL_MASK                        (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT                       (0U)
+#define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4002C000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SCT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONFIG;                            /**< SCT configuration register, offset: 0x0 */
+  __IO uint32_t CTRL;                              /**< SCT control register, offset: 0x4 */
+  __IO uint32_t LIMIT;                             /**< SCT limit event select register, offset: 0x8 */
+  __IO uint32_t HALT;                              /**< SCT halt event select register, offset: 0xC */
+  __IO uint32_t STOP;                              /**< SCT stop event select register, offset: 0x10 */
+  __IO uint32_t START;                             /**< SCT start event select register, offset: 0x14 */
+       uint8_t RESERVED_0[40];
+  __IO uint32_t COUNT;                             /**< SCT counter register, offset: 0x40 */
+  __IO uint32_t STATE;                             /**< SCT state register, offset: 0x44 */
+  __I  uint32_t INPUT;                             /**< SCT input register, offset: 0x48 */
+  __IO uint32_t REGMODE;                           /**< SCT match/capture mode register, offset: 0x4C */
+  __IO uint32_t OUTPUT;                            /**< SCT output register, offset: 0x50 */
+  __IO uint32_t OUTPUTDIRCTRL;                     /**< SCT output counter direction control register, offset: 0x54 */
+  __IO uint32_t RES;                               /**< SCT conflict resolution register, offset: 0x58 */
+  __IO uint32_t DMA0REQUEST;                       /**< SCT DMA request 0 register, offset: 0x5C */
+  __IO uint32_t DMA1REQUEST;                       /**< SCT DMA request 1 register, offset: 0x60 */
+       uint8_t RESERVED_1[140];
+  __IO uint32_t EVEN;                              /**< SCT event interrupt enable register, offset: 0xF0 */
+  __IO uint32_t EVFLAG;                            /**< SCT event flag register, offset: 0xF4 */
+  __IO uint32_t CONEN;                             /**< SCT conflict interrupt enable register, offset: 0xF8 */
+  __IO uint32_t CONFLAG;                           /**< SCT conflict flag register, offset: 0xFC */
+  union {                                          /* offset: 0x100 */
+    __IO uint32_t SCTCAP[10];                        /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
+    __IO uint32_t SCTMATCH[10];                      /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
+  };
+       uint8_t RESERVED_2[216];
+  union {                                          /* offset: 0x200 */
+    __IO uint32_t SCTCAPCTRL[10];                    /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
+    __IO uint32_t SCTMATCHREL[10];                   /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+  };
+       uint8_t RESERVED_3[216];
+  struct {                                         /* offset: 0x300, array step: 0x8 */
+    __IO uint32_t STATE;                             /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
+    __IO uint32_t CTRL;                              /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
+  } EVENT[10];
+       uint8_t RESERVED_4[432];
+  struct {                                         /* offset: 0x500, array step: 0x8 */
+    __IO uint32_t SET;                               /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
+    __IO uint32_t CLR;                               /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
+  } OUT[8];
+       uint8_t RESERVED_5[700];
+  __IO uint32_t MODULECONTENT;                     /**< Reserved, offset: 0x7FC */
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCT configuration register */
+#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
+#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
+#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
+#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+#define SCT_CONFIG_NORELAOD_L_MASK               (0x80U)
+#define SCT_CONFIG_NORELAOD_L_SHIFT              (7U)
+#define SCT_CONFIG_NORELAOD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
+#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
+#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+#define SCT_CONFIG_INSYNC_MASK                   (0x1E00U)
+#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
+#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
+#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
+#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+
+/*! @name CTRL - SCT control register */
+#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
+#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+#define SCT_CTRL_STOP_L_MASK                     (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT                    (1U)
+#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+#define SCT_CTRL_HALT_L_MASK                     (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT                    (2U)
+#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
+#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
+#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT                     (5U)
+#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
+#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT                    (17U)
+#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT                    (18U)
+#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
+#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
+#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT                     (21U)
+#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+
+/*! @name LIMIT - SCT limit event select register */
+#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
+#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
+#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+
+/*! @name HALT - SCT halt event select register */
+#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
+#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
+#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+
+/*! @name STOP - SCT stop event select register */
+#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
+#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
+#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+
+/*! @name START - SCT start event select register */
+#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT               (0U)
+#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT               (16U)
+#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+
+/*! @name COUNT - SCT counter register */
+#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT                    (0U)
+#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT                    (16U)
+#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+
+/*! @name STATE - SCT state register */
+#define SCT_STATE_STATE_L_MASK                   (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT                  (0U)
+#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT                  (16U)
+#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+
+/*! @name INPUT - SCT input register */
+#define SCT_INPUT_AIN0_MASK                      (0x1U)
+#define SCT_INPUT_AIN0_SHIFT                     (0U)
+#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+#define SCT_INPUT_AIN1_MASK                      (0x2U)
+#define SCT_INPUT_AIN1_SHIFT                     (1U)
+#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+#define SCT_INPUT_AIN2_MASK                      (0x4U)
+#define SCT_INPUT_AIN2_SHIFT                     (2U)
+#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+#define SCT_INPUT_AIN3_MASK                      (0x8U)
+#define SCT_INPUT_AIN3_SHIFT                     (3U)
+#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+#define SCT_INPUT_AIN4_MASK                      (0x10U)
+#define SCT_INPUT_AIN4_SHIFT                     (4U)
+#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+#define SCT_INPUT_AIN5_MASK                      (0x20U)
+#define SCT_INPUT_AIN5_SHIFT                     (5U)
+#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+#define SCT_INPUT_AIN6_MASK                      (0x40U)
+#define SCT_INPUT_AIN6_SHIFT                     (6U)
+#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+#define SCT_INPUT_AIN7_MASK                      (0x80U)
+#define SCT_INPUT_AIN7_SHIFT                     (7U)
+#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+#define SCT_INPUT_AIN8_MASK                      (0x100U)
+#define SCT_INPUT_AIN8_SHIFT                     (8U)
+#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+#define SCT_INPUT_AIN9_MASK                      (0x200U)
+#define SCT_INPUT_AIN9_SHIFT                     (9U)
+#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+#define SCT_INPUT_AIN10_MASK                     (0x400U)
+#define SCT_INPUT_AIN10_SHIFT                    (10U)
+#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+#define SCT_INPUT_AIN11_MASK                     (0x800U)
+#define SCT_INPUT_AIN11_SHIFT                    (11U)
+#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+#define SCT_INPUT_AIN12_MASK                     (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT                    (12U)
+#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+#define SCT_INPUT_AIN13_MASK                     (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT                    (13U)
+#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+#define SCT_INPUT_AIN14_MASK                     (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT                    (14U)
+#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+#define SCT_INPUT_AIN15_MASK                     (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT                    (15U)
+#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+#define SCT_INPUT_SIN0_MASK                      (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT                     (16U)
+#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+#define SCT_INPUT_SIN1_MASK                      (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT                     (17U)
+#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+#define SCT_INPUT_SIN2_MASK                      (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT                     (18U)
+#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+#define SCT_INPUT_SIN3_MASK                      (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT                     (19U)
+#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+#define SCT_INPUT_SIN4_MASK                      (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT                     (20U)
+#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+#define SCT_INPUT_SIN5_MASK                      (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT                     (21U)
+#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+#define SCT_INPUT_SIN6_MASK                      (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT                     (22U)
+#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+#define SCT_INPUT_SIN7_MASK                      (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT                     (23U)
+#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT                     (24U)
+#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT                     (25U)
+#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT                    (26U)
+#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT                    (27U)
+#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT                    (28U)
+#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT                    (29U)
+#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT                    (30U)
+#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT                    (31U)
+#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+
+/*! @name REGMODE - SCT match/capture mode register */
+#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
+#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
+#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+
+/*! @name OUTPUT - SCT output register */
+#define SCT_OUTPUT_OUT_MASK                      (0xFFFFU)
+#define SCT_OUTPUT_OUT_SHIFT                     (0U)
+#define SCT_OUTPUT_OUT(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
+
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK          (0x300000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT         (20U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK          (0xC00000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT         (22U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK          (0x3000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT         (24U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK          (0xC000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT         (26U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK          (0x30000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT         (28U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK          (0xC0000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT         (30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
+
+/*! @name RES - SCT conflict resolution register */
+#define SCT_RES_O0RES_MASK                       (0x3U)
+#define SCT_RES_O0RES_SHIFT                      (0U)
+#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+#define SCT_RES_O1RES_MASK                       (0xCU)
+#define SCT_RES_O1RES_SHIFT                      (2U)
+#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+#define SCT_RES_O2RES_MASK                       (0x30U)
+#define SCT_RES_O2RES_SHIFT                      (4U)
+#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+#define SCT_RES_O3RES_MASK                       (0xC0U)
+#define SCT_RES_O3RES_SHIFT                      (6U)
+#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+#define SCT_RES_O4RES_MASK                       (0x300U)
+#define SCT_RES_O4RES_SHIFT                      (8U)
+#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+#define SCT_RES_O5RES_MASK                       (0xC00U)
+#define SCT_RES_O5RES_SHIFT                      (10U)
+#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+#define SCT_RES_O6RES_MASK                       (0x3000U)
+#define SCT_RES_O6RES_SHIFT                      (12U)
+#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+#define SCT_RES_O7RES_MASK                       (0xC000U)
+#define SCT_RES_O7RES_SHIFT                      (14U)
+#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+#define SCT_RES_O8RES_MASK                       (0x30000U)
+#define SCT_RES_O8RES_SHIFT                      (16U)
+#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+#define SCT_RES_O9RES_MASK                       (0xC0000U)
+#define SCT_RES_O9RES_SHIFT                      (18U)
+#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+#define SCT_RES_O10RES_MASK                      (0x300000U)
+#define SCT_RES_O10RES_SHIFT                     (20U)
+#define SCT_RES_O10RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
+#define SCT_RES_O11RES_MASK                      (0xC00000U)
+#define SCT_RES_O11RES_SHIFT                     (22U)
+#define SCT_RES_O11RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
+#define SCT_RES_O12RES_MASK                      (0x3000000U)
+#define SCT_RES_O12RES_SHIFT                     (24U)
+#define SCT_RES_O12RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
+#define SCT_RES_O13RES_MASK                      (0xC000000U)
+#define SCT_RES_O13RES_SHIFT                     (26U)
+#define SCT_RES_O13RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
+#define SCT_RES_O14RES_MASK                      (0x30000000U)
+#define SCT_RES_O14RES_SHIFT                     (28U)
+#define SCT_RES_O14RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
+#define SCT_RES_O15RES_MASK                      (0xC0000000U)
+#define SCT_RES_O15RES_SHIFT                     (30U)
+#define SCT_RES_O15RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
+
+/*! @name DMA0REQUEST - SCT DMA request 0 register */
+#define SCT_DMA0REQUEST_DEV_0_MASK               (0xFFFFU)
+#define SCT_DMA0REQUEST_DEV_0_SHIFT              (0U)
+#define SCT_DMA0REQUEST_DEV_0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
+#define SCT_DMA0REQUEST_DRL0_MASK                (0x40000000U)
+#define SCT_DMA0REQUEST_DRL0_SHIFT               (30U)
+#define SCT_DMA0REQUEST_DRL0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
+#define SCT_DMA0REQUEST_DRQ0_MASK                (0x80000000U)
+#define SCT_DMA0REQUEST_DRQ0_SHIFT               (31U)
+#define SCT_DMA0REQUEST_DRQ0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
+
+/*! @name DMA1REQUEST - SCT DMA request 1 register */
+#define SCT_DMA1REQUEST_DEV_1_MASK               (0xFFFFU)
+#define SCT_DMA1REQUEST_DEV_1_SHIFT              (0U)
+#define SCT_DMA1REQUEST_DEV_1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
+#define SCT_DMA1REQUEST_DRL1_MASK                (0x40000000U)
+#define SCT_DMA1REQUEST_DRL1_SHIFT               (30U)
+#define SCT_DMA1REQUEST_DRL1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
+#define SCT_DMA1REQUEST_DRQ1_MASK                (0x80000000U)
+#define SCT_DMA1REQUEST_DRQ1_SHIFT               (31U)
+#define SCT_DMA1REQUEST_DRQ1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
+
+/*! @name EVEN - SCT event interrupt enable register */
+#define SCT_EVEN_IEN_MASK                        (0xFFFFU)
+#define SCT_EVEN_IEN_SHIFT                       (0U)
+#define SCT_EVEN_IEN(x)                          (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
+
+/*! @name EVFLAG - SCT event flag register */
+#define SCT_EVFLAG_FLAG_MASK                     (0xFFFFU)
+#define SCT_EVFLAG_FLAG_SHIFT                    (0U)
+#define SCT_EVFLAG_FLAG(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
+
+/*! @name CONEN - SCT conflict interrupt enable register */
+#define SCT_CONEN_NCEN_MASK                      (0xFFFFU)
+#define SCT_CONEN_NCEN_SHIFT                     (0U)
+#define SCT_CONEN_NCEN(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
+
+/*! @name CONFLAG - SCT conflict flag register */
+#define SCT_CONFLAG_NCFLAG_MASK                  (0xFFFFU)
+#define SCT_CONFLAG_NCFLAG_SHIFT                 (0U)
+#define SCT_CONFLAG_NCFLAG(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
+#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
+#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
+#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+
+/*! @name SCTCAP - SCT capture register of capture channel */
+#define SCT_SCTCAP_CAPn_L_MASK                   (0xFFFFU)
+#define SCT_SCTCAP_CAPn_L_SHIFT                  (0U)
+#define SCT_SCTCAP_CAPn_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
+#define SCT_SCTCAP_CAPn_H_MASK                   (0xFFFF0000U)
+#define SCT_SCTCAP_CAPn_H_SHIFT                  (16U)
+#define SCT_SCTCAP_CAPn_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
+
+/* The count of SCT_SCTCAP */
+#define SCT_SCTCAP_COUNT                         (10U)
+
+/*! @name SCTMATCH - SCT match value register of match channels */
+#define SCT_SCTMATCH_MATCHn_L_MASK               (0xFFFFU)
+#define SCT_SCTMATCH_MATCHn_L_SHIFT              (0U)
+#define SCT_SCTMATCH_MATCHn_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
+#define SCT_SCTMATCH_MATCHn_H_MASK               (0xFFFF0000U)
+#define SCT_SCTMATCH_MATCHn_H_SHIFT              (16U)
+#define SCT_SCTMATCH_MATCHn_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
+
+/* The count of SCT_SCTMATCH */
+#define SCT_SCTMATCH_COUNT                       (10U)
+
+/*! @name SCTCAPCTRL - SCT capture control register */
+#define SCT_SCTCAPCTRL_CAPCONn_L_MASK            (0xFFFFU)
+#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT           (0U)
+#define SCT_SCTCAPCTRL_CAPCONn_L(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
+#define SCT_SCTCAPCTRL_CAPCONn_H_MASK            (0xFFFF0000U)
+#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT           (16U)
+#define SCT_SCTCAPCTRL_CAPCONn_H(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
+
+/* The count of SCT_SCTCAPCTRL */
+#define SCT_SCTCAPCTRL_COUNT                     (10U)
+
+/*! @name SCTMATCHREL - SCT match reload value register */
+#define SCT_SCTMATCHREL_RELOADn_L_MASK           (0xFFFFU)
+#define SCT_SCTMATCHREL_RELOADn_L_SHIFT          (0U)
+#define SCT_SCTMATCHREL_RELOADn_L(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
+#define SCT_SCTMATCHREL_RELOADn_H_MASK           (0xFFFF0000U)
+#define SCT_SCTMATCHREL_RELOADn_H_SHIFT          (16U)
+#define SCT_SCTMATCHREL_RELOADn_H(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
+
+/* The count of SCT_SCTMATCHREL */
+#define SCT_SCTMATCHREL_COUNT                    (10U)
+
+/*! @name EVENT_STATE - SCT event state register 0 */
+#define SCT_EVENT_STATE_STATEMSKn_MASK           (0xFFFFU)
+#define SCT_EVENT_STATE_STATEMSKn_SHIFT          (0U)
+#define SCT_EVENT_STATE_STATEMSKn(x)             (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
+
+/* The count of SCT_EVENT_STATE */
+#define SCT_EVENT_STATE_COUNT                    (10U)
+
+/*! @name EVENT_CTRL - SCT event control register 0 */
+#define SCT_EVENT_CTRL_MATCHSEL_MASK             (0xFU)
+#define SCT_EVENT_CTRL_MATCHSEL_SHIFT            (0U)
+#define SCT_EVENT_CTRL_MATCHSEL(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
+#define SCT_EVENT_CTRL_HEVENT_MASK               (0x10U)
+#define SCT_EVENT_CTRL_HEVENT_SHIFT              (4U)
+#define SCT_EVENT_CTRL_HEVENT(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
+#define SCT_EVENT_CTRL_OUTSEL_MASK               (0x20U)
+#define SCT_EVENT_CTRL_OUTSEL_SHIFT              (5U)
+#define SCT_EVENT_CTRL_OUTSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
+#define SCT_EVENT_CTRL_IOSEL_MASK                (0x3C0U)
+#define SCT_EVENT_CTRL_IOSEL_SHIFT               (6U)
+#define SCT_EVENT_CTRL_IOSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
+#define SCT_EVENT_CTRL_IOCOND_MASK               (0xC00U)
+#define SCT_EVENT_CTRL_IOCOND_SHIFT              (10U)
+#define SCT_EVENT_CTRL_IOCOND(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
+#define SCT_EVENT_CTRL_COMBMODE_MASK             (0x3000U)
+#define SCT_EVENT_CTRL_COMBMODE_SHIFT            (12U)
+#define SCT_EVENT_CTRL_COMBMODE(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
+#define SCT_EVENT_CTRL_STATELD_MASK              (0x4000U)
+#define SCT_EVENT_CTRL_STATELD_SHIFT             (14U)
+#define SCT_EVENT_CTRL_STATELD(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
+#define SCT_EVENT_CTRL_STATEV_MASK               (0xF8000U)
+#define SCT_EVENT_CTRL_STATEV_SHIFT              (15U)
+#define SCT_EVENT_CTRL_STATEV(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
+#define SCT_EVENT_CTRL_MATCHMEM_MASK             (0x100000U)
+#define SCT_EVENT_CTRL_MATCHMEM_SHIFT            (20U)
+#define SCT_EVENT_CTRL_MATCHMEM(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
+#define SCT_EVENT_CTRL_DIRECTION_MASK            (0x600000U)
+#define SCT_EVENT_CTRL_DIRECTION_SHIFT           (21U)
+#define SCT_EVENT_CTRL_DIRECTION(x)              (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
+
+/* The count of SCT_EVENT_CTRL */
+#define SCT_EVENT_CTRL_COUNT                     (10U)
+
+/*! @name OUT_SET - SCT output 0 set register */
+#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT                    (0U)
+#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT                        (8U)
+
+/*! @name OUT_CLR - SCT output 0 clear register */
+#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
+#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT                        (8U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+/** Peripheral SCT0 base address */
+#define SCT0_BASE                                (0x40085000u)
+/** Peripheral SCT0 base pointer */
+#define SCT0                                     ((SCT_Type *)SCT0_BASE)
+/** Array initializer of SCT peripheral base addresses */
+#define SCT_BASE_ADDRS                           { SCT0_BASE }
+/** Array initializer of SCT peripheral base pointers */
+#define SCT_BASE_PTRS                            { SCT0 }
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS                                 { SCT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1024];
+  __IO uint32_t CFG;                               /**< SPI Configuration register, offset: 0x400 */
+  __IO uint32_t DLY;                               /**< SPI Delay register, offset: 0x404 */
+  __IO uint32_t STAT;                              /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
+  __IO uint32_t INTENSET;                          /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
+  __O  uint32_t INTENCLR;                          /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< SPI clock Divider, offset: 0x424 */
+  __I  uint32_t INTSTAT;                           /**< SPI Interrupt Status, offset: 0x428 */
+       uint8_t RESERVED_2[2516];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_6[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - SPI Configuration register */
+#define SPI_CFG_ENABLE_MASK                      (0x1U)
+#define SPI_CFG_ENABLE_SHIFT                     (0U)
+#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+#define SPI_CFG_MASTER_MASK                      (0x4U)
+#define SPI_CFG_MASTER_SHIFT                     (2U)
+#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+#define SPI_CFG_LSBF_MASK                        (0x8U)
+#define SPI_CFG_LSBF_SHIFT                       (3U)
+#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+#define SPI_CFG_CPHA_MASK                        (0x10U)
+#define SPI_CFG_CPHA_SHIFT                       (4U)
+#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+#define SPI_CFG_CPOL_MASK                        (0x20U)
+#define SPI_CFG_CPOL_SHIFT                       (5U)
+#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+#define SPI_CFG_LOOP_MASK                        (0x80U)
+#define SPI_CFG_LOOP_SHIFT                       (7U)
+#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+#define SPI_CFG_SPOL0_MASK                       (0x100U)
+#define SPI_CFG_SPOL0_SHIFT                      (8U)
+#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+#define SPI_CFG_SPOL1_MASK                       (0x200U)
+#define SPI_CFG_SPOL1_SHIFT                      (9U)
+#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+#define SPI_CFG_SPOL2_MASK                       (0x400U)
+#define SPI_CFG_SPOL2_SHIFT                      (10U)
+#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+#define SPI_CFG_SPOL3_MASK                       (0x800U)
+#define SPI_CFG_SPOL3_SHIFT                      (11U)
+#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+
+/*! @name DLY - SPI Delay register */
+#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
+#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
+#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
+#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
+#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
+#define SPI_STAT_SSA_MASK                        (0x10U)
+#define SPI_STAT_SSA_SHIFT                       (4U)
+#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+#define SPI_STAT_SSD_MASK                        (0x20U)
+#define SPI_STAT_SSD_SHIFT                       (5U)
+#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+#define SPI_STAT_STALLED_MASK                    (0x40U)
+#define SPI_STAT_STALLED_SHIFT                   (6U)
+#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
+#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
+#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
+#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
+#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
+#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
+#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
+#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
+#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
+#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+
+/*! @name DIV - SPI clock Divider */
+#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT                     (0U)
+#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - SPI Interrupt Status */
+#define SPI_INTSTAT_SSA_MASK                     (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT                    (4U)
+#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+#define SPI_INTSTAT_SSD_MASK                     (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT                    (5U)
+#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
+#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
+#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
+#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
+#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
+#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
+#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
+#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
+#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
+#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
+#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
+#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
+#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
+#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
+#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
+#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
+#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
+#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
+#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
+#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
+#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
+#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
+#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
+#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
+#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
+#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
+#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
+#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
+#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
+#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
+#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
+#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
+#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT                     (20U)
+#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT                     (21U)
+#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
+#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT                     (24U)
+#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
+#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
+#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
+#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
+#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
+#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+#define SPI_FIFORD_SOT_MASK                      (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT                     (20U)
+#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
+#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40086000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40087000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x40088000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+/** Peripheral SPI3 base address */
+#define SPI3_BASE                                (0x40089000u)
+/** Peripheral SPI3 base pointer */
+#define SPI3                                     ((SPI_Type *)SPI3_BASE)
+/** Peripheral SPI4 base address */
+#define SPI4_BASE                                (0x4008A000u)
+/** Peripheral SPI4 base pointer */
+#define SPI4                                     ((SPI_Type *)SPI4_BASE)
+/** Peripheral SPI5 base address */
+#define SPI5_BASE                                (0x40096000u)
+/** Peripheral SPI5 base pointer */
+#define SPI5                                     ((SPI_Type *)SPI5_BASE)
+/** Peripheral SPI6 base address */
+#define SPI6_BASE                                (0x40097000u)
+/** Peripheral SPI6 base pointer */
+#define SPI6                                     ((SPI_Type *)SPI6_BASE)
+/** Peripheral SPI7 base address */
+#define SPI7_BASE                                (0x40098000u)
+/** Peripheral SPI7 base pointer */
+#define SPI7                                     ((SPI_Type *)SPI7_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
+ * @{
+ */
+
+/** SPIFI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< SPIFI control register, offset: 0x0 */
+  __IO uint32_t CMD;                               /**< SPIFI command register, offset: 0x4 */
+  __IO uint32_t ADDR;                              /**< SPIFI address register, offset: 0x8 */
+  __IO uint32_t IDATA;                             /**< SPIFI intermediate data register, offset: 0xC */
+  __IO uint32_t CLIMIT;                            /**< SPIFI limit register, offset: 0x10 */
+  __IO uint32_t DATA;                              /**< SPIFI data register, offset: 0x14 */
+  __IO uint32_t MCMD;                              /**< SPIFI memory command register, offset: 0x18 */
+  __IO uint32_t STAT;                              /**< SPIFI status register, offset: 0x1C */
+} SPIFI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
+ * @{
+ */
+
+/*! @name CTRL - SPIFI control register */
+#define SPIFI_CTRL_TIMEOUT_MASK                  (0xFFFFU)
+#define SPIFI_CTRL_TIMEOUT_SHIFT                 (0U)
+#define SPIFI_CTRL_TIMEOUT(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
+#define SPIFI_CTRL_CSHIGH_MASK                   (0xF0000U)
+#define SPIFI_CTRL_CSHIGH_SHIFT                  (16U)
+#define SPIFI_CTRL_CSHIGH(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
+#define SPIFI_CTRL_D_PRFTCH_DIS_MASK             (0x200000U)
+#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT            (21U)
+#define SPIFI_CTRL_D_PRFTCH_DIS(x)               (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_INTEN_MASK                    (0x400000U)
+#define SPIFI_CTRL_INTEN_SHIFT                   (22U)
+#define SPIFI_CTRL_INTEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
+#define SPIFI_CTRL_MODE3_MASK                    (0x800000U)
+#define SPIFI_CTRL_MODE3_SHIFT                   (23U)
+#define SPIFI_CTRL_MODE3(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
+#define SPIFI_CTRL_PRFTCH_DIS_MASK               (0x8000000U)
+#define SPIFI_CTRL_PRFTCH_DIS_SHIFT              (27U)
+#define SPIFI_CTRL_PRFTCH_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_DUAL_MASK                     (0x10000000U)
+#define SPIFI_CTRL_DUAL_SHIFT                    (28U)
+#define SPIFI_CTRL_DUAL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
+#define SPIFI_CTRL_RFCLK_MASK                    (0x20000000U)
+#define SPIFI_CTRL_RFCLK_SHIFT                   (29U)
+#define SPIFI_CTRL_RFCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
+#define SPIFI_CTRL_FBCLK_MASK                    (0x40000000U)
+#define SPIFI_CTRL_FBCLK_SHIFT                   (30U)
+#define SPIFI_CTRL_FBCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
+#define SPIFI_CTRL_DMAEN_MASK                    (0x80000000U)
+#define SPIFI_CTRL_DMAEN_SHIFT                   (31U)
+#define SPIFI_CTRL_DMAEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
+
+/*! @name CMD - SPIFI command register */
+#define SPIFI_CMD_DATALEN_MASK                   (0x3FFFU)
+#define SPIFI_CMD_DATALEN_SHIFT                  (0U)
+#define SPIFI_CMD_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
+#define SPIFI_CMD_POLL_MASK                      (0x4000U)
+#define SPIFI_CMD_POLL_SHIFT                     (14U)
+#define SPIFI_CMD_POLL(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
+#define SPIFI_CMD_DOUT_MASK                      (0x8000U)
+#define SPIFI_CMD_DOUT_SHIFT                     (15U)
+#define SPIFI_CMD_DOUT(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
+#define SPIFI_CMD_INTLEN_MASK                    (0x70000U)
+#define SPIFI_CMD_INTLEN_SHIFT                   (16U)
+#define SPIFI_CMD_INTLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
+#define SPIFI_CMD_FIELDFORM_MASK                 (0x180000U)
+#define SPIFI_CMD_FIELDFORM_SHIFT                (19U)
+#define SPIFI_CMD_FIELDFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
+#define SPIFI_CMD_FRAMEFORM_MASK                 (0xE00000U)
+#define SPIFI_CMD_FRAMEFORM_SHIFT                (21U)
+#define SPIFI_CMD_FRAMEFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
+#define SPIFI_CMD_OPCODE_MASK                    (0xFF000000U)
+#define SPIFI_CMD_OPCODE_SHIFT                   (24U)
+#define SPIFI_CMD_OPCODE(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
+
+/*! @name ADDR - SPIFI address register */
+#define SPIFI_ADDR_ADDRESS_MASK                  (0xFFFFFFFFU)
+#define SPIFI_ADDR_ADDRESS_SHIFT                 (0U)
+#define SPIFI_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
+
+/*! @name IDATA - SPIFI intermediate data register */
+#define SPIFI_IDATA_IDATA_MASK                   (0xFFFFFFFFU)
+#define SPIFI_IDATA_IDATA_SHIFT                  (0U)
+#define SPIFI_IDATA_IDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
+
+/*! @name CLIMIT - SPIFI limit register */
+#define SPIFI_CLIMIT_CLIMIT_MASK                 (0xFFFFFFFFU)
+#define SPIFI_CLIMIT_CLIMIT_SHIFT                (0U)
+#define SPIFI_CLIMIT_CLIMIT(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
+
+/*! @name DATA - SPIFI data register */
+#define SPIFI_DATA_DATA_MASK                     (0xFFFFFFFFU)
+#define SPIFI_DATA_DATA_SHIFT                    (0U)
+#define SPIFI_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
+
+/*! @name MCMD - SPIFI memory command register */
+#define SPIFI_MCMD_POLL_MASK                     (0x4000U)
+#define SPIFI_MCMD_POLL_SHIFT                    (14U)
+#define SPIFI_MCMD_POLL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
+#define SPIFI_MCMD_DOUT_MASK                     (0x8000U)
+#define SPIFI_MCMD_DOUT_SHIFT                    (15U)
+#define SPIFI_MCMD_DOUT(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
+#define SPIFI_MCMD_INTLEN_MASK                   (0x70000U)
+#define SPIFI_MCMD_INTLEN_SHIFT                  (16U)
+#define SPIFI_MCMD_INTLEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
+#define SPIFI_MCMD_FIELDFORM_MASK                (0x180000U)
+#define SPIFI_MCMD_FIELDFORM_SHIFT               (19U)
+#define SPIFI_MCMD_FIELDFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
+#define SPIFI_MCMD_FRAMEFORM_MASK                (0xE00000U)
+#define SPIFI_MCMD_FRAMEFORM_SHIFT               (21U)
+#define SPIFI_MCMD_FRAMEFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
+#define SPIFI_MCMD_OPCODE_MASK                   (0xFF000000U)
+#define SPIFI_MCMD_OPCODE_SHIFT                  (24U)
+#define SPIFI_MCMD_OPCODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
+
+/*! @name STAT - SPIFI status register */
+#define SPIFI_STAT_MCINIT_MASK                   (0x1U)
+#define SPIFI_STAT_MCINIT_SHIFT                  (0U)
+#define SPIFI_STAT_MCINIT(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
+#define SPIFI_STAT_CMD_MASK                      (0x2U)
+#define SPIFI_STAT_CMD_SHIFT                     (1U)
+#define SPIFI_STAT_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
+#define SPIFI_STAT_RESET_MASK                    (0x10U)
+#define SPIFI_STAT_RESET_SHIFT                   (4U)
+#define SPIFI_STAT_RESET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
+#define SPIFI_STAT_INTRQ_MASK                    (0x20U)
+#define SPIFI_STAT_INTRQ_SHIFT                   (5U)
+#define SPIFI_STAT_INTRQ(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
+#define SPIFI_STAT_VERSION_MASK                  (0xFF000000U)
+#define SPIFI_STAT_VERSION_SHIFT                 (24U)
+#define SPIFI_STAT_VERSION(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_VERSION_SHIFT)) & SPIFI_STAT_VERSION_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Register_Masks */
+
+
+/* SPIFI - Peripheral instance base addresses */
+/** Peripheral SPIFI0 base address */
+#define SPIFI0_BASE                              (0x40080000u)
+/** Peripheral SPIFI0 base pointer */
+#define SPIFI0                                   ((SPIFI_Type *)SPIFI0_BASE)
+/** Array initializer of SPIFI peripheral base addresses */
+#define SPIFI_BASE_ADDRS                         { SPIFI0_BASE }
+/** Array initializer of SPIFI peripheral base pointers */
+#define SPIFI_BASE_PTRS                          { SPIFI0 }
+/** Interrupt vectors for the SPIFI peripheral type */
+#define SPIFI_IRQS                               { SPIFI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SYSMEMREMAP;                       /**< System Remap register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t AHBMATPRIO;                        /**< AHB multilayer matrix priority control, offset: 0x10 */
+       uint8_t RESERVED_1[44];
+  __IO uint32_t SYSTCKCAL;                         /**< System tick counter calibration, offset: 0x40 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
+  __IO uint32_t ASYNCAPBCTRL;                      /**< Asynchronous APB Control, offset: 0x4C */
+       uint8_t RESERVED_3[112];
+  __I  uint32_t PIOPORCAP[2];                      /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t PIORESCAP[2];                      /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
+       uint8_t RESERVED_5[40];
+  __IO uint32_t PRESETCTRL[2];                     /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __O  uint32_t PRESETCTRLSET[2];                  /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
+       uint8_t RESERVED_7[24];
+  __O  uint32_t PRESETCTRLCLR[2];                  /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
+       uint8_t RESERVED_8[168];
+  __IO uint32_t SYSRSTSTAT;                        /**< System reset status register, offset: 0x1F0 */
+       uint8_t RESERVED_9[12];
+  __IO uint32_t AHBCLKCTRL[2];                     /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_10[24];
+  __O  uint32_t AHBCLKCTRLSET[2];                  /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
+       uint8_t RESERVED_11[24];
+  __O  uint32_t AHBCLKCTRLCLR[2];                  /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
+       uint8_t RESERVED_12[56];
+  __IO uint32_t MAINCLKSELA;                       /**< Main clock source select A, offset: 0x280 */
+  __IO uint32_t MAINCLKSELB;                       /**< Main clock source select B, offset: 0x284 */
+  __IO uint32_t CLKOUTSELA;                        /**< CLKOUT clock source select A, offset: 0x288 */
+       uint8_t RESERVED_13[4];
+  __IO uint32_t SYSPLLCLKSEL;                      /**< PLL clock source select, offset: 0x290 */
+       uint8_t RESERVED_14[12];
+  __IO uint32_t SPIFICLKSEL;                       /**< SPIFI clock source select, offset: 0x2A0 */
+  __IO uint32_t ADCCLKSEL;                         /**< ADC clock source select, offset: 0x2A4 */
+  __IO uint32_t USBCLKSEL;                         /**< USB clock source select, offset: 0x2A8 */
+       uint8_t RESERVED_15[4];
+  __IO uint32_t FXCOMCLKSEL[8];                    /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */
+       uint8_t RESERVED_16[16];
+  __IO uint32_t MCLKCLKSEL;                        /**< MCLK clock source select, offset: 0x2E0 */
+       uint8_t RESERVED_17[4];
+  __IO uint32_t FRGCLKSEL;                         /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
+  __IO uint32_t DMICCLKSEL;                        /**< Digital microphone (D-Mic) subsystem clock select, offset: 0x2EC */
+       uint8_t RESERVED_18[16];
+  __IO uint32_t SYSTICKCLKDIV;                     /**< SYSTICK clock divider, offset: 0x300 */
+  __IO uint32_t TRACECLKDIV;                       /**< Trace clock divider, offset: 0x304 */
+       uint8_t RESERVED_19[120];
+  __IO uint32_t AHBCLKDIV;                         /**< AHB clock divider, offset: 0x380 */
+  __IO uint32_t CLKOUTDIV;                         /**< CLKOUT clock divider, offset: 0x384 */
+       uint8_t RESERVED_20[8];
+  __IO uint32_t SPIFICLKDIV;                       /**< SPIFI clock divider, offset: 0x390 */
+  __IO uint32_t ADCCLKDIV;                         /**< ADC clock divider, offset: 0x394 */
+  __IO uint32_t USBCLKDIV;                         /**< USB clock divider, offset: 0x398 */
+       uint8_t RESERVED_21[4];
+  __IO uint32_t FRGCTRL;                           /**< Fractional rate divider, offset: 0x3A0 */
+       uint8_t RESERVED_22[4];
+  __IO uint32_t DMICCLKDIV;                        /**< DMIC clock divider, offset: 0x3A8 */
+  __IO uint32_t MCLKDIV;                           /**< I2S MCLK clock divider, offset: 0x3AC */
+       uint8_t RESERVED_23[80];
+  __IO uint32_t FLASHCFG;                          /**< Flash wait states configuration, offset: 0x400 */
+       uint8_t RESERVED_24[8];
+  __IO uint32_t USBCLKCTRL;                        /**< USB clock control, offset: 0x40C */
+  __IO uint32_t USBCLKSTAT;                        /**< USB clock status, offset: 0x410 */
+       uint8_t RESERVED_25[4];
+  __IO uint32_t FREQMECTRL;                        /**< Frequency measure register, offset: 0x418 */
+       uint8_t RESERVED_26[4];
+  __IO uint32_t MCLKIO;                            /**< MCLK input/output control, offset: 0x420 */
+       uint8_t RESERVED_27[220];
+  __IO uint32_t FROCTRL;                           /**< FRO oscillator control, offset: 0x500 */
+       uint8_t RESERVED_28[4];
+  __IO uint32_t WDTOSCCTRL;                        /**< Watchdog oscillator control, offset: 0x508 */
+  __IO uint32_t RTCOSCCTRL;                        /**< RTC oscillator 32 kHz output control, offset: 0x50C */
+       uint8_t RESERVED_29[112];
+  __IO uint32_t SYSPLLCTRL;                        /**< PLL control, offset: 0x580 */
+  __I  uint32_t SYSPLLSTAT;                        /**< PLL status, offset: 0x584 */
+  __IO uint32_t SYSPLLNDEC;                        /**< PLL N decoder, offset: 0x588 */
+  __IO uint32_t SYSPLLPDEC;                        /**< PLL P decoder, offset: 0x58C */
+  __IO uint32_t SYSPLLSSCTRL0;                     /**< PLL spread spectrum control 0, offset: 0x590 */
+  __IO uint32_t SYSPLLSSCTRL1;                     /**< PLL spread spectrum control 1, offset: 0x594 */
+       uint8_t RESERVED_30[104];
+  __IO uint32_t PDSLEEPCFG[2];                     /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */
+       uint8_t RESERVED_31[8];
+  __IO uint32_t PDRUNCFG[2];                       /**< Power configuration register n, array offset: 0x610, array step: 0x4 */
+       uint8_t RESERVED_32[8];
+  __O  uint32_t PDRUNCFGSET[2];                    /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */
+       uint8_t RESERVED_33[8];
+  __O  uint32_t PDRUNCFGCLR[2];                    /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */
+       uint8_t RESERVED_34[72];
+  __IO uint32_t STARTERP[2];                       /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */
+       uint8_t RESERVED_35[24];
+  __O  uint32_t STARTERSET[2];                     /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */
+       uint8_t RESERVED_36[24];
+  __O  uint32_t STARTERCLR[2];                     /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */
+       uint8_t RESERVED_37[184];
+  __IO uint32_t HWWAKE;                            /**< Configures special cases of hardware wake-up, offset: 0x780 */
+       uint8_t RESERVED_38[124];
+  __IO uint32_t CPCTRL;                            /**< CPU Control for multiple processors, offset: 0x800 */
+  __IO uint32_t CPBOOT;                            /**< Coprocessor Boot Address, offset: 0x804 */
+  __IO uint32_t CPSTACK;                           /**< Coprocessor Stack Address, offset: 0x808 */
+  __I  uint32_t CPSTAT;                            /**< Coprocessor Status, offset: 0x80C */
+       uint8_t RESERVED_39[1524];
+  __IO uint32_t AUTOCGOR;                          /**< Auto Clock-Gate Override Register, offset: 0xE04 */
+       uint8_t RESERVED_40[492];
+  __I  uint32_t JTAGIDCODE;                        /**< JTAG ID code register, offset: 0xFF4 */
+  __I  uint32_t DEVICE_ID0;                        /**< Part ID register, offset: 0xFF8 */
+  __I  uint32_t DEVICE_ID1;                        /**< Boot ROM and die revision register, offset: 0xFFC */
+       uint8_t RESERVED_41[127044];
+  __IO uint32_t BODCTRL;                           /**< Brown-Out Detect control, offset: 0x20044 */
+} SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
+ * @{
+ */
+
+/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
+#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK         (0x3U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT        (0U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK         (0xCU)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT        (2U)
+#define SYSCON_AHBMATPRIO_PRI_DCODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SYS_MASK           (0x30U)
+#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT          (4U)
+#define SYSCON_AHBMATPRIO_PRI_SYS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
+#define SYSCON_AHBMATPRIO_PRI_M0_MASK            (0xC0U)
+#define SYSCON_AHBMATPRIO_PRI_M0_SHIFT           (6U)
+#define SYSCON_AHBMATPRIO_PRI_M0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB_MASK           (0x300U)
+#define SYSCON_AHBMATPRIO_PRI_USB_SHIFT          (8U)
+#define SYSCON_AHBMATPRIO_PRI_USB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DMA_MASK           (0xC00U)
+#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT          (10U)
+#define SYSCON_AHBMATPRIO_PRI_DMA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
+
+/*! @name SYSTCKCAL - System tick counter calibration */
+#define SYSCON_SYSTCKCAL_CAL_MASK                (0xFFFFFFU)
+#define SYSCON_SYSTCKCAL_CAL_SHIFT               (0U)
+#define SYSCON_SYSTCKCAL_CAL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
+#define SYSCON_SYSTCKCAL_SKEW_MASK               (0x1000000U)
+#define SYSCON_SYSTCKCAL_SKEW_SHIFT              (24U)
+#define SYSCON_SYSTCKCAL_SKEW(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
+#define SYSCON_SYSTCKCAL_NOREF_MASK              (0x2000000U)
+#define SYSCON_SYSTCKCAL_NOREF_SHIFT             (25U)
+#define SYSCON_SYSTCKCAL_NOREF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
+
+/*! @name NMISRC - NMI Source Select */
+#define SYSCON_NMISRC_IRQM4_MASK                 (0x3FU)
+#define SYSCON_NMISRC_IRQM4_SHIFT                (0U)
+#define SYSCON_NMISRC_IRQM4(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
+#define SYSCON_NMISRC_IRQM0_MASK                 (0x3F00U)
+#define SYSCON_NMISRC_IRQM0_SHIFT                (8U)
+#define SYSCON_NMISRC_IRQM0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK)
+#define SYSCON_NMISRC_NMIENM0_MASK               (0x40000000U)
+#define SYSCON_NMISRC_NMIENM0_SHIFT              (30U)
+#define SYSCON_NMISRC_NMIENM0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK)
+#define SYSCON_NMISRC_NMIENM4_MASK               (0x80000000U)
+#define SYSCON_NMISRC_NMIENM4_SHIFT              (31U)
+#define SYSCON_NMISRC_NMIENM4(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
+
+/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
+#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK          (0x1U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT         (0U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
+
+/*! @name PIOPORCAP - POR captured value of port n */
+#define SYSCON_PIOPORCAP_PIOPORCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT         (0U)
+#define SYSCON_PIOPORCAP_PIOPORCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
+
+/* The count of SYSCON_PIOPORCAP */
+#define SYSCON_PIOPORCAP_COUNT                   (2U)
+
+/*! @name PIORESCAP - Reset captured value of port n */
+#define SYSCON_PIORESCAP_PIORESCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIORESCAP_PIORESCAP_SHIFT         (0U)
+#define SYSCON_PIORESCAP_PIORESCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
+
+/* The count of SYSCON_PIORESCAP */
+#define SYSCON_PIORESCAP_COUNT                   (2U)
+
+/*! @name PRESETCTRL - Peripheral reset control n */
+#define SYSCON_PRESETCTRL_MRT0_RST_MASK          (0x1U)
+#define SYSCON_PRESETCTRL_MRT0_RST_SHIFT         (0U)
+#define SYSCON_PRESETCTRL_MRT0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK)
+#define SYSCON_PRESETCTRL_SCT0_RST_MASK          (0x4U)
+#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT         (2U)
+#define SYSCON_PRESETCTRL_SCT0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
+#define SYSCON_PRESETCTRL_FLASH_RST_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT        (7U)
+#define SYSCON_PRESETCTRL_FLASH_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)
+#define SYSCON_PRESETCTRL_FMC_RST_MASK           (0x100U)
+#define SYSCON_PRESETCTRL_FMC_RST_SHIFT          (8U)
+#define SYSCON_PRESETCTRL_FMC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)
+#define SYSCON_PRESETCTRL_UTICK0_RST_MASK        (0x400U)
+#define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT       (10U)
+#define SYSCON_PRESETCTRL_UTICK0_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK)
+#define SYSCON_PRESETCTRL_MUX_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_MUX_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_MUX_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
+#define SYSCON_PRESETCTRL_FC0_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_FC0_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_FC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
+#define SYSCON_PRESETCTRL_FC1_RST_MASK           (0x1000U)
+#define SYSCON_PRESETCTRL_FC1_RST_SHIFT          (12U)
+#define SYSCON_PRESETCTRL_FC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
+#define SYSCON_PRESETCTRL_FC2_RST_MASK           (0x2000U)
+#define SYSCON_PRESETCTRL_FC2_RST_SHIFT          (13U)
+#define SYSCON_PRESETCTRL_FC2_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
+#define SYSCON_PRESETCTRL_IOCON_RST_MASK         (0x2000U)
+#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT        (13U)
+#define SYSCON_PRESETCTRL_IOCON_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
+#define SYSCON_PRESETCTRL_FC3_RST_MASK           (0x4000U)
+#define SYSCON_PRESETCTRL_FC3_RST_SHIFT          (14U)
+#define SYSCON_PRESETCTRL_FC3_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO0_RST_MASK         (0x4000U)
+#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT        (14U)
+#define SYSCON_PRESETCTRL_GPIO0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
+#define SYSCON_PRESETCTRL_FC4_RST_MASK           (0x8000U)
+#define SYSCON_PRESETCTRL_FC4_RST_SHIFT          (15U)
+#define SYSCON_PRESETCTRL_FC4_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO1_RST_MASK         (0x8000U)
+#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT        (15U)
+#define SYSCON_PRESETCTRL_GPIO1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
+#define SYSCON_PRESETCTRL_FC5_RST_MASK           (0x10000U)
+#define SYSCON_PRESETCTRL_FC5_RST_SHIFT          (16U)
+#define SYSCON_PRESETCTRL_FC5_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
+#define SYSCON_PRESETCTRL_FC6_RST_MASK           (0x20000U)
+#define SYSCON_PRESETCTRL_FC6_RST_SHIFT          (17U)
+#define SYSCON_PRESETCTRL_FC6_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
+#define SYSCON_PRESETCTRL_FC7_RST_MASK           (0x40000U)
+#define SYSCON_PRESETCTRL_FC7_RST_SHIFT          (18U)
+#define SYSCON_PRESETCTRL_FC7_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
+#define SYSCON_PRESETCTRL_PINT_RST_MASK          (0x40000U)
+#define SYSCON_PRESETCTRL_PINT_RST_SHIFT         (18U)
+#define SYSCON_PRESETCTRL_PINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
+#define SYSCON_PRESETCTRL_GINT_RST_MASK          (0x80000U)
+#define SYSCON_PRESETCTRL_GINT_RST_SHIFT         (19U)
+#define SYSCON_PRESETCTRL_GINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
+#define SYSCON_PRESETCTRL_DMIC0_RST_MASK         (0x80000U)
+#define SYSCON_PRESETCTRL_DMIC0_RST_SHIFT        (19U)
+#define SYSCON_PRESETCTRL_DMIC0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC0_RST_MASK)
+#define SYSCON_PRESETCTRL_DMA0_RST_MASK          (0x100000U)
+#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT         (20U)
+#define SYSCON_PRESETCTRL_DMA0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)
+#define SYSCON_PRESETCTRL_CRC_RST_MASK           (0x200000U)
+#define SYSCON_PRESETCTRL_CRC_RST_SHIFT          (21U)
+#define SYSCON_PRESETCTRL_CRC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK       (0x400000U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT      (22U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
+#define SYSCON_PRESETCTRL_WWDT_RST_MASK          (0x400000U)
+#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT         (22U)
+#define SYSCON_PRESETCTRL_WWDT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0_RST_MASK          (0x2000000U)
+#define SYSCON_PRESETCTRL_USB0_RST_SHIFT         (25U)
+#define SYSCON_PRESETCTRL_USB0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK       (0x4000000U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT      (26U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK       (0x8000000U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT      (27U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
+#define SYSCON_PRESETCTRL_ADC0_RST_MASK          (0x8000000U)
+#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT         (27U)
+#define SYSCON_PRESETCTRL_ADC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
+
+/* The count of SYSCON_PRESETCTRL */
+#define SYSCON_PRESETCTRL_COUNT                  (2U)
+
+/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLSET_RST_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT       (0U)
+#define SYSCON_PRESETCTRLSET_RST_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
+
+/* The count of SYSCON_PRESETCTRLSET */
+#define SYSCON_PRESETCTRLSET_COUNT               (2U)
+
+/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT       (0U)
+#define SYSCON_PRESETCTRLCLR_RST_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
+
+/* The count of SYSCON_PRESETCTRLCLR */
+#define SYSCON_PRESETCTRLCLR_COUNT               (2U)
+
+/*! @name SYSRSTSTAT - System reset status register */
+#define SYSCON_SYSRSTSTAT_POR_MASK               (0x1U)
+#define SYSCON_SYSRSTSTAT_POR_SHIFT              (0U)
+#define SYSCON_SYSRSTSTAT_POR(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
+#define SYSCON_SYSRSTSTAT_EXTRST_MASK            (0x2U)
+#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT           (1U)
+#define SYSCON_SYSRSTSTAT_EXTRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
+#define SYSCON_SYSRSTSTAT_WDT_MASK               (0x4U)
+#define SYSCON_SYSRSTSTAT_WDT_SHIFT              (2U)
+#define SYSCON_SYSRSTSTAT_WDT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
+#define SYSCON_SYSRSTSTAT_BOD_MASK               (0x8U)
+#define SYSCON_SYSRSTSTAT_BOD_SHIFT              (3U)
+#define SYSCON_SYSRSTSTAT_BOD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
+#define SYSCON_SYSRSTSTAT_SYSRST_MASK            (0x10U)
+#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT           (4U)
+#define SYSCON_SYSRSTSTAT_SYSRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
+
+/*! @name AHBCLKCTRL - AHB Clock control n */
+#define SYSCON_AHBCLKCTRL_MRT0_MASK              (0x1U)
+#define SYSCON_AHBCLKCTRL_MRT0_SHIFT             (0U)
+#define SYSCON_AHBCLKCTRL_MRT0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK)
+#define SYSCON_AHBCLKCTRL_ROM_MASK               (0x2U)
+#define SYSCON_AHBCLKCTRL_ROM_SHIFT              (1U)
+#define SYSCON_AHBCLKCTRL_ROM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
+#define SYSCON_AHBCLKCTRL_SCT0_MASK              (0x4U)
+#define SYSCON_AHBCLKCTRL_SCT0_SHIFT             (2U)
+#define SYSCON_AHBCLKCTRL_SCT0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM1_MASK             (0x8U)
+#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT            (3U)
+#define SYSCON_AHBCLKCTRL_SRAM1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM2_MASK             (0x10U)
+#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT            (4U)
+#define SYSCON_AHBCLKCTRL_SRAM2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
+#define SYSCON_AHBCLKCTRL_FLASH_MASK             (0x80U)
+#define SYSCON_AHBCLKCTRL_FLASH_SHIFT            (7U)
+#define SYSCON_AHBCLKCTRL_FLASH(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)
+#define SYSCON_AHBCLKCTRL_FMC_MASK               (0x100U)
+#define SYSCON_AHBCLKCTRL_FMC_SHIFT              (8U)
+#define SYSCON_AHBCLKCTRL_FMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)
+#define SYSCON_AHBCLKCTRL_UTICK0_MASK            (0x400U)
+#define SYSCON_AHBCLKCTRL_UTICK0_SHIFT           (10U)
+#define SYSCON_AHBCLKCTRL_UTICK0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK         (0x800U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT        (11U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK          (0x800U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT         (11U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK         (0x1000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT        (12U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
+#define SYSCON_AHBCLKCTRL_IOCON_MASK             (0x2000U)
+#define SYSCON_AHBCLKCTRL_IOCON_SHIFT            (13U)
+#define SYSCON_AHBCLKCTRL_IOCON(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK         (0x2000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT        (13U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO0_MASK             (0x4000U)
+#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT            (14U)
+#define SYSCON_AHBCLKCTRL_GPIO0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK         (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT        (14U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK         (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT        (15U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO1_MASK             (0x8000U)
+#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT            (15U)
+#define SYSCON_AHBCLKCTRL_GPIO1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK         (0x10000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT        (16U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK         (0x20000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT        (17U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK         (0x40000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT        (18U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
+#define SYSCON_AHBCLKCTRL_PINT_MASK              (0x40000U)
+#define SYSCON_AHBCLKCTRL_PINT_SHIFT             (18U)
+#define SYSCON_AHBCLKCTRL_PINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
+#define SYSCON_AHBCLKCTRL_GINT_MASK              (0x80000U)
+#define SYSCON_AHBCLKCTRL_GINT_SHIFT             (19U)
+#define SYSCON_AHBCLKCTRL_GINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
+#define SYSCON_AHBCLKCTRL_DMIC0_MASK             (0x80000U)
+#define SYSCON_AHBCLKCTRL_DMIC0_SHIFT            (19U)
+#define SYSCON_AHBCLKCTRL_DMIC0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC0_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC0_MASK)
+#define SYSCON_AHBCLKCTRL_DMA0_MASK              (0x100000U)
+#define SYSCON_AHBCLKCTRL_DMA0_SHIFT             (20U)
+#define SYSCON_AHBCLKCTRL_DMA0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK)
+#define SYSCON_AHBCLKCTRL_CRC_MASK               (0x200000U)
+#define SYSCON_AHBCLKCTRL_CRC_SHIFT              (21U)
+#define SYSCON_AHBCLKCTRL_CRC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER2_MASK           (0x400000U)
+#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT          (22U)
+#define SYSCON_AHBCLKCTRL_CTIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
+#define SYSCON_AHBCLKCTRL_WWDT_MASK              (0x400000U)
+#define SYSCON_AHBCLKCTRL_WWDT_SHIFT             (22U)
+#define SYSCON_AHBCLKCTRL_WWDT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
+#define SYSCON_AHBCLKCTRL_RTC_MASK               (0x800000U)
+#define SYSCON_AHBCLKCTRL_RTC_SHIFT              (23U)
+#define SYSCON_AHBCLKCTRL_RTC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
+#define SYSCON_AHBCLKCTRL_USB0_MASK              (0x2000000U)
+#define SYSCON_AHBCLKCTRL_USB0_SHIFT             (25U)
+#define SYSCON_AHBCLKCTRL_USB0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER0_MASK           (0x4000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT          (26U)
+#define SYSCON_AHBCLKCTRL_CTIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
+#define SYSCON_AHBCLKCTRL_MAILBOX_MASK           (0x4000000U)
+#define SYSCON_AHBCLKCTRL_MAILBOX_SHIFT          (26U)
+#define SYSCON_AHBCLKCTRL_MAILBOX(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL_MAILBOX_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER1_MASK           (0x8000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT          (27U)
+#define SYSCON_AHBCLKCTRL_CTIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
+#define SYSCON_AHBCLKCTRL_ADC0_MASK              (0x8000000U)
+#define SYSCON_AHBCLKCTRL_ADC0_SHIFT             (27U)
+#define SYSCON_AHBCLKCTRL_ADC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
+
+/* The count of SYSCON_AHBCLKCTRL */
+#define SYSCON_AHBCLKCTRL_COUNT                  (2U)
+
+/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT       (0U)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLSET */
+#define SYSCON_AHBCLKCTRLSET_COUNT               (2U)
+
+/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT       (0U)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLCLR */
+#define SYSCON_AHBCLKCTRLCLR_COUNT               (2U)
+
+/*! @name MAINCLKSELA - Main clock source select A */
+#define SYSCON_MAINCLKSELA_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELA_SEL_SHIFT             (0U)
+#define SYSCON_MAINCLKSELA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
+
+/*! @name MAINCLKSELB - Main clock source select B */
+#define SYSCON_MAINCLKSELB_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELB_SEL_SHIFT             (0U)
+#define SYSCON_MAINCLKSELB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
+
+/*! @name CLKOUTSELA - CLKOUT clock source select A */
+#define SYSCON_CLKOUTSELA_SEL_MASK               (0x7U)
+#define SYSCON_CLKOUTSELA_SEL_SHIFT              (0U)
+#define SYSCON_CLKOUTSELA_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
+
+/*! @name SYSPLLCLKSEL - PLL clock source select */
+#define SYSCON_SYSPLLCLKSEL_SEL_MASK             (0x7U)
+#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT            (0U)
+#define SYSCON_SYSPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+
+/*! @name SPIFICLKSEL - SPIFI clock source select */
+#define SYSCON_SPIFICLKSEL_SEL_MASK              (0x7U)
+#define SYSCON_SPIFICLKSEL_SEL_SHIFT             (0U)
+#define SYSCON_SPIFICLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
+
+/*! @name ADCCLKSEL - ADC clock source select */
+#define SYSCON_ADCCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_ADCCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_ADCCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
+
+/*! @name USBCLKSEL - USB clock source select */
+#define SYSCON_USBCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_USBCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_USBCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK)
+
+/*! @name FXCOMCLKSEL - Flexcomm 0 clock source select */
+#define SYSCON_FXCOMCLKSEL_SEL_MASK              (0x7U)
+#define SYSCON_FXCOMCLKSEL_SEL_SHIFT             (0U)
+#define SYSCON_FXCOMCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK)
+
+/* The count of SYSCON_FXCOMCLKSEL */
+#define SYSCON_FXCOMCLKSEL_COUNT                 (8U)
+
+/*! @name MCLKCLKSEL - MCLK clock source select */
+#define SYSCON_MCLKCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_MCLKCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
+
+/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
+#define SYSCON_FRGCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_FRGCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_FRGCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
+
+/*! @name DMICCLKSEL - Digital microphone (D-Mic) subsystem clock select */
+#define SYSCON_DMICCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_DMICCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_DMICCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
+
+/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
+#define SYSCON_SYSTICKCLKDIV_DIV_MASK            (0xFFU)
+#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT           (0U)
+#define SYSCON_SYSTICKCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
+#define SYSCON_SYSTICKCLKDIV_RESET_MASK          (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT         (29U)
+#define SYSCON_SYSTICKCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
+#define SYSCON_SYSTICKCLKDIV_HALT_MASK           (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT          (30U)
+#define SYSCON_SYSTICKCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
+
+/*! @name TRACECLKDIV - Trace clock divider */
+#define SYSCON_TRACECLKDIV_DIV_MASK              (0xFFU)
+#define SYSCON_TRACECLKDIV_DIV_SHIFT             (0U)
+#define SYSCON_TRACECLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)
+#define SYSCON_TRACECLKDIV_RESET_MASK            (0x20000000U)
+#define SYSCON_TRACECLKDIV_RESET_SHIFT           (29U)
+#define SYSCON_TRACECLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)
+#define SYSCON_TRACECLKDIV_HALT_MASK             (0x40000000U)
+#define SYSCON_TRACECLKDIV_HALT_SHIFT            (30U)
+#define SYSCON_TRACECLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)
+
+/*! @name AHBCLKDIV - AHB clock divider */
+#define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+#define SYSCON_AHBCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_AHBCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_AHBCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK)
+#define SYSCON_AHBCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_AHBCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_AHBCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK)
+
+/*! @name CLKOUTDIV - CLKOUT clock divider */
+#define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
+#define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
+#define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
+#define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
+#define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
+#define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
+#define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
+
+/*! @name SPIFICLKDIV - SPIFI clock divider */
+#define SYSCON_SPIFICLKDIV_DIV_MASK              (0xFFU)
+#define SYSCON_SPIFICLKDIV_DIV_SHIFT             (0U)
+#define SYSCON_SPIFICLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
+#define SYSCON_SPIFICLKDIV_RESET_MASK            (0x20000000U)
+#define SYSCON_SPIFICLKDIV_RESET_SHIFT           (29U)
+#define SYSCON_SPIFICLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
+#define SYSCON_SPIFICLKDIV_HALT_MASK             (0x40000000U)
+#define SYSCON_SPIFICLKDIV_HALT_SHIFT            (30U)
+#define SYSCON_SPIFICLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
+
+/*! @name ADCCLKDIV - ADC clock divider */
+#define SYSCON_ADCCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_ADCCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_ADCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
+#define SYSCON_ADCCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_ADCCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_ADCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
+#define SYSCON_ADCCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_ADCCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_ADCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
+
+/*! @name USBCLKDIV - USB clock divider */
+#define SYSCON_USBCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_USBCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_USBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK)
+#define SYSCON_USBCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_USBCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_USBCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_RESET_SHIFT)) & SYSCON_USBCLKDIV_RESET_MASK)
+#define SYSCON_USBCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_USBCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_USBCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_HALT_SHIFT)) & SYSCON_USBCLKDIV_HALT_MASK)
+
+/*! @name FRGCTRL - Fractional rate divider */
+#define SYSCON_FRGCTRL_DIV_MASK                  (0xFFU)
+#define SYSCON_FRGCTRL_DIV_SHIFT                 (0U)
+#define SYSCON_FRGCTRL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
+#define SYSCON_FRGCTRL_MULT_MASK                 (0xFF00U)
+#define SYSCON_FRGCTRL_MULT_SHIFT                (8U)
+#define SYSCON_FRGCTRL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
+
+/*! @name DMICCLKDIV - DMIC clock divider */
+#define SYSCON_DMICCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_DMICCLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_DMICCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
+#define SYSCON_DMICCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_DMICCLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_DMICCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
+#define SYSCON_DMICCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_DMICCLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_DMICCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
+
+/*! @name MCLKDIV - I2S MCLK clock divider */
+#define SYSCON_MCLKDIV_DIV_MASK                  (0xFFU)
+#define SYSCON_MCLKDIV_DIV_SHIFT                 (0U)
+#define SYSCON_MCLKDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
+#define SYSCON_MCLKDIV_RESET_MASK                (0x20000000U)
+#define SYSCON_MCLKDIV_RESET_SHIFT               (29U)
+#define SYSCON_MCLKDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
+#define SYSCON_MCLKDIV_HALT_MASK                 (0x40000000U)
+#define SYSCON_MCLKDIV_HALT_SHIFT                (30U)
+#define SYSCON_MCLKDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
+
+/*! @name FLASHCFG - Flash wait states configuration */
+#define SYSCON_FLASHCFG_FETCHCFG_MASK            (0x3U)
+#define SYSCON_FLASHCFG_FETCHCFG_SHIFT           (0U)
+#define SYSCON_FLASHCFG_FETCHCFG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)
+#define SYSCON_FLASHCFG_DATACFG_MASK             (0xCU)
+#define SYSCON_FLASHCFG_DATACFG_SHIFT            (2U)
+#define SYSCON_FLASHCFG_DATACFG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)
+#define SYSCON_FLASHCFG_ACCEL_MASK               (0x10U)
+#define SYSCON_FLASHCFG_ACCEL_SHIFT              (4U)
+#define SYSCON_FLASHCFG_ACCEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)
+#define SYSCON_FLASHCFG_PREFEN_MASK              (0x20U)
+#define SYSCON_FLASHCFG_PREFEN_SHIFT             (5U)
+#define SYSCON_FLASHCFG_PREFEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)
+#define SYSCON_FLASHCFG_PREFOVR_MASK             (0x40U)
+#define SYSCON_FLASHCFG_PREFOVR_SHIFT            (6U)
+#define SYSCON_FLASHCFG_PREFOVR(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)
+#define SYSCON_FLASHCFG_FLASHTIM_MASK            (0xF000U)
+#define SYSCON_FLASHCFG_FLASHTIM_SHIFT           (12U)
+#define SYSCON_FLASHCFG_FLASHTIM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)
+
+/*! @name USBCLKCTRL - USB clock control */
+#define SYSCON_USBCLKCTRL_POL_CLK_MASK           (0x2U)
+#define SYSCON_USBCLKCTRL_POL_CLK_SHIFT          (1U)
+#define SYSCON_USBCLKCTRL_POL_CLK(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK)
+
+/*! @name USBCLKSTAT - USB clock status */
+#define SYSCON_USBCLKSTAT_NEED_CLKST_MASK        (0x1U)
+#define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT       (0U)
+#define SYSCON_USBCLKSTAT_NEED_CLKST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK)
+
+/*! @name FREQMECTRL - Frequency measure register */
+#define SYSCON_FREQMECTRL_CAPVAL_MASK            (0x3FFFU)
+#define SYSCON_FREQMECTRL_CAPVAL_SHIFT           (0U)
+#define SYSCON_FREQMECTRL_CAPVAL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
+#define SYSCON_FREQMECTRL_PROG_MASK              (0x80000000U)
+#define SYSCON_FREQMECTRL_PROG_SHIFT             (31U)
+#define SYSCON_FREQMECTRL_PROG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
+
+/*! @name MCLKIO - MCLK input/output control */
+#define SYSCON_MCLKIO_DIR_MASK                   (0x1U)
+#define SYSCON_MCLKIO_DIR_SHIFT                  (0U)
+#define SYSCON_MCLKIO_DIR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
+
+/*! @name FROCTRL - FRO oscillator control */
+#define SYSCON_FROCTRL_TRIM_MASK                 (0x3FFFU)
+#define SYSCON_FROCTRL_TRIM_SHIFT                (0U)
+#define SYSCON_FROCTRL_TRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)
+#define SYSCON_FROCTRL_SEL_MASK                  (0x4000U)
+#define SYSCON_FROCTRL_SEL_SHIFT                 (14U)
+#define SYSCON_FROCTRL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
+#define SYSCON_FROCTRL_FREQTRIM_MASK             (0xFF0000U)
+#define SYSCON_FROCTRL_FREQTRIM_SHIFT            (16U)
+#define SYSCON_FROCTRL_FREQTRIM(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
+#define SYSCON_FROCTRL_USBCLKADJ_MASK            (0x1000000U)
+#define SYSCON_FROCTRL_USBCLKADJ_SHIFT           (24U)
+#define SYSCON_FROCTRL_USBCLKADJ(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
+#define SYSCON_FROCTRL_USBMODCHG_MASK            (0x2000000U)
+#define SYSCON_FROCTRL_USBMODCHG_SHIFT           (25U)
+#define SYSCON_FROCTRL_USBMODCHG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
+#define SYSCON_FROCTRL_HSPDCLK_MASK              (0x40000000U)
+#define SYSCON_FROCTRL_HSPDCLK_SHIFT             (30U)
+#define SYSCON_FROCTRL_HSPDCLK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
+#define SYSCON_FROCTRL_WRTRIM_MASK               (0x80000000U)
+#define SYSCON_FROCTRL_WRTRIM_SHIFT              (31U)
+#define SYSCON_FROCTRL_WRTRIM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)
+
+/*! @name WDTOSCCTRL - Watchdog oscillator control */
+#define SYSCON_WDTOSCCTRL_DIVSEL_MASK            (0x1FU)
+#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT           (0U)
+#define SYSCON_WDTOSCCTRL_DIVSEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
+#define SYSCON_WDTOSCCTRL_FREQSEL_MASK           (0x3E0U)
+#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT          (5U)
+#define SYSCON_WDTOSCCTRL_FREQSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
+
+/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
+#define SYSCON_RTCOSCCTRL_EN_MASK                (0x1U)
+#define SYSCON_RTCOSCCTRL_EN_SHIFT               (0U)
+#define SYSCON_RTCOSCCTRL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
+
+/*! @name SYSPLLCTRL - PLL control */
+#define SYSCON_SYSPLLCTRL_SELR_MASK              (0xFU)
+#define SYSCON_SYSPLLCTRL_SELR_SHIFT             (0U)
+#define SYSCON_SYSPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
+#define SYSCON_SYSPLLCTRL_SELI_MASK              (0x3F0U)
+#define SYSCON_SYSPLLCTRL_SELI_SHIFT             (4U)
+#define SYSCON_SYSPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
+#define SYSCON_SYSPLLCTRL_SELP_MASK              (0x7C00U)
+#define SYSCON_SYSPLLCTRL_SELP_SHIFT             (10U)
+#define SYSCON_SYSPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
+#define SYSCON_SYSPLLCTRL_BYPASS_MASK            (0x8000U)
+#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT           (15U)
+#define SYSCON_SYSPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
+#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK     (0x10000U)
+#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT    (16U)
+#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK          (0x20000U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT         (17U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_SYSPLLCTRL_BANDSEL_MASK           (0x40000U)
+#define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT          (18U)
+#define SYSCON_SYSPLLCTRL_BANDSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTI_MASK           (0x80000U)
+#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT          (19U)
+#define SYSCON_SYSPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTO_MASK           (0x100000U)
+#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT          (20U)
+#define SYSCON_SYSPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
+
+/*! @name SYSPLLSTAT - PLL status */
+#define SYSCON_SYSPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_SYSPLLSTAT_LOCK_SHIFT             (0U)
+#define SYSCON_SYSPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
+
+/*! @name SYSPLLNDEC - PLL N decoder */
+#define SYSCON_SYSPLLNDEC_NDEC_MASK              (0x3FFU)
+#define SYSCON_SYSPLLNDEC_NDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
+#define SYSCON_SYSPLLNDEC_NREQ_MASK              (0x400U)
+#define SYSCON_SYSPLLNDEC_NREQ_SHIFT             (10U)
+#define SYSCON_SYSPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
+
+/*! @name SYSPLLPDEC - PLL P decoder */
+#define SYSCON_SYSPLLPDEC_PDEC_MASK              (0x7FU)
+#define SYSCON_SYSPLLPDEC_PDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
+#define SYSCON_SYSPLLPDEC_PREQ_MASK              (0x80U)
+#define SYSCON_SYSPLLPDEC_PREQ_SHIFT             (7U)
+#define SYSCON_SYSPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
+
+/*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */
+#define SYSCON_SYSPLLSSCTRL0_MDEC_MASK           (0x1FFFFU)
+#define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT          (0U)
+#define SYSCON_SYSPLLSSCTRL0_MDEC(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK)
+#define SYSCON_SYSPLLSSCTRL0_MREQ_MASK           (0x20000U)
+#define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT          (17U)
+#define SYSCON_SYSPLLSSCTRL0_MREQ(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK)
+#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK        (0x40000U)
+#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT       (18U)
+#define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK)
+
+/*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */
+#define SYSCON_SYSPLLSSCTRL1_MD_MASK             (0x7FFFFU)
+#define SYSCON_SYSPLLSSCTRL1_MD_SHIFT            (0U)
+#define SYSCON_SYSPLLSSCTRL1_MD(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK)
+#define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK          (0x80000U)
+#define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT         (19U)
+#define SYSCON_SYSPLLSSCTRL1_MDREQ(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK)
+#define SYSCON_SYSPLLSSCTRL1_MF_MASK             (0x700000U)
+#define SYSCON_SYSPLLSSCTRL1_MF_SHIFT            (20U)
+#define SYSCON_SYSPLLSSCTRL1_MF(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK)
+#define SYSCON_SYSPLLSSCTRL1_MR_MASK             (0x3800000U)
+#define SYSCON_SYSPLLSSCTRL1_MR_SHIFT            (23U)
+#define SYSCON_SYSPLLSSCTRL1_MR(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK)
+#define SYSCON_SYSPLLSSCTRL1_MC_MASK             (0xC000000U)
+#define SYSCON_SYSPLLSSCTRL1_MC_SHIFT            (26U)
+#define SYSCON_SYSPLLSSCTRL1_MC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK)
+#define SYSCON_SYSPLLSSCTRL1_PD_MASK             (0x10000000U)
+#define SYSCON_SYSPLLSSCTRL1_PD_SHIFT            (28U)
+#define SYSCON_SYSPLLSSCTRL1_PD(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK)
+#define SYSCON_SYSPLLSSCTRL1_DITHER_MASK         (0x20000000U)
+#define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT        (29U)
+#define SYSCON_SYSPLLSSCTRL1_DITHER(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK)
+
+/*! @name PDSLEEPCFG - Sleep configuration register n */
+#define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT         (0U)
+#define SYSCON_PDSLEEPCFG_PD_SLEEP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK)
+
+/* The count of SYSCON_PDSLEEPCFG */
+#define SYSCON_PDSLEEPCFG_COUNT                  (2U)
+
+/*! @name PDRUNCFG - Power configuration register n */
+#define SYSCON_PDRUNCFG_PDEN_FRO_MASK            (0x10U)
+#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT           (4U)
+#define SYSCON_PDRUNCFG_PDEN_FRO(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFG_PD_FLASH_MASK            (0x20U)
+#define SYSCON_PDRUNCFG_PD_FLASH_SHIFT           (5U)
+#define SYSCON_PDRUNCFG_PD_FLASH(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_MASK)
+#define SYSCON_PDRUNCFG_PDEN_TS_MASK             (0x40U)
+#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT            (6U)
+#define SYSCON_PDRUNCFG_PDEN_TS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK        (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT       (7U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK       (0x100U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT      (8U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK           (0x400U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT          (10U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFG_PD_VDDFLASH_MASK         (0x800U)
+#define SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT        (11U)
+#define SYSCON_PDRUNCFG_PD_VDDFLASH(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDFLASH_MASK)
+#define SYSCON_PDRUNCFG_LP_VDDFLASH_MASK         (0x1000U)
+#define SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT        (12U)
+#define SYSCON_PDRUNCFG_LP_VDDFLASH(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LP_VDDFLASH_SHIFT)) & SYSCON_PDRUNCFG_LP_VDDFLASH_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK          (0x2000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT         (13U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_MASK          (0x4000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT         (14U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM2_MASK          (0x8000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT         (15U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM2_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM2_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK          (0x10000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT         (16U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ROM_MASK            (0x20000U)
+#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT           (17U)
+#define SYSCON_PDRUNCFG_PDEN_ROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK        (0x40000U)
+#define SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT       (18U)
+#define SYSCON_PDRUNCFG_PD_VDDHV_ENA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_VDDHV_ENA_SHIFT)) & SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK           (0x80000U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT          (19U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK        (0x100000U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT       (20U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK        (0x200000U)
+#define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT       (21U)
+#define SYSCON_PDRUNCFG_PDEN_USB_PHY(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK        (0x400000U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT       (22U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK          (0x800000U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT         (23U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFG_PD_FLASH_BG_MASK         (0x2000000U)
+#define SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT        (25U)
+#define SYSCON_PDRUNCFG_PD_FLASH_BG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_FLASH_BG_SHIFT)) & SYSCON_PDRUNCFG_PD_FLASH_BG_MASK)
+#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK    (0x10000000U)
+#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT   (28U)
+#define SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_PD_ALT_FLASH_IBG_MASK)
+#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK   (0x20000000U)
+#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT  (29U)
+#define SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_SHIFT)) & SYSCON_PDRUNCFG_SEL_ALT_FLASH_IBG_MASK)
+
+/* The count of SYSCON_PDRUNCFG */
+#define SYSCON_PDRUNCFG_COUNT                    (2U)
+
+/*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */
+#define SYSCON_PDRUNCFGSET_PD_SET_MASK           (0xFFFFFFFFU)
+#define SYSCON_PDRUNCFGSET_PD_SET_SHIFT          (0U)
+#define SYSCON_PDRUNCFGSET_PD_SET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK)
+
+/* The count of SYSCON_PDRUNCFGSET */
+#define SYSCON_PDRUNCFGSET_COUNT                 (2U)
+
+/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */
+#define SYSCON_PDRUNCFGCLR_PD_CLR_MASK           (0xFFFFFFFFU)
+#define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT          (0U)
+#define SYSCON_PDRUNCFGCLR_PD_CLR(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK)
+
+/* The count of SYSCON_PDRUNCFGCLR */
+#define SYSCON_PDRUNCFGCLR_COUNT                 (2U)
+
+/*! @name STARTERP - Start logic n wake-up enable register */
+#define SYSCON_STARTERP_WDT_BOD_MASK             (0x1U)
+#define SYSCON_STARTERP_WDT_BOD_SHIFT            (0U)
+#define SYSCON_STARTERP_WDT_BOD(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_WDT_BOD_SHIFT)) & SYSCON_STARTERP_WDT_BOD_MASK)
+#define SYSCON_STARTERP_PINT4_MASK               (0x1U)
+#define SYSCON_STARTERP_PINT4_SHIFT              (0U)
+#define SYSCON_STARTERP_PINT4(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT4_SHIFT)) & SYSCON_STARTERP_PINT4_MASK)
+#define SYSCON_STARTERP_PINT5_MASK               (0x2U)
+#define SYSCON_STARTERP_PINT5_SHIFT              (1U)
+#define SYSCON_STARTERP_PINT5(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT5_SHIFT)) & SYSCON_STARTERP_PINT5_MASK)
+#define SYSCON_STARTERP_DMA0_MASK                (0x2U)
+#define SYSCON_STARTERP_DMA0_SHIFT               (1U)
+#define SYSCON_STARTERP_DMA0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMA0_SHIFT)) & SYSCON_STARTERP_DMA0_MASK)
+#define SYSCON_STARTERP_GINT0_MASK               (0x4U)
+#define SYSCON_STARTERP_GINT0_SHIFT              (2U)
+#define SYSCON_STARTERP_GINT0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT0_SHIFT)) & SYSCON_STARTERP_GINT0_MASK)
+#define SYSCON_STARTERP_PINT6_MASK               (0x4U)
+#define SYSCON_STARTERP_PINT6_SHIFT              (2U)
+#define SYSCON_STARTERP_PINT6(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT6_SHIFT)) & SYSCON_STARTERP_PINT6_MASK)
+#define SYSCON_STARTERP_GINT1_MASK               (0x8U)
+#define SYSCON_STARTERP_GINT1_SHIFT              (3U)
+#define SYSCON_STARTERP_GINT1(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_GINT1_SHIFT)) & SYSCON_STARTERP_GINT1_MASK)
+#define SYSCON_STARTERP_PINT7_MASK               (0x8U)
+#define SYSCON_STARTERP_PINT7_SHIFT              (3U)
+#define SYSCON_STARTERP_PINT7(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PINT7_SHIFT)) & SYSCON_STARTERP_PINT7_MASK)
+#define SYSCON_STARTERP_CTIMER2_MASK             (0x10U)
+#define SYSCON_STARTERP_CTIMER2_SHIFT            (4U)
+#define SYSCON_STARTERP_CTIMER2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER2_SHIFT)) & SYSCON_STARTERP_CTIMER2_MASK)
+#define SYSCON_STARTERP_PIN_INT0_MASK            (0x10U)
+#define SYSCON_STARTERP_PIN_INT0_SHIFT           (4U)
+#define SYSCON_STARTERP_PIN_INT0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT0_SHIFT)) & SYSCON_STARTERP_PIN_INT0_MASK)
+#define SYSCON_STARTERP_PIN_INT1_MASK            (0x20U)
+#define SYSCON_STARTERP_PIN_INT1_SHIFT           (5U)
+#define SYSCON_STARTERP_PIN_INT1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT1_SHIFT)) & SYSCON_STARTERP_PIN_INT1_MASK)
+#define SYSCON_STARTERP_CTIMER4_MASK             (0x20U)
+#define SYSCON_STARTERP_CTIMER4_SHIFT            (5U)
+#define SYSCON_STARTERP_CTIMER4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER4_SHIFT)) & SYSCON_STARTERP_CTIMER4_MASK)
+#define SYSCON_STARTERP_PIN_INT2_MASK            (0x40U)
+#define SYSCON_STARTERP_PIN_INT2_SHIFT           (6U)
+#define SYSCON_STARTERP_PIN_INT2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT2_SHIFT)) & SYSCON_STARTERP_PIN_INT2_MASK)
+#define SYSCON_STARTERP_PIN_INT3_MASK            (0x80U)
+#define SYSCON_STARTERP_PIN_INT3_SHIFT           (7U)
+#define SYSCON_STARTERP_PIN_INT3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_PIN_INT3_SHIFT)) & SYSCON_STARTERP_PIN_INT3_MASK)
+#define SYSCON_STARTERP_UTICK0_MASK              (0x100U)
+#define SYSCON_STARTERP_UTICK0_SHIFT             (8U)
+#define SYSCON_STARTERP_UTICK0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_UTICK0_SHIFT)) & SYSCON_STARTERP_UTICK0_MASK)
+#define SYSCON_STARTERP_MRT0_MASK                (0x200U)
+#define SYSCON_STARTERP_MRT0_SHIFT               (9U)
+#define SYSCON_STARTERP_MRT0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MRT0_SHIFT)) & SYSCON_STARTERP_MRT0_MASK)
+#define SYSCON_STARTERP_CTIMER0_MASK             (0x400U)
+#define SYSCON_STARTERP_CTIMER0_SHIFT            (10U)
+#define SYSCON_STARTERP_CTIMER0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER0_SHIFT)) & SYSCON_STARTERP_CTIMER0_MASK)
+#define SYSCON_STARTERP_CTIMER1_MASK             (0x800U)
+#define SYSCON_STARTERP_CTIMER1_SHIFT            (11U)
+#define SYSCON_STARTERP_CTIMER1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER1_SHIFT)) & SYSCON_STARTERP_CTIMER1_MASK)
+#define SYSCON_STARTERP_SCT0_MASK                (0x1000U)
+#define SYSCON_STARTERP_SCT0_SHIFT               (12U)
+#define SYSCON_STARTERP_SCT0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_SCT0_SHIFT)) & SYSCON_STARTERP_SCT0_MASK)
+#define SYSCON_STARTERP_CTIMER3_MASK             (0x2000U)
+#define SYSCON_STARTERP_CTIMER3_SHIFT            (13U)
+#define SYSCON_STARTERP_CTIMER3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_CTIMER3_SHIFT)) & SYSCON_STARTERP_CTIMER3_MASK)
+#define SYSCON_STARTERP_FLEXCOMM0_MASK           (0x4000U)
+#define SYSCON_STARTERP_FLEXCOMM0_SHIFT          (14U)
+#define SYSCON_STARTERP_FLEXCOMM0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM0_SHIFT)) & SYSCON_STARTERP_FLEXCOMM0_MASK)
+#define SYSCON_STARTERP_FLEXCOMM1_MASK           (0x8000U)
+#define SYSCON_STARTERP_FLEXCOMM1_SHIFT          (15U)
+#define SYSCON_STARTERP_FLEXCOMM1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM1_SHIFT)) & SYSCON_STARTERP_FLEXCOMM1_MASK)
+#define SYSCON_STARTERP_FLEXCOMM2_MASK           (0x10000U)
+#define SYSCON_STARTERP_FLEXCOMM2_SHIFT          (16U)
+#define SYSCON_STARTERP_FLEXCOMM2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM2_SHIFT)) & SYSCON_STARTERP_FLEXCOMM2_MASK)
+#define SYSCON_STARTERP_FLEXCOMM3_MASK           (0x20000U)
+#define SYSCON_STARTERP_FLEXCOMM3_SHIFT          (17U)
+#define SYSCON_STARTERP_FLEXCOMM3(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM3_SHIFT)) & SYSCON_STARTERP_FLEXCOMM3_MASK)
+#define SYSCON_STARTERP_FLEXCOMM4_MASK           (0x40000U)
+#define SYSCON_STARTERP_FLEXCOMM4_SHIFT          (18U)
+#define SYSCON_STARTERP_FLEXCOMM4(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM4_SHIFT)) & SYSCON_STARTERP_FLEXCOMM4_MASK)
+#define SYSCON_STARTERP_FLEXCOMM5_MASK           (0x80000U)
+#define SYSCON_STARTERP_FLEXCOMM5_SHIFT          (19U)
+#define SYSCON_STARTERP_FLEXCOMM5(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM5_SHIFT)) & SYSCON_STARTERP_FLEXCOMM5_MASK)
+#define SYSCON_STARTERP_FLEXCOMM6_MASK           (0x100000U)
+#define SYSCON_STARTERP_FLEXCOMM6_SHIFT          (20U)
+#define SYSCON_STARTERP_FLEXCOMM6(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM6_SHIFT)) & SYSCON_STARTERP_FLEXCOMM6_MASK)
+#define SYSCON_STARTERP_FLEXCOMM7_MASK           (0x200000U)
+#define SYSCON_STARTERP_FLEXCOMM7_SHIFT          (21U)
+#define SYSCON_STARTERP_FLEXCOMM7(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_FLEXCOMM7_SHIFT)) & SYSCON_STARTERP_FLEXCOMM7_MASK)
+#define SYSCON_STARTERP_ADC0_SEQA_MASK           (0x400000U)
+#define SYSCON_STARTERP_ADC0_SEQA_SHIFT          (22U)
+#define SYSCON_STARTERP_ADC0_SEQA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQA_SHIFT)) & SYSCON_STARTERP_ADC0_SEQA_MASK)
+#define SYSCON_STARTERP_ADC0_SEQB_MASK           (0x800000U)
+#define SYSCON_STARTERP_ADC0_SEQB_SHIFT          (23U)
+#define SYSCON_STARTERP_ADC0_SEQB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_SEQB_SHIFT)) & SYSCON_STARTERP_ADC0_SEQB_MASK)
+#define SYSCON_STARTERP_ADC0_THCMP_MASK          (0x1000000U)
+#define SYSCON_STARTERP_ADC0_THCMP_SHIFT         (24U)
+#define SYSCON_STARTERP_ADC0_THCMP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_ADC0_THCMP_SHIFT)) & SYSCON_STARTERP_ADC0_THCMP_MASK)
+#define SYSCON_STARTERP_DMIC0_MASK               (0x2000000U)
+#define SYSCON_STARTERP_DMIC0_SHIFT              (25U)
+#define SYSCON_STARTERP_DMIC0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_DMIC0_SHIFT)) & SYSCON_STARTERP_DMIC0_MASK)
+#define SYSCON_STARTERP_USB0_NEEDCLK_MASK        (0x8000000U)
+#define SYSCON_STARTERP_USB0_NEEDCLK_SHIFT       (27U)
+#define SYSCON_STARTERP_USB0_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTERP_USB0_NEEDCLK_MASK)
+#define SYSCON_STARTERP_USB0_MASK                (0x10000000U)
+#define SYSCON_STARTERP_USB0_SHIFT               (28U)
+#define SYSCON_STARTERP_USB0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_USB0_SHIFT)) & SYSCON_STARTERP_USB0_MASK)
+#define SYSCON_STARTERP_RTC_MASK                 (0x20000000U)
+#define SYSCON_STARTERP_RTC_SHIFT                (29U)
+#define SYSCON_STARTERP_RTC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_RTC_SHIFT)) & SYSCON_STARTERP_RTC_MASK)
+#define SYSCON_STARTERP_MAILBOX_MASK             (0x80000000U)
+#define SYSCON_STARTERP_MAILBOX_SHIFT            (31U)
+#define SYSCON_STARTERP_MAILBOX(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP_MAILBOX_SHIFT)) & SYSCON_STARTERP_MAILBOX_MASK)
+
+/* The count of SYSCON_STARTERP */
+#define SYSCON_STARTERP_COUNT                    (2U)
+
+/*! @name STARTERSET - Set bits in STARTERn */
+#define SYSCON_STARTERSET_START_SET_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERSET_START_SET_SHIFT        (0U)
+#define SYSCON_STARTERSET_START_SET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
+
+/* The count of SYSCON_STARTERSET */
+#define SYSCON_STARTERSET_COUNT                  (2U)
+
+/*! @name STARTERCLR - Clear bits in STARTERn */
+#define SYSCON_STARTERCLR_START_CLR_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERCLR_START_CLR_SHIFT        (0U)
+#define SYSCON_STARTERCLR_START_CLR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
+
+/* The count of SYSCON_STARTERCLR */
+#define SYSCON_STARTERCLR_COUNT                  (2U)
+
+/*! @name HWWAKE - Configures special cases of hardware wake-up */
+#define SYSCON_HWWAKE_FORCEWAKE_MASK             (0x1U)
+#define SYSCON_HWWAKE_FORCEWAKE_SHIFT            (0U)
+#define SYSCON_HWWAKE_FORCEWAKE(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
+#define SYSCON_HWWAKE_FCWAKE_MASK                (0x2U)
+#define SYSCON_HWWAKE_FCWAKE_SHIFT               (1U)
+#define SYSCON_HWWAKE_FCWAKE(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
+#define SYSCON_HWWAKE_WAKEDMIC_MASK              (0x4U)
+#define SYSCON_HWWAKE_WAKEDMIC_SHIFT             (2U)
+#define SYSCON_HWWAKE_WAKEDMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
+#define SYSCON_HWWAKE_WAKEDMA_MASK               (0x8U)
+#define SYSCON_HWWAKE_WAKEDMA_SHIFT              (3U)
+#define SYSCON_HWWAKE_WAKEDMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
+
+/*! @name CPCTRL - CPU Control for multiple processors */
+#define SYSCON_CPCTRL_MASTERCPU_MASK             (0x1U)
+#define SYSCON_CPCTRL_MASTERCPU_SHIFT            (0U)
+#define SYSCON_CPCTRL_MASTERCPU(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_MASTERCPU_SHIFT)) & SYSCON_CPCTRL_MASTERCPU_MASK)
+#define SYSCON_CPCTRL_CM4CLKEN_MASK              (0x4U)
+#define SYSCON_CPCTRL_CM4CLKEN_SHIFT             (2U)
+#define SYSCON_CPCTRL_CM4CLKEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4CLKEN_SHIFT)) & SYSCON_CPCTRL_CM4CLKEN_MASK)
+#define SYSCON_CPCTRL_CM0CLKEN_MASK              (0x8U)
+#define SYSCON_CPCTRL_CM0CLKEN_SHIFT             (3U)
+#define SYSCON_CPCTRL_CM0CLKEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0CLKEN_SHIFT)) & SYSCON_CPCTRL_CM0CLKEN_MASK)
+#define SYSCON_CPCTRL_CM4RSTEN_MASK              (0x10U)
+#define SYSCON_CPCTRL_CM4RSTEN_SHIFT             (4U)
+#define SYSCON_CPCTRL_CM4RSTEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM4RSTEN_SHIFT)) & SYSCON_CPCTRL_CM4RSTEN_MASK)
+#define SYSCON_CPCTRL_CM0RSTEN_MASK              (0x20U)
+#define SYSCON_CPCTRL_CM0RSTEN_SHIFT             (5U)
+#define SYSCON_CPCTRL_CM0RSTEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_CM0RSTEN_SHIFT)) & SYSCON_CPCTRL_CM0RSTEN_MASK)
+#define SYSCON_CPCTRL_POWERCPU_MASK              (0x40U)
+#define SYSCON_CPCTRL_POWERCPU_SHIFT             (6U)
+#define SYSCON_CPCTRL_POWERCPU(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CPCTRL_POWERCPU_SHIFT)) & SYSCON_CPCTRL_POWERCPU_MASK)
+
+/*! @name CPBOOT - Coprocessor Boot Address */
+#define SYSCON_CPBOOT_BOOTADDR_MASK              (0xFFFFFFFFU)
+#define SYSCON_CPBOOT_BOOTADDR_SHIFT             (0U)
+#define SYSCON_CPBOOT_BOOTADDR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_BOOTADDR_SHIFT)) & SYSCON_CPBOOT_BOOTADDR_MASK)
+
+/*! @name CPSTACK - Coprocessor Stack Address */
+#define SYSCON_CPSTACK_STACKADDR_MASK            (0xFFFFFFFFU)
+#define SYSCON_CPSTACK_STACKADDR_SHIFT           (0U)
+#define SYSCON_CPSTACK_STACKADDR(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_STACKADDR_SHIFT)) & SYSCON_CPSTACK_STACKADDR_MASK)
+
+/*! @name CPSTAT - Coprocessor Status */
+#define SYSCON_CPSTAT_CM4SLEEPING_MASK           (0x1U)
+#define SYSCON_CPSTAT_CM4SLEEPING_SHIFT          (0U)
+#define SYSCON_CPSTAT_CM4SLEEPING(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM4SLEEPING_MASK)
+#define SYSCON_CPSTAT_CM0SLEEPING_MASK           (0x2U)
+#define SYSCON_CPSTAT_CM0SLEEPING_SHIFT          (1U)
+#define SYSCON_CPSTAT_CM0SLEEPING(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CM0SLEEPING_MASK)
+#define SYSCON_CPSTAT_CM4LOCKUP_MASK             (0x4U)
+#define SYSCON_CPSTAT_CM4LOCKUP_SHIFT            (2U)
+#define SYSCON_CPSTAT_CM4LOCKUP(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM4LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM4LOCKUP_MASK)
+#define SYSCON_CPSTAT_CM0LOCKUP_MASK             (0x8U)
+#define SYSCON_CPSTAT_CM0LOCKUP_SHIFT            (3U)
+#define SYSCON_CPSTAT_CM0LOCKUP(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CM0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CM0LOCKUP_MASK)
+
+/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
+#define SYSCON_AUTOCGOR_RAM0X_MASK               (0x2U)
+#define SYSCON_AUTOCGOR_RAM0X_SHIFT              (1U)
+#define SYSCON_AUTOCGOR_RAM0X(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
+#define SYSCON_AUTOCGOR_RAM1_MASK                (0x4U)
+#define SYSCON_AUTOCGOR_RAM1_SHIFT               (2U)
+#define SYSCON_AUTOCGOR_RAM1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
+#define SYSCON_AUTOCGOR_RAM2_MASK                (0x8U)
+#define SYSCON_AUTOCGOR_RAM2_SHIFT               (3U)
+#define SYSCON_AUTOCGOR_RAM2(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
+
+/*! @name JTAGIDCODE - JTAG ID code register */
+#define SYSCON_JTAGIDCODE_JTAGID_MASK            (0xFFFFFFFFU)
+#define SYSCON_JTAGIDCODE_JTAGID_SHIFT           (0U)
+#define SYSCON_JTAGIDCODE_JTAGID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
+
+/*! @name DEVICE_ID0 - Part ID register */
+#define SYSCON_DEVICE_ID0_PARTID_MASK            (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID0_PARTID_SHIFT           (0U)
+#define SYSCON_DEVICE_ID0_PARTID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
+
+/*! @name DEVICE_ID1 - Boot ROM and die revision register */
+#define SYSCON_DEVICE_ID1_REVID_MASK             (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID1_REVID_SHIFT            (0U)
+#define SYSCON_DEVICE_ID1_REVID(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
+
+/*! @name BODCTRL - Brown-Out Detect control */
+#define SYSCON_BODCTRL_BODRSTLEV_MASK            (0x3U)
+#define SYSCON_BODCTRL_BODRSTLEV_SHIFT           (0U)
+#define SYSCON_BODCTRL_BODRSTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
+#define SYSCON_BODCTRL_BODRSTENA_MASK            (0x4U)
+#define SYSCON_BODCTRL_BODRSTENA_SHIFT           (2U)
+#define SYSCON_BODCTRL_BODRSTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
+#define SYSCON_BODCTRL_BODINTLEV_MASK            (0x18U)
+#define SYSCON_BODCTRL_BODINTLEV_SHIFT           (3U)
+#define SYSCON_BODCTRL_BODINTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
+#define SYSCON_BODCTRL_BODINTENA_MASK            (0x20U)
+#define SYSCON_BODCTRL_BODINTENA_SHIFT           (5U)
+#define SYSCON_BODCTRL_BODINTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
+#define SYSCON_BODCTRL_BODRSTSTAT_MASK           (0x40U)
+#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT          (6U)
+#define SYSCON_BODCTRL_BODRSTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
+#define SYSCON_BODCTRL_BODINTSTAT_MASK           (0x80U)
+#define SYSCON_BODCTRL_BODINTSTAT_SHIFT          (7U)
+#define SYSCON_BODCTRL_BODINTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Register_Masks */
+
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE                              (0x40000000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS                         { SYSCON }
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CFG;                               /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
+  __IO uint32_t CTL;                               /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
+  __IO uint32_t STAT;                              /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t BRG;                               /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
+  __IO uint32_t OSR;                               /**< Oversample selection register for asynchronous communication., offset: 0x28 */
+  __IO uint32_t ADDR;                              /**< Address register for automatic address matching., offset: 0x2C */
+       uint8_t RESERVED_1[3536];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_4[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
+#define USART_CFG_ENABLE_MASK                    (0x1U)
+#define USART_CFG_ENABLE_SHIFT                   (0U)
+#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+#define USART_CFG_DATALEN_MASK                   (0xCU)
+#define USART_CFG_DATALEN_SHIFT                  (2U)
+#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+#define USART_CFG_PARITYSEL_MASK                 (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT                (4U)
+#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+#define USART_CFG_STOPLEN_MASK                   (0x40U)
+#define USART_CFG_STOPLEN_SHIFT                  (6U)
+#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+#define USART_CFG_MODE32K_MASK                   (0x80U)
+#define USART_CFG_MODE32K_SHIFT                  (7U)
+#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+#define USART_CFG_LINMODE_MASK                   (0x100U)
+#define USART_CFG_LINMODE_SHIFT                  (8U)
+#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+#define USART_CFG_CTSEN_MASK                     (0x200U)
+#define USART_CFG_CTSEN_SHIFT                    (9U)
+#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+#define USART_CFG_SYNCEN_MASK                    (0x800U)
+#define USART_CFG_SYNCEN_SHIFT                   (11U)
+#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+#define USART_CFG_CLKPOL_MASK                    (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT                   (12U)
+#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+#define USART_CFG_SYNCMST_MASK                   (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT                  (14U)
+#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+#define USART_CFG_LOOP_MASK                      (0x8000U)
+#define USART_CFG_LOOP_SHIFT                     (15U)
+#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+#define USART_CFG_IOMODE_MASK                    (0x10000U)
+#define USART_CFG_IOMODE_SHIFT                   (16U)
+#define USART_CFG_IOMODE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_IOMODE_SHIFT)) & USART_CFG_IOMODE_MASK)
+#define USART_CFG_OETA_MASK                      (0x40000U)
+#define USART_CFG_OETA_SHIFT                     (18U)
+#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT                 (19U)
+#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+#define USART_CFG_OESEL_MASK                     (0x100000U)
+#define USART_CFG_OESEL_SHIFT                    (20U)
+#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+#define USART_CFG_OEPOL_MASK                     (0x200000U)
+#define USART_CFG_OEPOL_SHIFT                    (21U)
+#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+#define USART_CFG_RXPOL_MASK                     (0x400000U)
+#define USART_CFG_RXPOL_SHIFT                    (22U)
+#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+#define USART_CFG_TXPOL_MASK                     (0x800000U)
+#define USART_CFG_TXPOL_SHIFT                    (23U)
+#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
+#define USART_CTL_TXBRKEN_MASK                   (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT                  (1U)
+#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+#define USART_CTL_ADDRDET_MASK                   (0x4U)
+#define USART_CTL_ADDRDET_SHIFT                  (2U)
+#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+#define USART_CTL_TXDIS_MASK                     (0x40U)
+#define USART_CTL_TXDIS_SHIFT                    (6U)
+#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+#define USART_CTL_CC_MASK                        (0x100U)
+#define USART_CTL_CC_SHIFT                       (8U)
+#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT                (9U)
+#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
+#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
+#define USART_STAT_RXIDLE_MASK                   (0x2U)
+#define USART_STAT_RXIDLE_SHIFT                  (1U)
+#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+#define USART_STAT_TXIDLE_MASK                   (0x8U)
+#define USART_STAT_TXIDLE_SHIFT                  (3U)
+#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+#define USART_STAT_CTS_MASK                      (0x10U)
+#define USART_STAT_CTS_SHIFT                     (4U)
+#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+#define USART_STAT_DELTACTS_MASK                 (0x20U)
+#define USART_STAT_DELTACTS_SHIFT                (5U)
+#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+#define USART_STAT_TXDISSTAT_MASK                (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT               (6U)
+#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+#define USART_STAT_RXBRK_MASK                    (0x400U)
+#define USART_STAT_RXBRK_SHIFT                   (10U)
+#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+#define USART_STAT_DELTARXBRK_MASK               (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT              (11U)
+#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+#define USART_STAT_START_MASK                    (0x1000U)
+#define USART_STAT_START_SHIFT                   (12U)
+#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT              (13U)
+#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT            (14U)
+#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT              (15U)
+#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+#define USART_STAT_ABERR_MASK                    (0x10000U)
+#define USART_STAT_ABERR_SHIFT                   (16U)
+#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
+#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
+#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+#define USART_INTENSET_TXDISEN_MASK              (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT             (6U)
+#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
+#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+#define USART_INTENSET_STARTEN_MASK              (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT             (12U)
+#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
+#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
+#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
+#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+#define USART_INTENSET_ABERREN_MASK              (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT             (16U)
+#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
+#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
+#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
+#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
+#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
+#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
+#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
+#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
+#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
+#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
+#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
+#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT                   (0U)
+#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
+#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
+#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
+#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
+#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
+#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+#define USART_INTSTAT_START_MASK                 (0x1000U)
+#define USART_INTSTAT_START_SHIFT                (12U)
+#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
+#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
+#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
+#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
+#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+
+/*! @name OSR - Oversample selection register for asynchronous communication. */
+#define USART_OSR_OSRVAL_MASK                    (0xFU)
+#define USART_OSR_OSRVAL_SHIFT                   (0U)
+#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+
+/*! @name ADDR - Address register for automatic address matching. */
+#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT                 (0U)
+#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
+#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
+#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
+#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT                (12U)
+#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT                (13U)
+#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
+#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
+#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
+#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
+#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
+#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
+#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
+#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
+#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
+#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
+#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
+#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
+#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
+#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
+#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
+#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
+#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
+#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
+#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
+#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
+#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
+#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
+#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
+#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
+#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
+#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
+#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
+#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
+#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
+#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
+#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT                (0U)
+#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT                (0U)
+#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT               (13U)
+#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT             (14U)
+#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT               (15U)
+#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
+#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
+#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
+#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
+#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+/** Peripheral USART0 base address */
+#define USART0_BASE                              (0x40086000u)
+/** Peripheral USART0 base pointer */
+#define USART0                                   ((USART_Type *)USART0_BASE)
+/** Peripheral USART1 base address */
+#define USART1_BASE                              (0x40087000u)
+/** Peripheral USART1 base pointer */
+#define USART1                                   ((USART_Type *)USART1_BASE)
+/** Peripheral USART2 base address */
+#define USART2_BASE                              (0x40088000u)
+/** Peripheral USART2 base pointer */
+#define USART2                                   ((USART_Type *)USART2_BASE)
+/** Peripheral USART3 base address */
+#define USART3_BASE                              (0x40089000u)
+/** Peripheral USART3 base pointer */
+#define USART3                                   ((USART_Type *)USART3_BASE)
+/** Peripheral USART4 base address */
+#define USART4_BASE                              (0x4008A000u)
+/** Peripheral USART4 base pointer */
+#define USART4                                   ((USART_Type *)USART4_BASE)
+/** Peripheral USART5 base address */
+#define USART5_BASE                              (0x40096000u)
+/** Peripheral USART5 base pointer */
+#define USART5                                   ((USART_Type *)USART5_BASE)
+/** Peripheral USART6 base address */
+#define USART6_BASE                              (0x40097000u)
+/** Peripheral USART6 base pointer */
+#define USART6                                   ((USART_Type *)USART6_BASE)
+/** Peripheral USART7 base address */
+#define USART7_BASE                              (0x40098000u)
+/** Peripheral USART7 base pointer */
+#define USART7                                   ((USART_Type *)USART7_BASE)
+/** Array initializer of USART peripheral base addresses */
+#define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
+/** Array initializer of USART peripheral base pointers */
+#define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
+  __IO uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
+  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
+  __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
+  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
+  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
+  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
+  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
+  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
+  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK             (0x7FU)
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT            (0U)
+#define USB_DEVCMDSTAT_DEV_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USB_DEVCMDSTAT_DEV_EN_MASK               (0x80U)
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT              (7U)
+#define USB_DEVCMDSTAT_DEV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
+#define USB_DEVCMDSTAT_SETUP_MASK                (0x100U)
+#define USB_DEVCMDSTAT_SETUP_SHIFT               (8U)
+#define USB_DEVCMDSTAT_SETUP(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK        (0x200U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT       (9U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USB_DEVCMDSTAT_LPM_SUP_MASK              (0x800U)
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT             (11U)
+#define USB_DEVCMDSTAT_LPM_SUP(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK          (0x1000U)
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT         (12U)
+#define USB_DEVCMDSTAT_INTONNAK_AO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK          (0x2000U)
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT         (13U)
+#define USB_DEVCMDSTAT_INTONNAK_AI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK          (0x4000U)
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT         (14U)
+#define USB_DEVCMDSTAT_INTONNAK_CO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK          (0x8000U)
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT         (15U)
+#define USB_DEVCMDSTAT_INTONNAK_CI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USB_DEVCMDSTAT_DCON_MASK                 (0x10000U)
+#define USB_DEVCMDSTAT_DCON_SHIFT                (16U)
+#define USB_DEVCMDSTAT_DCON(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
+#define USB_DEVCMDSTAT_DSUS_MASK                 (0x20000U)
+#define USB_DEVCMDSTAT_DSUS_SHIFT                (17U)
+#define USB_DEVCMDSTAT_DSUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
+#define USB_DEVCMDSTAT_LPM_SUS_MASK              (0x80000U)
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT             (19U)
+#define USB_DEVCMDSTAT_LPM_SUS(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
+#define USB_DEVCMDSTAT_LPM_REWP_MASK             (0x100000U)
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT            (20U)
+#define USB_DEVCMDSTAT_LPM_REWP(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
+#define USB_DEVCMDSTAT_DCON_C_MASK               (0x1000000U)
+#define USB_DEVCMDSTAT_DCON_C_SHIFT              (24U)
+#define USB_DEVCMDSTAT_DCON_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
+#define USB_DEVCMDSTAT_DSUS_C_MASK               (0x2000000U)
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT              (25U)
+#define USB_DEVCMDSTAT_DSUS_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
+#define USB_DEVCMDSTAT_DRES_C_MASK               (0x4000000U)
+#define USB_DEVCMDSTAT_DRES_C_SHIFT              (26U)
+#define USB_DEVCMDSTAT_DRES_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK        (0x10000000U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT       (28U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
+
+/*! @name INFO - USB Info register */
+#define USB_INFO_FRAME_NR_MASK                   (0x7FFU)
+#define USB_INFO_FRAME_NR_SHIFT                  (0U)
+#define USB_INFO_FRAME_NR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
+#define USB_INFO_ERR_CODE_MASK                   (0x7800U)
+#define USB_INFO_ERR_CODE_SHIFT                  (11U)
+#define USB_INFO_ERR_CODE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+#define USB_EPLISTSTART_EP_LIST_MASK             (0xFFFFFF00U)
+#define USB_EPLISTSTART_EP_LIST_SHIFT            (8U)
+#define USB_EPLISTSTART_EP_LIST(x)               (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+#define USB_DATABUFSTART_DA_BUF_MASK             (0xFFC00000U)
+#define USB_DATABUFSTART_DA_BUF_SHIFT            (22U)
+#define USB_DATABUFSTART_DA_BUF(x)               (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
+
+/*! @name LPM - USB Link Power Management register */
+#define USB_LPM_HIRD_HW_MASK                     (0xFU)
+#define USB_LPM_HIRD_HW_SHIFT                    (0U)
+#define USB_LPM_HIRD_HW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
+#define USB_LPM_HIRD_SW_MASK                     (0xF0U)
+#define USB_LPM_HIRD_SW_SHIFT                    (4U)
+#define USB_LPM_HIRD_SW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
+#define USB_LPM_DATA_PENDING_MASK                (0x100U)
+#define USB_LPM_DATA_PENDING_SHIFT               (8U)
+#define USB_LPM_DATA_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
+
+/*! @name EPSKIP - USB Endpoint skip */
+#define USB_EPSKIP_SKIP_MASK                     (0x3FFFFFFFU)
+#define USB_EPSKIP_SKIP_SHIFT                    (0U)
+#define USB_EPSKIP_SKIP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+#define USB_EPINUSE_BUF_MASK                     (0x3FCU)
+#define USB_EPINUSE_BUF_SHIFT                    (2U)
+#define USB_EPINUSE_BUF(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+#define USB_EPBUFCFG_BUF_SB_MASK                 (0x3FCU)
+#define USB_EPBUFCFG_BUF_SB_SHIFT                (2U)
+#define USB_EPBUFCFG_BUF_SB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
+
+/*! @name INTSTAT - USB interrupt status register */
+#define USB_INTSTAT_EP0OUT_MASK                  (0x1U)
+#define USB_INTSTAT_EP0OUT_SHIFT                 (0U)
+#define USB_INTSTAT_EP0OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
+#define USB_INTSTAT_EP0IN_MASK                   (0x2U)
+#define USB_INTSTAT_EP0IN_SHIFT                  (1U)
+#define USB_INTSTAT_EP0IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
+#define USB_INTSTAT_EP1OUT_MASK                  (0x4U)
+#define USB_INTSTAT_EP1OUT_SHIFT                 (2U)
+#define USB_INTSTAT_EP1OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
+#define USB_INTSTAT_EP1IN_MASK                   (0x8U)
+#define USB_INTSTAT_EP1IN_SHIFT                  (3U)
+#define USB_INTSTAT_EP1IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
+#define USB_INTSTAT_EP2OUT_MASK                  (0x10U)
+#define USB_INTSTAT_EP2OUT_SHIFT                 (4U)
+#define USB_INTSTAT_EP2OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
+#define USB_INTSTAT_EP2IN_MASK                   (0x20U)
+#define USB_INTSTAT_EP2IN_SHIFT                  (5U)
+#define USB_INTSTAT_EP2IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
+#define USB_INTSTAT_EP3OUT_MASK                  (0x40U)
+#define USB_INTSTAT_EP3OUT_SHIFT                 (6U)
+#define USB_INTSTAT_EP3OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
+#define USB_INTSTAT_EP3IN_MASK                   (0x80U)
+#define USB_INTSTAT_EP3IN_SHIFT                  (7U)
+#define USB_INTSTAT_EP3IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
+#define USB_INTSTAT_EP4OUT_MASK                  (0x100U)
+#define USB_INTSTAT_EP4OUT_SHIFT                 (8U)
+#define USB_INTSTAT_EP4OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
+#define USB_INTSTAT_EP4IN_MASK                   (0x200U)
+#define USB_INTSTAT_EP4IN_SHIFT                  (9U)
+#define USB_INTSTAT_EP4IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
+#define USB_INTSTAT_FRAME_INT_MASK               (0x40000000U)
+#define USB_INTSTAT_FRAME_INT_SHIFT              (30U)
+#define USB_INTSTAT_FRAME_INT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
+#define USB_INTSTAT_DEV_INT_MASK                 (0x80000000U)
+#define USB_INTSTAT_DEV_INT_SHIFT                (31U)
+#define USB_INTSTAT_DEV_INT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
+
+/*! @name INTEN - USB interrupt enable register */
+#define USB_INTEN_EP_INT_EN_MASK                 (0x3FFU)
+#define USB_INTEN_EP_INT_EN_SHIFT                (0U)
+#define USB_INTEN_EP_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
+#define USB_INTEN_FRAME_INT_EN_MASK              (0x40000000U)
+#define USB_INTEN_FRAME_INT_EN_SHIFT             (30U)
+#define USB_INTEN_FRAME_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
+#define USB_INTEN_DEV_INT_EN_MASK                (0x80000000U)
+#define USB_INTEN_DEV_INT_EN_SHIFT               (31U)
+#define USB_INTEN_DEV_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+#define USB_INTSETSTAT_EP_SET_INT_MASK           (0x3FFU)
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT          (0U)
+#define USB_INTSETSTAT_EP_SET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK        (0x40000000U)
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT       (30U)
+#define USB_INTSETSTAT_FRAME_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USB_INTSETSTAT_DEV_SET_INT_MASK          (0x80000000U)
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT         (31U)
+#define USB_INTSETSTAT_DEV_SET_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+#define USB_EPTOGGLE_TOGGLE_MASK                 (0x3FFU)
+#define USB_EPTOGGLE_TOGGLE_SHIFT                (0U)
+#define USB_EPTOGGLE_TOGGLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40084000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+#define USB_NEEDCLK_IRQS                         { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register., offset: 0x0 */
+  __IO uint32_t STAT;                              /**< Status register., offset: 0x4 */
+  __IO uint32_t CFG;                               /**< Capture configuration register., offset: 0x8 */
+  __O  uint32_t CAPCLR;                            /**< Capture clear register., offset: 0xC */
+  __I  uint32_t CAP[4];                            /**< Capture register ., array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register. */
+#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
+#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
+#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+
+/*! @name STAT - Status register. */
+#define UTICK_STAT_INTR_MASK                     (0x1U)
+#define UTICK_STAT_INTR_SHIFT                    (0U)
+#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
+#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+
+/*! @name CFG - Capture configuration register. */
+#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
+#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
+#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
+#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
+#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
+#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
+#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
+#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
+#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+
+/*! @name CAPCLR - Capture clear register. */
+#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
+#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
+#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
+#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
+#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+
+/*! @name CAP - Capture register . */
+#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
+#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+#define UTICK_CAP_VALID_MASK                     (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT                    (31U)
+#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE                              (0x4000E000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS                          { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS                               { UTICK0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MOD;                               /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
+  __IO uint32_t TC;                                /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
+  __O  uint32_t FEED;                              /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
+  __I  uint32_t TV;                                /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t WARNINT;                           /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
+  __IO uint32_t WINDOW;                            /**< Watchdog Window compare value., offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+#define WWDT_MOD_WDEN_MASK                       (0x1U)
+#define WWDT_MOD_WDEN_SHIFT                      (0U)
+#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+#define WWDT_MOD_WDRESET_MASK                    (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT                   (1U)
+#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+#define WWDT_MOD_WDTOF_MASK                      (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT                     (2U)
+#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+#define WWDT_MOD_WDINT_MASK                      (0x8U)
+#define WWDT_MOD_WDINT_SHIFT                     (3U)
+#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
+#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_LOCK_MASK                       (0x20U)
+#define WWDT_MOD_LOCK_SHIFT                      (5U)
+#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
+#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT                      (0U)
+#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
+#define WWDT_FEED_FEED_MASK                      (0xFFU)
+#define WWDT_FEED_FEED_SHIFT                     (0U)
+#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT                      (0U)
+#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
+#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
+#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+
+/*! @name WINDOW - Watchdog Window compare value. */
+#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
+#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT base address */
+#define WWDT_BASE                                (0x4000C000u)
+/** Peripheral WWDT base pointer */
+#define WWDT                                     ((WWDT_Type *)WWDT_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS                          { WWDT_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS                           { WWDT }
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS                                { WDT_BOD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/* No SDK compatibility issues. */
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _LPC54114_CM4_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/LPC54114_cm4_features.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,134 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2016-05-09
+**     Build:               b160802
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-05-09)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _LPC54114_cm4_FEATURES_H_
+#define _LPC54114_cm4_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (8)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MAILBOX availability on the SoC. */
+#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (8)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (8)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
+
+#endif /* _LPC54114_cm4_FEATURES_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_ARM_STD/LPC54114J256_cm4.sct	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,129 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          LPC54114J256BD64_cm4
+**                          LPC54114J256UK49_cm4
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC5411x User manual Rev. 1.0 16 February 2016
+**     Version:             rev. 1.0, 2016-04-29
+**     Build:               b160526
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright (c) 2016 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+#define __ram_vector_table__            1
+
+#if (defined(__ram_vector_table__))
+  #define __ram_vector_table_size__    0x000000E0
+#else
+  #define __ram_vector_table_size__    0x00000000
+#endif
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x000000E0
+
+#define m_text_start                   0x000000E0
+#define m_text_size                    0x0002FF20
+
+#define m_core1_image_start            0x00030000
+#define m_core1_image_size             0x00010000
+
+#define m_interrupts_ram_start         0x20000000
+#define m_interrupts_ram_size          __ram_vector_table_size__
+
+#define m_rpmsg_sh_mem_start           0x20026800
+#define m_rpmsg_sh_mem_size            0x00001800
+
+#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size                    (0x00010000 - m_interrupts_ram_size)
+
+#define m_sramx_start                  0x04000000
+#define m_sramx_size                   0x00008000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start m_text_size  {  ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  ER_m_sramx m_sramx_start m_sramx_size { ; SRAMX memory
+    * (sramx)
+  }
+
+#if (defined(__ram_vector_table__))
+  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
+  }
+#else
+  VECTOR_RAM m_interrupts_start EMPTY 0 {
+  }
+#endif
+
+  RW_m_data m_data_start m_data_size  {  ; RW data
+    .ANY (+RW +ZI)
+  }
+  RW_IRAM1 ((ImageLimit(RW_m_data) == m_data_start) ? ImageLimit(RW_m_data) : +0) EMPTY Heap_Size { ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+    * (rpmsg_sh_mem_section)
+  }
+}
+
+LR_CORE1_IMAGE m_core1_image_start {
+  CORE1_REGION m_core1_image_start m_core1_image_size {
+    *(M0CODE)
+  }
+}
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_ARM_STD/libpower.ar has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_ARM_STD/startup_LPC54114_cm4.S	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,625 @@
+;/*****************************************************************************
+; * @file:    startup_LPC54114_cm4.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; *           LPC54114_cm4
+; * @version: 1.0
+; * @date:    2016-4-29
+; *
+; * Copyright: 1997 - 2016 Freescale Semiconductor, Inc. All Rights Reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD      |Image$$ARM_LIB_STACK$$ZI$$Limit|       ; Top of Stack
+                DCD     Reset_Handler   ; Reset Handler
+
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
+                DCD     MemManage_Handler
+                DCD     BusFault_Handler
+                DCD     UsageFault_Handler
+__vector_table_0x1c
+                DCD     0                         ; Checksum of the first 7 words
+                DCD     0
+                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
+                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
+                DCD     SVC_Handler
+                DCD     DebugMon_Handler
+                DCD     0
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
+
+                ; External Interrupts
+                DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
+                DCD     DMA0_IRQHandler  ; DMA controller
+                DCD     GINT0_IRQHandler  ; GPIO group 0
+                DCD     GINT1_IRQHandler  ; GPIO group 1
+                DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
+                DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
+                DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
+                DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
+                DCD     UTICK0_IRQHandler  ; Micro-tick Timer
+                DCD     MRT0_IRQHandler  ; Multi-rate timer
+                DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
+                DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
+                DCD     SCT0_IRQHandler  ; SCTimer/PWM
+                DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
+                DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C)
+                DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C)
+                DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C)
+                DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C)
+                DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C)
+                DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C)
+                DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S)
+                DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S)
+                DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
+                DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
+                DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
+                DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
+                DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
+                DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
+                DCD     USB0_IRQHandler  ; USB device
+                DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
+                DCD     IOH_IRQHandler  ; IOH
+                DCD     MAILBOX_IRQHandler  ; Mailbox interrupt (present on selected devices)
+                DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
+                DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
+                DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
+                DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
+                DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
+                DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
+                DCD     Reserved54_IRQHandler  ; Reserved interrupt
+                DCD     SPIFI0_IRQHandler  ; SPI flash interface
+
+;     <h> Code Read Protection level (CRP)
+;       <o>    CRP_Level:
+;                       <0xFFFFFFFF=> Disabled
+;                       <0x4E697370=> NO_ISP
+;                       <0x12345678=> CRP1
+;                       <0x87654321=> CRP2
+;                       <0x43218765=> CRP3 (Are you sure?)
+;     </h>
+CRP_Level       EQU     0xFFFFFFFF
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+cpu_id          EQU     0xE000ED00
+cpu_ctrl        EQU     0x40000800
+coproc_boot     EQU     0x40000804
+coproc_stack    EQU     0x40000808
+
+rel_vals
+                DCD     cpu_id, cpu_ctrl, coproc_boot, coproc_stack
+                DCW     0xFFF, 0xC24
+
+; Reset Handler - shared for both cores
+Reset_Handler   PROC
+                EXPORT  Reset_Handler               [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+                IF      :LNOT::DEF:SLAVEBOOT
+                ; Both the M0+ and M4 core come via this shared startup code,
+                ; but the M0+ and M4 core have different vector tables.
+                ; Determine if the core executing this code is the master or
+                ; the slave and handle each core state individually.
+shared_boot_entry
+                LDR     r6, =rel_vals
+                MOVS    r4, #0                          ; Flag for slave core (0)
+                MOVS    r5, #1
+
+                ; Determine which core (M0+ or M4) this code is running on
+                ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
+get_current_core_id
+                LDR     r0, [r6, #0]
+                LDR     r1, [r0]                        ; r1 = CPU ID status
+                LSRS    r1, r1, #4                      ; Right justify 12 CPU ID bits
+                LDRH    r2, [r6, #16]                   ; Mask for CPU ID bits
+                ANDS    r2, r1, r2                      ; r2 = ARM COrtex CPU ID
+                LDRH    r3, [r6, #18]                   ; Mask for CPU ID bits
+                CMP     r3, r2                          ; Core ID matches M4 identifier
+                BNE     get_master_status
+                MOV     r4, r5                          ; Set flag for master core (1)
+
+                ; Determine if M4 core is the master or slave
+                ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
+get_master_status
+                LDR     r0, [r6, #4]
+                LDR     r3, [r0]                        ; r3 = SYSCON co-processor CPU control status
+                ANDS    r3, r3, r5                      ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
+
+                ; Select boot based on selected master core and core ID
+select_boot
+                EORS    r3, r3, r4                      ; r4 = (Bit 0: 0 = master, 1 = slave)
+                BNE     slave_boot
+                B       normal_boot
+
+                ; Slave boot
+slave_boot
+                LDR     r0, [r6, #8]
+                LDR     r2, [r0]                        ; r1 = SYSCON co-processor boot address
+                CMP     r2, #0                          ; Slave boot address = 0 (not set up)?
+                BEQ     cpu_sleep
+                LDR     r0, [r6, #12]
+                LDR     r1, [r0]                        ; r5 = SYSCON co-processor stack address
+                MOV     sp, r1                          ; Update slave CPU stack pointer
+                ; Be sure to update VTOR for the slave MCU to point to the
+                ; slave vector table in boot memory
+                BX      r2                              ; Jump to slave boot address
+
+                ; Slave isn't yet setup for system boot from the master
+                ; so sleep until the master sets it up and then reboots it
+cpu_sleep
+                MOV     sp, r5                          ; Will force exception if something happens
+cpu_sleep_wfi
+                WFI                                     ; Sleep forever until master reboots
+                B       cpu_sleep_wfi
+                ENDIF
+
+                ; Normal boot for master/slave
+normal_boot
+                LDR     r0, =SystemInit
+                BLX     r0
+                LDR     r0, =__main
+                BX      r0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler \
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+
+MemManage_Handler     PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+
+BusFault_Handler PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+
+UsageFault_Handler PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+
+DebugMon_Handler PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+WDT_BOD_IRQHandler\
+                PROC
+                EXPORT     WDT_BOD_IRQHandler        [WEAK]
+                LDR        R0, =WDT_BOD_DriverIRQHandler
+                BX         R0
+                ENDP
+
+DMA0_IRQHandler\
+                PROC
+                EXPORT     DMA0_IRQHandler        [WEAK]
+                LDR        R0, =DMA0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+GINT0_IRQHandler\
+                PROC
+                EXPORT     GINT0_IRQHandler        [WEAK]
+                LDR        R0, =GINT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+GINT1_IRQHandler\
+                PROC
+                EXPORT     GINT1_IRQHandler        [WEAK]
+                LDR        R0, =GINT1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT0_IRQHandler\
+                PROC
+                EXPORT     PIN_INT0_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT1_IRQHandler\
+                PROC
+                EXPORT     PIN_INT1_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT2_IRQHandler\
+                PROC
+                EXPORT     PIN_INT2_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT3_IRQHandler\
+                PROC
+                EXPORT     PIN_INT3_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+UTICK0_IRQHandler\
+                PROC
+                EXPORT     UTICK0_IRQHandler        [WEAK]
+                LDR        R0, =UTICK0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+MRT0_IRQHandler\
+                PROC
+                EXPORT     MRT0_IRQHandler        [WEAK]
+                LDR        R0, =MRT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER0_IRQHandler\
+                PROC
+                EXPORT     CTIMER0_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER1_IRQHandler\
+                PROC
+                EXPORT     CTIMER1_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SCT0_IRQHandler\
+                PROC
+                EXPORT     SCT0_IRQHandler        [WEAK]
+                LDR        R0, =SCT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER3_IRQHandler\
+                PROC
+                EXPORT     CTIMER3_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM0_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM0_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM1_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM1_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM2_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM2_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM3_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM3_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM4_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM4_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM5_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM5_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM5_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM6_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM6_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM6_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM7_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM7_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM7_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_SEQA_IRQHandler\
+                PROC
+                EXPORT     ADC0_SEQA_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_SEQA_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_SEQB_IRQHandler\
+                PROC
+                EXPORT     ADC0_SEQB_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_SEQB_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_THCMP_IRQHandler\
+                PROC
+                EXPORT     ADC0_THCMP_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_THCMP_DriverIRQHandler
+                BX         R0
+                ENDP
+
+DMIC0_IRQHandler\
+                PROC
+                EXPORT     DMIC0_IRQHandler        [WEAK]
+                LDR        R0, =DMIC0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+HWVAD0_IRQHandler\
+                PROC
+                EXPORT     HWVAD0_IRQHandler        [WEAK]
+                LDR        R0, =HWVAD0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB0_NEEDCLK_IRQHandler\
+                PROC
+                EXPORT     USB0_NEEDCLK_IRQHandler        [WEAK]
+                LDR        R0, =USB0_NEEDCLK_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB0_IRQHandler\
+                PROC
+                EXPORT     USB0_IRQHandler        [WEAK]
+                LDR        R0, =USB0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+RTC_IRQHandler\
+                PROC
+                EXPORT     RTC_IRQHandler        [WEAK]
+                LDR        R0, =RTC_DriverIRQHandler
+                BX         R0
+                ENDP
+
+IOH_IRQHandler\
+                PROC
+                EXPORT     IOH_IRQHandler        [WEAK]
+                LDR        R0, =IOH_DriverIRQHandler
+                BX         R0
+                ENDP
+
+MAILBOX_IRQHandler\
+                PROC
+                EXPORT     MAILBOX_IRQHandler        [WEAK]
+                LDR        R0, =MAILBOX_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT4_IRQHandler\
+                PROC
+                EXPORT     PIN_INT4_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT5_IRQHandler\
+                PROC
+                EXPORT     PIN_INT5_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT5_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT6_IRQHandler\
+                PROC
+                EXPORT     PIN_INT6_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT6_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT7_IRQHandler\
+                PROC
+                EXPORT     PIN_INT7_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT7_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER2_IRQHandler\
+                PROC
+                EXPORT     CTIMER2_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER4_IRQHandler\
+                PROC
+                EXPORT     CTIMER4_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Reserved54_IRQHandler\
+                PROC
+                EXPORT     Reserved54_IRQHandler        [WEAK]
+                LDR        R0, =Reserved54_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SPIFI0_IRQHandler\
+                PROC
+                EXPORT     SPIFI0_IRQHandler        [WEAK]
+                LDR        R0, =SPIFI0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Default_Handler PROC
+                EXPORT     WDT_BOD_DriverIRQHandler        [WEAK]
+                EXPORT     DMA0_DriverIRQHandler        [WEAK]
+                EXPORT     GINT0_DriverIRQHandler        [WEAK]
+                EXPORT     GINT1_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT0_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT1_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT2_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT3_DriverIRQHandler        [WEAK]
+                EXPORT     UTICK0_DriverIRQHandler        [WEAK]
+                EXPORT     MRT0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER1_DriverIRQHandler        [WEAK]
+                EXPORT     SCT0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER3_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM0_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM1_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM2_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM3_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM4_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM5_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM6_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM7_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_SEQA_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_SEQB_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_THCMP_DriverIRQHandler        [WEAK]
+                EXPORT     DMIC0_DriverIRQHandler        [WEAK]
+                EXPORT     HWVAD0_DriverIRQHandler        [WEAK]
+                EXPORT     USB0_NEEDCLK_DriverIRQHandler        [WEAK]
+                EXPORT     USB0_DriverIRQHandler        [WEAK]
+                EXPORT     RTC_DriverIRQHandler        [WEAK]
+                EXPORT     IOH_DriverIRQHandler        [WEAK]
+                EXPORT     MAILBOX_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT4_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT5_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT6_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT7_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER2_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER4_DriverIRQHandler        [WEAK]
+                EXPORT     Reserved54_DriverIRQHandler        [WEAK]
+                EXPORT     SPIFI0_DriverIRQHandler        [WEAK]
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+IOH_DriverIRQHandler
+MAILBOX_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+Reserved54_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+                END
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_ARM_STD/sys.cpp	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_GCC_ARM/LPC54114J256_cm4_flash.ld	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,292 @@
+/*
+** ###################################################################
+**     Processors:          LPC54114J256_cm4
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    LPC54114 Series Reference Manual, Rev. 0 , 11/2016
+**     Version:             rev. 1.0, 2016-11-02
+**     Build:               b161214
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright (c) 2016 - 2017 , NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Copyright (c) 2016 NXP Semiconductors, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of NXP Semiconductors, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+__ram_vector_table__ = 1;
+
+__stack_size__ = 0x2000;
+__heap_size__ = 0x4000;
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0xE4 : 0x0;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0;
+
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x000000E4
+  m_text                (RX)  : ORIGIN = 0x000000E4, LENGTH = 0x0002FF1C
+  m_core1_image         (RX)  : ORIGIN = 0x00030000, LENGTH = 0x00010000
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00010000
+  rpmsg_sh_mem          (RW)  : ORIGIN = 0x20026800, LENGTH = RPMSG_SHMEM_SIZE
+
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* section for storing the secondary core image */
+  .m0code :
+  {
+     . = ALIGN(4) ;
+    KEEP (*(.m0code))
+     *(.m0code*)
+     . = ALIGN(4) ;
+  } > m_core1_image
+
+  /* NOINIT section for rpmsg_sh_mem */
+  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+  {
+     *(.noinit.$rpmsg_sh_mem*)
+     . = ALIGN(4) ;
+  } > rpmsg_sh_mem
+
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.ramfunc*)             /* for functions in ram */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_GCC_ARM/libpower.a has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_GCC_ARM/startup_LPC54114_cm4.S	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,791 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_LPC54114_cm4.S                                                      */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            LPC54114_cm4                                                                */
+/*  @version: 1.0                                                                         */
+/*  @date:    2016-11-2                                                                   */
+/*  @build:   b161214                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.                              */
+/* Copyright (c) 2016 - 2017 , NXP                                                        */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of copyright holder nor the names of its                            */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*                                                                                        */
+/* Copyright (c) 2016 , NXP Semiconductors, Inc.                                          */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of NXP Semiconductors, Inc. nor the names of its                    */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   WDT_BOD_IRQHandler                              /* Watchdog Timer, Brownout detect */
+    .long   DMA0_IRQHandler                                 /* DMA controller interrupt */
+    .long   GINT0_IRQHandler                                /* GPIO group 0 */
+    .long   GINT1_IRQHandler                                /* GPIO group 1 */
+    .long   PIN_INT0_IRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
+    .long   PIN_INT1_IRQHandler                             /* Pin interrupt 1 or pattern match engine slice 1 */
+    .long   PIN_INT2_IRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
+    .long   PIN_INT3_IRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
+    .long   UTICK0_IRQHandler                               /* Micro-tick Timer */
+    .long   MRT0_IRQHandler                                 /* Multi-rate timer */
+    .long   CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
+    .long   CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
+    .long   SCT0_IRQHandler                                 /* SCTimer/PWM */
+    .long   CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
+    .long   FLEXCOMM0_IRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM1_IRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM2_IRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM3_IRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM4_IRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM5_IRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM6_IRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM7_IRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */
+    .long   ADC0_SEQA_IRQHandler                            /* ADC0 sequence A completion */
+    .long   ADC0_SEQB_IRQHandler                            /* ADC0 sequence B completion */
+    .long   ADC0_THCMP_IRQHandler                           /* ADC0 threshold compare and error. */
+    .long   DMIC0_IRQHandler                                /* RTC alarm and wake-up interrupts */
+    .long   HWVAD0_IRQHandler                               /* Hardware Voice Activity Detector */
+    .long   USB0_NEEDCLK_IRQHandler                         /* USB Activity Wake-up Interrupt */
+    .long   USB0_IRQHandler                                 /* USB device */
+    .long   RTC_IRQHandler                                  /* RTC alarm and wake-up interrupts */
+    .long   IOH_IRQHandler                                  /* IOH interrupt */
+    .long   MAILBOX_IRQHandler                              /* Mailbox interrupt */
+    .long   PIN_INT4_IRQHandler                             /* Pin interrupt 4 or pattern match engine slice 4 int */
+    .long   PIN_INT5_IRQHandler                             /* Pin interrupt 5 or pattern match engine slice 5 int */
+    .long   PIN_INT6_IRQHandler                             /* Pin interrupt 6 or pattern match engine slice 6 int */
+    .long   PIN_INT7_IRQHandler                             /* Pin interrupt 7 or pattern match engine slice 7 int */
+    .long   CTIMER2_IRQHandler                              /* Standard counter/timer CTIMER2 */
+    .long   CTIMER4_IRQHandler                              /* Standard counter/timer CTIMER4 */
+    .long   0                                               /* Reserved interrupt */
+    .long   SPIFI0_IRQHandler                               /* SPI flash interface */
+    .size    __Vectors, . - __Vectors
+
+
+    
+    .text
+    .thumb
+#ifndef  SLAVEBOOT
+rel_vals:
+    .long   0xE000ED00   /* cpu_id */
+    .long   0x40000800   /* cpu_ctrl */
+    .long   0x40000804   /* coproc_boot */
+    .long   0x40000808   /* coproc_stack */
+    .short  0x0FFF       
+    .short  0x0C24
+#endif
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+#ifndef  SLAVEBOOT
+/* Both the M0+ and M4 core come via this shared startup code,
+ * but the M0+ and M4 core have different vector tables.
+ * Determine if the core executing this code is the master or
+ * the slave and handle each core state individually. */
+
+shared_boot_entry:
+    ldr     r6, =rel_vals
+                
+    /* Flag for slave core (0) */                
+    movs    r4, 0
+    movs    r5, 1
+
+    /* Determine which core (M0+ or M4) this code is running on */
+    /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */
+get_current_core_id:
+    ldr     r0, [r6, #0]
+    ldr     r1, [r0]                        /* r1 = CPU ID status */
+    lsrs    r1, r1, #4                      /* Right justify 12 CPU ID bits */
+    ldrh    r2, [r6, #16]                   /* Mask for CPU ID bits */
+    ands    r2, r1, r2                      /* r2 = ARM COrtex CPU ID */
+    ldrh    r3, [r6, #18]                   /* Mask for CPU ID bits */
+    cmp     r3, r2                          /* Core ID matches M4 identifier */
+    bne     get_master_status
+    mov     r4, r5                          /* Set flag for master core (1) */
+
+    /* Determine if M4 core is the master or slave */
+    /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */
+get_master_status:
+    ldr     r0, [r6, #4]
+    ldr     r3, [r0]                        /* r3 = SYSCON co-processor CPU control status */
+
+    ands    r3, r3, r5                      /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
+
+    /* Select boot based on selected master core and core ID */
+
+select_boot:
+    eors    r3, r3, r4                      /* r4 = (Bit 0: 0 = master, 1 = slave) */
+
+    bne     slave_boot
+    b       normal_boot
+
+    /* Slave boot */
+slave_boot:
+    ldr     r0, [r6, #8]
+    ldr     r2, [r0]                        /* r1 = SYSCON co-processor boot address */
+
+    cmp     r2, #0                          /* Slave boot address = 0 (not set up)? */
+
+    beq     cpu_sleep
+    ldr     r0, [r6, #12]
+    ldr     r1, [r0]                        /* r5 = SYSCON co-processor stack address */
+
+    mov     sp, r1                          /* Update slave CPU stack pointer */
+
+    /* Be sure to update VTOR for the slave MCU to point to the */
+    /* slave vector table in boot memory */
+    bx      r2                              /* Jump to slave boot address */
+
+    /* Slave isn't yet setup for system boot from the master */
+    /* so sleep until the master sets it up and then reboots it */
+cpu_sleep:
+    mov     sp, r5                          /* Will force exception if something happens */
+cpu_sleep_wfi:
+    wfi                                     /* Sleep forever until master reboots */
+    b       cpu_sleep_wfi
+#endif /* defined(SLAVEBOOT) */
+
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+normal_boot:
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+    /*      Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      __etext: End of code section, i.e., begin of data sections to copy from.
+     *      __data_start__/__data_end__: RAM address range that data should be
+     *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+#if 1
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one.
+ * Change to "#if 0" to use the second one */
+.LC0:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC0
+#else
+    subs    r3, r2
+    ble    .LC1
+.LC0:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC0
+.LC1:
+#endif
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    movs    r0, 0
+.LC2:
+    cmp     r1, r2
+    itt    lt
+    strlt   r0, [r1], #4
+    blt    .LC2
+#endif /* __STARTUP_CLEAR_BSS */
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+    
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak MemManage_Handler
+    .type MemManage_Handler, %function
+MemManage_Handler:
+    ldr   r0,=MemManage_Handler
+    bx    r0
+    .size MemManage_Handler, . - MemManage_Handler
+
+    .align 1
+    .thumb_func
+    .weak BusFault_Handler
+    .type BusFault_Handler, %function
+BusFault_Handler:
+    ldr   r0,=BusFault_Handler
+    bx    r0
+    .size BusFault_Handler, . - BusFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak UsageFault_Handler
+    .type UsageFault_Handler, %function
+UsageFault_Handler:
+    ldr   r0,=UsageFault_Handler
+    bx    r0
+    .size UsageFault_Handler, . - UsageFault_Handler
+    
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak DebugMon_Handler
+    .type DebugMon_Handler, %function
+DebugMon_Handler:
+    ldr   r0,=DebugMon_Handler
+    bx    r0
+    .size DebugMon_Handler, . - DebugMon_Handler
+    
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak WDT_BOD_IRQHandler
+    .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+    ldr   r0,=WDT_BOD_DriverIRQHandler
+    bx    r0
+    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT0_IRQHandler
+    .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+    ldr   r0,=GINT0_DriverIRQHandler
+    bx    r0
+    .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT1_IRQHandler
+    .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+    ldr   r0,=GINT1_DriverIRQHandler
+    bx    r0
+    .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT0_IRQHandler
+    .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+    ldr   r0,=PIN_INT0_DriverIRQHandler
+    bx    r0
+    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT1_IRQHandler
+    .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+    ldr   r0,=PIN_INT1_DriverIRQHandler
+    bx    r0
+    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT2_IRQHandler
+    .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+    ldr   r0,=PIN_INT2_DriverIRQHandler
+    bx    r0
+    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT3_IRQHandler
+    .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+    ldr   r0,=PIN_INT3_DriverIRQHandler
+    bx    r0
+    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UTICK0_IRQHandler
+    .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+    ldr   r0,=UTICK0_DriverIRQHandler
+    bx    r0
+    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MRT0_IRQHandler
+    .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+    ldr   r0,=MRT0_DriverIRQHandler
+    bx    r0
+    .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER0_IRQHandler
+    .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+    ldr   r0,=CTIMER0_DriverIRQHandler
+    bx    r0
+    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER1_IRQHandler
+    .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+    ldr   r0,=CTIMER1_DriverIRQHandler
+    bx    r0
+    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+
+    .align 1
+    .thumb_func
+    .weak SCT0_IRQHandler
+    .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+    ldr   r0,=SCT0_DriverIRQHandler
+    bx    r0
+    .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER3_IRQHandler
+    .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+    ldr   r0,=CTIMER3_DriverIRQHandler
+    bx    r0
+    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM0_IRQHandler
+    .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+    ldr   r0,=FLEXCOMM0_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM1_IRQHandler
+    .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+    ldr   r0,=FLEXCOMM1_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM2_IRQHandler
+    .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+    ldr   r0,=FLEXCOMM2_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM3_IRQHandler
+    .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+    ldr   r0,=FLEXCOMM3_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM4_IRQHandler
+    .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+    ldr   r0,=FLEXCOMM4_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM5_IRQHandler
+    .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+    ldr   r0,=FLEXCOMM5_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM6_IRQHandler
+    .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+    ldr   r0,=FLEXCOMM6_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler    
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM7_IRQHandler
+    .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+    ldr   r0,=FLEXCOMM7_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler    
+
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQA_IRQHandler
+    .type ADC0_SEQA_IRQHandler, %function
+ADC0_SEQA_IRQHandler:
+    ldr   r0,=ADC0_SEQA_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQB_IRQHandler
+    .type ADC0_SEQB_IRQHandler, %function
+ADC0_SEQB_IRQHandler:
+    ldr   r0,=ADC0_SEQB_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_THCMP_IRQHandler
+    .type ADC0_THCMP_IRQHandler, %function
+ADC0_THCMP_IRQHandler:
+    ldr   r0,=ADC0_THCMP_DriverIRQHandler
+    bx    r0
+    .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMIC0_IRQHandler
+    .type DMIC0_IRQHandler, %function
+DMIC0_IRQHandler:
+    ldr   r0,=DMIC0_DriverIRQHandler
+    bx    r0
+    .size DMIC0_IRQHandler, . - DMIC0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak HWVAD0_IRQHandler
+    .type HWVAD0_IRQHandler, %function
+HWVAD0_IRQHandler:
+    ldr   r0,=HWVAD0_DriverIRQHandler
+    bx    r0
+    .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_NEEDCLK_IRQHandler
+    .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_IRQHandler
+    .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+    ldr   r0,=USB0_DriverIRQHandler
+    bx    r0
+    .size USB0_IRQHandler, . - USB0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RTC_IRQHandler
+    .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+    ldr   r0,=RTC_DriverIRQHandler
+    bx    r0
+    .size RTC_IRQHandler, . - RTC_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak IOH_IRQHandler
+    .type IOH_IRQHandler, %function
+IOH_IRQHandler:
+    ldr   r0,=IOH_DriverIRQHandler
+    bx    r0
+    .size IOH_IRQHandler, . - IOH_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MAILBOX_IRQHandler
+    .type MAILBOX_IRQHandler, %function
+MAILBOX_IRQHandler:
+    ldr   r0,=MAILBOX_DriverIRQHandler
+    bx    r0
+    .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
+
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT4_IRQHandler
+    .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+    ldr   r0,=PIN_INT4_DriverIRQHandler
+    bx    r0
+    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak PIN_INT5_IRQHandler
+    .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+    ldr   r0,=PIN_INT5_DriverIRQHandler
+    bx    r0
+    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT6_IRQHandler
+    .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+    ldr   r0,=PIN_INT6_DriverIRQHandler
+    bx    r0
+    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT7_IRQHandler
+    .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+    ldr   r0,=PIN_INT7_DriverIRQHandler
+    bx    r0
+    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+
+
+    .align 1
+    .thumb_func
+    .weak CTIMER2_IRQHandler
+    .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+    ldr   r0,=CTIMER2_DriverIRQHandler
+    bx    r0
+    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER4_IRQHandler
+    .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+    ldr   r0,=CTIMER4_DriverIRQHandler
+    bx    r0
+    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+    
+    .align 1
+    .thumb_func
+    .weak SPIFI0_IRQHandler
+    .type SPIFI0_IRQHandler, %function
+SPIFI0_IRQHandler:
+    ldr   r0,=SPIFI0_DriverIRQHandler
+    bx    r0
+    .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler    
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler     WDT_BOD_DriverIRQHandler              /* Windowed watchdog timer, Brownout detect */
+    def_irq_handler     DMA0_DriverIRQHandler                 /* DMA controller */
+    def_irq_handler     GINT0_DriverIRQHandler                /* GPIO group 0 */
+    def_irq_handler     GINT1_DriverIRQHandler                /* GPIO group 1 */
+    def_irq_handler     PIN_INT0_DriverIRQHandler             /* Pin interrupt 0 or pattern match engine slice 0 */
+    def_irq_handler     PIN_INT1_DriverIRQHandler             /* Pin interrupt 1or pattern match engine slice 1 */
+    def_irq_handler     PIN_INT2_DriverIRQHandler             /* Pin interrupt 2 or pattern match engine slice 2 */
+    def_irq_handler     PIN_INT3_DriverIRQHandler             /* Pin interrupt 3 or pattern match engine slice 3 */
+    def_irq_handler     UTICK0_DriverIRQHandler               /* Micro-tick Timer */
+    def_irq_handler     MRT0_DriverIRQHandler                 /* Multi-rate timer */
+    def_irq_handler     CTIMER0_DriverIRQHandler              /* Standard counter/timer CTIMER0 */
+    def_irq_handler     CTIMER1_DriverIRQHandler              /* Standard counter/timer CTIMER1 */
+    def_irq_handler     SCT0_DriverIRQHandler                 /* SCTimer/PWM */
+    def_irq_handler     CTIMER3_DriverIRQHandler              /* Standard counter/timer CTIMER3 */
+    def_irq_handler     FLEXCOMM0_DriverIRQHandler            /* Flexcomm Interface 0 (USART, SPI, I2C) */
+    def_irq_handler     FLEXCOMM1_DriverIRQHandler            /* Flexcomm Interface 1 (USART, SPI, I2C) */
+    def_irq_handler     FLEXCOMM2_DriverIRQHandler            /* Flexcomm Interface 2 (USART, SPI, I2C) */
+    def_irq_handler     FLEXCOMM3_DriverIRQHandler            /* Flexcomm Interface 3 (USART, SPI, I2C) */
+    def_irq_handler     FLEXCOMM4_DriverIRQHandler            /* Flexcomm Interface 4 (USART, SPI, I2C) */
+    def_irq_handler     FLEXCOMM5_DriverIRQHandler            /* Flexcomm Interface 5 (USART, SPI, I2C) */
+    def_irq_handler     FLEXCOMM6_DriverIRQHandler            /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */
+    def_irq_handler     FLEXCOMM7_DriverIRQHandler            /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */
+    def_irq_handler     ADC0_SEQA_DriverIRQHandler            /* ADC0 sequence A completion. */
+    def_irq_handler     ADC0_SEQB_DriverIRQHandler            /* ADC0 sequence B completion. */
+    def_irq_handler     ADC0_THCMP_DriverIRQHandler           /* ADC0 threshold compare and error. */
+    def_irq_handler     DMIC0_DriverIRQHandler                /* Digital microphone and DMIC subsystem */
+    def_irq_handler     HWVAD0_DriverIRQHandler               /* Hardware Voice Activity Detector */
+    def_irq_handler     USB0_NEEDCLK_DriverIRQHandler         /* USB Activity Wake-up Interrupt */
+    def_irq_handler     USB0_DriverIRQHandler                 /* USB device */
+    def_irq_handler     RTC_DriverIRQHandler                  /* RTC alarm and wake-up interrupts */
+    def_irq_handler     IOH_DriverIRQHandler                  /* IOH */
+    def_irq_handler     MAILBOX_DriverIRQHandler              /* Mailbox interrupt (present on selected devices) */
+    def_irq_handler     PIN_INT4_DriverIRQHandler             /* Pin interrupt 4 or pattern match engine slice 4 int */
+    def_irq_handler     PIN_INT5_DriverIRQHandler             /* Pin interrupt 5 or pattern match engine slice 5 int */
+    def_irq_handler     PIN_INT6_DriverIRQHandler             /* Pin interrupt 6 or pattern match engine slice 6 int */
+    def_irq_handler     PIN_INT7_DriverIRQHandler             /* Pin interrupt 7 or pattern match engine slice 7 int */
+    def_irq_handler     CTIMER2_DriverIRQHandler              /* Standard counter/timer CTIMER2 */
+    def_irq_handler     CTIMER4_DriverIRQHandler              /* Standard counter/timer CTIMER4 */
+    def_irq_handler     SPIFI0_DriverIRQHandler               /* SPI flash interface */
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_IAR/LPC54114J256_cm4.icf	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,142 @@
+/*
+** ###################################################################
+**     Processors:          LPC54114J256BD64_M4
+**                          LPC54114J256UK49_M4
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    LPC5411x User manual Rev. 1.1 25 May 2016
+**     Version:             rev. 1.0, 2016-04-29
+**     Build:               b161227
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+define symbol __ram_vector_table__ = 1;
+
+/* Heap 1/4 of ram and stack 1/8 */
+define symbol __stack_size__=0x2000;
+define symbol __heap_size__=0x4000;
+
+define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000000E0 : 0;
+define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000000DF : 0;
+
+define symbol m_interrupts_start             = 0x00000000;
+define symbol m_interrupts_end               = 0x000000DF;
+
+define symbol m_text_start                   = 0x000000E0;
+define symbol m_text_end                     = 0x0002FFFF;
+
+define symbol m_interrupts_ram_start         = 0x20000000;
+define symbol m_interrupts_ram_end           = 0x20000000 + __ram_vector_table_offset__;
+
+define symbol m_data_start                   = m_interrupts_ram_start + __ram_vector_table_size__;
+define symbol m_data_end                     = 0x2000FFFF;
+
+define exported symbol rpmsg_sh_mem_start    = 0x20026800;
+define exported symbol rpmsg_sh_mem_end      = 0x20027FFF;
+
+define symbol m_sramx_start                  = 0x04000000;
+define symbol m_sramx_end                    = 0x04007FFF;
+
+define exported symbol core1_image_start     = 0x00030000;
+define exported symbol core1_image_end       = 0x0003FFFF;
+
+define symbol __crp_start__                  = 0x000002FC;
+define symbol __crp_end__                    = 0x000002FF;
+
+define symbol __ram_iap_start__              = 0x2000FFE0;
+define symbol __ram_iap_end__                = 0x2000FFFF;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0800;
+}
+
+define exported symbol __VECTOR_TABLE  = m_interrupts_start;
+define exported symbol __VECTOR_RAM    = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
+
+define memory mem with size = 4G;
+define region TEXT_region             = mem:[from m_interrupts_start to m_interrupts_end]
+                                      | mem:[from m_text_start to m_text_end]
+                                      - mem:[from  __crp_start__ to __crp_end__];
+define region DATA_region             = mem:[from m_data_start to m_data_end]
+                                      - mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_end__];
+define region CSTACK_region           = mem:[from __ram_iap_start__-__size_cstack__ to __ram_iap_start__-1];
+define region SRAMX_region            = mem:[from m_sramx_start to m_sramx_end];
+define region CRP_region              = mem:[from  __crp_start__ to __crp_end__];
+define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
+
+define region rpmsg_sh_mem_region     = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+define region core1_region = mem:[from core1_image_start to core1_image_end];
+define block SEC_CORE_IMAGE_WBLOCK          { section  __sec_core };
+
+initialize by copy { readwrite };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize  { section .noinit };
+do not initialize  { section rpmsg_sh_mem_section };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in SRAMX_region                       { section sramx };
+place in CSTACK_region                      { block CSTACK };
+place in CRP_region                         { section .crp };
+place in m_interrupts_ram_region            { section m_interrupts_ram };
+place in rpmsg_sh_mem_region                { section rpmsg_sh_mem_section };
+
+place in core1_region                       { block SEC_CORE_IMAGE_WBLOCK };

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_IAR/libpower.a has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/TOOLCHAIN_IAR/startup_LPC54114_cm4.S	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,567 @@
+;/*****************************************************************************
+; * @file:    startup_LPC54114_cm4.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File
+; *           LPC54114_cm4
+; * @version: 1.0
+; * @date:    2016-4-29
+; *----------------------------------------------------------------------------
+; *
+; * Copyright: 1997 - 2016 Freescale Semiconductor,
+; *
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
+        DCD     DMA0_IRQHandler  ; DMA controller
+        DCD     GINT0_IRQHandler  ; GPIO group 0
+        DCD     GINT1_IRQHandler  ; GPIO group 1
+        DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
+        DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
+        DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
+        DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
+        DCD     UTICK0_IRQHandler  ; Micro-tick Timer
+        DCD     MRT0_IRQHandler  ; Multi-rate timer
+        DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
+        DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
+        DCD     SCT0_IRQHandler  ; SCTimer/PWM
+        DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
+        DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C)
+        DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C)
+        DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C)
+        DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C)
+        DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C)
+        DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C)
+        DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S)
+        DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S)
+        DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
+        DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
+        DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
+        DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
+        DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
+        DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
+        DCD     USB0_IRQHandler  ; USB device
+        DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
+        DCD     IOH_IRQHandler  ; IOH
+        DCD     MAILBOX_IRQHandler  ; Mailbox interrupt (present on selected devices)
+        DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
+        DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
+        DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
+        DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
+        DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
+        DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
+        DCD     Reserved54_IRQHandler  ; Reserved interrupt
+        DCD     SPIFI0_IRQHandler  ; SPI flash interface
+__Vectors_End
+
+; Code Read Protection Level (CRP)
+;    <0xFFFFFFFF=> Disabled
+;    <0x4E697370=> NO_ISP
+;    <0x12345678=> CRP1
+;    <0x87654321=> CRP2
+;    <0x43218765=> CRP3
+
+#if !defined NO_CRP
+        SECTION .crp:CODE
+__CRP
+      	DCD	0xFFFFFFFF
+__CRP_End
+#endif
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        SECTION .intvec:CODE:NOROOT(2)
+#if !defined(SLAVEBOOT)
+        DATA
+cpu_id          EQU     0xE000ED00 ; CPUID Base Register (System control block register)
+cpu_ctrl        EQU     0x40000800
+coproc_boot     EQU     0x40000804
+coproc_stack    EQU     0x40000808
+rel_vals
+                DC32    cpu_id, cpu_ctrl, coproc_boot, coproc_stack
+                DC16    0xFFF, 0xC24
+#endif
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler - shared for both cores
+Reset_Handler
+
+#if !defined(SLAVEBOOT)
+; Both the M0+ and M4 core come via this shared startup code,
+                ; but the M0+ and M4 core have different vector tables.
+                ; Determine if the core executing this code is the master or
+                ; the slave and handle each core state individually.
+shared_boot_entry
+                LDR     r6, =rel_vals
+                MOVS    r4, #0            ; Flag for slave core (0)
+                MOVS    r5, #1
+
+                ; Determine which core (M0+ or M4) this code is running on
+                ; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
+get_current_core_id
+                LDR     r0, [r6, #0]
+                LDR     r1, [r0]                        ; r1 = CPU ID status
+                LSRS    r1, r1, #4                      ; Right justify 12 CPU ID bits
+                LDRH    r2, [r6, #16]                   ; Mask for CPU ID bits
+                ANDS    r2, r1, r2                      ; r2 = ARM COrtex CPU ID
+                LDRH    r3, [r6, #18]                   ; Mask for CPU ID bits
+                CMP     r3, r2                          ; Core ID matches M4 identifier
+                BNE     get_master_status
+                MOV     r4, r5                          ; Set flag for master core (1)
+
+                ; Determine if M4 core is the master or slave
+                ; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
+get_master_status
+                LDR     r0, [r6, #4]
+                LDR     r3, [r0]                        ; r3 = SYSCON co-processor CPU control status
+                ANDS    r3, r3, r5                      ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
+
+                ; Select boot based on selected master core and core ID
+select_boot
+                EORS    r3, r3, r4                      ; r4 = (Bit 0: 0 = master, 1 = slave)
+                BNE     slave_boot
+                B       normal_boot
+
+                ; Slave boot
+slave_boot
+                LDR     r0, [r6, #8]
+                LDR     r2, [r0]                        ; r1 = SYSCON co-processor boot address
+                CMP     r2, #0                          ; Slave boot address = 0 (not set up)?
+                BEQ     cpu_sleep
+                LDR     r0, [r6, #12]
+                LDR     r1, [r0]                        ; r5 = SYSCON co-processor stack address
+                MOV     sp, r1                          ; Update slave CPU stack pointer
+                ; Be sure to update VTOR for the slave MCU to point to the
+                ; slave vector table in boot memory
+                BX      r2                              ; Jump to slave boot address
+
+                ; Slave isn't yet setup for system boot from the master
+                ; so sleep until the master sets it up and then reboots it
+cpu_sleep
+                MOV     sp, r5                          ; Will force exception if something happens
+cpu_sleep_wfi
+                WFI                                     ; Sleep forever until master reboots
+                B       cpu_sleep_wfi
+#endif ; defined(SLAVEBOOT)
+
+                ; Normal boot for master/slave
+normal_boot
+                LDR     r0, =SystemInit
+                BLX     r0
+                LDR     r0, =__iar_program_start
+                BX      r0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK WDT_BOD_IRQHandler
+        PUBWEAK WDT_BOD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+        LDR     R0, =WDT_BOD_DriverIRQHandler
+        BX      R0
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+        PUBWEAK GINT0_IRQHandler
+        PUBWEAK GINT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+        LDR     R0, =GINT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK GINT1_IRQHandler
+        PUBWEAK GINT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+        LDR     R0, =GINT1_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT0_IRQHandler
+        PUBWEAK PIN_INT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+        LDR     R0, =PIN_INT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT1_IRQHandler
+        PUBWEAK PIN_INT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+        LDR     R0, =PIN_INT1_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT2_IRQHandler
+        PUBWEAK PIN_INT2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+        LDR     R0, =PIN_INT2_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT3_IRQHandler
+        PUBWEAK PIN_INT3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+        LDR     R0, =PIN_INT3_DriverIRQHandler
+        BX      R0
+        PUBWEAK UTICK0_IRQHandler
+        PUBWEAK UTICK0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+        LDR     R0, =UTICK0_DriverIRQHandler
+        BX      R0
+        PUBWEAK MRT0_IRQHandler
+        PUBWEAK MRT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+        LDR     R0, =MRT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER0_IRQHandler
+        PUBWEAK CTIMER0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+        LDR     R0, =CTIMER0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER1_IRQHandler
+        PUBWEAK CTIMER1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+        LDR     R0, =CTIMER1_DriverIRQHandler
+        BX      R0
+        PUBWEAK SCT0_IRQHandler
+        PUBWEAK SCT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+        LDR     R0, =SCT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER3_IRQHandler
+        PUBWEAK CTIMER3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+        LDR     R0, =CTIMER3_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM0_IRQHandler
+        PUBWEAK FLEXCOMM0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+        LDR     R0, =FLEXCOMM0_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM1_IRQHandler
+        PUBWEAK FLEXCOMM1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+        LDR     R0, =FLEXCOMM1_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM2_IRQHandler
+        PUBWEAK FLEXCOMM2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+        LDR     R0, =FLEXCOMM2_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM3_IRQHandler
+        PUBWEAK FLEXCOMM3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+        LDR     R0, =FLEXCOMM3_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM4_IRQHandler
+        PUBWEAK FLEXCOMM4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+        LDR     R0, =FLEXCOMM4_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM5_IRQHandler
+        PUBWEAK FLEXCOMM5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+        LDR     R0, =FLEXCOMM5_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM6_IRQHandler
+        PUBWEAK FLEXCOMM6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+        LDR     R0, =FLEXCOMM6_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM7_IRQHandler
+        PUBWEAK FLEXCOMM7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+        LDR     R0, =FLEXCOMM7_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_SEQA_IRQHandler
+        PUBWEAK ADC0_SEQA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+        LDR     R0, =ADC0_SEQA_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_SEQB_IRQHandler
+        PUBWEAK ADC0_SEQB_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+        LDR     R0, =ADC0_SEQB_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_THCMP_IRQHandler
+        PUBWEAK ADC0_THCMP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+        LDR     R0, =ADC0_THCMP_DriverIRQHandler
+        BX      R0
+        PUBWEAK DMIC0_IRQHandler
+        PUBWEAK DMIC0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+        LDR     R0, =DMIC0_DriverIRQHandler
+        BX      R0
+        PUBWEAK HWVAD0_IRQHandler
+        PUBWEAK HWVAD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+        LDR     R0, =HWVAD0_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB0_NEEDCLK_IRQHandler
+        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK USB0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+        LDR     R0, =USB0_DriverIRQHandler
+        BX      R0
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+        LDR     R0, =RTC_DriverIRQHandler
+        BX      R0
+        PUBWEAK IOH_IRQHandler
+        PUBWEAK IOH_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+IOH_IRQHandler
+        LDR     R0, =IOH_DriverIRQHandler
+        BX      R0
+        PUBWEAK MAILBOX_IRQHandler
+        PUBWEAK MAILBOX_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MAILBOX_IRQHandler
+        LDR     R0, =MAILBOX_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT4_IRQHandler
+        PUBWEAK PIN_INT4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+        LDR     R0, =PIN_INT4_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT5_IRQHandler
+        PUBWEAK PIN_INT5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+        LDR     R0, =PIN_INT5_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT6_IRQHandler
+        PUBWEAK PIN_INT6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+        LDR     R0, =PIN_INT6_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT7_IRQHandler
+        PUBWEAK PIN_INT7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+        LDR     R0, =PIN_INT7_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER2_IRQHandler
+        PUBWEAK CTIMER2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+        LDR     R0, =CTIMER2_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER4_IRQHandler
+        PUBWEAK CTIMER4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+        LDR     R0, =CTIMER4_DriverIRQHandler
+        BX      R0
+        PUBWEAK Reserved54_IRQHandler
+        PUBWEAK Reserved54_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved54_IRQHandler
+        LDR     R0, =Reserved54_DriverIRQHandler
+        BX      R0
+        PUBWEAK SPIFI0_IRQHandler
+        PUBWEAK SPIFI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+        LDR     R0, =SPIFI0_DriverIRQHandler
+        BX      R0
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+IOH_DriverIRQHandler
+MAILBOX_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+Reserved54_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+DefaultISR
+        B .
+
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/cmsis_nvic.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if defined(__CC_ARM)
+extern uint32_t Image$$VECTOR_RAM$$Base[];
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#else
+extern uint32_t __VECTOR_RAM[];
+#endif
+
+/* Symbols defined by the linker script */
+#define NVIC_NUM_VECTORS        (16 + 40)         // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM)    // Vectors positioned at start of RAM
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/system_LPC54114_cm4.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,359 @@
+/*
+** ###################################################################
+**     Processors:          LPC54114J256BD64_cm4
+**                          LPC54114J256UK49_cm4
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    LPC5411x User manual Rev. 1.0 16 February 2016
+**     Version:             rev. 1.0, 2016-04-29
+**     Build:               b160525
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-04-29)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54114_cm4
+ * @version 1.0
+ * @date 2016-04-29
+ * @brief Device specific configuration file for LPC54114_cm4 (implementation
+ *        file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define NVALMAX (0x100)
+#define PVALMAX (0x20)
+#define MVALMAX (0x8000)
+#define PLL_SSCG0_MDEC_VAL_P (0)                                 /* MDEC is in bits  16 downto 0 */
+#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits  9 downto 0 */
+#define PLL_NDEC_VAL_P (0)                                       /* NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
+
+extern void *__Vectors;
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, 
+                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+
+static uint32_t GetWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1;
+    freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+    return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+}
+
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0xFFF:
+            n = 0;
+            break;
+        case 0x302:
+            n = 1;
+            break;
+        case 0x202:
+            n = 2;
+            break;
+        default:
+            x = 0x080;
+            n = 0xFFFFFFFF;
+            for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--)
+            {
+                x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+            }
+            break;
+    }
+    return n;
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0xFF:
+            p = 0;
+            break;
+        case 0x62:
+            p = 1;
+            break;
+        case 0x42:
+            p = 2;
+            break;
+        default:
+            x = 0x10;
+            p = 0xFFFFFFFF;
+            for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--)
+            {
+                x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+            }
+            break;
+    }
+    return p;
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0xFFFFF:
+            m = 0;
+            break;
+        case 0x18003:
+            m = 1;
+            break;
+        case 0x10003:
+            m = 2;
+            break;
+        default:
+            x = 0x04000;
+            m = 0xFFFFFFFF;
+            for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--)
+            {
+                x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+                if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+            }
+            break;
+    }
+    return m;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FF);
+        if (preDiv == 0)
+        {
+            preDiv = 1;
+        }
+    }
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
+        if (postDiv == 0)
+        {
+            postDiv = 2;
+        }
+    }
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFF);
+    /* Extra multiply by 2 needed? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0)
+    {
+        mMult = mMult << 1;
+    }
+    if (mMult == 0)
+    {
+        mMult = 1;
+    }
+    return mMult;
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) || (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
+#endif                                                 /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+    SCB->VTOR = (uint32_t)&__Vectors;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+    SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate(void)
+{
+    uint32_t clkRate = 0;
+    uint32_t prediv, postdiv;
+    uint64_t workRate;
+
+    switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+    {
+        case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+            switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = GetWdtOscFreq();
+                    break;
+                default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
+                    if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
+                    {
+                        clkRate = CLK_FRO_96MHZ;
+                    }
+                    else
+                    {
+                        clkRate = CLK_FRO_48MHZ;
+                    }
+                    break;
+            }
+            break;
+        case 0x02: /* System PLL clock (pll_clk)*/
+            switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = GetWdtOscFreq();
+                    break;
+                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+                    clkRate = CLK_RTC_32K_CLK;
+                    break;
+                default:
+                    break;
+            }
+            if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
+            {
+                /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+                prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
+                postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
+                /* Adjust input clock */
+                clkRate = clkRate / prediv;
+                /* If using the SS, use the multiplier */
+                if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK)
+                {
+                    /* MDEC used for rate */
+                    workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0);
+                }
+                else
+                {
+                    /* SS multipler used for rate */
+                    workRate = 0;
+                    /* Adjust by fractional */
+                    workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800);
+                }
+                clkRate = workRate / ((uint64_t)postdiv);
+            }
+            break;
+        case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+            clkRate = CLK_RTC_32K_CLK;
+            break;
+        default:
+            break;
+    }
+    SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/system_LPC54114_cm4.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,119 @@
+/*
+** ###################################################################
+**     Processors:          LPC54114J256BD64_cm4
+**                          LPC54114J256UK49_cm4
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    LPC5411x User manual Rev. 1.0 16 February 2016
+**     Version:             rev. 1.0, 2016-04-29
+**     Build:               b160525
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-04-29)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54114_cm4
+ * @version 1.0
+ * @date 2016-04-29
+ * @brief Device specific configuration file for LPC54114_cm4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC54114_cm4_H_
+#define _SYSTEM_LPC54114_cm4_H_                  /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN                            0u           /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_LPC54114_cm4_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/cmsis.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC54114 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "fsl_device_registers.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/fsl_device_registers.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC54114J256BD64_cm4) || defined(CPU_LPC54114J256UK49_cm4))
+
+#define LPC54114_cm4_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC54114_cm4.h"
+/* CPU specific feature definitions */
+#include "LPC54114_cm4_features.h"
+
+#elif (defined(CPU_LPC54114J256BD64_cm0plus) || defined(CPU_LPC54114J256UK49_cm0plus))
+
+#define LPC54114_cm0plus_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC54114_cm0plus.h"
+/* CPU specific feature definitions */
+#include "LPC54114_cm0plus_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_adc.h"
+#include "fsl_clock.h"
+
+static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
+static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+
+static uint32_t ADC_GetInstance(ADC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_ADC_COUNT; instance++)
+    {
+        if (s_adcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_ADC_COUNT);
+
+    return instance;
+}
+
+void ADC_Init(ADC_Type *base, const adc_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32 = 0U;
+
+    /* Enable clock. */
+    CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+
+    /* Disable the interrupts. */
+    base->INTEN = 0U; /* Quickly disable all the interrupts. */
+
+    /* Configure the ADC block. */
+    tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber);
+
+    /* Async or Sync clock mode. */
+    switch (config->clockMode)
+    {
+        case kADC_ClockAsynchronousMode:
+            tmp32 |= ADC_CTRL_ASYNMODE_MASK;
+            break;
+        default: /* kADC_ClockSynchronousMode */
+            break;
+    }
+
+    /* Resolution. */
+    tmp32 |= ADC_CTRL_RESOL(config->resolution);
+
+    /* Bypass calibration. */
+    if (config->enableBypassCalibration)
+    {
+        tmp32 |= ADC_CTRL_BYPASSCAL_MASK;
+    }
+
+    /* Sample time clock count. */
+    tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber);
+
+    base->CTRL = tmp32;
+}
+
+void ADC_GetDefaultConfig(adc_config_t *config)
+{
+    config->clockMode = kADC_ClockSynchronousMode;
+    config->clockDividerNumber = 0U;
+    config->resolution = kADC_Resolution12bit;
+    config->enableBypassCalibration = false;
+    config->sampleTimeNumber = 0U;
+}
+
+void ADC_Deinit(ADC_Type *base)
+{
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+}
+
+bool ADC_DoSelfCalibration(ADC_Type *base)
+{
+    uint32_t i;
+
+    /* Enable the converter. */
+    /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down.
+       This bit should be set after at least 10 ms after the ADC is powered on. */
+    base->STARTUP = ADC_STARTUP_ADC_ENA_MASK;
+    for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */
+    {
+        __ASM("NOP");
+    }
+    if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK))
+    {
+        return false; /* ADC is not powered up. */
+    }
+
+    /* If not in by-pass mode, do the calibration. */
+    if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) &&
+        (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK)))
+    {
+        /* Calibration is needed, do it now. */
+        base->CALIB = ADC_CALIB_CALIB_MASK;
+        i = 0xF0000;
+        while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i))
+        {
+        }
+        if (i == 0U)
+        {
+            return false; /* Calibration timeout. */
+        }
+    }
+
+    /* A dummy conversion cycle will be performed. */
+    base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK;
+    i = 0x7FFFF;
+    while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i))
+    {
+    }
+    if (i == 0U)
+    {
+        return false;
+    }
+
+    return true;
+}
+
+void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
+            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
+
+    /* Polarity for tirgger signal. */
+    switch (config->triggerPolarity)
+    {
+        case kADC_TriggerPolarityPositiveEdge:
+            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
+            break;
+        default: /* kADC_TriggerPolarityNegativeEdge */
+            break;
+    }
+
+    /* Bypass the clock Sync. */
+    if (config->enableSyncBypass)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
+    }
+
+    /* Interrupt point. */
+    switch (config->interruptMode)
+    {
+        case kADC_InterruptForEachSequence:
+            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
+            break;
+        default: /* kADC_InterruptForEachConversion */
+            break;
+    }
+
+    /* One trigger for a conversion, or for a sequence. */
+    if (config->enableSingleStep)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
+    }
+
+    base->SEQ_CTRL[0] = tmp32;
+}
+
+void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
+            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
+
+    /* Polarity for tirgger signal. */
+    switch (config->triggerPolarity)
+    {
+        case kADC_TriggerPolarityPositiveEdge:
+            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
+            break;
+        default: /* kADC_TriggerPolarityPositiveEdge */
+            break;
+    }
+
+    /* Bypass the clock Sync. */
+    if (config->enableSyncBypass)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
+    }
+
+    /* Interrupt point. */
+    switch (config->interruptMode)
+    {
+        case kADC_InterruptForEachSequence:
+            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
+            break;
+        default: /* kADC_InterruptForEachConversion */
+            break;
+    }
+
+    /* One trigger for a conversion, or for a sequence. */
+    if (config->enableSingleStep)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
+    }
+
+    base->SEQ_CTRL[1] = tmp32;
+}
+
+bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
+{
+    assert(info != NULL);
+
+    uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */
+
+    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
+
+    return true;
+}
+
+bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
+{
+    assert(info != NULL);
+
+    uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */
+
+    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
+
+    return true;
+}
+
+bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info)
+{
+    assert(info != NULL);
+    assert(channel < ADC_DAT_COUNT);
+
+    uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */
+
+    if (0U == (ADC_DAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK);
+
+    return true;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,664 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ADC_H__
+#define __FSL_ADC_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_adc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief ADC driver version 1.0.0. */
+#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief Flags
+ */
+enum _adc_status_flags
+{
+    kADC_ThresholdCompareFlagOnChn0 = 1U << 0U,   /*!< Threshold comparison event on Channel 0. */
+    kADC_ThresholdCompareFlagOnChn1 = 1U << 1U,   /*!< Threshold comparison event on Channel 1. */
+    kADC_ThresholdCompareFlagOnChn2 = 1U << 2U,   /*!< Threshold comparison event on Channel 2. */
+    kADC_ThresholdCompareFlagOnChn3 = 1U << 3U,   /*!< Threshold comparison event on Channel 3. */
+    kADC_ThresholdCompareFlagOnChn4 = 1U << 4U,   /*!< Threshold comparison event on Channel 4. */
+    kADC_ThresholdCompareFlagOnChn5 = 1U << 5U,   /*!< Threshold comparison event on Channel 5. */
+    kADC_ThresholdCompareFlagOnChn6 = 1U << 6U,   /*!< Threshold comparison event on Channel 6. */
+    kADC_ThresholdCompareFlagOnChn7 = 1U << 7U,   /*!< Threshold comparison event on Channel 7. */
+    kADC_ThresholdCompareFlagOnChn8 = 1U << 8U,   /*!< Threshold comparison event on Channel 8. */
+    kADC_ThresholdCompareFlagOnChn9 = 1U << 9U,   /*!< Threshold comparison event on Channel 9. */
+    kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */
+    kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */
+    kADC_OverrunFlagForChn0 =
+        1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */
+    kADC_OverrunFlagForChn1 =
+        1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */
+    kADC_OverrunFlagForChn2 =
+        1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */
+    kADC_OverrunFlagForChn3 =
+        1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */
+    kADC_OverrunFlagForChn4 =
+        1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */
+    kADC_OverrunFlagForChn5 =
+        1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */
+    kADC_OverrunFlagForChn6 =
+        1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */
+    kADC_OverrunFlagForChn7 =
+        1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */
+    kADC_OverrunFlagForChn8 =
+        1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */
+    kADC_OverrunFlagForChn9 =
+        1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */
+    kADC_OverrunFlagForChn10 =
+        1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */
+    kADC_OverrunFlagForChn11 =
+        1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */
+    kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */
+    kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */
+    kADC_ConvSeqAInterruptFlag = 1U << 28U,    /*!< Sequence A interrupt/DMA trigger. */
+    kADC_ConvSeqBInterruptFlag = 1U << 29U,    /*!< Sequence B interrupt/DMA trigger. */
+    kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */
+    kADC_OverrunInterruptFlag = 1U << 31U,          /*!< Overrun interrupt flag. */
+};
+
+/*!
+ * @brief Interrupts
+ * @note Not all the interrupt options are listed here
+ */
+enum _adc_interrupt_enable
+{
+    kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
+                                                                   conversion in sequence A, or entire sequence. */
+    kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
+                                                                   conversion in sequence B, or entire sequence. */
+    kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of
+                                                                 the channel data registers will cause an overrun
+                                                                 interrupt/DMA trigger. */
+};
+
+/*!
+ * @brief Define selection of clock mode.
+ */
+typedef enum _adc_clock_mode
+{
+    kADC_ClockSynchronousMode =
+        0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */
+    kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */
+} adc_clock_mode_t;
+
+/*!
+ * @brief Define selection of resolution.
+ */
+typedef enum _adc_resolution
+{
+    kADC_Resolution6bit = 0U,  /*!< 6-bit resolution. */
+    kADC_Resolution8bit = 1U,  /*!< 8-bit resolution. */
+    kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */
+    kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */
+} adc_resolution_t;
+
+/*!
+ * @brief Define selection of polarity of selected input trigger for conversion sequence.
+ */
+typedef enum _adc_trigger_polarity
+{
+    kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */
+    kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */
+} adc_trigger_polarity_t;
+
+/*!
+ * @brief Define selection of conversion sequence's priority.
+ */
+typedef enum _adc_priority
+{
+    kADC_PriorityLow = 0U,  /*!< This sequence would be preempted when another sequence is started. */
+    kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */
+} adc_priority_t;
+
+/*!
+ * @brief Define selection of conversion sequence's interrupt.
+ */
+typedef enum _adc_seq_interrupt_mode
+{
+    kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each
+                                               individual ADC conversion inside this conversion sequence. */
+    kADC_InterruptForEachSequence = 1U,   /*!< The sequence interrupt/DMA trigger will be set when the entire set of
+                                               this sequence conversions completes. */
+} adc_seq_interrupt_mode_t;
+
+/*!
+ * @brief Define status of threshold compare result.
+ */
+typedef enum _adc_threshold_compare_status
+{
+    kADC_ThresholdCompareInRange = 0U,    /*!< LOW threshold <= conversion value <= HIGH threshold. */
+    kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */
+    kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */
+} adc_threshold_compare_status_t;
+
+/*!
+ * @brief Define status of threshold crossing detection result.
+ */
+typedef enum _adc_threshold_crossing_status
+{
+    /* The conversion on this channel had the same relationship (above or below) to the threshold value established by
+     * the designated LOW threshold value as did the previous conversion on this channel. */
+    kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */
+
+    /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this
+     * channel was above the threshold value established by the designated LOW threshold value and the current sample is
+     * below that threshold. */
+    kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */
+
+    /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this
+     * channel was below the threshold value established by the designated LOW threshold value and the current sample is
+     * above that threshold. */
+    kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */
+} adc_threshold_crossing_status_t;
+
+/*!
+ * @brief Define interrupt mode for threshold compare event.
+ */
+typedef enum _adc_threshold_interrupt_mode
+{
+    kADC_ThresholdInterruptDisabled = 0U,   /*!< Threshold comparison interrupt is disabled. */
+    kADC_ThresholdInterruptOnOutside = 1U,  /*!< Threshold comparison interrupt is enabled on outside threshold. */
+    kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */
+} adc_threshold_interrupt_mode_t;
+
+/*!
+ * @brief Define structure for configuring the block.
+ */
+typedef struct _adc_config
+{
+    adc_clock_mode_t clockMode;   /*!< Select the clock mode for ADC converter. */
+    uint32_t clockDividerNumber;  /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode"
+                                       field. The divider would be plused by 1 based on the value in this field. The
+                                       available range is in 8 bits. */
+    adc_resolution_t resolution;  /*!< Select the conversion bits. */
+    bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is
+                                       powered-up. Re-calibration may be warranted periodically - especially if
+                                       operating conditions have changed. To enable this option would avoid the need to
+                                       calibrate if offset error is not a concern in the application. */
+    uint32_t sampleTimeNumber;    /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then,
+                                       to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/
+} adc_config_t;
+
+/*!
+ * @brief Define structure for configuring conversion sequence.
+ */
+typedef struct _adc_conv_seq_config
+{
+    uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this
+                               sequence is launched. The masked channels would be involved in current conversion
+                               sequence, beginning with the lowest-order. The available range is in 12-bit. */
+    uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this
+                               conversion sequence to be initiated. The available range is 6-bit.*/
+    adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */
+    bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization
+                                flip-flop stages and therefore shorten the time between the trigger input signal and the
+                                start of a conversion. */
+    bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next
+                                channel in the sequence instead of the default response of launching an entire sequence
+                                of conversions. */
+    adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */
+} adc_conv_seq_config_t;
+
+/*!
+ * @brief Define structure of keeping conversion result information.
+ */
+typedef struct _adc_result_info
+{
+    uint32_t result;                                         /*!< Keey the conversion data value. */
+    adc_threshold_compare_status_t thresholdCompareStatus;   /*!< Keep the threshold compare status. */
+    adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
+    uint32_t channelNumber;                                  /*!< Keep the channel number for this conversion. */
+    bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */
+    /* The data available flag would be returned by the reading result API. */
+} adc_result_info_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization and Deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initialize the ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_config_t.
+ */
+void ADC_Init(ADC_Type *base, const adc_config_t *config);
+
+/*!
+ * @brief Deinitialize the ADC module.
+ *
+ * @param base ADC peripheral base address.
+ */
+void ADC_Deinit(ADC_Type *base);
+
+/*!
+ * @brief Gets an available pre-defined settings for initial configuration.
+ *
+ * This function initializes the initial configuration structure with an available settings. The default values are:
+ * @code
+ *   config->clockMode = kADC_ClockSynchronousMode;
+ *   config->clockDividerNumber = 0U;
+ *   config->resolution = kADC_Resolution12bit;
+ *   config->enableBypassCalibration = false;
+ *   config->sampleTimeNumber = 0U;
+ * @endcode
+ * @param config Pointer to configuration structure.
+ */
+void ADC_GetDefaultConfig(adc_config_t *config);
+
+/*!
+ * @brief Do the self hardware calibration.
+ *
+ * @param base ADC peripheral base address.
+ * @retval true  Calibration succeed.
+ * @retval false Calibration failed.
+ */
+bool ADC_DoSelfCalibration(ADC_Type *base);
+
+/*!
+ * @brief Enable the internal temperature sensor measurement.
+ *
+ * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor
+ * instead of external pin.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3);
+    }
+    else
+    {
+        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Control conversion sequence A.
+ * @{
+ */
+
+/*!
+ * @brief Enable the conversion sequence A.
+ *
+ * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
+ * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
+ * sequence during changing the sequence's setting.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+}
+
+/*!
+ * @brief Configure the conversion sequence A.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
+ */
+void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
+
+/*!
+ * @brief Do trigger the sequence's conversion by software.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK;
+}
+
+/*!
+ * @brief Enable the burst conversion of sequence A.
+ *
+ * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be
+ * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
+ * currently in process will be completed before cnversions are terminated.
+ * Note that a new sequence could begin just before the burst mode is disabled.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable this feature.
+ */
+static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK;
+    }
+}
+
+/*!
+ * @brief Set the high priority for conversion sequence A.
+ *
+ * @param base ADC peripheral bass address.
+ */
+static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Control conversion sequence B.
+ * @{
+ */
+
+/*!
+ * @brief Enable the conversion sequence B.
+ *
+ * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
+ * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
+ * sequence during changing the sequence's setting.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+}
+
+/*!
+ * @brief Configure the conversion sequence B.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
+ */
+void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
+
+/*!
+ * @brief Do trigger the sequence's conversion by software.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base)
+{
+    base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK;
+}
+
+/*!
+ * @brief Enable the burst conversion of sequence B.
+ *
+ * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be
+ * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
+ * currently in process will be completed before cnversions are terminated.
+ * Note that a new sequence could begin just before the burst mode is disabled.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable this feature.
+ */
+static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK;
+    }
+}
+
+/*!
+ * @brief Set the high priority for conversion sequence B.
+ *
+ * @param base ADC peripheral bass address.
+ */
+static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Data result.
+ * @{
+ */
+
+/*!
+ * @brief Get the global ADC conversion infomation of sequence A.
+ *
+ * @param base ADC peripheral base address.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
+
+/*!
+ * @brief Get the global ADC conversion infomation of sequence B.
+ *
+ * @param base ADC peripheral base address.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
+
+/*!
+ * @brief Get the channel's ADC conversion completed under each conversion sequence.
+ *
+ * @param base ADC peripheral base address.
+ * @param channel The indicated channel number.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info);
+
+/* @} */
+
+/*!
+ * @name Threshold function.
+ * @{
+ */
+
+/*!
+ * @brief Set the threshhold pair 0 with low and high value.
+ *
+ * @param base ADC peripheral base address.
+ * @param lowValue LOW threshold value.
+ * @param highValue HIGH threshold value.
+ */
+static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
+{
+    base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue);
+    base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue);
+}
+
+/*!
+ * @brief Set the threshhold pair 1 with low and high value.
+ *
+ * @param base ADC peripheral base address.
+ * @param lowValue LOW threshold value. The available value is with 12-bit.
+ * @param highValue HIGH threshold value. The available value is with 12-bit.
+ */
+static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
+{
+    base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue);
+    base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue);
+}
+
+/*!
+ * @brief Set given channels to apply the threshold pare 0.
+ *
+ * @param base ADC peripheral base address.
+ * @param channelMask Indicated channels' mask.
+ */
+static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask)
+{
+    base->CHAN_THRSEL &= ~(channelMask);
+}
+
+/*!
+ * @brief Set given channels to apply the threshold pare 1.
+ *
+ * @param base ADC peripheral base address.
+ * @param channelMask Indicated channels' mask.
+ */
+static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask)
+{
+    base->CHAN_THRSEL |= channelMask;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts.
+ * @{
+ */
+
+/*!
+ * @brief Enable interrupts for conversion sequences.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable.
+ */
+static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
+{
+    base->INTEN |= (0x7 & mask);
+}
+
+/*!
+ * @brief Disable interrupts for conversion sequence.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable.
+ */
+static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
+{
+    base->INTEN &= ~(0x7 & mask);
+}
+
+/*!
+ * @brief Enable the interrupt of shreshold compare event for each channel.
+ *
+ * @param base ADC peripheral base address.
+ * @param channel Channel number.
+ * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
+ */
+static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
+                                                       uint32_t channel,
+                                                       adc_threshold_interrupt_mode_t mode)
+{
+    base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
+}
+
+/* @} */
+
+/*!
+ * @name Status.
+ * @{
+ */
+
+/*!
+ * @brief Get status flags of ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @return Mask of status flags of module, see to #_adc_status_flags.
+ */
+static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
+{
+    return base->FLAGS;
+}
+
+/*!
+ * @brief Clear status flags of ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of status flags of module, see to #_adc_status_flags.
+ */
+static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
+{
+    base->FLAGS = mask; /* Write 1 to clear. */
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* __FSL_ADC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1357 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_clock.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define NVALMAX (0x100U)
+#define PVALMAX (0x20U)
+#define MVALMAX (0x8000U)
+
+#define PLL_MAX_N_DIV 0x100U
+
+#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000444U)
+#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x01000430U)
+/*--------------------------------------------------------------------------
+!!! If required these #defines can be moved to chip library file
+----------------------------------------------------------------------------*/
+
+#define PLL_SSCG0_MDEC_VAL_P (0U)                                /* MDEC is in bits  16 downto 0 */
+#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits  9 downto 0 */
+#define PLL_NDEC_VAL_P (0U)                                      /* NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
+
+#define PLL_MIN_CCO_FREQ_MHZ (75000000U)
+#define PLL_MAX_CCO_FREQ_MHZ (150000000U)
+#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */
+#define PLL_MIN_IN_SSMODE (2000000U)
+#define PLL_MAX_IN_SSMODE (4000000U)
+
+/* Middle of the range values for spread-spectrum */
+#define PLL_SSCG_MF_FREQ_VALUE 4U
+#define PLL_SSCG_MC_COMP_VALUE 2U
+#define PLL_SSCG_MR_DEPTH_VALUE 4U
+#define PLL_SSCG_DITHER_VALUE 0U
+
+/* PLL NDEC reg */
+#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
+/* PLL PDEC reg */
+#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
+/* SSCG control0 */
+#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M)
+
+/* SSCG control1 */
+#define PLL_SSCG1_MD_FRACT_P 0U
+#define PLL_SSCG1_MD_INT_P 11U
+#define PLL_SSCG1_MD_FRACT_M (0x7FFUL << PLL_SSCG1_MD_FRACT_P)
+#define PLL_SSCG1_MD_INT_M (0xFFUL << PLL_SSCG1_MD_INT_P)
+
+#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M)
+#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M)
+
+/* Saved value of PLL output rate, computed whenever needed to save run-time
+   computation on each call to retrive the PLL rate. */
+static uint32_t s_Pll_Freq;
+
+uint32_t g_I2S_Mclk_Freq = 0U;
+
+/** External clock rate on the CLKIN pin in Hz. If not used,
+    set this to 0. Otherwise, set it to the exact rate in Hz this pin is
+    being driven at. */
+const uint32_t g_Ext_Clk_Freq = 0U;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N);
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC);
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P);
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC);
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M);
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC);
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg);
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);
+/* Get the greatest common divisor */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
+/* Set PLL output based on desired output rate */
+static pll_error_t CLOCK_GetPllConfig(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS);
+/* Update local PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+
+static const uint8_t wdtFreqLookup[32] = {0,  8,  12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41,
+                                          42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+    bool final_descriptor = false;
+    uint8_t mux;
+    uint8_t pos;
+    uint32_t i;
+    volatile uint32_t *pClkSel;
+
+    pClkSel = &(SYSCON->MAINCLKSELA);
+
+    for (i = 0U; (i <= 2U) && (!final_descriptor); i++)
+    {
+        connection = (clock_attach_id_t)(connection >> (i * 12U)); /* pick up next descriptor */
+        mux = (uint8_t)connection;
+        if (connection)
+        {
+            pos = ((connection & 0xf00U) >> 8U) - 1U;
+            if (mux == CM_ASYNCAPB)
+            {
+                ASYNC_SYSCON->ASYNCAPBCLKSELA = pos;
+            }
+            else
+            {
+                pClkSel[mux] = pos;
+            }
+        }
+        else
+        {
+            final_descriptor = true;
+        }
+    }
+}
+
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
+{
+    volatile uint32_t *pClkDiv;
+
+    pClkDiv = &(SYSCON->SYSTICKCLKDIV);
+    if (reset)
+    {
+        pClkDiv[div_name] = 1U << 29U;
+    }
+    if (divided_by_value == 0U) /* halt */
+    {
+        pClkDiv[div_name] = 1U << 30U;
+    }
+    else
+    {
+        pClkDiv[div_name] = (divided_by_value - 1U);
+    }
+}
+
+/* Set FRO Clocking */
+status_t CLOCK_SetupFROClocking(uint32_t iFreq)
+{
+    uint32_t usb_adj;
+    if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U))
+    {
+        return kStatus_Fail;
+    }
+    /* Power up the FRO and set this as the base clock */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
+    /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */
+    usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT;
+    if (iFreq > 12000000U)
+    {
+        if (iFreq == 96000000U)
+        {
+            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) |
+                              SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
+                              SYSCON_FROCTRL_HSPDCLK(1);
+        }
+        else
+        {
+            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) |
+                              SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
+                              SYSCON_FROCTRL_HSPDCLK(1);
+        }
+    }
+    else
+    {
+        SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1);
+    }
+
+    return 0U;
+}
+
+uint32_t CLOCK_GetFro12MFreq(void)
+{
+    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U;
+}
+
+uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return (g_Ext_Clk_Freq);
+}
+uint32_t CLOCK_GetWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if (SYSCON->PDRUNCFG[kPDRUNCFG_PD_WDT_OSC >> 8UL] & (1UL << (kPDRUNCFG_PD_WDT_OSC & 0xffU)) )
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
+        freq_sel =
+            wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel);
+    }
+}
+
+uint32_t CLOCK_GetFroHfFreq(void)
+{
+    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ?
+                                                        0 :
+                                                        (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U :
+                                                                                                      48000000U;
+}
+
+uint32_t CLOCK_GetPllOutFreq(void)
+{
+    return s_Pll_Freq;
+}
+
+uint32_t CLOCK_GetOsc32KFreq(void)
+{
+    return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */
+}
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ?
+               CLOCK_GetFro12MFreq() :
+               ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ?
+               CLOCK_GetExtClkFreq() :
+               ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ?
+               CLOCK_GetWdtOscFreq() :
+               ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ?
+               CLOCK_GetFroHfFreq() :
+               (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() :
+                                             (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U;
+}
+uint32_t CLOCK_GetI2SMClkFreq(void)
+{
+    return g_I2S_Mclk_Freq;
+}
+
+uint32_t CLOCK_GetAsyncApbClkFreq(void)
+{
+    async_clock_src_t clkSrc;
+    uint32_t clkRate;
+
+    clkSrc = CLOCK_GetAsyncApbClkSrc();
+
+    switch (clkSrc)
+    {
+        case kCLOCK_AsyncMainClk:
+            clkRate = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_AsyncFro12Mhz:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
+{
+    return (SYSCON->FXCOMCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->FXCOMCLKSEL[id] == 1U) ?
+                                             CLOCK_GetFroHfFreq() :
+                                             (SYSCON->FXCOMCLKSEL[id] == 2U) ?
+                                             CLOCK_GetPllOutFreq() :
+                                             (SYSCON->FXCOMCLKSEL[id] == 3U) ?
+                                             CLOCK_GetI2SMClkFreq() :
+                                             (SYSCON->FXCOMCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U;
+}
+
+uint32_t CLOCK_GetFRGInputClock(void)
+{
+    return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : (SYSCON->FRGCLKSEL == 1U) ?
+                                       CLOCK_GetPllOutFreq() :
+                                       (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : (SYSCON->FRGCLKSEL == 3U) ?
+                                                                   CLOCK_GetFroHfFreq() :
+                                                                   0U;
+}
+
+uint32_t CLOCK_SetFRGClock(uint32_t freq)
+{
+    uint32_t input = CLOCK_GetFRGInputClock();
+    uint32_t mul;
+
+    if ((freq > 48000000) || (freq > input) || (input / freq >= 2))
+    {
+        /* FRG output frequency should be less than equal to 48MHz */
+        return 0;
+    }
+    else
+    {
+        mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);
+        SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK;
+        return 1;
+    }
+}
+
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+    switch (clockName)
+    {
+        case kCLOCK_CoreSysClk:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_FroHf:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case kCLOCK_Fro12M:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case kCLOCK_PllOut:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case kCLOCK_UsbClk:
+            freq = (SYSCON->USBCLKSEL == 0U) ? CLOCK_GetFroHfFreq() : (SYSCON->USBCLKSEL == 1) ? CLOCK_GetPllOutFreq() :
+                                                                                                 0U;
+            freq = freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U);
+            break;
+        case kClock_WdtOsc:
+            freq = CLOCK_GetWdtOscFreq();
+            break;
+        case kCLOCK_Frg:
+            freq = ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) ?
+                       ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) /
+                           ((SYSCON_FRGCTRL_DIV_MASK + 1) +
+                            ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)) :
+                       0;
+            break;
+        case kCLOCK_Dmic:
+            freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->DMICCLKSEL == 1U) ?
+                                                CLOCK_GetFroHfFreq() :
+                                                (SYSCON->DMICCLKSEL == 2U) ?
+                                                CLOCK_GetPllOutFreq() :
+                                                (SYSCON->DMICCLKSEL == 3U) ?
+                                                CLOCK_GetI2SMClkFreq() :
+                                                (SYSCON->DMICCLKSEL == 4U) ?
+                                                CLOCK_GetCoreSysClkFreq() :
+                                                (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U;
+            freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
+            break;
+
+        case kCLOCK_AsyncApbClk:
+            freq = CLOCK_GetAsyncApbClkFreq();
+            break;
+
+        case kCLOCK_FlexI2S:
+            freq = CLOCK_GetI2SMClkFreq();
+            break;
+
+        case kCLOCK_Flexcomm0:
+            freq = CLOCK_GetFlexCommClkFreq(0U);
+            break;
+        case kCLOCK_Flexcomm1:
+            freq = CLOCK_GetFlexCommClkFreq(1U);
+            break;
+        case kCLOCK_Flexcomm2:
+            freq = CLOCK_GetFlexCommClkFreq(2U);
+            break;
+        case kCLOCK_Flexcomm3:
+            freq = CLOCK_GetFlexCommClkFreq(3U);
+            break;
+        case kCLOCK_Flexcomm4:
+            freq = CLOCK_GetFlexCommClkFreq(4U);
+            break;
+        case kCLOCK_Flexcomm5:
+            freq = CLOCK_GetFlexCommClkFreq(5U);
+            break;
+        case kCLOCK_Flexcomm6:
+            freq = CLOCK_GetFlexCommClkFreq(6U);
+            break;
+        case kCLOCK_Flexcomm7:
+            freq = CLOCK_GetFlexCommClkFreq(7U);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Set the FLASH wait states for the passed frequency */
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
+{
+    if (iFreq <= 12000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle);
+    }
+    else if (iFreq <= 30000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle);
+    }
+    else if (iFreq <= 60000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle);
+    }
+    else if (iFreq <= 85000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle);
+    }
+    else
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle);
+    }
+}
+
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N)
+{
+    uint32_t x, i;
+
+    /* Find NDec */
+    switch (N)
+    {
+        case 0U:
+            x = 0xFFFU;
+            break;
+
+        case 1U:
+            x = 0x302U;
+            break;
+
+        case 2U:
+            x = 0x202U;
+            break;
+
+        default:
+            x = 0x080U;
+            for (i = N; i <= NVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+            }
+            break;
+    }
+
+    return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
+}
+
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0xFFFU:
+            n = 0U;
+            break;
+
+        case 0x302U:
+            n = 1U;
+            break;
+
+        case 0x202U:
+            n = 2U;
+            break;
+
+        default:
+            x = 0x080U;
+            n = 0xFFFFFFFFU;
+            for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+            }
+            break;
+    }
+
+    return n;
+}
+
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P)
+{
+    uint32_t x, i;
+
+    /* Find PDec */
+    switch (P)
+    {
+        case 0U:
+            x = 0xFFU;
+            break;
+
+        case 1U:
+            x = 0x62U;
+            break;
+
+        case 2U:
+            x = 0x42U;
+            break;
+
+        default:
+            x = 0x10U;
+            for (i = P; i <= PVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+            }
+            break;
+    }
+
+    return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0xFFU:
+            p = 0U;
+            break;
+
+        case 0x62U:
+            p = 1U;
+            break;
+
+        case 0x42U:
+            p = 2U;
+            break;
+
+        default:
+            x = 0x10U;
+            p = 0xFFFFFFFFU;
+            for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+            }
+            break;
+    }
+
+    return p;
+}
+
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M)
+{
+    uint32_t i, x;
+
+    /* Find MDec */
+    switch (M)
+    {
+        case 0U:
+            x = 0xFFFFFU;
+            break;
+
+        case 1U:
+            x = 0x18003U;
+            break;
+
+        case 2U:
+            x = 0x10003U;
+            break;
+
+        default:
+            x = 0x04000U;
+            for (i = M; i <= MVALMAX; i++)
+            {
+                x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
+            }
+            break;
+    }
+
+    return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P);
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0xFFFFFU:
+            m = 0U;
+            break;
+
+        case 0x18003U:
+            m = 1U;
+            break;
+
+        case 0x10003U:
+            m = 2U;
+            break;
+
+        default:
+            x = 0x04000U;
+            m = 0xFFFFFFFFU;
+            for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU);
+                if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+            }
+            break;
+    }
+
+    return m;
+}
+
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
+{
+    /* bandwidth: compute selP from Multiplier */
+    if (M < 60U)
+    {
+        *pSelP = (M >> 1U) + 1U;
+    }
+    else
+    {
+        *pSelP = PVALMAX - 1U;
+    }
+
+    /* bandwidth: compute selI from Multiplier */
+    if (M > 16384U)
+    {
+        *pSelI = 1U;
+    }
+    else if (M > 8192U)
+    {
+        *pSelI = 2U;
+    }
+    else if (M > 2048U)
+    {
+        *pSelI = 4U;
+    }
+    else if (M >= 501U)
+    {
+        *pSelI = 8U;
+    }
+    else if (M >= 60U)
+    {
+        *pSelI = 4U * (1024U / (M + 9U));
+    }
+    else
+    {
+        *pSelI = (M & 0x3CU) + 4U;
+    }
+
+    if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT))
+    {
+        *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT);
+    }
+
+    *pSelR = 0U;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FFU);
+        if (preDiv == 0U)
+        {
+            preDiv = 1U;
+        }
+    }
+
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1U;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_SHIFT) == 0U)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
+        if (postDiv == 0U)
+        {
+            postDiv = 2U;
+        }
+    }
+
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1U;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFFU);
+
+    /* Extra multiply by 2 needed? */
+    if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) == 0U)
+    {
+        mMult = mMult << 1U;
+    }
+
+    if (mMult == 0U)
+    {
+        mMult = 1U;
+    }
+
+    return mMult;
+}
+
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
+{
+    uint32_t tmp;
+
+    while (n != 0U)
+    {
+        tmp = n;
+        n = m % n;
+        m = tmp;
+    }
+
+    return m;
+}
+
+/* Set PLL output based on desired output rate */
+static pll_error_t CLOCK_GetPllConfig(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS)
+{
+    uint32_t nDivOutHz, fccoHz, multFccoDiv;
+    uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider;
+    uint32_t pllDirectInput, pllDirectOutput;
+    uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff;
+
+    /* Baseline parameters (no input or output dividers) */
+    pllPreDivider = 1U;  /* 1 implies pre-divider will be disabled */
+    pllPostDivider = 0U; /* 0 implies post-divider will be disabled */
+    pllDirectOutput = 1U;
+    if (useFeedbackDiv2)
+    {
+        /* Using feedback divider for M, so disable bypass */
+        pllBypassFBDIV2 = 0U;
+    }
+    else
+    {
+        pllBypassFBDIV2 = 1U;
+    }
+    multFccoDiv = (2U - pllBypassFBDIV2);
+
+    /* Verify output rate parameter */
+    if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
+    {
+        /* Maximum PLL output with post divider=1 cannot go above this frequency */
+        return kStatus_PLL_OutputTooHigh;
+    }
+    if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
+    {
+        /* Minmum PLL output with maximum post divider cannot go below this frequency */
+        return kStatus_PLL_OutputTooLow;
+    }
+
+    /* If using SS mode, input clock needs to be between 2MHz and 4MHz */
+    if (useSS)
+    {
+        /* Verify input rate parameter */
+        if (finHz < PLL_MIN_IN_SSMODE)
+        {
+            /* Input clock into the PLL cannot be lower than this */
+            return kStatus_PLL_InputTooLow;
+        }
+        /* PLL input in SS mode must be under 4MHz */
+        pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2);
+        if (pllPreDivider > NVALMAX)
+        {
+            return kStatus_PLL_InputTooHigh;
+        }
+    }
+    else
+    {
+        /* Verify input rate parameter */
+        if (finHz < PLL_LOWER_IN_LIMIT)
+        {
+            /* Input clock into the PLL cannot be lower than this */
+            return kStatus_PLL_InputTooLow;
+        }
+    }
+
+    /* Find the optimal CCO frequency for the output and input that
+       will keep it inside the PLL CCO range. This may require
+       tweaking the post-divider for the PLL. */
+    fccoHz = foutHz;
+    while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
+    {
+        /* CCO output is less than minimum CCO range, so the CCO output
+           needs to be bumped up and the post-divider is used to bring
+           the PLL output back down. */
+        pllPostDivider++;
+        if (pllPostDivider > PVALMAX)
+        {
+            return kStatus_PLL_OutsideIntLimit;
+        }
+
+        /* Target CCO goes up, PLL output goes down */
+        fccoHz = foutHz * (pllPostDivider * 2U);
+        pllDirectOutput = 0U;
+    }
+
+    /* Determine if a pre-divider is needed to get the best frequency */
+    if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false))
+    {
+        uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
+
+        if (a > 20000U)
+        {
+            a = (multFccoDiv * finHz) / a;
+            if ((a != 0U) && (a < PLL_MAX_N_DIV))
+            {
+                pllPreDivider = a;
+            }
+        }
+    }
+
+    /* Bypass pre-divider hardware if pre-divider is 1 */
+    if (pllPreDivider > 1U)
+    {
+        pllDirectInput = 0U;
+    }
+    else
+    {
+        pllDirectInput = 1U;
+    }
+
+    /* Determine PLL multipler */
+    nDivOutHz = (finHz / pllPreDivider);
+    pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
+
+    /* Find optimal values for filter */
+    if (useSS == false)
+    {
+        /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
+        if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
+        {
+            pllMultiplier++;
+        }
+
+        /* Setup filtering */
+        pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR);
+        bandsel = 1U;
+        uplimoff = 0U;
+
+        /* Get encoded value for M (mult) and use manual filter, disable SS mode */
+        pSetup->syspllssctrl[0] =
+            (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) | (1U << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT));
+
+        /* Power down SSC, not used */
+        pSetup->syspllssctrl[1] = (1U << SYSCON_SYSPLLSSCTRL1_PD_SHIFT);
+    }
+    else
+    {
+        uint64_t fc;
+
+        /* Filtering will be handled by SSC */
+        pllSelR = pllSelI = pllSelP = 0U;
+        bandsel = 0U;
+        uplimoff = 1U;
+
+        /* The PLL multiplier will get very close and slightly under the
+           desired target frequency. A small fractional component can be
+           added to fine tune the frequency upwards to the target. */
+        fc = ((uint64_t)(fccoHz % (multFccoDiv * nDivOutHz)) << 11U) / (multFccoDiv * nDivOutHz);
+
+        /* MDEC set by SSC */
+        pSetup->syspllssctrl[0U] = 0U;
+
+        /* Set multiplier */
+        pSetup->syspllssctrl[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) | PLL_SSCG1_MD_FRACT_SET((uint32_t)fc);
+    }
+
+    /* Get encoded values for N (prediv) and P (postdiv) */
+    pSetup->syspllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
+    pSetup->syspllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
+
+    /* PLL control */
+    pSetup->syspllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) |                  /* Filter coefficient */
+                         (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) |                  /* Filter coefficient */
+                         (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) |                  /* Filter coefficient */
+                         (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) |                      /* PLL bypass mode disabled */
+                         (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT) | /* Extra M / 2 divider? */
+                         (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) |             /* SS/fractional mode disabled */
+                         (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT) |        /* Manual bandwidth selection enabled */
+                         (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */
+                         (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */
+
+    return kStatus_PLL_Success;
+}
+
+/* Update local PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup);
+}
+
+/* Return System PLL input clock rate */
+uint32_t CLOCK_GetSystemPLLInClockRate(void)
+{
+    uint32_t clkRate = 0U;
+
+    switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
+    {
+        case 0x00U:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+
+        case 0x01U:
+            clkRate = CLOCK_GetExtClkFreq();
+            break;
+
+        case 0x02U:
+            clkRate = CLOCK_GetWdtOscFreq();
+            break;
+
+        case 0x03U:
+            clkRate = CLOCK_GetOsc32KFreq();
+            break;
+
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Return System PLL output clock rate from setup structure */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, mMult, inPllRate;
+    uint64_t workRate;
+
+    inPllRate = CLOCK_GetSystemPLLInClockRate();
+    if ((pSetup->syspllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+        prediv = findPllPreDiv(pSetup->syspllctrl, pSetup->syspllndec);
+        postdiv = findPllPostDiv(pSetup->syspllctrl, pSetup->syspllpdec);
+
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        /* If using the SS, use the multiplier */
+        if (pSetup->syspllssctrl[1] & (1U << SYSCON_SYSPLLSSCTRL1_PD_SHIFT))
+        {
+            /* MDEC used for rate */
+            mMult = findPllMMult(pSetup->syspllctrl, pSetup->syspllssctrl[0]);
+            workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+        }
+        else
+        {
+            uint64_t fract;
+
+            /* SS multipler used for rate */
+            mMult = (pSetup->syspllssctrl[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P;
+            workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+            /* Adjust by fractional */
+            fract = (uint64_t)(pSetup->syspllssctrl[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P;
+            workRate = workRate + ((inPllRate * fract) / 0x800U);
+        }
+
+        workRate = workRate / ((uint64_t)postdiv);
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Set the current PLL Rate */
+void CLOCK_SetStoredPLLClockRate(uint32_t rate)
+{
+    s_Pll_Freq = rate;
+}
+
+/* Return System PLL output clock rate */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
+{
+    pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Pll_Freq == 0U))
+    {
+        Setup.syspllctrl = SYSCON->SYSPLLCTRL;
+        Setup.syspllndec = SYSCON->SYSPLLNDEC;
+        Setup.syspllpdec = SYSCON->SYSPLLPDEC;
+        Setup.syspllssctrl[0] = SYSCON->SYSPLLSSCTRL0;
+        Setup.syspllssctrl[1] = SYSCON->SYSPLLSSCTRL1;
+
+        CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Pll_Freq;
+
+    return rate;
+}
+
+/* Set PLL output based on the passed PLL setup data */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+    uint32_t inRate;
+    bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U);
+    pll_error_t pllError;
+
+    /* Determine input rate for the PLL */
+    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+    {
+        inRate = pControl->inputRate;
+    }
+    else
+    {
+        inRate = CLOCK_GetSystemPLLInClockRate();
+    }
+
+    /* PLL flag options */
+    pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, false, useSS);
+    if ((useSS) && (pllError == kStatus_PLL_Success))
+    {
+        /* If using SS mode, then some tweaks are made to the generated setup */
+        pSetup->syspllssctrl[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc;
+        if (pControl->mfDither)
+        {
+            pSetup->syspllssctrl[1] |= (1U << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT);
+        }
+    }
+
+    return pllError;
+}
+
+/* Set PLL output from PLL setup structure */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->syspllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->syspllndec;
+    SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->syspllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0];
+    SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1];
+    SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLSSCTRL0 = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLSSCTRL0 = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup);
+
+    /* System voltage adjustment, occurs prior to setting main system clock */
+    if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)
+    {
+        POWER_SetVoltageForFreq(s_Pll_Freq);
+    }
+
+    return kStatus_PLL_Success;
+}
+
+/* Setup PLL Frequency from pre-calculated value */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
+{
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->syspllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->syspllndec;
+    SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->syspllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0];
+    SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1];
+    SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLSSCTRL0 = maxCCO;
+        SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK;
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLSSCTRL0 = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK;
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    s_Pll_Freq = pSetup->pllRate;
+
+    return kStatus_PLL_Success;
+}
+
+/* Set System PLL clock based on the input frequency and multiplier */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)
+{
+    uint32_t cco_freq = input_freq * multiply_by;
+    uint32_t pdec = 1U;
+    uint32_t selr;
+    uint32_t seli;
+    uint32_t selp;
+    uint32_t mdec, ndec;
+
+    uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO_SHIFT;
+
+    while (cco_freq < 75000000U)
+    {
+        multiply_by <<= 1U; /* double value in each iteration */
+        pdec <<= 1U;        /* correspondingly double pdec to cancel effect of double msel */
+        cco_freq = input_freq * multiply_by;
+    }
+    selr = 0U;
+    if (multiply_by < 60U)
+    {
+        seli = (multiply_by & 0x3cU) + 4U;
+        selp = (multiply_by >> 1U) + 1U;
+    }
+    else
+    {
+        selp = 31U;
+        if (multiply_by > 16384U)
+        {
+            seli = 1U;
+        }
+        else if (multiply_by > 8192U)
+        {
+            seli = 2U;
+        }
+        else if (multiply_by > 2048U)
+        {
+            seli = 4U;
+        }
+        else if (multiply_by >= 501U)
+        {
+            seli = 8U;
+        }
+        else
+        {
+            seli = 4U * (1024U / (multiply_by + 9U));
+        }
+    }
+
+    if (pdec > 1U)
+    {
+        directo = 0U;     /* use post divider */
+        pdec = pdec / 2U; /* Account for minus 1 encoding */
+                          /* Translate P value */
+        switch (pdec)
+        {
+            case 1U:
+                pdec = 0x62U; /* 1  * 2 */
+                break;
+            case 2U:
+                pdec = 0x42U; /* 2  * 2 */
+                break;
+            case 4U:
+                pdec = 0x02U; /* 4  * 2 */
+                break;
+            case 8U:
+                pdec = 0x0bU; /* 8  * 2 */
+                break;
+            case 16U:
+                pdec = 0x11U; /* 16 * 2 */
+                break;
+            case 32U:
+                pdec = 0x08U; /* 32 * 2 */
+                break;
+            default:
+                pdec = 0x08U;
+                break;
+        }
+    }
+
+    mdec = PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(multiply_by));
+    ndec = 0x302U; /* pre divide by 1 (hardcoded) */
+
+    SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL_SHIFT | directo | SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT |
+                         (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) |
+                         (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT);
+    SYSCON->SYSPLLPDEC = pdec | (1U << 7U);  /* set Pdec value and assert preq */
+    SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */
+    SYSCON->SYSPLLSSCTRL0 =
+        (1U << 18U) | (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
+}
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbd0);
+
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB_CLK);
+    }
+    else
+    {
+        /*TODO , we only implement FRO as usb clock source*/
+        ret = false;
+    }
+
+    CLOCK_EnableClock(kCLOCK_Usbd0);
+
+    return ret;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,857 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_device_registers.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *****************************************************************************/
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS                                                        \
+    {                                                                          \
+        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \
+					kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7 \
+    }
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS                                                                                         \
+    {                                                                                                         \
+        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
+            kCLOCK_MinUart6, kCLOCK_MinUart7                                                                  \
+    }
+
+/*! @brief Clock ip name array for BI2C. */
+#define BI2C_CLOCKS                                                                                                    \
+    {                                                                                                                  \
+        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
+    }
+/*! @brief Clock ip name array for LSPI. */
+#define LPSI_CLOCKS                                                                                                    \
+    {                                                                                                                  \
+        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
+    }
+/*! @brief Clock ip name array for FLEXI2S. */
+#define FLEXI2S_CLOCKS                                                                                        \
+    {                                                                                                         \
+        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
+            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7                                                                  \
+    }
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS \
+    {                \
+        kCLOCK_Utick \
+    }
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS \
+    {               \
+        kCLOCK_DMic \
+    }
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS \
+    {              \
+        kCLOCK_Dma \
+    }
+/*! @brief Clock ip name array for CT32B. */
+#define CTIMER_CLOCKS                                                             \
+    {                                                                             \
+        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
+    }
+
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS                \
+    {                              \
+        kCLOCK_Gpio0, kCLOCK_Gpio1 \
+    }
+/*! @brief Clock ip name array for ADC. */
+#define ADC_CLOCKS  \
+    {               \
+        kCLOCK_Adc0 \
+    }
+/*! @brief Clock ip name array for MRT. */
+#define MRT_CLOCKS \
+    {              \
+        kCLOCK_Mrt \
+    }
+/*! @brief Clock ip name array for MRT. */
+#define SCT_CLOCKS  \
+    {               \
+        kCLOCK_Sct0 \
+    }
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS \
+    {              \
+        kCLOCK_Rtc \
+    }
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS \
+    {               \
+        kCLOCK_Wwdt \
+    }
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS \
+    {              \
+        kCLOCK_Crc \
+    }
+/*! @brief Clock ip name array for USBD. */
+#define USBD_CLOCKS  \
+    {                \
+        kCLOCK_Usbd0 \
+    }
+
+/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */
+#define GINT_CLOCKS              \
+    {                            \
+        kCLOCK_Gint, kCLOCK_Gint \
+    }
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
+    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define AHB_CLK_CTRL0 0
+#define AHB_CLK_CTRL1 1
+#define ASYNC_CLK_CTRL0 2
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid = 0U,
+    kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
+    kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
+    kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
+    kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
+    kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
+    kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
+    kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
+    kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
+    kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
+    kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
+    kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
+    kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
+    kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
+    kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot  */
+    kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
+    kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
+    kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
+    kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
+    kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
+    kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
+    kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
+    kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
+    kCLOCK_SctIpu0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6),
+    kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
+	kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
+    kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
+    kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
+    kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
+    kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
+    kCLOCK_Pvtvf0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
+    kCLOCK_Pvtvf1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
+    kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
+    kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
+
+    kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
+    kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
+} clock_ip_name_t;
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+    kCLOCK_CoreSysClk,  /*!< Core/system clock  (aka MAIN_CLK)                       */
+    kCLOCK_BusClk,      /*!< Bus clock (AHB clock)                                   */
+    kCLOCK_FroHf,       /*!< FRO48/96                                                */
+    kCLOCK_Fro12M,      /*!< FRO12M                                                  */
+    kCLOCK_ExtClk,      /*!< External Clock                                          */
+    kCLOCK_PllOut,      /*!< PLL Output                                              */
+    kCLOCK_UsbClk,      /*!< USB input                                               */
+    kClock_WdtOsc,      /*!< Watchdog Oscillator                                     */
+    kCLOCK_Frg,         /*!< Frg Clock                                               */
+    kCLOCK_Dmic,        /*!< Digital Mic clock                                       */
+    kCLOCK_AsyncApbClk, /*!< Async APB clock																			    */
+    kCLOCK_FlexI2S,     /*!< FlexI2S clock                                           */
+    kCLOCK_Flexcomm0,   /*!< Flexcomm0Clock                                          */
+    kCLOCK_Flexcomm1,   /*!< Flexcomm1Clock                                          */
+    kCLOCK_Flexcomm2,   /*!< Flexcomm2Clock                                          */
+    kCLOCK_Flexcomm3,   /*!< Flexcomm3Clock                                          */
+    kCLOCK_Flexcomm4,   /*!< Flexcomm4Clock                                          */
+    kCLOCK_Flexcomm5,   /*!< Flexcomm5Clock                                          */
+    kCLOCK_Flexcomm6,   /*!< Flexcomm6Clock                                          */
+    kCLOCK_Flexcomm7,   /*!< Flexcomm7Clock                                          */
+} clock_name_t;
+
+/**
+ * Clock source selections for the asynchronous APB clock
+ */
+typedef enum _async_clock_src
+{
+    kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
+    kCLOCK_AsyncFro12Mhz,    /*!< 12MHz FRO */
+} async_clock_src_t;
+
+/*! @brief Clock Mux Switches
+*  The encoding is as follows each connection identified is 64bits wide
+*  starting from LSB upwards
+*
+*  [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
+*
+*/
+
+#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
+#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
+#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
+#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
+#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
+
+#define CM_MAINCLKSELA 0
+#define CM_MAINCLKSELB 1
+#define CM_CLKOUTCLKSELA 2
+#define CM_CLKOUTCLKSELB 3
+#define CM_SYSPLLCLKSEL 4
+#define CM_USBPLLCLKSEL 5
+#define CM_AUDPLLCLKSEL 6
+#define CM_SCTPLLCLKSEL 7
+#define CM_SPIFICLKSEL 8
+#define CM_ADCASYNCCLKSEL 9
+#define CM_USBCLKSEL 10
+#define CM_USB1CLKSEL 11
+#define CM_FXCOMCLKSEL0 12
+#define CM_FXCOMCLKSEL1 13
+#define CM_FXCOMCLKSEL2 14
+#define CM_FXCOMCLKSEL3 15
+#define CM_FXCOMCLKSEL4 16
+#define CM_FXCOMCLKSEL5 17
+#define CM_FXCOMCLKSEL6 18
+#define CM_FXCOMCLKSEL7 19
+#define CM_FXCOMCLKSEL8 20
+#define CM_FXCOMCLKSEL9 21
+#define CM_FXCOMCLKSEL10 22
+#define CM_FXCOMCLKSEL11 23
+#define CM_FXI2S0MCLKCLKSEL 24
+#define CM_FXI2S1MCLKCLKSEL 25
+#define CM_FRGCLKSEL 26
+#define CM_DMICCLKSEL 27
+
+#define CM_ASYNCAPB 28
+
+typedef enum _clock_attach_id
+{
+
+    kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
+    kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
+    kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
+    kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0),
+    kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
+    kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
+
+    kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
+    kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
+    kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
+    kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
+    kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
+
+    kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
+    kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
+
+    kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
+    kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
+    kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
+    kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
+
+    kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
+    kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
+    kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
+    kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
+
+    kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
+    kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
+    kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
+    kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
+    kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
+    kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
+
+    kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
+    kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
+    kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
+    kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
+    kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
+    kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
+
+    kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
+    kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
+    kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
+    kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
+    kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
+    kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
+
+    kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
+    kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
+    kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
+    kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
+    kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
+    kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
+
+    kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
+    kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
+    kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
+    kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
+    kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
+    kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
+
+    kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
+    kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
+    kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
+    kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
+    kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
+    kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
+
+    kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
+    kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
+    kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
+    kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
+    kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
+    kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
+
+    kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
+    kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
+    kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
+    kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
+    kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
+    kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
+
+    kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
+    kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
+    kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
+    kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
+    kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
+
+    kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0),
+    kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1),
+    kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7),
+
+    kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
+    kFRO_HF_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
+    kSYS_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
+    kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
+    kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),
+    kWDT_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),
+    kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
+
+    kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0),
+    kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1),
+    kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7),
+
+    kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
+    kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
+    kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
+    kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
+    kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
+    kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
+    kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
+    kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
+    kNONE_to_NONE = 0x80000000U,
+} clock_attach_id_t;
+
+/*  Clock dividers */
+typedef enum _clock_div_name
+{
+    kCLOCK_DivSystickClk = 0,
+    kCLOCK_DivTraceClk = 1,
+    kCLOCK_DivAhbClk = 32,
+    kCLOCK_DivClkOut = 33,
+    kCLOCK_DivSpifiClk = 36,
+    kCLOCK_DivAdcAsyncClk = 37,
+    kCLOCK_DivUsbClk = 38,
+    kCLOCK_DivFrg = 40,
+    kCLOCK_DivDmicClk = 42,
+    kCLOCK_DivFxI2s0MClk = 43
+} clock_div_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 2)
+    {
+        SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+}
+
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 2)
+    {
+        SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+}
+/**
+ * @brief FLASH Access time definitions
+ */
+typedef enum _clock_flashtim
+{
+    kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */
+    kCLOCK_Flash2Cycle,     /*!< Flash accesses use 2 CPU clocks */
+    kCLOCK_Flash3Cycle,     /*!< Flash accesses use 3 CPU clocks */
+    kCLOCK_Flash4Cycle,     /*!< Flash accesses use 4 CPU clocks */
+    kCLOCK_Flash5Cycle,     /*!< Flash accesses use 5 CPU clocks */
+    kCLOCK_Flash6Cycle,     /*!< Flash accesses use 6 CPU clocks */
+    kCLOCK_Flash7Cycle,     /*!< Flash accesses use 7 CPU clocks */
+    kCLOCK_Flash8Cycle      /*!< Flash accesses use 8 CPU clocks */
+} clock_flashtim_t;
+
+/**
+ * @brief	Set FLASH memory access time in clocks
+ * @param	clks	: Clock cycles for FLASH access
+ * @return	Nothing
+ */
+static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
+{
+    uint32_t tmp;
+
+    tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
+
+    /* Don't alter lower bits */
+    SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
+}
+
+/**
+ * @brief	Initialize the Core clock to given frequency (12, 48 or 96 MHz).
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
+ * enabled.
+ * @param	iFreq	: Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
+ * @return	returns success or fail status.
+ */
+status_t CLOCK_SetupFROClocking(uint32_t iFreq);
+/**
+ * @brief	Configure the clock selection muxes.
+ * @param	connection	: Clock to be configured.
+ * @return	Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+/**
+ * @brief	Setup peripheral clock dividers.
+ * @param	div_name	: Clock divider name
+ * @param divided_by_value: Value to be divided
+ * @param reset :  Whether to reset the divider counter.
+ * @return	Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
+/**
+ * @brief	Set the flash wait states for the input freuqency.
+ * @param	iFreq	: Input frequency
+ * @return	Nothing
+ */
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
+/*! @brief	Return Frequency of selected clock
+ *  @return	Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+
+/*! @brief	Return Input frequency for the Fractional baud rate generator
+ *  @return	Input Frequency for FRG
+ */
+uint32_t CLOCK_GetFRGInputClock(void);
+    
+/*! @brief	Set output of the Fractional baud rate generator
+ * @param	freq	: Desired output frequency
+ * @return	Error Code 0 - fail 1 - success
+ */
+uint32_t CLOCK_SetFRGClock(uint32_t freq);
+    
+/*! @brief	Return Frequency of FRO 12MHz
+ *  @return	Frequency of FRO 12MHz
+ */
+uint32_t CLOCK_GetFro12MFreq(void);
+/*! @brief	Return Frequency of External Clock
+ *  @return	Frequency of External Clock. If no external clock is used returns 0.
+ */
+uint32_t CLOCK_GetExtClkFreq(void);
+/*! @brief	Return Frequency of Watchdog Oscillator
+ *  @return	Frequency of Watchdog Oscillator
+ */
+uint32_t CLOCK_GetWdtOscFreq(void);
+/*! @brief	Return Frequency of High-Freq output of FRO
+ *  @return	Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFroHfFreq(void);
+/*! @brief	Return Frequency of PLL
+ *  @return	Frequency of PLL
+ */
+uint32_t CLOCK_GetPllOutFreq(void);
+/*! @brief	Return Frequency of 32kHz osc
+ *  @return	Frequency of 32kHz osc
+ */
+uint32_t CLOCK_GetOsc32KFreq(void);
+/*! @brief	Return Frequency of Core System
+ *  @return	Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+/*! @brief	Return Frequency of I2S MCLK Clock
+ *  @return	Frequency of I2S MCLK Clock
+ */
+uint32_t CLOCK_GetI2SMClkFreq(void);
+/*! @brief	Return Frequency of Flexcomm functional Clock
+ *  @return	Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
+/*! @brief	Return Asynchronous APB Clock source
+ *  @return	Asynchronous APB CLock source
+ */
+__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
+{
+    return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3);
+}
+/*! @brief	Return Frequency of Asynchronous APB Clock
+ *  @return	Frequency of Asynchronous APB Clock Clock
+ */
+uint32_t CLOCK_GetAsyncApbClkFreq(void);
+/*! @brief	Return System PLL input clock rate
+ *  @return	System PLL input clock rate
+ */
+uint32_t CLOCK_GetSystemPLLInClockRate(void);
+
+/*! @brief	Return System PLL output clock rate
+ *  @param	recompute	: Forces a PLL rate recomputation if true
+ *  @return	System PLL output clock rate
+ *  @note	The PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
+
+/*! @brief	Enables and disables PLL bypass mode
+ *  @brief	bypass	: true to bypass PLL (PLL output = PLL input, false to disable bypass
+ *  @return	System PLL output clock rate
+ */
+__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
+{
+    if (bypass)
+    {
+        SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+    else
+    {
+        SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+}
+
+/*! @brief	Check if PLL is locked or not
+ *  @return	true if the PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
+{
+    return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0);
+}
+
+/*! @brief Store the current PLL rate
+ *  @param	rate: Current rate of the PLL
+ *  @return	Nothing
+ **/
+void CLOCK_SetStoredPLLClockRate(uint32_t rate);
+
+/*! @brief PLL configuration structure flags for 'flags' field
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
+ *
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
+ * configuration structure must be assigned with the expected PLL frequency. If the
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
+ * function and the driver will determine the PLL rate from the currently selected
+ * PLL source. This flag might be used to configure the PLL input clock more accurately
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
+ *
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
+ * are not used.<br>
+ */
+#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
+#define PLL_CONFIGFLAG_FORCENOFRACT                                                                                    \
+    (1                                                                                                                 \
+     << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \
+                \ \ \                                                                                                                     \
+                  \ \ \ \ \                                                                                                                     \
+                    \ \ \ \ \ \ \                                                                                                                     \
+                      hardware */
+
+/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
+ * See (MF) field in the SYSPLLSSCTRL1 register in the UM.
+ */
+typedef enum _ss_progmodfm
+{
+    kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
+    kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
+    kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
+    kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
+    kSS_MF_64 = (4 << 20),  /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
+    kSS_MF_32 = (5 << 20),  /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
+    kSS_MF_24 = (6 << 20),  /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
+    kSS_MF_16 = (7 << 20)   /*!< Nss = 16 (fm ? 125- 250 kHz) */
+} ss_progmodfm_t;
+
+/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
+ * See (MR) field in the SYSPLLSSCTRL1 register in the UM.
+ */
+typedef enum _ss_progmoddp
+{
+    kSS_MR_K0 = (0 << 23),   /*!< k = 0 (no spread spectrum) */
+    kSS_MR_K1 = (1 << 23),   /*!< k = 1 */
+    kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
+    kSS_MR_K2 = (3 << 23),   /*!< k = 2 */
+    kSS_MR_K3 = (4 << 23),   /*!< k = 3 */
+    kSS_MR_K4 = (5 << 23),   /*!< k = 4 */
+    kSS_MR_K6 = (6 << 23),   /*!< k = 6 */
+    kSS_MR_K8 = (7 << 23)    /*!< k = 8 */
+} ss_progmoddp_t;
+
+/*! @brief PLL Spread Spectrum (SS) Modulation waveform control
+ * See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>
+ * Compensation for low pass filtering of the PLL to get a triangular
+ * modulation at the output of the PLL, giving a flat frequency spectrum.
+ */
+typedef enum _ss_modwvctrl
+{
+    kSS_MC_NOC = (0 << 26),  /*!< no compensation */
+    kSS_MC_RECC = (2 << 26), /*!< recommended setting */
+    kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
+} ss_modwvctrl_t;
+
+/*! @brief PLL configuration structure
+ *
+ * This structure can be used to configure the settings for a PLL
+ * setup structure. Fill in the desired configuration for the PLL
+ * and call the PLL setup function to fill in a PLL setup structure.
+ */
+typedef struct _pll_config
+{
+    uint32_t desiredRate; /*!< Desired PLL rate in Hz */
+    uint32_t inputRate;   /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
+    uint32_t flags;       /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
+    ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
+                             PLL_CONFIGFLAG_FORCENOFRACT flag */
+    ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
+                             PLL_CONFIGFLAG_FORCENOFRACT flag */
+    ss_modwvctrl_t
+        ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
+    bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
+                      PLL_CONFIGFLAG_FORCENOFRACT flag */
+
+} pll_config_t;
+
+/*! @brief PLL setup structure flags for 'flags' field
+* These flags control how the PLL setup function sets up the PLL
+*/
+#define PLL_SETUPFLAG_POWERUP (1 << 0)  /*!< Setup will power on the PLL after setup */
+#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
+#define PLL_SETUPFLAG_ADGVOLT (1 << 2)  /*!< Optimize system voltage for the new PLL rate */
+
+/*! @brief PLL setup structure
+* This structure can be used to pre-build a PLL setup configuration
+* at run-time and quickly set the PLL to the configuration. It can be
+* populated with the PLL setup function. If powering up or waiting
+* for PLL lock, the PLL input clock source should be configured prior
+* to PLL setup.
+*/
+typedef struct _pll_setup
+{
+    uint32_t syspllctrl;      /*!< PLL control register SYSPLLCTRL */
+    uint32_t syspllndec;      /*!< PLL NDEC register SYSPLLNDEC */
+    uint32_t syspllpdec;      /*!< PLL PDEC register SYSPLLPDEC */
+    uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */
+    uint32_t pllRate;         /*!< Acutal PLL rate */
+    uint32_t flags;           /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
+} pll_setup_t;
+
+/*! @brief PLL status definitions
+ */
+typedef enum _pll_error
+{
+    kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0),        /*!< PLL operation was successful */
+    kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1),   /*!< PLL output rate request was too low */
+    kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2),  /*!< PLL output rate request was too high */
+    kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3),    /*!< PLL input rate is too low */
+    kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4),   /*!< PLL input rate is too high */
+    kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */
+} pll_error_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+    kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf,            /*!< Use FRO 96 or 48 MHz. */
+    kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut,     /*!< Use System PLL output. */
+    kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock.    */
+    kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL(
+        7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
+} clock_usb_src_t;
+
+/*! @brief	Return System PLL output clock rate from setup structure
+ *  @param	pSetup	: Pointer to a PLL setup structure
+ *  @return	System PLL output clock rate calculated from the setup structure
+ */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output based on the passed PLL setup data
+ *  @param	pControl	: Pointer to populated PLL control structure to generate setup with
+ *  @param	pSetup		: Pointer to PLL setup structure to be filled
+ *  @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  @note	Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output from PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+* @param flagcfg : Flag configuration for PLL config structure
+ * @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/**
+ * @brief	Set PLL output from PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+ * @return	kStatus_PLL_Success on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output based on the multiplier and input frequency
+ * @param	multiply_by	: multiplier
+ * @param	input_freq	: Clock input frequency of the PLL
+ * @return	Nothing
+ * @note	Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
+ * function does not disable or enable PLL power, wait for PLL lock,
+ * or adjust system voltages. These must be done in the application.
+ * The function will not alter any source clocks (ie, main systen clock)
+ * that may use the PLL, so these should be setup prior to and after
+ * exiting the function.
+ */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
+
+/*! @brief Disable USB FS clock.
+ *
+ * Disable USB FS clock.
+ */
+static inline void CLOCK_DisableUsbfs0Clock(void)
+{
+    CLOCK_DisableClock(kCLOCK_Usbd0);
+}
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_common.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,161 @@
+/*
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_common.h"
+/* This is not needed for mbed */
+#if 0
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#elif(defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
+#endif /* NDEBUG */
+#endif
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+    uint32_t n;
+    uint32_t interrupts_disabled;
+
+    interrupts_disabled = __get_PRIMASK();
+    __disable_irq();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    if (!interrupts_disabled) {
+    __enable_irq();
+    }
+}
+#ifndef CPU_QN908X
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1u << intNumber;
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+#else
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    /*   SYSCON->STARTERSET[index] = 1u << intNumber; */
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+                           /*   SYSCON->STARTERCLR[index] = 1u << intNumber; */
+}
+#endif /*CPU_QN908X */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_common.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void EnableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+        NVIC_EnableIRQ(interrupt);
+    }
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void DisableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+        NVIC_DisableIRQ(interrupt);
+    }
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+    __set_PRIMASK(primask);
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ */
+void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_crc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
+/* @brief Default user configuration structure for CRC-CCITT */
+#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
+/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
+#define CRC_DRIVER_DEFAULT_REVERSE_IN false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
+/*< Default is without complement of written data */
+#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
+/*< Default is without complement of CRC data register read data */
+#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
+/*< Default initial checksum */
+#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void CRC_Init(CRC_Type *base, const crc_config_t *config)
+{
+    /* enable clock to CRC */
+    CLOCK_EnableClock(kCLOCK_Crc);
+
+    /* configure CRC module and write the seed */
+    base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
+                 CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
+                 CRC_MODE_CMPL_SUM(config->complementOut);
+    base->SEED = config->seed;
+}
+
+void CRC_GetDefaultConfig(crc_config_t *config)
+{
+    static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL,     CRC_DRIVER_DEFAULT_REVERSE_IN,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_IN,  CRC_DRIVER_DEFAULT_REVERSE_OUT,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
+
+    *config = default_config;
+}
+
+void CRC_Reset(CRC_Type *base)
+{
+    /* TODO - HW reset currently not exposed in API and they don't want
+     * dependencies to other modules anyway, so use SW reset temporarily. */
+
+    /* SYSCON_PeriphReset(RESET_CRC); */
+
+    crc_config_t config;
+    CRC_GetDefaultConfig(&config);
+    CRC_Init(base, &config);
+}
+
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
+{
+    /* extract CRC mode settings */
+    uint32_t mode = base->MODE;
+    config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
+    config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
+    config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
+    config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
+    config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
+
+    /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
+    base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
+
+    /* now we can obtain intermediate raw CRC sum value */
+    config->seed = base->SUM;
+
+    /* restore original CRC sum bit reverse and 1's complement setting */
+    base->MODE = mode;
+}
+
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
+{
+    const uint32_t *data32;
+
+    /* 8-bit reads and writes till source address is aligned 4 bytes */
+    while ((dataSize) && ((uint32_t)data & 3U))
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+
+    /* use 32-bit reads and writes as long as possible */
+    data32 = (const uint32_t *)data;
+    while (dataSize >= sizeof(uint32_t))
+    {
+        base->WR_DATA = *data32;
+        data32++;
+        dataSize -= sizeof(uint32_t);
+    }
+
+    data = (const uint8_t *)data32;
+
+    /* 8-bit reads and writes till end of data buffer */
+    while (dataSize)
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_crc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CRC driver version. Version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
+#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC polynomials to use. */
+typedef enum _crc_polynomial
+{
+    kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
+    kCRC_Polynomial_CRC_16 = 1U,    /*!< x^16+x^15+x^2+1 */
+    kCRC_Polynomial_CRC_32 = 2U     /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
+} crc_polynomial_t;
+
+/*!
+* @brief CRC protocol configuration.
+*
+* This structure holds the configuration for the CRC protocol.
+*
+*/
+typedef struct _crc_config
+{
+    crc_polynomial_t polynomial; /*!< CRC polynomial. */
+    bool reverseIn;              /*!< Reverse bits on input. */
+    bool complementIn;           /*!< Perform 1's complement on input. */
+    bool reverseOut;             /*!< Reverse bits on output. */
+    bool complementOut;          /*!< Perform 1's complement on output. */
+    uint32_t seed;               /*!< Starting checksum value. */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enables and configures the CRC peripheral module.
+ *
+ * This functions enables the CRC peripheral clock in the LPC SYSCON block.
+ * It also configures the CRC engine and starts checksum computation by writing the seed.
+ *
+ * @param base   CRC peripheral address.
+ * @param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disables the CRC peripheral module.
+ *
+ * This functions disables the CRC peripheral clock in the LPC SYSCON block.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+    /* disable clock to CRC */
+    CLOCK_DisableClock(kCLOCK_Crc);
+}
+
+/*!
+ * @brief resets CRC peripheral module.
+ *
+ * @param base   CRC peripheral address, currently not used.
+ */
+void CRC_Reset(CRC_Type *base);
+
+/*!
+ * @brief Loads default values to CRC protocol configuration structure.
+ *
+ * Loads default values to CRC protocol configuration structure. The default values are:
+ * @code
+ *   config->polynomial = kCRC_Polynomial_CRC_CCITT;
+ *   config->reverseIn = false;
+ *   config->complementIn = false;
+ *   config->reverseOut = false;
+ *   config->complementOut = false;
+ *   config->seed = 0xFFFFU;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
+ *
+ * The values, including seed, can be used to resume CRC calculation later.
+
+ * @param base   CRC peripheral address.
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
+
+/*!
+ * @brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to CRC data register.
+ *
+ * @param base     CRC peripheral address.
+ * @param data     Input data stream, MSByte in data[0].
+ * @param dataSize Size of the input data buffer in bytes.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Reads 32-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 32-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->SUM;
+}
+
+/*!
+ * @brief Reads 16-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 16-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
+{
+    return (uint16_t)base->SUM;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_ctimer.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ctimer.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The Timer instance
+ */
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to Timer bases for each instance. */
+static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
+
+/*! @brief Pointers to Timer clocks for each instance. */
+static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
+
+/*! @brief Pointers to Timer resets for each instance. */
+static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
+
+/*! @brief Pointers real ISRs installed by drivers for each instance. */
+static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
+
+/*! @brief Callback type installed by drivers for each instance. */
+static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
+
+/*! @brief Array to map timer instance to IRQ number. */
+static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
+{
+    uint32_t instance;
+    uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ctimerArrayCount; instance++)
+    {
+        if (s_ctimerBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ctimerArrayCount);
+
+    return instance;
+}
+
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
+{
+    assert(config);
+
+    /* Enable the timer clock*/
+    CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
+
+    /* Setup the cimer mode and count select */
+    base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
+
+    /* Setup the timer prescale value */
+    base->PR = CTIMER_PR_PRVAL(config->prescale);
+}
+
+void CTIMER_Deinit(CTIMER_Type *base)
+{
+    uint32_t index = CTIMER_GetInstance(base);
+    /* Stop the timer */
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+
+    /* Disable the timer clock*/
+    CLOCK_DisableClock(s_ctimerClocks[index]);
+
+    /* Disable IRQ at NVIC Level */
+    DisableIRQ(s_ctimerIRQ[index]);
+}
+
+void CTIMER_GetDefaultConfig(ctimer_config_t *config)
+{
+    assert(config);
+
+    /* Run as a timer */
+    config->mode = kCTIMER_TimerMode;
+    /* This field is ignored when mode is timer */
+    config->input = kCTIMER_Capture_0;
+    /* Timer counter is incremented on every APB bus clock */
+    config->prescale = 0;
+}
+
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt)
+{
+    assert(pwmFreq_Hz > 0);
+
+    uint32_t reg;
+    uint32_t period, pulsePeriod = 0;
+    uint32_t timerClock = srcClock_Hz / (base->PR + 1);
+    uint32_t index = CTIMER_GetInstance(base);
+
+    if (matchChannel == kCTIMER_Match_3)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Enable PWM mode on the channel */
+    base->PWMC |= (1U << matchChannel);
+
+    /* Clear the stop, reset and interrupt bits for this channel */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+
+    /* If call back function is valid then enable match interrupt for the channel */
+    if (enableInt)
+    {
+        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    }
+
+    /* Reset the counter when match on channel 3 */
+    reg |= CTIMER_MCR_MR3R_MASK;
+
+    base->MCR = reg;
+
+    /* Calculate PWM period match value */
+    period = (timerClock / pwmFreq_Hz) - 1;
+
+    /* Calculate pulse width match value */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Match on channel 3 will define the PWM period */
+    base->MR[kCTIMER_Match_3] = period;
+
+    /* This will define the PWM pulse period */
+    base->MR[matchChannel] = pulsePeriod;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If call back function is valid then enable interrupt and update the call back function */
+    if (enableInt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+
+    return kStatus_Success;
+}
+
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
+{
+    uint32_t pulsePeriod = 0, period;
+
+    /* Match channel 3 defines the PWM period */
+    period = base->MR[kCTIMER_Match_3];
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * dutyCyclePercent) / 100;
+
+    /* For 0% dutycyle, make pulse period greater than period so the event will never occur */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Update dutycycle */
+    base->MR[matchChannel] = pulsePeriod;
+}
+
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
+{
+    uint32_t reg;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the counter operation when a match on this channel occurs */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    base->MCR = reg;
+
+    reg = base->EMR;
+    /* Set the match output operation when a match on this channel occurs */
+    reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
+    reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
+
+    /* Set the initial state of the EM bit/output */
+    reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
+    reg |= (uint32_t)config->outPinInitState << matchChannel;
+    base->EMR = reg;
+
+    /* Set the match value */
+    base->MR[matchChannel] = config->matchValue;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If interrupt is enabled then enable interrupt and update the call back function */
+    if (config->enableInterrupt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+}
+
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt)
+{
+    uint32_t reg = base->CCR;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the capture edge */
+    reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
+    reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
+    /* If call back function is valid then enable capture interrupt for the channel and update the call back function */
+    if (enableInt)
+    {
+        reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+    base->CCR = reg;
+}
+
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
+{
+    uint32_t index = CTIMER_GetInstance(base);
+    s_ctimerCallback[index] = cb_func;
+    ctimerCallbackType[index] = cb_type;
+}
+
+void CTIMER_GenericIRQHandler(uint32_t index)
+{
+    uint32_t int_stat, i, mask;
+    /* Get Interrupt status flags */
+    int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
+    /* Clear the status flags that were set */
+    CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
+    if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
+    {
+        if (s_ctimerCallback[index][0])
+        {
+            s_ctimerCallback[index][0](int_stat);
+        }
+    }
+    else
+    {
+        for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
+        {
+            mask = 0x01 << i;
+            /* For each status flag bit that was set call the callback function if it is valid */
+            if ((int_stat & mask) && (s_ctimerCallback[index][i]))
+            {
+                s_ctimerCallback[index][i](int_stat);
+            }
+        }
+    }
+}
+
+#if (FSL_FEATURE_SOC_CTIMER_COUNT > 0U)
+/* IRQ handler functions overloading weak symbols in the startup */
+void CTIMER0_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(0);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_CTIMER_COUNT > 1U)
+void CTIMER1_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(1);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_CTIMER_COUNT > 2U)
+void CTIMER2_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(2);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_CTIMER_COUNT > 3U)
+void CTIMER3_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(3);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_CTIMER_COUNT > 4U)
+void CTIMER4_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(4);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_ctimer.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_CTIMER_H_
+#define _FSL_CTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup ctimer
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of Timer capture channels */
+typedef enum _ctimer_capture_channel
+{
+    kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
+    kCTIMER_Capture_1,      /*!< Timer capture channel 1 */
+    kCTIMER_Capture_2,      /*!< Timer capture channel 2 */
+    kCTIMER_Capture_3       /*!< Timer capture channel 3 */
+} ctimer_capture_channel_t;
+
+/*! @brief List of capture edge options */
+typedef enum _ctimer_capture_edge
+{
+    kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
+    kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
+    kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
+} ctimer_capture_edge_t;
+
+/*! @brief List of Timer match registers */
+typedef enum _ctimer_match
+{
+    kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
+    kCTIMER_Match_1,      /*!< Timer match register 1 */
+    kCTIMER_Match_2,      /*!< Timer match register 2 */
+    kCTIMER_Match_3       /*!< Timer match register 3 */
+} ctimer_match_t;
+
+/*! @brief List of output control options */
+typedef enum _ctimer_match_output_control
+{
+    kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
+    kCTIMER_Output_Clear,         /*!< Clear the EM bit/output to 0 */
+    kCTIMER_Output_Set,           /*!< Set the EM bit/output to 1 */
+    kCTIMER_Output_Toggle         /*!< Toggle the EM bit/output */
+} ctimer_match_output_control_t;
+
+/*! @brief List of Timer modes */
+typedef enum _ctimer_timer_mode
+{
+    kCTIMER_TimerMode = 0U,     /* TC is incremented every rising APB bus clock edge */
+    kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
+    kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
+    kCTIMER_IncreaseOnBothEdge  /* TC is incremented on both edges of input signal */
+} ctimer_timer_mode_t;
+
+/*! @brief List of Timer interrupts */
+typedef enum _ctimer_interrupt_enable
+{
+    kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK,    /*!< Match 0 interrupt */
+    kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK,    /*!< Match 1 interrupt */
+    kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK,    /*!< Match 2 interrupt */
+    kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK,    /*!< Match 3 interrupt */
+    kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
+    kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
+    kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
+    kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
+} ctimer_interrupt_enable_t;
+
+/*! @brief List of Timer flags */
+typedef enum _ctimer_status_flags
+{
+    kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK,   /*!< Match 0 interrupt flag */
+    kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK,   /*!< Match 1 interrupt flag */
+    kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK,   /*!< Match 2 interrupt flag */
+    kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK,   /*!< Match 3 interrupt flag */
+    kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
+    kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
+    kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
+    kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
+} ctimer_status_flags_t;
+
+typedef void (*ctimer_callback_t)(uint32_t flags);
+
+/*! @brief Callback type when registering for a callback. When registering a callback
+ *         an array of function pointers is passed the size could be 1 or 8, the callback
+ *         type will tell that.
+ */
+typedef enum
+{
+    kCTIMER_SingleCallback,  /*!< Single Callback type where there is only one callback for the timer. 
+                                 based on the status flags different channels needs to be handled differently */
+    kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. 
+                                 for both match/capture */
+} ctimer_callback_type_t;
+
+/*!
+ * @brief Match configuration
+ *
+ * This structure holds the configuration settings for each match register.
+ */
+typedef struct _ctimer_match_config
+{
+    uint32_t matchValue;                      /*!< This is stored in the match register */
+    bool enableCounterReset;                  /*!< true: Match will reset the counter
+                                                   false: Match will not reser the counter */
+    bool enableCounterStop;                   /*!< true: Match will stop the counter
+                                                   false: Match will not stop the counter */
+    ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
+    bool outPinInitState;                     /*!< Initial value of the EM bit/output */
+    bool enableInterrupt;                     /*!< true: Generate interrupt upon match
+                                                   false: Do not generate interrupt on match */
+
+} ctimer_match_config_t;
+
+/*!
+ * @brief Timer configuration structure
+ *
+ * This structure holds the configuration settings for the Timer peripheral. To initialize this
+ * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _ctimer_config
+{
+    ctimer_timer_mode_t mode;       /*!< Timer mode */
+    ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
+                                        modes that rely on this input signal to increment TC */
+    uint32_t prescale;              /*!< Prescale value */
+} ctimer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application before using the driver.
+ *
+ * @param base   Ctimer peripheral base address
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
+
+/*!
+ * @brief Gates the timer clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+void CTIMER_Deinit(CTIMER_Type *base);
+
+/*!
+ * @brief  Fills in the timers configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ *   config->mode = kCTIMER_TimerMode;
+ *   config->input = kCTIMER_Capture_0;
+ *   config->prescale = 0;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_GetDefaultConfig(ctimer_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name PWM setup operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Enables PWM mode on the match channel passed in and will then setup the match value
+ * and other match parameters to generate a PWM signal.
+ * This function will assign match channel 3 to set the PWM cycle.
+ *
+ * @note When setting PWM output from multiple output pins, all should use the same PWM
+ * frequency
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
+ * @param pwmFreq_Hz       PWM signal frequency in Hz
+ * @param srcClock_Hz      Timer counter clock in Hz
+ * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
+ *                         if it is 0 then no interrupt is generated
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ */
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt);
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
+ */
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
+
+/*! @}*/
+
+/*!
+ * @brief Setup the match register.
+ *
+ * User configuration is used to setup the match value and action to be taken when a match occurs.
+ *
+ * @param base         Ctimer peripheral base address
+ * @param matchChannel Match register to configure
+ * @param config       Pointer to the match configuration structure
+ */
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
+
+/*!
+ * @brief Setup the capture.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param capture   Capture channel to configure
+ * @param edge      Edge on the channel that will trigger a capture
+ * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
+ *                  is called upon capture
+ */
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt);
+
+/*!
+ * @brief Register callback.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param cb_func   callback function
+ * @param cb_type   callback function type, singular or multiple
+ */
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Enable match interrupts */
+    base->MCR |= mask;
+
+    /* Enable capture interrupts */
+    base->CCR |= mask;
+}
+
+/*!
+ * @brief Disables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Disable match interrupts */
+    base->MCR &= ~mask;
+
+    /* Disable capture interrupts */
+    base->CCR &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::ctimer_interrupt_enable_t
+ */
+static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
+{
+    uint32_t enabledIntrs = 0;
+
+    /* Get all the match interrupts enabled */
+    enabledIntrs =
+        base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT);
+
+    /* Get all the capture interrupts enabled */
+    enabledIntrs |=
+        base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT);
+
+    return enabledIntrs;
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::ctimer_status_flags_t
+ */
+static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
+{
+    return base->IR;
+}
+
+/*!
+ * @brief Clears the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::ctimer_status_flags_t
+ */
+static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
+{
+    base->IR = mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Counter Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StartTimer(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CEN_MASK;
+}
+
+/*!
+ * @brief Stops the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StopTimer(CTIMER_Type *base)
+{
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Reset the counter.
+ *
+ * The timer counter and prescale counter are reset on the next positive edge of the APB clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_Reset(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CRST_MASK;
+    base->TCR &= ~CTIMER_TCR_CRST_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CTIMER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,417 @@
+/*
+* Copyright (c) 2016, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "fsl_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for DMA.
+ *
+ * @param base DMA peripheral base address.
+ */
+static int32_t DMA_GetInstance(DMA_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map DMA instance number to base pointer. */
+static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
+
+/*! @brief Array to map DMA instance number to IRQ number. */
+static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
+
+/*! @brief Pointers to transfer handle for each DMA channel. */
+static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS];
+
+/*! @brief Static table of descriptors */
+#if defined(__ICCARM__)
+#pragma data_alignment = 512
+dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static int32_t DMA_GetInstance(DMA_Type *base)
+{
+    int32_t instance;
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_DMA_COUNT; instance++)
+    {
+        if (s_dmaBases[instance] == base)
+        {
+            break;
+        }
+    }
+    assert(instance < FSL_FEATURE_SOC_DMA_COUNT);
+    return instance < FSL_FEATURE_SOC_DMA_COUNT ? instance : -1;
+}
+
+void DMA_Init(DMA_Type *base)
+{
+    /* enable dma clock gate */
+    CLOCK_EnableClock(kCLOCK_Dma);
+    /* set descriptor table */
+    base->SRAMBASE = (uint32_t)s_dma_descriptor_table;
+    /* enable dma peripheral */
+    base->CTRL |= DMA_CTRL_ENABLE_MASK;
+}
+
+void DMA_Deinit(DMA_Type *base)
+{
+    /* Disable DMA peripheral */
+    base->CTRL &= ~(DMA_CTRL_ENABLE_MASK);
+}
+
+void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
+{
+    assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger));
+
+    uint32_t tmp = (
+        DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
+        DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
+        DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK
+    );
+    tmp = base->CHANNEL[channel].CFG & (~tmp);
+    tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
+    base->CHANNEL[channel].CFG = tmp;
+}
+
+/*!
+ * @brief Gets the remaining bytes of the current DMA descriptor transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The number of bytes which have not been transferred yet.
+ */
+uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+
+    /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes 
+     * impossible to distinguish between:
+     * - transfer finishes (represented by value '0x3FF')
+     * - and remaining 1024 bytes to transfer (value 0x3FF)
+     * for all descriptor in chain, except the last one.
+     * If you decide to use this function, please use 1023 transfers as maximal value */
+
+    /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
+    if (
+        (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && 
+        (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))
+    )
+    {
+        return 0;
+    }
+
+    return base->CHANNEL[channel].XFERCFG + 1;
+}
+
+static void DMA_SetupDescriptor(
+    dma_descriptor_t    *desc,
+    uint32_t            xfercfg,
+    void                *srcEndAddr,
+    void                *dstEndAddr,
+    void                *nextDesc
+)
+{
+    desc->xfercfg = xfercfg;
+    desc->srcEndAddr = srcEndAddr;
+    desc->dstEndAddr = dstEndAddr;
+    desc->linkToNextDesc = nextDesc;
+}
+
+/* Verify and convert dma_xfercfg_t to XFERCFG register */
+static void DMA_SetupXferCFG(
+    dma_xfercfg_t *xfercfg,
+    uint32_t *xfercfg_addr
+)
+{
+    assert(xfercfg != NULL);
+    /* check source increment */
+    assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4));
+    /* check destination increment */
+    assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4));
+    /* check data width */
+    assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4));
+    /* check transfer count */
+    assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
+
+    uint32_t xfer = 0, tmp;
+    /* set valid flag - descriptor is ready now */
+    xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0);
+    /* set reload - allow link to next descriptor */
+    xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0);
+    /* set swtrig flag - start transfer */
+    xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0);
+    /* set transfer count */
+    xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0);
+    /* set INTA */
+    xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0);
+    /* set INTB */
+    xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0);
+    /* set data width */
+    tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1;
+    xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp);
+    /* set source increment value */
+    tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc;
+    xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp);
+    /* set destination increment value */
+    tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc;
+    xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp);
+    /* set transfer count */
+    xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
+
+    /* store xferCFG */
+    *xfercfg_addr = xfer;
+}
+
+void DMA_CreateDescriptor(
+    dma_descriptor_t    *desc,
+    dma_xfercfg_t       *xfercfg,
+    void                *srcAddr,
+    void                *dstAddr,
+    void                *nextDesc
+)
+{
+    uint32_t xfercfg_reg = 0;
+
+    assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg));
+    assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
+    assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
+    assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16));
+
+    /* Setup channel configuration */
+    DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
+
+    /* Set descriptor structure */
+    DMA_SetupDescriptor(desc, xfercfg_reg,
+        (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
+        (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
+        nextDesc
+    );
+}
+
+void DMA_AbortTransfer(dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    DMA_DisableChannel(handle->base, handle->channel);
+    while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel)))
+    { }
+    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel);
+    DMA_EnableChannel(handle->base, handle->channel);
+}
+
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
+{
+    int32_t dmaInstance;
+    assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS));
+
+    /* base address is invalid DMA instance */
+    dmaInstance = DMA_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    handle->base = base;
+    handle->channel = channel;
+    s_DMAHandle[channel] = handle;
+    /* Enable NVIC interrupt */
+    EnableIRQ(s_dmaIRQNumber[dmaInstance]);
+}
+
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
+{
+    assert(handle != NULL);
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                          void *srcAddr,
+                          void *dstAddr,
+                          uint32_t byteWidth,
+                          uint32_t transferBytes,
+                          dma_transfer_type_t type,
+                          void *nextDesc)
+{
+    uint32_t xfer_count;
+    assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
+    assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
+
+    /* check max */
+    xfer_count = transferBytes / byteWidth;
+    assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
+
+    memset(config, 0, sizeof(*config));
+    switch (type)
+    {
+    case kDMA_MemoryToMemory:
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph = false;
+        break;
+    case kDMA_PeripheralToMemory:
+        /* Peripheral register - source doesn't increment */
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph = true;
+        break;
+    case kDMA_MemoryToPeripheral:
+        /* Peripheral register - destination doesn't increment */
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph = true;
+        break;
+    case kDMA_StaticToStatic:
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph = true;
+        break;
+    default:
+        return;
+    }
+
+    config->dstAddr = (uint8_t*)dstAddr;
+    config->srcAddr = (uint8_t*)srcAddr;
+    config->nextDesc = (uint8_t*)nextDesc;
+    config->xfercfg.transferCount = xfer_count;
+    config->xfercfg.byteWidth = byteWidth;
+    config->xfercfg.intA = true;
+    config->xfercfg.reload = nextDesc != NULL;
+    config->xfercfg.valid = true;
+}
+
+status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
+{
+    assert((NULL != handle) && (NULL != config));
+
+    /* Previous transfer has not finished */
+    if (DMA_ChannelIsActive(handle->base, handle->channel))
+    {
+         return kStatus_DMA_Busy;
+    }
+
+    /* enable/disable peripheral request */
+    if (config->isPeriph)
+    {
+        DMA_EnableChannelPeriphRq(handle->base, handle->channel);
+    }
+    else
+    {
+        DMA_DisableChannelPeriphRq(handle->base, handle->channel);
+    }
+
+    DMA_CreateDescriptor(
+        &s_dma_descriptor_table[ handle->channel ], &config->xfercfg,
+        config->srcAddr, config->dstAddr, config->nextDesc
+    );
+
+    return kStatus_Success;
+}
+
+void DMA_StartTransfer(dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Enable channel interrupt */
+    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel);
+
+    /* If HW trigger is enabled - disable SW trigger */
+    if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+    {
+        s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
+    }
+    /* Otherwise enable SW trigger */
+    else
+    {
+        s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
+    }
+
+    /* Set channel XFERCFG register according first channel descriptor. */
+    handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg;
+    /* At this moment, the channel ACTIVE bit is set and application cannot modify 
+     * or start another transfer using this channel. Channel ACTIVE bit is cleared by 
+    * 'AbortTransfer' function or when the transfer finishes */
+}
+
+void DMA0_DriverIRQHandler(void)
+{
+    dma_handle_t *handle;
+    int32_t channel_group;
+    int32_t channel_index;
+
+    /* Find channels that have completed transfer */
+    for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++)
+    {
+        handle = s_DMAHandle[i];
+        /* Handle is not present */
+        if (NULL == handle)
+        {
+            continue;
+        }
+        channel_group = DMA_CHANNEL_GROUP(handle->channel);
+        channel_index = DMA_CHANNEL_INDEX(handle->channel);
+        /* Channel uses INTA flag */
+        if (handle->base->COMMON[channel_group].INTA & (1U << channel_index))
+        {
+            /* Clear INTA flag */
+            handle->base->COMMON[channel_group].INTA = 1U << channel_index;
+            if (handle->callback)
+            {
+                (handle->callback)(handle, handle->userData, true, kDMA_IntA);
+            }
+        }
+        /* Channel uses INTB flag */
+        if (handle->base->COMMON[channel_group].INTB & (1U << channel_index))
+        {
+            /* Clear INTB flag */
+            handle->base->COMMON[channel_group].INTB = 1U << channel_index;
+            if (handle->callback)
+            {
+                (handle->callback)(handle, handle->userData, true, kDMA_IntB);
+            }
+        }
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,476 @@
+/*
+* Copyright (c) 2016, Freescale Semiconductor, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+*   of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+*   list of conditions and the following disclaimer in the documentation and/or
+*   other materials provided with the distribution.
+*
+* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+*   contributors may be used to endorse or promote products derived from this
+*   software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _FSL_DMA_H_
+#define _FSL_DMA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dma
+ * @{
+ */
+
+/*! @file */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief DMA driver version */
+#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+#define DMA_MAX_TRANSFER_COUNT 0x400
+
+/* Channel group consists of 32 channels. channel_group = (channel / 32) */
+#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U)
+/* Channel index in channel group. channel_index = (channel % 32) */
+#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
+
+
+/*! @brief DMA descriptor structure */
+typedef struct _dma_descriptor {
+    uint32_t xfercfg;       /*!< Transfer configuration */
+    void *srcEndAddr;       /*!< Last source address of DMA transfer */
+    void *dstEndAddr;       /*!< Last destination address of DMA transfer */
+    void *linkToNextDesc;   /*!< Address of next DMA descriptor in chain */
+} dma_descriptor_t;
+
+/*! @brief DMA transfer configuration */
+typedef struct _dma_xfercfg {
+    bool valid;             /*!< Descriptor is ready to transfer */
+    bool reload;            /*!< Reload channel configuration register after
+                                 current descriptor is exhausted */
+    bool swtrig;            /*!< Perform software trigger. Transfer if fired
+                                 when 'valid' is set */
+    bool clrtrig;           /*!< Clear trigger */
+    bool intA;              /*!< Raises IRQ when transfer is done and set IRQA status register flag */
+    bool intB;              /*!< Raises IRQ when transfer is done and set IRQB status register flag */
+    uint8_t byteWidth;      /*!< Byte width of data to transfer */
+    uint8_t srcInc;         /*!< Increment source address by 'srcInc' x 'byteWidth' */
+    uint8_t dstInc;         /*!< Increment destination address by 'dstInc' x 'byteWidth' */
+    uint16_t transferCount; /*!< Number of transfers */
+} dma_xfercfg_t;
+
+/*! @brief DMA channel priority */
+typedef enum _dma_priority {
+    kDMA_ChannelPriority0 = 0,  /*!< Highest channel priority - priority 0 */
+    kDMA_ChannelPriority1,      /*!< Channel priority 1 */
+    kDMA_ChannelPriority2,      /*!< Channel priority 2 */
+    kDMA_ChannelPriority3,      /*!< Channel priority 3 */
+    kDMA_ChannelPriority4,      /*!< Channel priority 4 */
+    kDMA_ChannelPriority5,      /*!< Channel priority 5 */
+    kDMA_ChannelPriority6,      /*!< Channel priority 6 */
+    kDMA_ChannelPriority7,      /*!< Lowest channel priority - priority 7 */
+} dma_priority_t;
+
+/*! @brief DMA interrupt flags */
+typedef enum _dma_int {
+    kDMA_IntA,  /*!< DMA interrupt flag A */
+    kDMA_IntB,  /*!< DMA interrupt flag B */
+} dma_irq_t;
+
+/*! @brief DMA trigger type*/
+typedef enum _dma_trigger_type {
+    kDMA_NoTrigger = 0, /*!< Trigger is disabled */
+    kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
+    kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
+    kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
+    kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
+} dma_trigger_type_t;
+
+/*! @brief DMA trigger burst */
+typedef enum _dma_trigger_burst {
+    kDMA_SingleTransfer = 0,                                                    /*!< Single transfer */
+    kDMA_LevelBurstTransfer  = DMA_CHANNEL_CFG_TRIGBURST(1),                            /*!< Burst transfer driven by level trigger */
+    kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1),                             /*!< Perform 1 transfer by edge trigger */
+    kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1),     /*!< Perform 2 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2),     /*!< Perform 4 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3),     /*!< Perform 8 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4),    /*!< Perform 16 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5),    /*!< Perform 32 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6),    /*!< Perform 64 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7),   /*!< Perform 128 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8),   /*!< Perform 256 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9),   /*!< Perform 512 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
+} dma_trigger_burst_t;  
+
+/*! @brief DMA burst wrapping */
+typedef enum _dma_burst_wrap {
+    kDMA_NoWrap = 0,                                                            /*!< Wrapping is disabled */
+    kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1),                                     /*!< Wrapping is enabled for source */
+    kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1),                                     /*!< Wrapping is enabled for destination */
+    kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1),     /*!< Wrapping is enabled for source and destination */
+} dma_burst_wrap_t;
+
+/*! @brief DMA transfer type */
+typedef enum _dma_transfer_type
+{
+    kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
+    kDMA_PeripheralToMemory,    /*!< Transfer from peripheral to memory (increment only destination) */
+    kDMA_MemoryToPeripheral,    /*!< Transfer from memory to peripheral (increment only source)*/
+    kDMA_StaticToStatic,        /*!< Peripheral to static memory (do not increment source or destination) */
+} dma_transfer_type_t;
+
+/*! @brief DMA channel trigger */
+typedef struct _dma_channel_trigger {
+    dma_trigger_type_t type;
+    dma_trigger_burst_t burst;
+    dma_burst_wrap_t wrap;
+} dma_channel_trigger_t;
+
+/*! @brief DMA transfer status */
+enum _dma_transfer_status
+{
+    kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0),      /*!< Channel is busy and can't handle the
+                                                                     transfer request. */
+};
+
+/*! @brief DMA transfer configuration */
+typedef struct _dma_transfer_config
+{
+    uint8_t             *srcAddr;       /*!< Source data address */
+    uint8_t             *dstAddr;       /*!< Destination data address */
+    uint8_t             *nextDesc;      /*!< Chain custom descriptor */
+    dma_xfercfg_t       xfercfg;        /*!< Transfer options */
+    bool                isPeriph;       /*!< DMA transfer is driven by peripheral */
+} dma_transfer_config_t;
+
+/*! @brief Callback for DMA */
+struct _dma_handle;
+
+/*! @brief Define Callback function for DMA. */
+typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*! @brief DMA transfer handle structure */
+typedef struct _dma_handle
+{
+    dma_callback callback;  /*!< Callback function. Invoked when transfer 
+                                of descriptor with interrupt flag finishes */
+    void *userData;         /*!< Callback function parameter */
+    DMA_Type *base;         /*!< DMA peripheral base address */
+    uint8_t channel;        /*!< DMA channel number */
+} dma_handle_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMA initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes DMA peripheral.
+ *
+ * This function enable the DMA clock, set descriptor table and
+ * enable DMA peripheral.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Init(DMA_Type *base);
+
+/*!
+ * @brief Deinitializes DMA peripheral.
+ *
+ * This function gates the DMA clock.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Deinit(DMA_Type *base);
+
+/* @} */
+/*!
+ * @name DMA Channel Operation
+ * @{
+ */
+
+ /*!
+ * @brief Return whether DMA channel is processing transfer
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return True for active state, false otherwise.
+ */
+static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
+}
+
+/*!
+ * @brief Enables the interrupt source for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Disables the interrupt source for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Enable DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Disable DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Set PERIPHREQEN of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
+}
+
+/*!
+ * @brief Get PERIPHREQEN value of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return True for enabled PeriphRq, false for disabled.
+ */
+static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
+}
+
+/*!
+ * @brief Set trigger settings of DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param trigger trigger configuration.
+ */
+void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
+
+/*!
+ * @brief Gets the remaining bytes of the current DMA descriptor transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The number of bytes which have not been transferred yet.
+ */
+uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Set priority of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param priority Channel priority value.
+ */
+static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
+}
+
+/*!
+ * @brief Get priority of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return Channel priority value.
+ */
+static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
+}
+
+/*!
+ * @brief Create application specific DMA descriptor 
+ *        to be used in a chain in transfer
+ *
+ * @param desc DMA descriptor address.
+ * @param xfercfg Transfer configuration for DMA descriptor.
+ * @param srcAddr Address of last item to transmit
+ * @param dstAddr Address of last item to receive.
+ * @param nextDesc Address of next descriptor in chain.
+ */
+void DMA_CreateDescriptor(
+    dma_descriptor_t    *desc,
+    dma_xfercfg_t       *xfercfg,
+    void                *srcAddr,
+    void                *dstAddr,
+    void                *nextDesc
+);
+
+/* @} */
+
+/*!
+ * @name DMA Transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Abort running transfer by handle.
+ *
+ * This function aborts DMA transfer specified by handle.
+ *
+ * @param handle DMA handle pointer. 
+ */
+void DMA_AbortTransfer(dma_handle_t *handle);
+
+/*!
+ * @brief Creates the DMA handle.
+ *
+ * This function is called if using transaction API for DMA. This function
+ * initializes the internal state of DMA handle.
+ *
+ * @param handle DMA handle pointer. The DMA handle stores callback function and
+ *               parameters.
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Installs a callback function for the DMA transfer.
+ *
+ * This callback is called in DMA IRQ handler. Use the callback to do something after
+ * the current major loop transfer completes.
+ *
+ * @param handle DMA handle pointer.
+ * @param callback DMA callback function pointer.
+ * @param userData Parameter for callback function.
+ */
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
+
+/*!
+ * @brief Prepares the DMA transfer structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * @param config The user configuration structure of type dma_transfer_t.
+ * @param srcAddr DMA transfer source address.
+ * @param dstAddr DMA transfer destination address.
+ * @param byteWidth DMA transfer destination address width(bytes).
+ * @param transferBytes DMA transfer bytes to be transferred.
+ * @param type DMA transfer type.
+ * @param nextDesc Chain custom descriptor to transfer.
+ * @note The data address and the data width must be consistent. For example, if the SRC
+ *       is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
+ *       source address error(SAE).
+ */
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                          void *srcAddr,
+                          void *dstAddr,
+                          uint32_t byteWidth,
+                          uint32_t transferBytes,
+                          dma_transfer_type_t type,
+                          void *nextDesc);
+
+/*!
+ * @brief Submits the DMA transfer request.
+ *
+ * This function submits the DMA transfer request according to the transfer configuration structure.
+ * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
+ * a TCD and enables scatter/gather feature to process it in the next time.
+ *
+ * @param handle DMA handle pointer.
+ * @param config Pointer to DMA transfer configuration structure.
+ * @retval kStatus_DMA_Success It means submit transfer request succeed.
+ * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
+ * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
+ */
+status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
+
+/*!
+ * @brief DMA start transfer.
+ *
+ * This function enables the channel request. User can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * @param handle DMA handle pointer.
+ */
+void DMA_StartTransfer(dma_handle_t *handle);
+
+/*!
+ * @brief DMA IRQ handler for descriptor transfer complete.
+ *
+ * This function clears the channel major interrupt flag and call
+ * the callback function if it is not NULL.
+ */
+void DMA_HandleIRQ(void);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /*_FSL_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_dmic.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dmic.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of DMIC peripheral base address. */
+static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS;
+
+/* Array of DMIC clock name. */
+static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS;
+
+/* Array of DMIC IRQ number. */
+static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS;
+
+/*! @brief Callback function array for DMIC(s). */
+static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT];
+
+/* Array of HWVAD IRQ number. */
+static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS;
+
+/*! @brief Callback function array for HWVAD(s). */
+static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+uint32_t DMIC_GetInstance(DMIC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_DMIC_COUNT; instance++)
+    {
+        if (s_dmicBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_DMIC_COUNT);
+
+    return instance;
+}
+
+void DMIC_Init(DMIC_Type *base)
+{
+    assert(base);
+
+    /* Enable the clock to the register interface */
+    CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]);
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn);
+
+    /* Disable DMA request*/
+    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+
+    /* Disable DMIC interrupt. */
+    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+}
+
+void DMIC_DeInit(DMIC_Type *base)
+{
+    assert(base);
+    /* Disable the clock to the register interface */
+    CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]);
+}
+
+void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config)
+{
+    base->IOCFG = config;
+}
+
+void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode)
+{
+    if (mode == kDMIC_OperationModeInterrupt)
+    {
+        /* Enable DMIC interrupt. */
+        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+    }
+    if (mode == kDMIC_OperationModeDma)
+    {
+        /* enable DMA request*/
+        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+    }
+}
+
+void DMIC_ConfigChannel(DMIC_Type *base,
+                        dmic_channel_t channel,
+                        stereo_side_t side,
+                        dmic_channel_config_t *channel_config)
+{
+    base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk;
+    base->CHANNEL[channel].OSR = channel_config->osr;
+    base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft;
+    base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef;
+    base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef;
+    base->CHANNEL[channel].PHY_CTRL =
+        DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate);
+    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) |
+                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) |
+                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit);
+}
+
+void DMIC_CfgChannelDc(DMIC_Type *base,
+                       dmic_channel_t channel,
+                       dc_removal_t dc_cut_level,
+                       uint32_t post_dc_gain_reduce,
+                       bool saturate16bit)
+{
+    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) |
+                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) |
+                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit);
+}
+
+void DMIC_Use2fs(DMIC_Type *base, bool use2fs)
+{
+    base->USE2FS = (use2fs) ? 0x1 : 0x0;
+}
+
+void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask)
+{
+    base->CHANEN = channelmask;
+}
+
+void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn)
+{
+    base->CHANNEL[channel].FIFO_CTRL |=
+        (base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) |
+        DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) |
+        DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn);
+}
+
+void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
+    /* Save callback pointer */
+    s_dmicCallback[instance] = cb;
+    EnableIRQ(s_dmicIRQ[instance]);
+}
+
+void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    DisableIRQ(s_dmicIRQ[instance]);
+    s_dmicCallback[instance] = NULL;
+    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
+}
+
+void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
+    /* Save callback pointer */
+    s_dmicHwvadCallback[instance] = vadcb;
+    EnableIRQ(s_dmicHwvadIRQ[instance]);
+}
+
+void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    DisableIRQ(s_dmicHwvadIRQ[instance]);
+    s_dmicHwvadCallback[instance] = NULL;
+    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(DMIC0)
+/*DMIC0 IRQ handler */
+void DMIC0_DriverIRQHandler(void)
+{
+    if (s_dmicCallback[0] != NULL)
+    {
+        s_dmicCallback[0]();
+    }
+}
+/*DMIC0 HWVAD IRQ handler */
+void HWVAD0_IRQHandler(void)
+{
+    if (s_dmicHwvadCallback[0] != NULL)
+    {
+        s_dmicHwvadCallback[0]();
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_dmic.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_DMIC_H_
+#define _FSL_DMIC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dmic_driver
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name DMIC version
+ * @{
+ */
+
+/*! @brief DMIC driver version 2.0.0. */
+#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief DMIC different operation modes. */
+typedef enum _operation_mode
+{
+    kDMIC_OperationModePoll = 0U,      /*!< Polling mode */
+    kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */
+    kDMIC_OperationModeDma = 2U,       /*!< DMA mode */
+} operation_mode_t;
+
+/*! @brief DMIC left/right values. */
+typedef enum _stereo_side
+{
+    kDMIC_Left = 0U,  /*!< Left Stereo channel */
+    kDMIC_Right = 1U, /*!< Right Stereo channel */
+} stereo_side_t;
+
+/*! @brief DMIC Clock pre-divider values. */
+typedef enum
+{
+    kDMIC_PdmDiv1 = 0U,    /*!< DMIC pre-divider set in divide by 1 */
+    kDMIC_PdmDiv2 = 1U,    /*!< DMIC pre-divider set in divide by 2 */
+    kDMIC_PdmDiv3 = 2U,    /*!< DMIC pre-divider set in divide by 3 */
+    kDMIC_PdmDiv4 = 3U,    /*!< DMIC pre-divider set in divide by 4 */
+    kDMIC_PdmDiv6 = 4U,    /*!< DMIC pre-divider set in divide by 6 */
+    kDMIC_PdmDiv8 = 5U,    /*!< DMIC pre-divider set in divide by 8 */
+    kDMIC_PdmDiv12 = 6U,   /*!< DMIC pre-divider set in divide by 12 */
+    kDMIC_PdmDiv16 = 7U,   /*!< DMIC pre-divider set in divide by 16*/
+    kDMIC_PdmDiv24 = 8U,   /*!< DMIC pre-divider set in divide by 24*/
+    kDMIC_PdmDiv32 = 9U,   /*!< DMIC pre-divider set in divide by 32 */
+    kDMIC_PdmDiv48 = 10U,  /*!< DMIC pre-divider set in divide by 48 */
+    kDMIC_PdmDiv64 = 11U,  /*!< DMIC pre-divider set in divide by 64*/
+    kDMIC_PdmDiv96 = 12U,  /*!< DMIC pre-divider set in divide by 96*/
+    kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */
+} pdm_div_t;
+
+/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */
+typedef enum _compensation
+{
+    kDMIC_CompValueZero = 0U,            /*!< Compensation 0 */
+    kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */
+    kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */
+    kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */
+} compensation_t;
+
+/*! @brief DMIC DC filter control values. */
+typedef enum _dc_removal
+{
+    kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */
+    kDMIC_DcCut155 = 1U,   /*!< Cut off Frequency is 155 Hz  */
+    kDMIC_DcCut78 = 2U,    /*!< Cut off Frequency is 78 Hz  */
+    kDMIC_DcCut39 = 3U,    /*!< Cut off Frequency is 39 Hz  */
+} dc_removal_t;
+
+/*! @brief DMIC IO configiration. */
+typedef enum _dmic_io
+{
+    kDMIC_PdmDual = 0U,       /*!< Two separate pairs of PDM wires */
+    kDMIC_PdmStereo = 4U,     /*!< Stereo Mic */
+    kDMIC_PdmBypass = 3U,     /*!< Clk Bypass clocks both channels */
+    kDMIC_PdmBypassClk0 = 1U, /*!< Clk Bypass clocks only channel0 */
+    kDMIC_PdmBypassClk1 = 2U, /*!< Clk Bypas clocks only channel1 */
+} dmic_io_t;
+
+/*! @brief DMIC Channel number. */
+typedef enum _dmic_channel
+{
+    kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */
+    kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */
+} dmic_channel_t;
+
+/*! @brief DMIC and decimator sample rates. */
+typedef enum _dmic_phy_sample_rate
+{
+    kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */
+    kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */
+} dmic_phy_sample_rate_t;
+
+/*! @brief DMIC transfer status.*/
+enum _dmic_status
+{
+    kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0),          /*!< DMIC is busy */
+    kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1),          /*!< DMIC is idle */
+    kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2),  /*!< DMIC  over run Error */
+    kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */
+};
+
+/*! @brief DMIC Channel configuration structure. */
+typedef struct _dmic_channel_config
+{
+    pdm_div_t divhfclk;                 /*!< DMIC Clock pre-divider values */
+    uint32_t osr;                       /*!< oversampling rate(CIC decimation rate) for PCM */
+    int32_t gainshft;                   /*!< 4FS PCM data gain control */
+    compensation_t preac2coef;          /*!< Pre-emphasis Filter coefficient value for 2FS */
+    compensation_t preac4coef;          /*!< Pre-emphasis Filter coefficient value for 4FS */
+    dc_removal_t dc_cut_level;          /*!< DMIC DC filter control values. */
+    uint32_t post_dc_gain_reduce;       /*!< Fine gain adjustment in the form of a number of bits to downshift */
+    dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */
+    bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate.
+                1 means if the result overflows, it saturates at 0xFFFF for positive overflow and
+                0x8000 for negative overflow.*/
+} dmic_channel_config_t;
+
+/*! @brief DMIC Callback function. */
+typedef void (*dmic_callback_t)(void);
+
+/*! @brief HWVAD Callback function. */
+typedef void (*dmic_hwvad_callback_t)(void);
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+uint32_t DMIC_GetInstance(DMIC_Type *base);
+
+/*!
+ * @brief	Turns DMIC Clock on
+ * @param	base	: DMIC base
+ * @return	Nothing
+ */
+void DMIC_Init(DMIC_Type *base);
+
+/*!
+ * @brief	Turns DMIC Clock off
+ * @param	base	: DMIC base
+ * @return	Nothing
+ */
+void DMIC_DeInit(DMIC_Type *base);
+
+/*!
+ * @brief	Configure DMIC io
+ * @param	base	: The base address of DMIC interface
+ * @param	config		: DMIC io configuration
+ * @return	Nothing
+ */
+void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config);
+
+/*!
+ * @brief	Set DMIC operating mode
+ * @param	base	: The base address of DMIC interface
+ * @param	mode	: DMIC mode
+ * @return	Nothing
+ */
+void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode);
+
+/*!
+ * @brief	Configure DMIC channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param side     : stereo_side_t, choice of left or right
+ * @param	channel_config	: Channel configuration
+ * @return	Nothing
+ */
+void DMIC_ConfigChannel(DMIC_Type *base,
+                        dmic_channel_t channel,
+                        stereo_side_t side,
+                        dmic_channel_config_t *channel_config);
+
+/*!
+ * @brief	Configure Clock scaling
+ * @param	base		: The base address of DMIC interface
+ * @param	use2fs		: clock scaling
+ * @return	Nothing
+ */
+void DMIC_Use2fs(DMIC_Type *base, bool use2fs);
+
+/*!
+ * @brief	Enable a particualr channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channelmask	: Channel selection
+ * @return	Nothing
+ */
+void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask);
+
+/*!
+ * @brief	Configure fifo settings for DMIC channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param	trig_level	: FIFO trigger level
+ * @param	enable		: FIFO level
+ * @param	resetn		: FIFO reset
+ * @return	Nothing
+ */
+void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn);
+
+/*!
+ * @brief	Get FIFO status
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @return	FIFO status
+ */
+static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel)
+{
+    return base->CHANNEL[channel].FIFO_STATUS;
+}
+
+/*!
+ * @brief	Clear FIFO status
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param	mask		: Bits to be cleared
+ * @return	FIFO status
+ */
+static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].FIFO_STATUS = mask;
+}
+
+/*!
+ * @brief	Get FIFO data
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @return	FIFO data
+ */
+static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel)
+{
+    return base->CHANNEL[channel].FIFO_DATA;
+}
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected DMIC peripheral.
+ * The callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param cb callback Pointer to store callback function.
+ * @retval None.
+ */
+void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected DMIC peripheral.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param cb callback Pointer to store callback function..
+ * @retval None.
+ */
+void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb);
+
+/**
+ * @}
+ */
+
+/*!
+ * @name hwvad
+ * @{
+ */
+
+/*!
+ * @brief Sets the gain value for the noise estimator.
+ *
+ * @param base DMIC base pointer
+ * @param value gain value for the noise estimator.
+ * @retval None.
+ */
+static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADTHGN = value & 0xFu;
+}
+
+/*!
+ * @brief Sets the gain value for the signal estimator.
+ *
+ * @param base DMIC base pointer
+ * @param value gain value for the signal estimator.
+ * @retval None.
+ */
+static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADTHGS = value & 0xFu;
+}
+
+/*!
+ * @brief Sets the hwvad filter cutoff frequency parameter.
+ *
+ * @param base DMIC base pointer
+ * @param value cut off frequency value.
+ * @retval None.
+ */
+static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADHPFS = value & 0x3u;
+}
+
+/*!
+ * @brief Sets the input gain of hwvad.
+ *
+ * @param base DMIC base pointer
+ * @param value input gain value for hwvad.
+ * @retval None.
+ */
+static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADGAIN = value & 0xFu;
+}
+
+/*!
+ * @brief Clears hwvad internal interrupt flag.
+ *
+ * @param base DMIC base pointer
+ * @param st10 bit value.
+ * @retval None.
+ */
+static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10)
+{
+    assert(NULL != base);
+    base->HWVADST10 = (st10) ? 0x1 : 0x0;
+}
+
+/*!
+ * @brief Resets hwvad filters.
+ *
+ * @param base DMIC base pointer
+ * @param rstt Reset bit value.
+ * @retval None.
+ */
+static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt)
+{
+    assert(NULL != base);
+    base->HWVADRSTT = (rstt) ? 0x1 : 0x0;
+}
+
+/*!
+ * @brief Gets the value from output of the filter z7.
+ *
+ * @param base DMIC base pointer
+ * @retval output of filter z7.
+ */
+static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base)
+{
+    assert(NULL != base);
+    return (base->HWVADLOWZ & 0xFFFFu);
+}
+
+/*!
+ * @brief	Enable hwvad callback.
+
+ * This function enables the hwvad interrupt for the selected DMIC  peripheral.
+ * The callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param vadcb callback Pointer to store callback function.
+ * @retval None.
+ */
+void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the hwvad interrupt for the selected DMIC peripheral.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param vadcb callback Pointer to store callback function..
+ * @retval None.
+ */
+void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_DMIC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_dmic_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dmic_dma.h"
+#include "fsl_dmic.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DMIC_HANDLE_ARRAY_SIZE 1
+
+/*<! Structure definition for dmic_dma_handle_t. The structure is private. */
+typedef struct _dmic_dma_private_handle
+{
+    DMIC_Type *base;
+    dmic_dma_handle_t *handle;
+} dmic_dma_private_handle_t;
+
+/*! @brief DMIC transfer state, which is used for DMIC transactiaonl APIs' internal state. */
+enum _dmic_dma_states_t
+{
+    kDMIC_Idle = 0x0, /*!< DMIC is idle state */
+    kDMIC_Busy        /*!< DMIC is busy tranferring data. */
+};
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+extern uint32_t DMIC_GetInstance(DMIC_Type *base);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*<! Private handle only used for internally. */
+static dmic_dma_private_handle_t s_dmaPrivateHandle[DMIC_HANDLE_ARRAY_SIZE];
+
+/*******************************************************************************
+ * Code
+********************************************************************************/
+
+static void DMIC_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    dmic_dma_private_handle_t *dmicPrivateHandle = (dmic_dma_private_handle_t *)param;
+    dmicPrivateHandle->handle->state = kDMIC_Idle;
+
+    if (dmicPrivateHandle->handle->callback)
+    {
+        dmicPrivateHandle->handle->callback(dmicPrivateHandle->base, dmicPrivateHandle->handle, kStatus_DMIC_Idle,
+                                            dmicPrivateHandle->handle->userData);
+    }
+}
+
+status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
+                                      dmic_dma_handle_t *handle,
+                                      dmic_dma_transfer_callback_t callback,
+                                      void *userData,
+                                      dma_handle_t *rxDmaHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check DMIC instance by 'base'*/
+    instance = DMIC_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    /* assign 'base' and 'handle' */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->rxDmaHandle = rxDmaHandle;
+
+    /* Set DMIC state to idle */
+    handle->state = kDMIC_Idle;
+    /* Configure RX. */
+    if (rxDmaHandle)
+    {
+        DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    return kStatus_Success;
+}
+
+status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
+                                 dmic_dma_handle_t *handle,
+                                 dmic_transfer_t *xfer,
+                                 uint32_t dmic_channel)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* Check if the device is busy. If previous RX not finished.*/
+    if (handle->state == kDMIC_Busy)
+    {
+        status = kStatus_DMIC_Busy;
+    }
+    else
+    {
+        handle->state = kDMIC_Busy;
+        handle->transferSize = xfer->dataSize;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t),
+                            xfer->dataSize, kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        status = kStatus_Success;
+    }
+    return status;
+}
+
+void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->rxDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+    handle->state = kDMIC_Idle;
+}
+
+status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(count);
+
+    if (kDMIC_Idle == handle->state)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_dmic_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DMIC_DMA_H_
+#define _FSL_DMIC_DMA_H_
+
+#include "fsl_common.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup dmic_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief DMIC transfer structure. */
+typedef struct _dmic_transfer
+{
+    uint16_t *data;  /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} dmic_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _dmic_dma_handle dmic_dma_handle_t;
+
+/*! @brief DMIC transfer callback function. */
+typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base,
+                                             dmic_dma_handle_t *handle,
+                                             status_t status,
+                                             void *userData);
+
+/*!
+* @brief DMIC DMA handle
+*/
+struct _dmic_dma_handle
+{
+    DMIC_Type *base;                       /*!< DMIC peripheral base address. */
+    dma_handle_t *rxDmaHandle;             /*!< The DMA RX channel used. */
+    dmic_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                        /*!< DMIC callback function parameter.*/
+    size_t transferSize;                   /*!< Size of the data to receive. */
+    volatile uint8_t state;                /*!< Internal state of DMIC DMA transfer */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name DMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMIC handle which is used in transactional functions.
+ * @param base DMIC peripheral base address.
+ * @param handle Pointer to dmic_dma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
+                                      dmic_dma_handle_t *handle,
+                                      dmic_dma_transfer_callback_t callback,
+                                      void *userData,
+                                      dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t.
+ * @param dmic_channel DMIC channel 
+ * @retval kStatus_Success
+ */
+status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
+                                 dmic_dma_handle_t *handle,
+                                 dmic_transfer_t *xfer,
+                                 uint32_t dmic_channel);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * @param base DMIC peripheral base address
+ * @param handle Pointer to dmic_dma_handle_t structure
+ */
+void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base DMIC peripheral base address.
+ * @param handle DMIC handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter count;
+ */
+status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_DMIC_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_flashiap.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flashiap.h"
+
+#define HZ_TO_KHZ_DIV 1000
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static status_t translate_iap_status(uint32_t status)
+{
+    /* Translate IAP return code to sdk status code */
+    if (status == kStatus_Success)
+    {
+        return status;
+    }
+    else
+    {
+        return MAKE_STATUS(kStatusGroup_FLASHIAP, status);
+    }
+}
+
+status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite;
+    command[1] = startSector;
+    command[2] = endSector;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_CopyRamToFlash;
+    command[1] = dstAddr;
+    command[2] = (uint32_t)srcAddr;
+    command[3] = numOfBytes;
+    command[4] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_EraseSector;
+    command[1] = startSector;
+    command[2] = endSector;
+    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_ErasePage;
+    command[1] = startPage;
+    command[2] = endPage;
+    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_BlankCheckSector;
+    command[1] = startSector;
+    command[2] = endSector;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_Compare;
+    command[1] = dstAddr;
+    command[2] = (uint32_t)srcAddr;
+    command[3] = numOfBytes;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_flashiap.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLASHIAP_H_
+#define _FSL_FLASHIAP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flashiap_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+                                                            /*@}*/
+
+/*!
+ * @brief Flashiap status codes.
+ */
+enum _flashiap_status
+{
+    kStatus_FLASHIAP_Success = kStatus_Success,                               /*!< Api is executed successfully */
+    kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */
+    kStatus_FLASHIAP_SrcAddrError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */
+    kStatus_FLASHIAP_DstAddrError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */
+    kStatus_FLASHIAP_SrcAddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */
+    kStatus_FLASHIAP_DstAddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */
+    kStatus_FLASHIAP_CountError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */
+    kStatus_FLASHIAP_InvalidSector =
+        MAKE_STATUS(kStatusGroup_FLASHIAP,
+                    7), /*!< Sector number is invalid or end sector number is greater than start sector number */
+    kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */
+    kStatus_FLASHIAP_NotPrepared =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */
+    kStatus_FLASHIAP_CompareError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */
+    kStatus_FLASHIAP_Busy =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */
+    kStatus_FLASHIAP_ParamError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */
+    kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */
+    kStatus_FLASHIAP_AddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 14U),                        /*!< Address is not mapped in the memory map */
+    kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */
+    kStatus_FLASHIAP_NoClock =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */
+};
+
+/*!
+ * @brief Flashiap command codes.
+ */
+enum _flashiap_commands
+{
+    kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */
+    kIapCmd_FLASHIAP_CopyRamToFlash = 51U,        /*!< Copy RAM to flash */
+    kIapCmd_FLASHIAP_EraseSector = 52U,           /*!< Erase Sector */
+    kIapCmd_FLASHIAP_BlankCheckSector = 53U,      /*!< Blank check sector */
+    kIapCmd_FLASHIAP_ReadPartId = 54U,            /*!< Read part id */
+    kIapCmd_FLASHIAP_Read_BootromVersion = 55U,   /*!< Read bootrom version */
+    kIapCmd_FLASHIAP_Compare = 56U,               /*!< Compare */
+    kIapCmd_FLASHIAP_ReinvokeISP = 57U,           /*!< Reinvoke ISP */
+    kIapCmd_FLASHIAP_ReadUid = 58U,               /*!< Read Uid isp */
+    kIapCmd_FLASHIAP_ErasePage = 59U,             /*!< Erase Page */
+    kIapCmd_FLASHIAP_ReadMisr = 70U,              /*!< Read Misr */
+    kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U      /*!< Reinvoke I2C/SPI isp */
+};
+
+/*! @brief IAP_ENTRY API function type */
+typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief IAP_ENTRY API function type
+ *
+ * Wrapper for rom iap call
+ *
+ * @param cmd_param IAP command and relevant parameter array.
+ * @param status_result IAP status result array.
+ *
+ * @retval None. Status/Result is returned via status_result array.
+ */
+static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result)
+{
+    ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result);
+}
+
+/*!
+ * @brief	Prepare sector for write operation
+
+ * This function prepares sector(s) for write/erase operation. This function must be
+ * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or
+ * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to
+ * start sector number.
+ *
+ * @param startSector Start sector number.
+ * @param endSector End sector number.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
+ *         is greater than start sector number.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector);
+
+/*!
+ * @brief	Copy RAM to flash.
+
+ * This function programs the flash memory. Corresponding sectors must be prepared
+ * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses
+ * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096.
+ *
+ * @param dstAddr Destination flash address where data bytes are to be written.
+ * @param srcAddr Source ram address from where data bytes are to be read.
+ * @param numOfBytes Number of bytes to be written.
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary.
+ * @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary.
+ * @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock);
+
+/*!
+ * @brief	Erase sector
+
+ * This function erases sector(s). The end sector must be greater than or equal to
+ * start sector number. FLASHIAP_PrepareSectorForWrite must be called before
+ * calling this function.
+ *
+ * @param startSector Start sector number.
+ * @param endSector End sector number.
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
+ *         is greater than start sector number.
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock);
+
+/*!
+
+ * This function erases page(s). The end page must be greater than or equal to
+ * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite
+ * before calling calling this function.
+ *
+ * @param startPage Start page number
+ * @param endPage End page number
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number
+ *         is greater than start page number
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock);
+
+/*!
+ * @brief Blank check sector(s)
+ *
+ * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to
+ * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call.
+ *
+ * @param	startSector	: Start sector number. Must be greater than or equal to start sector number
+ * @param	endSector	: End sector number
+ * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank.
+ */
+status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector);
+
+/*!
+ * @brief Compare memory contents of flash with ram.
+
+ * This function compares the contents of flash and ram. It can be used to verify the flash
+ * memory contents after FLASHIAP_CopyRamToFlash call.
+ *
+ * @param dstAddr Destination flash address.
+ * @param srcAddr Source ram address.
+ * @param numOfBytes Number of bytes to be compared.
+ *
+ * @retval #kStatus_FLASHIAP_Success Contents of flash and ram match.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary.
+ * @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
+ * @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match.
+ */
+status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLASHIAP_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_flexcomm.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = USART_IRQS;
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
+
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+    if (periph == FLEXCOMM_PERIPH_NONE)
+    {
+        return true;
+    }
+    else if ((periph >= FLEXCOMM_PERIPH_USART) && (periph <= FLEXCOMM_PERIPH_I2S_TX))
+    {
+        return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > 0 ? true : false;
+    }
+    else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+    {
+        return (base->PSELID & (1 << 7)) > 0 ? true : false;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+    {
+        if ((uint32_t)base == s_flexcommBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+/* Changes FLEXCOMM mode */
+status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+    /* Check whether peripheral type is present */
+    if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Flexcomm is locked to different peripheral type than expected  */
+    if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check if we are asked to lock */
+    if (lock)
+    {
+        base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+    }
+    else
+    {
+        base->PSELID = (uint32_t)periph;
+    }
+
+    return kStatus_Success;
+}
+
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+    int idx = FLEXCOMM_GetInstance(base);
+
+    if (idx < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_flexcommClocks[idx]);
+
+    /* Set the FLEXCOMM to given peripheral */
+    return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(base);
+
+    /* Clear handler first to avoid execution of the handler with wrong handle */
+    s_flexcommIrqHandler[instance] = NULL;
+    s_flexcommHandle[instance] = handle;
+    s_flexcommIrqHandler[instance] = handler;
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[0]);
+    s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
+}
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 1U)
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[1]);
+    s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 2U)
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[2]);
+    s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 3U)
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[3]);
+    s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 4U)
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[4]);
+    s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
+}
+
+#endif
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 5U)
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[5]);
+    s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 6U)
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[6]);
+    s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 7U)
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[7]);
+    s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_flexcomm.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_fmeas.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fmeas.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Target clock counter value.
+ * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */
+#define TARGET_CLOCK_COUNT(base) \
+    ((uint32_t)(                 \
+        ((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2))
+
+/*! @brief Reference clock counter value. */
+#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1))
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate)
+{
+    uint32_t targetClockCount = TARGET_CLOCK_COUNT(base);
+    uint64_t clkrate = 0;
+
+    if (targetClockCount > 0)
+    {
+        clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT;
+    }
+
+    return (uint32_t)clkrate;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_fmeas.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FMEAS_H_
+#define _FSL_FMEAS_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup fmeas
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines LPC Frequency Measure driver version 2.0.0.
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name FMEAS Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief    Starts a frequency measurement cycle.
+ *
+ * @param    base : SYSCON peripheral base address.
+ */
+static inline void FMEAS_StartMeasure(SYSCON_Type *base)
+{
+    base->FREQMECTRL = 0;
+    base->FREQMECTRL = (1UL << 31);
+}
+
+/*!
+ * @brief    Indicates when a frequency measurement cycle is complete.
+ *
+ * @param    base : SYSCON peripheral base address.
+ * @return   true if a measurement cycle is active, otherwise false.
+ */
+static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base)
+{
+    return (bool)((base->FREQMECTRL & (1UL << 31)) == 0);
+}
+
+/*!
+ * @brief    Returns the computed value for a frequency measurement cycle
+ *
+ * @param    base         : SYSCON peripheral base address.
+ * @param    refClockRate : Reference clock rate used during the frequency measurement cycle.
+ *
+ * @return   Frequency in Hz.
+ */
+uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_FMEAS_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gint.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gint.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to GINT bases for each instance. */
+static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS;
+
+/*! @brief Clocks for each instance. */
+static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS;
+
+/*! @brief Resets for each instance. */
+static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS;
+
+/* @brief Irq number for each instance */
+static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS;
+
+/*! @brief Callback function array for GINT(s). */
+static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GINT_GetInstance(GINT_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_GINT_COUNT; instance++)
+    {
+        if (s_gintBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_GINT_COUNT);
+
+    return instance;
+}
+
+void GINT_Init(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    s_gintCallback[instance] = NULL;
+
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_gintClocks[instance]);
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(s_gintResets[instance]);
+}
+
+void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig));
+
+    /* Save callback pointer */
+    s_gintCallback[instance] = callback;
+}
+
+void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
+    *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
+    *callback = s_gintCallback[instance];
+}
+
+void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask)
+{
+    base->PORT_POL[port] = polarityMask;
+    base->PORT_ENA[port] = enableMask;
+}
+
+void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask)
+{
+    *polarityMask = base->PORT_POL[port];
+    *enableMask = base->PORT_ENA[port];
+}
+
+void GINT_EnableCallback(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+    /* If GINT is configured in "AND" mode a spurious interrupt is generated.
+       Clear status and pending interrupt before enabling the irq in NVIC. */
+    GINT_ClrStatus(base);
+    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
+    EnableIRQ(s_gintIRQ[instance]);
+}
+
+void GINT_DisableCallback(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+    DisableIRQ(s_gintIRQ[instance]);
+    GINT_ClrStatus(base);
+    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
+}
+
+void GINT_Deinit(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    /* Cleanup */
+    GINT_DisableCallback(base);
+    s_gintCallback[instance] = NULL;
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(s_gintResets[instance]);
+
+    /* Disable the peripheral clock */
+    CLOCK_DisableClock(s_gintClocks[instance]);
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+void GINT0_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[0] != NULL)
+    {
+        s_gintCallback[0]();
+    }
+}
+
+#if (FSL_FEATURE_SOC_GINT_COUNT > 1U)
+void GINT1_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[1] != NULL)
+    {
+        s_gintCallback[1]();
+    }
+}
+#endif
+
+#if (FSL_FEATURE_SOC_GINT_COUNT > 2U)
+void GINT2_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[2] != NULL)
+    {
+        s_gintCallback[2]();
+    }
+}
+#endif
+
+#if (FSL_FEATURE_SOC_GINT_COUNT > 3U)
+void GINT3_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[3] != NULL)
+    {
+        s_gintCallback[3]();
+    }
+}
+#endif
+
+#if (FSL_FEATURE_SOC_GINT_COUNT > 4U)
+void GINT4_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[4] != NULL)
+    {
+        s_gintCallback[4]();
+    }
+}
+#endif
+
+#if (FSL_FEATURE_SOC_GINT_COUNT > 5U)
+void GINT5_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[5] != NULL)
+    {
+        s_gintCallback[5]();
+    }
+}
+#endif
+
+#if (FSL_FEATURE_SOC_GINT_COUNT > 6U)
+void GINT6_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[6] != NULL)
+    {
+        s_gintCallback[6]();
+    }
+}
+#endif
+
+#if (FSL_FEATURE_SOC_GINT_COUNT > 7U)
+void GINT7_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[7] != NULL)
+    {
+        s_gintCallback[7]();
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gint.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_GINT_H_
+#define _FSL_GINT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gint_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+/*! @brief GINT combine inputs type */
+typedef enum _gint_comb
+{
+    kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */
+    kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */
+} gint_comb_t;
+
+/*! @brief GINT trigger type */
+typedef enum _gint_trig
+{
+    kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */
+    kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */
+} gint_trig_t;
+
+/* @brief GINT port type */
+typedef enum _gint_port
+{
+    kGINT_Port0 = 0U,
+    kGINT_Port1 = 1U,
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U)
+    kGINT_Port2 = 2U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U)
+    kGINT_Port3 = 3U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U)
+    kGINT_Port4 = 4U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U)
+    kGINT_Port5 = 5U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U)
+    kGINT_Port6 = 6U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U)
+    kGINT_Port7 = 7U,
+#endif
+} gint_port_t;
+
+/*! @brief GINT Callback function. */
+typedef void (*gint_cb_t)(void);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize GINT peripheral.
+
+ * This function initializes the GINT peripheral and enables the clock.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_Init(GINT_Type *base);
+
+/*!
+ * @brief	Setup GINT peripheral control parameters.
+
+ * This function sets the control parameters of GINT peripheral.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
+ * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
+ * @param callback This function is called when configured group interrupt is generated.
+ *
+ * @retval None.
+ */
+void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback);
+
+/*!
+ * @brief	Get GINT peripheral control parameters.
+
+ * This function returns the control parameters of GINT peripheral.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param comb Pointer to store combine input value.
+ * @param trig Pointer to store trigger value.
+ * @param callback Pointer to store callback function.
+ *
+ * @retval None.
+ */
+void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback);
+
+/*!
+ * @brief	Configure GINT peripheral pins.
+
+ * This function enables and controls the polarity of enabled pin(s) of a given port.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param port Port number.
+ * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
+ *        0 = The pin is active LOW. 1 = The pin is active HIGH.
+ * @param enableMask Each bit position selects if the corresponding pin is enabled or not.
+ *        0 = The pin is disabled. 1 = The pin is enabled.
+ *
+ * @retval None.
+ */
+void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask);
+
+/*!
+ * @brief	Get GINT peripheral pin configuration.
+
+ * This function returns the pin configuration of a given port.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param port Port number.
+ * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
+ enabled pin.
+ *        0 = The pin is active LOW. 1 = The pin is active HIGH.
+ * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
+ or not.
+ *        0 = The pin is disabled. 1 = The pin is enabled.
+ *
+ * @retval None.
+ */
+void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask);
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
+ * as soon as they are enabled, the callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_EnableCallback(GINT_Type *base);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected GINT peripheral. Although the pins are still
+ * being monitored but the callback function is not called.
+ *
+ * @param base Base address of the peripheral.
+ *
+ * @retval None.
+ */
+void GINT_DisableCallback(GINT_Type *base);
+
+/*!
+ * @brief	Clear GINT status.
+
+ * This function clears the GINT status bit.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void GINT_ClrStatus(GINT_Type *base)
+{
+    base->CTRL |= GINT_CTRL_INT_MASK;
+}
+
+/*!
+ * @brief	Get GINT status.
+
+ * This function returns the GINT status.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval status = 0 No group interrupt request.  = 1 Group interrupt request active.
+ */
+static inline uint32_t GINT_GetStatus(GINT_Type *base)
+{
+    return (base->CTRL & GINT_CTRL_INT_MASK);
+}
+
+/*!
+ * @brief	Deinitialize GINT peripheral.
+
+ * This function disables the GINT clock.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_Deinit(GINT_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_GINT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+* Prototypes
+************ ******************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->DIR[port] &= ~(1U << pin);
+    }
+    else
+    {
+        base->DIR[port] |= 1U << pin;
+        /* Set default output value */
+        if (config->outputLogic == 0U)
+        {
+            base->CLR[port] = (1U << pin);
+        }
+        else
+        {
+            base->PIN[port] = (1U << pin);
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPC GPIO driver version 1.0.0. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*@}*/
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+    base->B[port][pin] = output;
+}
+/*@}*/
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+    return (uint32_t)base->B[port][pin];
+}
+/*@}*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->NOT[port] = mask;
+}
+/*@}*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->PIN[port];
+}
+
+/*@}*/
+/*! @name GPIO Mask Operations */
+/*@{*/
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param output  GPIO port output value.
+ */
+static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+    base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @retval       masked GPIO port value
+ */
+static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->MPIN[port];
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2c.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1382 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c.h"
+#include "fsl_flexcomm.h"
+#include <stdlib.h>
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Common sets of flags used by the driver. */
+enum _i2c_flag_constants
+{
+    kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK,
+    kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK,
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+static void I2C_SlaveInternalStateMachineReset(I2C_Type *base);
+static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal);
+static uint32_t I2C_SlavePollPending(I2C_Type *base);
+static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event);
+static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
+static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
+                                                     i2c_slave_handle_t *handle,
+                                                     const void *txData,
+                                                     size_t txSize,
+                                                     void *rxData,
+                                                     size_t rxSize,
+                                                     uint32_t eventMask);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Returns an instance number given a base address.
+ *
+ * If an invalid base address is passed, debug builds will assert. Release builds will just return
+ * instance number 0.
+ *
+ * @param base The I2C peripheral base address.
+ * @return I2C instance number starting from 0.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base)
+{
+    return FLEXCOMM_GetInstance(base);
+}
+
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
+{
+    masterConfig->enableMaster = true;
+    masterConfig->baudRate_Bps = 100000U;
+    masterConfig->enableTimeout = false;
+}
+
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
+    I2C_MasterEnable(base, masterConfig->enableMaster);
+    I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
+}
+
+void I2C_MasterDeinit(I2C_Type *base)
+{
+    I2C_MasterEnable(base, false);
+}
+
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t scl, divider;
+    uint32_t best_scl, best_div;
+    uint32_t err, best_err;
+
+    best_err = 0;
+
+    for (scl = 9; scl >= 2; scl--)
+    {
+        /* calculated ideal divider value for given scl */
+        divider = srcClock_Hz / (baudRate_Bps * scl * 2u);
+
+        /* adjust it if it is out of range */
+        divider = (divider > 0x10000u) ? 0x10000 : divider;
+
+        /* calculate error */
+        err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider);
+        if ((err < best_err) || (best_err == 0))
+        {
+            best_div = divider;
+            best_scl = scl;
+            best_err = err;
+        }
+
+        if ((err == 0) || (divider >= 0x10000u))
+        {
+            /* either exact value was found
+               or divider is at its max (it would even greater in the next iteration for sure) */
+            break;
+        }
+    }
+
+    base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1);
+    base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u);
+}
+
+static uint32_t I2C_PendingStatusWait(I2C_Type *base)
+{
+    uint32_t status;
+
+    do
+    {
+        status = I2C_GetStatusFlags(base);
+    } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+    /* Clear controller state. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    return status;
+}
+
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    I2C_PendingStatusWait(base);
+
+    /* Write Address and RW bit to data register */
+    base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u);
+    /* Start the transfer */
+    base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterStop(I2C_Type *base)
+{
+    I2C_PendingStatusWait(base);
+
+    base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+    return kStatus_Success;
+}
+
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)
+{
+    uint32_t status;
+    uint32_t master_state;
+    status_t err;
+
+    const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff;
+
+    assert(txBuff);
+
+    err = kStatus_Success;
+    while (txSize)
+    {
+        status = I2C_PendingStatusWait(base);
+
+        if (status & I2C_STAT_MSTARBLOSS_MASK)
+        {
+            return kStatus_I2C_ArbitrationLost;
+        }
+
+        if (status & I2C_STAT_MSTSTSTPERR_MASK)
+        {
+            return kStatus_I2C_StartStopError;
+        }
+
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+        switch (master_state)
+        {
+            case I2C_STAT_MSTCODE_TXREADY:
+                /* ready to send next byte */
+                base->MSTDAT = *buf++;
+                txSize--;
+                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+                break;
+
+            case I2C_STAT_MSTCODE_NACKADR:
+            case I2C_STAT_MSTCODE_NACKDAT:
+                /* slave nacked the last byte */
+                err = kStatus_I2C_Nak;
+                break;
+
+            default:
+                /* unexpected state */
+                err = kStatus_I2C_UnexpectedState;
+                break;
+        }
+
+        if (err != kStatus_Success)
+        {
+            return err;
+        }
+    }
+
+    status = I2C_PendingStatusWait(base);
+
+    if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0)
+    {
+        if (!(flags & kI2C_TransferNoStopFlag))
+        {
+            /* Initiate stop */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            status = I2C_PendingStatusWait(base);
+        }
+    }
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        return kStatus_I2C_StartStopError;
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)
+{
+    uint32_t status = 0;
+    uint32_t master_state;
+    status_t err;
+
+    uint8_t *buf = (uint8_t *)(rxBuff);
+
+    assert(rxBuff);
+
+    err = kStatus_Success;
+    while (rxSize)
+    {
+        status = I2C_PendingStatusWait(base);
+
+        if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK))
+        {
+            break;
+        }
+
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+        switch (master_state)
+        {
+            case I2C_STAT_MSTCODE_RXREADY:
+                /* ready to send next byte */
+                *(buf++) = base->MSTDAT;
+                if (--rxSize)
+                {
+                    base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+                }
+                else
+                {
+                    if ((flags & kI2C_TransferNoStopFlag) == 0)
+                    {
+                        /* initiate NAK and stop */
+                        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+                        status = I2C_PendingStatusWait(base);
+                    }
+                }
+                break;
+
+            case I2C_STAT_MSTCODE_NACKADR:
+            case I2C_STAT_MSTCODE_NACKDAT:
+                /* slave nacked the last byte */
+                err = kStatus_I2C_Nak;
+                break;
+
+            default:
+                /* unexpected state */
+                err = kStatus_I2C_UnexpectedState;
+                break;
+        }
+
+        if (err != kStatus_Success)
+        {
+            return err;
+        }
+    }
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        return kStatus_I2C_StartStopError;
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
+{
+    status_t result = kStatus_Success;
+    uint32_t subaddress;
+    uint8_t subaddrBuf[4];
+    int i;
+
+    assert(xfer);
+
+    /* If repeated start is requested, send repeated start. */
+    if (!(xfer->flags & kI2C_TransferNoStartFlag))
+    {
+        if (xfer->subaddressSize)
+        {
+            result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write);
+            if (result == kStatus_Success)
+            {
+                /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+                subaddress = xfer->subaddress;
+                for (i = xfer->subaddressSize - 1; i >= 0; i--)
+                {
+                    subaddrBuf[i] = subaddress & 0xff;
+                    subaddress >>= 8;
+                }
+                /* Send subaddress. */
+                result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag);
+                if ((result == kStatus_Success) && (xfer->direction == kI2C_Read))
+                {
+                    result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
+                }
+            }
+        }
+        else if (xfer->flags & kI2C_TransferRepeatedStartFlag)
+        {
+            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
+        }
+        else
+        {
+            result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction);
+        }
+    }
+
+    if (result == kStatus_Success)
+    {
+        if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
+        {
+            /* Transmit data. */
+            result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
+        }
+        else
+        {
+            if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
+            {
+                /* Receive Data. */
+                result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
+            }
+        }
+    }
+
+    if (result == kStatus_I2C_Nak)
+    {
+        I2C_MasterStop(base);
+    }
+
+    return result;
+}
+
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData)
+{
+    uint32_t instance;
+
+    assert(handle);
+
+    /* Clear out the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Save base and instance. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+    EnableIRQ(kFlexcommIrqs[instance]);
+}
+
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result;
+
+    assert(handle);
+    assert(xfer);
+    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->state != kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+    /* Prepare transfer state machine. */
+    result = I2C_InitTransferStateMachine(base, handle, xfer);
+
+    /* Clear error flags. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    /* Enable I2C internal IRQ sources. */
+    I2C_EnableInterrupts(base, kI2C_MasterIrqFlags);
+
+    return result;
+}
+
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == kIdleState)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* There is no necessity to disable interrupts as we read a single integer value */
+    *count = handle->transferCount;
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    uint32_t status;
+    uint32_t master_state;
+
+    if (handle->state != kIdleState)
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+        /* Wait until module is ready */
+        status = I2C_PendingStatusWait(base);
+
+        /* Get the state of the I2C module */
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+        if (master_state != I2C_STAT_MSTCODE_IDLE)
+        {
+            /* Send a stop command to finalize the transfer. */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+
+            /* Wait until the STOP is completed */
+            I2C_PendingStatusWait(base);
+        }
+
+        /* Reset handle. */
+        handle->state = kIdleState;
+    }
+}
+
+/*!
+ * @brief Prepares the transfer state machine and fills in the command buffer.
+ * @param handle Master nonblocking driver handle.
+ */
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    struct _i2c_master_transfer *transfer;
+
+    handle->transfer = *xfer;
+    transfer = &(handle->transfer);
+
+    handle->transferCount = 0;
+    handle->remainingBytes = transfer->dataSize;
+    handle->buf = (uint8_t *)transfer->data;
+    handle->remainingSubaddr = 0;
+
+    if (transfer->flags & kI2C_TransferNoStartFlag)
+    {
+        /* Start condition shall be ommited, switch directly to next phase */
+        if (transfer->dataSize == 0)
+        {
+            handle->state = kStopState;
+        }
+        else if (handle->transfer.direction == kI2C_Write)
+        {
+            handle->state = kTransmitDataState;
+        }
+        else if (handle->transfer.direction == kI2C_Read)
+        {
+            handle->state = kReceiveDataState;
+        }
+        else
+        {
+            return kStatus_I2C_InvalidParameter;
+        }
+    }
+    else
+    {
+        if (transfer->subaddressSize != 0)
+        {
+            int i;
+            uint32_t subaddress;
+
+            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
+            {
+                return kStatus_I2C_InvalidParameter;
+            }
+
+            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+            subaddress = xfer->subaddress;
+            for (i = xfer->subaddressSize - 1; i >= 0; i--)
+            {
+                handle->subaddrBuf[i] = subaddress & 0xff;
+                subaddress >>= 8;
+            }
+            handle->remainingSubaddr = transfer->subaddressSize;
+        }
+        handle->state = kStartState;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Execute states until FIFOs are exhausted.
+ * @param handle Master nonblocking driver handle.
+ * @param[out] isDone Set to true if the transfer has completed.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_ArbitrationLost
+ * @retval #kStatus_I2C_Nak
+ */
+static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
+{
+    uint32_t status;
+    uint32_t master_state;
+    struct _i2c_master_transfer *transfer;
+    status_t err;
+
+    transfer = &(handle->transfer);
+
+    *isDone = false;
+
+    status = I2C_GetStatusFlags(base);
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
+        return kStatus_I2C_StartStopError;
+    }
+
+    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Get the state of the I2C module */
+    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
+    {
+        /* Slave NACKed last byte, issue stop and return error */
+        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+        handle->state = kWaitForCompletionState;
+        return kStatus_I2C_Nak;
+    }
+
+    err = kStatus_Success;
+    switch (handle->state)
+    {
+        case kStartState:
+            if (handle->remainingSubaddr)
+            {
+                /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */
+                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+                handle->state = kTransmitSubaddrState;
+            }
+            else if (transfer->direction == kI2C_Write)
+            {
+                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+                handle->state = handle->remainingBytes ? kTransmitDataState : kStopState;
+            }
+            else
+            {
+                base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
+                handle->state = handle->remainingBytes ? kReceiveDataState : kStopState;
+            }
+            /* Send start condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+            break;
+
+        case kTransmitSubaddrState:
+            if (master_state != I2C_STAT_MSTCODE_TXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            /* Most significant subaddress byte comes first */
+            base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr];
+            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            if (--(handle->remainingSubaddr))
+            {
+                /* There are still subaddress bytes to be transmitted */
+                break;
+            }
+            if (handle->remainingBytes)
+            {
+                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
+                 * repeated start */
+                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
+            }
+            else
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            break;
+
+        case kTransmitDataState:
+            if (master_state != I2C_STAT_MSTCODE_TXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+            base->MSTDAT = *(handle->buf)++;
+            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            if (--handle->remainingBytes == 0)
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            handle->transferCount++;
+            break;
+
+        case kReceiveDataState:
+            if (master_state != I2C_STAT_MSTCODE_RXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+            *(handle->buf)++ = base->MSTDAT;
+            if (--handle->remainingBytes)
+            {
+                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            }
+            else
+            {
+                /* No more data expected, issue NACK and STOP right away */
+                base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+                handle->state = kWaitForCompletionState;
+            }
+            handle->transferCount++;
+            break;
+
+        case kStopState:
+            if (transfer->flags & kI2C_TransferNoStopFlag)
+            {
+                /* Stop condition is omitted, we are done */
+                *isDone = true;
+                handle->state = kIdleState;
+                break;
+            }
+            /* Send stop condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kWaitForCompletionState:
+            *isDone = true;
+            handle->state = kIdleState;
+            break;
+
+        case kIdleState:
+        default:
+            /* State machine shall not be invoked again once it enters the idle state */
+            err = kStatus_I2C_UnexpectedState;
+            break;
+    }
+
+    return err;
+}
+
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    bool isDone;
+    status_t result;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    result = I2C_RunTransferStateMachine(base, handle, &isDone);
+
+    if (isDone || (result != kStatus_Success))
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+        /* Invoke callback. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+/*!
+ * @brief Sets the hardware slave state machine to reset
+ *
+ * Per documentation, the only the state machine is reset, the configuration settings remain.
+ *
+ * @param base The I2C peripheral base address.
+ */
+static void I2C_SlaveInternalStateMachineReset(I2C_Type *base)
+{
+    I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */
+}
+
+/*!
+ * @brief Compute CLKDIV
+ *
+ * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency.
+ * This setting is used by hardware during slave clock stretching.
+ *
+ * @param base The I2C peripheral base address.
+ * @return status of the operation
+ */
+static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal)
+{
+    uint32_t dataSetupTime_ns;
+
+    switch (busSpeed)
+    {
+        case kI2C_SlaveStandardMode:
+            dataSetupTime_ns = 250u;
+            break;
+
+        case kI2C_SlaveFastMode:
+            dataSetupTime_ns = 100u;
+            break;
+
+        case kI2C_SlaveFastModePlus:
+            dataSetupTime_ns = 50u;
+            break;
+
+        case kI2C_SlaveHsMode:
+            dataSetupTime_ns = 10u;
+            break;
+
+        default:
+            dataSetupTime_ns = 0;
+            break;
+    }
+
+    if (0 == dataSetupTime_ns)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */
+    *divVal = srcClock_Hz / 1000u;
+    *divVal = (*divVal) * dataSetupTime_ns;
+    *divVal = (*divVal) / 1000000u;
+
+    if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK)
+    {
+        *divVal = I2C_CLKDIV_DIVVAL_MASK;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Poll wait for the SLVPENDING flag.
+ *
+ * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
+ *
+ * @param base The I2C peripheral base address.
+ * @return status register at time the SLVPENDING bit is read as set
+ */
+static uint32_t I2C_SlavePollPending(I2C_Type *base)
+{
+    uint32_t stat;
+
+    do
+    {
+        stat = base->STAT;
+    } while (0u == (stat & I2C_STAT_SLVPENDING_MASK));
+
+    return stat;
+}
+
+/*!
+ * @brief Invoke event from I2C_SlaveTransferHandleIRQ().
+ *
+ * Sets the event type to transfer structure and invokes the event callback, if it has been
+ * enabled by eventMask.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle The I2C slave handle for non-blocking APIs.
+ * @param event The I2C slave event to invoke.
+ */
+static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event)
+{
+    handle->transfer.event = event;
+    if ((handle->callback) && (handle->transfer.eventMask & event))
+    {
+        handle->callback(base, &handle->transfer, handle->userData);
+
+        /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */
+        if (false == handle->isBusy)
+        {
+            if (((handle->transfer.txData) && (handle->transfer.txSize)) ||
+                ((handle->transfer.rxData) && (handle->transfer.rxSize)))
+            {
+                handle->isBusy = true;
+            }
+        }
+
+        /* Clear the transferred count now that we have a new buffer. */
+        if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent))
+        {
+            handle->transfer.transferredCount = 0;
+        }
+    }
+}
+
+/*!
+ * @brief Handle slave address match event.
+ *
+ * Called by Slave interrupt routine to ACK or NACK the matched address.
+ * It also determines master direction (read or write).
+ *
+ * @param base The I2C peripheral base address.
+ * @return true if the matched address is ACK'ed
+ * @return false if the matched address is NACK'ed
+ */
+static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    uint8_t addressByte0;
+
+    addressByte0 = (uint8_t)base->SLVDAT;
+
+    /* store the matched address */
+    handle->transfer.receivedAddress = addressByte0;
+
+    /* R/nW */
+    if (addressByte0 & 1u)
+    {
+        /* if we have no data in this transfer, call callback to get new */
+        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+        {
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
+        }
+
+        /* NACK if we have no data in this transfer. */
+        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+        {
+            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+            return false;
+        }
+
+        /* master wants to read, so slave transmit is next state */
+        handle->slaveFsm = kI2C_SlaveFsmTransmit;
+    }
+    else
+    {
+        /* if we have no receive buffer in this transfer, call callback to get new */
+        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+        {
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
+        }
+
+        /* NACK if we have no data in this transfer */
+        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+        {
+            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+            return false;
+        }
+
+        /* master wants write, so slave receive is next state */
+        handle->slaveFsm = kI2C_SlaveFsmReceive;
+    }
+
+    /* continue transaction */
+    base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+    return true;
+}
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
+ * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only.
+ * @param txSize Size of txData buffer in bytes.
+ * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL
+ *               if slave TX only.
+ * @param rxSize Size of rxData buffer in bytes.
+ *
+ * @retval #kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
+                                                     i2c_slave_handle_t *handle,
+                                                     const void *txData,
+                                                     size_t txSize,
+                                                     void *rxData,
+                                                     size_t rxSize,
+                                                     uint32_t eventMask)
+{
+    status_t status;
+
+    assert(handle);
+
+    status = kStatus_Success;
+
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->isBusy)
+    {
+        status = kStatus_I2C_Busy;
+    }
+
+    /* Save transfer into handle. */
+    handle->transfer.txData = (const uint8_t *)(uintptr_t)txData;
+    handle->transfer.txSize = txSize;
+    handle->transfer.rxData = (uint8_t *)rxData;
+    handle->transfer.rxSize = rxSize;
+    handle->transfer.transferredCount = 0;
+    handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent;
+    handle->isBusy = true;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* Clear w1c flags. */
+    base->STAT |= 0u;
+
+    /* Enable I2C internal IRQ sources. */
+    I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    return status;
+}
+
+status_t I2C_SlaveSetSendBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask);
+}
+
+status_t I2C_SlaveSetReceiveBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask);
+}
+
+void I2C_SlaveSetAddress(I2C_Type *base,
+                         i2c_slave_address_register_t addressRegister,
+                         uint8_t address,
+                         bool addressDisable)
+{
+    base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable);
+}
+
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
+{
+    assert(slaveConfig);
+
+    i2c_slave_config_t mySlaveConfig = {0};
+
+    /* default config enables slave address 0 match to general I2C call address zero */
+    mySlaveConfig.enableSlave = true;
+    mySlaveConfig.address1.addressDisable = true;
+    mySlaveConfig.address2.addressDisable = true;
+    mySlaveConfig.address3.addressDisable = true;
+
+    *slaveConfig = mySlaveConfig;
+}
+
+status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
+{
+    status_t status;
+    uint32_t divVal = 0;
+
+    /* configure data setup time used when slave stretches clock */
+    status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
+
+    /* I2C Clock Divider register */
+    base->CLKDIV = divVal;
+
+    /* set Slave address */
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address,
+                        slaveConfig->address0.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address,
+                        slaveConfig->address1.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address,
+                        slaveConfig->address2.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address,
+                        slaveConfig->address3.addressDisable);
+
+    /* set Slave address 0 qual */
+    base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress);
+
+    /* set Slave enable */
+    base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave);
+
+    return status;
+}
+
+void I2C_SlaveDeinit(I2C_Type *base)
+{
+    I2C_SlaveEnable(base, false);
+}
+
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+{
+    const uint8_t *buf = txBuff;
+    uint32_t stat;
+    bool slaveAddress;
+    bool slaveTransmit;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* wait for SLVPENDING */
+    stat = I2C_SlavePollPending(base);
+
+    /* Get slave machine state */
+    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+    slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+    /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */
+    if (!(slaveAddress || slaveTransmit))
+    {
+        I2C_SlaveInternalStateMachineReset(base);
+        return kStatus_Fail;
+    }
+
+    if (slaveAddress)
+    {
+        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* wait for SLVPENDING */
+        stat = I2C_SlavePollPending(base);
+    }
+
+    /* send bytes up to txSize */
+    while (txSize)
+    {
+        slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+        if (!slaveTransmit)
+        {
+            I2C_SlaveInternalStateMachineReset(base);
+            return kStatus_Fail;
+        }
+
+        /* Write 8 bits of data to the SLVDAT register */
+        base->SLVDAT = I2C_SLVDAT_DATA(*buf);
+
+        /* continue transaction */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* advance counters and pointers for next data */
+        buf++;
+        txSize--;
+
+        if (txSize)
+        {
+            /* wait for SLVPENDING */
+            stat = I2C_SlavePollPending(base);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+{
+    uint8_t *buf = rxBuff;
+    uint32_t stat;
+    bool slaveAddress;
+    bool slaveReceive;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* wait for SLVPENDING */
+    stat = I2C_SlavePollPending(base);
+
+    /* Get slave machine state */
+    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+    slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+    /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */
+    if (!(slaveAddress || slaveReceive))
+    {
+        I2C_SlaveInternalStateMachineReset(base);
+        return kStatus_Fail;
+    }
+
+    if (slaveAddress)
+    {
+        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* wait for SLVPENDING */
+        stat = I2C_SlavePollPending(base);
+    }
+
+    /* receive bytes up to rxSize */
+    while (rxSize)
+    {
+        slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+        if (!slaveReceive)
+        {
+            I2C_SlaveInternalStateMachineReset(base);
+            return kStatus_Fail;
+        }
+
+        /* Read 8 bits of data from the SLVDAT register */
+        *buf = (uint8_t)base->SLVDAT;
+
+        /* continue transaction */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* advance counters and pointers for next data */
+        buf++;
+        rxSize--;
+
+        if (rxSize)
+        {
+            /* wait for SLVPENDING */
+            stat = I2C_SlavePollPending(base);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData)
+{
+    uint32_t instance;
+
+    assert(handle);
+
+    /* Clear out the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Save base and instance. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* initialize fsm */
+    handle->slaveFsm = kI2C_SlaveFsmAddressMatch;
+
+    /* store pointer to handle into transfer struct */
+    handle->transfer.handle = handle;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_SlaveTransferHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+    EnableIRQ(kFlexcommIrqs[instance]);
+}
+
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask);
+}
+
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (!handle->isBusy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* For an active transfer, just return the count from the handle. */
+    *count = handle->transfer.transferredCount;
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    /* Set the SLVEN bit to 0 in the CFG register. */
+    I2C_SlaveEnable(base, false);
+
+    handle->isBusy = false;
+    handle->transfer.txSize = 0;
+    handle->transfer.rxSize = 0;
+}
+
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    uint32_t i2cStatus = base->STAT;
+
+    if (i2cStatus & I2C_STAT_SLVDESEL_MASK)
+    {
+        I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent);
+        I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK);
+    }
+
+    /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */
+    if (i2cStatus & I2C_STAT_SLVPENDING_MASK)
+    {
+        bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+
+        if (slaveAddress)
+        {
+            I2C_SlaveAddressIRQ(base, handle);
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent);
+        }
+        else
+        {
+            switch (handle->slaveFsm)
+            {
+                case kI2C_SlaveFsmReceive:
+                {
+                    bool slaveReceive =
+                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+                    if (slaveReceive)
+                    {
+                        /* if we have no receive buffer in this transfer, call callback to get new */
+                        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+                        {
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
+                        }
+
+                        /* receive a byte */
+                        if ((handle->transfer.rxData) && (handle->transfer.rxSize))
+                        {
+                            *(handle->transfer.rxData) = (uint8_t)base->SLVDAT;
+                            (handle->transfer.rxSize)--;
+                            (handle->transfer.rxData)++;
+                            (handle->transfer.transferredCount)++;
+
+                            /* continue transaction */
+                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+                        }
+
+                        /* is this last transaction for this transfer? allow next transaction */
+                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
+                        {
+                            handle->isBusy = false;
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
+                        }
+                    }
+                    else
+                    {
+                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+                    }
+                }
+                break;
+
+                case kI2C_SlaveFsmTransmit:
+                {
+                    bool slaveTransmit =
+                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+                    if (slaveTransmit)
+                    {
+                        /* if we have no data in this transfer, call callback to get new */
+                        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+                        {
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
+                        }
+
+                        /* transmit a byte */
+                        if ((handle->transfer.txData) && (handle->transfer.txSize))
+                        {
+                            base->SLVDAT = *(handle->transfer.txData);
+                            (handle->transfer.txSize)--;
+                            (handle->transfer.txData)++;
+                            (handle->transfer.transferredCount)++;
+
+                            /* continue transaction */
+                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+                        }
+
+                        /* is this last transaction for this transfer? allow next transaction */
+                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
+                        {
+                            handle->isBusy = false;
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
+                        }
+                    }
+                    else
+                    {
+                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+                    }
+                }
+                break;
+
+                default:
+                    /* incorrect state, slv_abort()? */
+                    break;
+            }
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2c.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1038 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_H_
+#define _FSL_I2C_H_
+
+#include <stddef.h>
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define I2C_CFG_MASK 0x1f
+
+/*!
+ * @addtogroup i2c_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C driver version 1.0.0. */
+#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*@}*/
+
+/* definitions for MSTCODE bits in I2C Status register STAT */
+#define I2C_STAT_MSTCODE_IDLE (0)    /*!< Master Idle State Code */
+#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
+#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */
+#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */
+#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */
+
+/* definitions for SLVSTATE bits in I2C Status register STAT */
+#define I2C_STAT_SLVST_ADDR (0)
+#define I2C_STAT_SLVST_RX (1)
+#define I2C_STAT_SLVST_TX (2)
+
+/*! @brief I2C status return codes. */
+enum _i2c_status
+{
+    kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */
+    kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */
+    kStatus_I2C_Nak =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */
+    kStatus_I2C_InvalidParameter =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */
+    kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */
+    kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */
+    kStatus_I2C_NoTransferInProgress =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */
+    kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */
+    kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8),
+    kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9),
+};
+
+/*! @} */
+
+/*!
+ * @addtogroup i2c_master_driver
+ * @{
+ */
+
+/*!
+ * @brief I2C master peripheral flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _i2c_master_flags
+{
+    kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
+    kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */
+    kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */
+};
+
+/*! @brief Direction of master and slave transfers. */
+typedef enum _i2c_direction
+{
+    kI2C_Write = 0U, /*!< Master transmit. */
+    kI2C_Read = 1U   /*!< Master receive. */
+} i2c_direction_t;
+
+/*!
+ * @brief Structure with settings to initialize the I2C master module.
+ *
+ * This structure holds configuration settings for the I2C peripheral. To initialize this
+ * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and
+ * pass a pointer to your configuration structure instance.
+ *
+ * The configuration structure can be made constant so it resides in flash.
+ */
+typedef struct _i2c_master_config
+{
+    bool enableMaster;     /*!< Whether to enable master mode. */
+    uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */
+    bool enableTimeout;    /*!< Enable internal timeout function. */
+} i2c_master_config_t;
+
+/* Forward declaration of the transfer descriptor and handle typedefs. */
+/*! @brief I2C master transfer typedef */
+typedef struct _i2c_master_transfer i2c_master_transfer_t;
+
+/*! @brief I2C master handle typedef */
+typedef struct _i2c_master_handle i2c_master_handle_t;
+
+/*!
+ * @brief Master completion callback function pointer type.
+ *
+ * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use
+ * in the call to I2C_MasterTransferCreateHandle().
+ *
+ * @param base The I2C peripheral base address.
+ * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed.
+ * @param userData Arbitrary pointer-sized value passed from the application.
+ */
+typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
+                                               i2c_master_handle_t *handle,
+                                               status_t completionStatus,
+                                               void *userData);
+
+/*!
+ * @brief Transfer option flags.
+ *
+ * @note These enumerations are intended to be OR'd together to form a bit mask of options for
+ * the #_i2c_master_transfer::flags field.
+ */
+enum _i2c_master_transfer_flags
+{
+    kI2C_TransferDefaultFlag = 0x00U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
+    kI2C_TransferNoStartFlag = 0x01U,       /*!< Don't send a start condition, address, and sub address */
+    kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
+    kI2C_TransferNoStopFlag = 0x04U,        /*!< Don't send a stop condition. */
+};
+
+/*! @brief States for the state machine used by transactional APIs. */
+enum _i2c_transfer_states
+{
+    kIdleState = 0,
+    kTransmitSubaddrState,
+    kTransmitDataState,
+    kReceiveDataState,
+    kReceiveLastDataState,
+    kStartState,
+    kStopState,
+    kWaitForCompletionState
+};
+
+/*!
+ * @brief Non-blocking transfer descriptor structure.
+ *
+ * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API.
+ */
+struct _i2c_master_transfer
+{
+    uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available
+                       options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */
+    uint16_t slaveAddress;     /*!< The 7-bit slave address. */
+    i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */
+    uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
+    size_t subaddressSize;     /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
+    void *data;                /*!< Pointer to data to transfer. */
+    size_t dataSize;           /*!< Number of bytes to transfer. */
+};
+
+/*!
+ * @brief Driver handle for master non-blocking APIs.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i2c_master_handle
+{
+    uint8_t state;           /*!< Transfer state machine current state. */
+    uint32_t transferCount;  /*!< Indicates progress of the transfer */
+    uint32_t remainingBytes; /*!< Remaining byte count in current state. */
+    uint8_t *buf;            /*!< Buffer pointer for current state. */
+    uint32_t remainingSubaddr;
+    uint8_t subaddrBuf[4];
+    i2c_master_transfer_t transfer;                    /*!< Copy of the current transfer info. */
+    i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */
+    void *userData;                                    /*!< Application data passed to callback. */
+};
+
+/*! @} */
+
+/*!
+ * @addtogroup i2c_slave_driver
+ * @{
+ */
+
+ /*!
+ * @brief I2C slave peripheral flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _i2c_slave_flags
+{
+    kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
+    kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */
+    kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */
+    kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */
+};
+ 
+/*! @brief I2C slave address register. */
+typedef enum _i2c_slave_address_register
+{
+    kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */
+    kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */
+    kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */
+    kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */
+} i2c_slave_address_register_t;
+
+/*! @brief Data structure with 7-bit Slave address and Slave address disable. */
+typedef struct _i2c_slave_address
+{
+    uint8_t address;     /*!< 7-bit Slave address SLVADR. */
+    bool addressDisable; /*!< Slave address disable SADISABLE. */
+} i2c_slave_address_t;
+
+/*! @brief I2C slave address match options. */
+typedef enum _i2c_slave_address_qual_mode
+{
+    kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */
+    kI2C_QualModeExtend =
+        1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */
+} i2c_slave_address_qual_mode_t;
+
+/*! @brief I2C slave bus speed options. */
+typedef enum _i2c_slave_bus_speed
+{
+    kI2C_SlaveStandardMode = 0U,
+    kI2C_SlaveFastMode = 1U,
+    kI2C_SlaveFastModePlus = 2U,
+    kI2C_SlaveHsMode = 3U,
+} i2c_slave_bus_speed_t;
+
+/*!
+ * @brief Structure with settings to initialize the I2C slave module.
+ *
+ * This structure holds configuration settings for the I2C slave peripheral. To initialize this
+ * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and
+ * pass a pointer to your configuration structure instance.
+ *
+ * The configuration structure can be made constant so it resides in flash.
+ */
+typedef struct _i2c_slave_config
+{
+    i2c_slave_address_t address0;           /*!< Slave's 7-bit address and disable. */
+    i2c_slave_address_t address1;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_t address2;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_t address3;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */
+    uint8_t qualAddress;                    /*!< Slave address qualifier for address 0. */
+    i2c_slave_bus_speed_t
+        busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must
+                       provide sufficient data setup time to the master before releasing the stretched clock.
+                       This is accomplished by inserting one clock time of CLKDIV at that point.
+                       The #busSpeed value is used to configure CLKDIV
+                       such that one clock time is greater than the tSU;DAT value noted
+                       in the I2C bus specification for the I2C mode that is being used.
+                       If the #busSpeed mode is unknown at compile time, use the longest data setup time
+                       kI2C_SlaveStandardMode (250 ns) */
+    bool enableSlave; /*!< Enable slave mode. */
+} i2c_slave_config_t;
+
+/*!
+ * @brief Set of events sent to the callback for non blocking slave transfers.
+ *
+ * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
+ * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
+ * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
+ * parameter.
+ *
+ * @note These enumerations are meant to be OR'd together to form a bit mask of events.
+ */
+typedef enum _i2c_slave_transfer_event
+{
+    kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
+    kI2C_SlaveTransmitEvent = 0x02U,     /*!< Callback is requested to provide data to transmit
+                                                (slave-transmitter role). */
+    kI2C_SlaveReceiveEvent = 0x04U,      /*!< Callback is requested to provide a buffer in which to place received
+                                                 data (slave-receiver role). */
+    kI2C_SlaveCompletionEvent = 0x20U,   /*!< All data in the active transfer have been consumed. */
+    kI2C_SlaveDeselectedEvent =
+        0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */
+
+    /*! Bit mask of all available events. */
+    kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
+                          kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent,
+} i2c_slave_transfer_event_t;
+
+/*! @brief I2C slave handle typedef. */
+typedef struct _i2c_slave_handle i2c_slave_handle_t;
+
+/*! @brief I2C slave transfer structure */
+typedef struct _i2c_slave_transfer
+{
+    i2c_slave_handle_t *handle;       /*!< Pointer to handle that contains this transfer. */
+    i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
+    uint8_t receivedAddress;          /*!< Matching address send by master. 7-bits plus R/nW bit0 */
+    uint32_t eventMask;               /*!< Mask of enabled events. */
+    uint8_t *rxData;                  /*!< Transfer buffer for receive data */
+    const uint8_t *txData;            /*!< Transfer buffer for transmit data */
+    size_t txSize;                    /*!< Transfer size */
+    size_t rxSize;                    /*!< Transfer size */
+    size_t transferredCount;          /*!< Number of bytes transferred during this transfer. */
+    status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
+                                         #kI2C_SlaveCompletionEvent. */
+} i2c_slave_transfer_t;
+
+/*!
+ * @brief Slave event callback function pointer type.
+ *
+ * This callback is used only for the slave non-blocking transfer API. To install a callback,
+ * use the I2C_SlaveSetCallback() function after you have created a handle.
+ *
+ * @param base Base address for the I2C instance on which the event occurred.
+ * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
+ * @param userData Arbitrary pointer-sized value passed from the application.
+ */
+typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData);
+
+/*!
+ * @brief I2C slave software finite state machine states.
+ */
+typedef enum _i2c_slave_fsm
+{
+    kI2C_SlaveFsmAddressMatch = 0u,
+    kI2C_SlaveFsmReceive = 2u,
+    kI2C_SlaveFsmTransmit = 3u,
+} i2c_slave_fsm_t;
+
+/*!
+ * @brief I2C slave handle structure.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i2c_slave_handle
+{
+    volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */
+    volatile bool isBusy;                   /*!< Whether transfer is busy. */
+    volatile i2c_slave_fsm_t slaveFsm;      /*!< slave transfer state machine. */
+    i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
+    void *userData;                         /*!< Callback parameter passed to callback. */
+};
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup i2c_master_driver
+ * @{
+ */
+
+/*! @name Initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Provides a default configuration for the I2C master peripheral.
+ *
+ * This function provides the following default configuration for the I2C master peripheral:
+ * @code
+ *  masterConfig->enableMaster            = true;
+ *  masterConfig->baudRate_Bps            = 100000U;
+ *  masterConfig->enableTimeout           = false;
+ * @endcode
+ *
+ * After calling this function, you can override any settings in order to customize the configuration,
+ * prior to initializing the master driver with I2C_MasterInit().
+ *
+ * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t.
+ */
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief Initializes the I2C master peripheral.
+ *
+ * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user
+ * provided configuration. A software reset is performed prior to configuration.
+ *
+ * @param base The I2C peripheral base address.
+ * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of
+ * defaults
+ *      that you can override.
+ * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors,
+ *      filter widths, and timeout periods.
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+* @brief Deinitializes the I2C master peripheral.
+*
+ * This function disables the I2C master peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+void I2C_MasterDeinit(I2C_Type *base);
+
+/*!
+ * @brief Performs a software reset.
+ *
+ * Restores the I2C master peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+static inline void I2C_MasterReset(I2C_Type *base)
+{
+}
+
+/*!
+ * @brief Enables or disables the I2C module as master.
+ *
+ * @param base The I2C peripheral base address.
+ * @param enable Pass true to enable or false to disable the specified I2C as master.
+ */
+static inline void I2C_MasterEnable(I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK;
+    }
+    else
+    {
+        base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK;
+    }
+}
+
+/*@}*/
+
+/*! @name Status */
+/*@{*/
+
+/*!
+ * @brief Gets the I2C status flags.
+ *
+ * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit
+ * in the return value is set if the flag is asserted.
+ *
+ * @param base The I2C peripheral base address.
+ * @return State of the status flags:
+ *         - 1: related status flag is set.
+ *         - 0: related status flag is not set.
+ * @see _i2c_master_flags
+ */
+static inline uint32_t I2C_GetStatusFlags(I2C_Type *base)
+{
+    return base->STAT;
+}
+
+/*!
+ * @brief Clears the I2C master status flag state.
+ *
+ * The following status register flags can be cleared:
+ * - #kI2C_MasterArbitrationLostFlag
+ * - #kI2C_MasterStartStopErrorFlag
+ *
+ * Attempts to clear other flags has no effect.
+ *
+ * @param base The I2C peripheral base address.
+ * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
+ *  #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  I2C_GetStatusFlags().
+ * @see _i2c_master_flags.
+ */
+static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    /* Allow clearing just master status flags */
+    base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+}
+
+/*@}*/
+
+/*! @name Interrupts */
+/*@{*/
+
+/*!
+ * @brief Enables the I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask)
+{
+    base->INTENSET = interruptMask;
+}
+
+/*!
+ * @brief Disables the I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask)
+{
+    base->INTENCLR = interruptMask;
+}
+
+/*!
+ * @brief Returns the set of currently enabled I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the
+ *      set of enabled interrupts.
+ */
+static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base)
+{
+    return base->INTSTAT;
+}
+
+/*@}*/
+
+/*! @name Bus operations */
+/*@{*/
+
+/*!
+ * @brief Sets the I2C bus frequency for master transactions.
+ *
+ * The I2C master is automatically disabled and re-enabled as necessary to configure the baud
+ * rate. Do not call this function during a transfer, or the transfer is aborted.
+ *
+ * @param base The I2C peripheral base address.
+ * @param srcClock_Hz I2C functional clock frequency in Hertz.
+ * @param baudRate_Bps Requested bus frequency in bits per second.
+ */
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Returns whether the bus is idle.
+ *
+ * Requires the master mode to be enabled.
+ *
+ * @param base The I2C peripheral base address.
+ * @retval true Bus is busy.
+ * @retval false Bus is idle.
+ */
+static inline bool I2C_MasterGetBusIdleState(I2C_Type *base)
+{
+    /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */
+    return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK);
+}
+
+/*!
+ * @brief Sends a START on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal.
+ * The slave address is sent following the I2C START signal.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy.
+ */
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
+
+/*!
+ * @brief Sends a STOP signal on the I2C bus.
+ *
+ * @retval kStatus_Success Successfully send the stop signal.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterStop(I2C_Type *base);
+
+/*!
+ * @brief Sends a REPEATED START on the I2C bus.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
+ */
+static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    return I2C_MasterStart(base, address, direction);
+}
+
+/*!
+ * @brief Performs a polling send transfer on the I2C bus.
+ *
+ * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may
+ * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
+ * function returns #kStatus_I2C_Nak.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @retval kStatus_Success Data was sent successfully.
+ * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
+ * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
+ * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags);
+
+/*!
+ * @brief Performs a polling receive transfer on the I2C bus.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param rxBuff The pointer to the data to be transferred.
+ * @param rxSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @retval kStatus_Success Data was received successfully.
+ * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
+ * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
+ * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags);
+
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due
+ * to arbitration lost or receiving a NAK.
+ *
+ * @param base I2C peripheral base address.
+ * @param xfer Pointer to the transfer structure.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
+
+/*@}*/
+
+/*! @name Non-blocking */
+/*@{*/
+
+/*!
+ * @brief Creates a new handle for the I2C master non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I2C_MasterTransferAbort() API shall be called.
+ *
+ * @param base The I2C peripheral base address.
+ * @param[out] handle Pointer to the I2C master driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Performs a non-blocking transaction on the I2C bus.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @param xfer The pointer to the transfer descriptor.
+ * @retval kStatus_Success The transaction was started successfully.
+ * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking
+ *      transaction is already in progress.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Returns number of bytes transferred so far.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @param[out] count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_Success
+ * @retval #kStatus_I2C_Busy
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Terminates a non-blocking I2C master transmission early.
+ *
+ * @note It is not safe to call this function from an IRQ handler that has a higher priority than the
+ *      I2C peripheral's IRQ priority.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @retval kStatus_Success A transaction was successfully aborted.
+ * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress.
+ */
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*@}*/
+
+/*! @name IRQ handler */
+/*@{*/
+
+/*!
+ * @brief Reusable routine to handle master interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  nonblocking API's interrupt handler routines to add special functionality.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ */
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*@}*/
+
+/*! @} */ /* end of i2c_master_driver */
+
+/*!
+ * @addtogroup i2c_slave_driver
+ * @{
+ */
+
+/*! @name Slave initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Provides a default configuration for the I2C slave peripheral.
+ *
+ * This function provides the following default configuration for the I2C slave peripheral:
+ * @code
+ *  slaveConfig->enableSlave = true;
+ *  slaveConfig->address0.disable = false;
+ *  slaveConfig->address0.address = 0u;
+ *  slaveConfig->address1.disable = true;
+ *  slaveConfig->address2.disable = true;
+ *  slaveConfig->address3.disable = true;
+ *  slaveConfig->busSpeed = kI2C_SlaveStandardMode;
+ * @endcode
+ *
+ * After calling this function, override any settings  to customize the configuration,
+ * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a
+ * address0.address member of the configuration structure with the desired slave address.
+ *
+ * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to
+ *      #i2c_slave_config_t.
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Initializes the I2C slave peripheral.
+ *
+ * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user
+ * provided configuration.
+ *
+ * @param base The I2C peripheral base address.
+ * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults
+ *      that you can override.
+ * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide
+ * enough
+ *                       data setup time for master when slave stretches the clock.
+ */
+status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Configures Slave Address n register.
+ *
+ * This function writes new value to Slave Address register.
+ *
+ * @param base The I2C peripheral base address.
+ * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed.
+ * @param address The slave address to be stored to the address register for matching.
+ * @param addressDisable Disable matching of the specified address register.
+  */
+void I2C_SlaveSetAddress(I2C_Type *base,
+                         i2c_slave_address_register_t addressRegister,
+                         uint8_t address,
+                         bool addressDisable);
+
+/*!
+* @brief Deinitializes the I2C slave peripheral.
+*
+ * This function disables the I2C slave peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+void I2C_SlaveDeinit(I2C_Type *base);
+
+/*!
+ * @brief Enables or disables the I2C module as slave.
+ *
+ * @param base The I2C peripheral base address.
+ * @param enable True to enable or flase to disable.
+ */
+static inline void I2C_SlaveEnable(I2C_Type *base, bool enable)
+{
+    /* Set or clear the SLVEN bit in the CFG register. */
+    base->CFG = I2C_CFG_SLVEN(enable);
+}
+
+/*@}*/ /* end of Slave initialization and deinitialization */
+
+/*! @name Slave status */
+/*@{*/
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * The following status register flags can be cleared:
+ * - slave deselected flag
+ *
+ * Attempts to clear other flags has no effect.
+ *
+ * @param base The I2C peripheral base address.
+ * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
+ *  #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  I2C_SlaveGetStatusFlags().
+ * @see _i2c_slave_flags.
+ */
+static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    /* Allow clearing just slave status flags */
+    base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK;
+}
+
+/*@}*/ /* end of Slave status */
+
+/*! @name Slave bus operations */
+/*@{*/
+
+/*!
+ * @brief Performs a polling send transfer on the I2C bus.
+ *
+ * The function executes blocking address phase and blocking data phase.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @return kStatus_Success Data has been sent.
+ * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected).
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+
+/*!
+ * @brief Performs a polling receive transfer on the I2C bus.
+ *
+ * The function executes blocking address phase and blocking data phase.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param rxBuff The pointer to the data to be transferred.
+ * @param rxSize The length in bytes of the data to be transferred.
+ * @return kStatus_Success Data has been received.
+ * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected).
+ */
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+
+/*@}*/ /* end of Slave bus operations */
+
+/*! @name Slave non-blocking */
+/*@{*/
+
+/*!
+ * @brief Creates a new handle for the I2C slave non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called.
+ *
+ * @param base The I2C peripheral base address.
+ * @param[out] handle Pointer to the I2C slave driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback.
+ * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask);
+
+/*!
+ * @brief Starts accepting master read from slave requests.
+ *
+ * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer
+ * from within the transfer callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer Pointer to #i2c_slave_transfer_t structure.
+ * @param txData Pointer to data to send to master.
+ * @param txSize Size of txData in bytes.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveSetSendBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask);
+
+/*!
+ * @brief Starts accepting master write to slave requests.
+  *
+ * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer
+ * from within the transfer callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer Pointer to #i2c_slave_transfer_t structure.
+ * @param rxData Pointer to data to store data from master.
+ * @param rxSize Size of rxData in bytes.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveSetReceiveBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask);
+
+/*!
+ * @brief Returns the slave address sent by the I2C master.
+ *
+ * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer The I2C slave transfer.
+ * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and
+ *      the 7-bit slave address is in the upper 7 bits.
+ */
+static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer)
+{
+    return transfer->receivedAddress;
+}
+
+/*!
+ * @brief Aborts the slave non-blocking transfers.
+ * @note This API could be called at any time to stop slave for handling the bus events.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ * @retval kStatus_Success
+ * @retval #kStatus_I2C_Idle
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*!
+ * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
+
+/*@}*/ /* end of Slave non-blocking */
+
+/*! @name Slave IRQ handler */
+/*@{*/
+
+/*!
+ * @brief Reusable routine to handle slave interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  non blocking API's interrupt handler routines to add special functionality.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*@}*/ /* end of Slave IRQ handler */
+
+/*! @} */ /* end of i2c_slave_driver */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2C_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2c_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,539 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c_dma.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
+typedef struct _i2c_master_dma_private_handle
+{
+    I2C_Type *base;
+    i2c_master_dma_handle_t *handle;
+} i2c_master_dma_private_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA callback for I2C master DMA driver.
+ *
+ * @param handle DMA handler for I2C master DMA driver
+ * @param userData user param passed to the callback function
+ */
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
+
+/*!
+ * @brief Set up master transfer, send slave address and sub address(if any), wait until the
+ * wait until address sent status return.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ */
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get the I2C instance from peripheral base address.
+ *
+ * @param base I2C peripheral base address.
+ * @return I2C instance.
+ */
+extern uint32_t I2C_GetInstance(I2C_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+/*!
+ * @brief Prepares the transfer state machine and fills in the command buffer.
+ * @param handle Master nonblocking driver handle.
+ */
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer)
+{
+    struct _i2c_master_transfer *transfer;
+
+    handle->transfer = *xfer;
+    transfer = &(handle->transfer);
+
+    handle->transferCount = 0;
+    handle->remainingBytesDMA = 0;
+    handle->buf = (uint8_t *)transfer->data;
+    handle->remainingSubaddr = 0;
+
+    if (transfer->flags & kI2C_TransferNoStartFlag)
+    {
+        /* Start condition shall be ommited, switch directly to next phase */
+        if (transfer->dataSize == 0)
+        {
+            handle->state = kStopState;
+        }
+        else if (handle->transfer.direction == kI2C_Write)
+        {
+            handle->state = xfer->dataSize = kTransmitDataState;
+        }
+        else if (handle->transfer.direction == kI2C_Read)
+        {
+            handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState;
+        }
+        else
+        {
+            return kStatus_I2C_InvalidParameter;
+        }
+    }
+    else
+    {
+        if (transfer->subaddressSize != 0)
+        {
+            int i;
+            uint32_t subaddress;
+
+            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
+            {
+                return kStatus_I2C_InvalidParameter;
+            }
+
+            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+            subaddress = xfer->subaddress;
+            for (i = xfer->subaddressSize - 1; i >= 0; i--)
+            {
+                handle->subaddrBuf[i] = subaddress & 0xff;
+                subaddress >>= 8;
+            }
+            handle->remainingSubaddr = transfer->subaddressSize;
+        }
+
+        handle->state = kStartState;
+    }
+
+    return kStatus_Success;
+}
+
+static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    int transfer_size;
+    dma_transfer_config_t xferConfig;
+
+    /* Update transfer count */
+    handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data;
+
+    /* Check if there is anything to be transferred at all */
+    if (handle->remainingBytesDMA == 0)
+    {
+        /* No data to be transferrred, disable DMA */
+        base->MSTCTL = 0;
+        return;
+    }
+
+    /* Calculate transfer size */
+    transfer_size = handle->remainingBytesDMA;
+    if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
+    {
+        transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
+    }
+
+    switch (handle->transfer.direction)
+    {
+        case kI2C_Write:
+            DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size,
+                                kDMA_MemoryToPeripheral, NULL);
+            break;
+
+        case kI2C_Read:
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size,
+                                kDMA_PeripheralToMemory, NULL);
+            break;
+
+        default:
+            /* This should never happen */
+            assert(0);
+            break;
+    }
+
+    DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+    DMA_StartTransfer(handle->dmaHandle);
+
+    handle->remainingBytesDMA -= transfer_size;
+    handle->buf += transfer_size;
+}
+
+/*!
+ * @brief Execute states until the transfer is done.
+ * @param handle Master nonblocking driver handle.
+ * @param[out] isDone Set to true if the transfer has completed.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_ArbitrationLost
+ * @retval #kStatus_I2C_Nak
+ */
+static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
+{
+    uint32_t status;
+    uint32_t master_state;
+    struct _i2c_master_transfer *transfer;
+    dma_transfer_config_t xferConfig;
+    status_t err;
+    uint32_t start_flag = 0;
+
+    transfer = &(handle->transfer);
+
+    *isDone = false;
+
+    status = I2C_GetStatusFlags(base);
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_StartStopError;
+    }
+
+    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Get the state of the I2C module */
+    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
+    {
+        /* Slave NACKed last byte, issue stop and return error */
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+        handle->state = kWaitForCompletionState;
+        return kStatus_I2C_Nak;
+    }
+
+    err = kStatus_Success;
+
+    if (handle->state == kStartState)
+    {
+        /* set start flag for later use */
+        start_flag = I2C_MSTCTL_MSTSTART_MASK;
+
+        if (handle->remainingSubaddr)
+        {
+            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+            handle->state = kTransmitSubaddrState;
+        }
+        else if (transfer->direction == kI2C_Write)
+        {
+            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+            if (transfer->dataSize == 0)
+            {
+                /* No data to be transferred, initiate start and schedule stop */
+                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+                handle->state = kStopState;
+                return err;
+            }
+            handle->state = kTransmitDataState;
+        }
+        else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0))
+        {
+            base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
+            if (transfer->dataSize == 1)
+            {
+                /* The very last byte is always received by means of SW */
+                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+                handle->state = kReceiveLastDataState;
+                return err;
+            }
+            handle->state = kReceiveDataState;
+        }
+        else
+        {
+            handle->state = kIdleState;
+            err = kStatus_I2C_UnexpectedState;
+            return err;
+        }
+    }
+
+    switch (handle->state)
+    {
+        case kTransmitSubaddrState:
+            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+
+            /* Prepare and submit DMA transfer. */
+            DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
+                                handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
+            DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+
+            handle->remainingSubaddr = 0;
+            if (transfer->dataSize)
+            {
+                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
+                 * repeated start */
+                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
+            }
+            else
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            break;
+
+        case kTransmitDataState:
+            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+            handle->remainingBytesDMA = handle->transfer.dataSize;
+
+            I2C_RunDMATransfer(base, handle);
+
+            /* Schedule stop condition */
+            handle->state = kStopState;
+            break;
+
+        case kReceiveDataState:
+            if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+            handle->remainingBytesDMA = handle->transfer.dataSize - 1;
+
+            I2C_RunDMATransfer(base, handle);
+
+            /* Schedule reception of last data byte */
+            handle->state = kReceiveLastDataState;
+            break;
+
+        case kReceiveLastDataState:
+            if (master_state != I2C_STAT_MSTCODE_RXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT;
+            handle->transferCount++;
+
+            /* No more data expected, issue NACK and STOP right away */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kStopState:
+            if (transfer->flags & kI2C_TransferNoStopFlag)
+            {
+                /* Stop condition is omitted, we are done */
+                *isDone = true;
+                handle->state = kIdleState;
+                break;
+            }
+            /* Send stop condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kWaitForCompletionState:
+            *isDone = true;
+            handle->state = kIdleState;
+            break;
+
+        case kStartState:
+        case kIdleState:
+        default:
+            /* State machine shall not be invoked again once it enters the idle state */
+            err = kStatus_I2C_UnexpectedState;
+            break;
+    }
+
+    return err;
+}
+
+void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    bool isDone;
+    status_t result;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
+
+    if (isDone || (result != kStatus_Success))
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base,
+                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+
+        /* Invoke callback. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
+{
+    i2c_master_dma_private_handle_t *dmaPrivateHandle;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
+    I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle);
+}
+
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle)
+{
+    uint32_t instance;
+
+    assert(handle);
+    assert(dmaHandle);
+
+    /* Zero handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Set the user callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferDMAHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base,
+                          I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+    EnableIRQ(kFlexcommIrqs[instance]);
+
+    /* Set the handle for DMA. */
+    handle->dmaHandle = dmaHandle;
+
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    DMA_SetCallback(dmaHandle, (dma_callback)(uintptr_t)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
+}
+
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result;
+
+    assert(handle);
+    assert(xfer);
+    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->state != kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Prepare transfer state machine. */
+    result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
+
+    /* Clear error flags. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    /* Enable I2C internal IRQ sources */
+    I2C_EnableInterrupts(base,
+                         I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
+
+    return result;
+}
+
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == kIdleState)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* There is no necessity to disable interrupts as we read a single integer value */
+    *count = handle->transferCount;
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    /* Disable DMA */
+    base->MSTCTL = 0;
+
+    /* Reset the state to idle. */
+    handle->state = kIdleState;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2c_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_DMA_H_
+#define _FSL_I2C_DMA_H_
+
+#include "fsl_i2c.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup i2c_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
+#define I2C_MAX_DMA_TRANSFER_COUNT 1024
+
+/*! @brief I2C master dma handle typedef. */
+typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
+
+/*! @brief I2C master dma transfer callback typedef. */
+typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
+                                                   i2c_master_dma_handle_t *handle,
+                                                   status_t status,
+                                                   void *userData);
+
+/*! @brief I2C master dma transfer structure. */
+struct _i2c_master_dma_handle
+{
+    uint8_t state;              /*!< Transfer state machine current state. */
+    uint32_t transferCount;     /*!< Indicates progress of the transfer */
+    uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */
+    uint8_t *buf;               /*!< Buffer pointer for current state. */
+    uint32_t remainingSubaddr;
+    uint8_t subaddrBuf[4];
+    dma_handle_t *dmaHandle;                               /*!< The DMA handler used. */
+    i2c_master_transfer_t transfer;                        /*!< Copy of the current transfer info. */
+    i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
+    void *userData;                                        /*!< Callback parameter passed to callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name I2C Block DMA Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Init the I2C handle which is used in transcational functions
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param callback pointer to user callback function
+ * @param userData user param passed to the callback function
+ * @param dmaHandle DMA handle pointer
+ */
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Performs a master dma non-blocking transfer on the I2C bus
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param xfer pointer to transfer structure of i2c_master_transfer_t
+ * @retval kStatus_Success Sucessully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
+ */
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get master transfer status during a dma non-blocking transfer
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a master dma non-blocking transfer in a early time
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ */
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+#endif /*_FSL_I2C_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2s.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,824 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2s.h"
+#include "fsl_flexcomm.h"
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* TODO - absent in device header files, should be there */
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+
+/*! @brief I2S states. */
+enum _i2s_state
+{
+    kI2S_StateIdle = 0x0,             /*!< Not performing transfer */
+    kI2S_StateTx,                     /*!< Performing transmit */
+    kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */
+    kI2S_StateTxWaitForEmptyFifo,     /*!< Wait for FIFO to be flushed */
+    kI2S_StateRx,                     /*!< Performing receive */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static void I2S_Config(I2S_Type *base, const i2s_config_t *config);
+static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void I2S_TxInit(I2S_Type *base, const i2s_config_t *config)
+{
+    uint32_t cfg = 0U;
+    uint32_t trig = 0U;
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX);
+    I2S_Config(base, config);
+
+    /* Configure FIFO */
+
+    cfg |= I2S_FIFOCFG_ENABLETX(1U);                 /* enable TX FIFO */
+    cfg |= I2S_FIFOCFG_EMPTYTX(1U);                  /* empty TX FIFO */
+    cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */
+    cfg |= I2S_FIFOCFG_PACK48(config->pack48);       /* set pack 48-bit format or not */
+    trig |= I2S_FIFOTRIG_TXLVLENA(1U);               /* enable TX FIFO trigger */
+    trig |= I2S_FIFOTRIG_TXLVL(config->watermark);   /* set TX FIFO trigger level */
+
+    base->FIFOCFG = cfg;
+    base->FIFOTRIG = trig;
+}
+
+void I2S_RxInit(I2S_Type *base, const i2s_config_t *config)
+{
+    uint32_t cfg = 0U;
+    uint32_t trig = 0U;
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX);
+    I2S_Config(base, config);
+
+    /* Configure FIFO */
+
+    cfg |= I2S_FIFOCFG_ENABLERX(1U);               /* enable RX FIFO */
+    cfg |= I2S_FIFOCFG_EMPTYRX(1U);                /* empty RX FIFO */
+    cfg |= I2S_FIFOCFG_PACK48(config->pack48);     /* set pack 48-bit format or not */
+    trig |= I2S_FIFOTRIG_RXLVLENA(1U);             /* enable RX FIFO trigger */
+    trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */
+
+    base->FIFOCFG = cfg;
+    base->FIFOTRIG = trig;
+}
+
+void I2S_TxGetDefaultConfig(i2s_config_t *config)
+{
+    config->masterSlave = kI2S_MasterSlaveNormalMaster;
+    config->mode = kI2S_ModeI2sClassic;
+    config->rightLow = false;
+    config->leftJust = false;
+    config->pdmData = false;
+    config->sckPol = false;
+    config->wsPol = false;
+    config->divider = 1U;
+    config->oneChannel = false;
+    config->dataLength = 16U;
+    config->frameLength = 32U;
+    config->position = 0U;
+    config->watermark = 4U;
+    config->txEmptyZero = true;
+    config->pack48 = false;
+}
+
+void I2S_RxGetDefaultConfig(i2s_config_t *config)
+{
+    config->masterSlave = kI2S_MasterSlaveNormalSlave;
+    config->mode = kI2S_ModeI2sClassic;
+    config->rightLow = false;
+    config->leftJust = false;
+    config->pdmData = false;
+    config->sckPol = false;
+    config->wsPol = false;
+    config->divider = 1U;
+    config->oneChannel = false;
+    config->dataLength = 16U;
+    config->frameLength = 32U;
+    config->position = 0U;
+    config->watermark = 4U;
+    config->txEmptyZero = false;
+    config->pack48 = false;
+}
+
+static void I2S_Config(I2S_Type *base, const i2s_config_t *config)
+{
+    assert(config);
+
+    uint32_t cfg1 = 0U;
+    uint32_t cfg2 = 0U;
+
+    /* set master/slave configuration */
+    cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave);
+
+    /* set I2S mode */
+    cfg1 |= I2S_CFG1_MODE(config->mode);
+
+    /* set right low (channel swap) */
+    cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow);
+
+    /* set data justification */
+    cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust);
+
+    /* set source to PDM dmic */
+    cfg1 |= I2S_CFG1_PDMDATA(config->pdmData);
+
+    /* set SCLK polarity */
+    cfg1 |= I2S_CFG1_SCK_POL(config->sckPol);
+
+    /* set WS polarity */
+    cfg1 |= I2S_CFG1_WS_POL(config->wsPol);
+
+    /* set mono mode */
+    cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel);
+
+    /* set data length */
+    cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U);
+
+    /* set frame length */
+    cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U);
+
+    /* set data position of this channel pair within the frame */
+    cfg2 |= I2S_CFG2_POSITION(config->position);
+
+    /* write to registers */
+    base->CFG1 = cfg1;
+    base->CFG2 = cfg2;
+
+    /* set the clock divider */
+    base->DIV = I2S_DIV_DIV(config->divider - 1U);
+}
+
+void I2S_Deinit(I2S_Type *base)
+{
+    /* TODO gate FLEXCOMM clock via FLEXCOMM driver */
+}
+
+void I2S_TxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+        I2S_Enable(base);
+    }
+    else
+    {
+        I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+        I2S_Disable(base);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+    }
+}
+
+void I2S_RxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+        I2S_Enable(base);
+    }
+    else
+    {
+        I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+        I2S_Disable(base);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+    }
+}
+
+static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer)
+{
+    assert(transfer->data);
+    if (!transfer->data)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(transfer->dataSize > 0U);
+    if (transfer->dataSize <= 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->dataLength == 4U)
+    {
+        /* No alignment and data length requirements */
+    }
+    else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U))
+    {
+        assert((((uint32_t)transfer->data) % 2U) == 0U);
+        if ((((uint32_t)transfer->data) % 2U) != 0U)
+        {
+            /* Data not 2-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        assert((transfer->dataSize % 2U) == 0U);
+        if ((transfer->dataSize % 2U) != 0U)
+        {
+            /* Data not in pairs of left/right channel bytes */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U))
+    {
+        assert((((uint32_t)transfer->data) % 4U) == 0U);
+        if ((((uint32_t)transfer->data) % 4U) != 0U)
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        assert((transfer->dataSize % 4U) == 0U);
+        if ((transfer->dataSize % 4U) != 0U)
+        {
+            /* Data lenght not multiply of 4 */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U))
+    {
+        assert((transfer->dataSize % 6U) == 0U);
+        if ((transfer->dataSize % 6U) != 0U)
+        {
+            /* Data lenght not multiply of 6 */
+            return kStatus_InvalidArgument;
+        }
+
+        assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)));
+        if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else /* if (handle->dataLength >= 25U) */
+    {
+        assert((((uint32_t)transfer->data) % 4U) == 0U);
+        if ((((uint32_t)transfer->data) % 4U) != 0U)
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        if (handle->oneChannel)
+        {
+            assert((transfer->dataSize % 4U) == 0U);
+            if ((transfer->dataSize % 4U) != 0U)
+            {
+                /* Data lenght not multiply of 4 */
+                return kStatus_InvalidArgument;
+            }
+        }
+        else
+        {
+            assert((transfer->dataSize % 8U) == 0U);
+            if ((transfer->dataSize % 8U) != 0U)
+            {
+                /* Data lenght not multiply of 8 */
+                return kStatus_InvalidArgument;
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    /* Clear out the handle */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Save callback and user data */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Remember some items set previously by configuration */
+    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT);
+    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
+    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
+    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
+
+    handle->useFifo48H = false;
+
+    /* Register IRQ handling */
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_TxHandleIRQ, handle);
+}
+
+status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    status_t result;
+
+    result = I2S_ValidateBuffer(handle, &transfer);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet */
+        return kStatus_I2S_Busy;
+    }
+
+    handle->state = kI2S_StateTx;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark);
+    I2S_TxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable I2S operation and interrupts */
+    I2S_TxEnable(base, false);
+
+    /* Reset state */
+    handle->state = kI2S_StateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+}
+
+void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    /* Clear out the handle */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Save callback and user data */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Remember some items set previously by configuration */
+    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT);
+    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
+    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
+    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
+
+    handle->useFifo48H = false;
+
+    /* Register IRQ handling */
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_RxHandleIRQ, handle);
+}
+
+status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    status_t result;
+
+    result = I2S_ValidateBuffer(handle, &transfer);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet */
+        return kStatus_I2S_Busy;
+    }
+
+    handle->state = kI2S_StateRx;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark);
+    I2S_RxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable I2S operation and interrupts */
+    I2S_RxEnable(base, false);
+
+    /* Reset state */
+    handle->state = kI2S_StateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+}
+
+status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(count);
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->state == kI2S_StateIdle)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->transferCount;
+
+    return kStatus_Success;
+}
+
+status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(count);
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->state == kI2S_StateIdle)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->errorCount;
+
+    return kStatus_Success;
+}
+
+void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
+{
+    uint32_t intstat = base->FIFOINTSTAT;
+    uint32_t data;
+
+    if (intstat & I2S_FIFOINTSTAT_TXERR_MASK)
+    {
+        handle->errorCount++;
+
+        /* Clear TX error interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U);
+    }
+
+    if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK)
+    {
+        if (handle->state == kI2S_StateTx)
+        {
+            /* Send data */
+
+            while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) &&
+                   (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
+            {
+                /* Write output data */
+                if (handle->dataLength == 4U)
+                {
+                    data = *(handle->i2sQueue[handle->queueDriver].data);
+                    base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU);
+                    handle->i2sQueue[handle->queueDriver].data++;
+                    handle->transferCount++;
+                    handle->i2sQueue[handle->queueDriver].dataSize--;
+                }
+                else if (handle->dataLength <= 8U)
+                {
+                    data = *((uint16_t *)handle->i2sQueue[handle->queueDriver].data);
+                    base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU);
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                    handle->transferCount += sizeof(uint16_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                }
+                else if (handle->dataLength <= 16U)
+                {
+                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                    handle->transferCount += sizeof(uint32_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                }
+                else if (handle->dataLength <= 24U)
+                {
+                    if (handle->pack48)
+                    {
+                        if (handle->useFifo48H)
+                        {
+                            base->FIFOWR48H = *((uint16_t *)(handle->i2sQueue[handle->queueDriver].data));
+                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                            handle->transferCount += sizeof(uint16_t);
+                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                            handle->useFifo48H = false;
+                        }
+                        else
+                        {
+                            base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                            handle->transferCount += sizeof(uint32_t);
+                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                            handle->useFifo48H = true;
+                        }
+                    }
+                    else
+                    {
+                        data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++));
+                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U;
+                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U;
+                        if (handle->useFifo48H)
+                        {
+                            base->FIFOWR48H = data;
+                            handle->useFifo48H = false;
+                        }
+                        else
+                        {
+                            base->FIFOWR = data;
+                            handle->useFifo48H = true;
+                        }
+                        handle->transferCount += 3U;
+                        handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
+                    }
+                }
+                else /* if (handle->dataLength <= 32U) */
+                {
+                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                    handle->transferCount += sizeof(uint32_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                }
+
+                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                {
+                    /* Actual data buffer sent out, switch to a next one */
+                    handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+                    /* Notify user */
+                    if (handle->completionCallback)
+                    {
+                        handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
+                    }
+
+                    /* Check if the next buffer contains anything to send */
+                    if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                    {
+                        /* Everything has been written to FIFO */
+                        handle->state = kI2S_StateTxWaitToWriteDummyData;
+                        break;
+                    }
+                }
+            }
+        }
+        else if (handle->state == kI2S_StateTxWaitToWriteDummyData)
+        {
+            /* Write dummy data */
+            if ((handle->dataLength > 16U) && (handle->dataLength < 25U))
+            {
+                if (handle->useFifo48H)
+                {
+                    base->FIFOWR48H = 0U;
+                    handle->useFifo48H = false;
+                }
+                else
+                {
+                    base->FIFOWR = 0U;
+                    base->FIFOWR48H = 0U;
+                }
+            }
+            else
+            {
+                base->FIFOWR = 0U;
+            }
+
+            /* Next time invoke this handler when FIFO becomes empty (TX level 0) */
+            base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK;
+            handle->state = kI2S_StateTxWaitForEmptyFifo;
+        }
+        else if (handle->state == kI2S_StateTxWaitForEmptyFifo)
+        {
+            /* FIFO, including additional dummy data, has been emptied now,
+             * all relevant data should have been output from peripheral */
+
+            /* Stop transfer */
+            I2S_Disable(base);
+            I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+            base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+
+            /* Reset state */
+            handle->state = kI2S_StateIdle;
+
+            /* Notify user */
+            if (handle->completionCallback)
+            {
+                handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+
+        /* Clear TX level interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U);
+    }
+}
+
+void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
+{
+    uint32_t intstat = base->FIFOINTSTAT;
+    uint32_t data;
+
+    if (intstat & I2S_FIFOINTSTAT_RXERR_MASK)
+    {
+        handle->errorCount++;
+
+        /* Clear RX error interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U);
+    }
+
+    if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK)
+    {
+        while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
+        {
+            /* Read input data */
+            if (handle->dataLength == 4U)
+            {
+                data = base->FIFORD;
+                *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU);
+                handle->i2sQueue[handle->queueDriver].data++;
+                handle->transferCount++;
+                handle->i2sQueue[handle->queueDriver].dataSize--;
+            }
+            else if (handle->dataLength <= 8U)
+            {
+                data = base->FIFORD;
+                *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU);
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                handle->transferCount += sizeof(uint16_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+            }
+            else if (handle->dataLength <= 16U)
+            {
+                data = base->FIFORD;
+                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                handle->transferCount += sizeof(uint32_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+            }
+            else if (handle->dataLength <= 24U)
+            {
+                if (handle->pack48)
+                {
+                    if (handle->useFifo48H)
+                    {
+                        data = base->FIFORD48H;
+                        handle->useFifo48H = false;
+
+                        *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                        handle->transferCount += sizeof(uint16_t);
+                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                    }
+                    else
+                    {
+                        data = base->FIFORD;
+                        handle->useFifo48H = true;
+
+                        *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                        handle->transferCount += sizeof(uint32_t);
+                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                    }
+                }
+                else
+                {
+                    if (handle->useFifo48H)
+                    {
+                        data = base->FIFORD48H;
+                        handle->useFifo48H = false;
+                    }
+                    else
+                    {
+                        data = base->FIFORD;
+                        handle->useFifo48H = true;
+                    }
+
+                    *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU;
+                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU;
+                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU;
+                    handle->transferCount += 3U;
+                    handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
+                }
+            }
+            else /* if (handle->dataLength <= 32U) */
+            {
+                data = base->FIFORD;
+                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                handle->transferCount += sizeof(uint32_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+            }
+
+            if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+            {
+                /* Actual data buffer filled with input data, switch to a next one */
+                handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+                /* Notify user */
+                if (handle->completionCallback)
+                {
+                    handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
+                }
+
+                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                {
+                    /* No other buffer prepared to receive data into */
+
+                    /* Disable I2S operation and interrupts */
+                    I2S_Disable(base);
+                    I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+                    base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+
+                    /* Reset state */
+                    handle->state = kI2S_StateIdle;
+
+                    /* Notify user */
+                    if (handle->completionCallback)
+                    {
+                        handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
+                    }
+
+                    /* Clear RX level interrupt flag */
+                    base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
+
+                    return;
+                }
+            }
+        }
+
+        /* Clear RX level interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2s.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2S_H_
+#define _FSL_I2S_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup i2s_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2S driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#ifndef I2S_NUM_BUFFERS
+
+/*! @brief Number of buffers . */
+#define I2S_NUM_BUFFERS (4)
+
+#endif
+
+/*! @brief I2S status codes. */
+enum _i2s_status
+{
+    kStatus_I2S_BufferComplete =
+        MAKE_STATUS(kStatusGroup_I2S, 0),                /*!< Transfer from/into a single buffer has completed */
+    kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */
+    kStatus_I2S_Busy =
+        MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */
+};
+
+/*!
+ * @brief I2S flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+typedef enum _i2s_flags
+{
+    kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */
+    kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */
+    kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */
+    kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK  /*!< RX level interrupt */
+} i2s_flags_t;
+
+/*! @brief Master / slave mode. */
+typedef enum _i2s_master_slave
+{
+    kI2S_MasterSlaveNormalSlave = 0x0,  /*!< Normal slave */
+    kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */
+    kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */
+    kI2S_MasterSlaveNormalMaster = 0x3  /*!< Normal master */
+} i2s_master_slave_t;
+
+/*! @brief I2S mode. */
+typedef enum _i2s_mode
+{
+    kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */
+    kI2S_ModeDspWs50 = 0x1,    /*!< DSP mode, WS having 50% duty cycle */
+    kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */
+    kI2S_ModeDspWsLong = 0x3   /*!< DSP mode, WS having one data slot long pulse */
+} i2s_mode_t;
+
+/*! @brief I2S configuration structure. */
+typedef struct _i2s_config
+{
+    i2s_master_slave_t masterSlave; /*!< Master / slave configuration */
+    i2s_mode_t mode;                /*!< I2S mode */
+    bool rightLow;                  /*!< Right channel data in low portion of FIFO */
+    bool leftJust;                  /*!< Left justify data in FIFO */
+    bool pdmData;                   /*!< Data source is the D-Mic subsystem */
+    bool sckPol;                    /*!< SCK polarity */
+    bool wsPol;                     /*!< WS polarity */
+    uint16_t divider;               /*!< Flexcomm function clock divider (1 - 4096) */
+    bool oneChannel;                /*!< true mono, false stereo */
+    uint8_t dataLength;             /*!< Data length (4 - 32) */
+    uint16_t frameLength;           /*!< Frame width (4 - 512) */
+    uint16_t position;              /*!< Data position in the frame */
+    uint8_t watermark;              /*!< FIFO trigger level */
+    bool txEmptyZero;               /*!< Transmit zero when buffer becomes empty or last item */
+    bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                    values) */
+} i2s_config_t;
+
+/*! @brief Buffer to transfer from or receive audio data into. */
+typedef struct _i2s_transfer
+{
+    volatile uint8_t *data;   /*!< Pointer to data buffer. */
+    volatile size_t dataSize; /*!< Buffer size in bytes. */
+} i2s_transfer_t;
+
+/*! @brief Transactional state of the intialized transfer or receive I2S operation. */
+typedef struct _i2s_handle i2s_handle_t;
+
+/*!
+ * @brief Callback function invoked from transactional API
+ *        on completion of a single buffer transfer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to I2S transaction.
+ * @param completionStatus status of the transaction.
+ * @param userData optional pointer to user arguments data.
+ */
+typedef void (*i2s_transfer_callback_t)(I2S_Type *base,
+                                        i2s_handle_t *handle,
+                                        status_t completionStatus,
+                                        void *userData);
+
+/*! @brief Members not to be accessed / modified outside of the driver. */
+struct _i2s_handle
+{
+    uint32_t state;                             /*!< State of transfer */
+    i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */
+    void *userData;                             /*!< Application data passed to callback */
+    bool oneChannel;                            /*!< true mono, false stereo */
+    uint8_t dataLength;                         /*!< Data length (4 - 32) */
+    bool pack48;     /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                        values) */
+    bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
+    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
+    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
+    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+    volatile uint32_t errorCount;                      /*!< Number of buffer underruns/overruns */
+    volatile uint32_t transferCount;                   /*!< Number of bytes transferred */
+    volatile uint8_t watermark;                        /*!< FIFO trigger level */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality.
+ *
+ * Ungates the FLEXCOMM clock and configures the module
+ * for I2S transmission using a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * I2S_TxGetDefaultConfig().
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2S driver.
+ *
+ * @param base I2S base pointer.
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_TxInit(I2S_Type *base, const i2s_config_t *config);
+
+/*!
+ * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality.
+ *
+ * Ungates the FLEXCOMM clock and configures the module
+ * for I2S receive using a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * I2S_RxGetDefaultConfig().
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2S driver.
+ *
+ * @param base I2S base pointer.
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_RxInit(I2S_Type *base, const i2s_config_t *config);
+
+/*!
+ * @brief Sets the I2S Tx configuration structure to default values.
+ *
+ * This API initializes the configuration structure for use in I2S_TxInit().
+ * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified
+ * before calling I2S_TxInit().
+ * Example:
+   @code
+   i2s_config_t config;
+   I2S_TxGetDefaultConfig(&config);
+   @endcode
+ *
+ * Default values:
+ * @code
+ *   config->masterSlave = kI2S_MasterSlaveNormalMaster;
+ *   config->mode = kI2S_ModeI2sClassic;
+ *   config->rightLow = false;
+ *   config->leftJust = false;
+ *   config->pdmData = false;
+ *   config->sckPol = false;
+ *   config->wsPol = false;
+ *   config->divider = 1;
+ *   config->oneChannel = false;
+ *   config->dataLength = 16;
+ *   config->frameLength = 32;
+ *   config->position = 0;
+ *   config->watermark = 4;
+ *   config->txEmptyZero = true;
+ *   config->pack48 = false;
+ * @endcode
+ *
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_TxGetDefaultConfig(i2s_config_t *config);
+
+/*!
+ * @brief Sets the I2S Rx configuration structure to default values.
+ *
+ * This API initializes the configuration structure for use in I2S_RxInit().
+ * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified
+ * before calling I2S_RxInit().
+ * Example:
+   @code
+   i2s_config_t config;
+   I2S_RxGetDefaultConfig(&config);
+   @endcode
+ *
+ * Default values:
+ * @code
+ *   config->masterSlave = kI2S_MasterSlaveNormalSlave;
+ *   config->mode = kI2S_ModeI2sClassic;
+ *   config->rightLow = false;
+ *   config->leftJust = false;
+ *   config->pdmData = false;
+ *   config->sckPol = false;
+ *   config->wsPol = false;
+ *   config->divider = 1;
+ *   config->oneChannel = false;
+ *   config->dataLength = 16;
+ *   config->frameLength = 32;
+ *   config->position = 0;
+ *   config->watermark = 4;
+ *   config->txEmptyZero = false;
+ *   config->pack48 = false;
+ * @endcode
+ *
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_RxGetDefaultConfig(i2s_config_t *config);
+
+/*!
+ * @brief De-initializes the I2S peripheral.
+ *
+ * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit
+ * or I2S_RxInit is called to enable the clock.
+ *
+ * @param base I2S base pointer.
+ */
+void I2S_Deinit(I2S_Type *base);
+
+/*! @} */
+
+/*!
+ * @name Non-blocking API
+ * @{
+ */
+
+/*!
+ * @brief Initializes handle for transfer of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Begins or queue sending of the given data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
+ */
+status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts sending of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Initializes handle for reception of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Begins or queue reception of data into given buffer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full.
+ */
+status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts receiving of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Returns number of bytes transferred so far.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param[out] count number of bytes transferred so far by the non-blocking transaction.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
+ */
+status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Returns number of buffer underruns or overruns.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param[out] count number of transmit errors encountered so far by the non-blocking transaction.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
+ */
+status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
+
+/*! @} */
+
+/*!
+ * @name Enable / disable
+ * @{
+ */
+
+/*!
+ * @brief Enables I2S operation.
+ *
+ * @param base I2S base pointer.
+ */
+static inline void I2S_Enable(I2S_Type *base)
+{
+    base->CFG1 |= I2S_CFG1_MAINENABLE(1U);
+}
+
+/*!
+ * @brief Disables I2S operation.
+ *
+ * @param base I2S base pointer.
+ */
+static inline void I2S_Disable(I2S_Type *base)
+{
+    base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U));
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask)
+{
+    base->FIFOINTENSET = interruptMask;
+}
+
+/*!
+ * @brief Disables I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask)
+{
+    base->FIFOINTENCLR = interruptMask;
+}
+
+/*!
+ * @brief Returns the set of currently enabled I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ *
+ * @return A bitmask composed of #i2s_flags_t enumerators OR'd together
+ *         to indicate the set of enabled interrupts.
+ */
+static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base)
+{
+    return base->FIFOINTENSET;
+}
+
+/*!
+ * @brief Invoked from interrupt handler when transmit FIFO level decreases.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Invoked from interrupt handler when receive FIFO level decreases.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
+
+/*! @} */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2S_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2s_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dma.h"
+#include "fsl_i2s_dma.h"
+#include "fsl_flexcomm.h"
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t))
+#define DMA_DESCRIPTORS (2U)
+#define ENQUEUED_BYTES_BUFFER_SIZE (DMA_DESCRIPTORS + 1U)
+#define I2S_FIFO_DEPTH (8U)
+
+/*<! @brief Structure for statically allocated private data. */
+typedef struct _i2s_dma_private_handle
+{
+    I2S_Type *base;           /*!< I2S base address */
+    i2s_dma_handle_t *handle; /*!< I2S handle */
+    volatile uint16_t
+        enqueuedBytes[ENQUEUED_BYTES_BUFFER_SIZE]; /*!< Number of bytes being transferred by DMA descriptors */
+    volatile uint8_t enqueuedBytesStart;           /*!< First item in enqueuedBytes (for reading) */
+    volatile uint8_t enqueuedBytesEnd;             /*!< Last item in enqueuedBytes (for adding) */
+    volatile bool initialDescriptor;               /*!< Initial DMA descriptor transfer not finished yet */
+    volatile uint8_t
+        dmaDescriptorsUsed; /*!< Number of DMA descriptors with valid data (in queue, excluding initial descriptor) */
+    volatile uint8_t descriptor;      /*!< Index of next descriptor to be configured with data */
+    volatile uint8_t queueDescriptor; /*!< Queue index of buffer to be actually consumed by DMA */
+    volatile i2s_transfer_t descriptorQueue[I2S_NUM_BUFFERS]; /*!< Transfer data as queued to descriptors for DMA */
+} i2s_dma_private_handle_t;
+
+/*! @brief I2S DMA transfer private state. */
+enum _i2s_dma_state
+{
+    kI2S_DmaStateIdle = 0x0U, /*!< I2S is in idle state */
+    kI2S_DmaStateTx,          /*!< I2S is busy transmitting data */
+    kI2S_DmaStateRx,          /*!< I2S is busy receiving data */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+static uint32_t I2S_GetInstance(I2S_Type *base);
+static void I2S_TxEnableDMA(I2S_Type *base, bool enable);
+static void I2S_RxEnableDMA(I2S_Type *base, bool enable);
+static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+static status_t I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle, const uint16_t maxSize);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! @brief DMA transfer descriptors. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 16
+static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#elif defined(__CC_ARM)
+__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#elif defined(__GNUC__)
+__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#endif
+
+/*<! @brief Buffer with dummy TX data. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint32_t s_DummyBufferTx = 0U;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
+#endif
+
+/*<! @brief Buffer to fill with RX data. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint32_t s_DummyBufferRx = 0U;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
+#endif
+
+/*<! @brief Private array of data associated with available I2S peripherals. */
+static i2s_dma_private_handle_t s_DmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT];
+
+/*<! @brief Base addresses of available I2S peripherals. */
+static const uint32_t s_I2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    /* Validate input data and tranfer buffer */
+
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert((((uint32_t)transfer.data) % 4U) == 0U);
+    if ((((uint32_t)transfer.data) % 4U) != 0U)
+    {
+        /* Data not 4-bytes aligned */
+        return kStatus_InvalidArgument;
+    }
+
+    assert(transfer.dataSize != 0U);
+    if (transfer.dataSize == 0U)
+    {
+        /* No data to send or receive */
+        return kStatus_InvalidArgument;
+    }
+
+    assert((transfer.dataSize % 4U) == 0U);
+    if ((transfer.dataSize % 4U) != 0U)
+    {
+        /* Data length not multiply of 4 bytes */
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet, reject request */
+        return kStatus_I2S_Busy;
+    }
+
+    /* Enqueue data */
+    privateHandle->descriptorQueue[handle->queueUser].data = transfer.data;
+    privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    return kStatus_Success;
+}
+
+static uint32_t I2S_GetInstance(I2S_Type *base)
+{
+    uint32_t i;
+
+    for (i = 0U; i < FSL_FEATURE_SOC_I2S_COUNT; i++)
+    {
+        if ((uint32_t)base == s_I2sBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0U;
+}
+
+void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData)
+{
+    assert(handle);
+    assert(dmaHandle);
+
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    memset(handle, 0U, sizeof(*handle));
+    handle->state = kI2S_DmaStateIdle;
+    handle->dmaHandle = dmaHandle;
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    memset(privateHandle, 0U, sizeof(*privateHandle));
+    privateHandle->base = base;
+    privateHandle->handle = handle;
+    privateHandle->initialDescriptor = false;
+
+    DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle);
+}
+
+status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    /* Enqueue transfer buffer */
+    status_t status = I2S_EnqueueUserBuffer(base, handle, transfer);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Initialize DMA transfer */
+    if (handle->state == kI2S_DmaStateIdle)
+    {
+        handle->state = kI2S_DmaStateTx;
+        return I2S_StartTransferDMA(base, handle);
+    }
+
+    return kStatus_Success;
+}
+
+void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    assert(handle);
+    assert(handle->dmaHandle);
+
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    /* Abort operation */
+    DMA_AbortTransfer(handle->dmaHandle);
+    if (handle->state == kI2S_DmaStateTx)
+    {
+        I2S_TxEnableDMA(base, false);
+    }
+    else
+    {
+        I2S_RxEnableDMA(base, false);
+    }
+    I2S_Disable(base);
+
+    /* Reset state */
+    handle->state = kI2S_DmaStateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue));
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+
+    /* Clear internal state */
+    memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue));
+    memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes));
+    privateHandle->enqueuedBytesStart = 0U;
+    privateHandle->enqueuedBytesEnd = 0U;
+    privateHandle->initialDescriptor = false;
+    privateHandle->dmaDescriptorsUsed = 0U;
+    privateHandle->descriptor = 0U;
+    privateHandle->queueDescriptor = 0U;
+}
+
+void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData)
+{
+    I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData);
+}
+
+status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    /* Enqueue transfer buffer */
+    status_t status = I2S_EnqueueUserBuffer(base, handle, transfer);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Initialize DMA transfer */
+    if (handle->state == kI2S_DmaStateIdle)
+    {
+        handle->state = kI2S_DmaStateRx;
+        return I2S_StartTransferDMA(base, handle);
+    }
+
+    return kStatus_Success;
+}
+
+static void I2S_TxEnableDMA(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+    }
+}
+
+static void I2S_RxEnableDMA(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+    }
+}
+
+static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    status_t status;
+    dma_transfer_config_t xferConfig = {0};
+    i2s_dma_private_handle_t *privateHandle;
+    i2s_transfer_t volatile *transfer;
+    uint16_t transferBytes;
+    uint32_t instance;
+    uint32_t i;
+
+    instance = I2S_GetInstance(base);
+    privateHandle = &(s_DmaPrivateHandle[instance]);
+    transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
+
+    /*
+     * Divide first buffer between initial DMA descriptor and chained DMA descriptors.
+     * This allows to enqueue more data before entire buffer is processed
+     * and thus could prevent audio drop-outs due to requeing.
+     * But user is expected to enqueue more data in order for this to work.
+     */
+    transferBytes = (transfer->dataSize / (DMA_DESCRIPTORS + 1U));
+
+    if (transferBytes > DMA_MAX_TRANSFER_BYTES)
+    {
+        transferBytes = DMA_MAX_TRANSFER_BYTES;
+    }
+
+    if ((transferBytes % 4U) != 0U)
+    {
+        transferBytes -= (transferBytes % 4U);
+    }
+
+    assert(transferBytes > 0U);
+    if (transferBytes == 0U)
+    {
+        /*
+         * TODO buffer too small to be divided for multiple descriptors
+         * return invalid argument status for now
+         */
+        return kStatus_InvalidArgument;
+    }
+
+    /* Prepare transfer of data via initial DMA transfer descriptor */
+    DMA_PrepareTransfer(
+        &xferConfig, (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
+        (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, sizeof(uint32_t),
+        transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory,
+        (void *)&(s_DmaDescriptors[(instance * FSL_FEATURE_SOC_I2S_COUNT) + 0U]));
+
+    privateHandle->initialDescriptor = true; /* For IRQ handler to know that it will be fired for first descriptor */
+    privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
+    privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % ENQUEUED_BYTES_BUFFER_SIZE;
+
+    transfer->dataSize -= transferBytes;
+    transfer->data += transferBytes;
+    if (transfer->dataSize == 0U)
+    {
+        transfer->data = NULL;
+        privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
+    }
+
+    /* Prepare chained descriptors to transfer 2nd and 3rd part of initial data */
+    for (i = 0; i < DMA_DESCRIPTORS; i++)
+    {
+        if (i == (DMA_DESCRIPTORS - 1))
+        {
+            /* Last buffer will take the rest of data (because of possible truncating by division) */
+            transferBytes = transfer->dataSize;
+            if (transferBytes > DMA_MAX_TRANSFER_BYTES)
+            {
+                transferBytes = DMA_MAX_TRANSFER_BYTES;
+            }
+        }
+
+        I2S_AddTransferDMA(base, handle, transferBytes);
+    }
+
+    /* Submit and start initial DMA transfer */
+
+    if (handle->state == kI2S_DmaStateTx)
+    {
+        I2S_TxEnableDMA(base, true);
+    }
+    else
+    {
+        I2S_RxEnableDMA(base, true);
+    }
+
+    status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    DMA_StartTransfer(handle->dmaHandle);
+
+    I2S_Enable(base);
+    return kStatus_Success;
+}
+
+static status_t I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle, const uint16_t maxSize)
+{
+    dma_xfercfg_t xfercfg;
+    i2s_transfer_t volatile *transfer;
+    uint16_t transferBytes;
+    uint32_t instance;
+    i2s_dma_private_handle_t *privateHandle;
+    dma_descriptor_t *descriptor;
+    dma_descriptor_t *nextDescriptor;
+
+    instance = I2S_GetInstance(base);
+    privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    if (privateHandle->dmaDescriptorsUsed >= DMA_DESCRIPTORS)
+    {
+        /* No unprocessed DMA transfer descriptor */
+        return kStatus_I2S_Busy;
+    }
+
+    transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
+
+    /* Determine currently configured descriptor and the other which it will link to */
+    descriptor = &(s_DmaDescriptors[(instance * FSL_FEATURE_SOC_I2S_COUNT) + privateHandle->descriptor]);
+    privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS;
+    nextDescriptor = &(s_DmaDescriptors[(instance * FSL_FEATURE_SOC_I2S_COUNT) + privateHandle->descriptor]);
+
+    if (transfer->dataSize == 0U)
+    {
+        /* Currently nothing to enqueue, use dummy buffer instead */
+
+        xfercfg.valid = false;
+        xfercfg.reload = true;
+        xfercfg.swtrig = false;
+        xfercfg.clrtrig = false;
+        xfercfg.intA = true;
+        xfercfg.intB = false;
+        xfercfg.byteWidth = sizeof(uint32_t);
+        xfercfg.srcInc = 0U;
+        xfercfg.dstInc = 0U;
+        xfercfg.transferCount = I2S_FIFO_DEPTH + 1U;
+
+        DMA_CreateDescriptor(descriptor, &xfercfg,
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)&(base->FIFORD),
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)&s_DummyBufferRx,
+                             (void *)nextDescriptor);
+
+        /* TODO use API for this once it is available in DMA driver */
+        descriptor->xfercfg |= DMA_CHANNEL_XFERCFG_CFGVALID(1U);
+        handle->dmaHandle->base->COMMON->SETVALID = (1U << (handle->dmaHandle->channel));
+
+        return kStatus_Success;
+    }
+    else if (transfer->dataSize > maxSize)
+    {
+        /* Take part of data - DMA transfer limitation */
+        transferBytes = maxSize;
+    }
+    else
+    {
+        /* Entire buffer can fit into a single descriptor */
+        transferBytes = transfer->dataSize;
+        privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
+    }
+
+    privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
+    privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % ENQUEUED_BYTES_BUFFER_SIZE;
+
+    /* Configure descriptor */
+
+    xfercfg.valid = false;
+    xfercfg.reload = true;
+    xfercfg.swtrig = false;
+    xfercfg.clrtrig = false;
+    xfercfg.intA = true;
+    xfercfg.intB = false;
+    xfercfg.byteWidth = sizeof(uint32_t);
+    xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U;
+    xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U;
+    xfercfg.transferCount = transferBytes / sizeof(uint32_t);
+
+    DMA_CreateDescriptor(
+        descriptor, &xfercfg, (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
+        (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, (void *)nextDescriptor);
+
+    /* TODO use API for this once it is available in DMA driver */
+    descriptor->xfercfg |= DMA_CHANNEL_XFERCFG_CFGVALID(1U);
+    handle->dmaHandle->base->COMMON->SETVALID = (1U << (handle->dmaHandle->channel));
+
+    /* Advance internal state */
+    privateHandle->dmaDescriptorsUsed++;
+    transfer->dataSize -= transferBytes;
+    transfer->data += transferBytes;
+
+    return kStatus_Success;
+}
+
+void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
+{
+    i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData;
+    i2s_dma_handle_t *i2sHandle = privateHandle->handle;
+    I2S_Type *base = privateHandle->base;
+
+    if (!transferDone)
+    {
+        return;
+    }
+
+    if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+    {
+        /*
+         * All user buffers processed before, dataSize already zero,
+         * this means at least one dummy buffer sent/received
+         * and no new buffer enqueued by user meanwhile.
+         */
+
+        I2S_TransferAbortDMA(base, i2sHandle);
+
+        /* Notify user about completion of the final buffer */
+        if (i2sHandle->completionCallback)
+        {
+            (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData);
+        }
+
+        return;
+    }
+
+    if (privateHandle->initialDescriptor)
+    {
+        /* Initial descriptor finished, decrease amount of data to be processed */
+
+        assert(privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] > 0U);
+
+        i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
+            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+        i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
+            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+        privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
+        privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % ENQUEUED_BYTES_BUFFER_SIZE;
+
+        privateHandle->initialDescriptor = false;
+    }
+    else
+    {
+        if (privateHandle->dmaDescriptorsUsed > 0U)
+        {
+            /* Finished one of chained descriptors, decrease amount of data to be processed */
+
+            assert(privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] > 0U);
+
+            i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
+                privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+            i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
+                privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
+            privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % ENQUEUED_BYTES_BUFFER_SIZE;
+
+            privateHandle->dmaDescriptorsUsed--;
+        }
+    }
+
+    if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+    {
+        /* Entire user buffer sent or received - advance to next one */
+        i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL;
+        i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+        /* Notify user about buffer completion */
+        if (i2sHandle->completionCallback)
+        {
+            (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData);
+        }
+    }
+
+    /* Enqueue new chunk of data to DMA (if any) */
+    I2S_AddTransferDMA(base, i2sHandle, DMA_MAX_TRANSFER_BYTES);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_i2s_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2S_DMA_H_
+#define _FSL_I2S_DMA_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+#include "fsl_dma.h"
+#include "fsl_i2s.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup i2s_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2S DMA driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Members not to be accessed / modified outside of the driver. */
+typedef struct _i2s_dma_handle i2s_dma_handle_t;
+
+/*!
+ * @brief Callback function invoked from DMA API on completion.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to I2S transaction.
+ * @param completionStatus status of the transaction.
+ * @param userData optional pointer to user arguments data.
+ */
+typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base,
+                                            i2s_dma_handle_t *handle,
+                                            status_t completionStatus,
+                                            void *userData);
+
+struct _i2s_dma_handle
+{
+    uint32_t state;                                    /*!< Internal state of I2S DMA transfer */
+    i2s_dma_transfer_callback_t completionCallback;    /*!< Callback function pointer */
+    void *userData;                                    /*!< Application data passed to callback */
+    dma_handle_t *dmaHandle;                           /*!< DMA handle */
+    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
+    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
+    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*! @} */
+
+/*!
+ * @name DMA API
+ * @{
+ */
+
+/*!
+ * @brief Initializes handle for transfer of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param dmaHandle pointer to dma handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Begins or queue sending of the given data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
+ */
+status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts transfer of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+
+/*!
+ * @brief Initializes handle for reception of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param dmaHandle pointer to dma handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Begins or queue reception of data into given buffer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers
+ *         which are not full.
+ */
+status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Invoked from DMA interrupt handler.
+ *
+ * @param handle pointer to DMA handle structure.
+ * @param userData argument for user callback.
+ * @param transferDone if transfer was done.
+ * @param tcds
+ */
+void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);
+
+/*! @} */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2S_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_inputmux.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_inputmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void INPUTMUX_Init(INPUTMUX_Type *base)
+{
+    CLOCK_EnableClock(kCLOCK_InputMux);
+}
+
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
+{
+    uint32_t pmux_id;
+    uint32_t output_id;
+
+    /* extract pmux to be used */
+    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
+    /*  extract function number */
+    output_id = ((uint32_t)(connection)) & 0xffffU;
+    /* programm signal */
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
+}
+
+void INPUTMUX_Deinit(INPUTMUX_Type *base)
+{
+    CLOCK_DisableClock(kCLOCK_InputMux);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_inputmux.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INPUTMUX_H_
+#define _FSL_INPUTMUX_H_
+
+#include "fsl_inputmux_connections.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*! @file */
+/*! @file fsl_inputmux_connections.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Group interrupt driver version for SDK */
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+                                                            /*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base);
+
+/*!
+ * @brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param index Destination peripheral to attach the signal to.
+ * @param connection Selects connection.
+ *
+ * @retval None.
+*/
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
+
+/*!
+ * @brief	Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_inputmux_connections.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INPUTMUX_CONNECTIONS_
+#define _FSL_INPUTMUX_CONNECTIONS_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*! @brief Periphinmux IDs */
+#define PINTSEL_PMUX_ID 0xC0U
+#define DMA_TRIG0_PMUX_ID 0xE0U
+#define DMA_OTRIG_PMUX_ID 0x160U
+#define FREQMEAS_PMUX_ID 0x180U
+#define PMUX_SHIFT 20U
+
+/*! @brief INPUTMUX connections type */
+typedef enum _inputmux_connection_t
+{
+    /*!< Frequency measure. */
+    kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_WdtOscToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_32KhzOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_MainClkToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin4ToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin20ToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin24ToFreqmeas = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin4ToFreqmeas = 8U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    /*!< Pin Interrupt. */
+    kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA ITRIG. */
+    kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_ADC0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA OTRIG. */
+    kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaChannel19_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+} inputmux_connection_t;
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_CONNECTIONS_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_iocon.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_IOCON_H_
+#define _FSL_IOCON_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_iocon
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOCON driver version 2.0.0. */
+#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/**
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
+ */
+typedef struct _iocon_group
+{
+    uint32_t port : 8;      /* Pin port */
+    uint32_t pin : 8;       /* Pin number */
+    uint32_t modefunc : 16; /* Function and mode */
+} iocon_group_t;
+
+/**
+ * @brief IOCON function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+#define IOCON_FUNC0 0x0                   /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1                   /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2                   /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3                   /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4                   /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5                   /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6                   /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7                   /*!< Selects pin function 7 */
+#define IOCON_MODE_INACT (0x0 << 3)       /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN (0x1 << 3)    /*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP (0x2 << 3)      /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER (0x3 << 3)    /*!< Selects pin repeater function */
+#define IOCON_HYS_EN (0x1 << 5)           /*!< Enables hysteresis */
+#define IOCON_GPIO_MODE (0x1 << 5)        /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x1 << 5)         /*!< I2C Slew Rate Control */
+#define IOCON_INV_EN (0x1 << 6)           /*!< Enables invert function on input */
+#define IOCON_ANALOG_EN (0x0 << 7)        /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN (0x1 << 7)       /*!< Enables digital function by setting 1 to bit 7(default) */
+#define IOCON_STDI2C_EN (0x1 << 8)        /*!< I2C standard mode/fast-mode */
+#define IOCON_FASTI2C_EN (0x3 << 8)       /*!< I2C Fast-mode Plus and high-speed slave */
+#define IOCON_INPFILT_OFF (0x1 << 8)      /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << 8)       /*!< Input filter On for GPIO pins */
+#define IOCON_OPENDRAIN_EN (0x1 << 10)    /*!< Enables open-drain function */
+#define IOCON_S_MODE_0CLK (0x0 << 11)     /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK (0x1 << 11)     /*!< Input pulses shorter than 1 filter clock are rejected */
+#define IOCON_S_MODE_2CLK (0x2 << 11)     /*!< Input pulses shorter than 2 filter clock2 are rejected */
+#define IOCON_S_MODE_3CLK (0x3 << 11)     /*!< Input pulses shorter than 3 filter clock2 are rejected */
+#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
+#define IOCON_CLKDIV(div) \
+    ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief   Sets I/O Control pin mux
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   port        : GPIO port to mux
+ * @param   pin         : GPIO pin to mux
+ * @param   modefunc    : OR'ed values of type IOCON_*
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+    base->PIO[port][pin] = modefunc;
+}
+
+/**
+ * @brief   Set all I/O Control pin muxing
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   pinArray    : Pointer to array of pin mux selections
+ * @param   arrayLength : Number of entries in pinArray
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
+{
+    uint32_t i;
+
+    for (i = 0; i < arrayLength; i++)
+    {
+        IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
+    }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_IOCON_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_mailbox.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,196 @@
+/*
+ * Copyright(C) NXP Semiconductors, 2014
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_MAILBOX_H_
+#define _FSL_MAILBOX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mailbox
+ * @{
+ */
+
+/*! @file */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief MAILBOX driver version 2.0.0. */
+#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief CPU ID.
+ */
+typedef enum _mailbox_cpu_id
+{
+    kMAILBOX_CM0Plus = 0,
+    kMAILBOX_CM4
+} mailbox_cpu_id_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @name MAILBOX initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the MAILBOX module.
+ *
+ * This function enables the MAILBOX clock only.
+ *
+ * @param base MAILBOX peripheral base address.
+ */
+static inline void MAILBOX_Init(MAILBOX_Type *base)
+{
+    CLOCK_EnableClock(kCLOCK_Mailbox);
+}
+
+/*!
+ * @brief De-initializes the MAILBOX module.
+ *
+ * This function disables the MAILBOX clock only.
+ *
+ * @param base MAILBOX peripheral base address.
+ */
+static inline void MAILBOX_Deinit(MAILBOX_Type *base)
+{
+    CLOCK_DisableClock(kCLOCK_Mailbox);
+}
+
+/* @} */
+
+/*!
+ * @brief Set data value in the mailbox based on the CPU ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
+ * @param mboxData Data to send in the mailbox.
+ *
+ * @note Sets a data value to send via the MAILBOX to the other core.
+ */
+static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData)
+{
+    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
+    base->MBOXIRQ[cpu_id].IRQ = mboxData;
+}
+
+/*!
+ * @brief Get data in the mailbox based on the CPU ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
+ *
+ * @return Current mailbox data.
+ */
+static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id)
+{
+    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
+    return base->MBOXIRQ[cpu_id].IRQ;
+}
+
+/*!
+ * @brief Set data bits in the mailbox based on the CPU ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
+ * @param mboxSetBits Data bits to set in the mailbox.
+ *
+ * @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will
+ * do nothing. Only sets bits selected with a 1 in it's bit position.
+ */
+static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits)
+{
+    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
+    base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits;
+}
+
+/*!
+ * @brief Clear data bits in the mailbox based on the CPU ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
+ * @param mboxClrBits Data bits to clear in the mailbox.
+ *
+ * @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will
+ * do nothing. Only clears bits selected with a 1 in it's bit position.
+ */
+static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits)
+{
+    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
+    base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits;
+}
+
+/*!
+ * @brief Get MUTEX state and lock mutex
+ *
+ * @param base MAILBOX peripheral base address.
+ *
+ * @return See note
+ *
+ * @note Returns '1' if the mutex was taken or '0' if another resources has the
+ * mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex()
+ * function.
+ */
+static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base)
+{
+    return (base->MUTEX & MAILBOX_MUTEX_EX_MASK);
+}
+
+/*!
+ * @brief Set MUTEX state
+ *
+ * @param base MAILBOX peripheral base address.
+ *
+ * @note Sets mutex state to '1' and allows other resources to get the mutex.
+ */
+static inline void MAILBOX_SetMutex(MAILBOX_Type *base)
+{
+    base->MUTEX = MAILBOX_MUTEX_EX_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus*/
+/*@}*/
+
+#endif /* _FSL_MAILBOX_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_mrt.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mrt.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Multi-Rate timer peripheral base address
+ *
+ * @return The MRT instance
+ */
+static uint32_t MRT_GetInstance(MRT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to MRT bases for each instance. */
+static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS;
+
+/*! @brief Pointers to MRT clocks for each instance. */
+static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
+
+/*! @brief Pointers to MRT resets for each instance. */
+static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t MRT_GetInstance(MRT_Type *base)
+{
+    uint32_t instance;
+    uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < mrtArrayCount; instance++)
+    {
+        if (s_mrtBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < mrtArrayCount);
+
+    return instance;
+}
+
+void MRT_Init(MRT_Type *base, const mrt_config_t *config)
+{
+    assert(config);
+
+    /* Ungate the MRT clock */
+    CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
+
+    /* Set timer operating mode */
+    base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
+}
+
+void MRT_Deinit(MRT_Type *base)
+{
+    /* Stop all the timers */
+    MRT_StopTimer(base, kMRT_Channel_0);
+    MRT_StopTimer(base, kMRT_Channel_1);
+    MRT_StopTimer(base, kMRT_Channel_2);
+    MRT_StopTimer(base, kMRT_Channel_3);
+
+    /* Gate the MRT clock*/
+    CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]);
+}
+
+void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
+{
+    uint32_t newValue = count;
+    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
+    {
+        /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
+        newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
+    }
+
+    /* Update the timer interval value */
+    base->CHANNEL[channel].INTVAL = newValue;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_mrt.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_MRT_H_
+#define _FSL_MRT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mrt
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of MRT channels */
+typedef enum _mrt_chnl
+{
+    kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/
+    kMRT_Channel_1,      /*!< MRT channel number 1 */
+    kMRT_Channel_2,      /*!< MRT channel number 2 */
+    kMRT_Channel_3       /*!< MRT channel number 3 */
+} mrt_chnl_t;
+
+/*! @brief List of MRT timer modes */
+typedef enum _mrt_timer_mode
+{
+    kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT),      /*!< Repeat Interrupt mode */
+    kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT),     /*!< One-shot Interrupt mode */
+    kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */
+} mrt_timer_mode_t;
+
+/*! @brief List of MRT interrupts */
+typedef enum _mrt_interrupt_enable
+{
+    kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/
+} mrt_interrupt_enable_t;
+
+/*! @brief List of MRT status flags */
+typedef enum _mrt_status_flags
+{
+    kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */
+    kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK,           /*!< Indicates state of the timer */
+} mrt_status_flags_t;
+
+/*!
+ * @brief MRT configuration structure
+ *
+ * This structure holds the configuration settings for the MRT peripheral. To initialize this
+ * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _mrt_config
+{
+    bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */
+} mrt_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the MRT clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the MRT driver.
+ *
+ * @param base   Multi-Rate timer peripheral base address
+ * @param config Pointer to user's MRT config structure
+ */
+void MRT_Init(MRT_Type *base, const mrt_config_t *config);
+
+/*!
+ * @brief Gate the MRT clock
+ *
+ * @param base Multi-Rate timer peripheral base address
+ */
+void MRT_Deinit(MRT_Type *base);
+
+/*!
+ * @brief Fill in the MRT config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *     config->enableMultiTask = false;
+ * @endcode
+ * @param config Pointer to user's MRT config structure.
+ */
+static inline void MRT_GetDefaultConfig(mrt_config_t *config)
+{
+    assert(config);
+
+    /* Use hardware status operating mode */
+    config->enableMultiTask = false;
+}
+
+/*!
+ * @brief Sets up an MRT channel mode.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Channel that is being configured.
+ * @param mode    Timer mode to use for the channel.
+ */
+static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
+{
+    uint32_t reg = base->CHANNEL[channel].CTRL;
+
+    /* Clear old value */
+    reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
+    /* Add the new mode */
+    reg |= mode;
+
+    base->CHANNEL[channel].CTRL = reg;
+}
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the MRT interrupt.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to enable. This is a logical OR of members of the
+ *                enumeration ::mrt_interrupt_enable_t
+ */
+static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].CTRL |= mask;
+}
+
+/*!
+ * @brief Disables the selected MRT interrupt.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to disable. This is a logical OR of members of the
+ *                enumeration ::mrt_interrupt_enable_t
+ */
+static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].CTRL &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled MRT interrupts.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::mrt_interrupt_enable_t
+ */
+static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
+{
+    return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the MRT status flags
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::mrt_status_flags_t
+ */
+static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
+{
+    return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
+}
+
+/*!
+ * @brief Clears the MRT status flags.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The status flags to clear. This is a logical OR of members of the
+ *                enumeration ::mrt_status_flags_t
+ */
+static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Used to update the timer period in units of count.
+ *
+ * The new value will be immediately loaded or will be loaded at the end of the current time
+ * interval. For one-shot interrupt mode the new value will be immediately loaded.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base          Multi-Rate timer peripheral base address
+ * @param channel       Timer channel number
+ * @param count         Timer period in units of ticks
+ * @param immediateLoad true: Load the new value immediately into the TIMER register;
+ *                      false: Load the new value at the end of current timer interval
+ */
+void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad);
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return Current timer counting value in ticks
+ */
+static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
+{
+    return base->CHANNEL[channel].TIMER;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load period value, counts down to 0 and
+ * depending on the timer mode it will either load the respective start value again or stop.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ * @param count   Timer period in units of ticks
+ */
+static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
+{
+    /* Write the timer interval value */
+    base->CHANNEL[channel].INTVAL = count;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops the timer from counting.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
+{
+    /* Stop the timer immediately */
+    base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @name Get & release channel
+ * @{
+ */
+
+/*!
+ * @brief Find the available channel.
+ *
+ * This function returns the lowest available channel number.
+ *
+ * @param base Multi-Rate timer peripheral base address
+ */
+static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
+{
+    return base->IDLE_CH;
+}
+
+/*!
+ * @brief Release the channel when the timer is using the multi-task mode.
+ *
+ * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for
+ * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as
+ * long as it is needed and release it by calling this function. This removes the need to ask for
+ * an available channel for every use.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
+{
+    uint32_t reg = base->CHANNEL[channel].STAT;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK;
+    reg |= MRT_CHANNEL_STAT_INUSE_MASK;
+
+    base->CHANNEL[channel].STAT = reg;
+}
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_MRT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_pint.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pint.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Irq number array */
+static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
+
+/*! @brief Callback function array for PINT(s). */
+static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void PINT_Init(PINT_Type *base)
+{
+    uint32_t i;
+    uint32_t pmcfg;
+
+    assert(base);
+
+    pmcfg = 0;
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        s_pintCallback[i] = NULL;
+    }
+
+    /* Disable all bit slices */
+    for (i = 0; i < PINT_PIN_INT_COUNT; i++)
+    {
+        pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
+    }
+
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(kCLOCK_Pint);
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
+
+    /* Disable all pattern match bit slices */
+    base->PMCFG = pmcfg;
+}
+
+void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
+{
+    assert(base);
+
+    /* Clear Rise and Fall flags first */
+    PINT_PinInterruptClrRiseFlag(base, intr);
+    PINT_PinInterruptClrFallFlag(base, intr);
+
+    /* select level or edge sensitive */
+    base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U);
+
+    /* enable rising or level interrupt */
+    if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
+    {
+        base->SIENR = 1U << intr;
+    }
+    else
+    {
+        base->CIENR = 1U << intr;
+    }
+
+    /* Enable falling or select high level */
+    if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+    {
+        base->SIENF = 1U << intr;
+    }
+    else
+    {
+        base->CIENF = 1U << intr;
+    }
+
+    s_pintCallback[intr] = callback;
+}
+
+void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
+{
+    uint32_t mask;
+    bool level;
+
+    assert(base);
+
+    *enable = kPINT_PinIntEnableNone;
+    level = false;
+
+    mask = 1U << pintr;
+    if (base->ISEL & mask)
+    {
+        /* Pin interrupt is level sensitive */
+        level = true;
+    }
+
+    if (base->IENR & mask)
+    {
+        if (level)
+        {
+            /* Level interrupt is enabled */
+            *enable = kPINT_PinIntEnableLowLevel;
+        }
+        else
+        {
+            /* Rising edge interrupt */
+            *enable = kPINT_PinIntEnableRiseEdge;
+        }
+    }
+
+    if (base->IENF & mask)
+    {
+        if (level)
+        {
+            /* Level interrupt is active high */
+            *enable = kPINT_PinIntEnableHighLevel;
+        }
+        else
+        {
+            /* Either falling or both edge */
+            if (*enable == kPINT_PinIntEnableRiseEdge)
+            {
+                /* Rising and faling edge */
+                *enable = kPINT_PinIntEnableBothEdges;
+            }
+            else
+            {
+                /* Falling edge */
+                *enable = kPINT_PinIntEnableFallEdge;
+            }
+        }
+    }
+
+    *callback = s_pintCallback[pintr];
+}
+
+void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
+{
+    uint32_t src_shift;
+    uint32_t cfg_shift;
+    uint32_t pmcfg;
+
+    assert(base);
+
+    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
+    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
+
+    /* Input source selection for selected bit slice */
+    base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift);
+
+    /* Bit slice configuration */
+    pmcfg = base->PMCFG;
+    pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
+
+    /* If end point is true, enable the bits */
+    if (bslice != 7U)
+    {
+        if (cfg->end_point)
+        {
+            pmcfg |= (0x1U << bslice);
+        }
+        else
+        {
+            pmcfg &= ~(0x1U << bslice);
+        }
+    }
+
+    base->PMCFG = pmcfg;
+
+    /* Save callback pointer */
+    s_pintCallback[bslice] = cfg->callback;
+}
+
+void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
+{
+    uint32_t src_shift;
+    uint32_t cfg_shift;
+
+    assert(base);
+
+    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
+    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
+
+    cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift);
+    cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift);
+
+    if (bslice == 7U)
+    {
+        cfg->end_point = true;
+    }
+    else
+    {
+        cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice;
+    }
+    cfg->callback = s_pintCallback[bslice];
+}
+
+uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
+{
+    uint32_t pmctrl;
+    uint32_t pmstatus;
+    uint32_t pmsrc;
+
+    pmctrl = PINT->PMCTRL;
+    pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
+    if (pmstatus)
+    {
+        /* Reset Pattern match engine detection logic */
+        pmsrc = base->PMSRC;
+        base->PMSRC = pmsrc;
+    }
+    return (pmstatus);
+}
+
+void PINT_EnableCallback(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    PINT_PinInterruptClrStatusAll(base);
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
+        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
+        EnableIRQ(s_pintIRQ[i]);
+    }
+}
+
+void PINT_DisableCallback(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        DisableIRQ(s_pintIRQ[i]);
+        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
+        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
+    }
+}
+
+void PINT_Deinit(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    /* Cleanup */
+    PINT_DisableCallback(base);
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        s_pintCallback[i] = NULL;
+    }
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
+
+    /* Disable the peripheral clock */
+    CLOCK_DisableClock(kCLOCK_Pint);
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+void PIN_INT0_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt0] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
+    }
+}
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+void PIN_INT1_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt1] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+void PIN_INT2_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt2] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+void PIN_INT3_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt3] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+void PIN_INT4_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt4] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+void PIN_INT5_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt5] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+void PIN_INT6_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt6] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+void PIN_INT7_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt7] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_pint.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_PINT_H_
+#define _FSL_PINT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup pint_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/* Number of interrupt line supported by PINT */
+#define PINT_PIN_INT_COUNT 8U
+
+/* Number of input sources supported by PINT */
+#define PINT_INPUT_COUNT 8U
+
+/* PININT Bit slice source register bits */
+#define PININT_BITSLICE_SRC_START 8U
+#define PININT_BITSLICE_SRC_MASK 7U
+
+/* PININT Bit slice configuration register bits */
+#define PININT_BITSLICE_CFG_START 8U
+#define PININT_BITSLICE_CFG_MASK 7U
+#define PININT_BITSLICE_ENDP_MASK 7U
+
+#define PINT_PIN_INT_LEVEL 0x10U
+#define PINT_PIN_INT_EDGE 0x00U
+#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U
+#define PINT_PIN_INT_RISE 0x01U
+#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE)
+#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL)
+#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+
+/*! @brief PINT Pin Interrupt enable type */
+typedef enum _pint_pin_enable
+{
+    kPINT_PinIntEnableNone = 0U,                      /*!< Do not generate Pin Interrupt */
+    kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE,  /*!< Generate Pin Interrupt on rising edge */
+    kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE,  /*!< Generate Pin Interrupt on falling edge */
+    kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */
+    kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL,  /*!< Generate Pin Interrupt on low level */
+    kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */
+} pint_pin_enable_t;
+
+/*! @brief PINT Pin Interrupt type */
+typedef enum _pint_int
+{
+    kPINT_PinInt0 = 0U, /*!< Pin Interrupt  0 */
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+    kPINT_PinInt1 = 1U, /*!< Pin Interrupt  1 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+    kPINT_PinInt2 = 2U, /*!< Pin Interrupt  2 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+    kPINT_PinInt3 = 3U, /*!< Pin Interrupt  3 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+    kPINT_PinInt4 = 4U, /*!< Pin Interrupt  4 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+    kPINT_PinInt5 = 5U, /*!< Pin Interrupt  5 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+    kPINT_PinInt6 = 6U, /*!< Pin Interrupt  6 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+    kPINT_PinInt7 = 7U, /*!< Pin Interrupt  7 */
+#endif
+} pint_pin_int_t;
+
+/*! @brief PINT Pattern Match bit slice input source type */
+typedef enum _pint_pmatch_input_src
+{
+    kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */
+    kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */
+    kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */
+    kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */
+    kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */
+    kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */
+    kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */
+    kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */
+} pint_pmatch_input_src_t;
+
+/*! @brief PINT Pattern Match bit slice type */
+typedef enum _pint_pmatch_bslice
+{
+    kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+    kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+    kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+    kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+    kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+    kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+    kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+    kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */
+#endif
+} pint_pmatch_bslice_t;
+
+/*! @brief PINT Pattern Match configuration type */
+typedef enum _pint_pmatch_bslice_cfg
+{
+    kPINT_PatternMatchAlways = 0U,          /*!< Always Contributes to product term match */
+    kPINT_PatternMatchStickyRise = 1U,      /*!< Sticky Rising edge */
+    kPINT_PatternMatchStickyFall = 2U,      /*!< Sticky Falling edge */
+    kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */
+    kPINT_PatternMatchHigh = 4U,            /*!< High level */
+    kPINT_PatternMatchLow = 5U,             /*!< Low level */
+    kPINT_PatternMatchNever = 6U,           /*!< Never contributes to product term match */
+    kPINT_PatternMatchBothEdges = 7U,       /*!< Either rising or falling edge */
+} pint_pmatch_bslice_cfg_t;
+
+/*! @brief PINT Callback function. */
+typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status);
+
+typedef struct _pint_pmatch_cfg
+{
+    pint_pmatch_input_src_t bs_src;
+    pint_pmatch_bslice_cfg_t bs_cfg;
+    bool end_point;
+    pint_cb_t callback;
+} pint_pmatch_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize PINT peripheral.
+
+ * This function initializes the PINT peripheral and enables the clock.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_Init(PINT_Type *base);
+
+/*!
+ * @brief	Configure PINT peripheral pin interrupt.
+
+ * This function configures a given pin interrupt.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param intr Pin interrupt.
+ * @param enable Selects detection logic.
+ * @param callback Callback.
+ *
+ * @retval None.
+ */
+void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback);
+
+/*!
+ * @brief	Get PINT peripheral pin interrupt configuration.
+
+ * This function returns the configuration of a given pin interrupt.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ * @param enable Pointer to store the detection logic.
+ * @param callback Callback.
+ *
+ * @retval None.
+ */
+void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback);
+
+/*!
+ * @brief	Clear Selected pin interrupt status.
+
+ * This function clears the selected pin interrupt status.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->IST = (1U << pintr);
+}
+
+/*!
+ * @brief	Get Selected pin interrupt status.
+
+ * This function returns the selected pin interrupt status.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval status = 0 No pin interrupt request.  = 1 Selected Pin interrupt request active.
+ */
+static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->IST & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupts status.
+
+ * This function clears the status of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base)
+{
+    base->IST = PINT_IST_PSTAT_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupts status.
+
+ * This function returns the status of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval status Each bit position indicates the status of corresponding pin interrupt.
+ * = 0 No pin interrupt request. = 1 Pin interrupt request active.
+ */
+static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base)
+{
+    return (base->IST);
+}
+
+/*!
+ * @brief	Clear Selected pin interrupt fall flag.
+
+ * This function clears the selected pin interrupt fall flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->FALL = (1U << pintr);
+}
+
+/*!
+ * @brief	Get selected pin interrupt fall flag.
+
+ * This function returns the selected pin interrupt fall flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval flag = 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->FALL & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupt fall flags.
+
+ * This function clears the fall flag for all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base)
+{
+    base->FALL = PINT_FALL_FDET_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupt fall flags.
+
+ * This function returns the fall flag of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt.
+ * 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base)
+{
+    return (base->FALL);
+}
+
+/*!
+ * @brief	Clear Selected pin interrupt rise flag.
+
+ * This function clears the selected pin interrupt rise flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->RISE = (1U << pintr);
+}
+
+/*!
+ * @brief	Get selected pin interrupt rise flag.
+
+ * This function returns the selected pin interrupt rise flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval flag = 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->RISE & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupt rise flags.
+
+ * This function clears the rise flag for all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base)
+{
+    base->RISE = PINT_RISE_RDET_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupt rise flags.
+
+ * This function returns the rise flag of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt.
+ * 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base)
+{
+    return (base->RISE);
+}
+
+/*!
+ * @brief	Configure PINT pattern match.
+
+ * This function configures a given pattern match bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ * @param cfg Pointer to bit slice configuration.
+ *
+ * @retval None.
+ */
+void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
+
+/*!
+ * @brief	Get PINT pattern match configuration.
+
+ * This function returns the configuration of a given pattern match bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ * @param cfg Pointer to bit slice configuration.
+ *
+ * @retval None.
+ */
+void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
+
+/*!
+ * @brief	Get pattern match bit slice status.
+
+ * This function returns the status of selected bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ *
+ * @retval status = 0 Match has not been detected.  = 1 Match has been detected.
+ */
+static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice)
+{
+    return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice;
+}
+
+/*!
+ * @brief	Get status of all pattern match bit slices.
+
+ * This function returns the status of all bit slices.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval status Each bit position indicates the match status of corresponding bit slice.
+ * = 0 Match has not been detected.  = 1 Match has been detected.
+ */
+static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base)
+{
+    return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT;
+}
+
+/*!
+ * @brief	Reset pattern match detection logic.
+
+ * This function resets the pattern match detection logic if any of the product term is matching.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval pmstatus Each bit position indicates the match status of corresponding bit slice.
+ * = 0 Match was detected.  = 1 Match was not detected.
+ */
+uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base);
+
+/*!
+ * @brief	Enable pattern match function.
+
+ * This function enables the pattern match function.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchEnable(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK;
+}
+
+/*!
+ * @brief	Disable pattern match function.
+
+ * This function disables the pattern match function.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchDisable(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK;
+}
+
+/*!
+ * @brief	Enable RXEV output.
+
+ * This function enables the pattern match RXEV output.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK;
+}
+
+/*!
+ * @brief	Disable RXEV output.
+
+ * This function disables the pattern match RXEV output.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK;
+}
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
+ * as soon as they are enabled, the callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_EnableCallback(PINT_Type *base);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected PINT peripheral. Although the pins are still
+ * being monitored but the callback function is not called.
+ *
+ * @param base Base address of the peripheral.
+ *
+ * @retval None.
+ */
+void PINT_DisableCallback(PINT_Type *base);
+
+/*!
+ * @brief	Deinitialize PINT peripheral.
+
+ * This function disables the PINT clock.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_Deinit(PINT_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_PINT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_power.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Empty file since implementation is in header file and power library */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_power.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup power */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot)
+#define PDRCFG0 0x0U
+#define PDRCFG1 0x1U
+
+typedef enum pd_bits
+{
+    kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
+    kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U),
+    kPDRUNCFG_PD_TEMPS = MAKE_PD_BITS(PDRCFG0, 6U),
+    kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
+    kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
+    kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
+    kPDRUNCFG_PD_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 11U),
+    kPDRUNCFG_LP_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 12U),
+    kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
+    kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
+    kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
+    kPDRUNCFG_PD_RAMX = MAKE_PD_BITS(PDRCFG0, 16U),
+    kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
+    kPDRUNCFG_PD_VDDHV_ENA = MAKE_PD_BITS(PDRCFG0, 18U),
+    kPDRUNCFG_PD_VD7_ENA = MAKE_PD_BITS(PDRCFG0, 19U),
+    kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
+    kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
+    kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
+    kPDRUNCFG_PD_VREFP_SW = MAKE_PD_BITS(PDRCFG0, 23U),
+    kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
+
+    kPDRUNCFG_PD_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 28U),
+    kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U),
+    
+    kPDRUNCFG_ForceUnsigned = 0x80000000U
+} pd_bit_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @name Power Configuration
+* @{
+*/
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
+ *
+ * @param en    peripheral for which to enable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_EnablePD(pd_bit_t en)
+{
+    /* PDRUNCFGSET */
+    SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU));
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
+ *
+ * @param en    peripheral for which to disable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_DisablePD(pd_bit_t en)
+{
+    /* PDRUNCFGCLR */
+    SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU));
+}
+
+/*!
+ * @brief API to enable deep sleep bit in the ARM Core.
+ *
+ * @return none
+ */
+static inline void POWER_EnableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to disable deep sleep bit in the ARM Core.
+ *
+ * @return none
+ */
+static inline void POWER_DisableDeepSleep(void)
+{
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to power down flash controller.
+ *
+ * @return none
+ */
+static inline void POWER_PowerDownFlash(void)
+{
+    /* note, we retain flash trim to make waking back up faster */
+    SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK | SYSCON_PDRUNCFG_PD_FLASH_BG_MASK;
+
+    /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */
+    CLOCK_DisableClock(kCLOCK_Flash);
+
+    /* TURN OFF clock for Flash Accelerator */
+    CLOCK_DisableClock(kCLOCK_Fmc);
+}
+
+/*!
+ * @brief API to power up flash controller.
+ *
+ * @return none
+ */
+static inline void POWER_PowerUpFlash(void)
+{
+    SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_LP_VDDFLASH_MASK | SYSCON_PDRUNCFG_PD_VDDHV_ENA_MASK;
+
+    /* TURN ON clock for flash controller */
+    CLOCK_EnableClock(kCLOCK_Fmc);
+}
+
+
+/*!
+ * @brief Power Library API to enter deep sleep mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
+ * @return none
+ */
+void POWER_EnterDeepSleep(uint32_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter deep power down mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode, 
+ *                         but this is has no effect as the voltages are cut off.
+ * @return none
+ */
+void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq  - The desired frequency at which the part would like to operate, 
+ *                note that the voltage and flash wait states should be set before changing frequency
+ * @return none
+ */
+void POWER_SetVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq  - The desired frequency at which the part would like to operate, 
+ *                note only 12MHz and 48Mhz are supported
+ * @return none
+ */
+void POWER_SetLowPowerVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+/* @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_POWER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_reset.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* set bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* set bit */
+        SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* clear bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* clear bit */
+        SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_reset.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+    kFLASH_RST_SHIFT_RSTn = 0 | 7U,          /**< Flash controller reset control */
+    kFMC_RST_SHIFT_RSTn = 0 | 8U,            /**< Flash accelerator reset control */
+    kMUX_RST_SHIFT_RSTn = 0 | 11U,           /**< Input mux reset control */
+    kIOCON_RST_SHIFT_RSTn = 0 | 13U,         /**< IOCON reset control */
+    kGPIO0_RST_SHIFT_RSTn = 0 | 14U,         /**< GPIO0 reset control */
+    kGPIO1_RST_SHIFT_RSTn = 0 | 15U,         /**< GPIO1 reset control */
+    kPINT_RST_SHIFT_RSTn = 0 | 18U,          /**< Pin interrupt (PINT) reset control */
+    kGINT_RST_SHIFT_RSTn = 0 | 19U,          /**< Grouped interrupt (PINT) reset control. */
+    kDMA_RST_SHIFT_RSTn = 0 | 20U,           /**< DMA reset control */
+    kCRC_RST_SHIFT_RSTn = 0 | 21U,           /**< CRC reset control */
+    kWWDT_RST_SHIFT_RSTn = 0 | 22U,          /**< Watchdog timer reset control */
+    kADC0_RST_SHIFT_RSTn = 0 | 27U,          /**< ADC0 reset control */
+    kMRT_RST_SHIFT_RSTn = 65536 | 0U,        /**< Multi-rate timer (MRT) reset control */
+    kSCT0_RST_SHIFT_RSTn = 65536 | 2U,       /**< SCTimer/PWM 0 (SCT0) reset control */
+    kUTICK_RST_SHIFT_RSTn = 65536 | 10U,     /**< Micro-tick timer reset control */
+    kFC0_RST_SHIFT_RSTn = 65536 | 11U,       /**< Flexcomm Interface 0 reset control */
+    kFC1_RST_SHIFT_RSTn = 65536 | 12U,       /**< Flexcomm Interface 1 reset control */
+    kFC2_RST_SHIFT_RSTn = 65536 | 13U,       /**< Flexcomm Interface 2 reset control */
+    kFC3_RST_SHIFT_RSTn = 65536 | 14U,       /**< Flexcomm Interface 3 reset control */
+    kFC4_RST_SHIFT_RSTn = 65536 | 15U,       /**< Flexcomm Interface 4 reset control */
+    kFC5_RST_SHIFT_RSTn = 65536 | 16U,       /**< Flexcomm Interface 5 reset control */
+    kFC6_RST_SHIFT_RSTn = 65536 | 17U,       /**< Flexcomm Interface 6 reset control */
+    kFC7_RST_SHIFT_RSTn = 65536 | 18U,       /**< Flexcomm Interface 7 reset control */
+    kDMIC_RST_SHIFT_RSTn = 65536 | 19U,      /**< Digital microphone interface reset control */
+    kCT32B2_RST_SHIFT_RSTn = 65536 | 22U,    /**< CT32B2 reset control */
+    kUSB_RST_SHIFT_RSTn = 65536 | 25U,       /**< USB reset control */
+    kCT32B0_RST_SHIFT_RSTn = 65536 | 26U,    /**< CT32B0 reset control */
+    kCT32B1_RST_SHIFT_RSTn = 65536 | 27U,    /**< CT32B1 reset control */
+    kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
+    kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS             \
+    {                        \
+        kADC0_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define CRC_RSTS            \
+    {                       \
+        kCRC_RST_SHIFT_RSTn \
+    } /* Reset bits for CRC peripheral */
+#define DMA_RSTS            \
+    {                       \
+        kDMA_RST_SHIFT_RSTn \
+    } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS            \
+    {                        \
+        kDMIC_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define FLEXCOMM_RSTS                                                                                            \
+    {                                                                                                            \
+        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn                                        \
+    } /* Reset bits for FLEXCOMM peripheral */
+#define GINT_RSTS                                  \
+    {                                              \
+        kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
+    } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
+#define GPIO_RSTS                                    \
+    {                                                \
+        kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
+    } /* Reset bits for GPIO peripheral */
+#define INPUTMUX_RSTS       \
+    {                       \
+        kMUX_RST_SHIFT_RSTn \
+    } /* Reset bits for INPUTMUX peripheral */
+#define IOCON_RSTS            \
+    {                         \
+        kIOCON_RST_SHIFT_RSTn \
+    } /* Reset bits for IOCON peripheral */
+#define FLASH_RSTS                                 \
+    {                                              \
+        kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
+    } /* Reset bits for Flash peripheral */
+#define MRT_RSTS            \
+    {                       \
+        kMRT_RST_SHIFT_RSTn \
+    } /* Reset bits for MRT peripheral */
+#define PINT_RSTS            \
+    {                        \
+        kPINT_RST_SHIFT_RSTn \
+    } /* Reset bits for PINT peripheral */
+#define SCT_RSTS             \
+    {                        \
+        kSCT0_RST_SHIFT_RSTn \
+    } /* Reset bits for SCT peripheral */
+#define CTIMER_RSTS                                                                                      \
+    {                                                                                                   \
+        kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+            kCT32B4_RST_SHIFT_RSTn                                                                      \
+    } /* Reset bits for TIMER peripheral */
+#define USB_RSTS            \
+    {                       \
+        kUSB_RST_SHIFT_RSTn \
+    } /* Reset bits for USB peripheral */
+#define UTICK_RSTS            \
+    {                         \
+        kUTICK_RST_SHIFT_RSTn \
+    } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for WWDT peripheral */
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_rtc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SECONDS_IN_A_DAY (86400U)
+#define SECONDS_IN_A_HOUR (3600U)
+#define SECONDS_IN_A_MINUTE (60U)
+#define DAYS_IN_A_YEAR (365U)
+#define YEAR_RANGE_START (1970U)
+#define YEAR_RANGE_END (2099U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Checks whether the date and time passed in is valid
+ *
+ * @param datetime Pointer to structure where the date and time details are stored
+ *
+ * @return Returns false if the date & time details are out of range; true if in range
+ */
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from datetime to seconds
+ *
+ * @param datetime Pointer to datetime structure where the date and time details are stored
+ *
+ * @return The result of the conversion in seconds
+ */
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from seconds to a datetime structure
+ *
+ * @param seconds  Seconds value that needs to be converted to datetime format
+ * @param datetime Pointer to the datetime structure where the result of the conversion is stored
+ */
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Check year, month, hour, minute, seconds */
+    if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
+        (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
+    {
+        /* If not correct then error*/
+        return false;
+    }
+
+    /* Adjust the days in February for a leap year */
+    if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    /* Check the validity of the day */
+    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
+    {
+        return false;
+    }
+
+    return true;
+}
+
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Number of days from begin of the non Leap-year*/
+    /* Number of days from begin of the non Leap-year*/
+    uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
+    uint32_t seconds;
+
+    /* Compute number of days from 1970 till given year*/
+    seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
+    /* Add leap year days */
+    seconds += ((datetime->year / 4) - (1970U / 4));
+    /* Add number of days till given month*/
+    seconds += monthDays[datetime->month];
+    /* Add days in given month. We subtract the current day as it is
+     * represented in the hours, minutes and seconds field*/
+    seconds += (datetime->day - 1);
+    /* For leap year if month less than or equal to Febraury, decrement day counter*/
+    if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
+    {
+        seconds--;
+    }
+
+    seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
+              (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
+
+    return seconds;
+}
+
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t x;
+    uint32_t secondsRemaining, days;
+    uint16_t daysInYear;
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Start with the seconds value that is passed in to be converted to date time format */
+    secondsRemaining = seconds;
+
+    /* Calcuate the number of days, we add 1 for the current day which is represented in the
+     * hours and seconds field
+     */
+    days = secondsRemaining / SECONDS_IN_A_DAY + 1;
+
+    /* Update seconds left*/
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
+
+    /* Calculate the datetime hour, minute and second fields */
+    datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
+    datetime->minute = secondsRemaining / 60U;
+    datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
+
+    /* Calculate year */
+    daysInYear = DAYS_IN_A_YEAR;
+    datetime->year = YEAR_RANGE_START;
+    while (days > daysInYear)
+    {
+        /* Decrease day count by a year and increment year by 1 */
+        days -= daysInYear;
+        datetime->year++;
+
+        /* Adjust the number of days for a leap year */
+        if (datetime->year & 3U)
+        {
+            daysInYear = DAYS_IN_A_YEAR;
+        }
+        else
+        {
+            daysInYear = DAYS_IN_A_YEAR + 1;
+        }
+    }
+
+    /* Adjust the days in February for a leap year */
+    if (!(datetime->year & 3U))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    for (x = 1U; x <= 12U; x++)
+    {
+        if (days <= daysPerMonth[x])
+        {
+            datetime->month = x;
+            break;
+        }
+        else
+        {
+            days -= daysPerMonth[x];
+        }
+    }
+
+    datetime->day = days;
+}
+
+void RTC_Init(RTC_Type *base)
+{
+    /* Enable the RTC peripheral clock */
+    CLOCK_EnableClock(kCLOCK_Rtc);
+
+    /* Make sure the reset bit is cleared */
+    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
+
+    /* Make sure the RTC OSC is powered up */
+    base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK;
+}
+
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Return error if the time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(datetime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set time in seconds */
+    base->COUNT = RTC_ConvertDatetimeToSeconds(datetime);
+
+    return kStatus_Success;
+}
+
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t seconds = 0;
+
+    seconds = base->COUNT;
+    RTC_ConvertSecondsToDatetime(seconds, datetime);
+}
+
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
+{
+    assert(alarmTime);
+
+    uint32_t alarmSeconds = 0;
+    uint32_t currSeconds = 0;
+
+    /* Return error if the alarm time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(alarmTime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
+
+    /* Get the current time */
+    currSeconds = base->COUNT;
+
+    /* Return error if the alarm time has passed */
+    if (alarmSeconds < currSeconds)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set alarm in seconds*/
+    base->MATCH = alarmSeconds;
+
+    return kStatus_Success;
+}
+
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t alarmSeconds = 0;
+
+    /* Get alarm in seconds  */
+    alarmSeconds = base->MATCH;
+
+    RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_rtc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RTC_H_
+#define _FSL_RTC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rtc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RTC interrupts */
+typedef enum _rtc_interrupt_enable
+{
+    kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/
+    kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK  /*!< Wake-up interrupt.*/
+} rtc_interrupt_enable_t;
+
+/*! @brief List of RTC flags */
+typedef enum _rtc_status_flags
+{
+    kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/
+    kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/
+} rtc_status_flags_t;
+
+/*! @brief Structure is used to hold the date and time */
+typedef struct _rtc_datetime
+{
+    uint16_t year;  /*!< Range from 1970 to 2099.*/
+    uint8_t month;  /*!< Range from 1 to 12.*/
+    uint8_t day;    /*!< Range from 1 to 31 (depending on month).*/
+    uint8_t hour;   /*!< Range from 0 to 23.*/
+    uint8_t minute; /*!< Range from 0 to 59.*/
+    uint8_t second; /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RTC clock and enables the RTC oscillator.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_Init(RTC_Type *base);
+
+/*!
+ * @brief Stop the timer and gate the RTC clock
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Deinit(RTC_Type *base)
+{
+    /* Stop the RTC timer */
+    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
+
+    /* Gate the module clock */
+    CLOCK_DisableClock(kCLOCK_Rtc);
+}
+
+/*! @}*/
+
+/*!
+ * @name Current Time & Alarm
+ * @{
+ */
+
+/*!
+ * @brief Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter must be stopped prior to calling this function as writes to the RTC
+ * seconds register will fail if the RTC counter is running.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details to set are stored
+ *
+ * @return kStatus_Success: Success in setting the time and starting the RTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Gets the RTC time and stores it in the given time structure.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details are stored.
+ */
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*!
+ * @brief Sets the RTC alarm time
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base      RTC peripheral base address
+ * @param alarmTime Pointer to structure where the alarm time is stored.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
+
+/*!
+ * @brief Returns the RTC alarm time.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the alarm date and time details are stored.
+ */
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*! @}*/
+
+/*!
+ * @brief Enable the RTC high resolution timer and set the wake-up time.
+ *
+ * @param base        RTC peripheral base address
+ * @param wakeupValue The value to be loaded into the RTC WAKE register
+ */
+static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue)
+{
+    /* Enable the 1kHz RTC timer */
+    base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK;
+
+    /* Set the start count value into the wake-up timer */
+    base->WAKE = wakeupValue;
+}
+
+/*!
+ * @brief Read actual RTC counter value.
+ *
+ * @param base        RTC peripheral base address
+ */
+static inline uint16_t RTC_GetWakeupCount(RTC_Type *base)
+{
+    /* Read wake-up counter */
+    return RTC_WAKE_VAL(base->WAKE);
+}
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
+    reg |= mask;
+
+    base->CTRL = reg;
+}
+
+/*!
+ * @brief Disables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask);
+
+    base->CTRL = reg;
+}
+
+/*!
+ * @brief Gets the enabled RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::rtc_interrupt_enable_t
+ */
+static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
+{
+    return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RTC status flags
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::rtc_status_flags_t
+ */
+static inline uint32_t RTC_GetStatusFlags(RTC_Type *base)
+{
+    return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK));
+}
+
+/*!
+ * @brief  Clears the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::rtc_status_flags_t
+ */
+static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
+
+    /* Write 1 to the flags we wish to clear */
+    reg |= mask;
+
+    base->CTRL = reg;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * After calling this function, the timer counter increments once a second provided SR[TOF] or
+ * SR[TIF] are not set.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StartTimer(RTC_Type *base)
+{
+    base->CTRL |= RTC_CTRL_RTC_EN_MASK;
+}
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * RTC's seconds register can be written to only when the timer is stopped.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StopTimer(RTC_Type *base)
+{
+    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Reset(RTC_Type *base)
+{
+    base->CTRL |= RTC_CTRL_SWRESET_MASK;
+    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RTC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_sctimer.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,529 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sctimer.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Typedef for interrupt handler. */
+typedef void (*sctimer_isr_t)(SCT_Type *base);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The SCTimer instance
+ */
+static uint32_t SCTIMER_GetInstance(SCT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to SCT bases for each instance. */
+static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS;
+
+/*! @brief Pointers to SCT clocks for each instance. */
+static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS;
+
+/*! @brief Pointers to SCT resets for each instance. */
+static const reset_ip_name_t s_sctResets[] = SCT_RSTS;
+
+/*!< @brief SCTimer event Callback function. */
+static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS];
+
+/*!< @brief Keep track of SCTimer event number */
+static uint32_t s_currentEvent;
+
+/*!< @brief Keep track of SCTimer state number */
+static uint32_t s_currentState;
+
+/*!< @brief Keep track of SCTimer match/capture register number */
+static uint32_t s_currentMatch;
+
+/*! @brief Pointer to SCTimer IRQ handler */
+static sctimer_isr_t s_sctimerIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SCTIMER_GetInstance(SCT_Type *base)
+{
+    uint32_t instance;
+    uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < sctArrayCount; instance++)
+    {
+        if (s_sctBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < sctArrayCount);
+
+    return instance;
+}
+
+status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config)
+{
+    assert(config);
+    uint32_t i;
+
+    /* Enable the SCTimer clock*/
+    CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]);
+
+    /* Setup the counter operation */
+    base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) |
+                   SCT_CONFIG_UNIFY(config->enableCounterUnify);
+
+    /* Write to the control register, clear the counter and keep the counters halted */
+    base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) |
+                 SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK;
+
+    if (!(config->enableCounterUnify))
+    {
+        base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) |
+                      SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK;
+    }
+
+    /* Initial state of channel output */
+    base->OUTPUT = config->outInitState;
+
+    /* Clear the global variables */
+    s_currentEvent = 0;
+    s_currentState = 0;
+    s_currentMatch = 0;
+
+    /* Clear the callback array */
+    for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
+    {
+        s_eventCallback[i] = NULL;
+    }
+
+    /* Save interrupt handler */
+    s_sctimerIsr = SCTIMER_EventHandleIRQ;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_Deinit(SCT_Type *base)
+{
+    /* Halt the counters */
+    base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK);
+
+    /* Disable the SCTimer clock*/
+    CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
+}
+
+void SCTIMER_GetDefaultConfig(sctimer_config_t *config)
+{
+    assert(config);
+
+    /* SCT operates as a unified 32-bit counter */
+    config->enableCounterUnify = true;
+    /* System clock clocks the entire SCT module */
+    config->clockMode = kSCTIMER_System_ClockMode;
+    /* This is used only by certain clock modes */
+    config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
+    /* Up count mode only for the unified counter */
+    config->enableBidirection_l = false;
+    /* Up count mode only for Counte_H */
+    config->enableBidirection_h = false;
+    /* Prescale factor of 1 */
+    config->prescale_l = 0;
+    /* Prescale factor of 1 for Counter_H*/
+    config->prescale_h = 0;
+    /* Clear outputs */
+    config->outInitState = 0;
+}
+
+status_t SCTIMER_SetupPwm(SCT_Type *base,
+                          const sctimer_pwm_signal_param_t *pwmParams,
+                          sctimer_pwm_mode_t mode,
+                          uint32_t pwmFreq_Hz,
+                          uint32_t srcClock_Hz,
+                          uint32_t *event)
+{
+    assert(pwmParams);
+    assert(srcClock_Hz);
+    assert(pwmFreq_Hz);
+
+    uint32_t period, pulsePeriod = 0;
+    uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1);
+    uint32_t periodEvent, pulseEvent;
+    uint32_t reg;
+
+    /* This function will create 2 events, return an error if we do not have enough events available */
+    if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
+    {
+        return kStatus_Fail;
+    }
+
+    if (pwmParams->dutyCyclePercent == 0)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set unify bit to operate in 32-bit counter mode */
+    base->CONFIG |= SCT_CONFIG_UNIFY_MASK;
+
+    /* Use bi-directional mode for center-aligned PWM */
+    if (mode == kSCTIMER_CenterAlignedPwm)
+    {
+        base->CTRL |= SCT_CTRL_BIDIR_L_MASK;
+    }
+
+    /* Calculate PWM period match value */
+    if (mode == kSCTIMER_EdgeAlignedPwm)
+    {
+        period = (sctClock / pwmFreq_Hz) - 1;
+    }
+    else
+    {
+        period = sctClock / (pwmFreq_Hz * 2);
+    }
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100;
+
+    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
+    if (pwmParams->dutyCyclePercent >= 100)
+    {
+        pulsePeriod = period + 2;
+    }
+
+    /* Schedule an event when we reach the PWM period */
+    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent);
+
+    /* Schedule an event when we reach the pulse width */
+    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent);
+
+    /* Reset the counter when we reach the PWM period */
+    SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent);
+
+    /* Return the period event to the user */
+    *event = periodEvent;
+
+    /* For high-true level */
+    if (pwmParams->level == kSCTIMER_HighTrue)
+    {
+        /* Set the initial output level to low which is the inactive state */
+        base->OUTPUT &= ~(1U << pwmParams->output);
+
+        if (mode == kSCTIMER_EdgeAlignedPwm)
+        {
+            /* Set the output when we reach the PWM period */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent);
+            /* Clear the output when we reach the PWM pulse value */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
+        }
+        else
+        {
+            /* Clear the output when we reach the PWM pulse event */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
+            /* Reverse output when down counting */
+            reg = base->OUTPUTDIRCTRL;
+            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
+            reg |= (1U << (2 * pwmParams->output));
+            base->OUTPUTDIRCTRL = reg;
+        }
+    }
+    /* For low-true level */
+    else
+    {
+        /* Set the initial output level to high which is the inactive state */
+        base->OUTPUT |= (1U << pwmParams->output);
+
+        if (mode == kSCTIMER_EdgeAlignedPwm)
+        {
+            /* Clear the output when we reach the PWM period */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent);
+            /* Set the output when we reach the PWM pulse value */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
+        }
+        else
+        {
+            /* Set the output when we reach the PWM pulse event */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
+            /* Reverse output when down counting */
+            reg = base->OUTPUTDIRCTRL;
+            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
+            reg |= (1U << (2 * pwmParams->output));
+            base->OUTPUTDIRCTRL = reg;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event)
+
+{
+    assert(dutyCyclePercent > 0);
+
+    uint32_t periodMatchReg, pulseMatchReg;
+    uint32_t pulsePeriod = 0, period;
+
+    /* Retrieve the match register number for the PWM period */
+    periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
+
+    /* Retrieve the match register number for the PWM pulse period */
+    pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
+
+    period = base->SCTMATCH[periodMatchReg];
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * dutyCyclePercent) / 100;
+
+    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
+    if (dutyCyclePercent >= 100)
+    {
+        pulsePeriod = period + 2;
+    }
+
+    /* Stop the counter before updating match register */
+    SCTIMER_StopTimer(base, kSCTIMER_Counter_L);
+
+    /* Update dutycycle */
+    base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod);
+    base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod);
+
+    /* Restart the counter */
+    SCTIMER_StartTimer(base, kSCTIMER_Counter_L);
+}
+
+status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
+                                        sctimer_event_t howToMonitor,
+                                        uint32_t matchValue,
+                                        uint32_t whichIO,
+                                        sctimer_counter_t whichCounter,
+                                        uint32_t *event)
+{
+    uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT);
+    uint32_t currentCtrlVal = howToMonitor;
+
+    /* Return an error if we have hit the limit in terms of number of events created */
+    if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
+    {
+        return kStatus_Fail;
+    }
+
+    /* IO only mode */
+    if (combMode == 0x2U)
+    {
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO);
+    }
+    /* Match mode only */
+    else if (combMode == 0x1U)
+    {
+        /* Return an error if we have hit the limit in terms of number of number of match registers */
+        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+        {
+            return kStatus_Fail;
+        }
+
+        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch);
+        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+        {
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
+        }
+        else
+        {
+            /* Select the counter, no need for this if operating in 32-bit mode */
+            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
+        }
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
+        /* Increment the match register number */
+        s_currentMatch++;
+    }
+    /* Use both Match & IO */
+    else
+    {
+        /* Return an error if we have hit the limit in terms of number of number of match registers */
+        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+        {
+            return kStatus_Fail;
+        }
+
+        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO);
+        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+        {
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
+        }
+        else
+        {
+            /* Select the counter, no need for this if operating in 32-bit mode */
+            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
+        }
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
+        /* Increment the match register number */
+        s_currentMatch++;
+    }
+
+    /* Enable the event in the current state */
+    base->EVENT[s_currentEvent].STATE = (1U << s_currentState);
+
+    /* Return the event number */
+    *event = s_currentEvent;
+
+    /* Increment the event number */
+    s_currentEvent++;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event)
+{
+    /* Enable event in the current state */
+    base->EVENT[event].STATE |= (1U << s_currentState);
+}
+
+status_t SCTIMER_IncreaseState(SCT_Type *base)
+{
+    /* Return an error if we have hit the limit in terms of states used */
+    if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES)
+    {
+        return kStatus_Fail;
+    }
+
+    s_currentState++;
+
+    return kStatus_Success;
+}
+
+uint32_t SCTIMER_GetCurrentState(SCT_Type *base)
+{
+    return s_currentState;
+}
+
+void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    uint32_t reg;
+
+    /* Set the same event to set and clear the output */
+    base->OUT[whichIO].CLR |= (1U << event);
+    base->OUT[whichIO].SET |= (1U << event);
+
+    /* Set the conflict resolution to toggle output */
+    reg = base->RES;
+    reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO));
+    reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO));
+    base->RES = reg;
+}
+
+status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
+                                    sctimer_counter_t whichCounter,
+                                    uint32_t *captureRegister,
+                                    uint32_t event)
+{
+    /* Return an error if we have hit the limit in terms of number of capture/match registers used */
+    if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        /* Set the bit to enable event */
+        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event);
+
+        /* Set this resource to be a capture rather than match */
+        base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch);
+    }
+    else
+    {
+        /* Set bit to enable event */
+        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event);
+
+        /* Set this resource to be a capture rather than match */
+        base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch);
+    }
+
+    /* Return the match register number */
+    *captureRegister = s_currentMatch;
+
+    /* Increase the match register number */
+    s_currentMatch++;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event)
+{
+    s_eventCallback[event] = callback;
+}
+
+void SCTIMER_EventHandleIRQ(SCT_Type *base)
+{
+    uint32_t eventFlag = SCT0->EVFLAG;
+    /* Only clear the flags whose interrupt field is enabled */
+    uint32_t clearFlag = (eventFlag & SCT0->EVEN);
+    uint32_t mask = eventFlag;
+    int i = 0;
+
+    /* Invoke the callback for certain events */
+    for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++)
+    {
+        if (mask & 0x1)
+        {
+            if (s_eventCallback[i] != NULL)
+            {
+                s_eventCallback[i]();
+            }
+        }
+        mask >>= 1;
+    }
+
+    /* Clear event interrupt flag */
+    SCT0->EVFLAG = clearFlag;
+}
+
+void SCT0_IRQHandler(void)
+{
+    s_sctimerIsr(SCT0);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_sctimer.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,819 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SCTIMER_H_
+#define _FSL_SCTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sctimer
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief SCTimer PWM operation modes */
+typedef enum _sctimer_pwm_mode
+{
+    kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
+    kSCTIMER_CenterAlignedPwm     /*!< Center-aligned PWM */
+} sctimer_pwm_mode_t;
+
+/*! @brief SCTimer counters when working as two independent 16-bit counters */
+typedef enum _sctimer_counter
+{
+    kSCTIMER_Counter_L = 0U, /*!< Counter L */
+    kSCTIMER_Counter_H       /*!< Counter H */
+} sctimer_counter_t;
+
+/*! @brief List of SCTimer input pins */
+typedef enum _sctimer_input
+{
+    kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */
+    kSCTIMER_Input_1,      /*!< SCTIMER input 1 */
+    kSCTIMER_Input_2,      /*!< SCTIMER input 2 */
+    kSCTIMER_Input_3,      /*!< SCTIMER input 3 */
+    kSCTIMER_Input_4,      /*!< SCTIMER input 4 */
+    kSCTIMER_Input_5,      /*!< SCTIMER input 5 */
+    kSCTIMER_Input_6,      /*!< SCTIMER input 6 */
+    kSCTIMER_Input_7       /*!< SCTIMER input 7 */
+} sctimer_input_t;
+
+/*! @brief List of SCTimer output pins */
+typedef enum _sctimer_out
+{
+    kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/
+    kSCTIMER_Out_1,      /*!< SCTIMER output 1 */
+    kSCTIMER_Out_2,      /*!< SCTIMER output 2 */
+    kSCTIMER_Out_3,      /*!< SCTIMER output 3 */
+    kSCTIMER_Out_4,      /*!< SCTIMER output 4 */
+    kSCTIMER_Out_5,      /*!< SCTIMER output 5 */
+    kSCTIMER_Out_6,      /*!< SCTIMER output 6 */
+    kSCTIMER_Out_7       /*!< SCTIMER output 7 */
+} sctimer_out_t;
+
+/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */
+typedef enum _sctimer_pwm_level_select
+{
+    kSCTIMER_LowTrue = 0U, /*!< Low true pulses */
+    kSCTIMER_HighTrue      /*!< High true pulses */
+} sctimer_pwm_level_select_t;
+
+/*! @brief Options to configure a SCTimer PWM signal */
+typedef struct _sctimer_pwm_signal_param
+{
+    sctimer_out_t output;             /*!< The output pin to use to generate the PWM signal */
+    sctimer_pwm_level_select_t level; /*!< PWM output active level select. */
+    uint8_t dutyCyclePercent;         /*!< PWM pulse width, value should be between 1 to 100
+                                           100 = always active signal (100% duty cycle).*/
+} sctimer_pwm_signal_param_t;
+
+/*! @brief SCTimer clock mode options */
+typedef enum _sctimer_clock_mode
+{
+    kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */
+    kSCTIMER_Sampled_ClockMode,     /*!< Sampled System Clock Mode */
+    kSCTIMER_Input_ClockMode,       /*!< SCT Input Clock Mode */
+    kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */
+} sctimer_clock_mode_t;
+
+/*! @brief SCTimer clock select options */
+typedef enum _sctimer_clock_select
+{
+    kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */
+    kSCTIMER_Clock_On_Fall_Input_0,      /*!< Falling edges on input 0 */
+    kSCTIMER_Clock_On_Rise_Input_1,      /*!< Rising edges on input 1 */
+    kSCTIMER_Clock_On_Fall_Input_1,      /*!< Falling edges on input 1 */
+    kSCTIMER_Clock_On_Rise_Input_2,      /*!< Rising edges on input 2 */
+    kSCTIMER_Clock_On_Fall_Input_2,      /*!< Falling edges on input 2 */
+    kSCTIMER_Clock_On_Rise_Input_3,      /*!< Rising edges on input 3 */
+    kSCTIMER_Clock_On_Fall_Input_3,      /*!< Falling edges on input 3 */
+    kSCTIMER_Clock_On_Rise_Input_4,      /*!< Rising edges on input 4 */
+    kSCTIMER_Clock_On_Fall_Input_4,      /*!< Falling edges on input 4 */
+    kSCTIMER_Clock_On_Rise_Input_5,      /*!< Rising edges on input 5 */
+    kSCTIMER_Clock_On_Fall_Input_5,      /*!< Falling edges on input 5 */
+    kSCTIMER_Clock_On_Rise_Input_6,      /*!< Rising edges on input 6 */
+    kSCTIMER_Clock_On_Fall_Input_6,      /*!< Falling edges on input 6 */
+    kSCTIMER_Clock_On_Rise_Input_7,      /*!< Rising edges on input 7 */
+    kSCTIMER_Clock_On_Fall_Input_7       /*!< Falling edges on input 7 */
+} sctimer_clock_select_t;
+
+/*!
+ * @brief SCTimer output conflict resolution options.
+ *
+ * Specifies what action should be taken if multiple events dictate that a given output should be
+ * both set and cleared at the same time
+ */
+typedef enum _sctimer_conflict_resolution
+{
+    kSCTIMER_ResolveNone = 0U, /*!< No change */
+    kSCTIMER_ResolveSet,       /*!< Set output */
+    kSCTIMER_ResolveClear,     /*!< Clear output */
+    kSCTIMER_ResolveToggle     /*!< Toggle output */
+} sctimer_conflict_resolution_t;
+
+/*! @brief List of SCTimer event types */
+typedef enum _sctimer_event
+{
+    kSCTIMER_InputLowOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_MatchEventOnly =
+        (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_InputLowEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_InputLowAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT)
+} sctimer_event_t;
+
+/*! @brief SCTimer callback typedef. */
+typedef void (*sctimer_event_callback_t)(void);
+
+/*! @brief List of SCTimer interrupts */
+typedef enum _sctimer_interrupt_enable
+{
+    kSCTIMER_Event0InterruptEnable = (1U << 0),   /*!< Event 0 interrupt */
+    kSCTIMER_Event1InterruptEnable = (1U << 1),   /*!< Event 1 interrupt */
+    kSCTIMER_Event2InterruptEnable = (1U << 2),   /*!< Event 2 interrupt */
+    kSCTIMER_Event3InterruptEnable = (1U << 3),   /*!< Event 3 interrupt */
+    kSCTIMER_Event4InterruptEnable = (1U << 4),   /*!< Event 4 interrupt */
+    kSCTIMER_Event5InterruptEnable = (1U << 5),   /*!< Event 5 interrupt */
+    kSCTIMER_Event6InterruptEnable = (1U << 6),   /*!< Event 6 interrupt */
+    kSCTIMER_Event7InterruptEnable = (1U << 7),   /*!< Event 7 interrupt */
+    kSCTIMER_Event8InterruptEnable = (1U << 8),   /*!< Event 8 interrupt */
+    kSCTIMER_Event9InterruptEnable = (1U << 9),   /*!< Event 9 interrupt */
+    kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */
+    kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */
+    kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */
+} sctimer_interrupt_enable_t;
+
+/*! @brief List of SCTimer flags */
+typedef enum _sctimer_status_flags
+{
+    kSCTIMER_Event0Flag = (1U << 0),   /*!< Event 0 Flag */
+    kSCTIMER_Event1Flag = (1U << 1),   /*!< Event 1 Flag */
+    kSCTIMER_Event2Flag = (1U << 2),   /*!< Event 2 Flag */
+    kSCTIMER_Event3Flag = (1U << 3),   /*!< Event 3 Flag */
+    kSCTIMER_Event4Flag = (1U << 4),   /*!< Event 4 Flag */
+    kSCTIMER_Event5Flag = (1U << 5),   /*!< Event 5 Flag */
+    kSCTIMER_Event6Flag = (1U << 6),   /*!< Event 6 Flag */
+    kSCTIMER_Event7Flag = (1U << 7),   /*!< Event 7 Flag */
+    kSCTIMER_Event8Flag = (1U << 8),   /*!< Event 8 Flag */
+    kSCTIMER_Event9Flag = (1U << 9),   /*!< Event 9 Flag */
+    kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */
+    kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */
+    kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */
+    kSCTIMER_BusErrorLFlag =
+        (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */
+    kSCTIMER_BusErrorHFlag =
+        (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */
+} sctimer_status_flags_t;
+
+/*!
+ * @brief SCTimer configuration structure
+ *
+ * This structure holds the configuration settings for the SCTimer peripheral. To initialize this
+ * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _sctimer_config
+{
+    bool enableCounterUnify;            /*!< true: SCT operates as a unified 32-bit counter;
+                                             false: SCT operates as two 16-bit counters */
+    sctimer_clock_mode_t clockMode;     /*!< SCT clock mode value */
+    sctimer_clock_select_t clockSelect; /*!< SCT clock select value */
+    bool enableBidirection_l;           /*!< true: Up-down count mode for the L or unified counter
+                                             false: Up count mode only for the L or unified counter */
+    bool enableBidirection_h;           /*!< true: Up-down count mode for the H or unified counter
+                                             false: Up count mode only for the H or unified counter.
+                                             This field is used only if the enableCounterUnify is set
+                                             to false */
+    uint8_t prescale_l;                 /*!< Prescale value to produce the L or unified counter clock */
+    uint8_t prescale_h;                 /*!< Prescale value to produce the H counter clock.
+                                             This field is used only if the enableCounterUnify is set
+                                             to false */
+    uint8_t outInitState;               /*!< Defines the initial output value */
+} sctimer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the SCTimer clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the SCTimer driver.
+ *
+ * @param base   SCTimer peripheral base address
+ * @param config Pointer to the user configuration structure.
+ *
+ * @return kStatus_Success indicates success; Else indicates failure.
+ */
+status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config);
+
+/*!
+ * @brief Gates the SCTimer clock.
+ *
+ * @param base SCTimer peripheral base address
+ */
+void SCTIMER_Deinit(SCT_Type *base);
+
+/*!
+ * @brief  Fills in the SCTimer configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ *  config->enableCounterUnify = true;
+ *  config->clockMode = kSCTIMER_System_ClockMode;
+ *  config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
+ *  config->enableBidirection_l = false;
+ *  config->enableBidirection_h = false;
+ *  config->prescale_l = 0;
+ *  config->prescale_h = 0;
+ *  config->outInitState = 0;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void SCTIMER_GetDefaultConfig(sctimer_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name PWM setup operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This
+ * function will create 2 events; one of the events will trigger on match with the pulse value
+ * and the other will trigger when the counter matches the PWM period. The PWM period event is
+ * also used as a limit event to reset the counter or change direction. Both events are enabled
+ * for the same state. The state number can be retrieved by calling the function
+ * SCTIMER_GetCurrentStateNumber().
+ * The counter is set to operate as one 32-bit counter (unify bit is set to 1).
+ * The counter operates in bi-directional mode when generating a center-aligned PWM.
+ *
+ * @note When setting PWM output from multiple output pins, they all should use the same PWM mode
+ * i.e all PWM's should be either edge-aligned or center-aligned.
+ *
+ * @param base        SCTimer peripheral base address
+ * @param pwmParams   PWM parameters to configure the output
+ * @param mode        PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t
+ * @param pwmFreq_Hz  PWM signal frequency in Hz
+ * @param srcClock_Hz SCTimer counter clock in Hz
+ * @param event       Pointer to a variable where the PWM period event number is stored
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If we have hit the limit in terms of number of events created or if
+ *                      an incorrect PWM dutycylce is passed in.
+ */
+status_t SCTIMER_SetupPwm(SCT_Type *base,
+                          const sctimer_pwm_signal_param_t *pwmParams,
+                          sctimer_pwm_mode_t mode,
+                          uint32_t pwmFreq_Hz,
+                          uint32_t srcClock_Hz,
+                          uint32_t *event);
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base              SCTimer peripheral base address
+ * @param output            The output to configure
+ * @param dutyCyclePercent  New PWM pulse width; the value should be between 1 to 100
+ * @param event             Event number associated with this PWM signal. This was returned to the user by the
+ *                          function SCTIMER_SetupPwm().
+ */
+void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event);
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::sctimer_interrupt_enable_t
+ */
+static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask)
+{
+    base->EVEN |= mask;
+}
+
+/*!
+ * @brief Disables the selected SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::sctimer_interrupt_enable_t
+ */
+static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask)
+{
+    base->EVEN &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::sctimer_interrupt_enable_t
+ */
+static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base)
+{
+    return (base->EVEN & 0xFFFFU);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the SCTimer status flags.
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::sctimer_status_flags_t
+ */
+static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base)
+{
+    uint32_t statusFlags = 0;
+
+    /* Add the recorded events */
+    statusFlags = (base->EVFLAG & 0xFFFFU);
+
+    /* Add bus error flags */
+    statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
+
+    return statusFlags;
+}
+
+/*!
+ * @brief Clears the SCTimer status flags.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::sctimer_status_flags_t
+ */
+static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask)
+{
+    /* Write to the flag registers */
+    base->EVFLAG = (mask & 0xFFFFU);
+    base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Counter Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the SCTimer counter.
+ *
+ * @param base           SCTimer peripheral base address
+ * @param countertoStart SCTimer counter to start; if unify mode is set then function always
+ *                       writes to HALT_L bit
+ */
+static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart)
+{
+    /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L))
+    {
+        base->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
+    }
+    else
+    {
+        /* Start H counter */
+        base->CTRL &= ~(SCT_CTRL_HALT_H_MASK);
+    }
+}
+
+/*!
+ * @brief Halts the SCTimer counter.
+ *
+ * @param base          SCTimer peripheral base address
+ * @param countertoStop SCTimer counter to stop; if unify mode is set then function always
+ *                      writes to HALT_L bit
+ */
+static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop)
+{
+    /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L))
+    {
+        base->CTRL |= (SCT_CTRL_HALT_L_MASK);
+    }
+    else
+    {
+        /* Stop H counter */
+        base->CTRL |= (SCT_CTRL_HALT_H_MASK);
+    }
+}
+
+/*! @}*/
+
+/*!
+ * @name Functions to create a new event and manage the state logic
+ * @{
+ */
+
+/*!
+ * @brief Create an event that is triggered on a match or IO and schedule in current state.
+ *
+ * This function will configure an event using the options provided by the user. If the event type uses
+ * the counter match, then the function will set the user provided match value into a match register
+ * and put this match register number into the event control register.
+ * The event is enabled for the current state and the event number is increased by one at the end.
+ * The function returns the event number; this event number can be used to configure actions to be
+ * done when this event is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t
+ * @param matchValue   The match value that will be programmed to a match register
+ * @param whichIO      The input or output that will be involved in event triggering. This field
+ *                     is ignored if the event type is "match only"
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as we have only 1 unified counter; hence ignored.
+ * @param event        Pointer to a variable where the new event number is stored
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of number of events created or
+                         if we have reached the limit in terms of number of match registers
+ */
+status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
+                                        sctimer_event_t howToMonitor,
+                                        uint32_t matchValue,
+                                        uint32_t whichIO,
+                                        sctimer_counter_t whichCounter,
+                                        uint32_t *event);
+
+/*!
+ * @brief Enable an event in the current state.
+ *
+ * This function will allow the event passed in to trigger in the current state. The event must
+ * be created earlier by either calling the function SCTIMER_SetupPwm() or function
+ * SCTIMER_CreateAndScheduleEvent() .
+ *
+ * @param base  SCTimer peripheral base address
+ * @param event Event number to enable in the current state
+ *
+ */
+void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event);
+
+/*!
+ * @brief Increase the state by 1
+ *
+ * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new
+ * state.
+ *
+ * @param base  SCTimer peripheral base address
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of states used
+
+ */
+status_t SCTIMER_IncreaseState(SCT_Type *base);
+
+/*!
+ * @brief Provides the current state
+ *
+ * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction().
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The current state
+ */
+uint32_t SCTIMER_GetCurrentState(SCT_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Actions to take in response to an event
+ * @{
+ */
+
+/*!
+ * @brief Setup capture of the counter value on trigger of a selected event
+ *
+ * @param base            SCTimer peripheral base address
+ * @param whichCounter    SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                        field has no meaning as only the Counter_L bits are used.
+ * @param captureRegister Pointer to a variable where the capture register number will be returned. User
+ *                        can read the captured value from this register when the specified event is triggered.
+ * @param event           Event number that will trigger the capture
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of number of match/capture registers available
+ */
+status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
+                                    sctimer_counter_t whichCounter,
+                                    uint32_t *captureRegister,
+                                    uint32_t event);
+
+/*!
+ * @brief Receive noticification when the event trigger an interrupt.
+ *
+ * If the interrupt for the event is enabled by the user, then a callback can be registered
+ * which will be invoked when the event is triggered
+ *
+ * @param base     SCTimer peripheral base address
+ * @param event    Event number that will trigger the interrupt
+ * @param callback Function to invoke when the event is triggered
+ */
+
+void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event);
+
+/*!
+ * @brief Transition to the specified state.
+ *
+ * This transition will be triggered by the event number that is passed in by the user.
+ *
+ * @param base      SCTimer peripheral base address
+ * @param nextState The next state SCTimer will transition to
+ * @param event     Event number that will trigger the state transition
+ */
+static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event)
+{
+    uint32_t reg = base->EVENT[event].CTRL;
+
+    reg &= ~(SCT_EVENT_CTRL_STATEV_MASK);
+    /* Load the STATEV value when the event occurs to be the next state */
+    reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK;
+
+    base->EVENT[event].CTRL = reg;
+}
+
+/*!
+ * @brief Set the Output.
+ *
+ * This output will be set when the event number that is passed in by the user is triggered.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to set
+ * @param event   Event number that will trigger the output change
+ */
+static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    base->OUT[whichIO].SET |= (1U << event);
+}
+
+/*!
+ * @brief Clear the Output.
+ *
+ * This output will be cleared when the event number that is passed in by the user is triggered.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to clear
+ * @param event   Event number that will trigger the output change
+ */
+static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    base->OUT[whichIO].CLR |= (1U << event);
+}
+
+/*!
+ * @brief Toggle the output level.
+ *
+ * This change in the output level is triggered by the event number that is passed in by the user.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to toggle
+ * @param event   Event number that will trigger the output change
+ */
+void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event);
+
+/*!
+ * @brief Limit the running counter.
+ *
+ * The counter is limited when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be limited
+ */
+static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event);
+    }
+    else
+    {
+        base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Stop the running counter.
+ *
+ * The counter is stopped when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be stopped
+ */
+static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->STOP |= SCT_STOP_STOPMSK_L(1U << event);
+    }
+    else
+    {
+        base->STOP |= SCT_STOP_STOPMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Re-start the stopped counter.
+ *
+ * The counter will re-start when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to re-start
+ */
+static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->START |= SCT_START_STARTMSK_L(1U << event);
+    }
+    else
+    {
+        base->START |= SCT_START_STARTMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Halt the running counter.
+ *
+ * The counter is disabled (halted) when the event number that is passed in by the user is
+ * triggered. When the counter is halted, all further events are disabled. The HALT condition
+ * can only be removed by calling the SCTIMER_StartTimer() function.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be halted
+ */
+static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->HALT |= SCT_HALT_HALTMSK_L(1U << event);
+    }
+    else
+    {
+        base->HALT |= SCT_HALT_HALTMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Generate a DMA request.
+ *
+ * DMA request will be triggered by the event number that is passed in by the user.
+ *
+ * @param base      SCTimer peripheral base address
+ * @param dmaNumber The DMA request to generate
+ * @param event     Event number that will trigger the DMA request
+ */
+static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event)
+{
+    if (dmaNumber == 0)
+    {
+        base->DMA0REQUEST |= (1U << event);
+    }
+    else
+    {
+        base->DMA1REQUEST |= (1U << event);
+    }
+}
+
+/*!
+ * @brief SCTimer interrupt handler.
+ *
+ * @param base SCTimer peripheral base address.
+ */
+void SCTIMER_EventHandleIRQ(SCT_Type *base);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SCTIMER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_spi.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,688 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spi.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+/* Note:  FIFOCFG[SIZE] has always value 1 = 8 items depth */
+#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3)
+
+/* Convert transfer count to transfer bytes. dataWidth is a
+ * range <0,15>. Range <8,15> represents 2B transfer */
+#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U))
+#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U))
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief internal SPI config array */
+static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0};
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_spiIRQ[] = SPI_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void *SPI_GetConfig(SPI_Type *base)
+{
+    int32_t instance;
+    instance = FLEXCOMM_GetInstance(base);
+    if (instance < 0)
+    {
+        return NULL;
+    }
+    return &g_configs[instance];
+}
+
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableLoopback = false;
+    config->enableMaster = true;
+    config->polarity = kSPI_ClockPolarityActiveHigh;
+    config->phase = kSPI_ClockPhaseFirstEdge;
+    config->direction = kSPI_MsbFirst;
+    config->baudRate_Bps = 500000U;
+    config->dataWidth = kSPI_Data8Bits;
+    config->sselNum = kSPI_Ssel0;
+    config->txWatermark = kSPI_TxFifo0;
+    config->rxWatermark = kSPI_RxFifo1;
+}
+
+status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz)
+{
+    int32_t result = 0, instance = 0;
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to SPI mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
+    assert(kStatus_Success == result);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    /* set divider */
+    result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+    /* get instance number */
+    instance = FLEXCOMM_GetInstance(base);
+    assert(instance >= 0);
+
+    /* store configuration */
+    g_configs[instance].dataWidth = config->dataWidth;
+    g_configs[instance].sselNum = config->sselNum;
+    /* enable FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
+    /* trigger level - empty txFIFO, one item in rxFIFO */
+    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
+    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
+    /* enable generating interrupts for FIFOTRIG levels */
+    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
+    /* set FIFOTRIG */
+    base->FIFOTRIG = tmp;
+    /* configure SPI mode */
+    tmp = base->CFG;
+    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK);
+    /* phase */
+    tmp |= SPI_CFG_CPHA(config->phase);
+    /* polarity */
+    tmp |= SPI_CFG_CPOL(config->polarity);
+    /* direction */
+    tmp |= SPI_CFG_LSBF(config->direction);
+    /* master mode */
+    tmp |= SPI_CFG_MASTER(1);
+    /* loopback */
+    tmp |= SPI_CFG_LOOP(config->enableLoopback);
+    base->CFG = tmp;
+    SPI_Enable(base, config->enableMaster);
+    return kStatus_Success;
+}
+
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableSlave = true;
+    config->polarity = kSPI_ClockPolarityActiveHigh;
+    config->phase = kSPI_ClockPhaseFirstEdge;
+    config->direction = kSPI_MsbFirst;
+    config->dataWidth = kSPI_Data8Bits;
+    config->txWatermark = kSPI_TxFifo0;
+    config->rxWatermark = kSPI_RxFifo1;
+}
+
+status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config)
+{
+    int32_t result = 0, instance;
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (NULL == config)));
+    if ((NULL == base) || (NULL == config))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* configure flexcomm to SPI, enable clock gate */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
+    assert(kStatus_Success == result);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    instance = FLEXCOMM_GetInstance(base);
+
+    /* store configuration */
+    g_configs[instance].dataWidth = config->dataWidth;
+    /* empty and enable FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
+    /* trigger level - empty txFIFO, one item in rxFIFO */
+    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
+    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
+    /* enable generating interrupts for FIFOTRIG levels */
+    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
+    /* set FIFOTRIG */
+    base->FIFOTRIG = tmp;
+    /* configure SPI mode */
+    tmp = base->CFG;
+    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK);
+    /* phase */
+    tmp |= SPI_CFG_CPHA(config->phase);
+    /* polarity */
+    tmp |= SPI_CFG_CPOL(config->polarity);
+    /* direction */
+    tmp |= SPI_CFG_LSBF(config->direction);
+    base->CFG = tmp;
+    SPI_Enable(base, config->enableSlave);
+    return kStatus_Success;
+}
+
+void SPI_Deinit(SPI_Type *base)
+{
+    /* Assert arguments */
+    assert(NULL != base);
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK |
+                         SPI_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(SPI_CFG_ENABLE_MASK);
+}
+
+void SPI_EnableTxDMA(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK;
+    }
+}
+
+void SPI_EnableRxDMA(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK;
+    }
+}
+
+status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* calculate baudrate */
+    tmp = (srcClock_Hz / baudrate_Bps) - 1;
+    if (tmp > 0xFFFF)
+    {
+        return kStatus_SPI_BaudrateNotSupport;
+    }
+    base->DIV &= ~SPI_DIV_DIVVAL_MASK;
+    base->DIV |= SPI_DIV_DIVVAL(tmp);
+    return kStatus_Success;
+}
+
+void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags)
+{
+    uint32_t control = 0;
+    int32_t instance;
+
+    /* check params */
+    assert(NULL != base);
+    /* get and check instance */
+    instance = FLEXCOMM_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return;
+    }
+
+    /* set data width */
+    control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth);
+    /* set sssel */
+    control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
+    /* mask configFlags */
+    control |= (configFlags & SPI_FIFOWR_FLAGS_MASK);
+    /* control should not affect lower 16 bits */
+    assert(!(control & 0xFFFF));
+    base->FIFOWR = data | control;
+}
+
+status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                        spi_master_handle_t *handle,
+                                        spi_master_callback_t callback,
+                                        void *userData)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* get flexcomm instance by 'base' param */
+    instance = FLEXCOMM_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    /* Initialize the handle */
+    if (base->CFG & SPI_CFG_MASTER_MASK)
+    {
+        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_MasterTransferHandleIRQ, handle);
+    }
+    else
+    {
+        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_SlaveTransferHandleIRQ, handle);
+    }
+
+    handle->dataWidth = g_configs[instance].dataWidth;
+    /* in slave mode, the sselNum is not important */
+    handle->sselNum = g_configs[instance].sselNum;
+    handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base);
+    handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base);
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable SPI NVIC */
+    EnableIRQ(s_spiIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer)
+{
+    int32_t instance;
+    uint32_t tx_ctrl = 0, last_ctrl = 0;
+    uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth;
+    uint32_t toReceiveCount = 0;
+    uint8_t *txData, *rxData;
+    uint32_t fifoDepth;
+
+    /* check params */
+    assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
+    if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    fifoDepth = SPI_FIFO_DEPTH(base);
+    txData = xfer->txData;
+    rxData = xfer->rxData;
+    txRemainingBytes = txData ? xfer->dataSize : 0;
+    rxRemainingBytes = rxData ? xfer->dataSize : 0;
+
+    instance = FLEXCOMM_GetInstance(base);
+    assert(instance >= 0);
+    dataWidth = g_configs[instance].dataWidth;
+
+    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
+    assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
+    if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* clear tx/rx errors and empty FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
+    /* select slave to talk with */
+    tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
+    /* set width of data - range asserted at entry */
+    tx_ctrl |= SPI_FIFOWR_LEN(dataWidth);
+    /* end of transfer */
+    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
+    /* delay end of transfer */
+    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
+    /* last index of loop */
+    while (txRemainingBytes || rxRemainingBytes || toReceiveCount)
+    {
+        /* if rxFIFO is not empty */
+        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+        {
+            tmp32 = base->FIFORD;
+            /* rxBuffer is not empty */
+            if (rxRemainingBytes)
+            {
+                *(rxData++) = tmp32;
+                rxRemainingBytes--;
+                /* read 16 bits at once */
+                if (dataWidth > 8)
+                {
+                    *(rxData++) = tmp32 >> 8;
+                    rxRemainingBytes--;
+                }
+            }
+            /* decrease number of data expected to receive */
+            toReceiveCount -= 1;
+        }
+        /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */
+        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) &&
+            ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))))
+        {
+            /* txBuffer is not empty */
+            if (txRemainingBytes)
+            {
+                tmp32 = *(txData++);
+                txRemainingBytes--;
+                /* write 16 bit at once */
+                if (dataWidth > 8)
+                {
+                    tmp32 |= ((uint32_t)(*(txData++))) << 8U;
+                    txRemainingBytes--;
+                }
+                if (!txRemainingBytes)
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            else
+            {
+                tmp32 = SPI_DUMMYDATA;
+                /* last transfer */
+                if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            /* send data */
+            tmp32 = tx_ctrl | tmp32;
+            base->FIFOWR = tmp32;
+            toReceiveCount += 1;
+        }
+    }
+    /* wait if TX FIFO of previous transfer is not empty */
+    while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK))
+    {
+    }
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer)
+{
+    /* check params */
+    assert(
+        !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
+    assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
+    if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check if SPI is busy */
+    if (handle->state == kStatus_SPI_Busy)
+    {
+        return kStatus_SPI_Busy;
+    }
+
+    /* Set the handle information */
+    handle->txData = xfer->txData;
+    handle->rxData = xfer->rxData;
+    /* set count */
+    handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0;
+    handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0;
+    handle->totalByteCount = xfer->dataSize;
+    /* other options */
+    handle->toReceiveCount = 0;
+    handle->configFlags = xfer->configFlags;
+    /* Set the SPI state to busy */
+    handle->state = kStatus_SPI_Busy;
+    /* clear FIFOs when transfer starts */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
+    /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */
+    base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK;
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count)
+{
+    assert(NULL != handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kStatus_SPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->totalByteCount - handle->rxRemainingBytes;
+    return kStatus_Success;
+}
+
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupt requests*/
+    base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK);
+    /* Empty FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+
+    handle->state = kStatus_SPI_Idle;
+    handle->txRemainingBytes = 0;
+    handle->rxRemainingBytes = 0;
+}
+
+static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle)
+{
+    uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32;
+    bool loopContinue;
+    uint32_t fifoDepth;
+
+    /* check params */
+    assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData)));
+
+    fifoDepth = SPI_FIFO_DEPTH(base);
+    /* select slave to talk with */
+    tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum));
+    /* set width of data */
+    tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth);
+    /* end of transfer */
+    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
+    /* delay end of transfer */
+    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
+    do
+    {
+        loopContinue = false;
+
+        /* rxFIFO is not empty */
+        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+        {
+            tmp32 = base->FIFORD;
+            /* rxBuffer is not empty */
+            if (handle->rxRemainingBytes)
+            {
+                /* low byte must go first */
+                *(handle->rxData++) = tmp32;
+                handle->rxRemainingBytes--;
+                /* read 16 bits at once */
+                if (handle->dataWidth > kSPI_Data8Bits)
+                {
+                    *(handle->rxData++) = tmp32 >> 8;
+                    handle->rxRemainingBytes--;
+                }
+            }
+            /* decrease number of data expected to receive */
+            handle->toReceiveCount -= 1;
+            loopContinue = true;
+        }
+
+        /* - txFIFO is not full
+         * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO
+         * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer
+         */
+        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) &&
+            ((handle->txRemainingBytes) ||
+             (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))))
+        {
+            /* txBuffer is not empty */
+            if (handle->txRemainingBytes)
+            {
+                /* low byte must go first */
+                tmp32 = *(handle->txData++);
+                handle->txRemainingBytes--;
+                /* write 16 bit at once */
+                if (handle->dataWidth > kSPI_Data8Bits)
+                {
+                    tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U;
+                    handle->txRemainingBytes--;
+                }
+                /* last transfer */
+                if (!handle->txRemainingBytes)
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            else
+            {
+                tmp32 = SPI_DUMMYDATA;
+                /* last transfer */
+                if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            /* send data */
+            tmp32 = tx_ctrl | tmp32;
+            base->FIFOWR = tmp32;
+            /* increase number of expected data to receive */
+            handle->toReceiveCount += 1;
+            loopContinue = true;
+        }
+    } while (loopContinue);
+}
+
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert((NULL != base) && (NULL != handle));
+
+    /* IRQ behaviour:
+     * - first interrupt is triggered by empty txFIFO. The transfer function
+     *   then tries empty rxFIFO and fill txFIFO interleaved that results to
+     *   strategy to process as many items as possible.
+     * - the next IRQs can be:
+     *      rxIRQ from nonempty rxFIFO which requires to empty rxFIFO.
+     *      txIRQ from empty txFIFO which requires to refill txFIFO.
+     * - last interrupt is triggered by empty txFIFO. The last state is
+     *   known by empty rxBuffer and txBuffer. If there is nothing to receive
+     *   or send - both operations have been finished and interrupts can be
+     *   disabled.
+     */
+
+    /* Data to send or read or expected to receive */
+    if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount))
+    {
+        /* Transmit or receive data */
+        SPI_TransferHandleIRQInternal(base, handle);
+        /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and
+         * enable txIRQ to confirm when txFIFO becomes empty */
+        if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount))
+        {
+            base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK);
+            base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK;
+        }
+        else
+        {
+            uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes);
+            /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data,
+             * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */
+            if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount))
+            {
+                base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK;
+            }
+            /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel.
+             * Cannot clear rxFIFO, txFIFO might be still active */
+            if (rxRemainingCount == 0)
+            {
+                if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) &&
+                    (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1))
+                {
+                    base->FIFOTRIG =
+                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1);
+                }
+            }
+            /* Expected to receive less data than rxLevel value, we have to update rxLevel */
+            else
+            {
+                if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1))
+                {
+                    base->FIFOTRIG =
+                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1);
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */
+        base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK;
+        base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) |
+                         SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark);
+        /* set idle state and call user callback */
+        handle->state = kStatus_SPI_Idle;
+        if (handle->callback)
+        {
+            (handle->callback)(base, handle, handle->state, handle->userData);
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_spi.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,625 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used tom  endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPI_H_
+#define _FSL_SPI_H_
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*!
+ * @addtogroup spi_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.0.0. */
+#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define SPI_DUMMYDATA (0xFFFF)
+#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF)
+#define SPI_CTRLMASK (0xFFFF0000)
+
+#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000)
+#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16))
+#define SPI_DEASSERT_ALL (0xF0000)
+
+#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK))
+
+#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT)
+#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief SPI transfer option.*/
+typedef enum _spi_xfer_option {
+    kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK),  /*!< Delay chip select */
+    kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */
+} spi_xfer_option_t;
+
+/*! @brief SPI data shifter direction options.*/
+typedef enum _spi_shift_direction {
+    kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
+    kSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit. */
+} spi_shift_direction_t;
+
+/*! @brief SPI clock polarity configuration.*/
+typedef enum _spi_clock_polarity {
+    kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
+    kSPI_ClockPolarityActiveLow          /*!< Active-low SPI clock (idles high). */
+} spi_clock_polarity_t;
+
+/*! @brief SPI clock phase configuration.*/
+typedef enum _spi_clock_phase {
+    kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
+                                         *   cycle of a data transfer. */
+    kSPI_ClockPhaseSecondEdge        /*!< First edge on SCK occurs at the start of the
+                                         *   first cycle of a data transfer. */
+} spi_clock_phase_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _spi_txfifo_watermark {
+    kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */
+    kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */
+    kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */
+    kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */
+    kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */
+    kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */
+    kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */
+    kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */
+} spi_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _spi_rxfifo_watermark {
+    kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */
+    kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */
+    kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */
+    kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */
+    kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */
+    kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */
+    kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */
+    kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */
+} spi_rxfifo_watermark_t;
+
+/*! @brief Transfer data width */
+typedef enum _spi_data_width {
+    kSPI_Data4Bits = 3,   /*!< 4 bits data width */
+    kSPI_Data5Bits = 4,   /*!< 5 bits data width */
+    kSPI_Data6Bits = 5,   /*!< 6 bits data width */
+    kSPI_Data7Bits = 6,   /*!< 7 bits data width */
+    kSPI_Data8Bits = 7,   /*!< 8 bits data width */
+    kSPI_Data9Bits = 8,   /*!< 9 bits data width */
+    kSPI_Data10Bits = 9,  /*!< 10 bits data width */
+    kSPI_Data11Bits = 10, /*!< 11 bits data width */
+    kSPI_Data12Bits = 11, /*!< 12 bits data width */
+    kSPI_Data13Bits = 12, /*!< 13 bits data width */
+    kSPI_Data14Bits = 13, /*!< 14 bits data width */
+    kSPI_Data15Bits = 14, /*!< 15 bits data width */
+    kSPI_Data16Bits = 15, /*!< 16 bits data width */
+} spi_data_width_t;
+
+/*! @brief Slave select */
+typedef enum _spi_ssel {
+    kSPI_Ssel0 = 0, /*!< Slave select 0 */
+    kSPI_Ssel1 = 1, /*!< Slave select 1 */
+    kSPI_Ssel2 = 2, /*!< Slave select 2 */
+    kSPI_Ssel3 = 3, /*!< Slave select 3 */
+} spi_ssel_t;
+
+/*! @brief SPI master user configure structure.*/
+typedef struct _spi_master_config
+{
+    bool enableLoopback;                /*!< Enable loopback for test purpose */
+    bool enableMaster;                  /*!< Enable SPI at initialization time */
+    spi_clock_polarity_t polarity;      /*!< Clock polarity */
+    spi_clock_phase_t phase;            /*!< Clock phase */
+    spi_shift_direction_t direction;    /*!< MSB or LSB */
+    uint32_t baudRate_Bps;              /*!< Baud Rate for SPI in Hz */
+    spi_data_width_t dataWidth;         /*!< Width of the data */
+    spi_ssel_t sselNum;                 /*!< Slave select number */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} spi_master_config_t;
+
+/*! @brief SPI slave user configure structure.*/
+typedef struct _spi_slave_config
+{
+    bool enableSlave;                   /*!< Enable SPI at initialization time */
+    spi_clock_polarity_t polarity;      /*!< Clock polarity */
+    spi_clock_phase_t phase;            /*!< Clock phase */
+    spi_shift_direction_t direction;    /*!< MSB or LSB */
+    spi_data_width_t dataWidth;         /*!< Width of the data */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} spi_slave_config_t;
+
+/*! @brief SPI transfer status.*/
+enum _spi_status
+{
+    kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0),  /*!< SPI bus is busy */
+    kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1),  /*!< SPI is idle */
+    kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI  error */
+    kStatus_SPI_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief SPI interrupt sources.*/
+enum _spi_interrupt_enable
+{
+    kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */
+    kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */
+};
+
+/*! @brief SPI status flags.*/
+enum _spi_statusflags
+{
+    kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK,       /*!< txFifo is empty */
+    kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK,   /*!< txFifo is not full */
+    kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */
+    kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK,         /*!< rxFIFO is full */
+};
+
+/*! @brief SPI transfer structure */
+typedef struct _spi_transfer
+{
+    uint8_t *txData;      /*!< Send buffer */
+    uint8_t *rxData;      /*!< Receive buffer */
+    uint32_t configFlags; /*!< Additional option to control transfer */
+    size_t dataSize;      /*!< Transfer bytes */
+} spi_transfer_t;
+
+/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
+typedef struct _spi_config
+{
+    spi_data_width_t dataWidth;
+    spi_ssel_t sselNum;
+} spi_config_t;
+
+/*! @brief  Master handle type */
+typedef struct _spi_master_handle spi_master_handle_t;
+
+/*! @brief  Slave handle type */
+typedef spi_master_handle_t spi_slave_handle_t;
+
+/*! @brief SPI master callback for finished transmit */
+typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI slave callback for finished transmit */
+typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI transfer handle structure */
+struct _spi_master_handle
+{
+    uint8_t *volatile txData;         /*!< Transfer buffer */
+    uint8_t *volatile rxData;         /*!< Receive buffer */
+    volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
+    volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
+    volatile size_t toReceiveCount;   /*!< Receive data remaining in bytes */
+    size_t totalByteCount;            /*!< A number of transfer bytes */
+    volatile uint32_t state;          /*!< SPI internal state */
+    spi_master_callback_t callback;   /*!< SPI callback */
+    void *userData;                   /*!< Callback parameter */
+    uint8_t dataWidth;                /*!< Width of the data [Valid values: 1 to 16] */
+    uint8_t sselNum;      /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */
+    uint32_t configFlags; /*!< Additional option to control transfer */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief  Sets the SPI master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
+ * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
+ * some fields of the structure before calling SPI_MasterInit(). After calling this API,
+ * the master is ready to transfer.
+ * Example:
+   @code
+   spi_master_config_t config;
+   SPI_MasterGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to master config structure
+ */
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with master configuration.
+ *
+ * The configuration structure can be filled by user from scratch, or be set with default
+ * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+   spi_master_config_t config = {
+   .baudRate_Bps = 400000,
+   ...
+   };
+   SPI_MasterInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to master configuration structure
+ * @param srcClock_Hz Source clock frequency.
+ */
+status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief  Sets the SPI slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
+ * Modify some fields of the structure before calling SPI_SlaveInit().
+ * Example:
+   @code
+   spi_slave_config_t config;
+   SPI_SlaveGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to slave configuration structure
+ */
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with slave configuration.
+ *
+ * The configuration structure can be filled by user from scratch or be set with
+ * default values by SPI_SlaveGetDefaultConfig().
+ * After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+    spi_slave_config_t config = {
+    .polarity = flexSPIClockPolarity_ActiveHigh;
+    .phase = flexSPIClockPhase_FirstEdge;
+    .direction = flexSPIMsbFirst;
+    ...
+    };
+    SPI_SlaveInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to slave configuration structure
+ */
+status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
+
+/*!
+ * @brief De-initializes the SPI.
+ *
+ * Calling this API resets the SPI module, gates the SPI clock.
+ * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
+ *
+ * @param base SPI base pointer
+ */
+void SPI_Deinit(SPI_Type *base);
+
+/*!
+ * @brief Enable or disable the SPI Master or Slave
+ * @param base SPI base pointer
+ * @param enable or disable ( true = enable, false = disable)
+ */
+static inline void SPI_Enable(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= SPI_CFG_ENABLE_MASK;
+    }
+    else
+    {
+        base->CFG &= ~SPI_CFG_ENABLE_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the status flag.
+ *
+ * @param base SPI base pointer
+ * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status.
+ */
+static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
+{
+    assert(NULL != base);
+    return base->FIFOSTAT;
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxLvlIrq
+ *        @arg kSPI_TxLvlIrq
+ */
+static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
+{
+    assert(NULL != base);
+    base->FIFOINTENSET = irqs;
+}
+
+/*!
+ * @brief Disables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxLvlIrq
+ *        @arg kSPI_TxLvlIrq
+ */
+static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
+{
+    assert(NULL != base);
+    base->FIFOINTENCLR = irqs;
+}
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables the DMA request from SPI txFIFO.
+ *
+ * @param base SPI base pointer
+ * @param enable True means enable DMA, false means disable DMA
+ */
+void SPI_EnableTxDMA(SPI_Type *base, bool enable);
+
+/*!
+ * @brief Enables the DMA request from SPI rxFIFO.
+ *
+ * @param base SPI base pointer
+ * @param enable True means enable DMA, false means disable DMA
+ */
+void SPI_EnableRxDMA(SPI_Type *base, bool enable);
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the baud rate for SPI transfer. This is only used in master.
+ *
+ * @param base SPI base pointer
+ * @param baudrate_Bps baud rate needed in Hz.
+ * @param srcClock_Hz SPI source clock frequency in Hz.
+ */
+status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Writes a data into the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @param data needs to be write.
+ * @param configFlags transfer configuration options @ref spi_xfer_option_t
+ */
+void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags);
+
+/*!
+ * @brief Gets a data from the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @return Data in the register.
+ */
+static inline uint32_t SPI_ReadData(SPI_Type *base)
+{
+    assert(NULL != base);
+    return base->FIFORD;
+}
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPI master handle.
+ *
+ * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                        spi_master_handle_t *handle,
+                                        spi_master_callback_t callback,
+                                        void *userData);
+
+/*!
+ * @brief Transfers a block of data using a polling method.
+ *
+ * @param base SPI base pointer
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ */
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking SPI interrupt transfer.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer count.
+ *
+ * This function gets the master transfer count.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief SPI master aborts a transfer using an interrupt.
+ *
+ * This function aborts a transfer using an interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Interrupts the handler for the SPI.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Initializes the SPI slave handle.
+ *
+ * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
+                                                     spi_slave_handle_t *handle,
+                                                     spi_slave_callback_t callback,
+                                                     void *userData)
+{
+    return SPI_MasterTransferCreateHandle(base, handle, callback, userData);
+}
+
+/*!
+ * @brief Performs a non-blocking SPI slave interrupt transfer.
+ *
+ * @note The API returns immediately after the transfer initialization is finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
+{
+    return SPI_MasterTransferNonBlocking(base, handle, xfer);
+}
+
+/*!
+ * @brief Gets the slave transfer count.
+ *
+ * This function gets the slave transfer count.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
+ * @return status of status_t.
+ */
+static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count);
+}
+
+/*!
+ * @brief SPI slave aborts a transfer using an interrupt.
+ *
+ * This function aborts a transfer using an interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
+ */
+static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle);
+}
+
+/*!
+ * @brief Interrupts a handler for the SPI slave.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
+ */
+static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    SPI_MasterTransferHandleIRQ(base, handle);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_SPI_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_spi_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spi_dma.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
+typedef struct _spi_dma_private_handle
+{
+    SPI_Type *base;
+    spi_dma_handle_t *handle;
+} spi_dma_private_handle_t;
+
+/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
+enum _spi_dma_states_t
+{
+    kSPI_Idle = 0x0, /*!< SPI is idle state */
+    kSPI_Busy        /*!< SPI is busy tranferring data. */
+};
+
+typedef struct _spi_dma_txdummy
+{
+    uint32_t lastWord;
+    uint32_t word;
+} spi_dma_txdummy_t;
+
+/*<! Private handle only used for internally. */
+static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+* @brief SPI private function to return SPI configuration
+*
+* @param base SPI base address.
+*/
+void *SPI_GetConfig(SPI_Type *base);
+
+/*!
+ * @brief DMA callback function for SPI send transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*!
+ * @brief DMA callback function for SPI receive transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+static uint16_t s_rxDummy;
+
+#if defined(__ICCARM__)
+#pragma data_alignment = 16
+static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#endif
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+static void XferToFifoWR(spi_transfer_t *xfer, uint32_t *fifowr)
+{
+    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0;
+    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0;
+}
+
+static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr)
+{
+    *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum)));
+    /* set width of data - range asserted at entry */
+    *fifowr |= SPI_FIFOWR_LEN(config->dataWidth);
+}
+
+static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl)
+{
+    assert(!(fifo == NULL));
+    if (fifo == NULL)
+    {
+        return;
+    }
+    /* CS deassert and CS delay are relevant only for last word */
+    uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK));
+    uint32_t i = 0;
+    for (; i + 1 < count; i++)
+    {
+        fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U);
+    }
+    if (i < count)
+    {
+        fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U);
+    }
+}
+
+static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
+{
+    *dummy = SPI_DUMMYDATA;
+    XferToFifoWR(xfer, dummy);
+    SpiConfigToFifoWR(spi_config_p, dummy);
+}
+
+status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                           spi_dma_handle_t *handle,
+                                           spi_dma_callback_t callback,
+                                           void *userData,
+                                           dma_handle_t *txHandle,
+                                           dma_handle_t *rxHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = FLEXCOMM_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* Set spi base to handle */
+    handle->txHandle = txHandle;
+    handle->rxHandle = rxHandle;
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set SPI state to idle */
+    handle->state = kSPI_Idle;
+
+    /* Set handle to global state */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
+    DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
+
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    int32_t instance;
+    status_t result = kStatus_Success;
+    spi_config_t *spi_config_p;
+
+    assert(!((NULL == handle) || (NULL == xfer)));
+    if ((NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* txData set and not aligned to sizeof(uint32_t) */
+    assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))));
+    if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* rxData set and not aligned to sizeof(uint32_t) */
+    assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))));
+    if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* byte size is zero or not aligned to sizeof(uint32_t) */
+    assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))));
+    if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* cannot get instance from base address */
+    instance = FLEXCOMM_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check if the device is busy */
+    if (handle->state == kSPI_Busy)
+    {
+        return kStatus_SPI_Busy;
+    }
+    else
+    {
+        uint32_t tmp;
+        dma_transfer_config_t xferConfig = {0};
+        spi_config_p = (spi_config_t *)SPI_GetConfig(base);
+
+        handle->state = kStatus_SPI_Busy;
+        handle->transferSize = xfer->dataSize;
+
+        /* receive */
+        SPI_EnableRxDMA(base, true);
+        if (xfer->rxData)
+        {
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_PeripheralToMemory, NULL);
+        }
+        else
+        {
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_StaticToStatic, NULL);
+        }
+        DMA_SubmitTransfer(handle->rxHandle, &xferConfig);
+        handle->rxInProgress = true;
+        DMA_StartTransfer(handle->rxHandle);
+
+        /* transmit */
+        SPI_EnableTxDMA(base, true);
+        if (xfer->txData)
+        {
+            tmp = 0;
+            XferToFifoWR(xfer, &tmp);
+            SpiConfigToFifoWR(spi_config_p, &tmp);
+            PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp);
+            DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_MemoryToPeripheral, NULL);
+            DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+        }
+        else
+        {
+            if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t)))
+            {
+                dma_xfercfg_t tmp_xfercfg = { 0 };
+                tmp_xfercfg.valid = true;
+                tmp_xfercfg.swtrig = true;
+                tmp_xfercfg.intA = true;
+                tmp_xfercfg.byteWidth = sizeof(uint32_t);
+                tmp_xfercfg.srcInc = 0;
+                tmp_xfercfg.dstInc = 0;
+                tmp_xfercfg.transferCount = 1;
+                /* create chained descriptor to transmit last word */
+                SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p);
+                DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
+                                     (uint32_t *)&base->FIFOWR, NULL);
+                /* use common API to setup first descriptor */
+                SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p);
+                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
+                                    xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic,
+                                    &s_spi_descriptor_table[instance]);
+                /* disable interrupts for first descriptor
+                 * to avoid calling callback twice */
+                xferConfig.xfercfg.intA = false;
+                xferConfig.xfercfg.intB = false;
+                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+            }
+            else
+            {
+                SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p);
+                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
+                                    xfer->dataSize, kDMA_StaticToStatic, NULL);
+                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+            }
+        }
+        handle->txInProgress = true;
+        DMA_StartTransfer(handle->txHandle);
+    }
+
+    return result;
+}
+
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle = privHandle->handle;
+    SPI_Type *base = privHandle->base;
+
+    /* change the state */
+    spiHandle->rxInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = kSPI_Idle;
+        if (spiHandle->callback)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle = privHandle->handle;
+    SPI_Type *base = privHandle->base;
+
+    /* change the state */
+    spiHandle->txInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = kSPI_Idle;
+        if (spiHandle->callback)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Stop tx transfer first */
+    DMA_AbortTransfer(handle->txHandle);
+    /* Then rx transfer */
+    DMA_AbortTransfer(handle->rxHandle);
+
+    /* Set the handle state */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+    handle->state = kSPI_Idle;
+}
+
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kSPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    size_t bytes;
+
+    bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
+
+    *count = handle->transferSize - bytes;
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_spi_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used tom  endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPI_DMA_H_
+#define _FSL_SPI_DMA_H_
+
+#include "fsl_dma.h"
+#include "fsl_spi.h"
+
+/*!
+ * @addtogroup spi_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef struct _spi_dma_handle spi_dma_handle_t;
+
+/*! @brief SPI DMA callback called at the end of transfer. */
+typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/
+struct _spi_dma_handle
+{
+    volatile bool txInProgress;  /*!< Send transfer finished */
+    volatile bool rxInProgress;  /*!< Receive transfer finished */
+    dma_handle_t *txHandle;      /*!< DMA handler for SPI send */
+    dma_handle_t *rxHandle;      /*!< DMA handler for SPI receive */
+    uint8_t bytesPerFrame;       /*!< Bytes in a frame for SPI tranfer */
+    spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */
+    void *userData;              /*!< User Data for SPI DMA callback */
+    uint32_t state;              /*!< Internal state of SPI DMA transfer */
+    size_t transferSize;         /*!< Bytes need to be transfer */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initialize the SPI master DMA handle.
+ *
+ * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                           spi_dma_handle_t *handle,
+                                           spi_dma_callback_t callback,
+                                           void *userData,
+                                           dma_handle_t *txHandle,
+                                           dma_handle_t *rxHandle);
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Initialize the SPI slave DMA handle.
+ *
+ * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base,
+                                                        spi_dma_handle_t *handle,
+                                                        spi_dma_callback_t callback,
+                                                        void *userData,
+                                                        dma_handle_t *txHandle,
+                                                        dma_handle_t *rxHandle)
+{
+    return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle);
+}
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    return SPI_MasterTransferDMA(base, handle, xfer);
+}
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the master DMA transfer remaining bytes.
+ *
+ * This function gets the master DMA transfer remaining bytes.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    SPI_MasterTransferAbortDMA(base, handle);
+}
+
+/*!
+ * @brief Gets the slave DMA transfer remaining bytes.
+ *
+ * This function gets the slave DMA transfer remaining bytes.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
+ * @return status of status_t.
+ */
+static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCountDMA(base, handle, count);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_SPI_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_usart.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/* Array of UART IRQ number. */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+    size_t size;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    {
+        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+    }
+    else
+    {
+        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+    }
+    return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+    bool full;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+    /* ring buffer is ready we can start receiving data */
+    base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+
+    if (handle->rxState == kUSART_RxIdle)
+    {
+        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+    }
+    handle->rxRingBuffer = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+    int result;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to USART mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    /* setup baudrate */
+    result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (config->enableTx)
+    {
+        /* empty and enable txFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+    }
+
+    /* empty and enable rxFIFO */
+    if (config->enableRx)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+    }
+    /* setup configuration and enable USART */
+    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK;
+    return kStatus_Success;
+}
+
+void USART_Deinit(USART_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | USART_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+    /* Check arguments */
+    assert(NULL != config);
+
+    /* Set always all members ! */
+    config->baudRate_Bps = 115200U;
+    config->parityMode = kUSART_ParityDisabled;
+    config->stopBitCount = kUSART_OneStopBit;
+    config->bitCountPerChar = kUSART_8BitsPerChar;
+    config->loopback = false;
+    config->enableRx = false;
+    config->enableTx = false;
+    config->txWatermark = kUSART_TxFifo0;
+    config->rxWatermark = kUSART_RxFifo1;
+}
+
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+    uint32_t osrval, brgval, diff, baudrate;
+
+    /* check arguments */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    for (osrval = best_osrval; osrval >= 4; osrval--)
+    {
+        brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1;
+        if (brgval > 0xFFFF)
+        {
+            continue;
+        }
+        baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1));
+        diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
+        if (diff < best_diff)
+        {
+            best_diff = diff;
+            best_osrval = osrval;
+            best_brgval = brgval;
+        }
+    }
+
+    /* value over range */
+    if (best_brgval > 0xFFFF)
+    {
+        return kStatus_USART_BaudrateNotSupport;
+    }
+
+    base->OSR = best_osrval;
+    base->BRG = best_brgval;
+    return kStatus_Success;
+}
+
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return;
+    }
+    /* Check whether txFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+    {
+        return;
+    }
+    for (; length > 0; length--)
+    {
+        /* Loop until txFIFO get some space for new data */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+        }
+        base->FIFOWR = *data;
+        data++;
+    }
+    /* Wait to finish transfer */
+    while (!(base->FIFOSTAT & USART_FIFOSTAT_TXEMPTY_MASK))
+    {
+    }
+}
+
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+    uint32_t status;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check whether rxFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK))
+    {
+        return kStatus_Fail;
+    }
+    for (; length > 0; length--)
+    {
+        /* loop until rxFIFO have some data to read */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+        }
+        /* check receive status */
+        status = base->STAT;
+        if (status & USART_STAT_FRAMERRINT_MASK)
+        {
+            return kStatus_USART_FramingError;
+        }
+        if (status & USART_STAT_PARITYERRINT_MASK)
+        {
+            return kStatus_USART_ParityError;
+        }
+        if (status & USART_STAT_RXNOISEINT_MASK)
+        {
+            return kStatus_USART_NoiseError;
+        }
+        /* check rxFIFO status */
+        if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+        {
+            return kStatus_USART_RxError;
+        }
+        *data = base->FIFORD;
+        data++;
+    }
+    return kStatus_Success;
+}
+
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData)
+{
+    int32_t instance = 0;
+
+    /* Check 'base' */
+    assert(!((NULL == base) || (NULL == handle)));
+    if ((NULL == base) || (NULL == handle))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = FLEXCOMM_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* Set the TX/RX state. */
+    handle->rxState = kUSART_RxIdle;
+    handle->txState = kUSART_TxIdle;
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+    handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base);
+    handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)USART_TransferHandleIRQ, handle);
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(s_usartIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if (kUSART_TxBusy == handle->txState)
+    {
+        return kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txData = xfer->data;
+        handle->txDataSize = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState = kUSART_TxBusy;
+        /* Enable transmiter interrupt. */
+        base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
+    }
+    return kStatus_Success;
+}
+
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupts */
+    base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK;
+    /* Empty txFIFO */
+    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+    handle->txDataSize = 0;
+    handle->txState = kUSART_TxIdle;
+}
+
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes)
+{
+    uint32_t i;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t regPrimask = 0U;
+
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+    if (kUSART_RxBusy == handle->rxState)
+    {
+        return kStatus_USART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            regPrimask = DisableGlobalIRQ();
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+            if (bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+                bytesToReceive -= bytesToCopy;
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize = bytesToReceive;
+                handle->rxDataSizeAll = bytesToReceive;
+                handle->rxState = kUSART_RxBusy;
+            }
+            /* Enable IRQ if previously enabled. */
+            EnableGlobalIRQ(regPrimask);
+            /* Call user callback since all data are received. */
+            if (0 == bytesToReceive)
+            {
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState = kUSART_RxBusy;
+
+            /* Enable RX interrupt. */
+            base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
+        }
+        /* Return the how many bytes have read. */
+        if (receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+    }
+    return kStatus_Success;
+}
+
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (!handle->rxRingBuffer)
+    {
+        /* Disable interrupts */
+        base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK;
+        /* Empty rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState = kUSART_RxIdle;
+}
+
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert((NULL != base) && (NULL != handle));
+
+    bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer);
+    bool sendEnabled = handle->txDataSize;
+
+    /* If RX overrun. */
+    if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+    {
+        /* Clear rx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+        }
+    }
+    while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||
+           (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))
+    {
+        /* Receive data */
+        if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+            /* Receive to app bufffer if app buffer is present */
+            if (handle->rxDataSize)
+            {
+                *handle->rxData = base->FIFORD;
+                handle->rxDataSize--;
+                handle->rxData++;
+                receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer));
+                if (!handle->rxDataSize)
+                {
+                    if (!handle->rxRingBuffer)
+                    {
+                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+                    }
+                    handle->rxState = kUSART_RxIdle;
+                    if (handle->callback)
+                    {
+                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                    }
+                }
+            }
+            /* Otherwise receive to ring buffer if ring buffer is present */
+            else
+            {
+                if (handle->rxRingBuffer)
+                {
+                    /* If RX ring buffer is full, trigger callback to notify over run. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        if (handle->callback)
+                        {
+                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+                        }
+                    }
+                    /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        /* Increase handle->rxRingBufferTail to make room for new data. */
+                        if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                        {
+                            handle->rxRingBufferTail = 0U;
+                        }
+                        else
+                        {
+                            handle->rxRingBufferTail++;
+                        }
+                    }
+                    /* Read data. */
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD;
+                    /* Increase handle->rxRingBufferHead. */
+                    if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferHead = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferHead++;
+                    }
+                }
+            }
+        }
+        /* Send data */
+        if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+            base->FIFOWR = *handle->txData;
+            handle->txDataSize--;
+            handle->txData++;
+            sendEnabled = handle->txDataSize != 0;
+            if (!sendEnabled)
+            {
+                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+                handle->txState = kUSART_TxIdle;
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+
+    /* ring buffer is not used */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* restore if rx transfer ends and rxLevel is different from default value */
+        if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+        {
+            base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+        }
+        /* decrease level if rx transfer is bellow */
+        if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1)))
+        {
+            base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1));
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_usart.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,614 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_USART_H_
+#define _FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.0.0. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Error codes for the USART driver. */
+enum _usart_status
+{
+    kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0),              /*!< Transmitter is busy. */
+    kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1),              /*!< Receiver is busy. */
+    kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2),              /*!< USART transmitter is idle. */
+    kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3),              /*!< USART receiver is idle. */
+    kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7),             /*!< Error happens on txFIFO. */
+    kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9),             /*!< Error happens on txFIFO. */
+    kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */
+    kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10),         /*!< USART noise error. */
+    kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11),       /*!< USART framing error. */
+    kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12),        /*!< USART parity error. */
+    kStatus_USART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode {
+    kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kUSART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kUSART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count {
+    kUSART_OneStopBit = 0U, /*!< One stop bit */
+    kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len {
+    kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+    kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark {
+    kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+    kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+    kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+    kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+    kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+    kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+    kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+    kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark {
+    kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+    kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+    kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+    kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+    kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+    kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+    kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+    kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+    kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+    kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+    kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+    kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+    kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK),                 /*!< TXEMPT bit, sets if TX buffer is empty */
+    kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK),                 /*!< TXEMPT bit, sets if TX buffer is empty */
+    kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK),       /*!< TXEMPT bit, sets if TX buffer is empty */
+    kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK),   /*!< TXEMPT bit, sets if TX buffer is not full */
+    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXEMPT bit, sets if RX buffer is not empty */
+    kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK),         /*!< RXEMPT bit, sets if RX buffer is full */
+};
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+    uint32_t baudRate_Bps;               /*!< USART baud rate  */
+    usart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    usart_data_len_t bitCountPerChar;    /*!< Data length - 7 bit, 8 bit  */
+    bool loopback;                       /*!< Enable peripheral loopback */
+    bool enableRx;                       /*!< Enable RX */
+    bool enableTx;                       /*!< Enable TX */
+    usart_txfifo_watermark_t txWatermark;/*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark;/*!< rxFIFO watermark */
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    usart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                     /*!< USART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source freqency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+    return base->FIFOSTAT;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = mask & 0xF;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = ~(mask & 0xF);
+}
+
+/*!
+* @brief Enable DMA for Tx
+*/
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+    }
+}
+
+/*!
+* @brief Enable DMA for Rx
+*/
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+    base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+    return base->FIFORD;
+}
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See  #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+                                   usart_handle_t *handle,
+                                   uint8_t *ringBuffer,
+                                   size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_usart_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_dma.h"
+#include "fsl_flexcomm.h"
+#include "fsl_usart_dma.h"
+
+#define USART_HANDLE_ARRAY_SIZE 7
+
+/*<! Structure definition for uart_dma_handle_t. The structure is private. */
+typedef struct _usart_dma_private_handle
+{
+    USART_Type *base;
+    usart_dma_handle_t *handle;
+} usart_dma_private_handle_t;
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*<! Private handle only used for internally. */
+static usart_dma_private_handle_t s_dmaPrivateHandle[USART_HANDLE_ARRAY_SIZE];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static void USART_TransferSendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
+
+    /* Disable UART TX DMA. */
+    USART_EnableTxDMA(usartPrivateHandle->base, false);
+
+    usartPrivateHandle->handle->txState = kUSART_TxIdle;
+
+    if (usartPrivateHandle->handle->callback)
+    {
+        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle,
+                                             usartPrivateHandle->handle->userData);
+    }
+}
+
+static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
+
+    /* Disable UART RX DMA. */
+    USART_EnableRxDMA(usartPrivateHandle->base, false);
+
+    usartPrivateHandle->handle->rxState = kUSART_RxIdle;
+
+    if (usartPrivateHandle->handle->callback)
+    {
+        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle,
+                                             usartPrivateHandle->handle->userData);
+    }
+}
+
+status_t USART_TransferCreateHandleDMA(USART_Type *base,
+                                       usart_dma_handle_t *handle,
+                                       usart_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txDmaHandle,
+                                       dma_handle_t *rxDmaHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = FLEXCOMM_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* assign 'base' and 'handle' */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    /* set tx/rx 'idle' state */
+    handle->rxState = kUSART_RxIdle;
+    handle->txState = kUSART_TxIdle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->txDmaHandle = txDmaHandle;
+
+    /* Configure TX. */
+    if (txDmaHandle)
+    {
+        DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    /* Configure RX. */
+    if (rxDmaHandle)
+    {
+        DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->txDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kUSART_TxBusy == handle->txState)
+    {
+        status = kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txState = kUSART_TxBusy;
+        handle->txDataSizeAll = xfer->dataSize;
+
+        /* Enable DMA request from txFIFO */
+        USART_EnableTxDMA(base, true);
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)&base->FIFOWR, sizeof(uint8_t), xfer->dataSize,
+                            kDMA_MemoryToPeripheral, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->txDmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous RX not finished. */
+    if (kUSART_RxBusy == handle->rxState)
+    {
+        status = kStatus_USART_RxBusy;
+    }
+    else
+    {
+        handle->rxState = kUSART_RxBusy;
+        handle->rxDataSizeAll = xfer->dataSize;
+
+        /* Enable DMA request from rxFIFO */
+        USART_EnableRxDMA(base, true);
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->data, sizeof(uint8_t), xfer->dataSize,
+                            kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->txDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->txDmaHandle);
+    handle->txState = kUSART_TxIdle;
+}
+
+void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->rxDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+    handle->rxState = kUSART_RxIdle;
+}
+
+status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(count);
+
+    if (kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_usart_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_USART_DMA_H_
+#define _FSL_USART_DMA_H_
+
+#include "fsl_common.h"
+#include "fsl_dma.h"
+#include "fsl_usart.h"
+
+/*!
+ * @addtogroup usart_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_dma_handle usart_dma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*usart_dma_transfer_callback_t)(USART_Type *base,
+                                              usart_dma_handle_t *handle,
+                                              status_t status,
+                                              void *userData);
+
+/*!
+* @brief UART DMA handle
+*/
+struct _usart_dma_handle
+{
+    USART_Type *base; /*!< UART peripheral base address. */
+
+    usart_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                         /*!< UART callback function parameter.*/
+    size_t rxDataSizeAll;                   /*!< Size of the data to receive. */
+    size_t txDataSizeAll;                   /*!< Size of the data to send out. */
+
+    dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
+    dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name DMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle which is used in transactional functions.
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param txDmaHandle User-requested DMA handle for TX DMA transfer.
+ * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+status_t USART_TransferCreateHandleDMA(USART_Type *base,
+                                       usart_dma_handle_t *handle,
+                                       usart_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txDmaHandle,
+                                       dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Sends data using DMA.
+ *
+ * This function sends data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART DMA transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_USART_TxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer USART DMA transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_USART_RxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using DMA.
+ *
+ * This function aborts send data using DMA.
+ *
+ * @param base USART peripheral base address
+ * @param handle Pointer to usart_dma_handle_t structure
+ */
+void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * @param base USART peripheral base address
+ * @param handle Pointer to usart_dma_handle_t structure
+ */
+void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_utick.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_utick.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Typedef for interrupt handler. */
+typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base UTICK peripheral base address
+ *
+ * @return The UTICK instance
+ */
+static uint32_t UTICK_GetInstance(UTICK_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of UTICK handle. */
+static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT];
+/* Array of UTICK peripheral base address. */
+static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS;
+/* Array of UTICK IRQ number. */
+static const IRQn_Type s_utickIRQ[] = UTICK_IRQS;
+/* Array of UTICK clock name. */
+static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS;
+/* UTICK ISR for transactional APIs. */
+static utick_isr_t s_utickIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t UTICK_GetInstance(UTICK_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_UTICK_COUNT; instance++)
+    {
+        if (s_utickBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_UTICK_COUNT);
+
+    return instance;
+}
+
+void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb)
+{
+    uint32_t instance;
+
+    /* Get instance from peripheral base address. */
+    instance = UTICK_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_utickHandle[instance] = cb;
+    EnableDeepSleepIRQ(s_utickIRQ[instance]);
+    base->CTRL = count | UTICK_CTRL_REPEAT(mode);
+}
+
+void UTICK_Init(UTICK_Type *base)
+{
+    /* Enable utick clock */
+    CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]);
+    /* Power up Watchdog oscillator*/
+    POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC);
+    s_utickIsr = UTICK_HandleIRQ;
+}
+
+void UTICK_Deinit(UTICK_Type *base)
+{
+    /* Turn off utick */
+    base->CTRL = 0;
+    /* Disable utick clock */
+    CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]);
+}
+
+uint32_t UTICK_GetStatusFlags(UTICK_Type *base)
+{
+    return (base->STAT);
+}
+
+void UTICK_ClearStatusFlags(UTICK_Type *base)
+{
+    base->STAT = UTICK_STAT_INTR_MASK;
+}
+
+void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb)
+{
+    UTICK_ClearStatusFlags(base);
+    if (cb)
+    {
+        cb();
+    }
+}
+
+#if defined(UTICK0)
+void UTICK0_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK0, s_utickHandle[0]);
+}
+#endif
+#if defined(UTICK1)
+void UTICK1_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK1, s_utickHandle[1]);
+}
+#endif
+#if defined(UTICK2)
+void UTICK2_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK2, s_utickHandle[2]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_utick.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_UTICK_H_
+#define _FSL_UTICK_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup utick
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UTICK driver version 2.0.0. */
+#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief UTICK timer operational mode. */
+typedef enum _utick_mode
+{
+    kUTICK_Onetime = 0x0U, /*!< Trigger once*/
+    kUTICK_Repeat = 0x1U,  /*!< Trigger repeatedly */
+} utick_mode_t;
+
+/*! @brief UTICK callback function. */
+typedef void (*utick_callback_t)(void);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+* @brief Initializes an UTICK by turning its bus clock on
+*
+*/
+void UTICK_Init(UTICK_Type *base);
+
+/*!
+ * @brief Deinitializes a UTICK instance.
+ *
+ * This function shuts down Utick bus clock
+ *
+ * @param base UTICK peripheral base address.
+ */
+void UTICK_Deinit(UTICK_Type *base);
+/*!
+ * @brief Get Status Flags.
+ *
+ * This returns the status flag
+ *
+ * @param base UTICK peripheral base address.
+ * @return status register value
+ */
+uint32_t UTICK_GetStatusFlags(UTICK_Type *base);
+/*!
+ * @brief Clear Status Interrupt Flags.
+ *
+ * This clears intr status flag
+ *
+ * @param base UTICK peripheral base address.
+ * @return none
+ */
+void UTICK_ClearStatusFlags(UTICK_Type *base);
+
+/*!
+ * @brief Starts UTICK.
+ *
+ * This function starts a repeat/onetime countdown with an optional callback
+ *
+ * @param base   UTICK peripheral base address.
+ * @param mode  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
+ * @param count  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
+ * @param cb  UTICK callback (can be left as NULL if none, otherwise should be a void func(void))
+ * @return none
+ */
+void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb);
+/*!
+ * @brief UTICK Interrupt Service Handler.
+ *
+ * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request
+ * in UTICK_SetTick()).
+ * if no user callback is scheduled, the interrupt will simply be cleared.
+ *
+ * @param base   UTICK peripheral base address.
+ * @param cb  callback scheduled for this instance of UTICK
+ * @return none
+ */
+void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UTICK_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_wwdt.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wwdt.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base WWDT peripheral base address
+ *
+ * @return The WWDT instance
+ */
+static uint32_t WWDT_GetInstance(WWDT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to WWDT bases for each instance. */
+static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS;
+
+/*! @brief Pointers to WWDT clocks for each instance. */
+static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS;
+
+/*! @brief Pointers to WWDT resets for each instance. */
+static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t WWDT_GetInstance(WWDT_Type *base)
+{
+    uint32_t instance;
+    uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < wwdtArrayCount; instance++)
+    {
+        if (s_wwdtBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < wwdtArrayCount);
+
+    return instance;
+}
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void WWDT_GetDefaultConfig(wwdt_config_t *config)
+{
+    assert(config);
+
+    /* Enable the watch dog */
+    config->enableWwdt = true;
+    /* Disable the watchdog timeout reset */
+    config->enableWatchdogReset = false;
+    /* Disable the watchdog protection for updating the timeout value */
+    config->enableWatchdogProtect = false;
+    /* Do not lock the watchdog oscillator */
+    config->enableLockOscillator = false;
+    /* Windowing is not in effect */
+    config->windowValue = 0xFFFFFFU;
+    /* Set the timeout value to the max */
+    config->timeoutValue = 0xFFFFFFU;
+    /* No warning is provided */
+    config->warningValue = 0;
+}
+
+void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)
+{
+    assert(config);
+
+    uint32_t value = 0U;
+
+    /* Enable the WWDT clock */
+    CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
+
+    /* Reset the WWDT module */
+    RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]);
+
+    value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) |
+            WWDT_MOD_WDPROTECT(config->enableWatchdogProtect) | WWDT_MOD_LOCK(config->enableLockOscillator);
+    /* Set configruation */
+    base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue);
+    base->TC = WWDT_TC_COUNT(config->timeoutValue);
+    base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue);
+    base->MOD = value;
+}
+
+void WWDT_Deinit(WWDT_Type *base)
+{
+    WWDT_Disable(base);
+
+    /* Disable the WWDT clock */
+    CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
+}
+
+void WWDT_Refresh(WWDT_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupt to protect refresh sequence */
+    primaskValue = DisableGlobalIRQ();
+    base->FEED = WWDT_FIRST_WORD_OF_REFRESH;
+    base->FEED = WWDT_SECOND_WORD_OF_REFRESH;
+    EnableGlobalIRQ(primaskValue);
+}
+
+void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask)
+{
+    /* Clear the WDINT bit so that we don't accidentally clear it */
+    uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK));
+
+    /* Clear timeout by writing a zero */
+    if (mask & kWWDT_TimeoutFlag)
+    {
+        reg &= ~WWDT_MOD_WDTOF_MASK;
+    }
+
+    /* Clear warning interrupt flag by writing a one */
+    if (mask & kWWDT_WarningFlag)
+    {
+        reg |= WWDT_MOD_WDINT_MASK;
+    }
+
+    base->MOD = reg;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_wwdt.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_WWDT_H_
+#define _FSL_WWDT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup wwdt
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines WWDT driver version 2.0.0. */
+#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @name Refresh sequence */
+/*@{*/
+#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU)  /*!< First word of refresh sequence */
+#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */
+/*@}*/
+
+/*! @brief Describes WWDT configuration structure. */
+typedef struct _wwdt_config
+{
+    bool enableWwdt;            /*!< Enables or disables WWDT */
+    bool enableWatchdogReset;   /*!< true: Watchdog timeout will cause a chip reset
+                                     false: Watchdog timeout will not cause a chip reset */
+    bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be
+                                           changed after counter is below warning & window values
+                                     false: Disable watchdog protect; timeout value can be changed
+                                            at any time */
+    bool enableLockOscillator;  /*!< true: Disabling or powering down the watchdog oscillator is prevented
+                                           Once set, this bit can only be cleared by a reset
+                                     false: Do not lock oscillator */
+    uint32_t windowValue;       /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */
+    uint32_t timeoutValue;      /*!< Timeout value */
+    uint32_t warningValue;      /*!< Watchdog time counter value that will generate a
+                                     warning interrupt. Set this to 0 for no warning */
+
+} wwdt_config_t;
+
+/*!
+ * @brief WWDT status flags.
+ *
+ * This structure contains the WWDT status flags for use in the WWDT functions.
+ */
+enum _wwdt_status_flags_t
+{
+    kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */
+    kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK  /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */
+};
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name WWDT Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes WWDT configure sturcture.
+ *
+ * This function initializes the WWDT configure structure to default value. The default
+ * value are:
+ * @code
+ *  config->enableWwdt = true;
+ *  config->enableWatchdogReset = false;
+ *  config->enableWatchdogProtect = false;
+ *  config->enableLockOscillator = false;
+ *  config->windowValue = 0xFFFFFFU;
+ *  config->timeoutValue = 0xFFFFFFU;
+ *  config->warningValue = 0;
+ * @endcode
+ *
+ * @param config Pointer to WWDT config structure.
+ * @see wwdt_config_t
+ */
+void WWDT_GetDefaultConfig(wwdt_config_t *config);
+
+/*!
+ * @brief Initializes the WWDT.
+ *
+ * This function initializes the WWDT. When called, the WWDT runs according to the configuration.
+ *
+ * Example:
+ * @code
+ *   wwdt_config_t config;
+ *   WWDT_GetDefaultConfig(&config);
+ *   config.timeoutValue = 0x7ffU;
+ *   WWDT_Init(wwdt_base,&config);
+ * @endcode
+ *
+ * @param base   WWDT peripheral base address
+ * @param config The configuration of WWDT
+ */
+void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config);
+
+/*!
+ * @brief Shuts down the WWDT.
+ *
+ * This function shuts down the WWDT.
+ *
+ * @param base WWDT peripheral base address
+ */
+void WWDT_Deinit(WWDT_Type *base);
+
+/* @} */
+
+/*!
+ * @name WWDT Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the WWDT module.
+ *
+ * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit;
+ * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run
+ * permanently.
+ *
+ * @param base WWDT peripheral base address
+ */
+static inline void WWDT_Enable(WWDT_Type *base)
+{
+    base->MOD |= WWDT_MOD_WDEN_MASK;
+}
+
+/*!
+ * @brief Disables the WWDT module.
+ *
+ * This function write value into WWDT_MOD register to disable the WWDT.
+ *
+ * @param base WWDT peripheral base address
+ */
+static inline void WWDT_Disable(WWDT_Type *base)
+{
+    base->MOD &= ~WWDT_MOD_WDEN_MASK;
+}
+
+/*!
+ * @brief Gets all WWDT status flags.
+ *
+ * This function gets all status flags.
+ *
+ * Example for getting Timeout Flag:
+ * @code
+ *   uint32_t status;
+ *   status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag;
+ * @endcode
+ * @param base        WWDT peripheral base address
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::_wwdt_status_flags_t
+ */
+static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base)
+{
+    return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK));
+}
+
+/*!
+ * @brief Clear WWDT flag.
+ *
+ * This function clears WWDT status flag.
+ *
+ * Example for clearing warning flag:
+ * @code
+ *   WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag);
+ * @endcode
+ * @param base WWDT peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::_wwdt_status_flags_t
+ */
+void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask);
+
+/*!
+ * @brief Set the WWDT warning value.
+ *
+ * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog
+ * interrupt. When the watchdog timer counter is no longer greater than the value defined by
+ * WARNINT, an interrupt will be generated after the subsequent WDCLK.
+ *
+ * @param base         WWDT peripheral base address
+ * @param warningValue WWDT warning value.
+ */
+static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue)
+{
+    base->WARNINT = WWDT_WARNINT_WARNINT(warningValue);
+}
+
+/*!
+ * @brief Set the WWDT timeout value.
+ *
+ * This function sets the timeout value. Every time a feed sequence occurs the value in the TC
+ * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be
+ * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4.
+ * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change
+ * the timeout value before the watchdog counter is below the warning and window values
+ * will cause a watchdog reset and set the WDTOF flag.
+ *
+ * @param base WWDT peripheral base address
+ * @param timeoutCount WWDT timeout value, count of WWDT clock tick.
+ */
+static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount)
+{
+    base->TC = WWDT_TC_COUNT(timeoutCount);
+}
+
+/*!
+ * @brief Sets the WWDT window value.
+ *
+ * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed.
+ * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog
+ * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer
+ * value) so windowing is not in effect.
+ *
+ * @param base        WWDT peripheral base address
+ * @param windowValue WWDT window value.
+ */
+static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)
+{
+    base->WINDOW = WWDT_WINDOW_WINDOW(windowValue);
+}
+
+/*!
+ * @brief Refreshes the WWDT timer.
+ *
+ * This function feeds the WWDT.
+ * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * @param base WWDT peripheral base address
+ */
+void WWDT_Refresh(WWDT_Type *base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_WWDT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralNames.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,112 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+    UART_0 = Flexcomm0,
+    UART_1 = Flexcomm4
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+typedef enum {
+    I2C_0 = Flexcomm1,
+    I2C_1 = Flexcomm2
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // FTM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // FTM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // FTM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // FTM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // FTM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // FTM0 CH5
+    PWM_7  = (0 << TPM_SHIFT) | (6),  // FTM0 CH6
+    PWM_8  = (0 << TPM_SHIFT) | (7),  // FTM0 CH7
+    PWM_9  = (1 << TPM_SHIFT) | (0),  // FTM1 CH0
+    PWM_10 = (1 << TPM_SHIFT) | (1),  // FTM1 CH1
+    PWM_11 = (1 << TPM_SHIFT) | (2),  // FTM1 CH2
+    PWM_12 = (1 << TPM_SHIFT) | (3),  // FTM1 CH3
+    PWM_13 = (1 << TPM_SHIFT) | (4),  // FTM1 CH4
+    PWM_14 = (1 << TPM_SHIFT) | (5),  // FTM1 CH5
+    PWM_15 = (1 << TPM_SHIFT) | (6),  // FTM1 CH6
+    PWM_16 = (1 << TPM_SHIFT) | (7),  // FTM1 CH7
+    PWM_17 = (2 << TPM_SHIFT) | (0),  // FTM2 CH0
+    PWM_18 = (2 << TPM_SHIFT) | (1),  // FTM2 CH1
+    PWM_19 = (2 << TPM_SHIFT) | (2),  // FTM2 CH2
+    PWM_20 = (2 << TPM_SHIFT) | (3),  // FTM2 CH3
+    PWM_21 = (2 << TPM_SHIFT) | (4),  // FTM2 CH4
+    PWM_22 = (2 << TPM_SHIFT) | (5),  // FTM2 CH5
+    PWM_23 = (2 << TPM_SHIFT) | (6),  // FTM2 CH6
+    PWM_24 = (2 << TPM_SHIFT) | (7),  // FTM2 CH7
+    PWM_25 = (3 << TPM_SHIFT) | (0),  // FTM3 CH0
+    PWM_26 = (3 << TPM_SHIFT) | (1),  // FTM3 CH1
+    PWM_27 = (3 << TPM_SHIFT) | (2),  // FTM3 CH2
+    PWM_28 = (3 << TPM_SHIFT) | (3),  // FTM3 CH3
+    PWM_29 = (3 << TPM_SHIFT) | (4),  // FTM3 CH4
+    PWM_30 = (3 << TPM_SHIFT) | (5),  // FTM3 CH5
+    PWM_31 = (3 << TPM_SHIFT) | (6),  // FTM3 CH6
+    PWM_32 = (3 << TPM_SHIFT) | (7),  // FTM3 CH7
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT           8
+#define ADC_B_CHANNEL_SHIFT        5
+
+typedef enum {
+    ADC0_SE0  = 0,
+    ADC0_SE1  = 1,
+    ADC0_SE2  = 2,
+    ADC0_SE3  = 3,
+    ADC0_SE4  = 4,
+    ADC0_SE5  = 5,
+    ADC0_SE6  = 6,
+    ADC0_SE7  = 7,
+    ADC0_SE8  = 8,
+    ADC0_SE9  = 9,
+    ADC0_SE10 = 10,
+    ADC0_SE11 = 11,
+} ADCName;
+
+typedef enum {
+    CAN_0 = 0,
+    CAN_1 = 1
+} CANName;
+
+typedef enum {
+    SPI_0 = Flexcomm3,
+    SPI_1 = Flexcomm9
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P0_16, ADC0_SE4,  0},
+    {P0_31, ADC0_SE5,  0},
+    {P1_0,  ADC0_SE6,  0},
+    {P2_0,  ADC0_SE7,  0},
+    {NC   , NC      ,  0}
+};
+
+/************CAN***************/
+const PinMap PinMap_CAN_TD[] = {
+    {P3_18, CAN_0,  4},
+    {P1_17, CAN_1,  5},
+    {NC   , NC   ,  0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {P3_19, CAN_0,  4},
+    {P1_18, CAN_1,  5},
+    {NC   , NC   ,  0}
+};
+
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+    {NC      , NC   , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_13, I2C_0, 1},
+    {P3_23, I2C_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_14, I2C_0, 1},
+    {P3_24, I2C_1, 1},
+    {NC   , NC   , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_30, UART_0, 1},
+    {P3_27, UART_1, 1},
+    {NC   ,  NC   , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_29, UART_0, 1},
+    {P3_26, UART_1, 1},
+    {NC   ,  NC   , 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {P3_28, UART_1, 1},
+    {NC   , NC    , 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {P3_29, UART_1, 1},
+    {NC   , NC    , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P0_0,  SPI_0, 2},
+    {P3_20, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P0_3,  SPI_0, 1},
+    {P3_21, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P0_2,  SPI_0, 1},
+    {P3_22, SPI_1, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_1,  SPI_0, 2},
+    {P3_30, SPI_1, 1},
+    {P4_6,  SPI_1, 2},
+    {NC  ,  NC   , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {NC   , NC    , 0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    P0_0 = (0 << PORT_SHIFT | 0),
+    P0_1 = (0 << PORT_SHIFT | 1),
+    P0_2 = (0 << PORT_SHIFT | 2),
+    P0_3 = (0 << PORT_SHIFT | 3),
+    P0_4 = (0 << PORT_SHIFT | 4),
+    P0_5 = (0 << PORT_SHIFT | 5),
+    P0_6 = (0 << PORT_SHIFT | 6),
+    P0_7 = (0 << PORT_SHIFT | 7),
+    P0_8 = (0 << PORT_SHIFT | 8),
+    P0_9 = (0 << PORT_SHIFT | 9),
+    P0_10 = (0 << PORT_SHIFT | 10),
+    P0_11 = (0 << PORT_SHIFT | 11),
+    P0_12 = (0 << PORT_SHIFT | 12),
+    P0_13 = (0 << PORT_SHIFT | 13),
+    P0_14 = (0 << PORT_SHIFT | 14),
+    P0_15 = (0 << PORT_SHIFT | 15),
+    P0_16 = (0 << PORT_SHIFT | 16),
+    P0_17 = (0 << PORT_SHIFT | 17),
+    P0_18 = (0 << PORT_SHIFT | 18),
+    P0_19 = (0 << PORT_SHIFT | 19),
+    P0_20 = (0 << PORT_SHIFT | 20),
+    P0_21 = (0 << PORT_SHIFT | 21),
+    P0_22 = (0 << PORT_SHIFT | 22),
+    P0_23 = (0 << PORT_SHIFT | 23),
+    P0_24 = (0 << PORT_SHIFT | 24),
+    P0_25 = (0 << PORT_SHIFT | 25),
+    P0_26 = (0 << PORT_SHIFT | 26),
+    P0_27 = (0 << PORT_SHIFT | 27),
+    P0_28 = (0 << PORT_SHIFT | 28),
+    P0_29 = (0 << PORT_SHIFT | 29),
+    P0_30 = (0 << PORT_SHIFT | 30),
+    P0_31 = (0 << PORT_SHIFT | 31),
+
+    P1_0 = (1 << PORT_SHIFT | 0),
+    P1_1 = (1 << PORT_SHIFT | 1),
+    P1_2 = (1 << PORT_SHIFT | 2),
+    P1_3 = (1 << PORT_SHIFT | 3),
+    P1_4 = (1 << PORT_SHIFT | 4),
+    P1_5 = (1 << PORT_SHIFT | 5),
+    P1_6 = (1 << PORT_SHIFT | 6),
+    P1_7 = (1 << PORT_SHIFT | 7),
+    P1_8 = (1 << PORT_SHIFT | 8),
+    P1_9 = (1 << PORT_SHIFT | 9),
+    P1_10 = (1 << PORT_SHIFT | 10),
+    P1_11 = (1 << PORT_SHIFT | 11),
+    P1_12 = (1 << PORT_SHIFT | 12),
+    P1_13 = (1 << PORT_SHIFT | 13),
+    P1_14 = (1 << PORT_SHIFT | 14),
+    P1_15 = (1 << PORT_SHIFT | 15),
+    P1_16 = (1 << PORT_SHIFT | 16),
+    P1_17 = (1 << PORT_SHIFT | 17),
+    P1_18 = (1 << PORT_SHIFT | 18),
+    P1_19 = (1 << PORT_SHIFT | 19),
+    P1_20 = (1 << PORT_SHIFT | 20),
+    P1_21 = (1 << PORT_SHIFT | 21),
+    P1_22 = (1 << PORT_SHIFT | 22),
+    P1_23 = (1 << PORT_SHIFT | 23),
+    P1_24 = (1 << PORT_SHIFT | 24),
+    P1_25 = (1 << PORT_SHIFT | 25),
+    P1_26 = (1 << PORT_SHIFT | 26),
+    P1_27 = (1 << PORT_SHIFT | 27),
+    P1_28 = (1 << PORT_SHIFT | 28),
+    P1_29 = (1 << PORT_SHIFT | 29),
+    P1_30 = (1 << PORT_SHIFT | 30),
+    P1_31 = (1 << PORT_SHIFT | 31),
+
+    P2_0 = (2 <<  PORT_SHIFT | 0),
+    P2_1 = (2 <<  PORT_SHIFT | 1),
+    P2_2 = (2 <<  PORT_SHIFT | 2),
+    P2_3 = (2 <<  PORT_SHIFT | 3),
+    P2_4 = (2 <<  PORT_SHIFT | 4),
+    P2_5 = (2 <<  PORT_SHIFT | 5),
+    P2_6 = (2 <<  PORT_SHIFT | 6),
+    P2_7 = (2 <<  PORT_SHIFT | 7),
+    P2_8 = (2 <<  PORT_SHIFT | 8),
+    P2_9 = (2 <<  PORT_SHIFT | 9),
+    P2_10 = (2 <<  PORT_SHIFT | 10),
+    P2_11 = (2 <<  PORT_SHIFT | 11),
+    P2_12 = (2 <<  PORT_SHIFT | 12),
+    P2_13 = (2 <<  PORT_SHIFT | 13),
+    P2_14 = (2 <<  PORT_SHIFT | 14),
+    P2_15 = (2 <<  PORT_SHIFT | 15),
+    P2_16 = (2 <<  PORT_SHIFT | 16),
+    P2_17 = (2 <<  PORT_SHIFT | 17),
+    P2_18 = (2 <<  PORT_SHIFT | 18),
+    P2_19 = (2 <<  PORT_SHIFT | 19),
+    P2_20 = (2 <<  PORT_SHIFT | 20),
+    P2_21 = (2 <<  PORT_SHIFT | 21),
+    P2_22 = (2 <<  PORT_SHIFT | 22),
+    P2_23 = (2 <<  PORT_SHIFT | 23),
+    P2_24 = (2 <<  PORT_SHIFT | 24),
+    P2_25 = (2 <<  PORT_SHIFT | 25),
+    P2_26 = (2 <<  PORT_SHIFT | 26),
+    P2_27 = (2 <<  PORT_SHIFT | 27),
+    P2_28 = (2 <<  PORT_SHIFT | 28),
+    P2_29 = (2 <<  PORT_SHIFT | 29),
+    P2_30 = (2 <<  PORT_SHIFT | 30),
+    P2_31 = (2 <<  PORT_SHIFT | 31),
+
+    P3_0 = (3 <<  PORT_SHIFT | 0),
+    P3_1 = (3 <<  PORT_SHIFT | 1),
+    P3_2 = (3 <<  PORT_SHIFT | 2),
+    P3_3 = (3 <<  PORT_SHIFT | 3),
+    P3_4 = (3 <<  PORT_SHIFT | 4),
+    P3_5 = (3 <<  PORT_SHIFT | 5),
+    P3_6 = (3 <<  PORT_SHIFT | 6),
+    P3_7 = (3 <<  PORT_SHIFT | 7),
+    P3_8 = (3 <<  PORT_SHIFT | 8),
+    P3_9 = (3 <<  PORT_SHIFT | 9),
+    P3_10 = (3 <<  PORT_SHIFT | 10),
+    P3_11 = (3 <<  PORT_SHIFT | 11),
+    P3_12 = (3 <<  PORT_SHIFT | 12),
+    P3_13 = (3 <<  PORT_SHIFT | 13),
+    P3_14 = (3 <<  PORT_SHIFT | 14),
+    P3_15 = (3 <<  PORT_SHIFT | 15),
+    P3_16 = (3 <<  PORT_SHIFT | 16),
+    P3_17 = (3 <<  PORT_SHIFT | 17),
+    P3_18 = (3 <<  PORT_SHIFT | 18),
+    P3_19 = (3 <<  PORT_SHIFT | 19),
+    P3_20 = (3 <<  PORT_SHIFT | 20),
+    P3_21 = (3 <<  PORT_SHIFT | 21),
+    P3_22 = (3 <<  PORT_SHIFT | 22),
+    P3_23 = (3 <<  PORT_SHIFT | 23),
+    P3_24 = (3 <<  PORT_SHIFT | 24),
+    P3_25 = (3 <<  PORT_SHIFT | 25),
+    P3_26 = (3 <<  PORT_SHIFT | 26),
+    P3_27 = (3 <<  PORT_SHIFT | 27),
+    P3_28 = (3 <<  PORT_SHIFT | 28),
+    P3_29 = (3 <<  PORT_SHIFT | 29),
+    P3_30 = (3 <<  PORT_SHIFT | 30),
+    P3_31 = (3 <<  PORT_SHIFT | 31),
+
+    P4_0 = (4 <<  PORT_SHIFT | 0),
+    P4_1 = (4 <<  PORT_SHIFT | 1),
+    P4_2 = (4 <<  PORT_SHIFT | 2),
+    P4_3 = (4 <<  PORT_SHIFT | 3),
+    P4_4 = (4 <<  PORT_SHIFT | 4),
+    P4_5 = (4 <<  PORT_SHIFT | 5),
+    P4_6 = (4 <<  PORT_SHIFT | 6),
+    P4_7 = (4 <<  PORT_SHIFT | 7),
+    P4_8 = (4 <<  PORT_SHIFT | 8),
+    P4_9 = (4 <<  PORT_SHIFT | 9),
+    P4_10 = (4 <<  PORT_SHIFT | 10),
+    P4_11 = (4 <<  PORT_SHIFT | 11),
+    P4_12 = (4 <<  PORT_SHIFT | 12),
+    P4_13 = (4 <<  PORT_SHIFT | 13),
+    P4_14 = (4 <<  PORT_SHIFT | 14),
+    P4_15 = (4 <<  PORT_SHIFT | 15),
+    P4_16 = (4 <<  PORT_SHIFT | 16),
+
+    LED_RED   = P2_2,
+
+    // mbed original LED naming
+    LED1 = LED_RED,
+    LED2 = P3_3,
+    LED3 = P3_14,
+    LED4 = LED_RED,
+
+    //Push buttons
+    SW2 = P0_6,
+    SW3 = P0_5,
+    SW4 = P0_4,
+    SW5 = P1_1,
+
+    // USB Pins
+    USBTX = P0_30,
+    USBRX = P0_29,
+
+    // Arduino Headers
+    D0 = P3_26,
+    D1 = P3_27,
+    D2 = P3_2,
+    D3 = P4_5,
+    D4 = P3_10,
+    D5 = P3_14,
+    D6 = P3_1,
+    D7 = P1_22,
+    D8 = P4_7,
+    D9 = P2_1,
+    D10 = P3_30,
+    D11 = P3_21,
+    D12 = P3_22,
+    D13 = P3_20,
+    D14 = P3_23,
+    D15 = P3_24,
+
+    I2C_SCL = D15,
+    I2C_SDA = D14,
+
+    A0 = P0_16,
+    A1 = P0_31,
+    A2 = P1_0,
+    A3 = P2_0,
+    A4 = P3_4,
+    A5 = P1_1,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp   = 2,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: LPC54608J512
+package_id: LPC54608J512ET180
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+board: LPCXpresso54608
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockPLL180M **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockPLL180M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: SYSPLL_clock.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+settings:
+- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+sources:
+- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL180M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
+
+    /*!< Set up SYS PLL */
+    const pll_setup_t pllSetup = {
+        .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
+        .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
+        .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
+        .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+        .pllRate = 180000000U,
+        .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
+    CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */
+    CLOCK_SetPLLFreq(&pllSetup);          /*!< Configure PLL to the desired value */
+    POWER_SetVoltageForFreq(
+        180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */
+    CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK);         /*!< Switch System clock to SYS PLL 180MHz */
+
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+#define BOARD_BootClockRUN BOARD_BootClockFROHF48M
+
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK   12000000U    /*!< Core clock frequency:12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK   48000000U    /*!< Core clock frequency:48000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK   96000000U    /*!< Core clock frequency:96000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockPLL180M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#define BOARD_BootClockPLL180M_CORE_CLOCK   180000000U    /*!< Core clock frequency:180000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL180M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+#endif /* _CLOCK_CONFIG_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/device.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,39 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define NUMBER_OF_GPIO_INTS    8
+
+#define APP_EXCLUDE_FROM_DEEPSLEEP                                                                        \
+    (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK |  SYSCON_PDRUNCFG_PDEN_SRAMX_MASK |                               \
+     SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+
+/* Defines used by the sleep code */
+#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M
+#define LPC_CLOCK_RUN          BOARD_BootClockFROHF48M
+
+#define DEVICE_ID_LENGTH       24
+
+
+
+
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/mbed_overrides.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "clock_config.h"
+#include "fsl_emc.h"
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* The SDRAM timing. */
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
+#define SDRAM_TRP_NS (18u)
+#define SDRAM_TRAS_NS (42u)
+#define SDRAM_TSREX_NS (67u)
+#define SDRAM_TAPR_NS (18u)
+#define SDRAM_TWRDELT_NS (6u)
+#define SDRAM_TRC_NS (60u)
+#define SDRAM_RFC_NS (60u)
+#define SDRAM_XSR_NS (67u)
+#define SDRAM_RRD_NS (12u)
+#define SDRAM_MRD_NCLK (2u)
+#define SDRAM_RAS_NCLK (2u)
+#define SDRAM_MODEREG_VALUE (0x23u)
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+
+// called before main
+void mbed_sdk_init()
+{
+    BOARD_BootClockFROHF48M();
+}
+
+// Change the NMI pin to an input. This allows NMI pin to
+//  be used as a low power mode wakeup.  The application will
+//  need to change the pin back to NMI_b or wakeup only occurs once!
+void NMI_Handler(void)
+{
+    //gpio_t gpio;
+    //gpio_init_in(&gpio, PTA4);
+}
+
+// Enable the RTC oscillator if available on the board
+void rtc_setup_oscillator(void)
+{
+    /* Enable the RTC 32K Oscillator */
+    SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
+}
+
+void ADC_ClockPower_Configuration(void)
+{
+    /* SYSCON power. */
+    POWER_DisablePD(kPDRUNCFG_PD_VDDA);    /* Power on VDDA. */
+    POWER_DisablePD(kPDRUNCFG_PD_ADC0);    /* Power on the ADC converter. */
+    POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */
+    POWER_DisablePD(kPDRUNCFG_PD_VREFP);   /* Power on the reference voltage source. */
+    POWER_DisablePD(kPDRUNCFG_PD_TS);      /* Power on the temperature sensor. */
+
+    /* Enable the clock. */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+    /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */
+    /* Sync clock source is not used. Using sync clock source and would be divided by 2.
+     * The divider would be set when configuring the converter.
+     */
+    CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */
+}
+
+/* Initialize the external memory. */
+void BOARD_InitSDRAM(void)
+{
+    emc_basic_config_t basicConfig;
+    emc_dynamic_timing_config_t dynTiming;
+    emc_dynamic_chip_config_t dynChipConfig;
+
+    /* Basic configuration. */
+    basicConfig.endian = kEMC_LittleEndian;
+    basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
+    /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
+     * If you change the divide to 0 and EMC clock is larger than 100M
+     * please take refer to emc.dox to adjust EMC clock delay.
+     */
+    basicConfig.emcClkDiv = 1;
+    /* Dynamic memory timing configuration. */
+    dynTiming.readConfig = kEMC_Cmddelay;
+    dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
+    dynTiming.tRp_Ns = SDRAM_TRP_NS;
+    dynTiming.tRas_Ns = SDRAM_TRAS_NS;
+    dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
+    dynTiming.tApr_Ns = SDRAM_TAPR_NS;
+    dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */
+    dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
+    dynTiming.tRc_Ns = SDRAM_TRC_NS;
+    dynTiming.tRfc_Ns = SDRAM_RFC_NS;
+    dynTiming.tXsr_Ns = SDRAM_XSR_NS;
+    dynTiming.tRrd_Ns = SDRAM_RRD_NS;
+    dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
+    /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
+    dynChipConfig.chipIndex = 0;
+    dynChipConfig.dynamicDevice = kEMC_Sdram;
+    dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
+    dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
+    dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
+    dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
+    /* EMC Basic configuration. */
+    EMC_Init(EMC, &basicConfig);
+    /* EMC Dynamc memory configuration. */
+    EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,12371 @@
+/*
+** ###################################################################
+**     Processors:          LPC54608J512BD208
+**                          LPC54608J512ET180
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b170214
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for LPC54608
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54608.h
+ * @version 1.1
+ * @date 2016-11-25
+ * @brief CMSIS Peripheral Access Layer for LPC54608
+ *
+ * CMSIS Peripheral Access Layer for LPC54608
+ */
+
+#ifndef _LPC54608_H_
+#define _LPC54608_H_                             /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 73                 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect */
+  DMA0_IRQn                    = 1,                /**< DMA controller */
+  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
+  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
+  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
+  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
+  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
+  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
+  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
+  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
+  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
+  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
+  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
+  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
+  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+  ADC0_SEQA_IRQn               = 22,               /**< ADC0 sequence A completion. */
+  ADC0_SEQB_IRQn               = 23,               /**< ADC0 sequence B completion. */
+  ADC0_THCMP_IRQn              = 24,               /**< ADC0 threshold compare and error. */
+  DMIC0_IRQn                   = 25,               /**< Digital microphone and DMIC subsystem */
+  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
+  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
+  USB0_IRQn                    = 28,               /**< USB device */
+  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt */
+  Reserved47_IRQn              = 31,               /**< Reserved interrupt */
+  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
+  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
+  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
+  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
+  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
+  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
+  RIT_IRQn                     = 38,               /**< Repetitive Interrupt Timer */
+  SPIFI0_IRQn                  = 39,               /**< SPI flash interface */
+  FLEXCOMM8_IRQn               = 40,               /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+  FLEXCOMM9_IRQn               = 41,               /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+  SDIO_IRQn                    = 42,               /**< SD/MMC  */
+  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
+  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
+  CAN1_IRQ0_IRQn               = 45,               /**< CAN1 interrupt0 */
+  CAN1_IRQ1_IRQn               = 46,               /**< CAN1 interrupt1 */
+  USB1_IRQn                    = 47,               /**< USB1 interrupt */
+  USB1_NEEDCLK_IRQn            = 48,               /**< USB1 activity */
+  ETHERNET_IRQn                = 49,               /**< Ethernet */
+  ETHERNET_PMT_IRQn            = 50,               /**< Ethernet power management interrupt */
+  ETHERNET_MACLP_IRQn          = 51,               /**< Ethernet MAC interrupt */
+  EEPROM_IRQn                  = 52,               /**< EEPROM interrupt */
+  LCD_IRQn                     = 53,               /**< LCD interrupt */
+  SHA_IRQn                     = 54,               /**< SHA interrupt */
+  SMARTCARD0_IRQn              = 55,               /**< Smart card 0 interrupt */
+  SMARTCARD1_IRQn              = 56                /**< Smart card 1 interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_LPC54608.h"           /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+  __IO uint32_t INSEL;                             /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+  __IO uint32_t SEQ_CTRL[2];                       /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+  __I  uint32_t SEQ_GDAT[2];                       /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t DAT[12];                           /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+  __IO uint32_t THR0_LOW;                          /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+  __IO uint32_t THR1_LOW;                          /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+  __IO uint32_t THR0_HIGH;                         /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+  __IO uint32_t THR1_HIGH;                         /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+  __IO uint32_t CHAN_THRSEL;                       /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+  __IO uint32_t INTEN;                             /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+  __IO uint32_t FLAGS;                             /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+  __IO uint32_t STARTUP;                           /**< ADC Startup register., offset: 0x6C */
+  __IO uint32_t CALIB;                             /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+#define ADC_CTRL_CLKDIV_MASK                     (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT                    (0U)
+#define ADC_CTRL_CLKDIV(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK                   (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT                  (8U)
+#define ADC_CTRL_ASYNMODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK                      (0x600U)
+#define ADC_CTRL_RESOL_SHIFT                     (9U)
+#define ADC_CTRL_RESOL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK                  (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT                 (11U)
+#define ADC_CTRL_BYPASSCAL(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK                      (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT                     (12U)
+#define ADC_CTRL_TSAMP(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+#define ADC_INSEL_SEL_MASK                       (0x3U)
+#define ADC_INSEL_SEL_SHIFT                      (0U)
+#define ADC_INSEL_SEL(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+#define ADC_SEQ_CTRL_CHANNELS_MASK               (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT              (0U)
+#define ADC_SEQ_CTRL_CHANNELS(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK                (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT               (12U)
+#define ADC_SEQ_CTRL_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK                (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT               (18U)
+#define ADC_SEQ_CTRL_TRIGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK             (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT            (19U)
+#define ADC_SEQ_CTRL_SYNCBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK                  (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT                 (26U)
+#define ADC_SEQ_CTRL_START(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK                  (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT                 (27U)
+#define ADC_SEQ_CTRL_BURST(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK             (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT            (28U)
+#define ADC_SEQ_CTRL_SINGLESTEP(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK                (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT               (29U)
+#define ADC_SEQ_CTRL_LOWPRIO(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK                   (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT                  (30U)
+#define ADC_SEQ_CTRL_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK                (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT               (31U)
+#define ADC_SEQ_CTRL_SEQ_ENA(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT                       (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+#define ADC_SEQ_GDAT_RESULT_MASK                 (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT                (4U)
+#define ADC_SEQ_GDAT_RESULT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK             (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT            (16U)
+#define ADC_SEQ_GDAT_THCMPRANGE(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK             (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT            (18U)
+#define ADC_SEQ_GDAT_THCMPCROSS(x)               (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK                    (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT                   (26U)
+#define ADC_SEQ_GDAT_CHN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK                (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT               (30U)
+#define ADC_SEQ_GDAT_OVERRUN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK              (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT             (31U)
+#define ADC_SEQ_GDAT_DATAVALID(x)                (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT                       (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+#define ADC_DAT_RESULT_MASK                      (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT                     (4U)
+#define ADC_DAT_RESULT(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK                  (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT                 (16U)
+#define ADC_DAT_THCMPRANGE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK                  (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT                 (18U)
+#define ADC_DAT_THCMPCROSS(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK                     (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT                    (26U)
+#define ADC_DAT_CHANNEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK                     (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT                    (30U)
+#define ADC_DAT_OVERRUN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK                   (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT                  (31U)
+#define ADC_DAT_DATAVALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT                            (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT                (4U)
+#define ADC_THR0_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_LOW_THRLOW_MASK                 (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT                (4U)
+#define ADC_THR1_LOW_THRLOW(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT              (4U)
+#define ADC_THR0_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_HIGH_THRHIGH_MASK               (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT              (4U)
+#define ADC_THR1_HIGH_THRHIGH(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK          (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT         (0U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK          (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT         (1U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK          (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT         (2U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK          (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT         (3U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK          (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT         (4U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK          (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT         (5U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK          (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT         (6U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK          (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT         (7U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK          (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT         (8U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK          (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT         (9U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x)            (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK         (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT        (10U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK         (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT        (11U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x)           (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+#define ADC_INTEN_SEQA_INTEN_MASK                (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT               (0U)
+#define ADC_INTEN_SEQA_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK                (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT               (1U)
+#define ADC_INTEN_SEQB_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK                 (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT                (2U)
+#define ADC_INTEN_OVR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK               (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT              (3U)
+#define ADC_INTEN_ADCMPINTEN0(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK               (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT              (5U)
+#define ADC_INTEN_ADCMPINTEN1(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK               (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT              (7U)
+#define ADC_INTEN_ADCMPINTEN2(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK               (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT              (9U)
+#define ADC_INTEN_ADCMPINTEN3(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK               (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT              (11U)
+#define ADC_INTEN_ADCMPINTEN4(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK               (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT              (13U)
+#define ADC_INTEN_ADCMPINTEN5(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK               (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT              (15U)
+#define ADC_INTEN_ADCMPINTEN6(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK               (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT              (17U)
+#define ADC_INTEN_ADCMPINTEN7(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK               (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT              (19U)
+#define ADC_INTEN_ADCMPINTEN8(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK               (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT              (21U)
+#define ADC_INTEN_ADCMPINTEN9(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK              (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT             (23U)
+#define ADC_INTEN_ADCMPINTEN10(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK              (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT             (25U)
+#define ADC_INTEN_ADCMPINTEN11(x)                (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+#define ADC_FLAGS_THCMP0_MASK                    (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT                   (0U)
+#define ADC_FLAGS_THCMP0(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK                    (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT                   (1U)
+#define ADC_FLAGS_THCMP1(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK                    (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT                   (2U)
+#define ADC_FLAGS_THCMP2(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK                    (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT                   (3U)
+#define ADC_FLAGS_THCMP3(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK                    (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT                   (4U)
+#define ADC_FLAGS_THCMP4(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK                    (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT                   (5U)
+#define ADC_FLAGS_THCMP5(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK                    (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT                   (6U)
+#define ADC_FLAGS_THCMP6(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK                    (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT                   (7U)
+#define ADC_FLAGS_THCMP7(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK                    (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT                   (8U)
+#define ADC_FLAGS_THCMP8(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK                    (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT                   (9U)
+#define ADC_FLAGS_THCMP9(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK                   (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT                  (10U)
+#define ADC_FLAGS_THCMP10(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK                   (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT                  (11U)
+#define ADC_FLAGS_THCMP11(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK                  (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT                 (12U)
+#define ADC_FLAGS_OVERRUN0(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK                  (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT                 (13U)
+#define ADC_FLAGS_OVERRUN1(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK                  (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT                 (14U)
+#define ADC_FLAGS_OVERRUN2(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK                  (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT                 (15U)
+#define ADC_FLAGS_OVERRUN3(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK                  (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT                 (16U)
+#define ADC_FLAGS_OVERRUN4(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK                  (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT                 (17U)
+#define ADC_FLAGS_OVERRUN5(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK                  (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT                 (18U)
+#define ADC_FLAGS_OVERRUN6(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK                  (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT                 (19U)
+#define ADC_FLAGS_OVERRUN7(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK                  (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT                 (20U)
+#define ADC_FLAGS_OVERRUN8(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK                  (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT                 (21U)
+#define ADC_FLAGS_OVERRUN9(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK                 (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT                (22U)
+#define ADC_FLAGS_OVERRUN10(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK                 (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT                (23U)
+#define ADC_FLAGS_OVERRUN11(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK                  (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT                 (24U)
+#define ADC_FLAGS_SEQA_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK                  (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT                 (25U)
+#define ADC_FLAGS_SEQB_OVR(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK                  (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT                 (28U)
+#define ADC_FLAGS_SEQA_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK                  (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT                 (29U)
+#define ADC_FLAGS_SEQB_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK                 (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT                (30U)
+#define ADC_FLAGS_THCMP_INT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK                   (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT                  (31U)
+#define ADC_FLAGS_OVR_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+
+/*! @name STARTUP - ADC Startup register. */
+#define ADC_STARTUP_ADC_ENA_MASK                 (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT                (0U)
+#define ADC_STARTUP_ADC_ENA(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK                (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT               (1U)
+#define ADC_STARTUP_ADC_INIT(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+
+/*! @name CALIB - ADC Calibration register. */
+#define ADC_CALIB_CALIB_MASK                     (0x1U)
+#define ADC_CALIB_CALIB_SHIFT                    (0U)
+#define ADC_CALIB_CALIB(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK                   (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT                  (1U)
+#define ADC_CALIB_CALREQD(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK                  (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT                 (2U)
+#define ADC_CALIB_CALVALUE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS                             { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS                           { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASYNCPRESETCTRL;                   /**< Async peripheral reset control, offset: 0x0 */
+  __O  uint32_t ASYNCPRESETCTRLSET;                /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+  __O  uint32_t ASYNCPRESETCTRLCLR;                /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASYNCAPBCLKCTRL;                   /**< Async peripheral clock control, offset: 0x10 */
+  __O  uint32_t ASYNCAPBCLKCTRLSET;                /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+  __O  uint32_t ASYNCAPBCLKCTRLCLR;                /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ASYNCAPBCLKSELA;                   /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASYNC_SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x)  (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK    (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT   (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x)      (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE                        (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON                             ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS                  { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS                   { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t TEST;                              /**< Test Register, offset: 0x10 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t CCCR;                              /**< CC Control Register, offset: 0x18 */
+  __IO uint32_t NBTP;                              /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
+  __IO uint32_t TSCC;                              /**< Timestamp Counter Configuration, offset: 0x20 */
+  __IO uint32_t TSCV;                              /**< Timestamp Counter Value, offset: 0x24 */
+  __IO uint32_t TOCC;                              /**< Timeout Counter Configuration, offset: 0x28 */
+  __I  uint32_t TOCV;                              /**< Timeout Counter Value, offset: 0x2C */
+       uint8_t RESERVED_2[16];
+  __I  uint32_t ECR;                               /**< Error Counter Register, offset: 0x40 */
+  __I  uint32_t PSR;                               /**< Protocol Status Register, offset: 0x44 */
+  __IO uint32_t TDCR;                              /**< Transmitter Delay Compensator Register, offset: 0x48 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t IR;                                /**< Interrupt Register, offset: 0x50 */
+  __IO uint32_t IE;                                /**< Interrupt Enable, offset: 0x54 */
+  __IO uint32_t ILS;                               /**< Interrupt Line Select, offset: 0x58 */
+  __IO uint32_t ILE;                               /**< Interrupt Line Enable, offset: 0x5C */
+       uint8_t RESERVED_4[32];
+  __IO uint32_t GFC;                               /**< Global Filter Configuration, offset: 0x80 */
+  __IO uint32_t SIDFC;                             /**< Standard ID Filter Configuration, offset: 0x84 */
+  __IO uint32_t XIDFC;                             /**< Extended ID Filter Configuration, offset: 0x88 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t XIDAM;                             /**< Extended ID AND Mask, offset: 0x90 */
+  __I  uint32_t HPMS;                              /**< High Priority Message Status, offset: 0x94 */
+  __IO uint32_t NDAT1;                             /**< New Data 1, offset: 0x98 */
+  __IO uint32_t NDAT2;                             /**< New Data 2, offset: 0x9C */
+  __IO uint32_t RXF0C;                             /**< Rx FIFO 0 Configuration, offset: 0xA0 */
+  __IO uint32_t RXF0S;                             /**< Rx FIFO 0 Status, offset: 0xA4 */
+  __IO uint32_t RXF0A;                             /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
+  __IO uint32_t RXBC;                              /**< Rx Buffer Configuration, offset: 0xAC */
+  __IO uint32_t RXF1C;                             /**< Rx FIFO 1 Configuration, offset: 0xB0 */
+  __I  uint32_t RXF1S;                             /**< Rx FIFO 1 Status, offset: 0xB4 */
+  __IO uint32_t RXF1A;                             /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
+  __IO uint32_t RXESC;                             /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
+  __IO uint32_t TXBC;                              /**< Tx Buffer Configuration, offset: 0xC0 */
+  __IO uint32_t TXFQS;                             /**< Tx FIFO/Queue Status, offset: 0xC4 */
+  __IO uint32_t TXESC;                             /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
+  __IO uint32_t TXBRP;                             /**< Tx Buffer Request Pending, offset: 0xCC */
+  __IO uint32_t TXBAR;                             /**< Tx Buffer Add Request, offset: 0xD0 */
+  __IO uint32_t TXBCR;                             /**< Tx Buffer Cancellation Request, offset: 0xD4 */
+  __IO uint32_t TXBTO;                             /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
+  __IO uint32_t TXBCF;                             /**< Tx Buffer Cancellation Finished, offset: 0xDC */
+  __IO uint32_t TXBTIE;                            /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
+  __IO uint32_t TXBCIE;                            /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
+       uint8_t RESERVED_6[8];
+  __IO uint32_t TXEFC;                             /**< Tx Event FIFO Configuration, offset: 0xF0 */
+  __I  uint32_t TXEFS;                             /**< Tx Event FIFO Status, offset: 0xF4 */
+  __IO uint32_t TXEFA;                             /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
+       uint8_t RESERVED_7[260];
+  __IO uint32_t MRBA;                              /**< CAN Message RAM Base Address, offset: 0x200 */
+       uint8_t RESERVED_8[508];
+  __IO uint32_t ETSCC;                             /**< External Timestamp Counter Configuration, offset: 0x400 */
+       uint8_t RESERVED_9[508];
+  __IO uint32_t ETSCV;                             /**< External Timestamp Counter Value, offset: 0x600 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name TEST - Test Register */
+#define CAN_TEST_LBCK_MASK                       (0x10U)
+#define CAN_TEST_LBCK_SHIFT                      (4U)
+#define CAN_TEST_LBCK(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
+#define CAN_TEST_TX_MASK                         (0x60U)
+#define CAN_TEST_TX_SHIFT                        (5U)
+#define CAN_TEST_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
+#define CAN_TEST_RX_MASK                         (0x80U)
+#define CAN_TEST_RX_SHIFT                        (7U)
+#define CAN_TEST_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
+
+/*! @name CCCR - CC Control Register */
+#define CAN_CCCR_INIT_MASK                       (0x1U)
+#define CAN_CCCR_INIT_SHIFT                      (0U)
+#define CAN_CCCR_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
+#define CAN_CCCR_CCE_MASK                        (0x2U)
+#define CAN_CCCR_CCE_SHIFT                       (1U)
+#define CAN_CCCR_CCE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
+#define CAN_CCCR_ASM_MASK                        (0x4U)
+#define CAN_CCCR_ASM_SHIFT                       (2U)
+#define CAN_CCCR_ASM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
+#define CAN_CCCR_CSA_MASK                        (0x8U)
+#define CAN_CCCR_CSA_SHIFT                       (3U)
+#define CAN_CCCR_CSA(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
+#define CAN_CCCR_CSR_MASK                        (0x10U)
+#define CAN_CCCR_CSR_SHIFT                       (4U)
+#define CAN_CCCR_CSR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
+#define CAN_CCCR_MON_MASK                        (0x20U)
+#define CAN_CCCR_MON_SHIFT                       (5U)
+#define CAN_CCCR_MON(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
+#define CAN_CCCR_DAR_MASK                        (0x40U)
+#define CAN_CCCR_DAR_SHIFT                       (6U)
+#define CAN_CCCR_DAR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
+#define CAN_CCCR_TEST_MASK                       (0x80U)
+#define CAN_CCCR_TEST_SHIFT                      (7U)
+#define CAN_CCCR_TEST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
+#define CAN_CCCR_PXHD_MASK                       (0x1000U)
+#define CAN_CCCR_PXHD_SHIFT                      (12U)
+#define CAN_CCCR_PXHD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
+#define CAN_CCCR_EFBI_MASK                       (0x2000U)
+#define CAN_CCCR_EFBI_SHIFT                      (13U)
+#define CAN_CCCR_EFBI(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
+#define CAN_CCCR_TXP_MASK                        (0x4000U)
+#define CAN_CCCR_TXP_SHIFT                       (14U)
+#define CAN_CCCR_TXP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
+
+/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
+#define CAN_NBTP_NTSEG2_MASK                     (0x7FU)
+#define CAN_NBTP_NTSEG2_SHIFT                    (0U)
+#define CAN_NBTP_NTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
+#define CAN_NBTP_NTSEG1_MASK                     (0xFF00U)
+#define CAN_NBTP_NTSEG1_SHIFT                    (8U)
+#define CAN_NBTP_NTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
+#define CAN_NBTP_NBRP_MASK                       (0x1FF0000U)
+#define CAN_NBTP_NBRP_SHIFT                      (16U)
+#define CAN_NBTP_NBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
+#define CAN_NBTP_NSJW_MASK                       (0xFE000000U)
+#define CAN_NBTP_NSJW_SHIFT                      (25U)
+#define CAN_NBTP_NSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
+
+/*! @name TSCC - Timestamp Counter Configuration */
+#define CAN_TSCC_TSS_MASK                        (0x3U)
+#define CAN_TSCC_TSS_SHIFT                       (0U)
+#define CAN_TSCC_TSS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
+#define CAN_TSCC_TCP_MASK                        (0xF0000U)
+#define CAN_TSCC_TCP_SHIFT                       (16U)
+#define CAN_TSCC_TCP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
+
+/*! @name TSCV - Timestamp Counter Value */
+#define CAN_TSCV_TSC_MASK                        (0xFFFFU)
+#define CAN_TSCV_TSC_SHIFT                       (0U)
+#define CAN_TSCV_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
+
+/*! @name TOCC - Timeout Counter Configuration */
+#define CAN_TOCC_ETOC_MASK                       (0x1U)
+#define CAN_TOCC_ETOC_SHIFT                      (0U)
+#define CAN_TOCC_ETOC(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
+#define CAN_TOCC_TOS_MASK                        (0x6U)
+#define CAN_TOCC_TOS_SHIFT                       (1U)
+#define CAN_TOCC_TOS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
+#define CAN_TOCC_TOP_MASK                        (0xFFFF0000U)
+#define CAN_TOCC_TOP_SHIFT                       (16U)
+#define CAN_TOCC_TOP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
+
+/*! @name TOCV - Timeout Counter Value */
+#define CAN_TOCV_TOC_MASK                        (0xFFFFU)
+#define CAN_TOCV_TOC_SHIFT                       (0U)
+#define CAN_TOCV_TOC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
+
+/*! @name ECR - Error Counter Register */
+#define CAN_ECR_TEC_MASK                         (0xFFU)
+#define CAN_ECR_TEC_SHIFT                        (0U)
+#define CAN_ECR_TEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
+#define CAN_ECR_REC_MASK                         (0x7F00U)
+#define CAN_ECR_REC_SHIFT                        (8U)
+#define CAN_ECR_REC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
+#define CAN_ECR_RP_MASK                          (0x8000U)
+#define CAN_ECR_RP_SHIFT                         (15U)
+#define CAN_ECR_RP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
+#define CAN_ECR_CEL_MASK                         (0xFF0000U)
+#define CAN_ECR_CEL_SHIFT                        (16U)
+#define CAN_ECR_CEL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
+
+/*! @name PSR - Protocol Status Register */
+#define CAN_PSR_LEC_MASK                         (0x7U)
+#define CAN_PSR_LEC_SHIFT                        (0U)
+#define CAN_PSR_LEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
+#define CAN_PSR_ACT_MASK                         (0x18U)
+#define CAN_PSR_ACT_SHIFT                        (3U)
+#define CAN_PSR_ACT(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
+#define CAN_PSR_EP_MASK                          (0x20U)
+#define CAN_PSR_EP_SHIFT                         (5U)
+#define CAN_PSR_EP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
+#define CAN_PSR_EW_MASK                          (0x40U)
+#define CAN_PSR_EW_SHIFT                         (6U)
+#define CAN_PSR_EW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
+#define CAN_PSR_BO_MASK                          (0x80U)
+#define CAN_PSR_BO_SHIFT                         (7U)
+#define CAN_PSR_BO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
+#define CAN_PSR_PXE_MASK                         (0x4000U)
+#define CAN_PSR_PXE_SHIFT                        (14U)
+#define CAN_PSR_PXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
+#define CAN_PSR_TDCV_MASK                        (0x7F0000U)
+#define CAN_PSR_TDCV_SHIFT                       (16U)
+#define CAN_PSR_TDCV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
+
+/*! @name TDCR - Transmitter Delay Compensator Register */
+#define CAN_TDCR_TDCF_MASK                       (0x7FU)
+#define CAN_TDCR_TDCF_SHIFT                      (0U)
+#define CAN_TDCR_TDCF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
+#define CAN_TDCR_TDCO_MASK                       (0x7F00U)
+#define CAN_TDCR_TDCO_SHIFT                      (8U)
+#define CAN_TDCR_TDCO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
+
+/*! @name IR - Interrupt Register */
+#define CAN_IR_RF0N_MASK                         (0x1U)
+#define CAN_IR_RF0N_SHIFT                        (0U)
+#define CAN_IR_RF0N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
+#define CAN_IR_RF0W_MASK                         (0x2U)
+#define CAN_IR_RF0W_SHIFT                        (1U)
+#define CAN_IR_RF0W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
+#define CAN_IR_RF0F_MASK                         (0x4U)
+#define CAN_IR_RF0F_SHIFT                        (2U)
+#define CAN_IR_RF0F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
+#define CAN_IR_RF0L_MASK                         (0x8U)
+#define CAN_IR_RF0L_SHIFT                        (3U)
+#define CAN_IR_RF0L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
+#define CAN_IR_RF1N_MASK                         (0x10U)
+#define CAN_IR_RF1N_SHIFT                        (4U)
+#define CAN_IR_RF1N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
+#define CAN_IR_RF1W_MASK                         (0x20U)
+#define CAN_IR_RF1W_SHIFT                        (5U)
+#define CAN_IR_RF1W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
+#define CAN_IR_RF1F_MASK                         (0x40U)
+#define CAN_IR_RF1F_SHIFT                        (6U)
+#define CAN_IR_RF1F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
+#define CAN_IR_RF1L_MASK                         (0x80U)
+#define CAN_IR_RF1L_SHIFT                        (7U)
+#define CAN_IR_RF1L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
+#define CAN_IR_HPM_MASK                          (0x100U)
+#define CAN_IR_HPM_SHIFT                         (8U)
+#define CAN_IR_HPM(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
+#define CAN_IR_TC_MASK                           (0x200U)
+#define CAN_IR_TC_SHIFT                          (9U)
+#define CAN_IR_TC(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
+#define CAN_IR_TCF_MASK                          (0x400U)
+#define CAN_IR_TCF_SHIFT                         (10U)
+#define CAN_IR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
+#define CAN_IR_TFE_MASK                          (0x800U)
+#define CAN_IR_TFE_SHIFT                         (11U)
+#define CAN_IR_TFE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
+#define CAN_IR_TEFN_MASK                         (0x1000U)
+#define CAN_IR_TEFN_SHIFT                        (12U)
+#define CAN_IR_TEFN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
+#define CAN_IR_TEFW_MASK                         (0x2000U)
+#define CAN_IR_TEFW_SHIFT                        (13U)
+#define CAN_IR_TEFW(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
+#define CAN_IR_TEFF_MASK                         (0x4000U)
+#define CAN_IR_TEFF_SHIFT                        (14U)
+#define CAN_IR_TEFF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
+#define CAN_IR_TEFL_MASK                         (0x8000U)
+#define CAN_IR_TEFL_SHIFT                        (15U)
+#define CAN_IR_TEFL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
+#define CAN_IR_TSW_MASK                          (0x10000U)
+#define CAN_IR_TSW_SHIFT                         (16U)
+#define CAN_IR_TSW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
+#define CAN_IR_MRAF_MASK                         (0x20000U)
+#define CAN_IR_MRAF_SHIFT                        (17U)
+#define CAN_IR_MRAF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
+#define CAN_IR_TOO_MASK                          (0x40000U)
+#define CAN_IR_TOO_SHIFT                         (18U)
+#define CAN_IR_TOO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
+#define CAN_IR_DRX_MASK                          (0x80000U)
+#define CAN_IR_DRX_SHIFT                         (19U)
+#define CAN_IR_DRX(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
+#define CAN_IR_BEC_MASK                          (0x100000U)
+#define CAN_IR_BEC_SHIFT                         (20U)
+#define CAN_IR_BEC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
+#define CAN_IR_BEU_MASK                          (0x200000U)
+#define CAN_IR_BEU_SHIFT                         (21U)
+#define CAN_IR_BEU(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
+#define CAN_IR_ELO_MASK                          (0x400000U)
+#define CAN_IR_ELO_SHIFT                         (22U)
+#define CAN_IR_ELO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
+#define CAN_IR_EP_MASK                           (0x800000U)
+#define CAN_IR_EP_SHIFT                          (23U)
+#define CAN_IR_EP(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
+#define CAN_IR_EW_MASK                           (0x1000000U)
+#define CAN_IR_EW_SHIFT                          (24U)
+#define CAN_IR_EW(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
+#define CAN_IR_BO_MASK                           (0x2000000U)
+#define CAN_IR_BO_SHIFT                          (25U)
+#define CAN_IR_BO(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
+#define CAN_IR_WDI_MASK                          (0x4000000U)
+#define CAN_IR_WDI_SHIFT                         (26U)
+#define CAN_IR_WDI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
+#define CAN_IR_PEA_MASK                          (0x8000000U)
+#define CAN_IR_PEA_SHIFT                         (27U)
+#define CAN_IR_PEA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
+#define CAN_IR_PED_MASK                          (0x10000000U)
+#define CAN_IR_PED_SHIFT                         (28U)
+#define CAN_IR_PED(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
+#define CAN_IR_ARA_MASK                          (0x20000000U)
+#define CAN_IR_ARA_SHIFT                         (29U)
+#define CAN_IR_ARA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
+
+/*! @name IE - Interrupt Enable */
+#define CAN_IE_RF0NE_MASK                        (0x1U)
+#define CAN_IE_RF0NE_SHIFT                       (0U)
+#define CAN_IE_RF0NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
+#define CAN_IE_RF0WE_MASK                        (0x2U)
+#define CAN_IE_RF0WE_SHIFT                       (1U)
+#define CAN_IE_RF0WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
+#define CAN_IE_RF0FE_MASK                        (0x4U)
+#define CAN_IE_RF0FE_SHIFT                       (2U)
+#define CAN_IE_RF0FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
+#define CAN_IE_RF0LE_MASK                        (0x8U)
+#define CAN_IE_RF0LE_SHIFT                       (3U)
+#define CAN_IE_RF0LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
+#define CAN_IE_RF1NE_MASK                        (0x10U)
+#define CAN_IE_RF1NE_SHIFT                       (4U)
+#define CAN_IE_RF1NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
+#define CAN_IE_RF1WE_MASK                        (0x20U)
+#define CAN_IE_RF1WE_SHIFT                       (5U)
+#define CAN_IE_RF1WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
+#define CAN_IE_RF1FE_MASK                        (0x40U)
+#define CAN_IE_RF1FE_SHIFT                       (6U)
+#define CAN_IE_RF1FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
+#define CAN_IE_RF1LE_MASK                        (0x80U)
+#define CAN_IE_RF1LE_SHIFT                       (7U)
+#define CAN_IE_RF1LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
+#define CAN_IE_HPME_MASK                         (0x100U)
+#define CAN_IE_HPME_SHIFT                        (8U)
+#define CAN_IE_HPME(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
+#define CAN_IE_TCE_MASK                          (0x200U)
+#define CAN_IE_TCE_SHIFT                         (9U)
+#define CAN_IE_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
+#define CAN_IE_TCFE_MASK                         (0x400U)
+#define CAN_IE_TCFE_SHIFT                        (10U)
+#define CAN_IE_TCFE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
+#define CAN_IE_TFEE_MASK                         (0x800U)
+#define CAN_IE_TFEE_SHIFT                        (11U)
+#define CAN_IE_TFEE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
+#define CAN_IE_TEFNE_MASK                        (0x1000U)
+#define CAN_IE_TEFNE_SHIFT                       (12U)
+#define CAN_IE_TEFNE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
+#define CAN_IE_TEFWE_MASK                        (0x2000U)
+#define CAN_IE_TEFWE_SHIFT                       (13U)
+#define CAN_IE_TEFWE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
+#define CAN_IE_TEFFE_MASK                        (0x4000U)
+#define CAN_IE_TEFFE_SHIFT                       (14U)
+#define CAN_IE_TEFFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
+#define CAN_IE_TEFLE_MASK                        (0x8000U)
+#define CAN_IE_TEFLE_SHIFT                       (15U)
+#define CAN_IE_TEFLE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
+#define CAN_IE_TSWE_MASK                         (0x10000U)
+#define CAN_IE_TSWE_SHIFT                        (16U)
+#define CAN_IE_TSWE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
+#define CAN_IE_MRAFE_MASK                        (0x20000U)
+#define CAN_IE_MRAFE_SHIFT                       (17U)
+#define CAN_IE_MRAFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
+#define CAN_IE_TOOE_MASK                         (0x40000U)
+#define CAN_IE_TOOE_SHIFT                        (18U)
+#define CAN_IE_TOOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
+#define CAN_IE_DRXE_MASK                         (0x80000U)
+#define CAN_IE_DRXE_SHIFT                        (19U)
+#define CAN_IE_DRXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
+#define CAN_IE_BECE_MASK                         (0x100000U)
+#define CAN_IE_BECE_SHIFT                        (20U)
+#define CAN_IE_BECE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
+#define CAN_IE_BEUE_MASK                         (0x200000U)
+#define CAN_IE_BEUE_SHIFT                        (21U)
+#define CAN_IE_BEUE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
+#define CAN_IE_ELOE_MASK                         (0x400000U)
+#define CAN_IE_ELOE_SHIFT                        (22U)
+#define CAN_IE_ELOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
+#define CAN_IE_EPE_MASK                          (0x800000U)
+#define CAN_IE_EPE_SHIFT                         (23U)
+#define CAN_IE_EPE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
+#define CAN_IE_EWE_MASK                          (0x1000000U)
+#define CAN_IE_EWE_SHIFT                         (24U)
+#define CAN_IE_EWE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
+#define CAN_IE_BOE_MASK                          (0x2000000U)
+#define CAN_IE_BOE_SHIFT                         (25U)
+#define CAN_IE_BOE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
+#define CAN_IE_WDIE_MASK                         (0x4000000U)
+#define CAN_IE_WDIE_SHIFT                        (26U)
+#define CAN_IE_WDIE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
+#define CAN_IE_PEAE_MASK                         (0x8000000U)
+#define CAN_IE_PEAE_SHIFT                        (27U)
+#define CAN_IE_PEAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
+#define CAN_IE_PEDE_MASK                         (0x10000000U)
+#define CAN_IE_PEDE_SHIFT                        (28U)
+#define CAN_IE_PEDE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
+#define CAN_IE_ARAE_MASK                         (0x20000000U)
+#define CAN_IE_ARAE_SHIFT                        (29U)
+#define CAN_IE_ARAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
+
+/*! @name ILS - Interrupt Line Select */
+#define CAN_ILS_RF0NL_MASK                       (0x1U)
+#define CAN_ILS_RF0NL_SHIFT                      (0U)
+#define CAN_ILS_RF0NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
+#define CAN_ILS_RF0WL_MASK                       (0x2U)
+#define CAN_ILS_RF0WL_SHIFT                      (1U)
+#define CAN_ILS_RF0WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
+#define CAN_ILS_RF0FL_MASK                       (0x4U)
+#define CAN_ILS_RF0FL_SHIFT                      (2U)
+#define CAN_ILS_RF0FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
+#define CAN_ILS_RF0LL_MASK                       (0x8U)
+#define CAN_ILS_RF0LL_SHIFT                      (3U)
+#define CAN_ILS_RF0LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
+#define CAN_ILS_RF1NL_MASK                       (0x10U)
+#define CAN_ILS_RF1NL_SHIFT                      (4U)
+#define CAN_ILS_RF1NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
+#define CAN_ILS_RF1WL_MASK                       (0x20U)
+#define CAN_ILS_RF1WL_SHIFT                      (5U)
+#define CAN_ILS_RF1WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
+#define CAN_ILS_RF1FL_MASK                       (0x40U)
+#define CAN_ILS_RF1FL_SHIFT                      (6U)
+#define CAN_ILS_RF1FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
+#define CAN_ILS_RF1LL_MASK                       (0x80U)
+#define CAN_ILS_RF1LL_SHIFT                      (7U)
+#define CAN_ILS_RF1LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
+#define CAN_ILS_HPML_MASK                        (0x100U)
+#define CAN_ILS_HPML_SHIFT                       (8U)
+#define CAN_ILS_HPML(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
+#define CAN_ILS_TCL_MASK                         (0x200U)
+#define CAN_ILS_TCL_SHIFT                        (9U)
+#define CAN_ILS_TCL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
+#define CAN_ILS_TCFL_MASK                        (0x400U)
+#define CAN_ILS_TCFL_SHIFT                       (10U)
+#define CAN_ILS_TCFL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
+#define CAN_ILS_TFEL_MASK                        (0x800U)
+#define CAN_ILS_TFEL_SHIFT                       (11U)
+#define CAN_ILS_TFEL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
+#define CAN_ILS_TEFNL_MASK                       (0x1000U)
+#define CAN_ILS_TEFNL_SHIFT                      (12U)
+#define CAN_ILS_TEFNL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
+#define CAN_ILS_TEFWL_MASK                       (0x2000U)
+#define CAN_ILS_TEFWL_SHIFT                      (13U)
+#define CAN_ILS_TEFWL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
+#define CAN_ILS_TEFFL_MASK                       (0x4000U)
+#define CAN_ILS_TEFFL_SHIFT                      (14U)
+#define CAN_ILS_TEFFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
+#define CAN_ILS_TEFLL_MASK                       (0x8000U)
+#define CAN_ILS_TEFLL_SHIFT                      (15U)
+#define CAN_ILS_TEFLL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
+#define CAN_ILS_TSWL_MASK                        (0x10000U)
+#define CAN_ILS_TSWL_SHIFT                       (16U)
+#define CAN_ILS_TSWL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
+#define CAN_ILS_MRAFL_MASK                       (0x20000U)
+#define CAN_ILS_MRAFL_SHIFT                      (17U)
+#define CAN_ILS_MRAFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
+#define CAN_ILS_TOOL_MASK                        (0x40000U)
+#define CAN_ILS_TOOL_SHIFT                       (18U)
+#define CAN_ILS_TOOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
+#define CAN_ILS_DRXL_MASK                        (0x80000U)
+#define CAN_ILS_DRXL_SHIFT                       (19U)
+#define CAN_ILS_DRXL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
+#define CAN_ILS_BECL_MASK                        (0x100000U)
+#define CAN_ILS_BECL_SHIFT                       (20U)
+#define CAN_ILS_BECL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
+#define CAN_ILS_BEUL_MASK                        (0x200000U)
+#define CAN_ILS_BEUL_SHIFT                       (21U)
+#define CAN_ILS_BEUL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
+#define CAN_ILS_ELOL_MASK                        (0x400000U)
+#define CAN_ILS_ELOL_SHIFT                       (22U)
+#define CAN_ILS_ELOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
+#define CAN_ILS_EPL_MASK                         (0x800000U)
+#define CAN_ILS_EPL_SHIFT                        (23U)
+#define CAN_ILS_EPL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
+#define CAN_ILS_EWL_MASK                         (0x1000000U)
+#define CAN_ILS_EWL_SHIFT                        (24U)
+#define CAN_ILS_EWL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
+#define CAN_ILS_BOL_MASK                         (0x2000000U)
+#define CAN_ILS_BOL_SHIFT                        (25U)
+#define CAN_ILS_BOL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
+#define CAN_ILS_WDIL_MASK                        (0x4000000U)
+#define CAN_ILS_WDIL_SHIFT                       (26U)
+#define CAN_ILS_WDIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
+#define CAN_ILS_PEAL_MASK                        (0x8000000U)
+#define CAN_ILS_PEAL_SHIFT                       (27U)
+#define CAN_ILS_PEAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
+#define CAN_ILS_PEDL_MASK                        (0x10000000U)
+#define CAN_ILS_PEDL_SHIFT                       (28U)
+#define CAN_ILS_PEDL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
+#define CAN_ILS_ARAL_MASK                        (0x20000000U)
+#define CAN_ILS_ARAL_SHIFT                       (29U)
+#define CAN_ILS_ARAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
+
+/*! @name ILE - Interrupt Line Enable */
+#define CAN_ILE_EINT0_MASK                       (0x1U)
+#define CAN_ILE_EINT0_SHIFT                      (0U)
+#define CAN_ILE_EINT0(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
+#define CAN_ILE_EINT1_MASK                       (0x2U)
+#define CAN_ILE_EINT1_SHIFT                      (1U)
+#define CAN_ILE_EINT1(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
+
+/*! @name GFC - Global Filter Configuration */
+#define CAN_GFC_RRFE_MASK                        (0x1U)
+#define CAN_GFC_RRFE_SHIFT                       (0U)
+#define CAN_GFC_RRFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
+#define CAN_GFC_RRFS_MASK                        (0x2U)
+#define CAN_GFC_RRFS_SHIFT                       (1U)
+#define CAN_GFC_RRFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
+#define CAN_GFC_ANFE_MASK                        (0xCU)
+#define CAN_GFC_ANFE_SHIFT                       (2U)
+#define CAN_GFC_ANFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
+#define CAN_GFC_ANFS_MASK                        (0x30U)
+#define CAN_GFC_ANFS_SHIFT                       (4U)
+#define CAN_GFC_ANFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
+
+/*! @name SIDFC - Standard ID Filter Configuration */
+#define CAN_SIDFC_FLSSA_MASK                     (0xFFFCU)
+#define CAN_SIDFC_FLSSA_SHIFT                    (2U)
+#define CAN_SIDFC_FLSSA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
+#define CAN_SIDFC_LSS_MASK                       (0xFF0000U)
+#define CAN_SIDFC_LSS_SHIFT                      (16U)
+#define CAN_SIDFC_LSS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
+
+/*! @name XIDFC - Extended ID Filter Configuration */
+#define CAN_XIDFC_FLESA_MASK                     (0xFFFCU)
+#define CAN_XIDFC_FLESA_SHIFT                    (2U)
+#define CAN_XIDFC_FLESA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
+#define CAN_XIDFC_LSE_MASK                       (0xFF0000U)
+#define CAN_XIDFC_LSE_SHIFT                      (16U)
+#define CAN_XIDFC_LSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
+
+/*! @name XIDAM - Extended ID AND Mask */
+#define CAN_XIDAM_EIDM_MASK                      (0x1FFFFFFFU)
+#define CAN_XIDAM_EIDM_SHIFT                     (0U)
+#define CAN_XIDAM_EIDM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
+
+/*! @name HPMS - High Priority Message Status */
+#define CAN_HPMS_BIDX_MASK                       (0x3FU)
+#define CAN_HPMS_BIDX_SHIFT                      (0U)
+#define CAN_HPMS_BIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
+#define CAN_HPMS_MSI_MASK                        (0xC0U)
+#define CAN_HPMS_MSI_SHIFT                       (6U)
+#define CAN_HPMS_MSI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
+#define CAN_HPMS_FIDX_MASK                       (0x7F00U)
+#define CAN_HPMS_FIDX_SHIFT                      (8U)
+#define CAN_HPMS_FIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
+#define CAN_HPMS_FLST_MASK                       (0x8000U)
+#define CAN_HPMS_FLST_SHIFT                      (15U)
+#define CAN_HPMS_FLST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
+
+/*! @name NDAT1 - New Data 1 */
+#define CAN_NDAT1_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT1_ND_SHIFT                       (0U)
+#define CAN_NDAT1_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
+
+/*! @name NDAT2 - New Data 2 */
+#define CAN_NDAT2_ND_MASK                        (0xFFFFFFFFU)
+#define CAN_NDAT2_ND_SHIFT                       (0U)
+#define CAN_NDAT2_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
+
+/*! @name RXF0C - Rx FIFO 0 Configuration */
+#define CAN_RXF0C_F0SA_MASK                      (0xFFFCU)
+#define CAN_RXF0C_F0SA_SHIFT                     (2U)
+#define CAN_RXF0C_F0SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
+#define CAN_RXF0C_F0S_MASK                       (0x7F0000U)
+#define CAN_RXF0C_F0S_SHIFT                      (16U)
+#define CAN_RXF0C_F0S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
+#define CAN_RXF0C_F0WM_MASK                      (0x7F000000U)
+#define CAN_RXF0C_F0WM_SHIFT                     (24U)
+#define CAN_RXF0C_F0WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
+#define CAN_RXF0C_F0OM_MASK                      (0x80000000U)
+#define CAN_RXF0C_F0OM_SHIFT                     (31U)
+#define CAN_RXF0C_F0OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
+
+/*! @name RXF0S - Rx FIFO 0 Status */
+#define CAN_RXF0S_F0FL_MASK                      (0x7FU)
+#define CAN_RXF0S_F0FL_SHIFT                     (0U)
+#define CAN_RXF0S_F0FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
+#define CAN_RXF0S_F0GI_MASK                      (0x3F00U)
+#define CAN_RXF0S_F0GI_SHIFT                     (8U)
+#define CAN_RXF0S_F0GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
+#define CAN_RXF0S_F0PI_MASK                      (0x3F0000U)
+#define CAN_RXF0S_F0PI_SHIFT                     (16U)
+#define CAN_RXF0S_F0PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
+#define CAN_RXF0S_F0F_MASK                       (0x1000000U)
+#define CAN_RXF0S_F0F_SHIFT                      (24U)
+#define CAN_RXF0S_F0F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
+#define CAN_RXF0S_RF0L_MASK                      (0x2000000U)
+#define CAN_RXF0S_RF0L_SHIFT                     (25U)
+#define CAN_RXF0S_RF0L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
+
+/*! @name RXF0A - Rx FIFO 0 Acknowledge */
+#define CAN_RXF0A_F0AI_MASK                      (0x3FU)
+#define CAN_RXF0A_F0AI_SHIFT                     (0U)
+#define CAN_RXF0A_F0AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
+
+/*! @name RXBC - Rx Buffer Configuration */
+#define CAN_RXBC_RBSA_MASK                       (0xFFFCU)
+#define CAN_RXBC_RBSA_SHIFT                      (2U)
+#define CAN_RXBC_RBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
+
+/*! @name RXF1C - Rx FIFO 1 Configuration */
+#define CAN_RXF1C_F1SA_MASK                      (0xFFFCU)
+#define CAN_RXF1C_F1SA_SHIFT                     (2U)
+#define CAN_RXF1C_F1SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
+#define CAN_RXF1C_F1S_MASK                       (0x7F0000U)
+#define CAN_RXF1C_F1S_SHIFT                      (16U)
+#define CAN_RXF1C_F1S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
+#define CAN_RXF1C_F1WM_MASK                      (0x7F000000U)
+#define CAN_RXF1C_F1WM_SHIFT                     (24U)
+#define CAN_RXF1C_F1WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
+#define CAN_RXF1C_F1OM_MASK                      (0x80000000U)
+#define CAN_RXF1C_F1OM_SHIFT                     (31U)
+#define CAN_RXF1C_F1OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
+
+/*! @name RXF1S - Rx FIFO 1 Status */
+#define CAN_RXF1S_F1FL_MASK                      (0x7FU)
+#define CAN_RXF1S_F1FL_SHIFT                     (0U)
+#define CAN_RXF1S_F1FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
+#define CAN_RXF1S_F1GI_MASK                      (0x3F00U)
+#define CAN_RXF1S_F1GI_SHIFT                     (8U)
+#define CAN_RXF1S_F1GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
+#define CAN_RXF1S_F1PI_MASK                      (0x3F0000U)
+#define CAN_RXF1S_F1PI_SHIFT                     (16U)
+#define CAN_RXF1S_F1PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
+#define CAN_RXF1S_F1F_MASK                       (0x1000000U)
+#define CAN_RXF1S_F1F_SHIFT                      (24U)
+#define CAN_RXF1S_F1F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
+#define CAN_RXF1S_RF1L_MASK                      (0x2000000U)
+#define CAN_RXF1S_RF1L_SHIFT                     (25U)
+#define CAN_RXF1S_RF1L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
+
+/*! @name RXF1A - Rx FIFO 1 Acknowledge */
+#define CAN_RXF1A_F1AI_MASK                      (0x3FU)
+#define CAN_RXF1A_F1AI_SHIFT                     (0U)
+#define CAN_RXF1A_F1AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
+
+/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
+#define CAN_RXESC_F0DS_MASK                      (0x7U)
+#define CAN_RXESC_F0DS_SHIFT                     (0U)
+#define CAN_RXESC_F0DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
+#define CAN_RXESC_F1DS_MASK                      (0x70U)
+#define CAN_RXESC_F1DS_SHIFT                     (4U)
+#define CAN_RXESC_F1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
+#define CAN_RXESC_RBDS_MASK                      (0x700U)
+#define CAN_RXESC_RBDS_SHIFT                     (8U)
+#define CAN_RXESC_RBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
+
+/*! @name TXBC - Tx Buffer Configuration */
+#define CAN_TXBC_TBSA_MASK                       (0xFFFCU)
+#define CAN_TXBC_TBSA_SHIFT                      (2U)
+#define CAN_TXBC_TBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
+#define CAN_TXBC_NDTB_MASK                       (0x3F0000U)
+#define CAN_TXBC_NDTB_SHIFT                      (16U)
+#define CAN_TXBC_NDTB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
+#define CAN_TXBC_TFQS_MASK                       (0x3F000000U)
+#define CAN_TXBC_TFQS_SHIFT                      (24U)
+#define CAN_TXBC_TFQS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
+#define CAN_TXBC_TFQM_MASK                       (0x40000000U)
+#define CAN_TXBC_TFQM_SHIFT                      (30U)
+#define CAN_TXBC_TFQM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
+
+/*! @name TXFQS - Tx FIFO/Queue Status */
+#define CAN_TXFQS_TFGI_MASK                      (0x1F00U)
+#define CAN_TXFQS_TFGI_SHIFT                     (8U)
+#define CAN_TXFQS_TFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
+#define CAN_TXFQS_TFQPI_MASK                     (0x1F0000U)
+#define CAN_TXFQS_TFQPI_SHIFT                    (16U)
+#define CAN_TXFQS_TFQPI(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
+#define CAN_TXFQS_TFQF_MASK                      (0x200000U)
+#define CAN_TXFQS_TFQF_SHIFT                     (21U)
+#define CAN_TXFQS_TFQF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
+
+/*! @name TXESC - Tx Buffer Element Size Configuration */
+#define CAN_TXESC_TBDS_MASK                      (0x7U)
+#define CAN_TXESC_TBDS_SHIFT                     (0U)
+#define CAN_TXESC_TBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
+
+/*! @name TXBRP - Tx Buffer Request Pending */
+#define CAN_TXBRP_TRP_MASK                       (0xFFFFFFFFU)
+#define CAN_TXBRP_TRP_SHIFT                      (0U)
+#define CAN_TXBRP_TRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
+
+/*! @name TXBAR - Tx Buffer Add Request */
+#define CAN_TXBAR_AR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBAR_AR_SHIFT                       (0U)
+#define CAN_TXBAR_AR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
+
+/*! @name TXBCR - Tx Buffer Cancellation Request */
+#define CAN_TXBCR_CR_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCR_CR_SHIFT                       (0U)
+#define CAN_TXBCR_CR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
+
+/*! @name TXBTO - Tx Buffer Transmission Occurred */
+#define CAN_TXBTO_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBTO_TO_SHIFT                       (0U)
+#define CAN_TXBTO_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
+
+/*! @name TXBCF - Tx Buffer Cancellation Finished */
+#define CAN_TXBCF_TO_MASK                        (0xFFFFFFFFU)
+#define CAN_TXBCF_TO_SHIFT                       (0U)
+#define CAN_TXBCF_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
+
+/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
+#define CAN_TXBTIE_TIE_MASK                      (0xFFFFFFFFU)
+#define CAN_TXBTIE_TIE_SHIFT                     (0U)
+#define CAN_TXBTIE_TIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
+
+/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
+#define CAN_TXBCIE_CFIE_MASK                     (0xFFFFFFFFU)
+#define CAN_TXBCIE_CFIE_SHIFT                    (0U)
+#define CAN_TXBCIE_CFIE(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
+
+/*! @name TXEFC - Tx Event FIFO Configuration */
+#define CAN_TXEFC_EFSA_MASK                      (0xFFFCU)
+#define CAN_TXEFC_EFSA_SHIFT                     (2U)
+#define CAN_TXEFC_EFSA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
+#define CAN_TXEFC_EFS_MASK                       (0x3F0000U)
+#define CAN_TXEFC_EFS_SHIFT                      (16U)
+#define CAN_TXEFC_EFS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
+#define CAN_TXEFC_EFWM_MASK                      (0x3F000000U)
+#define CAN_TXEFC_EFWM_SHIFT                     (24U)
+#define CAN_TXEFC_EFWM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
+
+/*! @name TXEFS - Tx Event FIFO Status */
+#define CAN_TXEFS_EFFL_MASK                      (0x3FU)
+#define CAN_TXEFS_EFFL_SHIFT                     (0U)
+#define CAN_TXEFS_EFFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
+#define CAN_TXEFS_EFGI_MASK                      (0x1F00U)
+#define CAN_TXEFS_EFGI_SHIFT                     (8U)
+#define CAN_TXEFS_EFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
+#define CAN_TXEFS_EFPI_MASK                      (0x3F0000U)
+#define CAN_TXEFS_EFPI_SHIFT                     (16U)
+#define CAN_TXEFS_EFPI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
+#define CAN_TXEFS_EFF_MASK                       (0x1000000U)
+#define CAN_TXEFS_EFF_SHIFT                      (24U)
+#define CAN_TXEFS_EFF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
+#define CAN_TXEFS_TEFL_MASK                      (0x2000000U)
+#define CAN_TXEFS_TEFL_SHIFT                     (25U)
+#define CAN_TXEFS_TEFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
+
+/*! @name TXEFA - Tx Event FIFO Acknowledge */
+#define CAN_TXEFA_EFAI_MASK                      (0x1FU)
+#define CAN_TXEFA_EFAI_SHIFT                     (0U)
+#define CAN_TXEFA_EFAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
+
+/*! @name MRBA - CAN Message RAM Base Address */
+#define CAN_MRBA_BA_MASK                         (0xFFFFFFFFU)
+#define CAN_MRBA_BA_SHIFT                        (0U)
+#define CAN_MRBA_BA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
+
+/*! @name ETSCC - External Timestamp Counter Configuration */
+#define CAN_ETSCC_ETCP_MASK                      (0x7FFU)
+#define CAN_ETSCC_ETCP_SHIFT                     (0U)
+#define CAN_ETSCC_ETCP(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
+#define CAN_ETSCC_ETCE_MASK                      (0x80000000U)
+#define CAN_ETSCC_ETCE_SHIFT                     (31U)
+#define CAN_ETSCC_ETCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
+
+/*! @name ETSCV - External Timestamp Counter Value */
+#define CAN_ETSCV_ETSC_MASK                      (0xFFFFU)
+#define CAN_ETSCV_ETSC_SHIFT                     (0U)
+#define CAN_ETSCV_ETSC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x4009D000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE                                (0x4009E000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1                                     ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_IRQS                                 { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MODE;                              /**< CRC mode register, offset: 0x0 */
+  __IO uint32_t SEED;                              /**< CRC seed register, offset: 0x4 */
+  union {                                          /* offset: 0x8 */
+    __I  uint32_t SUM;                               /**< CRC checksum register, offset: 0x8 */
+    __O  uint32_t WR_DATA;                           /**< CRC data register, offset: 0x8 */
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
+#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
+#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
+#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
+#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
+#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+
+/*! @name SEED - CRC seed register */
+#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
+#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+
+/*! @name SUM - CRC checksum register */
+#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
+#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+
+/*! @name WR_DATA - CRC data register */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK             (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT            (0U)
+#define CRC_WR_DATA_CRC_WR_DATA(x)               (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE                          (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t IR;                                /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+  __IO uint32_t TCR;                               /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
+  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
+  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
+  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
+  __IO uint32_t MR[4];                             /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+  __IO uint32_t CCR;                               /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+  __I  uint32_t CR[4];                             /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+  __IO uint32_t EMR;                               /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t CTCR;                              /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+  __IO uint32_t PWMC;                              /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CTIMER Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+#define CTIMER_IR_MR0INT_MASK                    (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT                   (0U)
+#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK                    (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT                   (1U)
+#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK                    (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT                   (2U)
+#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK                    (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT                   (3U)
+#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK                    (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT                   (4U)
+#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK                    (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT                   (5U)
+#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK                    (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT                   (6U)
+#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK                    (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT                   (7U)
+#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+#define CTIMER_TCR_CEN_MASK                      (0x1U)
+#define CTIMER_TCR_CEN_SHIFT                     (0U)
+#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK                     (0x2U)
+#define CTIMER_TCR_CRST_SHIFT                    (1U)
+#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+
+/*! @name TC - Timer Counter */
+#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT                    (0U)
+#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+
+/*! @name PR - Prescale Register */
+#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT                    (0U)
+#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+
+/*! @name PC - Prescale Counter */
+#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT                    (0U)
+#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+
+/*! @name MCR - Match Control Register */
+#define CTIMER_MCR_MR0I_MASK                     (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT                    (0U)
+#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK                     (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT                    (1U)
+#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK                     (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT                    (2U)
+#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK                     (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT                    (3U)
+#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK                     (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT                    (4U)
+#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK                     (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT                    (5U)
+#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK                     (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT                    (6U)
+#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK                     (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT                    (7U)
+#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK                     (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT                    (8U)
+#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK                     (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT                    (9U)
+#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK                     (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT                    (10U)
+#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK                     (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT                    (11U)
+#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
+#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
+#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
+#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
+#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT                    (0U)
+#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT                          (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
+#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
+#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
+#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
+#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
+#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
+#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
+#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
+#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
+#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
+#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
+#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
+#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT                      (0U)
+#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT                          (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+#define CTIMER_EMR_EM0_MASK                      (0x1U)
+#define CTIMER_EMR_EM0_SHIFT                     (0U)
+#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK                      (0x2U)
+#define CTIMER_EMR_EM1_SHIFT                     (1U)
+#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK                      (0x4U)
+#define CTIMER_EMR_EM2_SHIFT                     (2U)
+#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK                      (0x8U)
+#define CTIMER_EMR_EM3_SHIFT                     (3U)
+#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK                     (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT                    (4U)
+#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT                    (6U)
+#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK                     (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT                    (8U)
+#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT                    (10U)
+#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
+#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
+#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
+#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
+#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
+#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
+#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
+#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
+#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+
+/*! @name MSR - Match Shadow Register */
+#define CTIMER_MSR_SHADOWW_MASK                  (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT                 (0U)
+#define CTIMER_MSR_SHADOWW(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT                         (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE                             (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE                             (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE                             (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE                             (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE                             (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< DMA control., offset: 0x0 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status., offset: 0x4 */
+  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table., offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  struct {                                         /* offset: 0x20, array step: 0x5C */
+    __IO uint32_t ENABLESET;                         /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+         uint8_t RESERVED_0[4];
+    __O  uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+         uint8_t RESERVED_1[4];
+    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+         uint8_t RESERVED_2[4];
+    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+         uint8_t RESERVED_3[4];
+    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+         uint8_t RESERVED_4[4];
+    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+         uint8_t RESERVED_5[4];
+    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+         uint8_t RESERVED_6[4];
+    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+         uint8_t RESERVED_7[4];
+    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+         uint8_t RESERVED_8[4];
+    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+         uint8_t RESERVED_9[4];
+    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+         uint8_t RESERVED_10[4];
+    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+  } COMMON[1];
+       uint8_t RESERVED_1[900];
+  struct {                                         /* offset: 0x400, array step: 0x10 */
+    __IO uint32_t CFG;                               /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } CHANNEL[30];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+#define DMA_CTRL_ENABLE_MASK                     (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT                    (0U)
+#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+
+/*! @name INTSTAT - Interrupt status. */
+#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
+#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
+#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
+#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+#define DMA_COMMON_ENABLESET_ENA_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT           (0U)
+#define DMA_COMMON_ENABLESET_ENA(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT               (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+#define DMA_COMMON_ENABLECLR_CLR_MASK            (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT           (0U)
+#define DMA_COMMON_ENABLECLR_CLR(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT               (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+#define DMA_COMMON_ACTIVE_ACT_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT              (0U)
+#define DMA_COMMON_ACTIVE_ACT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT                  (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+#define DMA_COMMON_BUSY_BSY_MASK                 (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT                (0U)
+#define DMA_COMMON_BUSY_BSY(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT                    (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+#define DMA_COMMON_ERRINT_ERR_MASK               (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT              (0U)
+#define DMA_COMMON_ERRINT_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT                  (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+#define DMA_COMMON_INTENSET_INTEN_MASK           (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT          (0U)
+#define DMA_COMMON_INTENSET_INTEN(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT                (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+#define DMA_COMMON_INTENCLR_CLR_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT            (0U)
+#define DMA_COMMON_INTENCLR_CLR(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT                (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+#define DMA_COMMON_INTA_IA_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT                 (0U)
+#define DMA_COMMON_INTA_IA(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT                    (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+#define DMA_COMMON_INTB_IB_MASK                  (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT                 (0U)
+#define DMA_COMMON_INTB_IB(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT                    (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+#define DMA_COMMON_SETVALID_SV_MASK              (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT             (0U)
+#define DMA_COMMON_SETVALID_SV(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT                (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+#define DMA_COMMON_SETTRIG_TRIG_MASK             (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT            (0U)
+#define DMA_COMMON_SETTRIG_TRIG(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT                 (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK          (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT         (0U)
+#define DMA_COMMON_ABORT_ABORTCTRL(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT                   (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
+#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
+#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
+#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
+#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
+#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
+#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT                    (30U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
+#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT                (30U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
+#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
+#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
+#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
+#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
+#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
+#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT                (30U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE                                (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0                                     ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS                                 { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t OSR;                               /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+    __IO uint32_t PREAC2FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+    __IO uint32_t PREAC4FSCOEF;                      /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_0[108];
+    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+    __IO uint32_t FIFO_DATA;                         /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+    __IO uint32_t PHY_CTRL;                          /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+    __IO uint32_t DC_CTRL;                           /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+         uint8_t RESERVED_1[108];
+  } CHANNEL[2];
+       uint8_t RESERVED_0[3328];
+  __IO uint32_t CHANEN;                            /**< Channel Enable register, offset: 0xF00 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t IOCFG;                             /**< I/O Configuration register, offset: 0xF0C */
+  __IO uint32_t USE2FS;                            /**< Use 2FS register, offset: 0xF10 */
+       uint8_t RESERVED_2[108];
+  __IO uint32_t HWVADGAIN;                         /**< HWVAD input gain register, offset: 0xF80 */
+  __IO uint32_t HWVADHPFS;                         /**< HWVAD filter control register, offset: 0xF84 */
+  __IO uint32_t HWVADST10;                         /**< HWVAD control register, offset: 0xF88 */
+  __IO uint32_t HWVADRSTT;                         /**< HWVAD filter reset register, offset: 0xF8C */
+  __IO uint32_t HWVADTHGN;                         /**< HWVAD noise estimator gain register, offset: 0xF90 */
+  __IO uint32_t HWVADTHGS;                         /**< HWVAD signal estimator gain register, offset: 0xF94 */
+  __I  uint32_t HWVADLOWZ;                         /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+       uint8_t RESERVED_3[96];
+  __I  uint32_t ID;                                /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMIC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
+#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT                   (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)
+
+/*! @name CHANEN - Channel Enable register */
+#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
+#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
+#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+
+/*! @name IOCFG - I/O Configuration register */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK              (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT             (0U)
+#define DMIC_IOCFG_CLK_BYPASS0(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK              (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT             (1U)
+#define DMIC_IOCFG_CLK_BYPASS1(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK             (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT            (2U)
+#define DMIC_IOCFG_STEREO_DATA0(x)               (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+
+/*! @name USE2FS - Use 2FS register */
+#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
+#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
+#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
+#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+
+/*! @name HWVADST10 - HWVAD control register */
+#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT                (0U)
+#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+#define DMIC_HWVADRSTT_RSTT_MASK                 (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT                (0U)
+#define DMIC_HWVADRSTT_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
+#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
+#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
+#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+
+/*! @name ID - Module Identification register */
+#define DMIC_ID_ID_MASK                          (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT                         (0U)
+#define DMIC_ID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE                               (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS                           { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS                                { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EEPROM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
+ * @{
+ */
+
+/** EEPROM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CMD;                               /**< EEPROM command register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RWSTATE;                           /**< EEPROM read wait state register, offset: 0x8 */
+  __IO uint32_t AUTOPROG;                          /**< EEPROM auto programming register, offset: 0xC */
+  __IO uint32_t WSTATE;                            /**< EEPROM wait state register, offset: 0x10 */
+  __IO uint32_t CLKDIV;                            /**< EEPROM clock divider register, offset: 0x14 */
+  __IO uint32_t PWRDWN;                            /**< EEPROM power-down register, offset: 0x18 */
+       uint8_t RESERVED_1[4028];
+  __O  uint32_t INTENCLR;                          /**< EEPROM interrupt enable clear, offset: 0xFD8 */
+  __O  uint32_t INTENSET;                          /**< EEPROM interrupt enable set, offset: 0xFDC */
+  __I  uint32_t INTSTAT;                           /**< EEPROM interrupt status, offset: 0xFE0 */
+  __I  uint32_t INTEN;                             /**< EEPROM interrupt enable, offset: 0xFE4 */
+  __O  uint32_t INTSTATCLR;                        /**< EEPROM interrupt status clear, offset: 0xFE8 */
+  __O  uint32_t INTSTATSET;                        /**< EEPROM interrupt status set, offset: 0xFEC */
+} EEPROM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EEPROM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EEPROM_Register_Masks EEPROM Register Masks
+ * @{
+ */
+
+/*! @name CMD - EEPROM command register */
+#define EEPROM_CMD_CMD_MASK                      (0x7U)
+#define EEPROM_CMD_CMD_SHIFT                     (0U)
+#define EEPROM_CMD_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
+
+/*! @name RWSTATE - EEPROM read wait state register */
+#define EEPROM_RWSTATE_RPHASE2_MASK              (0xFFU)
+#define EEPROM_RWSTATE_RPHASE2_SHIFT             (0U)
+#define EEPROM_RWSTATE_RPHASE2(x)                (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)
+#define EEPROM_RWSTATE_RPHASE1_MASK              (0xFF00U)
+#define EEPROM_RWSTATE_RPHASE1_SHIFT             (8U)
+#define EEPROM_RWSTATE_RPHASE1(x)                (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)
+
+/*! @name AUTOPROG - EEPROM auto programming register */
+#define EEPROM_AUTOPROG_AUTOPROG_MASK            (0x3U)
+#define EEPROM_AUTOPROG_AUTOPROG_SHIFT           (0U)
+#define EEPROM_AUTOPROG_AUTOPROG(x)              (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)
+
+/*! @name WSTATE - EEPROM wait state register */
+#define EEPROM_WSTATE_PHASE3_MASK                (0xFFU)
+#define EEPROM_WSTATE_PHASE3_SHIFT               (0U)
+#define EEPROM_WSTATE_PHASE3(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)
+#define EEPROM_WSTATE_PHASE2_MASK                (0xFF00U)
+#define EEPROM_WSTATE_PHASE2_SHIFT               (8U)
+#define EEPROM_WSTATE_PHASE2(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)
+#define EEPROM_WSTATE_PHASE1_MASK                (0xFF0000U)
+#define EEPROM_WSTATE_PHASE1_SHIFT               (16U)
+#define EEPROM_WSTATE_PHASE1(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)
+#define EEPROM_WSTATE_LCK_PARWEP_MASK            (0x80000000U)
+#define EEPROM_WSTATE_LCK_PARWEP_SHIFT           (31U)
+#define EEPROM_WSTATE_LCK_PARWEP(x)              (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)
+
+/*! @name CLKDIV - EEPROM clock divider register */
+#define EEPROM_CLKDIV_CLKDIV_MASK                (0xFFFFU)
+#define EEPROM_CLKDIV_CLKDIV_SHIFT               (0U)
+#define EEPROM_CLKDIV_CLKDIV(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)
+
+/*! @name PWRDWN - EEPROM power-down register */
+#define EEPROM_PWRDWN_PWRDWN_MASK                (0x1U)
+#define EEPROM_PWRDWN_PWRDWN_SHIFT               (0U)
+#define EEPROM_PWRDWN_PWRDWN(x)                  (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)
+
+/*! @name INTENCLR - EEPROM interrupt enable clear */
+#define EEPROM_INTENCLR_PROG_CLR_EN_MASK         (0x4U)
+#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT        (2U)
+#define EEPROM_INTENCLR_PROG_CLR_EN(x)           (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)
+
+/*! @name INTENSET - EEPROM interrupt enable set */
+#define EEPROM_INTENSET_PROG_SET_EN_MASK         (0x4U)
+#define EEPROM_INTENSET_PROG_SET_EN_SHIFT        (2U)
+#define EEPROM_INTENSET_PROG_SET_EN(x)           (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)
+
+/*! @name INTSTAT - EEPROM interrupt status */
+#define EEPROM_INTSTAT_END_OF_PROG_MASK          (0x4U)
+#define EEPROM_INTSTAT_END_OF_PROG_SHIFT         (2U)
+#define EEPROM_INTSTAT_END_OF_PROG(x)            (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)
+
+/*! @name INTEN - EEPROM interrupt enable */
+#define EEPROM_INTEN_EE_PROG_DONE_MASK           (0x4U)
+#define EEPROM_INTEN_EE_PROG_DONE_SHIFT          (2U)
+#define EEPROM_INTEN_EE_PROG_DONE(x)             (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)
+
+/*! @name INTSTATCLR - EEPROM interrupt status clear */
+#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK       (0x4U)
+#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT      (2U)
+#define EEPROM_INTSTATCLR_PROG_CLR_ST(x)         (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)
+
+/*! @name INTSTATSET - EEPROM interrupt status set */
+#define EEPROM_INTSTATSET_PROG_SET_ST_MASK       (0x4U)
+#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT      (2U)
+#define EEPROM_INTSTATSET_PROG_SET_ST(x)         (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EEPROM_Register_Masks */
+
+
+/* EEPROM - Peripheral instance base addresses */
+/** Peripheral EEPROM base address */
+#define EEPROM_BASE                              (0x40014000u)
+/** Peripheral EEPROM base pointer */
+#define EEPROM                                   ((EEPROM_Type *)EEPROM_BASE)
+/** Array initializer of EEPROM peripheral base addresses */
+#define EEPROM_BASE_ADDRS                        { EEPROM_BASE }
+/** Array initializer of EEPROM peripheral base pointers */
+#define EEPROM_BASE_PTRS                         { EEPROM }
+/** Interrupt vectors for the EEPROM peripheral type */
+#define EEPROM_IRQS                              { EEPROM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EEPROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
+ * @{
+ */
+
+/** EMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Controls operation of the memory controller, offset: 0x0 */
+  __I  uint32_t STATUS;                            /**< Provides EMC status information, offset: 0x4 */
+  __IO uint32_t CONFIG;                            /**< Configures operation of the memory controller, offset: 0x8 */
+       uint8_t RESERVED_0[20];
+  __IO uint32_t DYNAMICCONTROL;                    /**< Controls dynamic memory operation, offset: 0x20 */
+  __IO uint32_t DYNAMICREFRESH;                    /**< Configures dynamic memory refresh, offset: 0x24 */
+  __IO uint32_t DYNAMICREADCONFIG;                 /**< Configures dynamic memory read strategy, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t DYNAMICRP;                         /**< Precharge command period, offset: 0x30 */
+  __IO uint32_t DYNAMICRAS;                        /**< Active to precharge command period, offset: 0x34 */
+  __IO uint32_t DYNAMICSREX;                       /**< Self-refresh exit time, offset: 0x38 */
+  __IO uint32_t DYNAMICAPR;                        /**< Last-data-out to active command time, offset: 0x3C */
+  __IO uint32_t DYNAMICDAL;                        /**< Data-in to active command time, offset: 0x40 */
+  __IO uint32_t DYNAMICWR;                         /**< Write recovery time, offset: 0x44 */
+  __IO uint32_t DYNAMICRC;                         /**< Selects the active to active command period, offset: 0x48 */
+  __IO uint32_t DYNAMICRFC;                        /**< Selects the auto-refresh period, offset: 0x4C */
+  __IO uint32_t DYNAMICXSR;                        /**< Time for exit self-refresh to active command, offset: 0x50 */
+  __IO uint32_t DYNAMICRRD;                        /**< Latency for active bank A to active bank B, offset: 0x54 */
+  __IO uint32_t DYNAMICMRD;                        /**< Time for load mode register to active command, offset: 0x58 */
+       uint8_t RESERVED_2[36];
+  __IO uint32_t STATICEXTENDEDWAIT;                /**< Time for long static memory read and write transfers, offset: 0x80 */
+       uint8_t RESERVED_3[124];
+  struct {                                         /* offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICCONFIG;                     /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
+    __IO uint32_t DYNAMICRASCAS;                     /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
+         uint8_t RESERVED_0[24];
+  } DYNAMIC[4];
+       uint8_t RESERVED_4[128];
+  struct {                                         /* offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICCONFIG;                      /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
+    __IO uint32_t STATICWAITWEN;                     /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
+    __IO uint32_t STATICWAITOEN;                     /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
+    __IO uint32_t STATICWAITRD;                      /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
+    __IO uint32_t STATICWAITPAGE;                    /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
+    __IO uint32_t STATICWAITWR;                      /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
+    __IO uint32_t STATICWAITTURN;                    /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
+         uint8_t RESERVED_0[4];
+  } STATIC[4];
+} EMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Register_Masks EMC Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Controls operation of the memory controller */
+#define EMC_CONTROL_E_MASK                       (0x1U)
+#define EMC_CONTROL_E_SHIFT                      (0U)
+#define EMC_CONTROL_E(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
+#define EMC_CONTROL_M_MASK                       (0x2U)
+#define EMC_CONTROL_M_SHIFT                      (1U)
+#define EMC_CONTROL_M(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
+#define EMC_CONTROL_L_MASK                       (0x4U)
+#define EMC_CONTROL_L_SHIFT                      (2U)
+#define EMC_CONTROL_L(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
+
+/*! @name STATUS - Provides EMC status information */
+#define EMC_STATUS_B_MASK                        (0x1U)
+#define EMC_STATUS_B_SHIFT                       (0U)
+#define EMC_STATUS_B(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
+#define EMC_STATUS_S_MASK                        (0x2U)
+#define EMC_STATUS_S_SHIFT                       (1U)
+#define EMC_STATUS_S(x)                          (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
+#define EMC_STATUS_SA_MASK                       (0x4U)
+#define EMC_STATUS_SA_SHIFT                      (2U)
+#define EMC_STATUS_SA(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
+
+/*! @name CONFIG - Configures operation of the memory controller */
+#define EMC_CONFIG_EM_MASK                       (0x1U)
+#define EMC_CONFIG_EM_SHIFT                      (0U)
+#define EMC_CONFIG_EM(x)                         (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
+#define EMC_CONFIG_CLKR_MASK                     (0x100U)
+#define EMC_CONFIG_CLKR_SHIFT                    (8U)
+#define EMC_CONFIG_CLKR(x)                       (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
+
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
+#define EMC_DYNAMICCONTROL_CE_MASK               (0x1U)
+#define EMC_DYNAMICCONTROL_CE_SHIFT              (0U)
+#define EMC_DYNAMICCONTROL_CE(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
+#define EMC_DYNAMICCONTROL_CS_MASK               (0x2U)
+#define EMC_DYNAMICCONTROL_CS_SHIFT              (1U)
+#define EMC_DYNAMICCONTROL_CS(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
+#define EMC_DYNAMICCONTROL_SR_MASK               (0x4U)
+#define EMC_DYNAMICCONTROL_SR_SHIFT              (2U)
+#define EMC_DYNAMICCONTROL_SR(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
+#define EMC_DYNAMICCONTROL_MMC_MASK              (0x20U)
+#define EMC_DYNAMICCONTROL_MMC_SHIFT             (5U)
+#define EMC_DYNAMICCONTROL_MMC(x)                (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
+#define EMC_DYNAMICCONTROL_I_MASK                (0x180U)
+#define EMC_DYNAMICCONTROL_I_SHIFT               (7U)
+#define EMC_DYNAMICCONTROL_I(x)                  (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
+
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
+#define EMC_DYNAMICREFRESH_REFRESH_MASK          (0x7FFU)
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT         (0U)
+#define EMC_DYNAMICREFRESH_REFRESH(x)            (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
+
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
+#define EMC_DYNAMICREADCONFIG_RD_MASK            (0x3U)
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT           (0U)
+#define EMC_DYNAMICREADCONFIG_RD(x)              (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
+
+/*! @name DYNAMICRP - Precharge command period */
+#define EMC_DYNAMICRP_TRP_MASK                   (0xFU)
+#define EMC_DYNAMICRP_TRP_SHIFT                  (0U)
+#define EMC_DYNAMICRP_TRP(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
+
+/*! @name DYNAMICRAS - Active to precharge command period */
+#define EMC_DYNAMICRAS_TRAS_MASK                 (0xFU)
+#define EMC_DYNAMICRAS_TRAS_SHIFT                (0U)
+#define EMC_DYNAMICRAS_TRAS(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
+
+/*! @name DYNAMICSREX - Self-refresh exit time */
+#define EMC_DYNAMICSREX_TSREX_MASK               (0xFU)
+#define EMC_DYNAMICSREX_TSREX_SHIFT              (0U)
+#define EMC_DYNAMICSREX_TSREX(x)                 (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
+
+/*! @name DYNAMICAPR - Last-data-out to active command time */
+#define EMC_DYNAMICAPR_TAPR_MASK                 (0xFU)
+#define EMC_DYNAMICAPR_TAPR_SHIFT                (0U)
+#define EMC_DYNAMICAPR_TAPR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
+
+/*! @name DYNAMICDAL - Data-in to active command time */
+#define EMC_DYNAMICDAL_TDAL_MASK                 (0xFU)
+#define EMC_DYNAMICDAL_TDAL_SHIFT                (0U)
+#define EMC_DYNAMICDAL_TDAL(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
+
+/*! @name DYNAMICWR - Write recovery time */
+#define EMC_DYNAMICWR_TWR_MASK                   (0xFU)
+#define EMC_DYNAMICWR_TWR_SHIFT                  (0U)
+#define EMC_DYNAMICWR_TWR(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
+
+/*! @name DYNAMICRC - Selects the active to active command period */
+#define EMC_DYNAMICRC_TRC_MASK                   (0x1FU)
+#define EMC_DYNAMICRC_TRC_SHIFT                  (0U)
+#define EMC_DYNAMICRC_TRC(x)                     (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
+
+/*! @name DYNAMICRFC - Selects the auto-refresh period */
+#define EMC_DYNAMICRFC_TRFC_MASK                 (0x1FU)
+#define EMC_DYNAMICRFC_TRFC_SHIFT                (0U)
+#define EMC_DYNAMICRFC_TRFC(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
+
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
+#define EMC_DYNAMICXSR_TXSR_MASK                 (0x1FU)
+#define EMC_DYNAMICXSR_TXSR_SHIFT                (0U)
+#define EMC_DYNAMICXSR_TXSR(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
+
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
+#define EMC_DYNAMICRRD_TRRD_MASK                 (0xFU)
+#define EMC_DYNAMICRRD_TRRD_SHIFT                (0U)
+#define EMC_DYNAMICRRD_TRRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
+
+/*! @name DYNAMICMRD - Time for load mode register to active command */
+#define EMC_DYNAMICMRD_TMRD_MASK                 (0xFU)
+#define EMC_DYNAMICMRD_TMRD_SHIFT                (0U)
+#define EMC_DYNAMICMRD_TMRD(x)                   (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
+
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x)   (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
+
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK        (0x18U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT       (3U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x)          (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK       (0x1F80U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT      (7U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK       (0x4000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT      (14U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK         (0x80000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT        (19U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK         (0x100000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT        (20U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x)           (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
+
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT          (4U)
+
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK       (0x3U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT      (0U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK       (0x300U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT      (8U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x)         (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
+
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT          (4U)
+
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
+#define EMC_STATIC_STATICCONFIG_MW_MASK          (0x3U)
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT         (0U)
+#define EMC_STATIC_STATICCONFIG_MW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
+#define EMC_STATIC_STATICCONFIG_PM_MASK          (0x8U)
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT         (3U)
+#define EMC_STATIC_STATICCONFIG_PM(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
+#define EMC_STATIC_STATICCONFIG_PC_MASK          (0x40U)
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT         (6U)
+#define EMC_STATIC_STATICCONFIG_PC(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
+#define EMC_STATIC_STATICCONFIG_PB_MASK          (0x80U)
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT         (7U)
+#define EMC_STATIC_STATICCONFIG_PB(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
+#define EMC_STATIC_STATICCONFIG_EW_MASK          (0x100U)
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT         (8U)
+#define EMC_STATIC_STATICCONFIG_EW(x)            (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
+#define EMC_STATIC_STATICCONFIG_B_MASK           (0x80000U)
+#define EMC_STATIC_STATICCONFIG_B_SHIFT          (19U)
+#define EMC_STATIC_STATICCONFIG_B(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
+#define EMC_STATIC_STATICCONFIG_P_MASK           (0x100000U)
+#define EMC_STATIC_STATICCONFIG_P_SHIFT          (20U)
+#define EMC_STATIC_STATICCONFIG_P(x)             (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
+
+/* The count of EMC_STATIC_STATICCONFIG */
+#define EMC_STATIC_STATICCONFIG_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT   (0U)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITWEN */
+#define EMC_STATIC_STATICWAITWEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK    (0xFU)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT   (0U)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x)      (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITOEN */
+#define EMC_STATIC_STATICWAITOEN_COUNT           (4U)
+
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT     (0U)
+#define EMC_STATIC_STATICWAITRD_WAITRD(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
+
+/* The count of EMC_STATIC_STATICWAITRD */
+#define EMC_STATIC_STATICWAITRD_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK  (0x1FU)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
+
+/* The count of EMC_STATIC_STATICWAITPAGE */
+#define EMC_STATIC_STATICWAITPAGE_COUNT          (4U)
+
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK      (0x1FU)
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT     (0U)
+#define EMC_STATIC_STATICWAITWR_WAITWR(x)        (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
+
+/* The count of EMC_STATIC_STATICWAITWR */
+#define EMC_STATIC_STATICWAITWR_COUNT            (4U)
+
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK  (0xFU)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x)    (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITTURN */
+#define EMC_STATIC_STATICWAITTURN_COUNT          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group EMC_Register_Masks */
+
+
+/* EMC - Peripheral instance base addresses */
+/** Peripheral EMC base address */
+#define EMC_BASE                                 (0x40081000u)
+/** Peripheral EMC base pointer */
+#define EMC                                      ((EMC_Type *)EMC_BASE)
+/** Array initializer of EMC peripheral base addresses */
+#define EMC_BASE_ADDRS                           { EMC_BASE }
+/** Array initializer of EMC peripheral base pointers */
+#define EMC_BASE_PTRS                            { EMC }
+
+/*!
+ * @}
+ */ /* end of group EMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MAC_CONFIG;                        /**< MAC configuration register, offset: 0x0 */
+  __IO uint32_t MAC_EXT_CONFIG;                    /**< , offset: 0x4 */
+  __IO uint32_t MAC_FRAME_FILTER;                  /**< MAC frame filter register, offset: 0x8 */
+  __IO uint32_t MAC_WD_TIMEROUT;                   /**< MAC watchdog Timeout register, offset: 0xC */
+       uint8_t RESERVED_0[64];
+  __IO uint32_t MAC_VLAN_TAG;                      /**< MAC vlan tag register, offset: 0x50 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t MAC_TX_FLOW_CTRL_Q[2];             /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< Receive flow control register, offset: 0x90 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t MAC_TXQ_PRIO_MAP;                  /**< , offset: 0x98 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t MAC_RXQ_CTRL[3];                   /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[4];
+  __I  uint32_t MAC_INTR_STAT;                     /**< Interrupt status register 0x0000, offset: 0xB0 */
+  __IO uint32_t MAC_INTR_EN;                       /**< Interrupt enable register 0x0000, offset: 0xB4 */
+  __I  uint32_t MAC_RXTX_STAT;                     /**< Receive Transmit Status register, offset: 0xB8 */
+       uint8_t RESERVED_6[4];
+  __IO uint32_t MAC_PMT_CRTL_STAT;                 /**< , offset: 0xC0 */
+  __IO uint32_t MAC_RWAKE_FRFLT;                   /**< Remote wake-up frame filter, offset: 0xC4 */
+       uint8_t RESERVED_7[8];
+  __IO uint32_t MAC_LPI_CTRL_STAT;                 /**< LPI Control and Status Register, offset: 0xD0 */
+  __IO uint32_t MAC_LPI_TIMER_CTRL;                /**< LPI Timers Control register, offset: 0xD4 */
+  __IO uint32_t MAC_LPI_ENTR_TIMR;                 /**< LPI entry Timer register, offset: 0xD8 */
+  __IO uint32_t MAC_1US_TIC_COUNTR;                /**< , offset: 0xDC */
+       uint8_t RESERVED_8[48];
+  __IO uint32_t MAC_VERSION;                       /**< MAC version register, offset: 0x110 */
+  __I  uint32_t MAC_DBG;                           /**< MAC debug register, offset: 0x114 */
+       uint8_t RESERVED_9[4];
+  __IO uint32_t MAC_HW_FEAT[3];                    /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
+       uint8_t RESERVED_10[216];
+  __IO uint32_t MAC_MDIO_ADDR;                     /**< MIDO address Register, offset: 0x200 */
+  __IO uint32_t MAC_MDIO_DATA;                     /**< MDIO Data register, offset: 0x204 */
+       uint8_t RESERVED_11[248];
+  __IO uint32_t MAC_ADDR_HIGH;                     /**< MAC address0 high register, offset: 0x300 */
+  __IO uint32_t MAC_ADDR_LOW;                      /**< MAC address0 low register, offset: 0x304 */
+       uint8_t RESERVED_12[2040];
+  __IO uint32_t MAC_TIMESTAMP_CTRL;                /**< Time stamp control register, offset: 0xB00 */
+  __IO uint32_t MAC_SUB_SCND_INCR;                 /**< Sub-second increment register, offset: 0xB04 */
+  __I  uint32_t MAC_SYS_TIME_SCND;                 /**< System time seconds register, offset: 0xB08 */
+  __I  uint32_t MAC_SYS_TIME_NSCND;                /**< System time nanoseconds register, offset: 0xB0C */
+  __IO uint32_t MAC_SYS_TIME_SCND_UPD;             /**< , offset: 0xB10 */
+  __IO uint32_t MAC_SYS_TIME_NSCND_UPD;            /**< , offset: 0xB14 */
+  __IO uint32_t MAC_SYS_TIMESTMP_ADDEND;           /**< Time stamp addend register, offset: 0xB18 */
+  __IO uint32_t MAC_SYS_TIME_HWORD_SCND;           /**< , offset: 0xB1C */
+  __I  uint32_t MAC_SYS_TIMESTMP_STAT;             /**< Time stamp status register, offset: 0xB20 */
+       uint8_t RESERVED_13[12];
+  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
+  __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Tx timestamp status seconds, offset: 0xB34 */
+       uint8_t RESERVED_14[32];
+  __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
+  __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
+       uint8_t RESERVED_15[160];
+  __IO uint32_t MTL_OP_MODE;                       /**< MTL Operation Mode Register, offset: 0xC00 */
+       uint8_t RESERVED_16[28];
+  __I  uint32_t MTL_INTR_STAT;                     /**< MTL Interrupt Status register, offset: 0xC20 */
+       uint8_t RESERVED_17[12];
+  __IO uint32_t MTL_RXQ_DMA_MAP;                   /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
+       uint8_t RESERVED_18[204];
+  struct {                                         /* offset: 0xD00, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_OP_MODE;                  /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
+    __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
+    __I  uint32_t MTL_TXQX_DBG;                      /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
+         uint8_t RESERVED_0[4];
+    __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_ETS_STAT;                 /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< , array offset: 0xD18, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
+    __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
+         uint8_t RESERVED_1[4];
+    __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< , array offset: 0xD2C, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_OP_MODE;                  /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_DBG;                      /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
+    __IO uint32_t MTL_RXQX_CTRL;                     /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
+  } MTL_QUEUE[2];
+       uint8_t RESERVED_19[640];
+  __IO uint32_t DMA_MODE;                          /**< DMA mode register, offset: 0x1000 */
+  __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus mode, offset: 0x1004 */
+  __IO uint32_t DMA_INTR_STAT;                     /**< DMA Interrupt status, offset: 0x1008 */
+  __IO uint32_t DMA_DBG_STAT;                      /**< DMA Debug Status, offset: 0x100C */
+       uint8_t RESERVED_20[240];
+  struct {                                         /* offset: 0x1100, array step: 0x80 */
+    __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
+         uint8_t RESERVED_0[8];
+    __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< , array offset: 0x1114, array step: 0x80 */
+         uint8_t RESERVED_1[4];
+    __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< , array offset: 0x111C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< , array offset: 0x1120, array step: 0x80 */
+         uint8_t RESERVED_2[4];
+    __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< , array offset: 0x1128, array step: 0x80 */
+    __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< , array offset: 0x112C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
+    __IO uint32_t DMA_CHX_INT_EN;                    /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
+    __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
+    __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
+         uint8_t RESERVED_3[4];
+    __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
+         uint8_t RESERVED_4[4];
+    __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< , array offset: 0x114C, array step: 0x80 */
+         uint8_t RESERVED_5[4];
+    __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< , array offset: 0x1154, array step: 0x80 */
+         uint8_t RESERVED_6[4];
+    __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
+    __IO uint32_t DMA_CHX_STAT;                      /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
+         uint8_t RESERVED_7[28];
+  } DMA_CH[2];
+} ENET_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name MAC_CONFIG - MAC configuration register */
+#define ENET_MAC_CONFIG_RE_MASK                  (0x1U)
+#define ENET_MAC_CONFIG_RE_SHIFT                 (0U)
+#define ENET_MAC_CONFIG_RE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
+#define ENET_MAC_CONFIG_TE_MASK                  (0x2U)
+#define ENET_MAC_CONFIG_TE_SHIFT                 (1U)
+#define ENET_MAC_CONFIG_TE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
+#define ENET_MAC_CONFIG_PRELEN_MASK              (0xCU)
+#define ENET_MAC_CONFIG_PRELEN_SHIFT             (2U)
+#define ENET_MAC_CONFIG_PRELEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
+#define ENET_MAC_CONFIG_DC_MASK                  (0x10U)
+#define ENET_MAC_CONFIG_DC_SHIFT                 (4U)
+#define ENET_MAC_CONFIG_DC(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
+#define ENET_MAC_CONFIG_BL_MASK                  (0x60U)
+#define ENET_MAC_CONFIG_BL_SHIFT                 (5U)
+#define ENET_MAC_CONFIG_BL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
+#define ENET_MAC_CONFIG_DR_MASK                  (0x100U)
+#define ENET_MAC_CONFIG_DR_SHIFT                 (8U)
+#define ENET_MAC_CONFIG_DR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
+#define ENET_MAC_CONFIG_DCRS_MASK                (0x200U)
+#define ENET_MAC_CONFIG_DCRS_SHIFT               (9U)
+#define ENET_MAC_CONFIG_DCRS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
+#define ENET_MAC_CONFIG_DO_MASK                  (0x400U)
+#define ENET_MAC_CONFIG_DO_SHIFT                 (10U)
+#define ENET_MAC_CONFIG_DO(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
+#define ENET_MAC_CONFIG_ECRSFD_MASK              (0x800U)
+#define ENET_MAC_CONFIG_ECRSFD_SHIFT             (11U)
+#define ENET_MAC_CONFIG_ECRSFD(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
+#define ENET_MAC_CONFIG_LM_MASK                  (0x1000U)
+#define ENET_MAC_CONFIG_LM_SHIFT                 (12U)
+#define ENET_MAC_CONFIG_LM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
+#define ENET_MAC_CONFIG_DM_MASK                  (0x2000U)
+#define ENET_MAC_CONFIG_DM_SHIFT                 (13U)
+#define ENET_MAC_CONFIG_DM(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
+#define ENET_MAC_CONFIG_FES_MASK                 (0x4000U)
+#define ENET_MAC_CONFIG_FES_SHIFT                (14U)
+#define ENET_MAC_CONFIG_FES(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
+#define ENET_MAC_CONFIG_PS_MASK                  (0x8000U)
+#define ENET_MAC_CONFIG_PS_SHIFT                 (15U)
+#define ENET_MAC_CONFIG_PS(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
+#define ENET_MAC_CONFIG_JE_MASK                  (0x10000U)
+#define ENET_MAC_CONFIG_JE_SHIFT                 (16U)
+#define ENET_MAC_CONFIG_JE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
+#define ENET_MAC_CONFIG_JD_MASK                  (0x20000U)
+#define ENET_MAC_CONFIG_JD_SHIFT                 (17U)
+#define ENET_MAC_CONFIG_JD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
+#define ENET_MAC_CONFIG_BE_MASK                  (0x40000U)
+#define ENET_MAC_CONFIG_BE_SHIFT                 (18U)
+#define ENET_MAC_CONFIG_BE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
+#define ENET_MAC_CONFIG_WD_MASK                  (0x80000U)
+#define ENET_MAC_CONFIG_WD_SHIFT                 (19U)
+#define ENET_MAC_CONFIG_WD(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
+#define ENET_MAC_CONFIG_ACS_MASK                 (0x100000U)
+#define ENET_MAC_CONFIG_ACS_SHIFT                (20U)
+#define ENET_MAC_CONFIG_ACS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
+#define ENET_MAC_CONFIG_CST_MASK                 (0x200000U)
+#define ENET_MAC_CONFIG_CST_SHIFT                (21U)
+#define ENET_MAC_CONFIG_CST(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
+#define ENET_MAC_CONFIG_S2KP_MASK                (0x400000U)
+#define ENET_MAC_CONFIG_S2KP_SHIFT               (22U)
+#define ENET_MAC_CONFIG_S2KP(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
+#define ENET_MAC_CONFIG_GPSLCE_MASK              (0x800000U)
+#define ENET_MAC_CONFIG_GPSLCE_SHIFT             (23U)
+#define ENET_MAC_CONFIG_GPSLCE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
+#define ENET_MAC_CONFIG_IPG_MASK                 (0x7000000U)
+#define ENET_MAC_CONFIG_IPG_SHIFT                (24U)
+#define ENET_MAC_CONFIG_IPG(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
+#define ENET_MAC_CONFIG_IPC_MASK                 (0x8000000U)
+#define ENET_MAC_CONFIG_IPC_SHIFT                (27U)
+#define ENET_MAC_CONFIG_IPC(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
+
+/*! @name MAC_EXT_CONFIG -  */
+#define ENET_MAC_EXT_CONFIG_GPSL_MASK            (0x3FFFU)
+#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT           (0U)
+#define ENET_MAC_EXT_CONFIG_GPSL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
+#define ENET_MAC_EXT_CONFIG_DCRCC_MASK           (0x10000U)
+#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT          (16U)
+#define ENET_MAC_EXT_CONFIG_DCRCC(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
+#define ENET_MAC_EXT_CONFIG_SPEN_MASK            (0x20000U)
+#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT           (17U)
+#define ENET_MAC_EXT_CONFIG_SPEN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
+#define ENET_MAC_EXT_CONFIG_USP_MASK             (0x40000U)
+#define ENET_MAC_EXT_CONFIG_USP_SHIFT            (18U)
+#define ENET_MAC_EXT_CONFIG_USP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
+
+/*! @name MAC_FRAME_FILTER - MAC frame filter register */
+#define ENET_MAC_FRAME_FILTER_PR_MASK            (0x1U)
+#define ENET_MAC_FRAME_FILTER_PR_SHIFT           (0U)
+#define ENET_MAC_FRAME_FILTER_PR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
+#define ENET_MAC_FRAME_FILTER_DAIF_MASK          (0x8U)
+#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT         (3U)
+#define ENET_MAC_FRAME_FILTER_DAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_PM_MASK            (0x10U)
+#define ENET_MAC_FRAME_FILTER_PM_SHIFT           (4U)
+#define ENET_MAC_FRAME_FILTER_PM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
+#define ENET_MAC_FRAME_FILTER_DBF_MASK           (0x20U)
+#define ENET_MAC_FRAME_FILTER_DBF_SHIFT          (5U)
+#define ENET_MAC_FRAME_FILTER_DBF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
+#define ENET_MAC_FRAME_FILTER_PCF_MASK           (0xC0U)
+#define ENET_MAC_FRAME_FILTER_PCF_SHIFT          (6U)
+#define ENET_MAC_FRAME_FILTER_PCF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAIF_MASK          (0x100U)
+#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT         (8U)
+#define ENET_MAC_FRAME_FILTER_SAIF(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAF_MASK           (0x200U)
+#define ENET_MAC_FRAME_FILTER_SAF_SHIFT          (9U)
+#define ENET_MAC_FRAME_FILTER_SAF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
+#define ENET_MAC_FRAME_FILTER_RA_MASK            (0x80000000U)
+#define ENET_MAC_FRAME_FILTER_RA_SHIFT           (31U)
+#define ENET_MAC_FRAME_FILTER_RA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
+
+/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
+#define ENET_MAC_WD_TIMEROUT_WTO_MASK            (0xFU)
+#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT           (0U)
+#define ENET_MAC_WD_TIMEROUT_WTO(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
+#define ENET_MAC_WD_TIMEROUT_PWE_MASK            (0x100U)
+#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT           (8U)
+#define ENET_MAC_WD_TIMEROUT_PWE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
+
+/*! @name MAC_VLAN_TAG - MAC vlan tag register */
+#define ENET_MAC_VLAN_TAG_VL_MASK                (0xFFFFU)
+#define ENET_MAC_VLAN_TAG_VL_SHIFT               (0U)
+#define ENET_MAC_VLAN_TAG_VL(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
+#define ENET_MAC_VLAN_TAG_ETV_MASK               (0x10000U)
+#define ENET_MAC_VLAN_TAG_ETV_SHIFT              (16U)
+#define ENET_MAC_VLAN_TAG_ETV(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
+#define ENET_MAC_VLAN_TAG_VTIM_MASK              (0x20000U)
+#define ENET_MAC_VLAN_TAG_VTIM_SHIFT             (17U)
+#define ENET_MAC_VLAN_TAG_VTIM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
+#define ENET_MAC_VLAN_TAG_ESVL_MASK              (0x40000U)
+#define ENET_MAC_VLAN_TAG_ESVL_SHIFT             (18U)
+#define ENET_MAC_VLAN_TAG_ESVL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
+#define ENET_MAC_VLAN_TAG_ERSVLM_MASK            (0x80000U)
+#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT           (19U)
+#define ENET_MAC_VLAN_TAG_ERSVLM(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
+#define ENET_MAC_VLAN_TAG_DOVLTC_MASK            (0x100000U)
+#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT           (20U)
+#define ENET_MAC_VLAN_TAG_DOVLTC(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
+#define ENET_MAC_VLAN_TAG_EVLS_MASK              (0x600000U)
+#define ENET_MAC_VLAN_TAG_EVLS_SHIFT             (21U)
+#define ENET_MAC_VLAN_TAG_EVLS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EVLRXS_MASK            (0x1000000U)
+#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT           (24U)
+#define ENET_MAC_VLAN_TAG_EVLRXS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
+#define ENET_MAC_VLAN_TAG_VTHM_MASK              (0x2000000U)
+#define ENET_MAC_VLAN_TAG_VTHM_SHIFT             (25U)
+#define ENET_MAC_VLAN_TAG_VTHM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
+#define ENET_MAC_VLAN_TAG_EDVLP_MASK             (0x4000000U)
+#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT            (26U)
+#define ENET_MAC_VLAN_TAG_EDVLP(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
+#define ENET_MAC_VLAN_TAG_ERIVLT_MASK            (0x8000000U)
+#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT           (27U)
+#define ENET_MAC_VLAN_TAG_ERIVLT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLS_MASK             (0x30000000U)
+#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT            (28U)
+#define ENET_MAC_VLAN_TAG_EIVLS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK           (0x80000000U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT          (31U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
+
+/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK         (0x1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT        (0U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK         (0x2U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT        (1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK         (0x70U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT        (4U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK        (0x80U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT       (7U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK          (0xFFFF0000U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT         (16U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
+
+/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
+#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT            (2U)
+
+/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
+#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK           (0x1U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT          (0U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
+#define ENET_MAC_RX_FLOW_CTRL_UP_MASK            (0x2U)
+#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT           (1U)
+#define ENET_MAC_RX_FLOW_CTRL_UP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
+
+/*! @name MAC_TXQ_PRIO_MAP -  */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK         (0xFFU)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT        (0U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK         (0xFF00U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT        (8U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
+
+/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK            (0x3U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT           (0U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK             (0xFFU)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT            (0U)
+#define ENET_MAC_RXQ_CTRL_PSRQ0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK             (0x7U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT            (0U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK            (0xCU)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT           (2U)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK            (0x70U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT           (4U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK             (0xFF00U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT            (8U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
+#define ENET_MAC_RXQ_CTRL_UPQ_MASK               (0x7000U)
+#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT              (12U)
+#define ENET_MAC_RXQ_CTRL_UPQ(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK             (0xFF0000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT            (16U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK             (0x70000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT            (16U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK           (0x100000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT          (20U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK             (0xFF000000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT            (24U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
+
+/* The count of ENET_MAC_RXQ_CTRL */
+#define ENET_MAC_RXQ_CTRL_COUNT                  (3U)
+
+/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
+#define ENET_MAC_INTR_STAT_PHYIS_MASK            (0x8U)
+#define ENET_MAC_INTR_STAT_PHYIS_SHIFT           (3U)
+#define ENET_MAC_INTR_STAT_PHYIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
+#define ENET_MAC_INTR_STAT_PMTIS_MASK            (0x10U)
+#define ENET_MAC_INTR_STAT_PMTIS_SHIFT           (4U)
+#define ENET_MAC_INTR_STAT_PMTIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
+#define ENET_MAC_INTR_STAT_LPIIS_MASK            (0x20U)
+#define ENET_MAC_INTR_STAT_LPIIS_SHIFT           (5U)
+#define ENET_MAC_INTR_STAT_LPIIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
+#define ENET_MAC_INTR_STAT_TSIS_MASK             (0x1000U)
+#define ENET_MAC_INTR_STAT_TSIS_SHIFT            (12U)
+#define ENET_MAC_INTR_STAT_TSIS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
+#define ENET_MAC_INTR_STAT_TXSTSIS_MASK          (0x2000U)
+#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT         (13U)
+#define ENET_MAC_INTR_STAT_TXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
+#define ENET_MAC_INTR_STAT_RXSTSIS_MASK          (0x4000U)
+#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT         (14U)
+#define ENET_MAC_INTR_STAT_RXSTSIS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
+
+/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
+#define ENET_MAC_INTR_EN_PHYIE_MASK              (0x8U)
+#define ENET_MAC_INTR_EN_PHYIE_SHIFT             (3U)
+#define ENET_MAC_INTR_EN_PHYIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
+#define ENET_MAC_INTR_EN_PMTIE_MASK              (0x10U)
+#define ENET_MAC_INTR_EN_PMTIE_SHIFT             (4U)
+#define ENET_MAC_INTR_EN_PMTIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
+#define ENET_MAC_INTR_EN_LPIIE_MASK              (0x20U)
+#define ENET_MAC_INTR_EN_LPIIE_SHIFT             (5U)
+#define ENET_MAC_INTR_EN_LPIIE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
+#define ENET_MAC_INTR_EN_TSIE_MASK               (0x1000U)
+#define ENET_MAC_INTR_EN_TSIE_SHIFT              (12U)
+#define ENET_MAC_INTR_EN_TSIE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
+#define ENET_MAC_INTR_EN_TXSTSIE_MASK            (0x2000U)
+#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT           (13U)
+#define ENET_MAC_INTR_EN_TXSTSIE(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
+#define ENET_MAC_INTR_EN_RXSTSIS_MASK            (0x4000U)
+#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT           (14U)
+#define ENET_MAC_INTR_EN_RXSTSIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
+
+/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
+#define ENET_MAC_RXTX_STAT_TJT_MASK              (0x1U)
+#define ENET_MAC_RXTX_STAT_TJT_SHIFT             (0U)
+#define ENET_MAC_RXTX_STAT_TJT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
+#define ENET_MAC_RXTX_STAT_NCARR_MASK            (0x2U)
+#define ENET_MAC_RXTX_STAT_NCARR_SHIFT           (1U)
+#define ENET_MAC_RXTX_STAT_NCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
+#define ENET_MAC_RXTX_STAT_LCARR_MASK            (0x4U)
+#define ENET_MAC_RXTX_STAT_LCARR_SHIFT           (2U)
+#define ENET_MAC_RXTX_STAT_LCARR(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
+#define ENET_MAC_RXTX_STAT_EXDEF_MASK            (0x8U)
+#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT           (3U)
+#define ENET_MAC_RXTX_STAT_EXDEF(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
+#define ENET_MAC_RXTX_STAT_LCOL_MASK             (0x10U)
+#define ENET_MAC_RXTX_STAT_LCOL_SHIFT            (4U)
+#define ENET_MAC_RXTX_STAT_LCOL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
+#define ENET_MAC_RXTX_STAT_EXCOL_MASK            (0x20U)
+#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT           (5U)
+#define ENET_MAC_RXTX_STAT_EXCOL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
+#define ENET_MAC_RXTX_STAT_RWT_MASK              (0x100U)
+#define ENET_MAC_RXTX_STAT_RWT_SHIFT             (8U)
+#define ENET_MAC_RXTX_STAT_RWT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
+
+/*! @name MAC_PMT_CRTL_STAT -  */
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK       (0x1U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT      (0U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK     (0x2U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT    (1U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK     (0x4U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT    (2U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK     (0x20U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT    (5U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK     (0x40U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT    (6U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK    (0x200U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT   (9U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK       (0x400U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT      (10U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK       (0x1F000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT      (24U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK   (0x80000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT  (31U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
+
+/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
+#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK           (0xFFFFFFFFU)
+#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT          (0U)
+#define ENET_MAC_RWAKE_FRFLT_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
+
+/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK       (0x1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT      (0U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK       (0x2U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT      (1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK       (0x4U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT      (2U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK       (0x8U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT      (3U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK       (0x100U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT      (8U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK       (0x200U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT      (9U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK        (0x10000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT       (16U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK          (0x20000U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT         (17U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK       (0x80000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT      (19U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK       (0x100000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT      (20U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK      (0x200000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT     (21U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
+
+/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK         (0xFFFFU)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT        (0U)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK         (0x3FF0000U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT        (16U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
+
+/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK        (0xFFFF8U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT       (3U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
+
+/*! @name MAC_1US_TIC_COUNTR -  */
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
+
+/*! @name MAC_VERSION - MAC version register */
+#define ENET_MAC_VERSION_SNPVER_MASK             (0xFFU)
+#define ENET_MAC_VERSION_SNPVER_SHIFT            (0U)
+#define ENET_MAC_VERSION_SNPVER(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
+#define ENET_MAC_VERSION_USERVER_MASK            (0xFF00U)
+#define ENET_MAC_VERSION_USERVER_SHIFT           (8U)
+#define ENET_MAC_VERSION_USERVER(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
+
+/*! @name MAC_DBG - MAC debug register */
+#define ENET_MAC_DBG_REPESTS_MASK                (0x1U)
+#define ENET_MAC_DBG_REPESTS_SHIFT               (0U)
+#define ENET_MAC_DBG_REPESTS(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
+#define ENET_MAC_DBG_RFCFCSTS_MASK               (0x6U)
+#define ENET_MAC_DBG_RFCFCSTS_SHIFT              (1U)
+#define ENET_MAC_DBG_RFCFCSTS(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
+#define ENET_MAC_DBG_TPESTS_MASK                 (0x10000U)
+#define ENET_MAC_DBG_TPESTS_SHIFT                (16U)
+#define ENET_MAC_DBG_TPESTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
+#define ENET_MAC_DBG_TFCSTS_MASK                 (0x60000U)
+#define ENET_MAC_DBG_TFCSTS_SHIFT                (17U)
+#define ENET_MAC_DBG_TFCSTS(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
+
+/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK         (0x1FU)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT        (0U)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_RXQCNT_MASK             (0xFU)
+#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT            (0U)
+#define ENET_MAC_HW_FEAT_RXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_MIISEL_MASK             (0x1U)
+#define ENET_MAC_HW_FEAT_MIISEL_SHIFT            (0U)
+#define ENET_MAC_HW_FEAT_MIISEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
+#define ENET_MAC_HW_FEAT_HDSEL_MASK              (0x4U)
+#define ENET_MAC_HW_FEAT_HDSEL_SHIFT             (2U)
+#define ENET_MAC_HW_FEAT_HDSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
+#define ENET_MAC_HW_FEAT_VLHASH_MASK             (0x10U)
+#define ENET_MAC_HW_FEAT_VLHASH_SHIFT            (4U)
+#define ENET_MAC_HW_FEAT_VLHASH(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
+#define ENET_MAC_HW_FEAT_SMASEL_MASK             (0x20U)
+#define ENET_MAC_HW_FEAT_SMASEL_SHIFT            (5U)
+#define ENET_MAC_HW_FEAT_SMASEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
+#define ENET_MAC_HW_FEAT_TXQCNT_MASK             (0x3C0U)
+#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT            (6U)
+#define ENET_MAC_HW_FEAT_TXQCNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_RWKSEL_MASK             (0x40U)
+#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT            (6U)
+#define ENET_MAC_HW_FEAT_RWKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK         (0x7C0U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT        (6U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_MGKSEL_MASK             (0x80U)
+#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT            (7U)
+#define ENET_MAC_HW_FEAT_MGKSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
+#define ENET_MAC_HW_FEAT_MMCSEL_MASK             (0x100U)
+#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT            (8U)
+#define ENET_MAC_HW_FEAT_MMCSEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK          (0x200U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT         (9U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
+#define ENET_MAC_HW_FEAT_OSTEN_MASK              (0x800U)
+#define ENET_MAC_HW_FEAT_OSTEN_SHIFT             (11U)
+#define ENET_MAC_HW_FEAT_OSTEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCHCNT_MASK            (0xF000U)
+#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT           (12U)
+#define ENET_MAC_HW_FEAT_RXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSSEL_MASK              (0x1000U)
+#define ENET_MAC_HW_FEAT_TSSEL_SHIFT             (12U)
+#define ENET_MAC_HW_FEAT_TSSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
+#define ENET_MAC_HW_FEAT_PTOEN_MASK              (0x1000U)
+#define ENET_MAC_HW_FEAT_PTOEN_SHIFT             (12U)
+#define ENET_MAC_HW_FEAT_PTOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
+#define ENET_MAC_HW_FEAT_EEESEL_MASK             (0x2000U)
+#define ENET_MAC_HW_FEAT_EEESEL_SHIFT            (13U)
+#define ENET_MAC_HW_FEAT_EEESEL(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK          (0x2000U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT         (13U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
+#define ENET_MAC_HW_FEAT_ADDR64_MASK             (0xC000U)
+#define ENET_MAC_HW_FEAT_ADDR64_SHIFT            (14U)
+#define ENET_MAC_HW_FEAT_ADDR64(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
+#define ENET_MAC_HW_FEAT_TXCOESEL_MASK           (0x4000U)
+#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT          (14U)
+#define ENET_MAC_HW_FEAT_TXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_DCBEN_MASK              (0x10000U)
+#define ENET_MAC_HW_FEAT_DCBEN_SHIFT             (16U)
+#define ENET_MAC_HW_FEAT_DCBEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCOESEL_MASK           (0x10000U)
+#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT          (16U)
+#define ENET_MAC_HW_FEAT_RXCOESEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_SPEN_MASK               (0x20000U)
+#define ENET_MAC_HW_FEAT_SPEN_SHIFT              (17U)
+#define ENET_MAC_HW_FEAT_SPEN(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
+#define ENET_MAC_HW_FEAT_TXCHCNT_MASK            (0x3C0000U)
+#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT           (18U)
+#define ENET_MAC_HW_FEAT_TXCHCNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSOEN_MASK              (0x40000U)
+#define ENET_MAC_HW_FEAT_TSOEN_SHIFT             (18U)
+#define ENET_MAC_HW_FEAT_TSOEN(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
+#define ENET_MAC_HW_FEAT_DBGMEMA_MASK            (0x80000U)
+#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT           (19U)
+#define ENET_MAC_HW_FEAT_DBGMEMA(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
+#define ENET_MAC_HW_FEAT_AVSEL_MASK              (0x100000U)
+#define ENET_MAC_HW_FEAT_AVSEL_SHIFT             (20U)
+#define ENET_MAC_HW_FEAT_AVSEL(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
+#define ENET_MAC_HW_FEAT_LPMODEEN_MASK           (0x800000U)
+#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT          (23U)
+#define ENET_MAC_HW_FEAT_LPMODEEN(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK          (0x7000000U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT         (24U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK          (0x3000000U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT         (24U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK           (0x6000000U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT          (25U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK       (0x78000000U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT      (27U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK         (0x70000000U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT        (28U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x)           (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK          (0x70000000U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT         (28U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
+
+/* The count of ENET_MAC_HW_FEAT */
+#define ENET_MAC_HW_FEAT_COUNT                   (3U)
+
+/*! @name MAC_MDIO_ADDR - MIDO address Register */
+#define ENET_MAC_MDIO_ADDR_MB_MASK               (0x1U)
+#define ENET_MAC_MDIO_ADDR_MB_SHIFT              (0U)
+#define ENET_MAC_MDIO_ADDR_MB(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
+#define ENET_MAC_MDIO_ADDR_MOC_MASK              (0xCU)
+#define ENET_MAC_MDIO_ADDR_MOC_SHIFT             (2U)
+#define ENET_MAC_MDIO_ADDR_MOC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
+#define ENET_MAC_MDIO_ADDR_CR_MASK               (0xF00U)
+#define ENET_MAC_MDIO_ADDR_CR_SHIFT              (8U)
+#define ENET_MAC_MDIO_ADDR_CR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
+#define ENET_MAC_MDIO_ADDR_NTC_MASK              (0x7000U)
+#define ENET_MAC_MDIO_ADDR_NTC_SHIFT             (12U)
+#define ENET_MAC_MDIO_ADDR_NTC(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
+#define ENET_MAC_MDIO_ADDR_RDA_MASK              (0x1F0000U)
+#define ENET_MAC_MDIO_ADDR_RDA_SHIFT             (16U)
+#define ENET_MAC_MDIO_ADDR_RDA(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
+#define ENET_MAC_MDIO_ADDR_PA_MASK               (0x3E00000U)
+#define ENET_MAC_MDIO_ADDR_PA_SHIFT              (21U)
+#define ENET_MAC_MDIO_ADDR_PA(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
+#define ENET_MAC_MDIO_ADDR_BTB_MASK              (0x4000000U)
+#define ENET_MAC_MDIO_ADDR_BTB_SHIFT             (26U)
+#define ENET_MAC_MDIO_ADDR_BTB(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
+#define ENET_MAC_MDIO_ADDR_PSE_MASK              (0x8000000U)
+#define ENET_MAC_MDIO_ADDR_PSE_SHIFT             (27U)
+#define ENET_MAC_MDIO_ADDR_PSE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
+
+/*! @name MAC_MDIO_DATA - MDIO Data register */
+#define ENET_MAC_MDIO_DATA_MD_MASK               (0xFFFFU)
+#define ENET_MAC_MDIO_DATA_MD_SHIFT              (0U)
+#define ENET_MAC_MDIO_DATA_MD(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
+
+/*! @name MAC_ADDR_HIGH - MAC address0 high register */
+#define ENET_MAC_ADDR_HIGH_A47_32_MASK           (0xFFFFU)
+#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT          (0U)
+#define ENET_MAC_ADDR_HIGH_A47_32(x)             (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
+#define ENET_MAC_ADDR_HIGH_DCS_MASK              (0x10000U)
+#define ENET_MAC_ADDR_HIGH_DCS_SHIFT             (16U)
+#define ENET_MAC_ADDR_HIGH_DCS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
+#define ENET_MAC_ADDR_HIGH_AE_MASK               (0x80000000U)
+#define ENET_MAC_ADDR_HIGH_AE_SHIFT              (31U)
+#define ENET_MAC_ADDR_HIGH_AE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
+
+/*! @name MAC_ADDR_LOW - MAC address0 low register */
+#define ENET_MAC_ADDR_LOW_A31_0_MASK             (0xFFFFFFFFU)
+#define ENET_MAC_ADDR_LOW_A31_0_SHIFT            (0U)
+#define ENET_MAC_ADDR_LOW_A31_0(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
+
+/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK       (0x1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT      (0U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK    (0x2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT   (1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK      (0x4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT     (2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK      (0x8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT     (3U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK      (0x10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT     (4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK     (0x20U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT    (5U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK     (0x100U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT    (8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK   (0x200U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT  (9U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK   (0x400U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT  (10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK     (0x800U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT    (11U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK   (0x1000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT  (12U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK   (0x2000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT  (13U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK    (0x4000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT   (14U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK   (0x8000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT  (15U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK  (0x30000U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK   (0x1000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT  (24U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
+
+/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
+#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK        (0xFF0000U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT       (16U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
+
+/*! @name MAC_SYS_TIME_SCND - System time seconds register */
+#define ENET_MAC_SYS_TIME_SCND_TSS_MASK          (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT         (0U)
+#define ENET_MAC_SYS_TIME_SCND_TSS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
+
+/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK        (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT       (0U)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
+
+/*! @name MAC_SYS_TIME_SCND_UPD -  */
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK      (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT     (0U)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
+
+/*! @name MAC_SYS_TIME_NSCND_UPD -  */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK    (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT   (0U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK  (0x80000000U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
+
+/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK   (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT  (0U)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
+
+/*! @name MAC_SYS_TIME_HWORD_SCND -  */
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK  (0xFFFFU)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
+
+/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK   (0x1U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT  (0U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
+
+/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
+
+/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
+
+/*! @name MTL_OP_MODE - MTL Operation Mode Register */
+#define ENET_MTL_OP_MODE_DTXSTS_MASK             (0x2U)
+#define ENET_MTL_OP_MODE_DTXSTS_SHIFT            (1U)
+#define ENET_MTL_OP_MODE_DTXSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
+#define ENET_MTL_OP_MODE_RAA_MASK                (0x4U)
+#define ENET_MTL_OP_MODE_RAA_SHIFT               (2U)
+#define ENET_MTL_OP_MODE_RAA(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
+#define ENET_MTL_OP_MODE_SCHALG_MASK             (0x60U)
+#define ENET_MTL_OP_MODE_SCHALG_SHIFT            (5U)
+#define ENET_MTL_OP_MODE_SCHALG(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
+#define ENET_MTL_OP_MODE_CNTPRST_MASK            (0x100U)
+#define ENET_MTL_OP_MODE_CNTPRST_SHIFT           (8U)
+#define ENET_MTL_OP_MODE_CNTPRST(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
+#define ENET_MTL_OP_MODE_CNTCLR_MASK             (0x200U)
+#define ENET_MTL_OP_MODE_CNTCLR_SHIFT            (9U)
+#define ENET_MTL_OP_MODE_CNTCLR(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
+
+/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
+#define ENET_MTL_INTR_STAT_Q0IS_MASK             (0x1U)
+#define ENET_MTL_INTR_STAT_Q0IS_SHIFT            (0U)
+#define ENET_MTL_INTR_STAT_Q0IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
+#define ENET_MTL_INTR_STAT_Q1IS_MASK             (0x2U)
+#define ENET_MTL_INTR_STAT_Q1IS_SHIFT            (1U)
+#define ENET_MTL_INTR_STAT_Q1IS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
+
+/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK       (0x1U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT      (0U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK       (0x10U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT      (4U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK       (0x100U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT      (8U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK       (0x1000U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT      (12U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x)         (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
+
+/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK  (0x6U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK  (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK  (0x10U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK    (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT   (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT        (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT   (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT   (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT -  */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT  (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK  (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK  (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT -  */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT    (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK  (0x1U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK  (0x6U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK  (0x30U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK    (0x3FFF0000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT   (16U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT        (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT       (2U)
+
+/*! @name DMA_MODE - DMA mode register */
+#define ENET_DMA_MODE_SWR_MASK                   (0x1U)
+#define ENET_DMA_MODE_SWR_SHIFT                  (0U)
+#define ENET_DMA_MODE_SWR(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
+#define ENET_DMA_MODE_DA_MASK                    (0x2U)
+#define ENET_DMA_MODE_DA_SHIFT                   (1U)
+#define ENET_DMA_MODE_DA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
+#define ENET_DMA_MODE_TAA_MASK                   (0x1CU)
+#define ENET_DMA_MODE_TAA_SHIFT                  (2U)
+#define ENET_DMA_MODE_TAA(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
+#define ENET_DMA_MODE_TXPR_MASK                  (0x800U)
+#define ENET_DMA_MODE_TXPR_SHIFT                 (11U)
+#define ENET_DMA_MODE_TXPR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
+#define ENET_DMA_MODE_PR_MASK                    (0x7000U)
+#define ENET_DMA_MODE_PR_SHIFT                   (12U)
+#define ENET_DMA_MODE_PR(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
+
+/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
+#define ENET_DMA_SYSBUS_MODE_FB_MASK             (0x1U)
+#define ENET_DMA_SYSBUS_MODE_FB_SHIFT            (0U)
+#define ENET_DMA_SYSBUS_MODE_FB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
+#define ENET_DMA_SYSBUS_MODE_AAL_MASK            (0x1000U)
+#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT           (12U)
+#define ENET_DMA_SYSBUS_MODE_AAL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
+#define ENET_DMA_SYSBUS_MODE_MB_MASK             (0x4000U)
+#define ENET_DMA_SYSBUS_MODE_MB_SHIFT            (14U)
+#define ENET_DMA_SYSBUS_MODE_MB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
+#define ENET_DMA_SYSBUS_MODE_RB_MASK             (0x8000U)
+#define ENET_DMA_SYSBUS_MODE_RB_SHIFT            (15U)
+#define ENET_DMA_SYSBUS_MODE_RB(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
+
+/*! @name DMA_INTR_STAT - DMA Interrupt status */
+#define ENET_DMA_INTR_STAT_DC0IS_MASK            (0x1U)
+#define ENET_DMA_INTR_STAT_DC0IS_SHIFT           (0U)
+#define ENET_DMA_INTR_STAT_DC0IS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
+#define ENET_DMA_INTR_STAT_DC1IS_MASK            (0x2U)
+#define ENET_DMA_INTR_STAT_DC1IS_SHIFT           (1U)
+#define ENET_DMA_INTR_STAT_DC1IS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
+#define ENET_DMA_INTR_STAT_MTLIS_MASK            (0x10000U)
+#define ENET_DMA_INTR_STAT_MTLIS_SHIFT           (16U)
+#define ENET_DMA_INTR_STAT_MTLIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
+#define ENET_DMA_INTR_STAT_MACIS_MASK            (0x20000U)
+#define ENET_DMA_INTR_STAT_MACIS_SHIFT           (17U)
+#define ENET_DMA_INTR_STAT_MACIS(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
+
+/*! @name DMA_DBG_STAT - DMA Debug Status */
+#define ENET_DMA_DBG_STAT_AHSTS_MASK             (0x1U)
+#define ENET_DMA_DBG_STAT_AHSTS_SHIFT            (0U)
+#define ENET_DMA_DBG_STAT_AHSTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
+#define ENET_DMA_DBG_STAT_RPS0_MASK              (0xF00U)
+#define ENET_DMA_DBG_STAT_RPS0_SHIFT             (8U)
+#define ENET_DMA_DBG_STAT_RPS0(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
+#define ENET_DMA_DBG_STAT_TPS0_MASK              (0xF000U)
+#define ENET_DMA_DBG_STAT_TPS0_SHIFT             (12U)
+#define ENET_DMA_DBG_STAT_TPS0(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
+#define ENET_DMA_DBG_STAT_RPS1_MASK              (0xF0000U)
+#define ENET_DMA_DBG_STAT_RPS1_SHIFT             (16U)
+#define ENET_DMA_DBG_STAT_RPS1(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
+#define ENET_DMA_DBG_STAT_TPS1_MASK              (0xF00000U)
+#define ENET_DMA_DBG_STAT_TPS1_SHIFT             (20U)
+#define ENET_DMA_DBG_STAT_TPS1(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
+
+/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK      (0x10000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT     (16U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK        (0x1C0000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT       (18U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT           (2U)
+
+/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK      (0x1U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT     (0U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK     (0xEU)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT    (1U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK     (0x10U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT    (4U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK   (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT  (16U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT        (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK      (0x1U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT     (0U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK    (0x7FF8U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT   (3U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK   (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT  (16U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK     (0x80000000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT    (31U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT        (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR -  */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR -  */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR -  */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR -  */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH -  */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK      (0x1U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT     (0U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK      (0x2U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT     (1U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK     (0x4U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT    (2U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK      (0x40U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT     (6U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK     (0x80U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT    (7U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK      (0x100U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT     (8U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK     (0x200U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT    (9U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK     (0x400U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT    (10U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK     (0x800U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT    (11U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK     (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT    (12U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK      (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT     (14U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK      (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT     (15U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT         (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC -  */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF -  */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT  (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT  (2U)
+
+/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK         (0x1U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT        (0U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK        (0x2U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT       (1U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK        (0x4U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT       (2U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK         (0x40U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT        (6U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK        (0x80U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT       (7U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK        (0x100U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT       (8U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK        (0x200U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT       (9U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK        (0x400U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT       (10U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK        (0x800U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT       (11U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK        (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT       (12U)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK        (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT       (14U)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK        (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT       (15U)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK         (0x70000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT        (16U)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_STAT */
+#define ENET_DMA_CH_DMA_CHX_STAT_COUNT           (2U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x40092000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_IRQS                                { ETHERNET_IRQn }
+#define ENET_PMT_IRQS                            { ETHERNET_PMT_IRQn }
+#define ENET_MACLP_IRQS                          { ETHERNET_MACLP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4088];
+  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+  __IO uint32_t PID;                               /**< Peripheral identification register., offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FLEXCOMM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
+#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
+#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
+#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
+#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
+#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
+#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
+#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
+#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+
+/*! @name PID - Peripheral identification register. */
+#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
+#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
+#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT                    (16U)
+#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+/** Peripheral FLEXCOMM0 base address */
+#define FLEXCOMM0_BASE                           (0x40086000u)
+/** Peripheral FLEXCOMM0 base pointer */
+#define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+/** Peripheral FLEXCOMM1 base address */
+#define FLEXCOMM1_BASE                           (0x40087000u)
+/** Peripheral FLEXCOMM1 base pointer */
+#define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+/** Peripheral FLEXCOMM2 base address */
+#define FLEXCOMM2_BASE                           (0x40088000u)
+/** Peripheral FLEXCOMM2 base pointer */
+#define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+/** Peripheral FLEXCOMM3 base address */
+#define FLEXCOMM3_BASE                           (0x40089000u)
+/** Peripheral FLEXCOMM3 base pointer */
+#define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+/** Peripheral FLEXCOMM4 base address */
+#define FLEXCOMM4_BASE                           (0x4008A000u)
+/** Peripheral FLEXCOMM4 base pointer */
+#define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+/** Peripheral FLEXCOMM5 base address */
+#define FLEXCOMM5_BASE                           (0x40096000u)
+/** Peripheral FLEXCOMM5 base pointer */
+#define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+/** Peripheral FLEXCOMM6 base address */
+#define FLEXCOMM6_BASE                           (0x40097000u)
+/** Peripheral FLEXCOMM6 base pointer */
+#define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+/** Peripheral FLEXCOMM7 base address */
+#define FLEXCOMM7_BASE                           (0x40098000u)
+/** Peripheral FLEXCOMM7 base pointer */
+#define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+/** Peripheral FLEXCOMM8 base address */
+#define FLEXCOMM8_BASE                           (0x40099000u)
+/** Peripheral FLEXCOMM8 base pointer */
+#define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+/** Peripheral FLEXCOMM9 base address */
+#define FLEXCOMM9_BASE                           (0x4009A000u)
+/** Peripheral FLEXCOMM9 base pointer */
+#define FLEXCOMM9                                ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+/** Array initializer of FLEXCOMM peripheral base addresses */
+#define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE }
+/** Array initializer of FLEXCOMM peripheral base pointers */
+#define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 }
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t FCTR;                              /**< Control register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t FBWST;                             /**< Wait state register, offset: 0x10 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t FMSSTART;                          /**< Signature start address register, offset: 0x20 */
+  __IO uint32_t FMSSTOP;                           /**< Signature stop-address register, offset: 0x24 */
+       uint8_t RESERVED_2[4];
+  __I  uint32_t FMSW[4];                           /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */
+       uint8_t RESERVED_3[4004];
+  __I  uint32_t FMSTAT;                            /**< Signature generation status register, offset: 0xFE0 */
+       uint8_t RESERVED_4[4];
+  __O  uint32_t FMSTATCLR;                         /**< Signature generation status clear register, offset: 0xFE8 */
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name FCTR - Control register */
+#define FMC_FCTR_FS_RD0_MASK                     (0x8U)
+#define FMC_FCTR_FS_RD0_SHIFT                    (3U)
+#define FMC_FCTR_FS_RD0(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK)
+#define FMC_FCTR_FS_RD1_MASK                     (0x10U)
+#define FMC_FCTR_FS_RD1_SHIFT                    (4U)
+#define FMC_FCTR_FS_RD1(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK)
+
+/*! @name FBWST - Wait state register */
+#define FMC_FBWST_WAITSTATES_MASK                (0xFFU)
+#define FMC_FBWST_WAITSTATES_SHIFT               (0U)
+#define FMC_FBWST_WAITSTATES(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK)
+
+/*! @name FMSSTART - Signature start address register */
+#define FMC_FMSSTART_START_MASK                  (0x1FFFFU)
+#define FMC_FMSSTART_START_SHIFT                 (0U)
+#define FMC_FMSSTART_START(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK)
+
+/*! @name FMSSTOP - Signature stop-address register */
+#define FMC_FMSSTOP_STOP_MASK                    (0x1FFFFU)
+#define FMC_FMSSTOP_STOP_SHIFT                   (0U)
+#define FMC_FMSSTOP_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK)
+#define FMC_FMSSTOP_SIG_START_MASK               (0x20000U)
+#define FMC_FMSSTOP_SIG_START_SHIFT              (17U)
+#define FMC_FMSSTOP_SIG_START(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK)
+
+/*! @name FMSW - Words of 128-bit signature word */
+#define FMC_FMSW_SW_MASK                         (0xFFFFFFFFU)
+#define FMC_FMSW_SW_SHIFT                        (0U)
+#define FMC_FMSW_SW(x)                           (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK)
+
+/* The count of FMC_FMSW */
+#define FMC_FMSW_COUNT                           (4U)
+
+/*! @name FMSTAT - Signature generation status register */
+#define FMC_FMSTAT_SIG_DONE_MASK                 (0x4U)
+#define FMC_FMSTAT_SIG_DONE_SHIFT                (2U)
+#define FMC_FMSTAT_SIG_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK)
+
+/*! @name FMSTATCLR - Signature generation status clear register */
+#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK          (0x4U)
+#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT         (2U)
+#define FMC_FMSTATCLR_SIG_DONE_CLR(x)            (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x40034000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
+ * @{
+ */
+
+/** GINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PORT_POL[2];                       /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+} GINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Register_Masks GINT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - GPIO grouped interrupt control register */
+#define GINT_CTRL_INT_MASK                       (0x1U)
+#define GINT_CTRL_INT_SHIFT                      (0U)
+#define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+#define GINT_CTRL_COMB_MASK                      (0x2U)
+#define GINT_CTRL_COMB_SHIFT                     (1U)
+#define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+#define GINT_CTRL_TRIG_MASK                      (0x4U)
+#define GINT_CTRL_TRIG_SHIFT                     (2U)
+#define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
+#define GINT_PORT_POL_POL_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT                  (0U)
+#define GINT_PORT_POL_POL(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+
+/* The count of GINT_PORT_POL */
+#define GINT_PORT_POL_COUNT                      (2U)
+
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
+#define GINT_PORT_ENA_ENA_MASK                   (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT                  (0U)
+#define GINT_PORT_ENA_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+
+/* The count of GINT_PORT_ENA */
+#define GINT_PORT_ENA_COUNT                      (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GINT_Register_Masks */
+
+
+/* GINT - Peripheral instance base addresses */
+/** Peripheral GINT0 base address */
+#define GINT0_BASE                               (0x40002000u)
+/** Peripheral GINT0 base pointer */
+#define GINT0                                    ((GINT_Type *)GINT0_BASE)
+/** Peripheral GINT1 base address */
+#define GINT1_BASE                               (0x40003000u)
+/** Peripheral GINT1 base pointer */
+#define GINT1                                    ((GINT_Type *)GINT1_BASE)
+/** Array initializer of GINT peripheral base addresses */
+#define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
+/** Array initializer of GINT peripheral base pointers */
+#define GINT_BASE_PTRS                           { GINT0, GINT1 }
+/** Interrupt vectors for the GINT peripheral type */
+#define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t B[6][32];                           /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+       uint8_t RESERVED_0[3904];
+  __IO uint32_t W[6][32];                          /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+       uint8_t RESERVED_1[3328];
+  __IO uint32_t DIR[6];                            /**< Direction registers, array offset: 0x2000, array step: 0x4 */
+       uint8_t RESERVED_2[104];
+  __IO uint32_t MASK[6];                           /**< Mask register, array offset: 0x2080, array step: 0x4 */
+       uint8_t RESERVED_3[104];
+  __IO uint32_t PIN[6];                            /**< Port pin register, array offset: 0x2100, array step: 0x4 */
+       uint8_t RESERVED_4[104];
+  __IO uint32_t MPIN[6];                           /**< Masked port register, array offset: 0x2180, array step: 0x4 */
+       uint8_t RESERVED_5[104];
+  __IO uint32_t SET[6];                            /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+       uint8_t RESERVED_6[104];
+  __O  uint32_t CLR[6];                            /**< Clear port, array offset: 0x2280, array step: 0x4 */
+       uint8_t RESERVED_7[104];
+  __O  uint32_t NOT[6];                            /**< Toggle port, array offset: 0x2300, array step: 0x4 */
+       uint8_t RESERVED_8[104];
+  __O  uint32_t DIRSET[6];                         /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+       uint8_t RESERVED_9[104];
+  __O  uint32_t DIRCLR[6];                         /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+       uint8_t RESERVED_10[104];
+  __O  uint32_t DIRNOT[6];                         /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_B_PBYTE_MASK                        (0x1U)
+#define GPIO_B_PBYTE_SHIFT                       (0U)
+#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT                             (6U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2                            (32U)
+
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT                       (0U)
+#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT                             (6U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2                            (32U)
+
+/*! @name DIR - Direction registers */
+#define GPIO_DIR_DIRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT                      (0U)
+#define GPIO_DIR_DIRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT                           (6U)
+
+/*! @name MASK - Mask register */
+#define GPIO_MASK_MASKP_MASK                     (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT                    (0U)
+#define GPIO_MASK_MASKP(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT                          (6U)
+
+/*! @name PIN - Port pin register */
+#define GPIO_PIN_PORT_MASK                       (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT                      (0U)
+#define GPIO_PIN_PORT(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT                           (6U)
+
+/*! @name MPIN - Masked port register */
+#define GPIO_MPIN_MPORTP_MASK                    (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT                   (0U)
+#define GPIO_MPIN_MPORTP(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT                          (6U)
+
+/*! @name SET - Write: Set register for port Read: output bits for port */
+#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT                      (0U)
+#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT                           (6U)
+
+/*! @name CLR - Clear port */
+#define GPIO_CLR_CLRP_MASK                       (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT                      (0U)
+#define GPIO_CLR_CLRP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT                           (6U)
+
+/*! @name NOT - Toggle port */
+#define GPIO_NOT_NOTP_MASK                       (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT                      (0U)
+#define GPIO_NOT_NOTP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT                           (6U)
+
+/*! @name DIRSET - Set pin direction bits for port */
+#define GPIO_DIRSET_DIRSETP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT                (0U)
+#define GPIO_DIRSET_DIRSETP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT                        (6U)
+
+/*! @name DIRCLR - Clear pin direction bits for port */
+#define GPIO_DIRCLR_DIRCLRP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT                (0U)
+#define GPIO_DIRCLR_DIRCLRP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT                        (6U)
+
+/*! @name DIRNOT - Toggle pin direction bits for port */
+#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
+#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT                        (6U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE                                (0x4008C000u)
+/** Peripheral GPIO base pointer */
+#define GPIO                                     ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIO }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[2048];
+  __IO uint32_t CFG;                               /**< Configuration for shared functions., offset: 0x800 */
+  __IO uint32_t STAT;                              /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set and read register., offset: 0x808 */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register., offset: 0x80C */
+  __IO uint32_t TIMEOUT;                           /**< Time-out value register., offset: 0x810 */
+  __IO uint32_t CLKDIV;                            /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t MSTCTL;                            /**< Master control register., offset: 0x820 */
+  __IO uint32_t MSTTIME;                           /**< Master timing configuration., offset: 0x824 */
+  __IO uint32_t MSTDAT;                            /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+       uint8_t RESERVED_2[20];
+  __IO uint32_t SLVCTL;                            /**< Slave control register., offset: 0x840 */
+  __IO uint32_t SLVDAT;                            /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+  __IO uint32_t SLVADR[4];                         /**< Slave address register., array offset: 0x848, array step: 0x4 */
+  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for address 0., offset: 0x858 */
+       uint8_t RESERVED_3[36];
+  __I  uint32_t MONRXDAT;                          /**< Monitor receiver data register., offset: 0x880 */
+       uint8_t RESERVED_4[1912];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration for shared functions. */
+#define I2C_CFG_MSTEN_MASK                       (0x1U)
+#define I2C_CFG_MSTEN_SHIFT                      (0U)
+#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK                       (0x2U)
+#define I2C_CFG_SLVEN_SHIFT                      (1U)
+#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK                       (0x4U)
+#define I2C_CFG_MONEN_SHIFT                      (2U)
+#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
+#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
+#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
+#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
+#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT                (0U)
+#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
+#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
+#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
+#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT                (8U)
+#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
+#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
+#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT                    (12U)
+#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT                    (14U)
+#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
+#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK                     (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT                    (16U)
+#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK                      (0x20000U)
+#define I2C_STAT_MONOV_SHIFT                     (17U)
+#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
+#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT                   (19U)
+#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
+#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
+#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+
+/*! @name INTENSET - Interrupt Enable Set and read register. */
+#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
+#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
+#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
+#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
+#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
+#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
+#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
+#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
+#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
+#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
+#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
+#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
+#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
+#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
+#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
+#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
+#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
+#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
+#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
+#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+
+/*! @name TIMEOUT - Time-out value register. */
+#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
+#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT                     (4U)
+#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
+#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
+#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
+#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
+#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
+#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
+#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
+#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
+#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
+#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
+#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
+#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
+#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
+#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
+#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+
+/*! @name MSTCTL - Master control register. */
+#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
+#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
+#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
+#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
+#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+
+/*! @name MSTTIME - Master timing configuration. */
+#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
+#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
+#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
+#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT                    (0U)
+#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+
+/*! @name SLVCTL - Slave control register. */
+#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
+#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
+#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
+#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
+#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
+#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
+#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT                    (0U)
+#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+
+/*! @name SLVADR - Slave address register. */
+#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
+#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
+#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
+#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT                         (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */
+#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
+#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
+#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+
+/*! @name MONRXDAT - Monitor receiver data register. */
+#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
+#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
+#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
+#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
+#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define I2C_ID_APERTURE_MASK                     (0xFFU)
+#define I2C_ID_APERTURE_SHIFT                    (0U)
+#define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+#define I2C_ID_MINOR_REV_MASK                    (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT                   (8U)
+#define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+#define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT                   (12U)
+#define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+#define I2C_ID_ID_MASK                           (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT                          (16U)
+#define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40086000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40087000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x40088000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE                                (0x40089000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3                                     ((I2C_Type *)I2C3_BASE)
+/** Peripheral I2C4 base address */
+#define I2C4_BASE                                (0x4008A000u)
+/** Peripheral I2C4 base pointer */
+#define I2C4                                     ((I2C_Type *)I2C4_BASE)
+/** Peripheral I2C5 base address */
+#define I2C5_BASE                                (0x40096000u)
+/** Peripheral I2C5 base pointer */
+#define I2C5                                     ((I2C_Type *)I2C5_BASE)
+/** Peripheral I2C6 base address */
+#define I2C6_BASE                                (0x40097000u)
+/** Peripheral I2C6 base pointer */
+#define I2C6                                     ((I2C_Type *)I2C6_BASE)
+/** Peripheral I2C7 base address */
+#define I2C7_BASE                                (0x40098000u)
+/** Peripheral I2C7 base pointer */
+#define I2C7                                     ((I2C_Type *)I2C7_BASE)
+/** Peripheral I2C8 base address */
+#define I2C8_BASE                                (0x40099000u)
+/** Peripheral I2C8 base pointer */
+#define I2C8                                     ((I2C_Type *)I2C8_BASE)
+/** Peripheral I2C9 base address */
+#define I2C9_BASE                                (0x4009A000u)
+/** Peripheral I2C9 base pointer */
+#define I2C9                                     ((I2C_Type *)I2C9_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[32];
+  struct {                                         /* offset: 0x20, array step: 0x20 */
+    __IO uint32_t PCFG1;                             /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */
+    __IO uint32_t PCFG2;                             /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */
+    __IO uint32_t PSTAT;                             /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */
+         uint8_t RESERVED_0[20];
+  } SECCHANNEL[3];
+       uint8_t RESERVED_1[2944];
+  __IO uint32_t CFG1;                              /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
+  __IO uint32_t CFG2;                              /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
+  __IO uint32_t STAT;                              /**< Status register for the primary channel pair., offset: 0xC08 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t DIV;                               /**< Clock divider, used by all channel pairs., offset: 0xC1C */
+       uint8_t RESERVED_3[480];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_5[4];
+  __O  uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+  __O  uint32_t FIFOWR48H;                         /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
+       uint8_t RESERVED_6[8];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+  __I  uint32_t FIFORD48H;                         /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
+       uint8_t RESERVED_7[8];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
+       uint8_t RESERVED_8[4020];
+  __I  uint32_t ID;                                /**< I2S Module identification, offset: 0x1DFC */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK     (0x1U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT    (0U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK     (0x400U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT    (10U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
+
+/* The count of I2S_SECCHANNEL_PCFG1 */
+#define I2S_SECCHANNEL_PCFG1_COUNT               (3U)
+
+/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK       (0x1FF0000U)
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT      (16U)
+#define I2S_SECCHANNEL_PCFG2_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
+
+/* The count of I2S_SECCHANNEL_PCFG2 */
+#define I2S_SECCHANNEL_PCFG2_COUNT               (3U)
+
+/*! @name SECCHANNEL_PSTAT - Status register for channel pair */
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK           (0x1U)
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT          (0U)
+#define I2S_SECCHANNEL_PSTAT_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK      (0x2U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT     (1U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x)        (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
+#define I2S_SECCHANNEL_PSTAT_LR_MASK             (0x4U)
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT            (2U)
+#define I2S_SECCHANNEL_PSTAT_LR(x)               (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK     (0x8U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT    (3U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
+
+/* The count of I2S_SECCHANNEL_PSTAT */
+#define I2S_SECCHANNEL_PSTAT_COUNT               (3U)
+
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
+#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
+#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
+#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
+#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
+#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+#define I2S_CFG1_MODE_MASK                       (0xC0U)
+#define I2S_CFG1_MODE_SHIFT                      (6U)
+#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
+#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
+#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
+#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
+#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
+#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT                    (13U)
+#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT                   (16U)
+#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
+#define I2S_CFG2_FRAMELEN_MASK                   (0x1FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
+#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+#define I2S_CFG2_POSITION_MASK                   (0x1FF0000U)
+#define I2S_CFG2_POSITION_SHIFT                  (16U)
+#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+
+/*! @name STAT - Status register for the primary channel pair. */
+#define I2S_STAT_BUSY_MASK                       (0x1U)
+#define I2S_STAT_BUSY_SHIFT                      (0U)
+#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
+#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+#define I2S_STAT_LR_MASK                         (0x4U)
+#define I2S_STAT_LR_SHIFT                        (2U)
+#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
+#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+
+/*! @name DIV - Clock divider, used by all channel pairs. */
+#define I2S_DIV_DIV_MASK                         (0xFFFU)
+#define I2S_DIV_DIV_SHIFT                        (0U)
+#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
+#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
+#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+#define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
+#define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
+#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
+#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
+#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
+#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
+#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
+#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
+#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
+#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+#define I2S_FIFOCFG_POPDBG_MASK                  (0x40000U)
+#define I2S_FIFOCFG_POPDBG_SHIFT                 (18U)
+#define I2S_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
+#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
+#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
+#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
+#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
+#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
+#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
+#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
+#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
+#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
+#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
+#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
+#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
+#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
+#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
+#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
+#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
+#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
+#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
+#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
+#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
+#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
+#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+
+/*! @name ID - I2S Module identification */
+#define I2S_ID_Aperture_MASK                     (0xFFU)
+#define I2S_ID_Aperture_SHIFT                    (0U)
+#define I2S_ID_Aperture(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
+#define I2S_ID_Minor_Rev_MASK                    (0xF00U)
+#define I2S_ID_Minor_Rev_SHIFT                   (8U)
+#define I2S_ID_Minor_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
+#define I2S_ID_Major_Rev_MASK                    (0xF000U)
+#define I2S_ID_Major_Rev_SHIFT                   (12U)
+#define I2S_ID_Major_Rev(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
+#define I2S_ID_ID_MASK                           (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT                          (16U)
+#define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x40097000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Peripheral I2S1 base address */
+#define I2S1_BASE                                (0x40098000u)
+/** Peripheral I2S1 base pointer */
+#define I2S1                                     ((I2S_Type *)I2S1_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0, I2S1 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS                                 { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SCT0_INMUX[7];                     /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[164];
+  __IO uint32_t PINTSEL[8];                        /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
+  __IO uint32_t DMA_ITRIG_INMUX[30];               /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t DMA_OTRIG_INMUX[4];                /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
+  __IO uint32_t FREQMEAS_TARGET;                   /**< Selection for frequency measurement target clock, offset: 0x184 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- INPUTMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name SCT0_INMUX - Trigger select register for DMA channel */
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK           (0x1FU)
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT          (0U)
+#define INPUTMUX_SCT0_INMUX_INP_N(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
+
+/* The count of INPUTMUX_SCT0_INMUX */
+#define INPUTMUX_SCT0_INMUX_COUNT                (7U)
+
+/*! @name PINTSEL - Pin interrupt select register */
+#define INPUTMUX_PINTSEL_INTPIN_MASK             (0xFFU)
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT            (0U)
+#define INPUTMUX_PINTSEL_INTPIN(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
+
+/* The count of INPUTMUX_PINTSEL */
+#define INPUTMUX_PINTSEL_COUNT                   (8U)
+
+/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT       (0U)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_ITRIG_INMUX */
+#define INPUTMUX_DMA_ITRIG_INMUX_COUNT           (30U)
+
+/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK        (0x1FU)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT       (0U)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_OTRIG_INMUX */
+#define INPUTMUX_DMA_OTRIG_INMUX_COUNT           (4U)
+
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
+
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK      (0x1FU)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT     (0U)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX base address */
+#define INPUTMUX_BASE                            (0x40005000u)
+/** Peripheral INPUTMUX base pointer */
+#define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS                       { INPUTMUX }
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
+ * @{
+ */
+
+/** IOCON - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PIO[6][32];                        /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
+} IOCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- IOCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks
+ * @{
+ */
+
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
+#define IOCON_PIO_FUNC_MASK                      (0xFU)
+#define IOCON_PIO_FUNC_SHIFT                     (0U)
+#define IOCON_PIO_FUNC(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
+#define IOCON_PIO_MODE_MASK                      (0x30U)
+#define IOCON_PIO_MODE_SHIFT                     (4U)
+#define IOCON_PIO_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
+#define IOCON_PIO_I2CSLEW_MASK                   (0x40U)
+#define IOCON_PIO_I2CSLEW_SHIFT                  (6U)
+#define IOCON_PIO_I2CSLEW(x)                     (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
+#define IOCON_PIO_INVERT_MASK                    (0x80U)
+#define IOCON_PIO_INVERT_SHIFT                   (7U)
+#define IOCON_PIO_INVERT(x)                      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
+#define IOCON_PIO_DIGIMODE_MASK                  (0x100U)
+#define IOCON_PIO_DIGIMODE_SHIFT                 (8U)
+#define IOCON_PIO_DIGIMODE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
+#define IOCON_PIO_FILTEROFF_MASK                 (0x200U)
+#define IOCON_PIO_FILTEROFF_SHIFT                (9U)
+#define IOCON_PIO_FILTEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
+#define IOCON_PIO_I2CDRIVE_MASK                  (0x400U)
+#define IOCON_PIO_I2CDRIVE_SHIFT                 (10U)
+#define IOCON_PIO_I2CDRIVE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
+#define IOCON_PIO_SLEW_MASK                      (0x400U)
+#define IOCON_PIO_SLEW_SHIFT                     (10U)
+#define IOCON_PIO_SLEW(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
+#define IOCON_PIO_OD_MASK                        (0x800U)
+#define IOCON_PIO_OD_SHIFT                       (11U)
+#define IOCON_PIO_OD(x)                          (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
+#define IOCON_PIO_I2CFILTER_MASK                 (0x800U)
+#define IOCON_PIO_I2CFILTER_SHIFT                (11U)
+#define IOCON_PIO_I2CFILTER(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT                          (6U)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT2                         (32U)
+
+
+/*!
+ * @}
+ */ /* end of group IOCON_Register_Masks */
+
+
+/* IOCON - Peripheral instance base addresses */
+/** Peripheral IOCON base address */
+#define IOCON_BASE                               (0x40001000u)
+/** Peripheral IOCON base pointer */
+#define IOCON                                    ((IOCON_Type *)IOCON_BASE)
+/** Array initializer of IOCON peripheral base addresses */
+#define IOCON_BASE_ADDRS                         { IOCON_BASE }
+/** Array initializer of IOCON peripheral base pointers */
+#define IOCON_BASE_PTRS                          { IOCON }
+
+/*!
+ * @}
+ */ /* end of group IOCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TIMH;                              /**< Horizontal Timing Control register, offset: 0x0 */
+  __IO uint32_t TIMV;                              /**< Vertical Timing Control register, offset: 0x4 */
+  __IO uint32_t POL;                               /**< Clock and Signal Polarity Control register, offset: 0x8 */
+  __IO uint32_t LE;                                /**< Line End Control register, offset: 0xC */
+  __IO uint32_t UPBASE;                            /**< Upper Panel Frame Base Address register, offset: 0x10 */
+  __IO uint32_t LPBASE;                            /**< Lower Panel Frame Base Address register, offset: 0x14 */
+  __IO uint32_t CTRL;                              /**< LCD Control register, offset: 0x18 */
+  __IO uint32_t INTMSK;                            /**< Interrupt Mask register, offset: 0x1C */
+  __I  uint32_t INTRAW;                            /**< Raw Interrupt Status register, offset: 0x20 */
+  __I  uint32_t INTSTAT;                           /**< Masked Interrupt Status register, offset: 0x24 */
+  __IO uint32_t INTCLR;                            /**< Interrupt Clear register, offset: 0x28 */
+  __I  uint32_t UPCURR;                            /**< Upper Panel Current Address Value register, offset: 0x2C */
+  __I  uint32_t LPCURR;                            /**< Lower Panel Current Address Value register, offset: 0x30 */
+       uint8_t RESERVED_0[460];
+  __IO uint32_t PAL[128];                          /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_1[1024];
+  __IO uint32_t CRSR_IMG[256];                     /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */
+  __IO uint32_t CRSR_CTRL;                         /**< Cursor Control register, offset: 0xC00 */
+  __IO uint32_t CRSR_CFG;                          /**< Cursor Configuration register, offset: 0xC04 */
+  __IO uint32_t CRSR_PAL0;                         /**< Cursor Palette register 0, offset: 0xC08 */
+  __IO uint32_t CRSR_PAL1;                         /**< Cursor Palette register 1, offset: 0xC0C */
+  __IO uint32_t CRSR_XY;                           /**< Cursor XY Position register, offset: 0xC10 */
+  __IO uint32_t CRSR_CLIP;                         /**< Cursor Clip Position register, offset: 0xC14 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t CRSR_INTMSK;                       /**< Cursor Interrupt Mask register, offset: 0xC20 */
+  __O  uint32_t CRSR_INTCLR;                       /**< Cursor Interrupt Clear register, offset: 0xC24 */
+  __I  uint32_t CRSR_INTRAW;                       /**< Cursor Raw Interrupt Status register, offset: 0xC28 */
+  __I  uint32_t CRSR_INTSTAT;                      /**< Cursor Masked Interrupt Status register, offset: 0xC2C */
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/*! @name TIMH - Horizontal Timing Control register */
+#define LCD_TIMH_PPL_MASK                        (0xFCU)
+#define LCD_TIMH_PPL_SHIFT                       (2U)
+#define LCD_TIMH_PPL(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)
+#define LCD_TIMH_HSW_MASK                        (0xFF00U)
+#define LCD_TIMH_HSW_SHIFT                       (8U)
+#define LCD_TIMH_HSW(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)
+#define LCD_TIMH_HFP_MASK                        (0xFF0000U)
+#define LCD_TIMH_HFP_SHIFT                       (16U)
+#define LCD_TIMH_HFP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)
+#define LCD_TIMH_HBP_MASK                        (0xFF000000U)
+#define LCD_TIMH_HBP_SHIFT                       (24U)
+#define LCD_TIMH_HBP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)
+
+/*! @name TIMV - Vertical Timing Control register */
+#define LCD_TIMV_LPP_MASK                        (0x3FFU)
+#define LCD_TIMV_LPP_SHIFT                       (0U)
+#define LCD_TIMV_LPP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)
+#define LCD_TIMV_VSW_MASK                        (0xFC00U)
+#define LCD_TIMV_VSW_SHIFT                       (10U)
+#define LCD_TIMV_VSW(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)
+#define LCD_TIMV_VFP_MASK                        (0xFF0000U)
+#define LCD_TIMV_VFP_SHIFT                       (16U)
+#define LCD_TIMV_VFP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)
+#define LCD_TIMV_VBP_MASK                        (0xFF000000U)
+#define LCD_TIMV_VBP_SHIFT                       (24U)
+#define LCD_TIMV_VBP(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)
+
+/*! @name POL - Clock and Signal Polarity Control register */
+#define LCD_POL_PCD_LO_MASK                      (0x1FU)
+#define LCD_POL_PCD_LO_SHIFT                     (0U)
+#define LCD_POL_PCD_LO(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)
+#define LCD_POL_ACB_MASK                         (0x7C0U)
+#define LCD_POL_ACB_SHIFT                        (6U)
+#define LCD_POL_ACB(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)
+#define LCD_POL_IVS_MASK                         (0x800U)
+#define LCD_POL_IVS_SHIFT                        (11U)
+#define LCD_POL_IVS(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)
+#define LCD_POL_IHS_MASK                         (0x1000U)
+#define LCD_POL_IHS_SHIFT                        (12U)
+#define LCD_POL_IHS(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)
+#define LCD_POL_IPC_MASK                         (0x2000U)
+#define LCD_POL_IPC_SHIFT                        (13U)
+#define LCD_POL_IPC(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)
+#define LCD_POL_IOE_MASK                         (0x4000U)
+#define LCD_POL_IOE_SHIFT                        (14U)
+#define LCD_POL_IOE(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)
+#define LCD_POL_CPL_MASK                         (0x3FF0000U)
+#define LCD_POL_CPL_SHIFT                        (16U)
+#define LCD_POL_CPL(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)
+#define LCD_POL_BCD_MASK                         (0x4000000U)
+#define LCD_POL_BCD_SHIFT                        (26U)
+#define LCD_POL_BCD(x)                           (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)
+#define LCD_POL_PCD_HI_MASK                      (0xF8000000U)
+#define LCD_POL_PCD_HI_SHIFT                     (27U)
+#define LCD_POL_PCD_HI(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)
+
+/*! @name LE - Line End Control register */
+#define LCD_LE_LED_MASK                          (0x7FU)
+#define LCD_LE_LED_SHIFT                         (0U)
+#define LCD_LE_LED(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)
+#define LCD_LE_LEE_MASK                          (0x10000U)
+#define LCD_LE_LEE_SHIFT                         (16U)
+#define LCD_LE_LEE(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)
+
+/*! @name UPBASE - Upper Panel Frame Base Address register */
+#define LCD_UPBASE_LCDUPBASE_MASK                (0xFFFFFFF8U)
+#define LCD_UPBASE_LCDUPBASE_SHIFT               (3U)
+#define LCD_UPBASE_LCDUPBASE(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)
+
+/*! @name LPBASE - Lower Panel Frame Base Address register */
+#define LCD_LPBASE_LCDLPBASE_MASK                (0xFFFFFFF8U)
+#define LCD_LPBASE_LCDLPBASE_SHIFT               (3U)
+#define LCD_LPBASE_LCDLPBASE(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)
+
+/*! @name CTRL - LCD Control register */
+#define LCD_CTRL_LCDEN_MASK                      (0x1U)
+#define LCD_CTRL_LCDEN_SHIFT                     (0U)
+#define LCD_CTRL_LCDEN(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)
+#define LCD_CTRL_LCDBPP_MASK                     (0xEU)
+#define LCD_CTRL_LCDBPP_SHIFT                    (1U)
+#define LCD_CTRL_LCDBPP(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)
+#define LCD_CTRL_LCDBW_MASK                      (0x10U)
+#define LCD_CTRL_LCDBW_SHIFT                     (4U)
+#define LCD_CTRL_LCDBW(x)                        (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)
+#define LCD_CTRL_LCDTFT_MASK                     (0x20U)
+#define LCD_CTRL_LCDTFT_SHIFT                    (5U)
+#define LCD_CTRL_LCDTFT(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)
+#define LCD_CTRL_LCDMONO8_MASK                   (0x40U)
+#define LCD_CTRL_LCDMONO8_SHIFT                  (6U)
+#define LCD_CTRL_LCDMONO8(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)
+#define LCD_CTRL_LCDDUAL_MASK                    (0x80U)
+#define LCD_CTRL_LCDDUAL_SHIFT                   (7U)
+#define LCD_CTRL_LCDDUAL(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)
+#define LCD_CTRL_BGR_MASK                        (0x100U)
+#define LCD_CTRL_BGR_SHIFT                       (8U)
+#define LCD_CTRL_BGR(x)                          (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)
+#define LCD_CTRL_BEBO_MASK                       (0x200U)
+#define LCD_CTRL_BEBO_SHIFT                      (9U)
+#define LCD_CTRL_BEBO(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)
+#define LCD_CTRL_BEPO_MASK                       (0x400U)
+#define LCD_CTRL_BEPO_SHIFT                      (10U)
+#define LCD_CTRL_BEPO(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)
+#define LCD_CTRL_LCDPWR_MASK                     (0x800U)
+#define LCD_CTRL_LCDPWR_SHIFT                    (11U)
+#define LCD_CTRL_LCDPWR(x)                       (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)
+#define LCD_CTRL_LCDVCOMP_MASK                   (0x3000U)
+#define LCD_CTRL_LCDVCOMP_SHIFT                  (12U)
+#define LCD_CTRL_LCDVCOMP(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)
+#define LCD_CTRL_WATERMARK_MASK                  (0x10000U)
+#define LCD_CTRL_WATERMARK_SHIFT                 (16U)
+#define LCD_CTRL_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)
+
+/*! @name INTMSK - Interrupt Mask register */
+#define LCD_INTMSK_FUFIM_MASK                    (0x2U)
+#define LCD_INTMSK_FUFIM_SHIFT                   (1U)
+#define LCD_INTMSK_FUFIM(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)
+#define LCD_INTMSK_LNBUIM_MASK                   (0x4U)
+#define LCD_INTMSK_LNBUIM_SHIFT                  (2U)
+#define LCD_INTMSK_LNBUIM(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)
+#define LCD_INTMSK_VCOMPIM_MASK                  (0x8U)
+#define LCD_INTMSK_VCOMPIM_SHIFT                 (3U)
+#define LCD_INTMSK_VCOMPIM(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)
+#define LCD_INTMSK_BERIM_MASK                    (0x10U)
+#define LCD_INTMSK_BERIM_SHIFT                   (4U)
+#define LCD_INTMSK_BERIM(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)
+
+/*! @name INTRAW - Raw Interrupt Status register */
+#define LCD_INTRAW_FUFRIS_MASK                   (0x2U)
+#define LCD_INTRAW_FUFRIS_SHIFT                  (1U)
+#define LCD_INTRAW_FUFRIS(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)
+#define LCD_INTRAW_LNBURIS_MASK                  (0x4U)
+#define LCD_INTRAW_LNBURIS_SHIFT                 (2U)
+#define LCD_INTRAW_LNBURIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)
+#define LCD_INTRAW_VCOMPRIS_MASK                 (0x8U)
+#define LCD_INTRAW_VCOMPRIS_SHIFT                (3U)
+#define LCD_INTRAW_VCOMPRIS(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)
+#define LCD_INTRAW_BERRAW_MASK                   (0x10U)
+#define LCD_INTRAW_BERRAW_SHIFT                  (4U)
+#define LCD_INTRAW_BERRAW(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)
+
+/*! @name INTSTAT - Masked Interrupt Status register */
+#define LCD_INTSTAT_FUFMIS_MASK                  (0x2U)
+#define LCD_INTSTAT_FUFMIS_SHIFT                 (1U)
+#define LCD_INTSTAT_FUFMIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)
+#define LCD_INTSTAT_LNBUMIS_MASK                 (0x4U)
+#define LCD_INTSTAT_LNBUMIS_SHIFT                (2U)
+#define LCD_INTSTAT_LNBUMIS(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)
+#define LCD_INTSTAT_VCOMPMIS_MASK                (0x8U)
+#define LCD_INTSTAT_VCOMPMIS_SHIFT               (3U)
+#define LCD_INTSTAT_VCOMPMIS(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)
+#define LCD_INTSTAT_BERMIS_MASK                  (0x10U)
+#define LCD_INTSTAT_BERMIS_SHIFT                 (4U)
+#define LCD_INTSTAT_BERMIS(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)
+
+/*! @name INTCLR - Interrupt Clear register */
+#define LCD_INTCLR_FUFIC_MASK                    (0x2U)
+#define LCD_INTCLR_FUFIC_SHIFT                   (1U)
+#define LCD_INTCLR_FUFIC(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)
+#define LCD_INTCLR_LNBUIC_MASK                   (0x4U)
+#define LCD_INTCLR_LNBUIC_SHIFT                  (2U)
+#define LCD_INTCLR_LNBUIC(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)
+#define LCD_INTCLR_VCOMPIC_MASK                  (0x8U)
+#define LCD_INTCLR_VCOMPIC_SHIFT                 (3U)
+#define LCD_INTCLR_VCOMPIC(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)
+#define LCD_INTCLR_BERIC_MASK                    (0x10U)
+#define LCD_INTCLR_BERIC_SHIFT                   (4U)
+#define LCD_INTCLR_BERIC(x)                      (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)
+
+/*! @name UPCURR - Upper Panel Current Address Value register */
+#define LCD_UPCURR_LCDUPCURR_MASK                (0xFFFFFFFFU)
+#define LCD_UPCURR_LCDUPCURR_SHIFT               (0U)
+#define LCD_UPCURR_LCDUPCURR(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)
+
+/*! @name LPCURR - Lower Panel Current Address Value register */
+#define LCD_LPCURR_LCDLPCURR_MASK                (0xFFFFFFFFU)
+#define LCD_LPCURR_LCDLPCURR_SHIFT               (0U)
+#define LCD_LPCURR_LCDLPCURR(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)
+
+/*! @name PAL - 256x16-bit Color Palette registers */
+#define LCD_PAL_R04_0_MASK                       (0x1FU)
+#define LCD_PAL_R04_0_SHIFT                      (0U)
+#define LCD_PAL_R04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)
+#define LCD_PAL_G04_0_MASK                       (0x3E0U)
+#define LCD_PAL_G04_0_SHIFT                      (5U)
+#define LCD_PAL_G04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)
+#define LCD_PAL_B04_0_MASK                       (0x7C00U)
+#define LCD_PAL_B04_0_SHIFT                      (10U)
+#define LCD_PAL_B04_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)
+#define LCD_PAL_I0_MASK                          (0x8000U)
+#define LCD_PAL_I0_SHIFT                         (15U)
+#define LCD_PAL_I0(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)
+#define LCD_PAL_R14_0_MASK                       (0x1F0000U)
+#define LCD_PAL_R14_0_SHIFT                      (16U)
+#define LCD_PAL_R14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)
+#define LCD_PAL_G14_0_MASK                       (0x3E00000U)
+#define LCD_PAL_G14_0_SHIFT                      (21U)
+#define LCD_PAL_G14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)
+#define LCD_PAL_B14_0_MASK                       (0x7C000000U)
+#define LCD_PAL_B14_0_SHIFT                      (26U)
+#define LCD_PAL_B14_0(x)                         (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)
+#define LCD_PAL_I1_MASK                          (0x80000000U)
+#define LCD_PAL_I1_SHIFT                         (31U)
+#define LCD_PAL_I1(x)                            (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)
+
+/* The count of LCD_PAL */
+#define LCD_PAL_COUNT                            (128U)
+
+/*! @name CRSR_IMG - Cursor Image registers */
+#define LCD_CRSR_IMG_CRSR_IMG_MASK               (0xFFFFFFFFU)
+#define LCD_CRSR_IMG_CRSR_IMG_SHIFT              (0U)
+#define LCD_CRSR_IMG_CRSR_IMG(x)                 (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)
+
+/* The count of LCD_CRSR_IMG */
+#define LCD_CRSR_IMG_COUNT                       (256U)
+
+/*! @name CRSR_CTRL - Cursor Control register */
+#define LCD_CRSR_CTRL_CRSRON_MASK                (0x1U)
+#define LCD_CRSR_CTRL_CRSRON_SHIFT               (0U)
+#define LCD_CRSR_CTRL_CRSRON(x)                  (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK            (0x30U)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT           (4U)
+#define LCD_CRSR_CTRL_CRSRNUM1_0(x)              (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)
+
+/*! @name CRSR_CFG - Cursor Configuration register */
+#define LCD_CRSR_CFG_CRSRSIZE_MASK               (0x1U)
+#define LCD_CRSR_CFG_CRSRSIZE_SHIFT              (0U)
+#define LCD_CRSR_CFG_CRSRSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)
+#define LCD_CRSR_CFG_FRAMESYNC_MASK              (0x2U)
+#define LCD_CRSR_CFG_FRAMESYNC_SHIFT             (1U)
+#define LCD_CRSR_CFG_FRAMESYNC(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)
+
+/*! @name CRSR_PAL0 - Cursor Palette register 0 */
+#define LCD_CRSR_PAL0_RED_MASK                   (0xFFU)
+#define LCD_CRSR_PAL0_RED_SHIFT                  (0U)
+#define LCD_CRSR_PAL0_RED(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)
+#define LCD_CRSR_PAL0_GREEN_MASK                 (0xFF00U)
+#define LCD_CRSR_PAL0_GREEN_SHIFT                (8U)
+#define LCD_CRSR_PAL0_GREEN(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)
+#define LCD_CRSR_PAL0_BLUE_MASK                  (0xFF0000U)
+#define LCD_CRSR_PAL0_BLUE_SHIFT                 (16U)
+#define LCD_CRSR_PAL0_BLUE(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)
+
+/*! @name CRSR_PAL1 - Cursor Palette register 1 */
+#define LCD_CRSR_PAL1_RED_MASK                   (0xFFU)
+#define LCD_CRSR_PAL1_RED_SHIFT                  (0U)
+#define LCD_CRSR_PAL1_RED(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)
+#define LCD_CRSR_PAL1_GREEN_MASK                 (0xFF00U)
+#define LCD_CRSR_PAL1_GREEN_SHIFT                (8U)
+#define LCD_CRSR_PAL1_GREEN(x)                   (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)
+#define LCD_CRSR_PAL1_BLUE_MASK                  (0xFF0000U)
+#define LCD_CRSR_PAL1_BLUE_SHIFT                 (16U)
+#define LCD_CRSR_PAL1_BLUE(x)                    (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)
+
+/*! @name CRSR_XY - Cursor XY Position register */
+#define LCD_CRSR_XY_CRSRX_MASK                   (0x3FFU)
+#define LCD_CRSR_XY_CRSRX_SHIFT                  (0U)
+#define LCD_CRSR_XY_CRSRX(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)
+#define LCD_CRSR_XY_CRSRY_MASK                   (0x3FF0000U)
+#define LCD_CRSR_XY_CRSRY_SHIFT                  (16U)
+#define LCD_CRSR_XY_CRSRY(x)                     (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)
+
+/*! @name CRSR_CLIP - Cursor Clip Position register */
+#define LCD_CRSR_CLIP_CRSRCLIPX_MASK             (0x3FU)
+#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT            (0U)
+#define LCD_CRSR_CLIP_CRSRCLIPX(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)
+#define LCD_CRSR_CLIP_CRSRCLIPY_MASK             (0x3F00U)
+#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT            (8U)
+#define LCD_CRSR_CLIP_CRSRCLIPY(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)
+
+/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */
+#define LCD_CRSR_INTMSK_CRSRIM_MASK              (0x1U)
+#define LCD_CRSR_INTMSK_CRSRIM_SHIFT             (0U)
+#define LCD_CRSR_INTMSK_CRSRIM(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)
+
+/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */
+#define LCD_CRSR_INTCLR_CRSRIC_MASK              (0x1U)
+#define LCD_CRSR_INTCLR_CRSRIC_SHIFT             (0U)
+#define LCD_CRSR_INTCLR_CRSRIC(x)                (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)
+
+/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */
+#define LCD_CRSR_INTRAW_CRSRRIS_MASK             (0x1U)
+#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT            (0U)
+#define LCD_CRSR_INTRAW_CRSRRIS(x)               (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)
+
+/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */
+#define LCD_CRSR_INTSTAT_CRSRMIS_MASK            (0x1U)
+#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT           (0U)
+#define LCD_CRSR_INTSTAT_CRSRMIS(x)              (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE                                 (0x40083000u)
+/** Peripheral LCD base pointer */
+#define LCD                                      ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base addresses */
+#define LCD_BASE_ADDRS                           { LCD_BASE }
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASE_PTRS                            { LCD }
+/** Interrupt vectors for the LCD peripheral type */
+#define LCD_IRQS                                 { LCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MRT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x10 */
+    __IO uint32_t INTVAL;                            /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
+    __I  uint32_t TIMER;                             /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
+    __IO uint32_t CTRL;                              /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
+    __IO uint32_t STAT;                              /**< MRT Status register., array offset: 0xC, array step: 0x10 */
+  } CHANNEL[4];
+       uint8_t RESERVED_0[176];
+  __IO uint32_t MODCFG;                            /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
+  __I  uint32_t IDLE_CH;                           /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
+  __IO uint32_t IRQ_FLAG;                          /**< Global interrupt flag register, offset: 0xF8 */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MRT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
+#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
+#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT                 (4U)
+
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
+#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
+#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT                  (4U)
+
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
+#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
+#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
+#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT                   (4U)
+
+/*! @name CHANNEL_STAT - MRT Status register. */
+#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
+#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
+#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
+#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT                   (4U)
+
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
+#define MRT_MODCFG_NOC_MASK                      (0xFU)
+#define MRT_MODCFG_NOC_SHIFT                     (0U)
+#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT                     (4U)
+#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
+#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
+#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
+#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+
+/*! @name IRQ_FLAG - Global interrupt flag register */
+#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
+#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
+#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
+#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
+#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+/** Peripheral MRT0 base address */
+#define MRT0_BASE                                (0x4000D000u)
+/** Peripheral MRT0 base pointer */
+#define MRT0                                     ((MRT_Type *)MRT0_BASE)
+/** Array initializer of MRT peripheral base addresses */
+#define MRT_BASE_ADDRS                           { MRT0_BASE }
+/** Array initializer of MRT peripheral base pointers */
+#define MRT_BASE_PTRS                            { MRT0 }
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS                                 { MRT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OTPC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
+ * @{
+ */
+
+/** OTPC - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __I  uint32_t AESKEY[8];                         /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
+  __I  uint32_t ECRP;                              /**< ECRP options., offset: 0x30 */
+       uint8_t RESERVED_1[4];
+  __I  uint32_t USER0;                             /**< User application specific options., offset: 0x38 */
+  __I  uint32_t USER1;                             /**< User application specific options., offset: 0x3C */
+} OTPC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OTPC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Register_Masks OTPC Register Masks
+ * @{
+ */
+
+/*! @name AESKEY - Register for reading the AES key. */
+#define OTPC_AESKEY_KEY_MASK                     (0xFFFFFFFFU)
+#define OTPC_AESKEY_KEY_SHIFT                    (0U)
+#define OTPC_AESKEY_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
+
+/* The count of OTPC_AESKEY */
+#define OTPC_AESKEY_COUNT                        (8U)
+
+/*! @name ECRP - ECRP options. */
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK    (0x10U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT   (4U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK     (0x20U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT    (5U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK       (0x40U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT      (6U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK       (0x80U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT      (7U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x)         (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK            (0x200U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT           (9U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO(x)              (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
+#define OTPC_ECRP_JTAG_DISABLE_MASK              (0x80000000U)
+#define OTPC_ECRP_JTAG_DISABLE_SHIFT             (31U)
+#define OTPC_ECRP_JTAG_DISABLE(x)                (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
+
+/*! @name USER0 - User application specific options. */
+#define OTPC_USER0_USER0_MASK                    (0xFFFFFFFFU)
+#define OTPC_USER0_USER0_SHIFT                   (0U)
+#define OTPC_USER0_USER0(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
+
+/*! @name USER1 - User application specific options. */
+#define OTPC_USER1_USER1_MASK                    (0xFFFFFFFFU)
+#define OTPC_USER1_USER1_SHIFT                   (0U)
+#define OTPC_USER1_USER1(x)                      (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OTPC_Register_Masks */
+
+
+/* OTPC - Peripheral instance base addresses */
+/** Peripheral OTPC base address */
+#define OTPC_BASE                                (0x40015000u)
+/** Peripheral OTPC base pointer */
+#define OTPC                                     ((OTPC_Type *)OTPC_BASE)
+/** Array initializer of OTPC peripheral base addresses */
+#define OTPC_BASE_ADDRS                          { OTPC_BASE }
+/** Array initializer of OTPC peripheral base pointers */
+#define OTPC_BASE_PTRS                           { OTPC }
+
+/*!
+ * @}
+ */ /* end of group OTPC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PINT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode register, offset: 0x0 */
+  __IO uint32_t IENR;                              /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
+  __O  uint32_t SIENR;                             /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
+  __O  uint32_t CIENR;                             /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
+  __IO uint32_t IENF;                              /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
+  __O  uint32_t SIENF;                             /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
+  __O  uint32_t CIENF;                             /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
+  __IO uint32_t RISE;                              /**< Pin interrupt rising edge register, offset: 0x1C */
+  __IO uint32_t FALL;                              /**< Pin interrupt falling edge register, offset: 0x20 */
+  __IO uint32_t IST;                               /**< Pin interrupt status register, offset: 0x24 */
+  __IO uint32_t PMCTRL;                            /**< Pattern match interrupt control register, offset: 0x28 */
+  __IO uint32_t PMSRC;                             /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
+  __IO uint32_t PMCFG;                             /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PINT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode register */
+#define PINT_ISEL_PMODE_MASK                     (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT                    (0U)
+#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
+#define PINT_IENR_ENRL_MASK                      (0xFFU)
+#define PINT_IENR_ENRL_SHIFT                     (0U)
+#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
+#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT                 (0U)
+#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
+#define PINT_CIENR_CENRL_MASK                    (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT                   (0U)
+#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
+#define PINT_IENF_ENAF_MASK                      (0xFFU)
+#define PINT_IENF_ENAF_SHIFT                     (0U)
+#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
+#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT                 (0U)
+#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
+#define PINT_CIENF_CENAF_MASK                    (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT                   (0U)
+#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+
+/*! @name RISE - Pin interrupt rising edge register */
+#define PINT_RISE_RDET_MASK                      (0xFFU)
+#define PINT_RISE_RDET_SHIFT                     (0U)
+#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+
+/*! @name FALL - Pin interrupt falling edge register */
+#define PINT_FALL_FDET_MASK                      (0xFFU)
+#define PINT_FALL_FDET_SHIFT                     (0U)
+#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+
+/*! @name IST - Pin interrupt status register */
+#define PINT_IST_PSTAT_MASK                      (0xFFU)
+#define PINT_IST_PSTAT_SHIFT                     (0U)
+#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+
+/*! @name PMCTRL - Pattern match interrupt control register */
+#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
+#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
+#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
+#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */
+#define PINT_PMSRC_SRC0_MASK                     (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT                    (8U)
+#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT                    (11U)
+#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT                    (14U)
+#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT                    (17U)
+#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT                    (20U)
+#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT                    (23U)
+#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT                    (26U)
+#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT                    (29U)
+#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
+#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
+#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
+#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
+#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
+#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
+#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
+#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
+#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+#define PINT_PMCFG_CFG0_MASK                     (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT                    (8U)
+#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT                    (11U)
+#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT                    (14U)
+#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT                    (17U)
+#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT                    (20U)
+#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT                    (23U)
+#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT                    (26U)
+#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT                    (29U)
+#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+/** Peripheral PINT base address */
+#define PINT_BASE                                (0x40004000u)
+/** Peripheral PINT base pointer */
+#define PINT                                     ((PINT_Type *)PINT_BASE)
+/** Array initializer of PINT peripheral base addresses */
+#define PINT_BASE_ADDRS                          { PINT_BASE }
+/** Array initializer of PINT peripheral base pointers */
+#define PINT_BASE_PTRS                           { PINT }
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
+ * @{
+ */
+
+/** RIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t COMPVAL;                           /**< Compare value LSB register, offset: 0x0 */
+  __IO uint32_t MASK;                              /**< Mask LSB register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x8 */
+  __IO uint32_t COUNTER;                           /**< Counter LSB register, offset: 0xC */
+  __IO uint32_t COMPVAL_H;                         /**< Compare value MSB register, offset: 0x10 */
+  __IO uint32_t MASK_H;                            /**< Mask MSB register, offset: 0x14 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t COUNTER_H;                         /**< Counter MSB register, offset: 0x1C */
+} RIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Register_Masks RIT Register Masks
+ * @{
+ */
+
+/*! @name COMPVAL - Compare value LSB register */
+#define RIT_COMPVAL_RICOMP_MASK                  (0xFFFFFFFFU)
+#define RIT_COMPVAL_RICOMP_SHIFT                 (0U)
+#define RIT_COMPVAL_RICOMP(x)                    (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
+
+/*! @name MASK - Mask LSB register */
+#define RIT_MASK_RIMASK_MASK                     (0xFFFFFFFFU)
+#define RIT_MASK_RIMASK_SHIFT                    (0U)
+#define RIT_MASK_RIMASK(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
+
+/*! @name CTRL - Control register */
+#define RIT_CTRL_RITINT_MASK                     (0x1U)
+#define RIT_CTRL_RITINT_SHIFT                    (0U)
+#define RIT_CTRL_RITINT(x)                       (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
+#define RIT_CTRL_RITENCLR_MASK                   (0x2U)
+#define RIT_CTRL_RITENCLR_SHIFT                  (1U)
+#define RIT_CTRL_RITENCLR(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
+#define RIT_CTRL_RITENBR_MASK                    (0x4U)
+#define RIT_CTRL_RITENBR_SHIFT                   (2U)
+#define RIT_CTRL_RITENBR(x)                      (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
+#define RIT_CTRL_RITEN_MASK                      (0x8U)
+#define RIT_CTRL_RITEN_SHIFT                     (3U)
+#define RIT_CTRL_RITEN(x)                        (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
+
+/*! @name COUNTER - Counter LSB register */
+#define RIT_COUNTER_RICOUNTER_MASK               (0xFFFFFFFFU)
+#define RIT_COUNTER_RICOUNTER_SHIFT              (0U)
+#define RIT_COUNTER_RICOUNTER(x)                 (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
+
+/*! @name COMPVAL_H - Compare value MSB register */
+#define RIT_COMPVAL_H_RICOMP_MASK                (0xFFFFU)
+#define RIT_COMPVAL_H_RICOMP_SHIFT               (0U)
+#define RIT_COMPVAL_H_RICOMP(x)                  (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
+
+/*! @name MASK_H - Mask MSB register */
+#define RIT_MASK_H_RIMASK_MASK                   (0xFFFFU)
+#define RIT_MASK_H_RIMASK_SHIFT                  (0U)
+#define RIT_MASK_H_RIMASK(x)                     (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
+
+/*! @name COUNTER_H - Counter MSB register */
+#define RIT_COUNTER_H_RICOUNTER_MASK             (0xFFFFU)
+#define RIT_COUNTER_H_RICOUNTER_SHIFT            (0U)
+#define RIT_COUNTER_H_RICOUNTER(x)               (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RIT_Register_Masks */
+
+
+/* RIT - Peripheral instance base addresses */
+/** Peripheral RIT base address */
+#define RIT_BASE                                 (0x4002D000u)
+/** Peripheral RIT base pointer */
+#define RIT                                      ((RIT_Type *)RIT_BASE)
+/** Array initializer of RIT peripheral base addresses */
+#define RIT_BASE_ADDRS                           { RIT_BASE }
+/** Array initializer of RIT peripheral base pointers */
+#define RIT_BASE_PTRS                            { RIT }
+/** Interrupt vectors for the RIT peripheral type */
+#define RIT_IRQS                                 { RIT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< RTC control register, offset: 0x0 */
+  __IO uint32_t MATCH;                             /**< RTC match register, offset: 0x4 */
+  __IO uint32_t COUNT;                             /**< RTC counter register, offset: 0x8 */
+  __IO uint32_t WAKE;                              /**< High-resolution/wake-up timer control register, offset: 0xC */
+       uint8_t RESERVED_0[48];
+  __IO uint32_t GPREG[8];                          /**< General Purpose register, array offset: 0x40, array step: 0x4 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC control register */
+#define RTC_CTRL_SWRESET_MASK                    (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT                   (0U)
+#define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+#define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
+#define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+#define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
+#define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+#define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
+#define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+#define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
+#define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+#define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
+#define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+#define RTC_CTRL_RTC_EN_MASK                     (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT                    (7U)
+#define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+#define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
+#define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+
+/*! @name MATCH - RTC match register */
+#define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT                   (0U)
+#define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+
+/*! @name COUNT - RTC counter register */
+#define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT                      (0U)
+#define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+
+/*! @name WAKE - High-resolution/wake-up timer control register */
+#define RTC_WAKE_VAL_MASK                        (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT                       (0U)
+#define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+
+/*! @name GPREG - General Purpose register */
+#define RTC_GPREG_GPDATA_MASK                    (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT                   (0U)
+#define RTC_GPREG_GPDATA(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+
+/* The count of RTC_GPREG */
+#define RTC_GPREG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4002C000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SCT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONFIG;                            /**< SCT configuration register, offset: 0x0 */
+  __IO uint32_t CTRL;                              /**< SCT control register, offset: 0x4 */
+  __IO uint32_t LIMIT;                             /**< SCT limit event select register, offset: 0x8 */
+  __IO uint32_t HALT;                              /**< SCT halt event select register, offset: 0xC */
+  __IO uint32_t STOP;                              /**< SCT stop event select register, offset: 0x10 */
+  __IO uint32_t START;                             /**< SCT start event select register, offset: 0x14 */
+       uint8_t RESERVED_0[40];
+  __IO uint32_t COUNT;                             /**< SCT counter register, offset: 0x40 */
+  __IO uint32_t STATE;                             /**< SCT state register, offset: 0x44 */
+  __I  uint32_t INPUT;                             /**< SCT input register, offset: 0x48 */
+  __IO uint32_t REGMODE;                           /**< SCT match/capture mode register, offset: 0x4C */
+  __IO uint32_t OUTPUT;                            /**< SCT output register, offset: 0x50 */
+  __IO uint32_t OUTPUTDIRCTRL;                     /**< SCT output counter direction control register, offset: 0x54 */
+  __IO uint32_t RES;                               /**< SCT conflict resolution register, offset: 0x58 */
+  __IO uint32_t DMA0REQUEST;                       /**< SCT DMA request 0 register, offset: 0x5C */
+  __IO uint32_t DMA1REQUEST;                       /**< SCT DMA request 1 register, offset: 0x60 */
+       uint8_t RESERVED_1[140];
+  __IO uint32_t EVEN;                              /**< SCT event interrupt enable register, offset: 0xF0 */
+  __IO uint32_t EVFLAG;                            /**< SCT event flag register, offset: 0xF4 */
+  __IO uint32_t CONEN;                             /**< SCT conflict interrupt enable register, offset: 0xF8 */
+  __IO uint32_t CONFLAG;                           /**< SCT conflict flag register, offset: 0xFC */
+  union {                                          /* offset: 0x100 */
+    __IO uint32_t SCTCAP[10];                        /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
+    __IO uint32_t SCTMATCH[10];                      /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
+  };
+       uint8_t RESERVED_2[216];
+  union {                                          /* offset: 0x200 */
+    __IO uint32_t SCTCAPCTRL[10];                    /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
+    __IO uint32_t SCTMATCHREL[10];                   /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+  };
+       uint8_t RESERVED_3[216];
+  struct {                                         /* offset: 0x300, array step: 0x8 */
+    __IO uint32_t STATE;                             /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
+    __IO uint32_t CTRL;                              /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
+  } EVENT[10];
+       uint8_t RESERVED_4[432];
+  struct {                                         /* offset: 0x500, array step: 0x8 */
+    __IO uint32_t SET;                               /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
+    __IO uint32_t CLR;                               /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
+  } OUT[10];
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SCT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCT configuration register */
+#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
+#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
+#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
+#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+#define SCT_CONFIG_NORELAOD_L_MASK               (0x80U)
+#define SCT_CONFIG_NORELAOD_L_SHIFT              (7U)
+#define SCT_CONFIG_NORELAOD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
+#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
+#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+#define SCT_CONFIG_INSYNC_MASK                   (0x1E00U)
+#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
+#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
+#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
+#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+
+/*! @name CTRL - SCT control register */
+#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
+#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+#define SCT_CTRL_STOP_L_MASK                     (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT                    (1U)
+#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+#define SCT_CTRL_HALT_L_MASK                     (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT                    (2U)
+#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
+#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
+#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT                     (5U)
+#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
+#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT                    (17U)
+#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT                    (18U)
+#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
+#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
+#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT                     (21U)
+#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+
+/*! @name LIMIT - SCT limit event select register */
+#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
+#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
+#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+
+/*! @name HALT - SCT halt event select register */
+#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
+#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
+#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+
+/*! @name STOP - SCT stop event select register */
+#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
+#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
+#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+
+/*! @name START - SCT start event select register */
+#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT               (0U)
+#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT               (16U)
+#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+
+/*! @name COUNT - SCT counter register */
+#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT                    (0U)
+#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT                    (16U)
+#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+
+/*! @name STATE - SCT state register */
+#define SCT_STATE_STATE_L_MASK                   (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT                  (0U)
+#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT                  (16U)
+#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+
+/*! @name INPUT - SCT input register */
+#define SCT_INPUT_AIN0_MASK                      (0x1U)
+#define SCT_INPUT_AIN0_SHIFT                     (0U)
+#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+#define SCT_INPUT_AIN1_MASK                      (0x2U)
+#define SCT_INPUT_AIN1_SHIFT                     (1U)
+#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+#define SCT_INPUT_AIN2_MASK                      (0x4U)
+#define SCT_INPUT_AIN2_SHIFT                     (2U)
+#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+#define SCT_INPUT_AIN3_MASK                      (0x8U)
+#define SCT_INPUT_AIN3_SHIFT                     (3U)
+#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+#define SCT_INPUT_AIN4_MASK                      (0x10U)
+#define SCT_INPUT_AIN4_SHIFT                     (4U)
+#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+#define SCT_INPUT_AIN5_MASK                      (0x20U)
+#define SCT_INPUT_AIN5_SHIFT                     (5U)
+#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+#define SCT_INPUT_AIN6_MASK                      (0x40U)
+#define SCT_INPUT_AIN6_SHIFT                     (6U)
+#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+#define SCT_INPUT_AIN7_MASK                      (0x80U)
+#define SCT_INPUT_AIN7_SHIFT                     (7U)
+#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+#define SCT_INPUT_AIN8_MASK                      (0x100U)
+#define SCT_INPUT_AIN8_SHIFT                     (8U)
+#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+#define SCT_INPUT_AIN9_MASK                      (0x200U)
+#define SCT_INPUT_AIN9_SHIFT                     (9U)
+#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+#define SCT_INPUT_AIN10_MASK                     (0x400U)
+#define SCT_INPUT_AIN10_SHIFT                    (10U)
+#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+#define SCT_INPUT_AIN11_MASK                     (0x800U)
+#define SCT_INPUT_AIN11_SHIFT                    (11U)
+#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+#define SCT_INPUT_AIN12_MASK                     (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT                    (12U)
+#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+#define SCT_INPUT_AIN13_MASK                     (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT                    (13U)
+#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+#define SCT_INPUT_AIN14_MASK                     (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT                    (14U)
+#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+#define SCT_INPUT_AIN15_MASK                     (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT                    (15U)
+#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+#define SCT_INPUT_SIN0_MASK                      (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT                     (16U)
+#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+#define SCT_INPUT_SIN1_MASK                      (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT                     (17U)
+#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+#define SCT_INPUT_SIN2_MASK                      (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT                     (18U)
+#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+#define SCT_INPUT_SIN3_MASK                      (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT                     (19U)
+#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+#define SCT_INPUT_SIN4_MASK                      (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT                     (20U)
+#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+#define SCT_INPUT_SIN5_MASK                      (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT                     (21U)
+#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+#define SCT_INPUT_SIN6_MASK                      (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT                     (22U)
+#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+#define SCT_INPUT_SIN7_MASK                      (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT                     (23U)
+#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT                     (24U)
+#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT                     (25U)
+#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT                    (26U)
+#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT                    (27U)
+#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT                    (28U)
+#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT                    (29U)
+#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT                    (30U)
+#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT                    (31U)
+#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+
+/*! @name REGMODE - SCT match/capture mode register */
+#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
+#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
+#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+
+/*! @name OUTPUT - SCT output register */
+#define SCT_OUTPUT_OUT_MASK                      (0xFFFFU)
+#define SCT_OUTPUT_OUT_SHIFT                     (0U)
+#define SCT_OUTPUT_OUT(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
+
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK          (0x300000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT         (20U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK          (0xC00000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT         (22U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK          (0x3000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT         (24U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK          (0xC000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT         (26U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK          (0x30000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT         (28U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK          (0xC0000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT         (30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x)            (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
+
+/*! @name RES - SCT conflict resolution register */
+#define SCT_RES_O0RES_MASK                       (0x3U)
+#define SCT_RES_O0RES_SHIFT                      (0U)
+#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+#define SCT_RES_O1RES_MASK                       (0xCU)
+#define SCT_RES_O1RES_SHIFT                      (2U)
+#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+#define SCT_RES_O2RES_MASK                       (0x30U)
+#define SCT_RES_O2RES_SHIFT                      (4U)
+#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+#define SCT_RES_O3RES_MASK                       (0xC0U)
+#define SCT_RES_O3RES_SHIFT                      (6U)
+#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+#define SCT_RES_O4RES_MASK                       (0x300U)
+#define SCT_RES_O4RES_SHIFT                      (8U)
+#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+#define SCT_RES_O5RES_MASK                       (0xC00U)
+#define SCT_RES_O5RES_SHIFT                      (10U)
+#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+#define SCT_RES_O6RES_MASK                       (0x3000U)
+#define SCT_RES_O6RES_SHIFT                      (12U)
+#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+#define SCT_RES_O7RES_MASK                       (0xC000U)
+#define SCT_RES_O7RES_SHIFT                      (14U)
+#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+#define SCT_RES_O8RES_MASK                       (0x30000U)
+#define SCT_RES_O8RES_SHIFT                      (16U)
+#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+#define SCT_RES_O9RES_MASK                       (0xC0000U)
+#define SCT_RES_O9RES_SHIFT                      (18U)
+#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+#define SCT_RES_O10RES_MASK                      (0x300000U)
+#define SCT_RES_O10RES_SHIFT                     (20U)
+#define SCT_RES_O10RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
+#define SCT_RES_O11RES_MASK                      (0xC00000U)
+#define SCT_RES_O11RES_SHIFT                     (22U)
+#define SCT_RES_O11RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
+#define SCT_RES_O12RES_MASK                      (0x3000000U)
+#define SCT_RES_O12RES_SHIFT                     (24U)
+#define SCT_RES_O12RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
+#define SCT_RES_O13RES_MASK                      (0xC000000U)
+#define SCT_RES_O13RES_SHIFT                     (26U)
+#define SCT_RES_O13RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
+#define SCT_RES_O14RES_MASK                      (0x30000000U)
+#define SCT_RES_O14RES_SHIFT                     (28U)
+#define SCT_RES_O14RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
+#define SCT_RES_O15RES_MASK                      (0xC0000000U)
+#define SCT_RES_O15RES_SHIFT                     (30U)
+#define SCT_RES_O15RES(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
+
+/*! @name DMA0REQUEST - SCT DMA request 0 register */
+#define SCT_DMA0REQUEST_DEV_0_MASK               (0xFFFFU)
+#define SCT_DMA0REQUEST_DEV_0_SHIFT              (0U)
+#define SCT_DMA0REQUEST_DEV_0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
+#define SCT_DMA0REQUEST_DRL0_MASK                (0x40000000U)
+#define SCT_DMA0REQUEST_DRL0_SHIFT               (30U)
+#define SCT_DMA0REQUEST_DRL0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
+#define SCT_DMA0REQUEST_DRQ0_MASK                (0x80000000U)
+#define SCT_DMA0REQUEST_DRQ0_SHIFT               (31U)
+#define SCT_DMA0REQUEST_DRQ0(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
+
+/*! @name DMA1REQUEST - SCT DMA request 1 register */
+#define SCT_DMA1REQUEST_DEV_1_MASK               (0xFFFFU)
+#define SCT_DMA1REQUEST_DEV_1_SHIFT              (0U)
+#define SCT_DMA1REQUEST_DEV_1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
+#define SCT_DMA1REQUEST_DRL1_MASK                (0x40000000U)
+#define SCT_DMA1REQUEST_DRL1_SHIFT               (30U)
+#define SCT_DMA1REQUEST_DRL1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
+#define SCT_DMA1REQUEST_DRQ1_MASK                (0x80000000U)
+#define SCT_DMA1REQUEST_DRQ1_SHIFT               (31U)
+#define SCT_DMA1REQUEST_DRQ1(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
+
+/*! @name EVEN - SCT event interrupt enable register */
+#define SCT_EVEN_IEN_MASK                        (0xFFFFU)
+#define SCT_EVEN_IEN_SHIFT                       (0U)
+#define SCT_EVEN_IEN(x)                          (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
+
+/*! @name EVFLAG - SCT event flag register */
+#define SCT_EVFLAG_FLAG_MASK                     (0xFFFFU)
+#define SCT_EVFLAG_FLAG_SHIFT                    (0U)
+#define SCT_EVFLAG_FLAG(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
+
+/*! @name CONEN - SCT conflict interrupt enable register */
+#define SCT_CONEN_NCEN_MASK                      (0xFFFFU)
+#define SCT_CONEN_NCEN_SHIFT                     (0U)
+#define SCT_CONEN_NCEN(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
+
+/*! @name CONFLAG - SCT conflict flag register */
+#define SCT_CONFLAG_NCFLAG_MASK                  (0xFFFFU)
+#define SCT_CONFLAG_NCFLAG_SHIFT                 (0U)
+#define SCT_CONFLAG_NCFLAG(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
+#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
+#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
+#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+
+/*! @name SCTCAP - SCT capture register of capture channel */
+#define SCT_SCTCAP_CAPn_L_MASK                   (0xFFFFU)
+#define SCT_SCTCAP_CAPn_L_SHIFT                  (0U)
+#define SCT_SCTCAP_CAPn_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
+#define SCT_SCTCAP_CAPn_H_MASK                   (0xFFFF0000U)
+#define SCT_SCTCAP_CAPn_H_SHIFT                  (16U)
+#define SCT_SCTCAP_CAPn_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
+
+/* The count of SCT_SCTCAP */
+#define SCT_SCTCAP_COUNT                         (10U)
+
+/*! @name SCTMATCH - SCT match value register of match channels */
+#define SCT_SCTMATCH_MATCHn_L_MASK               (0xFFFFU)
+#define SCT_SCTMATCH_MATCHn_L_SHIFT              (0U)
+#define SCT_SCTMATCH_MATCHn_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
+#define SCT_SCTMATCH_MATCHn_H_MASK               (0xFFFF0000U)
+#define SCT_SCTMATCH_MATCHn_H_SHIFT              (16U)
+#define SCT_SCTMATCH_MATCHn_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
+
+/* The count of SCT_SCTMATCH */
+#define SCT_SCTMATCH_COUNT                       (10U)
+
+/*! @name SCTCAPCTRL - SCT capture control register */
+#define SCT_SCTCAPCTRL_CAPCONn_L_MASK            (0xFFFFU)
+#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT           (0U)
+#define SCT_SCTCAPCTRL_CAPCONn_L(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
+#define SCT_SCTCAPCTRL_CAPCONn_H_MASK            (0xFFFF0000U)
+#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT           (16U)
+#define SCT_SCTCAPCTRL_CAPCONn_H(x)              (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
+
+/* The count of SCT_SCTCAPCTRL */
+#define SCT_SCTCAPCTRL_COUNT                     (10U)
+
+/*! @name SCTMATCHREL - SCT match reload value register */
+#define SCT_SCTMATCHREL_RELOADn_L_MASK           (0xFFFFU)
+#define SCT_SCTMATCHREL_RELOADn_L_SHIFT          (0U)
+#define SCT_SCTMATCHREL_RELOADn_L(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
+#define SCT_SCTMATCHREL_RELOADn_H_MASK           (0xFFFF0000U)
+#define SCT_SCTMATCHREL_RELOADn_H_SHIFT          (16U)
+#define SCT_SCTMATCHREL_RELOADn_H(x)             (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
+
+/* The count of SCT_SCTMATCHREL */
+#define SCT_SCTMATCHREL_COUNT                    (10U)
+
+/*! @name EVENT_STATE - SCT event state register 0 */
+#define SCT_EVENT_STATE_STATEMSKn_MASK           (0xFFFFU)
+#define SCT_EVENT_STATE_STATEMSKn_SHIFT          (0U)
+#define SCT_EVENT_STATE_STATEMSKn(x)             (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
+
+/* The count of SCT_EVENT_STATE */
+#define SCT_EVENT_STATE_COUNT                    (10U)
+
+/*! @name EVENT_CTRL - SCT event control register 0 */
+#define SCT_EVENT_CTRL_MATCHSEL_MASK             (0xFU)
+#define SCT_EVENT_CTRL_MATCHSEL_SHIFT            (0U)
+#define SCT_EVENT_CTRL_MATCHSEL(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
+#define SCT_EVENT_CTRL_HEVENT_MASK               (0x10U)
+#define SCT_EVENT_CTRL_HEVENT_SHIFT              (4U)
+#define SCT_EVENT_CTRL_HEVENT(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
+#define SCT_EVENT_CTRL_OUTSEL_MASK               (0x20U)
+#define SCT_EVENT_CTRL_OUTSEL_SHIFT              (5U)
+#define SCT_EVENT_CTRL_OUTSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
+#define SCT_EVENT_CTRL_IOSEL_MASK                (0x3C0U)
+#define SCT_EVENT_CTRL_IOSEL_SHIFT               (6U)
+#define SCT_EVENT_CTRL_IOSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
+#define SCT_EVENT_CTRL_IOCOND_MASK               (0xC00U)
+#define SCT_EVENT_CTRL_IOCOND_SHIFT              (10U)
+#define SCT_EVENT_CTRL_IOCOND(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
+#define SCT_EVENT_CTRL_COMBMODE_MASK             (0x3000U)
+#define SCT_EVENT_CTRL_COMBMODE_SHIFT            (12U)
+#define SCT_EVENT_CTRL_COMBMODE(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
+#define SCT_EVENT_CTRL_STATELD_MASK              (0x4000U)
+#define SCT_EVENT_CTRL_STATELD_SHIFT             (14U)
+#define SCT_EVENT_CTRL_STATELD(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
+#define SCT_EVENT_CTRL_STATEV_MASK               (0xF8000U)
+#define SCT_EVENT_CTRL_STATEV_SHIFT              (15U)
+#define SCT_EVENT_CTRL_STATEV(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
+#define SCT_EVENT_CTRL_MATCHMEM_MASK             (0x100000U)
+#define SCT_EVENT_CTRL_MATCHMEM_SHIFT            (20U)
+#define SCT_EVENT_CTRL_MATCHMEM(x)               (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
+#define SCT_EVENT_CTRL_DIRECTION_MASK            (0x600000U)
+#define SCT_EVENT_CTRL_DIRECTION_SHIFT           (21U)
+#define SCT_EVENT_CTRL_DIRECTION(x)              (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
+
+/* The count of SCT_EVENT_CTRL */
+#define SCT_EVENT_CTRL_COUNT                     (10U)
+
+/*! @name OUT_SET - SCT output 0 set register */
+#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT                    (0U)
+#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT                        (10U)
+
+/*! @name OUT_CLR - SCT output 0 clear register */
+#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
+#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT                        (10U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+/** Peripheral SCT0 base address */
+#define SCT0_BASE                                (0x40085000u)
+/** Peripheral SCT0 base pointer */
+#define SCT0                                     ((SCT_Type *)SCT0_BASE)
+/** Array initializer of SCT peripheral base addresses */
+#define SCT_BASE_ADDRS                           { SCT0_BASE }
+/** Array initializer of SCT peripheral base pointers */
+#define SCT_BASE_PTRS                            { SCT0 }
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS                                 { SCT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDIF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
+ * @{
+ */
+
+/** SDIF - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register, offset: 0x0 */
+  __IO uint32_t PWREN;                             /**< Power Enable register, offset: 0x4 */
+  __IO uint32_t CLKDIV;                            /**< Clock Divider register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLKENA;                            /**< Clock Enable register, offset: 0x10 */
+  __IO uint32_t TMOUT;                             /**< Time-out register, offset: 0x14 */
+  __IO uint32_t CTYPE;                             /**< Card Type register, offset: 0x18 */
+  __IO uint32_t BLKSIZ;                            /**< Block Size register, offset: 0x1C */
+  __IO uint32_t BYTCNT;                            /**< Byte Count register, offset: 0x20 */
+  __IO uint32_t INTMASK;                           /**< Interrupt Mask register, offset: 0x24 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x28 */
+  __IO uint32_t CMD;                               /**< Command register, offset: 0x2C */
+  __IO uint32_t RESP[4];                           /**< Response register, array offset: 0x30, array step: 0x4 */
+  __IO uint32_t MINTSTS;                           /**< Masked Interrupt Status register, offset: 0x40 */
+  __IO uint32_t RINTSTS;                           /**< Raw Interrupt Status register, offset: 0x44 */
+  __IO uint32_t STATUS;                            /**< Status register, offset: 0x48 */
+  __IO uint32_t FIFOTH;                            /**< FIFO Threshold Watermark register, offset: 0x4C */
+  __IO uint32_t CDETECT;                           /**< Card Detect register, offset: 0x50 */
+  __IO uint32_t WRTPRT;                            /**< Write Protect register, offset: 0x54 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t TCBCNT;                            /**< Transferred CIU Card Byte Count register, offset: 0x5C */
+  __IO uint32_t TBBCNT;                            /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
+  __IO uint32_t DEBNCE;                            /**< Debounce Count register, offset: 0x64 */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t RST_N;                             /**< Hardware Reset, offset: 0x78 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t BMOD;                              /**< Bus Mode register, offset: 0x80 */
+  __IO uint32_t PLDMND;                            /**< Poll Demand register, offset: 0x84 */
+  __IO uint32_t DBADDR;                            /**< Descriptor List Base Address register, offset: 0x88 */
+  __IO uint32_t IDSTS;                             /**< Internal DMAC Status register, offset: 0x8C */
+  __IO uint32_t IDINTEN;                           /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
+  __IO uint32_t DSCADDR;                           /**< Current Host Descriptor Address register, offset: 0x94 */
+  __IO uint32_t BUFADDR;                           /**< Current Buffer Descriptor Address register, offset: 0x98 */
+       uint8_t RESERVED_4[100];
+  __IO uint32_t CARDTHRCTL;                        /**< Card Threshold Control, offset: 0x100 */
+  __IO uint32_t BACKENDPWR;                        /**< Power control, offset: 0x104 */
+       uint8_t RESERVED_5[248];
+  __IO uint32_t FIFO[64];                          /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
+} SDIF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDIF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+#define SDIF_CTRL_CONTROLLER_RESET_MASK          (0x1U)
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT         (0U)
+#define SDIF_CTRL_CONTROLLER_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
+#define SDIF_CTRL_FIFO_RESET_MASK                (0x2U)
+#define SDIF_CTRL_FIFO_RESET_SHIFT               (1U)
+#define SDIF_CTRL_FIFO_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
+#define SDIF_CTRL_DMA_RESET_MASK                 (0x4U)
+#define SDIF_CTRL_DMA_RESET_SHIFT                (2U)
+#define SDIF_CTRL_DMA_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
+#define SDIF_CTRL_INT_ENABLE_MASK                (0x10U)
+#define SDIF_CTRL_INT_ENABLE_SHIFT               (4U)
+#define SDIF_CTRL_INT_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
+#define SDIF_CTRL_READ_WAIT_MASK                 (0x40U)
+#define SDIF_CTRL_READ_WAIT_SHIFT                (6U)
+#define SDIF_CTRL_READ_WAIT(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK         (0x80U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT        (7U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
+#define SDIF_CTRL_ABORT_READ_DATA_MASK           (0x100U)
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT          (8U)
+#define SDIF_CTRL_ABORT_READ_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
+#define SDIF_CTRL_SEND_CCSD_MASK                 (0x200U)
+#define SDIF_CTRL_SEND_CCSD_SHIFT                (9U)
+#define SDIF_CTRL_SEND_CCSD(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK       (0x400U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT      (10U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK           (0x10000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT          (16U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK           (0x20000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT          (17U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK           (0x40000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT          (18U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK         (0x2000000U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT        (25U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
+
+/*! @name PWREN - Power Enable register */
+#define SDIF_PWREN_POWER_ENABLE_MASK             (0x1U)
+#define SDIF_PWREN_POWER_ENABLE_SHIFT            (0U)
+#define SDIF_PWREN_POWER_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
+
+/*! @name CLKDIV - Clock Divider register */
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK            (0xFFU)
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT           (0U)
+#define SDIF_CLKDIV_CLK_DIVIDER0(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
+
+/*! @name CLKENA - Clock Enable register */
+#define SDIF_CLKENA_CCLK_ENABLE_MASK             (0x1U)
+#define SDIF_CLKENA_CCLK_ENABLE_SHIFT            (0U)
+#define SDIF_CLKENA_CCLK_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
+#define SDIF_CLKENA_CCLK_LOW_POWER_MASK          (0x10000U)
+#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT         (16U)
+#define SDIF_CLKENA_CCLK_LOW_POWER(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
+
+/*! @name TMOUT - Time-out register */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK         (0xFFU)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT        (0U)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK             (0xFFFFFF00U)
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT            (8U)
+#define SDIF_TMOUT_DATA_TIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
+
+/*! @name CTYPE - Card Type register */
+#define SDIF_CTYPE_CARD_WIDTH0_MASK              (0x1U)
+#define SDIF_CTYPE_CARD_WIDTH0_SHIFT             (0U)
+#define SDIF_CTYPE_CARD_WIDTH0(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
+#define SDIF_CTYPE_CARD_WIDTH1_MASK              (0x10000U)
+#define SDIF_CTYPE_CARD_WIDTH1_SHIFT             (16U)
+#define SDIF_CTYPE_CARD_WIDTH1(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
+
+/*! @name BLKSIZ - Block Size register */
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK              (0xFFFFU)
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT             (0U)
+#define SDIF_BLKSIZ_BLOCK_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
+
+/*! @name BYTCNT - Byte Count register */
+#define SDIF_BYTCNT_BYTE_COUNT_MASK              (0xFFFFFFFFU)
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT             (0U)
+#define SDIF_BYTCNT_BYTE_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
+
+/*! @name INTMASK - Interrupt Mask register */
+#define SDIF_INTMASK_CDET_MASK                   (0x1U)
+#define SDIF_INTMASK_CDET_SHIFT                  (0U)
+#define SDIF_INTMASK_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
+#define SDIF_INTMASK_RE_MASK                     (0x2U)
+#define SDIF_INTMASK_RE_SHIFT                    (1U)
+#define SDIF_INTMASK_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
+#define SDIF_INTMASK_CDONE_MASK                  (0x4U)
+#define SDIF_INTMASK_CDONE_SHIFT                 (2U)
+#define SDIF_INTMASK_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
+#define SDIF_INTMASK_DTO_MASK                    (0x8U)
+#define SDIF_INTMASK_DTO_SHIFT                   (3U)
+#define SDIF_INTMASK_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
+#define SDIF_INTMASK_TXDR_MASK                   (0x10U)
+#define SDIF_INTMASK_TXDR_SHIFT                  (4U)
+#define SDIF_INTMASK_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
+#define SDIF_INTMASK_RXDR_MASK                   (0x20U)
+#define SDIF_INTMASK_RXDR_SHIFT                  (5U)
+#define SDIF_INTMASK_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
+#define SDIF_INTMASK_RCRC_MASK                   (0x40U)
+#define SDIF_INTMASK_RCRC_SHIFT                  (6U)
+#define SDIF_INTMASK_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
+#define SDIF_INTMASK_DCRC_MASK                   (0x80U)
+#define SDIF_INTMASK_DCRC_SHIFT                  (7U)
+#define SDIF_INTMASK_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
+#define SDIF_INTMASK_RTO_MASK                    (0x100U)
+#define SDIF_INTMASK_RTO_SHIFT                   (8U)
+#define SDIF_INTMASK_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
+#define SDIF_INTMASK_DRTO_MASK                   (0x200U)
+#define SDIF_INTMASK_DRTO_SHIFT                  (9U)
+#define SDIF_INTMASK_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
+#define SDIF_INTMASK_HTO_MASK                    (0x400U)
+#define SDIF_INTMASK_HTO_SHIFT                   (10U)
+#define SDIF_INTMASK_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
+#define SDIF_INTMASK_FRUN_MASK                   (0x800U)
+#define SDIF_INTMASK_FRUN_SHIFT                  (11U)
+#define SDIF_INTMASK_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
+#define SDIF_INTMASK_HLE_MASK                    (0x1000U)
+#define SDIF_INTMASK_HLE_SHIFT                   (12U)
+#define SDIF_INTMASK_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
+#define SDIF_INTMASK_SBE_MASK                    (0x2000U)
+#define SDIF_INTMASK_SBE_SHIFT                   (13U)
+#define SDIF_INTMASK_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
+#define SDIF_INTMASK_ACD_MASK                    (0x4000U)
+#define SDIF_INTMASK_ACD_SHIFT                   (14U)
+#define SDIF_INTMASK_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
+#define SDIF_INTMASK_EBE_MASK                    (0x8000U)
+#define SDIF_INTMASK_EBE_SHIFT                   (15U)
+#define SDIF_INTMASK_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK          (0x10000U)
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT         (16U)
+#define SDIF_INTMASK_SDIO_INT_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
+
+/*! @name CMDARG - Command Argument register */
+#define SDIF_CMDARG_CMD_ARG_MASK                 (0xFFFFFFFFU)
+#define SDIF_CMDARG_CMD_ARG_SHIFT                (0U)
+#define SDIF_CMDARG_CMD_ARG(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
+
+/*! @name CMD - Command register */
+#define SDIF_CMD_CMD_INDEX_MASK                  (0x3FU)
+#define SDIF_CMD_CMD_INDEX_SHIFT                 (0U)
+#define SDIF_CMD_CMD_INDEX(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
+#define SDIF_CMD_RESPONSE_EXPECT_MASK            (0x40U)
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT           (6U)
+#define SDIF_CMD_RESPONSE_EXPECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
+#define SDIF_CMD_RESPONSE_LENGTH_MASK            (0x80U)
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT           (7U)
+#define SDIF_CMD_RESPONSE_LENGTH(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK         (0x100U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT        (8U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
+#define SDIF_CMD_DATA_EXPECTED_MASK              (0x200U)
+#define SDIF_CMD_DATA_EXPECTED_SHIFT             (9U)
+#define SDIF_CMD_DATA_EXPECTED(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
+#define SDIF_CMD_READ_WRITE_MASK                 (0x400U)
+#define SDIF_CMD_READ_WRITE_SHIFT                (10U)
+#define SDIF_CMD_READ_WRITE(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
+#define SDIF_CMD_TRANSFER_MODE_MASK              (0x800U)
+#define SDIF_CMD_TRANSFER_MODE_SHIFT             (11U)
+#define SDIF_CMD_TRANSFER_MODE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
+#define SDIF_CMD_SEND_AUTO_STOP_MASK             (0x1000U)
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT            (12U)
+#define SDIF_CMD_SEND_AUTO_STOP(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK      (0x2000U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT     (13U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
+#define SDIF_CMD_STOP_ABORT_CMD_MASK             (0x4000U)
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT            (14U)
+#define SDIF_CMD_STOP_ABORT_CMD(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
+#define SDIF_CMD_SEND_INITIALIZATION_MASK        (0x8000U)
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT       (15U)
+#define SDIF_CMD_SEND_INITIALIZATION(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK          (0x400000U)
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT         (22U)
+#define SDIF_CMD_READ_CEATA_DEVICE(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
+#define SDIF_CMD_CCS_EXPECTED_MASK               (0x800000U)
+#define SDIF_CMD_CCS_EXPECTED_SHIFT              (23U)
+#define SDIF_CMD_CCS_EXPECTED(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
+#define SDIF_CMD_ENABLE_BOOT_MASK                (0x1000000U)
+#define SDIF_CMD_ENABLE_BOOT_SHIFT               (24U)
+#define SDIF_CMD_ENABLE_BOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK            (0x2000000U)
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT           (25U)
+#define SDIF_CMD_EXPECT_BOOT_ACK(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
+#define SDIF_CMD_DISABLE_BOOT_MASK               (0x4000000U)
+#define SDIF_CMD_DISABLE_BOOT_SHIFT              (26U)
+#define SDIF_CMD_DISABLE_BOOT(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
+#define SDIF_CMD_BOOT_MODE_MASK                  (0x8000000U)
+#define SDIF_CMD_BOOT_MODE_SHIFT                 (27U)
+#define SDIF_CMD_BOOT_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
+#define SDIF_CMD_VOLT_SWITCH_MASK                (0x10000000U)
+#define SDIF_CMD_VOLT_SWITCH_SHIFT               (28U)
+#define SDIF_CMD_VOLT_SWITCH(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
+#define SDIF_CMD_USE_HOLD_REG_MASK               (0x20000000U)
+#define SDIF_CMD_USE_HOLD_REG_SHIFT              (29U)
+#define SDIF_CMD_USE_HOLD_REG(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
+#define SDIF_CMD_START_CMD_MASK                  (0x80000000U)
+#define SDIF_CMD_START_CMD_SHIFT                 (31U)
+#define SDIF_CMD_START_CMD(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
+
+/*! @name RESP - Response register */
+#define SDIF_RESP_RESPONSE_MASK                  (0xFFFFFFFFU)
+#define SDIF_RESP_RESPONSE_SHIFT                 (0U)
+#define SDIF_RESP_RESPONSE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
+
+/* The count of SDIF_RESP */
+#define SDIF_RESP_COUNT                          (4U)
+
+/*! @name MINTSTS - Masked Interrupt Status register */
+#define SDIF_MINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_MINTSTS_CDET_SHIFT                  (0U)
+#define SDIF_MINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
+#define SDIF_MINTSTS_RE_MASK                     (0x2U)
+#define SDIF_MINTSTS_RE_SHIFT                    (1U)
+#define SDIF_MINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
+#define SDIF_MINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_MINTSTS_CDONE_SHIFT                 (2U)
+#define SDIF_MINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
+#define SDIF_MINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_MINTSTS_DTO_SHIFT                   (3U)
+#define SDIF_MINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
+#define SDIF_MINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_MINTSTS_TXDR_SHIFT                  (4U)
+#define SDIF_MINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
+#define SDIF_MINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_MINTSTS_RXDR_SHIFT                  (5U)
+#define SDIF_MINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
+#define SDIF_MINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_MINTSTS_RCRC_SHIFT                  (6U)
+#define SDIF_MINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
+#define SDIF_MINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_MINTSTS_DCRC_SHIFT                  (7U)
+#define SDIF_MINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
+#define SDIF_MINTSTS_RTO_MASK                    (0x100U)
+#define SDIF_MINTSTS_RTO_SHIFT                   (8U)
+#define SDIF_MINTSTS_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
+#define SDIF_MINTSTS_DRTO_MASK                   (0x200U)
+#define SDIF_MINTSTS_DRTO_SHIFT                  (9U)
+#define SDIF_MINTSTS_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
+#define SDIF_MINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_MINTSTS_HTO_SHIFT                   (10U)
+#define SDIF_MINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
+#define SDIF_MINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_MINTSTS_FRUN_SHIFT                  (11U)
+#define SDIF_MINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
+#define SDIF_MINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_MINTSTS_HLE_SHIFT                   (12U)
+#define SDIF_MINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
+#define SDIF_MINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_MINTSTS_SBE_SHIFT                   (13U)
+#define SDIF_MINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
+#define SDIF_MINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_MINTSTS_ACD_SHIFT                   (14U)
+#define SDIF_MINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
+#define SDIF_MINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_MINTSTS_EBE_SHIFT                   (15U)
+#define SDIF_MINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
+
+/*! @name RINTSTS - Raw Interrupt Status register */
+#define SDIF_RINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_RINTSTS_CDET_SHIFT                  (0U)
+#define SDIF_RINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
+#define SDIF_RINTSTS_RE_MASK                     (0x2U)
+#define SDIF_RINTSTS_RE_SHIFT                    (1U)
+#define SDIF_RINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
+#define SDIF_RINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_RINTSTS_CDONE_SHIFT                 (2U)
+#define SDIF_RINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
+#define SDIF_RINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_RINTSTS_DTO_SHIFT                   (3U)
+#define SDIF_RINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
+#define SDIF_RINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_RINTSTS_TXDR_SHIFT                  (4U)
+#define SDIF_RINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
+#define SDIF_RINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_RINTSTS_RXDR_SHIFT                  (5U)
+#define SDIF_RINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
+#define SDIF_RINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_RINTSTS_RCRC_SHIFT                  (6U)
+#define SDIF_RINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
+#define SDIF_RINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_RINTSTS_DCRC_SHIFT                  (7U)
+#define SDIF_RINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
+#define SDIF_RINTSTS_RTO_BAR_MASK                (0x100U)
+#define SDIF_RINTSTS_RTO_BAR_SHIFT               (8U)
+#define SDIF_RINTSTS_RTO_BAR(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
+#define SDIF_RINTSTS_DRTO_BDS_MASK               (0x200U)
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT              (9U)
+#define SDIF_RINTSTS_DRTO_BDS(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
+#define SDIF_RINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_RINTSTS_HTO_SHIFT                   (10U)
+#define SDIF_RINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
+#define SDIF_RINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_RINTSTS_FRUN_SHIFT                  (11U)
+#define SDIF_RINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
+#define SDIF_RINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_RINTSTS_HLE_SHIFT                   (12U)
+#define SDIF_RINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
+#define SDIF_RINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_RINTSTS_SBE_SHIFT                   (13U)
+#define SDIF_RINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
+#define SDIF_RINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_RINTSTS_ACD_SHIFT                   (14U)
+#define SDIF_RINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
+#define SDIF_RINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_RINTSTS_EBE_SHIFT                   (15U)
+#define SDIF_RINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
+
+/*! @name STATUS - Status register */
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK       (0x1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT      (0U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK       (0x2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT      (1U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_EMPTY_MASK              (0x4U)
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT             (2U)
+#define SDIF_STATUS_FIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
+#define SDIF_STATUS_FIFO_FULL_MASK               (0x8U)
+#define SDIF_STATUS_FIFO_FULL_SHIFT              (3U)
+#define SDIF_STATUS_FIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
+#define SDIF_STATUS_CMDFSMSTATES_MASK            (0xF0U)
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT           (4U)
+#define SDIF_STATUS_CMDFSMSTATES(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
+#define SDIF_STATUS_DATA_3_STATUS_MASK           (0x100U)
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT          (8U)
+#define SDIF_STATUS_DATA_3_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
+#define SDIF_STATUS_DATA_BUSY_MASK               (0x200U)
+#define SDIF_STATUS_DATA_BUSY_SHIFT              (9U)
+#define SDIF_STATUS_DATA_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK      (0x400U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT     (10U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
+#define SDIF_STATUS_RESPONSE_INDEX_MASK          (0x1F800U)
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT         (11U)
+#define SDIF_STATUS_RESPONSE_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
+#define SDIF_STATUS_FIFO_COUNT_MASK              (0x3FFE0000U)
+#define SDIF_STATUS_FIFO_COUNT_SHIFT             (17U)
+#define SDIF_STATUS_FIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
+#define SDIF_STATUS_DMA_ACK_MASK                 (0x40000000U)
+#define SDIF_STATUS_DMA_ACK_SHIFT                (30U)
+#define SDIF_STATUS_DMA_ACK(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
+#define SDIF_STATUS_DMA_REQ_MASK                 (0x80000000U)
+#define SDIF_STATUS_DMA_REQ_SHIFT                (31U)
+#define SDIF_STATUS_DMA_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
+
+/*! @name FIFOTH - FIFO Threshold Watermark register */
+#define SDIF_FIFOTH_TX_WMARK_MASK                (0xFFFU)
+#define SDIF_FIFOTH_TX_WMARK_SHIFT               (0U)
+#define SDIF_FIFOTH_TX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
+#define SDIF_FIFOTH_RX_WMARK_MASK                (0xFFF0000U)
+#define SDIF_FIFOTH_RX_WMARK_SHIFT               (16U)
+#define SDIF_FIFOTH_RX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
+#define SDIF_FIFOTH_DMA_MTS_MASK                 (0x70000000U)
+#define SDIF_FIFOTH_DMA_MTS_SHIFT                (28U)
+#define SDIF_FIFOTH_DMA_MTS(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
+
+/*! @name CDETECT - Card Detect register */
+#define SDIF_CDETECT_CARD_DETECT_MASK            (0x1U)
+#define SDIF_CDETECT_CARD_DETECT_SHIFT           (0U)
+#define SDIF_CDETECT_CARD_DETECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
+
+/*! @name WRTPRT - Write Protect register */
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK           (0x1U)
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT          (0U)
+#define SDIF_WRTPRT_WRITE_PROTECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
+
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT  (0U)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
+
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT  (0U)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
+
+/*! @name DEBNCE - Debounce Count register */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK          (0xFFFFFFU)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT         (0U)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
+
+/*! @name RST_N - Hardware Reset */
+#define SDIF_RST_N_CARD_RESET_MASK               (0x1U)
+#define SDIF_RST_N_CARD_RESET_SHIFT              (0U)
+#define SDIF_RST_N_CARD_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
+
+/*! @name BMOD - Bus Mode register */
+#define SDIF_BMOD_SWR_MASK                       (0x1U)
+#define SDIF_BMOD_SWR_SHIFT                      (0U)
+#define SDIF_BMOD_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
+#define SDIF_BMOD_FB_MASK                        (0x2U)
+#define SDIF_BMOD_FB_SHIFT                       (1U)
+#define SDIF_BMOD_FB(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
+#define SDIF_BMOD_DSL_MASK                       (0x7CU)
+#define SDIF_BMOD_DSL_SHIFT                      (2U)
+#define SDIF_BMOD_DSL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
+#define SDIF_BMOD_DE_MASK                        (0x80U)
+#define SDIF_BMOD_DE_SHIFT                       (7U)
+#define SDIF_BMOD_DE(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
+#define SDIF_BMOD_PBL_MASK                       (0x700U)
+#define SDIF_BMOD_PBL_SHIFT                      (8U)
+#define SDIF_BMOD_PBL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
+
+/*! @name PLDMND - Poll Demand register */
+#define SDIF_PLDMND_PD_MASK                      (0xFFFFFFFFU)
+#define SDIF_PLDMND_PD_SHIFT                     (0U)
+#define SDIF_PLDMND_PD(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
+
+/*! @name DBADDR - Descriptor List Base Address register */
+#define SDIF_DBADDR_SDL_MASK                     (0xFFFFFFFFU)
+#define SDIF_DBADDR_SDL_SHIFT                    (0U)
+#define SDIF_DBADDR_SDL(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
+
+/*! @name IDSTS - Internal DMAC Status register */
+#define SDIF_IDSTS_TI_MASK                       (0x1U)
+#define SDIF_IDSTS_TI_SHIFT                      (0U)
+#define SDIF_IDSTS_TI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
+#define SDIF_IDSTS_RI_MASK                       (0x2U)
+#define SDIF_IDSTS_RI_SHIFT                      (1U)
+#define SDIF_IDSTS_RI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
+#define SDIF_IDSTS_FBE_MASK                      (0x4U)
+#define SDIF_IDSTS_FBE_SHIFT                     (2U)
+#define SDIF_IDSTS_FBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
+#define SDIF_IDSTS_DU_MASK                       (0x10U)
+#define SDIF_IDSTS_DU_SHIFT                      (4U)
+#define SDIF_IDSTS_DU(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
+#define SDIF_IDSTS_CES_MASK                      (0x20U)
+#define SDIF_IDSTS_CES_SHIFT                     (5U)
+#define SDIF_IDSTS_CES(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
+#define SDIF_IDSTS_NIS_MASK                      (0x100U)
+#define SDIF_IDSTS_NIS_SHIFT                     (8U)
+#define SDIF_IDSTS_NIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
+#define SDIF_IDSTS_AIS_MASK                      (0x200U)
+#define SDIF_IDSTS_AIS_SHIFT                     (9U)
+#define SDIF_IDSTS_AIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
+#define SDIF_IDSTS_EB_MASK                       (0x1C00U)
+#define SDIF_IDSTS_EB_SHIFT                      (10U)
+#define SDIF_IDSTS_EB(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
+#define SDIF_IDSTS_FSM_MASK                      (0x1E000U)
+#define SDIF_IDSTS_FSM_SHIFT                     (13U)
+#define SDIF_IDSTS_FSM(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
+
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
+#define SDIF_IDINTEN_TI_MASK                     (0x1U)
+#define SDIF_IDINTEN_TI_SHIFT                    (0U)
+#define SDIF_IDINTEN_TI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
+#define SDIF_IDINTEN_RI_MASK                     (0x2U)
+#define SDIF_IDINTEN_RI_SHIFT                    (1U)
+#define SDIF_IDINTEN_RI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
+#define SDIF_IDINTEN_FBE_MASK                    (0x4U)
+#define SDIF_IDINTEN_FBE_SHIFT                   (2U)
+#define SDIF_IDINTEN_FBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
+#define SDIF_IDINTEN_DU_MASK                     (0x10U)
+#define SDIF_IDINTEN_DU_SHIFT                    (4U)
+#define SDIF_IDINTEN_DU(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
+#define SDIF_IDINTEN_CES_MASK                    (0x20U)
+#define SDIF_IDINTEN_CES_SHIFT                   (5U)
+#define SDIF_IDINTEN_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
+#define SDIF_IDINTEN_NIS_MASK                    (0x100U)
+#define SDIF_IDINTEN_NIS_SHIFT                   (8U)
+#define SDIF_IDINTEN_NIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
+#define SDIF_IDINTEN_AIS_MASK                    (0x200U)
+#define SDIF_IDINTEN_AIS_SHIFT                   (9U)
+#define SDIF_IDINTEN_AIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
+
+/*! @name DSCADDR - Current Host Descriptor Address register */
+#define SDIF_DSCADDR_HDA_MASK                    (0xFFFFFFFFU)
+#define SDIF_DSCADDR_HDA_SHIFT                   (0U)
+#define SDIF_DSCADDR_HDA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
+
+/*! @name BUFADDR - Current Buffer Descriptor Address register */
+#define SDIF_BUFADDR_HBA_MASK                    (0xFFFFFFFFU)
+#define SDIF_BUFADDR_HBA_SHIFT                   (0U)
+#define SDIF_BUFADDR_HBA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
+
+/*! @name CARDTHRCTL - Card Threshold Control */
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK         (0x1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT        (0U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK         (0x2U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT        (1U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK       (0xFF0000U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT      (16U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
+
+/*! @name BACKENDPWR - Power control */
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK          (0x1U)
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT         (0U)
+#define SDIF_BACKENDPWR_BACKENDPWR(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
+
+/*! @name FIFO - SDIF FIFO */
+#define SDIF_FIFO_DATA_MASK                      (0xFFFFFFFFU)
+#define SDIF_FIFO_DATA_SHIFT                     (0U)
+#define SDIF_FIFO_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
+
+/* The count of SDIF_FIFO */
+#define SDIF_FIFO_COUNT                          (64U)
+
+
+/*!
+ * @}
+ */ /* end of group SDIF_Register_Masks */
+
+
+/* SDIF - Peripheral instance base addresses */
+/** Peripheral SDIF base address */
+#define SDIF_BASE                                (0x4009B000u)
+/** Peripheral SDIF base pointer */
+#define SDIF                                     ((SDIF_Type *)SDIF_BASE)
+/** Array initializer of SDIF peripheral base addresses */
+#define SDIF_BASE_ADDRS                          { SDIF_BASE }
+/** Array initializer of SDIF peripheral base pointers */
+#define SDIF_BASE_PTRS                           { SDIF }
+/** Interrupt vectors for the SDIF peripheral type */
+#define SDIF_IRQS                                { SDIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDIF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMARTCARD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
+ * @{
+ */
+
+/** SMARTCARD - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t DLL;                               /**< Divisor Latch LSB, offset: 0x0 */
+    __I  uint32_t RBR;                               /**< Receiver Buffer Register, offset: 0x0 */
+    __O  uint32_t THR;                               /**< Transmit Holding Register, offset: 0x0 */
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint32_t DLM;                               /**< Divisor Latch MSB, offset: 0x4 */
+    __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x4 */
+  };
+  union {                                          /* offset: 0x8 */
+    __O  uint32_t FCR;                               /**< FIFO Control Register, offset: 0x8 */
+    __I  uint32_t IIR;                               /**< Interrupt ID Register, offset: 0x8 */
+  };
+  __IO uint32_t LCR;                               /**< Line Control Register, offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __I  uint32_t LSR;                               /**< Line Status Register, offset: 0x14 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SCR;                               /**< Scratch Pad Register, offset: 0x1C */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t OSR;                               /**< Oversampling register, offset: 0x2C */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t SCICTRL;                           /**< Smart Card Interface control register, offset: 0x48 */
+} SMARTCARD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMARTCARD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
+ * @{
+ */
+
+/*! @name DLL - Divisor Latch LSB */
+#define SMARTCARD_DLL_DLLSB_MASK                 (0xFFU)
+#define SMARTCARD_DLL_DLLSB_SHIFT                (0U)
+#define SMARTCARD_DLL_DLLSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
+
+/*! @name RBR - Receiver Buffer Register */
+#define SMARTCARD_RBR_RBR_MASK                   (0xFFU)
+#define SMARTCARD_RBR_RBR_SHIFT                  (0U)
+#define SMARTCARD_RBR_RBR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
+
+/*! @name THR - Transmit Holding Register */
+#define SMARTCARD_THR_THR_MASK                   (0xFFU)
+#define SMARTCARD_THR_THR_SHIFT                  (0U)
+#define SMARTCARD_THR_THR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
+
+/*! @name DLM - Divisor Latch MSB */
+#define SMARTCARD_DLM_DLMSB_MASK                 (0xFFU)
+#define SMARTCARD_DLM_DLMSB_SHIFT                (0U)
+#define SMARTCARD_DLM_DLMSB(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
+
+/*! @name IER - Interrupt Enable Register */
+#define SMARTCARD_IER_RBRIE_MASK                 (0x1U)
+#define SMARTCARD_IER_RBRIE_SHIFT                (0U)
+#define SMARTCARD_IER_RBRIE(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
+#define SMARTCARD_IER_THREIE_MASK                (0x2U)
+#define SMARTCARD_IER_THREIE_SHIFT               (1U)
+#define SMARTCARD_IER_THREIE(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
+#define SMARTCARD_IER_RXIE_MASK                  (0x4U)
+#define SMARTCARD_IER_RXIE_SHIFT                 (2U)
+#define SMARTCARD_IER_RXIE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
+
+/*! @name FCR - FIFO Control Register */
+#define SMARTCARD_FCR_FIFOEN_MASK                (0x1U)
+#define SMARTCARD_FCR_FIFOEN_SHIFT               (0U)
+#define SMARTCARD_FCR_FIFOEN(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
+#define SMARTCARD_FCR_RXFIFORES_MASK             (0x2U)
+#define SMARTCARD_FCR_RXFIFORES_SHIFT            (1U)
+#define SMARTCARD_FCR_RXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
+#define SMARTCARD_FCR_TXFIFORES_MASK             (0x4U)
+#define SMARTCARD_FCR_TXFIFORES_SHIFT            (2U)
+#define SMARTCARD_FCR_TXFIFORES(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
+#define SMARTCARD_FCR_DMAMODE_MASK               (0x8U)
+#define SMARTCARD_FCR_DMAMODE_SHIFT              (3U)
+#define SMARTCARD_FCR_DMAMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
+#define SMARTCARD_FCR_RXTRIGLVL_MASK             (0xC0U)
+#define SMARTCARD_FCR_RXTRIGLVL_SHIFT            (6U)
+#define SMARTCARD_FCR_RXTRIGLVL(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
+
+/*! @name IIR - Interrupt ID Register */
+#define SMARTCARD_IIR_INTSTATUS_MASK             (0x1U)
+#define SMARTCARD_IIR_INTSTATUS_SHIFT            (0U)
+#define SMARTCARD_IIR_INTSTATUS(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
+#define SMARTCARD_IIR_INTID_MASK                 (0xEU)
+#define SMARTCARD_IIR_INTID_SHIFT                (1U)
+#define SMARTCARD_IIR_INTID(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
+#define SMARTCARD_IIR_FIFOENABLE_MASK            (0xC0U)
+#define SMARTCARD_IIR_FIFOENABLE_SHIFT           (6U)
+#define SMARTCARD_IIR_FIFOENABLE(x)              (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
+
+/*! @name LCR - Line Control Register */
+#define SMARTCARD_LCR_WLS_MASK                   (0x3U)
+#define SMARTCARD_LCR_WLS_SHIFT                  (0U)
+#define SMARTCARD_LCR_WLS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
+#define SMARTCARD_LCR_SBS_MASK                   (0x4U)
+#define SMARTCARD_LCR_SBS_SHIFT                  (2U)
+#define SMARTCARD_LCR_SBS(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
+#define SMARTCARD_LCR_PE_MASK                    (0x8U)
+#define SMARTCARD_LCR_PE_SHIFT                   (3U)
+#define SMARTCARD_LCR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
+#define SMARTCARD_LCR_PS_MASK                    (0x30U)
+#define SMARTCARD_LCR_PS_SHIFT                   (4U)
+#define SMARTCARD_LCR_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
+#define SMARTCARD_LCR_DLAB_MASK                  (0x80U)
+#define SMARTCARD_LCR_DLAB_SHIFT                 (7U)
+#define SMARTCARD_LCR_DLAB(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
+
+/*! @name LSR - Line Status Register */
+#define SMARTCARD_LSR_RDR_MASK                   (0x1U)
+#define SMARTCARD_LSR_RDR_SHIFT                  (0U)
+#define SMARTCARD_LSR_RDR(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
+#define SMARTCARD_LSR_OE_MASK                    (0x2U)
+#define SMARTCARD_LSR_OE_SHIFT                   (1U)
+#define SMARTCARD_LSR_OE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
+#define SMARTCARD_LSR_PE_MASK                    (0x4U)
+#define SMARTCARD_LSR_PE_SHIFT                   (2U)
+#define SMARTCARD_LSR_PE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
+#define SMARTCARD_LSR_FE_MASK                    (0x8U)
+#define SMARTCARD_LSR_FE_SHIFT                   (3U)
+#define SMARTCARD_LSR_FE(x)                      (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
+#define SMARTCARD_LSR_THRE_MASK                  (0x20U)
+#define SMARTCARD_LSR_THRE_SHIFT                 (5U)
+#define SMARTCARD_LSR_THRE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
+#define SMARTCARD_LSR_TEMT_MASK                  (0x40U)
+#define SMARTCARD_LSR_TEMT_SHIFT                 (6U)
+#define SMARTCARD_LSR_TEMT(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
+#define SMARTCARD_LSR_RXFE_MASK                  (0x80U)
+#define SMARTCARD_LSR_RXFE_SHIFT                 (7U)
+#define SMARTCARD_LSR_RXFE(x)                    (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
+
+/*! @name SCR - Scratch Pad Register */
+#define SMARTCARD_SCR_PAD_MASK                   (0xFFU)
+#define SMARTCARD_SCR_PAD_SHIFT                  (0U)
+#define SMARTCARD_SCR_PAD(x)                     (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
+
+/*! @name OSR - Oversampling register */
+#define SMARTCARD_OSR_OSFRAC_MASK                (0xEU)
+#define SMARTCARD_OSR_OSFRAC_SHIFT               (1U)
+#define SMARTCARD_OSR_OSFRAC(x)                  (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
+#define SMARTCARD_OSR_OSINT_MASK                 (0xF0U)
+#define SMARTCARD_OSR_OSINT_SHIFT                (4U)
+#define SMARTCARD_OSR_OSINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
+#define SMARTCARD_OSR_FDINT_MASK                 (0x7F00U)
+#define SMARTCARD_OSR_FDINT_SHIFT                (8U)
+#define SMARTCARD_OSR_FDINT(x)                   (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
+
+/*! @name SCICTRL - Smart Card Interface control register */
+#define SMARTCARD_SCICTRL_SCIEN_MASK             (0x1U)
+#define SMARTCARD_SCICTRL_SCIEN_SHIFT            (0U)
+#define SMARTCARD_SCICTRL_SCIEN(x)               (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
+#define SMARTCARD_SCICTRL_NACKDIS_MASK           (0x2U)
+#define SMARTCARD_SCICTRL_NACKDIS_SHIFT          (1U)
+#define SMARTCARD_SCICTRL_NACKDIS(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
+#define SMARTCARD_SCICTRL_PROTSEL_MASK           (0x4U)
+#define SMARTCARD_SCICTRL_PROTSEL_SHIFT          (2U)
+#define SMARTCARD_SCICTRL_PROTSEL(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
+#define SMARTCARD_SCICTRL_TXRETRY_MASK           (0xE0U)
+#define SMARTCARD_SCICTRL_TXRETRY_SHIFT          (5U)
+#define SMARTCARD_SCICTRL_TXRETRY(x)             (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
+#define SMARTCARD_SCICTRL_GUARDTIME_MASK         (0xFF00U)
+#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT        (8U)
+#define SMARTCARD_SCICTRL_GUARDTIME(x)           (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Register_Masks */
+
+
+/* SMARTCARD - Peripheral instance base addresses */
+/** Peripheral SMARTCARD0 base address */
+#define SMARTCARD0_BASE                          (0x40036000u)
+/** Peripheral SMARTCARD0 base pointer */
+#define SMARTCARD0                               ((SMARTCARD_Type *)SMARTCARD0_BASE)
+/** Peripheral SMARTCARD1 base address */
+#define SMARTCARD1_BASE                          (0x40037000u)
+/** Peripheral SMARTCARD1 base pointer */
+#define SMARTCARD1                               ((SMARTCARD_Type *)SMARTCARD1_BASE)
+/** Array initializer of SMARTCARD peripheral base addresses */
+#define SMARTCARD_BASE_ADDRS                     { SMARTCARD0_BASE, SMARTCARD1_BASE }
+/** Array initializer of SMARTCARD peripheral base pointers */
+#define SMARTCARD_BASE_PTRS                      { SMARTCARD0, SMARTCARD1 }
+/** Interrupt vectors for the SMARTCARD peripheral type */
+#define SMARTCARD_IRQS                           { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1024];
+  __IO uint32_t CFG;                               /**< SPI Configuration register, offset: 0x400 */
+  __IO uint32_t DLY;                               /**< SPI Delay register, offset: 0x404 */
+  __IO uint32_t STAT;                              /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
+  __IO uint32_t INTENSET;                          /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
+  __O  uint32_t INTENCLR;                          /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t DIV;                               /**< SPI clock Divider, offset: 0x424 */
+  __I  uint32_t INTSTAT;                           /**< SPI Interrupt Status, offset: 0x428 */
+       uint8_t RESERVED_2[2516];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_6[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+       uint8_t RESERVED_7[440];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - SPI Configuration register */
+#define SPI_CFG_ENABLE_MASK                      (0x1U)
+#define SPI_CFG_ENABLE_SHIFT                     (0U)
+#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+#define SPI_CFG_MASTER_MASK                      (0x4U)
+#define SPI_CFG_MASTER_SHIFT                     (2U)
+#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+#define SPI_CFG_LSBF_MASK                        (0x8U)
+#define SPI_CFG_LSBF_SHIFT                       (3U)
+#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+#define SPI_CFG_CPHA_MASK                        (0x10U)
+#define SPI_CFG_CPHA_SHIFT                       (4U)
+#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+#define SPI_CFG_CPOL_MASK                        (0x20U)
+#define SPI_CFG_CPOL_SHIFT                       (5U)
+#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+#define SPI_CFG_LOOP_MASK                        (0x80U)
+#define SPI_CFG_LOOP_SHIFT                       (7U)
+#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+#define SPI_CFG_SPOL0_MASK                       (0x100U)
+#define SPI_CFG_SPOL0_SHIFT                      (8U)
+#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+#define SPI_CFG_SPOL1_MASK                       (0x200U)
+#define SPI_CFG_SPOL1_SHIFT                      (9U)
+#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+#define SPI_CFG_SPOL2_MASK                       (0x400U)
+#define SPI_CFG_SPOL2_SHIFT                      (10U)
+#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+#define SPI_CFG_SPOL3_MASK                       (0x800U)
+#define SPI_CFG_SPOL3_SHIFT                      (11U)
+#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+
+/*! @name DLY - SPI Delay register */
+#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
+#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
+#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
+#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
+#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
+#define SPI_STAT_SSA_MASK                        (0x10U)
+#define SPI_STAT_SSA_SHIFT                       (4U)
+#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+#define SPI_STAT_SSD_MASK                        (0x20U)
+#define SPI_STAT_SSD_SHIFT                       (5U)
+#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+#define SPI_STAT_STALLED_MASK                    (0x40U)
+#define SPI_STAT_STALLED_SHIFT                   (6U)
+#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
+#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
+#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
+#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
+#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
+#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
+#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
+#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
+#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
+#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+
+/*! @name DIV - SPI clock Divider */
+#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT                     (0U)
+#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - SPI Interrupt Status */
+#define SPI_INTSTAT_SSA_MASK                     (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT                    (4U)
+#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+#define SPI_INTSTAT_SSD_MASK                     (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT                    (5U)
+#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
+#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
+#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
+#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
+#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
+#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
+#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
+#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
+#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
+#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
+#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+#define SPI_FIFOCFG_POPDBG_MASK                  (0x40000U)
+#define SPI_FIFOCFG_POPDBG_SHIFT                 (18U)
+#define SPI_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
+#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
+#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
+#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
+#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
+#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
+#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
+#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
+#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
+#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
+#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
+#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
+#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
+#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
+#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
+#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
+#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
+#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
+#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
+#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
+#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
+#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
+#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
+#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
+#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
+#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
+#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
+#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
+#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
+#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
+#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
+#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT                     (20U)
+#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT                     (21U)
+#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
+#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT                     (24U)
+#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
+#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
+#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
+#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
+#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
+#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+#define SPI_FIFORD_SOT_MASK                      (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT                     (20U)
+#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
+#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
+#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define SPI_ID_APERTURE_MASK                     (0xFFU)
+#define SPI_ID_APERTURE_SHIFT                    (0U)
+#define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+#define SPI_ID_MINOR_REV_MASK                    (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT                   (8U)
+#define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+#define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT                   (12U)
+#define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+#define SPI_ID_ID_MASK                           (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT                          (16U)
+#define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40086000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40087000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x40088000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+/** Peripheral SPI3 base address */
+#define SPI3_BASE                                (0x40089000u)
+/** Peripheral SPI3 base pointer */
+#define SPI3                                     ((SPI_Type *)SPI3_BASE)
+/** Peripheral SPI4 base address */
+#define SPI4_BASE                                (0x4008A000u)
+/** Peripheral SPI4 base pointer */
+#define SPI4                                     ((SPI_Type *)SPI4_BASE)
+/** Peripheral SPI5 base address */
+#define SPI5_BASE                                (0x40096000u)
+/** Peripheral SPI5 base pointer */
+#define SPI5                                     ((SPI_Type *)SPI5_BASE)
+/** Peripheral SPI6 base address */
+#define SPI6_BASE                                (0x40097000u)
+/** Peripheral SPI6 base pointer */
+#define SPI6                                     ((SPI_Type *)SPI6_BASE)
+/** Peripheral SPI7 base address */
+#define SPI7_BASE                                (0x40098000u)
+/** Peripheral SPI7 base pointer */
+#define SPI7                                     ((SPI_Type *)SPI7_BASE)
+/** Peripheral SPI8 base address */
+#define SPI8_BASE                                (0x40099000u)
+/** Peripheral SPI8 base pointer */
+#define SPI8                                     ((SPI_Type *)SPI8_BASE)
+/** Peripheral SPI9 base address */
+#define SPI9_BASE                                (0x4009A000u)
+/** Peripheral SPI9 base pointer */
+#define SPI9                                     ((SPI_Type *)SPI9_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
+ * @{
+ */
+
+/** SPIFI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< SPIFI control register, offset: 0x0 */
+  __IO uint32_t CMD;                               /**< SPIFI command register, offset: 0x4 */
+  __IO uint32_t ADDR;                              /**< SPIFI address register, offset: 0x8 */
+  __IO uint32_t IDATA;                             /**< SPIFI intermediate data register, offset: 0xC */
+  __IO uint32_t CLIMIT;                            /**< SPIFI limit register, offset: 0x10 */
+  __IO uint32_t DATA;                              /**< SPIFI data register, offset: 0x14 */
+  __IO uint32_t MCMD;                              /**< SPIFI memory command register, offset: 0x18 */
+  __IO uint32_t STAT;                              /**< SPIFI status register, offset: 0x1C */
+} SPIFI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPIFI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
+ * @{
+ */
+
+/*! @name CTRL - SPIFI control register */
+#define SPIFI_CTRL_TIMEOUT_MASK                  (0xFFFFU)
+#define SPIFI_CTRL_TIMEOUT_SHIFT                 (0U)
+#define SPIFI_CTRL_TIMEOUT(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
+#define SPIFI_CTRL_CSHIGH_MASK                   (0xF0000U)
+#define SPIFI_CTRL_CSHIGH_SHIFT                  (16U)
+#define SPIFI_CTRL_CSHIGH(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
+#define SPIFI_CTRL_D_PRFTCH_DIS_MASK             (0x200000U)
+#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT            (21U)
+#define SPIFI_CTRL_D_PRFTCH_DIS(x)               (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_INTEN_MASK                    (0x400000U)
+#define SPIFI_CTRL_INTEN_SHIFT                   (22U)
+#define SPIFI_CTRL_INTEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
+#define SPIFI_CTRL_MODE3_MASK                    (0x800000U)
+#define SPIFI_CTRL_MODE3_SHIFT                   (23U)
+#define SPIFI_CTRL_MODE3(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
+#define SPIFI_CTRL_PRFTCH_DIS_MASK               (0x8000000U)
+#define SPIFI_CTRL_PRFTCH_DIS_SHIFT              (27U)
+#define SPIFI_CTRL_PRFTCH_DIS(x)                 (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_DUAL_MASK                     (0x10000000U)
+#define SPIFI_CTRL_DUAL_SHIFT                    (28U)
+#define SPIFI_CTRL_DUAL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
+#define SPIFI_CTRL_RFCLK_MASK                    (0x20000000U)
+#define SPIFI_CTRL_RFCLK_SHIFT                   (29U)
+#define SPIFI_CTRL_RFCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
+#define SPIFI_CTRL_FBCLK_MASK                    (0x40000000U)
+#define SPIFI_CTRL_FBCLK_SHIFT                   (30U)
+#define SPIFI_CTRL_FBCLK(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
+#define SPIFI_CTRL_DMAEN_MASK                    (0x80000000U)
+#define SPIFI_CTRL_DMAEN_SHIFT                   (31U)
+#define SPIFI_CTRL_DMAEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
+
+/*! @name CMD - SPIFI command register */
+#define SPIFI_CMD_DATALEN_MASK                   (0x3FFFU)
+#define SPIFI_CMD_DATALEN_SHIFT                  (0U)
+#define SPIFI_CMD_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
+#define SPIFI_CMD_POLL_MASK                      (0x4000U)
+#define SPIFI_CMD_POLL_SHIFT                     (14U)
+#define SPIFI_CMD_POLL(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
+#define SPIFI_CMD_DOUT_MASK                      (0x8000U)
+#define SPIFI_CMD_DOUT_SHIFT                     (15U)
+#define SPIFI_CMD_DOUT(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
+#define SPIFI_CMD_INTLEN_MASK                    (0x70000U)
+#define SPIFI_CMD_INTLEN_SHIFT                   (16U)
+#define SPIFI_CMD_INTLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
+#define SPIFI_CMD_FIELDFORM_MASK                 (0x180000U)
+#define SPIFI_CMD_FIELDFORM_SHIFT                (19U)
+#define SPIFI_CMD_FIELDFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
+#define SPIFI_CMD_FRAMEFORM_MASK                 (0xE00000U)
+#define SPIFI_CMD_FRAMEFORM_SHIFT                (21U)
+#define SPIFI_CMD_FRAMEFORM(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
+#define SPIFI_CMD_OPCODE_MASK                    (0xFF000000U)
+#define SPIFI_CMD_OPCODE_SHIFT                   (24U)
+#define SPIFI_CMD_OPCODE(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
+
+/*! @name ADDR - SPIFI address register */
+#define SPIFI_ADDR_ADDRESS_MASK                  (0xFFFFFFFFU)
+#define SPIFI_ADDR_ADDRESS_SHIFT                 (0U)
+#define SPIFI_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
+
+/*! @name IDATA - SPIFI intermediate data register */
+#define SPIFI_IDATA_IDATA_MASK                   (0xFFFFFFFFU)
+#define SPIFI_IDATA_IDATA_SHIFT                  (0U)
+#define SPIFI_IDATA_IDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
+
+/*! @name CLIMIT - SPIFI limit register */
+#define SPIFI_CLIMIT_CLIMIT_MASK                 (0xFFFFFFFFU)
+#define SPIFI_CLIMIT_CLIMIT_SHIFT                (0U)
+#define SPIFI_CLIMIT_CLIMIT(x)                   (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
+
+/*! @name DATA - SPIFI data register */
+#define SPIFI_DATA_DATA_MASK                     (0xFFFFFFFFU)
+#define SPIFI_DATA_DATA_SHIFT                    (0U)
+#define SPIFI_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
+
+/*! @name MCMD - SPIFI memory command register */
+#define SPIFI_MCMD_POLL_MASK                     (0x4000U)
+#define SPIFI_MCMD_POLL_SHIFT                    (14U)
+#define SPIFI_MCMD_POLL(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
+#define SPIFI_MCMD_DOUT_MASK                     (0x8000U)
+#define SPIFI_MCMD_DOUT_SHIFT                    (15U)
+#define SPIFI_MCMD_DOUT(x)                       (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
+#define SPIFI_MCMD_INTLEN_MASK                   (0x70000U)
+#define SPIFI_MCMD_INTLEN_SHIFT                  (16U)
+#define SPIFI_MCMD_INTLEN(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
+#define SPIFI_MCMD_FIELDFORM_MASK                (0x180000U)
+#define SPIFI_MCMD_FIELDFORM_SHIFT               (19U)
+#define SPIFI_MCMD_FIELDFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
+#define SPIFI_MCMD_FRAMEFORM_MASK                (0xE00000U)
+#define SPIFI_MCMD_FRAMEFORM_SHIFT               (21U)
+#define SPIFI_MCMD_FRAMEFORM(x)                  (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
+#define SPIFI_MCMD_OPCODE_MASK                   (0xFF000000U)
+#define SPIFI_MCMD_OPCODE_SHIFT                  (24U)
+#define SPIFI_MCMD_OPCODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
+
+/*! @name STAT - SPIFI status register */
+#define SPIFI_STAT_MCINIT_MASK                   (0x1U)
+#define SPIFI_STAT_MCINIT_SHIFT                  (0U)
+#define SPIFI_STAT_MCINIT(x)                     (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
+#define SPIFI_STAT_CMD_MASK                      (0x2U)
+#define SPIFI_STAT_CMD_SHIFT                     (1U)
+#define SPIFI_STAT_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
+#define SPIFI_STAT_RESET_MASK                    (0x10U)
+#define SPIFI_STAT_RESET_SHIFT                   (4U)
+#define SPIFI_STAT_RESET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
+#define SPIFI_STAT_INTRQ_MASK                    (0x20U)
+#define SPIFI_STAT_INTRQ_SHIFT                   (5U)
+#define SPIFI_STAT_INTRQ(x)                      (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Register_Masks */
+
+
+/* SPIFI - Peripheral instance base addresses */
+/** Peripheral SPIFI0 base address */
+#define SPIFI0_BASE                              (0x40080000u)
+/** Peripheral SPIFI0 base pointer */
+#define SPIFI0                                   ((SPIFI_Type *)SPIFI0_BASE)
+/** Array initializer of SPIFI peripheral base addresses */
+#define SPIFI_BASE_ADDRS                         { SPIFI0_BASE }
+/** Array initializer of SPIFI peripheral base pointers */
+#define SPIFI_BASE_PTRS                          { SPIFI0 }
+/** Interrupt vectors for the SPIFI peripheral type */
+#define SPIFI_IRQS                               { SPIFI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCON - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t AHBMATPRIO;                        /**< AHB multilayer matrix priority control, offset: 0x10 */
+       uint8_t RESERVED_1[44];
+  __IO uint32_t SYSTCKCAL;                         /**< System tick counter calibration, offset: 0x40 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
+  __IO uint32_t ASYNCAPBCTRL;                      /**< Asynchronous APB Control, offset: 0x4C */
+       uint8_t RESERVED_3[112];
+  __I  uint32_t PIOPORCAP[2];                      /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t PIORESCAP[2];                      /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
+       uint8_t RESERVED_5[40];
+  __IO uint32_t PRESETCTRL[3];                     /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
+       uint8_t RESERVED_6[20];
+  __O  uint32_t PRESETCTRLSET[3];                  /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t PRESETCTRLCLR[3];                  /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
+       uint8_t RESERVED_8[164];
+  __IO uint32_t SYSRSTSTAT;                        /**< System reset status register, offset: 0x1F0 */
+       uint8_t RESERVED_9[12];
+  __IO uint32_t AHBCLKCTRL[3];                     /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_10[20];
+  __O  uint32_t AHBCLKCTRLSET[3];                  /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
+       uint8_t RESERVED_11[20];
+  __O  uint32_t AHBCLKCTRLCLR[3];                  /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
+       uint8_t RESERVED_12[52];
+  __IO uint32_t MAINCLKSELA;                       /**< Main clock source select A, offset: 0x280 */
+  __IO uint32_t MAINCLKSELB;                       /**< Main clock source select B, offset: 0x284 */
+  __IO uint32_t CLKOUTSELA;                        /**< CLKOUT clock source select A, offset: 0x288 */
+       uint8_t RESERVED_13[4];
+  __IO uint32_t SYSPLLCLKSEL;                      /**< PLL clock source select, offset: 0x290 */
+       uint8_t RESERVED_14[4];
+  __IO uint32_t AUDPLLCLKSEL;                      /**< Audio PLL clock source select, offset: 0x298 */
+       uint8_t RESERVED_15[4];
+  __IO uint32_t SPIFICLKSEL;                       /**< SPIFI clock source select, offset: 0x2A0 */
+  __IO uint32_t ADCCLKSEL;                         /**< ADC clock source select, offset: 0x2A4 */
+  __IO uint32_t USB0CLKSEL;                        /**< USB0 clock source select, offset: 0x2A8 */
+  __IO uint32_t USB1CLKSEL;                        /**< USB1 clock source select, offset: 0x2AC */
+  __IO uint32_t FCLKSEL[10];                       /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */
+       uint8_t RESERVED_16[8];
+  __IO uint32_t MCLKCLKSEL;                        /**< MCLK clock source select, offset: 0x2E0 */
+       uint8_t RESERVED_17[4];
+  __IO uint32_t FRGCLKSEL;                         /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
+  __IO uint32_t DMICCLKSEL;                        /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
+  __IO uint32_t SCTCLKSEL;                         /**< SCTimer/PWM clock source select, offset: 0x2F0 */
+  __IO uint32_t LCDCLKSEL;                         /**< LCD clock source select, offset: 0x2F4 */
+  __IO uint32_t SDIOCLKSEL;                        /**< SDIO clock source select, offset: 0x2F8 */
+       uint8_t RESERVED_18[4];
+  __IO uint32_t SYSTICKCLKDIV;                     /**< SYSTICK clock divider, offset: 0x300 */
+  __IO uint32_t ARMTRACECLKDIV;                    /**< ARM Trace clock divider, offset: 0x304 */
+  __IO uint32_t CAN0CLKDIV;                        /**< MCAN0 clock divider, offset: 0x308 */
+  __IO uint32_t CAN1CLKDIV;                        /**< MCAN1 clock divider, offset: 0x30C */
+  __IO uint32_t SC0CLKDIV;                         /**< Smartcard0 clock divider, offset: 0x310 */
+  __IO uint32_t SC1CLKDIV;                         /**< Smartcard1 clock divider, offset: 0x314 */
+       uint8_t RESERVED_19[104];
+  __IO uint32_t AHBCLKDIV;                         /**< AHB clock divider, offset: 0x380 */
+  __IO uint32_t CLKOUTDIV;                         /**< CLKOUT clock divider, offset: 0x384 */
+  __IO uint32_t FROHFCLKDIV;                       /**< FROHF clock divider, offset: 0x388 */
+       uint8_t RESERVED_20[4];
+  __IO uint32_t SPIFICLKDIV;                       /**< SPIFI clock divider, offset: 0x390 */
+  __IO uint32_t ADCCLKDIV;                         /**< ADC clock divider, offset: 0x394 */
+  __IO uint32_t USB0CLKDIV;                        /**< USB0 clock divider, offset: 0x398 */
+  __IO uint32_t USB1CLKDIV;                        /**< USB1 clock divider, offset: 0x39C */
+  __IO uint32_t FRGCTRL;                           /**< Fractional rate divider, offset: 0x3A0 */
+       uint8_t RESERVED_21[4];
+  __IO uint32_t DMICCLKDIV;                        /**< DMIC clock divider, offset: 0x3A8 */
+  __IO uint32_t MCLKDIV;                           /**< I2S MCLK clock divider, offset: 0x3AC */
+  __IO uint32_t LCDCLKDIV;                         /**< LCD clock divider, offset: 0x3B0 */
+  __IO uint32_t SCTCLKDIV;                         /**< SCT/PWM clock divider, offset: 0x3B4 */
+  __IO uint32_t EMCCLKDIV;                         /**< EMC clock divider, offset: 0x3B8 */
+  __IO uint32_t SDIOCLKDIV;                        /**< SDIO clock divider, offset: 0x3BC */
+       uint8_t RESERVED_22[64];
+  __IO uint32_t FLASHCFG;                          /**< Flash wait states configuration, offset: 0x400 */
+       uint8_t RESERVED_23[8];
+  __IO uint32_t USB0CLKCTRL;                       /**< USB0 clock control, offset: 0x40C */
+  __IO uint32_t USB0CLKSTAT;                       /**< USB0 clock status, offset: 0x410 */
+       uint8_t RESERVED_24[4];
+  __IO uint32_t FREQMECTRL;                        /**< Frequency measure register, offset: 0x418 */
+       uint8_t RESERVED_25[4];
+  __IO uint32_t MCLKIO;                            /**< MCLK input/output control, offset: 0x420 */
+  __IO uint32_t USB1CLKCTRL;                       /**< USB1 clock control, offset: 0x424 */
+  __IO uint32_t USB1CLKSTAT;                       /**< USB1 clock status, offset: 0x428 */
+       uint8_t RESERVED_26[24];
+  __IO uint32_t EMCSYSCTRL;                        /**< EMC system control, offset: 0x444 */
+  __IO uint32_t EMCDLYCTRL;                        /**< EMC clock delay control, offset: 0x448 */
+  __IO uint32_t EMCDLYCAL;                         /**< EMC delay chain calibration control, offset: 0x44C */
+  __IO uint32_t ETHPHYSEL;                         /**< Ethernet PHY Selection, offset: 0x450 */
+  __IO uint32_t ETHSBDCTRL;                        /**< Ethernet SBD flow control, offset: 0x454 */
+       uint8_t RESERVED_27[8];
+  __IO uint32_t SDIOCLKCTRL;                       /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
+       uint8_t RESERVED_28[156];
+  __IO uint32_t FROCTRL;                           /**< FRO oscillator control, offset: 0x500 */
+  __IO uint32_t SYSOSCCTRL;                        /**< System oscillator control, offset: 0x504 */
+  __IO uint32_t WDTOSCCTRL;                        /**< Watchdog oscillator control, offset: 0x508 */
+  __IO uint32_t RTCOSCCTRL;                        /**< RTC oscillator 32 kHz output control, offset: 0x50C */
+       uint8_t RESERVED_29[12];
+  __IO uint32_t USBPLLCTRL;                        /**< USB PLL control, offset: 0x51C */
+  __IO uint32_t USBPLLSTAT;                        /**< USB PLL status, offset: 0x520 */
+       uint8_t RESERVED_30[92];
+  __IO uint32_t SYSPLLCTRL;                        /**< System PLL control, offset: 0x580 */
+  __IO uint32_t SYSPLLSTAT;                        /**< PLL status, offset: 0x584 */
+  __IO uint32_t SYSPLLNDEC;                        /**< PLL N divider, offset: 0x588 */
+  __IO uint32_t SYSPLLPDEC;                        /**< PLL P divider, offset: 0x58C */
+  __IO uint32_t SYSPLLMDEC;                        /**< System PLL M divider, offset: 0x590 */
+       uint8_t RESERVED_31[12];
+  __IO uint32_t AUDPLLCTRL;                        /**< Audio PLL control, offset: 0x5A0 */
+  __IO uint32_t AUDPLLSTAT;                        /**< Audio PLL status, offset: 0x5A4 */
+  __IO uint32_t AUDPLLNDEC;                        /**< Audio PLL N divider, offset: 0x5A8 */
+  __IO uint32_t AUDPLLPDEC;                        /**< Audio PLL P divider, offset: 0x5AC */
+  __IO uint32_t AUDPLLMDEC;                        /**< Audio PLL M divider, offset: 0x5B0 */
+  __IO uint32_t AUDPLLFRAC;                        /**< Audio PLL fractional divider control, offset: 0x5B4 */
+       uint8_t RESERVED_32[72];
+  __IO uint32_t PDSLEEPCFG[2];                     /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */
+       uint8_t RESERVED_33[8];
+  __IO uint32_t PDRUNCFG[2];                       /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */
+       uint8_t RESERVED_34[8];
+  __IO uint32_t PDRUNCFGSET[2];                    /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */
+       uint8_t RESERVED_35[8];
+  __IO uint32_t PDRUNCFGCLR[2];                    /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */
+       uint8_t RESERVED_36[72];
+  __IO uint32_t STARTER[2];                        /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
+       uint8_t RESERVED_37[24];
+  __O  uint32_t STARTERSET[2];                     /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
+       uint8_t RESERVED_38[24];
+  __O  uint32_t STARTERCLR[2];                     /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
+       uint8_t RESERVED_39[184];
+  __IO uint32_t HWWAKE;                            /**< Configures special cases of hardware wake-up, offset: 0x780 */
+       uint8_t RESERVED_40[1664];
+  __IO uint32_t AUTOCGOR;                          /**< Auto Clock-Gate Override Register, offset: 0xE04 */
+       uint8_t RESERVED_41[492];
+  __I  uint32_t JTAGIDCODE;                        /**< JTAG ID code register, offset: 0xFF4 */
+  __I  uint32_t DEVICE_ID0;                        /**< Part ID register, offset: 0xFF8 */
+  __I  uint32_t DEVICE_ID1;                        /**< Boot ROM and die revision register, offset: 0xFFC */
+       uint8_t RESERVED_42[127044];
+  __IO uint32_t BODCTRL;                           /**< Brown-Out Detect control, offset: 0x20044 */
+} SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSCON Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
+ * @{
+ */
+
+/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
+#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK         (0x3U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT        (0U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK         (0xCU)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT        (2U)
+#define SYSCON_AHBMATPRIO_PRI_DCODE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SYS_MASK           (0x30U)
+#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT          (4U)
+#define SYSCON_AHBMATPRIO_PRI_SYS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DMA_MASK           (0x3C0U)
+#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT          (6U)
+#define SYSCON_AHBMATPRIO_PRI_DMA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
+#define SYSCON_AHBMATPRIO_PRI_ETH_MASK           (0xC00U)
+#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT          (10U)
+#define SYSCON_AHBMATPRIO_PRI_ETH(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
+#define SYSCON_AHBMATPRIO_PRI_LCD_MASK           (0x3000U)
+#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT          (12U)
+#define SYSCON_AHBMATPRIO_PRI_LCD(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB0_MASK          (0xC000U)
+#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT         (14U)
+#define SYSCON_AHBMATPRIO_PRI_USB0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB1_MASK          (0x30000U)
+#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT         (16U)
+#define SYSCON_AHBMATPRIO_PRI_USB1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK          (0xC0000U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT         (18U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK         (0x300000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT        (20U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK         (0xC00000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT        (22U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SHA_MASK           (0x3000000U)
+#define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT          (24U)
+#define SYSCON_AHBMATPRIO_PRI_SHA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK)
+
+/*! @name SYSTCKCAL - System tick counter calibration */
+#define SYSCON_SYSTCKCAL_CAL_MASK                (0xFFFFFFU)
+#define SYSCON_SYSTCKCAL_CAL_SHIFT               (0U)
+#define SYSCON_SYSTCKCAL_CAL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
+#define SYSCON_SYSTCKCAL_SKEW_MASK               (0x1000000U)
+#define SYSCON_SYSTCKCAL_SKEW_SHIFT              (24U)
+#define SYSCON_SYSTCKCAL_SKEW(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
+#define SYSCON_SYSTCKCAL_NOREF_MASK              (0x2000000U)
+#define SYSCON_SYSTCKCAL_NOREF_SHIFT             (25U)
+#define SYSCON_SYSTCKCAL_NOREF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
+
+/*! @name NMISRC - NMI Source Select */
+#define SYSCON_NMISRC_IRQM4_MASK                 (0x3FU)
+#define SYSCON_NMISRC_IRQM4_SHIFT                (0U)
+#define SYSCON_NMISRC_IRQM4(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
+#define SYSCON_NMISRC_NMIENM4_MASK               (0x80000000U)
+#define SYSCON_NMISRC_NMIENM4_SHIFT              (31U)
+#define SYSCON_NMISRC_NMIENM4(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
+
+/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
+#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK          (0x1U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT         (0U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
+
+/*! @name PIOPORCAP - POR captured value of port n */
+#define SYSCON_PIOPORCAP_PIOPORCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT         (0U)
+#define SYSCON_PIOPORCAP_PIOPORCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
+
+/* The count of SYSCON_PIOPORCAP */
+#define SYSCON_PIOPORCAP_COUNT                   (2U)
+
+/*! @name PIORESCAP - Reset captured value of port n */
+#define SYSCON_PIORESCAP_PIORESCAP_MASK          (0xFFFFFFFFU)
+#define SYSCON_PIORESCAP_PIORESCAP_SHIFT         (0U)
+#define SYSCON_PIORESCAP_PIORESCAP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
+
+/* The count of SYSCON_PIORESCAP */
+#define SYSCON_PIORESCAP_COUNT                   (2U)
+
+/*! @name PRESETCTRL - Peripheral reset control n */
+#define SYSCON_PRESETCTRL_MRT_RST_MASK           (0x1U)
+#define SYSCON_PRESETCTRL_MRT_RST_SHIFT          (0U)
+#define SYSCON_PRESETCTRL_MRT_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
+#define SYSCON_PRESETCTRL_SCT0_RST_MASK          (0x4U)
+#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT         (2U)
+#define SYSCON_PRESETCTRL_SCT0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
+#define SYSCON_PRESETCTRL_LCD_RST_MASK           (0x4U)
+#define SYSCON_PRESETCTRL_LCD_RST_SHIFT          (2U)
+#define SYSCON_PRESETCTRL_LCD_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
+#define SYSCON_PRESETCTRL_SDIO_RST_MASK          (0x8U)
+#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT         (3U)
+#define SYSCON_PRESETCTRL_SDIO_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1H_RST_MASK         (0x10U)
+#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT        (4U)
+#define SYSCON_PRESETCTRL_USB1H_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1D_RST_MASK         (0x20U)
+#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT        (5U)
+#define SYSCON_PRESETCTRL_USB1D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK       (0x40U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT      (6U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
+#define SYSCON_PRESETCTRL_EMC_RESET_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT        (7U)
+#define SYSCON_PRESETCTRL_EMC_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
+#define SYSCON_PRESETCTRL_FLASH_RST_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT        (7U)
+#define SYSCON_PRESETCTRL_FLASH_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN0_RST_MASK         (0x80U)
+#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT        (7U)
+#define SYSCON_PRESETCTRL_MCAN0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
+#define SYSCON_PRESETCTRL_FMC_RST_MASK           (0x100U)
+#define SYSCON_PRESETCTRL_FMC_RST_SHIFT          (8U)
+#define SYSCON_PRESETCTRL_FMC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)
+#define SYSCON_PRESETCTRL_ETH_RST_MASK           (0x100U)
+#define SYSCON_PRESETCTRL_ETH_RST_SHIFT          (8U)
+#define SYSCON_PRESETCTRL_ETH_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN1_RST_MASK         (0x100U)
+#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT        (8U)
+#define SYSCON_PRESETCTRL_MCAN1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO4_RST_MASK         (0x200U)
+#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT        (9U)
+#define SYSCON_PRESETCTRL_GPIO4_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
+#define SYSCON_PRESETCTRL_EEPROM_RST_MASK        (0x200U)
+#define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT       (9U)
+#define SYSCON_PRESETCTRL_EEPROM_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO5_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT        (10U)
+#define SYSCON_PRESETCTRL_GPIO5_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
+#define SYSCON_PRESETCTRL_UTICK_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT        (10U)
+#define SYSCON_PRESETCTRL_UTICK_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
+#define SYSCON_PRESETCTRL_SPIFI_RST_MASK         (0x400U)
+#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT        (10U)
+#define SYSCON_PRESETCTRL_SPIFI_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
+#define SYSCON_PRESETCTRL_AES_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_AES_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_AES_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK)
+#define SYSCON_PRESETCTRL_MUX_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_MUX_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_MUX_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
+#define SYSCON_PRESETCTRL_FC0_RST_MASK           (0x800U)
+#define SYSCON_PRESETCTRL_FC0_RST_SHIFT          (11U)
+#define SYSCON_PRESETCTRL_FC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
+#define SYSCON_PRESETCTRL_OTP_RST_MASK           (0x1000U)
+#define SYSCON_PRESETCTRL_OTP_RST_SHIFT          (12U)
+#define SYSCON_PRESETCTRL_OTP_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
+#define SYSCON_PRESETCTRL_FC1_RST_MASK           (0x1000U)
+#define SYSCON_PRESETCTRL_FC1_RST_SHIFT          (12U)
+#define SYSCON_PRESETCTRL_FC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
+#define SYSCON_PRESETCTRL_IOCON_RST_MASK         (0x2000U)
+#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT        (13U)
+#define SYSCON_PRESETCTRL_IOCON_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
+#define SYSCON_PRESETCTRL_RNG_RST_MASK           (0x2000U)
+#define SYSCON_PRESETCTRL_RNG_RST_SHIFT          (13U)
+#define SYSCON_PRESETCTRL_RNG_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
+#define SYSCON_PRESETCTRL_FC2_RST_MASK           (0x2000U)
+#define SYSCON_PRESETCTRL_FC2_RST_SHIFT          (13U)
+#define SYSCON_PRESETCTRL_FC2_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
+#define SYSCON_PRESETCTRL_FC8_RST_MASK           (0x4000U)
+#define SYSCON_PRESETCTRL_FC8_RST_SHIFT          (14U)
+#define SYSCON_PRESETCTRL_FC8_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
+#define SYSCON_PRESETCTRL_FC3_RST_MASK           (0x4000U)
+#define SYSCON_PRESETCTRL_FC3_RST_SHIFT          (14U)
+#define SYSCON_PRESETCTRL_FC3_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO0_RST_MASK         (0x4000U)
+#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT        (14U)
+#define SYSCON_PRESETCTRL_GPIO0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO1_RST_MASK         (0x8000U)
+#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT        (15U)
+#define SYSCON_PRESETCTRL_GPIO1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
+#define SYSCON_PRESETCTRL_FC9_RST_MASK           (0x8000U)
+#define SYSCON_PRESETCTRL_FC9_RST_SHIFT          (15U)
+#define SYSCON_PRESETCTRL_FC9_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
+#define SYSCON_PRESETCTRL_FC4_RST_MASK           (0x8000U)
+#define SYSCON_PRESETCTRL_FC4_RST_SHIFT          (15U)
+#define SYSCON_PRESETCTRL_FC4_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK       (0x10000U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT      (16U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO2_RST_MASK         (0x10000U)
+#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT        (16U)
+#define SYSCON_PRESETCTRL_GPIO2_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
+#define SYSCON_PRESETCTRL_FC5_RST_MASK           (0x10000U)
+#define SYSCON_PRESETCTRL_FC5_RST_SHIFT          (16U)
+#define SYSCON_PRESETCTRL_FC5_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO3_RST_MASK         (0x20000U)
+#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT        (17U)
+#define SYSCON_PRESETCTRL_GPIO3_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
+#define SYSCON_PRESETCTRL_FC6_RST_MASK           (0x20000U)
+#define SYSCON_PRESETCTRL_FC6_RST_SHIFT          (17U)
+#define SYSCON_PRESETCTRL_FC6_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK       (0x20000U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT      (17U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
+#define SYSCON_PRESETCTRL_FC7_RST_MASK           (0x40000U)
+#define SYSCON_PRESETCTRL_FC7_RST_SHIFT          (18U)
+#define SYSCON_PRESETCTRL_FC7_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
+#define SYSCON_PRESETCTRL_SHA_RST_MASK           (0x40000U)
+#define SYSCON_PRESETCTRL_SHA_RST_SHIFT          (18U)
+#define SYSCON_PRESETCTRL_SHA_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
+#define SYSCON_PRESETCTRL_PINT_RST_MASK          (0x40000U)
+#define SYSCON_PRESETCTRL_PINT_RST_SHIFT         (18U)
+#define SYSCON_PRESETCTRL_PINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
+#define SYSCON_PRESETCTRL_DMIC_RST_MASK          (0x80000U)
+#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT         (19U)
+#define SYSCON_PRESETCTRL_DMIC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
+#define SYSCON_PRESETCTRL_SC0_RST_MASK           (0x80000U)
+#define SYSCON_PRESETCTRL_SC0_RST_SHIFT          (19U)
+#define SYSCON_PRESETCTRL_SC0_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
+#define SYSCON_PRESETCTRL_GINT_RST_MASK          (0x80000U)
+#define SYSCON_PRESETCTRL_GINT_RST_SHIFT         (19U)
+#define SYSCON_PRESETCTRL_GINT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
+#define SYSCON_PRESETCTRL_SC1_RST_MASK           (0x100000U)
+#define SYSCON_PRESETCTRL_SC1_RST_SHIFT          (20U)
+#define SYSCON_PRESETCTRL_SC1_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
+#define SYSCON_PRESETCTRL_DMA0_RST_MASK          (0x100000U)
+#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT         (20U)
+#define SYSCON_PRESETCTRL_DMA0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)
+#define SYSCON_PRESETCTRL_CRC_RST_MASK           (0x200000U)
+#define SYSCON_PRESETCTRL_CRC_RST_SHIFT          (21U)
+#define SYSCON_PRESETCTRL_CRC_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK       (0x400000U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT      (22U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
+#define SYSCON_PRESETCTRL_WWDT_RST_MASK          (0x400000U)
+#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT         (22U)
+#define SYSCON_PRESETCTRL_WWDT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0D_RST_MASK         (0x2000000U)
+#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT        (25U)
+#define SYSCON_PRESETCTRL_USB0D_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK       (0x4000000U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT      (26U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
+#define SYSCON_PRESETCTRL_ADC0_RST_MASK          (0x8000000U)
+#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT         (27U)
+#define SYSCON_PRESETCTRL_ADC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK       (0x8000000U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT      (27U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
+
+/* The count of SYSCON_PRESETCTRL */
+#define SYSCON_PRESETCTRL_COUNT                  (3U)
+
+/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLSET_RST_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT       (0U)
+#define SYSCON_PRESETCTRLSET_RST_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
+
+/* The count of SYSCON_PRESETCTRLSET */
+#define SYSCON_PRESETCTRLSET_COUNT               (3U)
+
+/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT       (0U)
+#define SYSCON_PRESETCTRLCLR_RST_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
+
+/* The count of SYSCON_PRESETCTRLCLR */
+#define SYSCON_PRESETCTRLCLR_COUNT               (3U)
+
+/*! @name SYSRSTSTAT - System reset status register */
+#define SYSCON_SYSRSTSTAT_POR_MASK               (0x1U)
+#define SYSCON_SYSRSTSTAT_POR_SHIFT              (0U)
+#define SYSCON_SYSRSTSTAT_POR(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
+#define SYSCON_SYSRSTSTAT_EXTRST_MASK            (0x2U)
+#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT           (1U)
+#define SYSCON_SYSRSTSTAT_EXTRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
+#define SYSCON_SYSRSTSTAT_WDT_MASK               (0x4U)
+#define SYSCON_SYSRSTSTAT_WDT_SHIFT              (2U)
+#define SYSCON_SYSRSTSTAT_WDT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
+#define SYSCON_SYSRSTSTAT_BOD_MASK               (0x8U)
+#define SYSCON_SYSRSTSTAT_BOD_SHIFT              (3U)
+#define SYSCON_SYSRSTSTAT_BOD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
+#define SYSCON_SYSRSTSTAT_SYSRST_MASK            (0x10U)
+#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT           (4U)
+#define SYSCON_SYSRSTSTAT_SYSRST(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
+
+/*! @name AHBCLKCTRL - AHB Clock control n */
+#define SYSCON_AHBCLKCTRL_MRT_MASK               (0x1U)
+#define SYSCON_AHBCLKCTRL_MRT_SHIFT              (0U)
+#define SYSCON_AHBCLKCTRL_MRT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
+#define SYSCON_AHBCLKCTRL_RIT_MASK               (0x2U)
+#define SYSCON_AHBCLKCTRL_RIT_SHIFT              (1U)
+#define SYSCON_AHBCLKCTRL_RIT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
+#define SYSCON_AHBCLKCTRL_ROM_MASK               (0x2U)
+#define SYSCON_AHBCLKCTRL_ROM_SHIFT              (1U)
+#define SYSCON_AHBCLKCTRL_ROM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
+#define SYSCON_AHBCLKCTRL_SCT0_MASK              (0x4U)
+#define SYSCON_AHBCLKCTRL_SCT0_SHIFT             (2U)
+#define SYSCON_AHBCLKCTRL_SCT0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
+#define SYSCON_AHBCLKCTRL_LCD_MASK               (0x4U)
+#define SYSCON_AHBCLKCTRL_LCD_SHIFT              (2U)
+#define SYSCON_AHBCLKCTRL_LCD(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM1_MASK             (0x8U)
+#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT            (3U)
+#define SYSCON_AHBCLKCTRL_SRAM1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
+#define SYSCON_AHBCLKCTRL_SDIO_MASK              (0x8U)
+#define SYSCON_AHBCLKCTRL_SDIO_SHIFT             (3U)
+#define SYSCON_AHBCLKCTRL_SDIO(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM2_MASK             (0x10U)
+#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT            (4U)
+#define SYSCON_AHBCLKCTRL_SRAM2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
+#define SYSCON_AHBCLKCTRL_USB1H_MASK             (0x10U)
+#define SYSCON_AHBCLKCTRL_USB1H_SHIFT            (4U)
+#define SYSCON_AHBCLKCTRL_USB1H(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM3_MASK             (0x20U)
+#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT            (5U)
+#define SYSCON_AHBCLKCTRL_SRAM3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
+#define SYSCON_AHBCLKCTRL_USB1D_MASK             (0x20U)
+#define SYSCON_AHBCLKCTRL_USB1D_SHIFT            (5U)
+#define SYSCON_AHBCLKCTRL_USB1D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
+#define SYSCON_AHBCLKCTRL_USB1RAM_MASK           (0x40U)
+#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT          (6U)
+#define SYSCON_AHBCLKCTRL_USB1RAM(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
+#define SYSCON_AHBCLKCTRL_FLASH_MASK             (0x80U)
+#define SYSCON_AHBCLKCTRL_FLASH_SHIFT            (7U)
+#define SYSCON_AHBCLKCTRL_FLASH(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)
+#define SYSCON_AHBCLKCTRL_EMC_MASK               (0x80U)
+#define SYSCON_AHBCLKCTRL_EMC_SHIFT              (7U)
+#define SYSCON_AHBCLKCTRL_EMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN0_MASK             (0x80U)
+#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT            (7U)
+#define SYSCON_AHBCLKCTRL_MCAN0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
+#define SYSCON_AHBCLKCTRL_FMC_MASK               (0x100U)
+#define SYSCON_AHBCLKCTRL_FMC_SHIFT              (8U)
+#define SYSCON_AHBCLKCTRL_FMC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)
+#define SYSCON_AHBCLKCTRL_ETH_MASK               (0x100U)
+#define SYSCON_AHBCLKCTRL_ETH_SHIFT              (8U)
+#define SYSCON_AHBCLKCTRL_ETH(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN1_MASK             (0x100U)
+#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT            (8U)
+#define SYSCON_AHBCLKCTRL_MCAN1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
+#define SYSCON_AHBCLKCTRL_EEPROM_MASK            (0x200U)
+#define SYSCON_AHBCLKCTRL_EEPROM_SHIFT           (9U)
+#define SYSCON_AHBCLKCTRL_EEPROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO4_MASK             (0x200U)
+#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT            (9U)
+#define SYSCON_AHBCLKCTRL_GPIO4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO5_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT            (10U)
+#define SYSCON_AHBCLKCTRL_GPIO5(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
+#define SYSCON_AHBCLKCTRL_UTICK_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_UTICK_SHIFT            (10U)
+#define SYSCON_AHBCLKCTRL_UTICK(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
+#define SYSCON_AHBCLKCTRL_SPIFI_MASK             (0x400U)
+#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT            (10U)
+#define SYSCON_AHBCLKCTRL_SPIFI(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK          (0x800U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT         (11U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
+#define SYSCON_AHBCLKCTRL_AES_MASK               (0x800U)
+#define SYSCON_AHBCLKCTRL_AES_SHIFT              (11U)
+#define SYSCON_AHBCLKCTRL_AES(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK         (0x800U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT        (11U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
+#define SYSCON_AHBCLKCTRL_OTP_MASK               (0x1000U)
+#define SYSCON_AHBCLKCTRL_OTP_SHIFT              (12U)
+#define SYSCON_AHBCLKCTRL_OTP(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK         (0x1000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT        (12U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
+#define SYSCON_AHBCLKCTRL_RNG_MASK               (0x2000U)
+#define SYSCON_AHBCLKCTRL_RNG_SHIFT              (13U)
+#define SYSCON_AHBCLKCTRL_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
+#define SYSCON_AHBCLKCTRL_IOCON_MASK             (0x2000U)
+#define SYSCON_AHBCLKCTRL_IOCON_SHIFT            (13U)
+#define SYSCON_AHBCLKCTRL_IOCON(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK         (0x2000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT        (13U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO0_MASK             (0x4000U)
+#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT            (14U)
+#define SYSCON_AHBCLKCTRL_GPIO0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK         (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT        (14U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK         (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT        (14U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK         (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT        (15U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK         (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT        (15U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO1_MASK             (0x8000U)
+#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT            (15U)
+#define SYSCON_AHBCLKCTRL_GPIO1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO2_MASK             (0x10000U)
+#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT            (16U)
+#define SYSCON_AHBCLKCTRL_GPIO2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HMR_MASK           (0x10000U)
+#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT          (16U)
+#define SYSCON_AHBCLKCTRL_USB0HMR(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK         (0x10000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT        (16U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK         (0x20000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT        (17U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO3_MASK             (0x20000U)
+#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT            (17U)
+#define SYSCON_AHBCLKCTRL_GPIO3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HSL_MASK           (0x20000U)
+#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT          (17U)
+#define SYSCON_AHBCLKCTRL_USB0HSL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
+#define SYSCON_AHBCLKCTRL_PINT_MASK              (0x40000U)
+#define SYSCON_AHBCLKCTRL_PINT_SHIFT             (18U)
+#define SYSCON_AHBCLKCTRL_PINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
+#define SYSCON_AHBCLKCTRL_SHA0_MASK              (0x40000U)
+#define SYSCON_AHBCLKCTRL_SHA0_SHIFT             (18U)
+#define SYSCON_AHBCLKCTRL_SHA0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK         (0x40000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT        (18U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
+#define SYSCON_AHBCLKCTRL_DMIC_MASK              (0x80000U)
+#define SYSCON_AHBCLKCTRL_DMIC_SHIFT             (19U)
+#define SYSCON_AHBCLKCTRL_DMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
+#define SYSCON_AHBCLKCTRL_GINT_MASK              (0x80000U)
+#define SYSCON_AHBCLKCTRL_GINT_SHIFT             (19U)
+#define SYSCON_AHBCLKCTRL_GINT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
+#define SYSCON_AHBCLKCTRL_SC0_MASK               (0x80000U)
+#define SYSCON_AHBCLKCTRL_SC0_SHIFT              (19U)
+#define SYSCON_AHBCLKCTRL_SC0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
+#define SYSCON_AHBCLKCTRL_SC1_MASK               (0x100000U)
+#define SYSCON_AHBCLKCTRL_SC1_SHIFT              (20U)
+#define SYSCON_AHBCLKCTRL_SC1(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
+#define SYSCON_AHBCLKCTRL_DMA_MASK               (0x100000U)
+#define SYSCON_AHBCLKCTRL_DMA_SHIFT              (20U)
+#define SYSCON_AHBCLKCTRL_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
+#define SYSCON_AHBCLKCTRL_CRC_MASK               (0x200000U)
+#define SYSCON_AHBCLKCTRL_CRC_SHIFT              (21U)
+#define SYSCON_AHBCLKCTRL_CRC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
+#define SYSCON_AHBCLKCTRL_WWDT_MASK              (0x400000U)
+#define SYSCON_AHBCLKCTRL_WWDT_SHIFT             (22U)
+#define SYSCON_AHBCLKCTRL_WWDT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER2_MASK           (0x400000U)
+#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT          (22U)
+#define SYSCON_AHBCLKCTRL_CTIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
+#define SYSCON_AHBCLKCTRL_RTC_MASK               (0x800000U)
+#define SYSCON_AHBCLKCTRL_RTC_SHIFT              (23U)
+#define SYSCON_AHBCLKCTRL_RTC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
+#define SYSCON_AHBCLKCTRL_USB0D_MASK             (0x2000000U)
+#define SYSCON_AHBCLKCTRL_USB0D_SHIFT            (25U)
+#define SYSCON_AHBCLKCTRL_USB0D(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER0_MASK           (0x4000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT          (26U)
+#define SYSCON_AHBCLKCTRL_CTIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER1_MASK           (0x8000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT          (27U)
+#define SYSCON_AHBCLKCTRL_CTIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
+#define SYSCON_AHBCLKCTRL_ADC0_MASK              (0x8000000U)
+#define SYSCON_AHBCLKCTRL_ADC0_SHIFT             (27U)
+#define SYSCON_AHBCLKCTRL_ADC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
+
+/* The count of SYSCON_AHBCLKCTRL */
+#define SYSCON_AHBCLKCTRL_COUNT                  (3U)
+
+/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT       (0U)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLSET */
+#define SYSCON_AHBCLKCTRLSET_COUNT               (3U)
+
+/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK        (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT       (0U)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLCLR */
+#define SYSCON_AHBCLKCTRLCLR_COUNT               (3U)
+
+/*! @name MAINCLKSELA - Main clock source select A */
+#define SYSCON_MAINCLKSELA_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELA_SEL_SHIFT             (0U)
+#define SYSCON_MAINCLKSELA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
+
+/*! @name MAINCLKSELB - Main clock source select B */
+#define SYSCON_MAINCLKSELB_SEL_MASK              (0x3U)
+#define SYSCON_MAINCLKSELB_SEL_SHIFT             (0U)
+#define SYSCON_MAINCLKSELB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
+
+/*! @name CLKOUTSELA - CLKOUT clock source select A */
+#define SYSCON_CLKOUTSELA_SEL_MASK               (0x7U)
+#define SYSCON_CLKOUTSELA_SEL_SHIFT              (0U)
+#define SYSCON_CLKOUTSELA_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
+
+/*! @name SYSPLLCLKSEL - PLL clock source select */
+#define SYSCON_SYSPLLCLKSEL_SEL_MASK             (0x7U)
+#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT            (0U)
+#define SYSCON_SYSPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+
+/*! @name AUDPLLCLKSEL - Audio PLL clock source select */
+#define SYSCON_AUDPLLCLKSEL_SEL_MASK             (0x7U)
+#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT            (0U)
+#define SYSCON_AUDPLLCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
+
+/*! @name SPIFICLKSEL - SPIFI clock source select */
+#define SYSCON_SPIFICLKSEL_SEL_MASK              (0x7U)
+#define SYSCON_SPIFICLKSEL_SEL_SHIFT             (0U)
+#define SYSCON_SPIFICLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
+
+/*! @name ADCCLKSEL - ADC clock source select */
+#define SYSCON_ADCCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_ADCCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_ADCCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
+
+/*! @name USB0CLKSEL - USB0 clock source select */
+#define SYSCON_USB0CLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_USB0CLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_USB0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
+
+/*! @name USB1CLKSEL - USB1 clock source select */
+#define SYSCON_USB1CLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_USB1CLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_USB1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
+
+/*! @name FCLKSEL - Flexcomm 0 clock source select */
+#define SYSCON_FCLKSEL_SEL_MASK                  (0x7U)
+#define SYSCON_FCLKSEL_SEL_SHIFT                 (0U)
+#define SYSCON_FCLKSEL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
+
+/* The count of SYSCON_FCLKSEL */
+#define SYSCON_FCLKSEL_COUNT                     (10U)
+
+/*! @name MCLKCLKSEL - MCLK clock source select */
+#define SYSCON_MCLKCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_MCLKCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
+
+/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
+#define SYSCON_FRGCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_FRGCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_FRGCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
+
+/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
+#define SYSCON_DMICCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_DMICCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_DMICCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
+
+/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
+#define SYSCON_SCTCLKSEL_SEL_MASK                (0x7U)
+#define SYSCON_SCTCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_SCTCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
+
+/*! @name LCDCLKSEL - LCD clock source select */
+#define SYSCON_LCDCLKSEL_SEL_MASK                (0x3U)
+#define SYSCON_LCDCLKSEL_SEL_SHIFT               (0U)
+#define SYSCON_LCDCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
+
+/*! @name SDIOCLKSEL - SDIO clock source select */
+#define SYSCON_SDIOCLKSEL_SEL_MASK               (0x7U)
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT              (0U)
+#define SYSCON_SDIOCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
+
+/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
+#define SYSCON_SYSTICKCLKDIV_DIV_MASK            (0xFFU)
+#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT           (0U)
+#define SYSCON_SYSTICKCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
+#define SYSCON_SYSTICKCLKDIV_RESET_MASK          (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT         (29U)
+#define SYSCON_SYSTICKCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
+#define SYSCON_SYSTICKCLKDIV_HALT_MASK           (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT          (30U)
+#define SYSCON_SYSTICKCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK        (0x80000000U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT       (31U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
+
+/*! @name ARMTRACECLKDIV - ARM Trace clock divider */
+#define SYSCON_ARMTRACECLKDIV_DIV_MASK           (0xFFU)
+#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT          (0U)
+#define SYSCON_ARMTRACECLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
+#define SYSCON_ARMTRACECLKDIV_RESET_MASK         (0x20000000U)
+#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT        (29U)
+#define SYSCON_ARMTRACECLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
+#define SYSCON_ARMTRACECLKDIV_HALT_MASK          (0x40000000U)
+#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT         (30U)
+#define SYSCON_ARMTRACECLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK       (0x80000000U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT      (31U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
+
+/*! @name CAN0CLKDIV - MCAN0 clock divider */
+#define SYSCON_CAN0CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_CAN0CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_CAN0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
+#define SYSCON_CAN0CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_CAN0CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_CAN0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
+#define SYSCON_CAN0CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_CAN0CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_CAN0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
+#define SYSCON_CAN0CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_CAN0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
+
+/*! @name CAN1CLKDIV - MCAN1 clock divider */
+#define SYSCON_CAN1CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_CAN1CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_CAN1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
+#define SYSCON_CAN1CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_CAN1CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_CAN1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
+#define SYSCON_CAN1CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_CAN1CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_CAN1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
+#define SYSCON_CAN1CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_CAN1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
+
+/*! @name SC0CLKDIV - Smartcard0 clock divider */
+#define SYSCON_SC0CLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SC0CLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_SC0CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
+#define SYSCON_SC0CLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SC0CLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_SC0CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
+#define SYSCON_SC0CLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SC0CLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_SC0CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
+#define SYSCON_SC0CLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_SC0CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
+
+/*! @name SC1CLKDIV - Smartcard1 clock divider */
+#define SYSCON_SC1CLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SC1CLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_SC1CLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
+#define SYSCON_SC1CLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SC1CLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_SC1CLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
+#define SYSCON_SC1CLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SC1CLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_SC1CLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
+#define SYSCON_SC1CLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_SC1CLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
+
+/*! @name AHBCLKDIV - AHB clock divider */
+#define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_AHBCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
+
+/*! @name CLKOUTDIV - CLKOUT clock divider */
+#define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
+#define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
+#define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
+#define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
+#define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
+#define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
+#define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_CLKOUTDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
+
+/*! @name FROHFCLKDIV - FROHF clock divider */
+#define SYSCON_FROHFCLKDIV_DIV_MASK              (0xFFU)
+#define SYSCON_FROHFCLKDIV_DIV_SHIFT             (0U)
+#define SYSCON_FROHFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK)
+#define SYSCON_FROHFCLKDIV_RESET_MASK            (0x20000000U)
+#define SYSCON_FROHFCLKDIV_RESET_SHIFT           (29U)
+#define SYSCON_FROHFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK)
+#define SYSCON_FROHFCLKDIV_HALT_MASK             (0x40000000U)
+#define SYSCON_FROHFCLKDIV_HALT_SHIFT            (30U)
+#define SYSCON_FROHFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK)
+#define SYSCON_FROHFCLKDIV_REQFLAG_MASK          (0x80000000U)
+#define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT         (31U)
+#define SYSCON_FROHFCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK)
+
+/*! @name SPIFICLKDIV - SPIFI clock divider */
+#define SYSCON_SPIFICLKDIV_DIV_MASK              (0xFFU)
+#define SYSCON_SPIFICLKDIV_DIV_SHIFT             (0U)
+#define SYSCON_SPIFICLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
+#define SYSCON_SPIFICLKDIV_RESET_MASK            (0x20000000U)
+#define SYSCON_SPIFICLKDIV_RESET_SHIFT           (29U)
+#define SYSCON_SPIFICLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
+#define SYSCON_SPIFICLKDIV_HALT_MASK             (0x40000000U)
+#define SYSCON_SPIFICLKDIV_HALT_SHIFT            (30U)
+#define SYSCON_SPIFICLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
+#define SYSCON_SPIFICLKDIV_REQFLAG_MASK          (0x80000000U)
+#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT         (31U)
+#define SYSCON_SPIFICLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
+
+/*! @name ADCCLKDIV - ADC clock divider */
+#define SYSCON_ADCCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_ADCCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_ADCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
+#define SYSCON_ADCCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_ADCCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_ADCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
+#define SYSCON_ADCCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_ADCCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_ADCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_ADCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
+
+/*! @name USB0CLKDIV - USB0 clock divider */
+#define SYSCON_USB0CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_USB0CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_USB0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
+#define SYSCON_USB0CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_USB0CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_USB0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
+#define SYSCON_USB0CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_USB0CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_USB0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_USB0CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
+
+/*! @name USB1CLKDIV - USB1 clock divider */
+#define SYSCON_USB1CLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_USB1CLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_USB1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
+#define SYSCON_USB1CLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_USB1CLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_USB1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
+#define SYSCON_USB1CLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_USB1CLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_USB1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
+#define SYSCON_USB1CLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_USB1CLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
+
+/*! @name FRGCTRL - Fractional rate divider */
+#define SYSCON_FRGCTRL_DIV_MASK                  (0xFFU)
+#define SYSCON_FRGCTRL_DIV_SHIFT                 (0U)
+#define SYSCON_FRGCTRL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
+#define SYSCON_FRGCTRL_MULT_MASK                 (0xFF00U)
+#define SYSCON_FRGCTRL_MULT_SHIFT                (8U)
+#define SYSCON_FRGCTRL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
+
+/*! @name DMICCLKDIV - DMIC clock divider */
+#define SYSCON_DMICCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_DMICCLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_DMICCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
+#define SYSCON_DMICCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_DMICCLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_DMICCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
+#define SYSCON_DMICCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_DMICCLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_DMICCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
+#define SYSCON_DMICCLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_DMICCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
+
+/*! @name MCLKDIV - I2S MCLK clock divider */
+#define SYSCON_MCLKDIV_DIV_MASK                  (0xFFU)
+#define SYSCON_MCLKDIV_DIV_SHIFT                 (0U)
+#define SYSCON_MCLKDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
+#define SYSCON_MCLKDIV_RESET_MASK                (0x20000000U)
+#define SYSCON_MCLKDIV_RESET_SHIFT               (29U)
+#define SYSCON_MCLKDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
+#define SYSCON_MCLKDIV_HALT_MASK                 (0x40000000U)
+#define SYSCON_MCLKDIV_HALT_SHIFT                (30U)
+#define SYSCON_MCLKDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
+#define SYSCON_MCLKDIV_REQFLAG_MASK              (0x80000000U)
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT             (31U)
+#define SYSCON_MCLKDIV_REQFLAG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
+
+/*! @name LCDCLKDIV - LCD clock divider */
+#define SYSCON_LCDCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_LCDCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_LCDCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
+#define SYSCON_LCDCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_LCDCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_LCDCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
+#define SYSCON_LCDCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_LCDCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_LCDCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
+#define SYSCON_LCDCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_LCDCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
+
+/*! @name SCTCLKDIV - SCT/PWM clock divider */
+#define SYSCON_SCTCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_SCTCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_SCTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
+#define SYSCON_SCTCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_SCTCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_SCTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
+#define SYSCON_SCTCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_SCTCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_SCTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_SCTCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
+
+/*! @name EMCCLKDIV - EMC clock divider */
+#define SYSCON_EMCCLKDIV_DIV_MASK                (0xFFU)
+#define SYSCON_EMCCLKDIV_DIV_SHIFT               (0U)
+#define SYSCON_EMCCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
+#define SYSCON_EMCCLKDIV_RESET_MASK              (0x20000000U)
+#define SYSCON_EMCCLKDIV_RESET_SHIFT             (29U)
+#define SYSCON_EMCCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
+#define SYSCON_EMCCLKDIV_HALT_MASK               (0x40000000U)
+#define SYSCON_EMCCLKDIV_HALT_SHIFT              (30U)
+#define SYSCON_EMCCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
+#define SYSCON_EMCCLKDIV_REQFLAG_MASK            (0x80000000U)
+#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT           (31U)
+#define SYSCON_EMCCLKDIV_REQFLAG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
+
+/*! @name SDIOCLKDIV - SDIO clock divider */
+#define SYSCON_SDIOCLKDIV_DIV_MASK               (0xFFU)
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT              (0U)
+#define SYSCON_SDIOCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
+#define SYSCON_SDIOCLKDIV_RESET_MASK             (0x20000000U)
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT            (29U)
+#define SYSCON_SDIOCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
+#define SYSCON_SDIOCLKDIV_HALT_MASK              (0x40000000U)
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT             (30U)
+#define SYSCON_SDIOCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK           (0x80000000U)
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT          (31U)
+#define SYSCON_SDIOCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
+
+/*! @name FLASHCFG - Flash wait states configuration */
+#define SYSCON_FLASHCFG_FETCHCFG_MASK            (0x3U)
+#define SYSCON_FLASHCFG_FETCHCFG_SHIFT           (0U)
+#define SYSCON_FLASHCFG_FETCHCFG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)
+#define SYSCON_FLASHCFG_DATACFG_MASK             (0xCU)
+#define SYSCON_FLASHCFG_DATACFG_SHIFT            (2U)
+#define SYSCON_FLASHCFG_DATACFG(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)
+#define SYSCON_FLASHCFG_ACCEL_MASK               (0x10U)
+#define SYSCON_FLASHCFG_ACCEL_SHIFT              (4U)
+#define SYSCON_FLASHCFG_ACCEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)
+#define SYSCON_FLASHCFG_PREFEN_MASK              (0x20U)
+#define SYSCON_FLASHCFG_PREFEN_SHIFT             (5U)
+#define SYSCON_FLASHCFG_PREFEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)
+#define SYSCON_FLASHCFG_PREFOVR_MASK             (0x40U)
+#define SYSCON_FLASHCFG_PREFOVR_SHIFT            (6U)
+#define SYSCON_FLASHCFG_PREFOVR(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)
+#define SYSCON_FLASHCFG_FLASHTIM_MASK            (0xF000U)
+#define SYSCON_FLASHCFG_FLASHTIM_SHIFT           (12U)
+#define SYSCON_FLASHCFG_FLASHTIM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)
+
+/*! @name USB0CLKCTRL - USB0 clock control */
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK       (0x10U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT      (4U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
+
+/*! @name USB0CLKSTAT - USB0 clock status */
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
+
+/*! @name FREQMECTRL - Frequency measure register */
+#define SYSCON_FREQMECTRL_CAPVAL_MASK            (0x3FFFU)
+#define SYSCON_FREQMECTRL_CAPVAL_SHIFT           (0U)
+#define SYSCON_FREQMECTRL_CAPVAL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
+#define SYSCON_FREQMECTRL_PROG_MASK              (0x80000000U)
+#define SYSCON_FREQMECTRL_PROG_SHIFT             (31U)
+#define SYSCON_FREQMECTRL_PROG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
+
+/*! @name MCLKIO - MCLK input/output control */
+#define SYSCON_MCLKIO_DIR_MASK                   (0x1U)
+#define SYSCON_MCLKIO_DIR_SHIFT                  (0U)
+#define SYSCON_MCLKIO_DIR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
+
+/*! @name USB1CLKCTRL - USB1 clock control */
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK    (0x1U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT   (0U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK   (0x2U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT  (1U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK   (0x4U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT  (2U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK  (0x8U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK  (0x10U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
+
+/*! @name USB1CLKSTAT - USB1 clock status */
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK   (0x1U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT  (0U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK  (0x2U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
+
+/*! @name EMCSYSCTRL - EMC system control */
+#define SYSCON_EMCSYSCTRL_EMCSC_MASK             (0x1U)
+#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT            (0U)
+#define SYSCON_EMCSYSCTRL_EMCSC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCRD_MASK             (0x2U)
+#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT            (1U)
+#define SYSCON_EMCSYSCTRL_EMCRD(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
+#define SYSCON_EMCSYSCTRL_EMCBC_MASK             (0x4U)
+#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT            (2U)
+#define SYSCON_EMCSYSCTRL_EMCBC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK     (0x8U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT    (3U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
+
+/*! @name EMCDLYCTRL - EMC clock delay control */
+#define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK         (0x1FU)
+#define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT        (0U)
+#define SYSCON_EMCDLYCTRL_CMD_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK       (0x1F00U)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT      (8U)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK)
+
+/*! @name EMCDLYCAL - EMC delay chain calibration control */
+#define SYSCON_EMCDLYCAL_CALVALUE_MASK           (0xFFU)
+#define SYSCON_EMCDLYCAL_CALVALUE_SHIFT          (0U)
+#define SYSCON_EMCDLYCAL_CALVALUE(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK)
+#define SYSCON_EMCDLYCAL_START_MASK              (0x4000U)
+#define SYSCON_EMCDLYCAL_START_SHIFT             (14U)
+#define SYSCON_EMCDLYCAL_START(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK)
+#define SYSCON_EMCDLYCAL_DONE_MASK               (0x8000U)
+#define SYSCON_EMCDLYCAL_DONE_SHIFT              (15U)
+#define SYSCON_EMCDLYCAL_DONE(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK)
+
+/*! @name ETHPHYSEL - Ethernet PHY Selection */
+#define SYSCON_ETHPHYSEL_PHY_SEL_MASK            (0x4U)
+#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT           (2U)
+#define SYSCON_ETHPHYSEL_PHY_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
+
+/*! @name ETHSBDCTRL - Ethernet SBD flow control */
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK          (0x3U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT         (0U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
+
+/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK   (0x3U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT  (0U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK     (0x80U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT    (7U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK   (0x1F0000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT  (16U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
+
+/*! @name FROCTRL - FRO oscillator control */
+#define SYSCON_FROCTRL_TRIM_MASK                 (0x3FFFU)
+#define SYSCON_FROCTRL_TRIM_SHIFT                (0U)
+#define SYSCON_FROCTRL_TRIM(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)
+#define SYSCON_FROCTRL_SEL_MASK                  (0x4000U)
+#define SYSCON_FROCTRL_SEL_SHIFT                 (14U)
+#define SYSCON_FROCTRL_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
+#define SYSCON_FROCTRL_FREQTRIM_MASK             (0xFF0000U)
+#define SYSCON_FROCTRL_FREQTRIM_SHIFT            (16U)
+#define SYSCON_FROCTRL_FREQTRIM(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
+#define SYSCON_FROCTRL_USBCLKADJ_MASK            (0x1000000U)
+#define SYSCON_FROCTRL_USBCLKADJ_SHIFT           (24U)
+#define SYSCON_FROCTRL_USBCLKADJ(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
+#define SYSCON_FROCTRL_USBMODCHG_MASK            (0x2000000U)
+#define SYSCON_FROCTRL_USBMODCHG_SHIFT           (25U)
+#define SYSCON_FROCTRL_USBMODCHG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
+#define SYSCON_FROCTRL_HSPDCLK_MASK              (0x40000000U)
+#define SYSCON_FROCTRL_HSPDCLK_SHIFT             (30U)
+#define SYSCON_FROCTRL_HSPDCLK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
+#define SYSCON_FROCTRL_WRTRIM_MASK               (0x80000000U)
+#define SYSCON_FROCTRL_WRTRIM_SHIFT              (31U)
+#define SYSCON_FROCTRL_WRTRIM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)
+
+/*! @name SYSOSCCTRL - System oscillator control */
+#define SYSCON_SYSOSCCTRL_BYPASS_MASK            (0x1U)
+#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT           (0U)
+#define SYSCON_SYSOSCCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK         (0x2U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT        (1U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
+
+/*! @name WDTOSCCTRL - Watchdog oscillator control */
+#define SYSCON_WDTOSCCTRL_DIVSEL_MASK            (0x1FU)
+#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT           (0U)
+#define SYSCON_WDTOSCCTRL_DIVSEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
+#define SYSCON_WDTOSCCTRL_FREQSEL_MASK           (0x3E0U)
+#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT          (5U)
+#define SYSCON_WDTOSCCTRL_FREQSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
+
+/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
+#define SYSCON_RTCOSCCTRL_EN_MASK                (0x1U)
+#define SYSCON_RTCOSCCTRL_EN_SHIFT               (0U)
+#define SYSCON_RTCOSCCTRL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
+
+/*! @name USBPLLCTRL - USB PLL control */
+#define SYSCON_USBPLLCTRL_MSEL_MASK              (0xFFU)
+#define SYSCON_USBPLLCTRL_MSEL_SHIFT             (0U)
+#define SYSCON_USBPLLCTRL_MSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
+#define SYSCON_USBPLLCTRL_PSEL_MASK              (0x300U)
+#define SYSCON_USBPLLCTRL_PSEL_SHIFT             (8U)
+#define SYSCON_USBPLLCTRL_PSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
+#define SYSCON_USBPLLCTRL_NSEL_MASK              (0xC00U)
+#define SYSCON_USBPLLCTRL_NSEL_SHIFT             (10U)
+#define SYSCON_USBPLLCTRL_NSEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
+#define SYSCON_USBPLLCTRL_DIRECT_MASK            (0x1000U)
+#define SYSCON_USBPLLCTRL_DIRECT_SHIFT           (12U)
+#define SYSCON_USBPLLCTRL_DIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
+#define SYSCON_USBPLLCTRL_BYPASS_MASK            (0x2000U)
+#define SYSCON_USBPLLCTRL_BYPASS_SHIFT           (13U)
+#define SYSCON_USBPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
+#define SYSCON_USBPLLCTRL_FBSEL_MASK             (0x4000U)
+#define SYSCON_USBPLLCTRL_FBSEL_SHIFT            (14U)
+#define SYSCON_USBPLLCTRL_FBSEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
+
+/*! @name USBPLLSTAT - USB PLL status */
+#define SYSCON_USBPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_USBPLLSTAT_LOCK_SHIFT             (0U)
+#define SYSCON_USBPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
+
+/*! @name SYSPLLCTRL - System PLL control */
+#define SYSCON_SYSPLLCTRL_SELR_MASK              (0xFU)
+#define SYSCON_SYSPLLCTRL_SELR_SHIFT             (0U)
+#define SYSCON_SYSPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
+#define SYSCON_SYSPLLCTRL_SELI_MASK              (0x3F0U)
+#define SYSCON_SYSPLLCTRL_SELI_SHIFT             (4U)
+#define SYSCON_SYSPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
+#define SYSCON_SYSPLLCTRL_SELP_MASK              (0x7C00U)
+#define SYSCON_SYSPLLCTRL_SELP_SHIFT             (10U)
+#define SYSCON_SYSPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
+#define SYSCON_SYSPLLCTRL_BYPASS_MASK            (0x8000U)
+#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT           (15U)
+#define SYSCON_SYSPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK          (0x20000U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT         (17U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTI_MASK           (0x80000U)
+#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT          (19U)
+#define SYSCON_SYSPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTO_MASK           (0x100000U)
+#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT          (20U)
+#define SYSCON_SYSPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
+
+/*! @name SYSPLLSTAT - PLL status */
+#define SYSCON_SYSPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_SYSPLLSTAT_LOCK_SHIFT             (0U)
+#define SYSCON_SYSPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
+
+/*! @name SYSPLLNDEC - PLL N divider */
+#define SYSCON_SYSPLLNDEC_NDEC_MASK              (0x3FFU)
+#define SYSCON_SYSPLLNDEC_NDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
+#define SYSCON_SYSPLLNDEC_NREQ_MASK              (0x400U)
+#define SYSCON_SYSPLLNDEC_NREQ_SHIFT             (10U)
+#define SYSCON_SYSPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
+
+/*! @name SYSPLLPDEC - PLL P divider */
+#define SYSCON_SYSPLLPDEC_PDEC_MASK              (0x7FU)
+#define SYSCON_SYSPLLPDEC_PDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
+#define SYSCON_SYSPLLPDEC_PREQ_MASK              (0x80U)
+#define SYSCON_SYSPLLPDEC_PREQ_SHIFT             (7U)
+#define SYSCON_SYSPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
+
+/*! @name SYSPLLMDEC - System PLL M divider */
+#define SYSCON_SYSPLLMDEC_MDEC_MASK              (0x1FFFFU)
+#define SYSCON_SYSPLLMDEC_MDEC_SHIFT             (0U)
+#define SYSCON_SYSPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
+#define SYSCON_SYSPLLMDEC_MREQ_MASK              (0x20000U)
+#define SYSCON_SYSPLLMDEC_MREQ_SHIFT             (17U)
+#define SYSCON_SYSPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
+
+/*! @name AUDPLLCTRL - Audio PLL control */
+#define SYSCON_AUDPLLCTRL_SELR_MASK              (0xFU)
+#define SYSCON_AUDPLLCTRL_SELR_SHIFT             (0U)
+#define SYSCON_AUDPLLCTRL_SELR(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
+#define SYSCON_AUDPLLCTRL_SELI_MASK              (0x3F0U)
+#define SYSCON_AUDPLLCTRL_SELI_SHIFT             (4U)
+#define SYSCON_AUDPLLCTRL_SELI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
+#define SYSCON_AUDPLLCTRL_SELP_MASK              (0x7C00U)
+#define SYSCON_AUDPLLCTRL_SELP_SHIFT             (10U)
+#define SYSCON_AUDPLLCTRL_SELP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
+#define SYSCON_AUDPLLCTRL_BYPASS_MASK            (0x8000U)
+#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT           (15U)
+#define SYSCON_AUDPLLCTRL_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK          (0x20000U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT         (17U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTI_MASK           (0x80000U)
+#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT          (19U)
+#define SYSCON_AUDPLLCTRL_DIRECTI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTO_MASK           (0x100000U)
+#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT          (20U)
+#define SYSCON_AUDPLLCTRL_DIRECTO(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
+
+/*! @name AUDPLLSTAT - Audio PLL status */
+#define SYSCON_AUDPLLSTAT_LOCK_MASK              (0x1U)
+#define SYSCON_AUDPLLSTAT_LOCK_SHIFT             (0U)
+#define SYSCON_AUDPLLSTAT_LOCK(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
+
+/*! @name AUDPLLNDEC - Audio PLL N divider */
+#define SYSCON_AUDPLLNDEC_NDEC_MASK              (0x3FFU)
+#define SYSCON_AUDPLLNDEC_NDEC_SHIFT             (0U)
+#define SYSCON_AUDPLLNDEC_NDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
+#define SYSCON_AUDPLLNDEC_NREQ_MASK              (0x400U)
+#define SYSCON_AUDPLLNDEC_NREQ_SHIFT             (10U)
+#define SYSCON_AUDPLLNDEC_NREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
+
+/*! @name AUDPLLPDEC - Audio PLL P divider */
+#define SYSCON_AUDPLLPDEC_PDEC_MASK              (0x7FU)
+#define SYSCON_AUDPLLPDEC_PDEC_SHIFT             (0U)
+#define SYSCON_AUDPLLPDEC_PDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
+#define SYSCON_AUDPLLPDEC_PREQ_MASK              (0x80U)
+#define SYSCON_AUDPLLPDEC_PREQ_SHIFT             (7U)
+#define SYSCON_AUDPLLPDEC_PREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
+
+/*! @name AUDPLLMDEC - Audio PLL M divider */
+#define SYSCON_AUDPLLMDEC_MDEC_MASK              (0x1FFFFU)
+#define SYSCON_AUDPLLMDEC_MDEC_SHIFT             (0U)
+#define SYSCON_AUDPLLMDEC_MDEC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
+#define SYSCON_AUDPLLMDEC_MREQ_MASK              (0x20000U)
+#define SYSCON_AUDPLLMDEC_MREQ_SHIFT             (17U)
+#define SYSCON_AUDPLLMDEC_MREQ(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
+
+/*! @name AUDPLLFRAC - Audio PLL fractional divider control */
+#define SYSCON_AUDPLLFRAC_CTRL_MASK              (0x3FFFFFU)
+#define SYSCON_AUDPLLFRAC_CTRL_SHIFT             (0U)
+#define SYSCON_AUDPLLFRAC_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
+#define SYSCON_AUDPLLFRAC_REQ_MASK               (0x400000U)
+#define SYSCON_AUDPLLFRAC_REQ_SHIFT              (22U)
+#define SYSCON_AUDPLLFRAC_REQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK           (0x800000U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT          (23U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
+
+/*! @name PDSLEEPCFG - Power configuration register 0 */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK     (0x1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT    (0U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK     (0x2U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT    (1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK      (0x4U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT     (2U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK       (0x8U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT      (3U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK          (0x10U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT         (4U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK       (0x20U)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT      (5U)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK           (0x40U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT          (6U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK      (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT     (7U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK          (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT         (7U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK     (0x100U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT    (8U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK      (0x200U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT     (9U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK         (0x400U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT        (10U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK        (0x2000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT       (13U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK        (0x4000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT       (14U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK    (0x8000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT   (15U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK      (0x10000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT     (16U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK          (0x20000U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT         (17U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK         (0x80000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT        (19U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK      (0x100000U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT     (20U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK     (0x200000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT    (21U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK      (0x400000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT     (22U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK        (0x800000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT       (23U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK          (0x4000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT         (26U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK          (0x8000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT         (27U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK          (0x10000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT         (28U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK          (0x20000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT         (29U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDSLEEPCFG */
+#define SYSCON_PDSLEEPCFG_COUNT                  (2U)
+
+/*! @name PDRUNCFG - Power configuration register 0 */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK       (0x1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT      (0U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK       (0x2U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT      (1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK        (0x4U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT       (2U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK         (0x8U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT        (3U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_FRO_MASK            (0x10U)
+#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT           (4U)
+#define SYSCON_PDRUNCFG_PDEN_FRO(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK         (0x20U)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT        (5U)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_TS_MASK             (0x40U)
+#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT            (6U)
+#define SYSCON_PDRUNCFG_PDEN_TS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK        (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT       (7U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFG_PDEN_RNG_MASK            (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT           (7U)
+#define SYSCON_PDRUNCFG_PDEN_RNG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK       (0x100U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT      (8U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK        (0x200U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT       (9U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK           (0x400U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT          (10U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK          (0x2000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT         (13U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK          (0x4000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT         (14U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK      (0x8000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT     (15U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK        (0x10000U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT       (16U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ROM_MASK            (0x20000U)
+#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT           (17U)
+#define SYSCON_PDRUNCFG_PDEN_ROM(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK           (0x80000U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT          (19U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK        (0x100000U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT       (20U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK       (0x200000U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT      (21U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK        (0x400000U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT       (22U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK          (0x800000U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT         (23U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD3_MASK            (0x4000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT           (26U)
+#define SYSCON_PDRUNCFG_PDEN_VD3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD4_MASK            (0x8000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT           (27U)
+#define SYSCON_PDRUNCFG_PDEN_VD4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD5_MASK            (0x10000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT           (28U)
+#define SYSCON_PDRUNCFG_PDEN_VD5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD6_MASK            (0x20000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT           (29U)
+#define SYSCON_PDRUNCFG_PDEN_VD6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFG */
+#define SYSCON_PDRUNCFG_COUNT                    (2U)
+
+/*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK    (0x1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT   (0U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK    (0x2U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT   (1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK     (0x4U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT    (2U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK      (0x8U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT     (3U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK         (0x10U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT        (4U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK      (0x20U)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT     (5U)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK          (0x40U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT         (6U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK     (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT    (7U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK         (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT        (7U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK    (0x100U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT   (8U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK     (0x200U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT    (9U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK        (0x400U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT       (10U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK       (0x2000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT      (13U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK       (0x4000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT      (14U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK   (0x8000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT  (15U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK     (0x10000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT    (16U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK         (0x20000U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT        (17U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK        (0x80000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT       (19U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK     (0x100000U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT    (20U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK    (0x200000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT   (21U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK     (0x400000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT    (22U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK       (0x800000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT      (23U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK         (0x4000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT        (26U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK         (0x8000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT        (27U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK         (0x10000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT        (28U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK         (0x20000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT        (29U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFGSET */
+#define SYSCON_PDRUNCFGSET_COUNT                 (2U)
+
+/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK    (0x1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT   (0U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK    (0x2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT   (1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK     (0x4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT    (2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK      (0x8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT     (3U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK         (0x10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT        (4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK      (0x20U)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT     (5U)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK          (0x40U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT         (6U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK     (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT    (7U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK         (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT        (7U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK    (0x100U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT   (8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK     (0x200U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT    (9U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK        (0x400U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT       (10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK       (0x2000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT      (13U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK       (0x4000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT      (14U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK   (0x8000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT  (15U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK     (0x10000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT    (16U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK         (0x20000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT        (17U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK        (0x80000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT       (19U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK     (0x100000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT    (20U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK    (0x200000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT   (21U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK     (0x400000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT    (22U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK       (0x800000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT      (23U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK         (0x4000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT        (26U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK         (0x8000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT        (27U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK         (0x10000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT        (28U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK         (0x20000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT        (29U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFGCLR */
+#define SYSCON_PDRUNCFGCLR_COUNT                 (2U)
+
+/*! @name STARTER - Start logic 0 wake-up enable register */
+#define SYSCON_STARTER_WDT_BOD_MASK              (0x1U)
+#define SYSCON_STARTER_WDT_BOD_SHIFT             (0U)
+#define SYSCON_STARTER_WDT_BOD(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
+#define SYSCON_STARTER_PINT4_MASK                (0x1U)
+#define SYSCON_STARTER_PINT4_SHIFT               (0U)
+#define SYSCON_STARTER_PINT4(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
+#define SYSCON_STARTER_PINT5_MASK                (0x2U)
+#define SYSCON_STARTER_PINT5_SHIFT               (1U)
+#define SYSCON_STARTER_PINT5(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
+#define SYSCON_STARTER_DMA_MASK                  (0x2U)
+#define SYSCON_STARTER_DMA_SHIFT                 (1U)
+#define SYSCON_STARTER_DMA(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
+#define SYSCON_STARTER_GINT0_MASK                (0x4U)
+#define SYSCON_STARTER_GINT0_SHIFT               (2U)
+#define SYSCON_STARTER_GINT0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
+#define SYSCON_STARTER_PINT6_MASK                (0x4U)
+#define SYSCON_STARTER_PINT6_SHIFT               (2U)
+#define SYSCON_STARTER_PINT6(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
+#define SYSCON_STARTER_GINT1_MASK                (0x8U)
+#define SYSCON_STARTER_GINT1_SHIFT               (3U)
+#define SYSCON_STARTER_GINT1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
+#define SYSCON_STARTER_PINT7_MASK                (0x8U)
+#define SYSCON_STARTER_PINT7_SHIFT               (3U)
+#define SYSCON_STARTER_PINT7(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
+#define SYSCON_STARTER_CTIMER2_MASK              (0x10U)
+#define SYSCON_STARTER_CTIMER2_SHIFT             (4U)
+#define SYSCON_STARTER_CTIMER2(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)
+#define SYSCON_STARTER_PIN_INT0_MASK             (0x10U)
+#define SYSCON_STARTER_PIN_INT0_SHIFT            (4U)
+#define SYSCON_STARTER_PIN_INT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
+#define SYSCON_STARTER_CTIMER4_MASK              (0x20U)
+#define SYSCON_STARTER_CTIMER4_SHIFT             (5U)
+#define SYSCON_STARTER_CTIMER4(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)
+#define SYSCON_STARTER_PIN_INT1_MASK             (0x20U)
+#define SYSCON_STARTER_PIN_INT1_SHIFT            (5U)
+#define SYSCON_STARTER_PIN_INT1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
+#define SYSCON_STARTER_PIN_INT2_MASK             (0x40U)
+#define SYSCON_STARTER_PIN_INT2_SHIFT            (6U)
+#define SYSCON_STARTER_PIN_INT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
+#define SYSCON_STARTER_PIN_INT3_MASK             (0x80U)
+#define SYSCON_STARTER_PIN_INT3_SHIFT            (7U)
+#define SYSCON_STARTER_PIN_INT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
+#define SYSCON_STARTER_SPIFI_MASK                (0x80U)
+#define SYSCON_STARTER_SPIFI_SHIFT               (7U)
+#define SYSCON_STARTER_SPIFI(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK)
+#define SYSCON_STARTER_FLEXCOMM8_MASK            (0x100U)
+#define SYSCON_STARTER_FLEXCOMM8_SHIFT           (8U)
+#define SYSCON_STARTER_FLEXCOMM8(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
+#define SYSCON_STARTER_UTICK_MASK                (0x100U)
+#define SYSCON_STARTER_UTICK_SHIFT               (8U)
+#define SYSCON_STARTER_UTICK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
+#define SYSCON_STARTER_MRT_MASK                  (0x200U)
+#define SYSCON_STARTER_MRT_SHIFT                 (9U)
+#define SYSCON_STARTER_MRT(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK)
+#define SYSCON_STARTER_FLEXCOMM9_MASK            (0x200U)
+#define SYSCON_STARTER_FLEXCOMM9_SHIFT           (9U)
+#define SYSCON_STARTER_FLEXCOMM9(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
+#define SYSCON_STARTER_CTIMER0_MASK              (0x400U)
+#define SYSCON_STARTER_CTIMER0_SHIFT             (10U)
+#define SYSCON_STARTER_CTIMER0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)
+#define SYSCON_STARTER_CTIMER1_MASK              (0x800U)
+#define SYSCON_STARTER_CTIMER1_SHIFT             (11U)
+#define SYSCON_STARTER_CTIMER1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)
+#define SYSCON_STARTER_SCT0_MASK                 (0x1000U)
+#define SYSCON_STARTER_SCT0_SHIFT                (12U)
+#define SYSCON_STARTER_SCT0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)
+#define SYSCON_STARTER_CTIMER3_MASK              (0x2000U)
+#define SYSCON_STARTER_CTIMER3_SHIFT             (13U)
+#define SYSCON_STARTER_CTIMER3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)
+#define SYSCON_STARTER_FLEXCOMM0_MASK            (0x4000U)
+#define SYSCON_STARTER_FLEXCOMM0_SHIFT           (14U)
+#define SYSCON_STARTER_FLEXCOMM0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
+#define SYSCON_STARTER_FLEXCOMM1_MASK            (0x8000U)
+#define SYSCON_STARTER_FLEXCOMM1_SHIFT           (15U)
+#define SYSCON_STARTER_FLEXCOMM1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
+#define SYSCON_STARTER_USB1_MASK                 (0x8000U)
+#define SYSCON_STARTER_USB1_SHIFT                (15U)
+#define SYSCON_STARTER_USB1(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
+#define SYSCON_STARTER_FLEXCOMM2_MASK            (0x10000U)
+#define SYSCON_STARTER_FLEXCOMM2_SHIFT           (16U)
+#define SYSCON_STARTER_FLEXCOMM2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
+#define SYSCON_STARTER_USB1_ACT_MASK             (0x10000U)
+#define SYSCON_STARTER_USB1_ACT_SHIFT            (16U)
+#define SYSCON_STARTER_USB1_ACT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
+#define SYSCON_STARTER_ENET_INT1_MASK            (0x20000U)
+#define SYSCON_STARTER_ENET_INT1_SHIFT           (17U)
+#define SYSCON_STARTER_ENET_INT1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK)
+#define SYSCON_STARTER_FLEXCOMM3_MASK            (0x20000U)
+#define SYSCON_STARTER_FLEXCOMM3_SHIFT           (17U)
+#define SYSCON_STARTER_FLEXCOMM3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
+#define SYSCON_STARTER_ENET_INT2_MASK            (0x40000U)
+#define SYSCON_STARTER_ENET_INT2_SHIFT           (18U)
+#define SYSCON_STARTER_ENET_INT2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK)
+#define SYSCON_STARTER_FLEXCOMM4_MASK            (0x40000U)
+#define SYSCON_STARTER_FLEXCOMM4_SHIFT           (18U)
+#define SYSCON_STARTER_FLEXCOMM4(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
+#define SYSCON_STARTER_ENET_INT0_MASK            (0x80000U)
+#define SYSCON_STARTER_ENET_INT0_SHIFT           (19U)
+#define SYSCON_STARTER_ENET_INT0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK)
+#define SYSCON_STARTER_FLEXCOMM5_MASK            (0x80000U)
+#define SYSCON_STARTER_FLEXCOMM5_SHIFT           (19U)
+#define SYSCON_STARTER_FLEXCOMM5(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
+#define SYSCON_STARTER_FLEXCOMM6_MASK            (0x100000U)
+#define SYSCON_STARTER_FLEXCOMM6_SHIFT           (20U)
+#define SYSCON_STARTER_FLEXCOMM6(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
+#define SYSCON_STARTER_FLEXCOMM7_MASK            (0x200000U)
+#define SYSCON_STARTER_FLEXCOMM7_SHIFT           (21U)
+#define SYSCON_STARTER_FLEXCOMM7(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
+#define SYSCON_STARTER_ADC0_SEQA_MASK            (0x400000U)
+#define SYSCON_STARTER_ADC0_SEQA_SHIFT           (22U)
+#define SYSCON_STARTER_ADC0_SEQA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK)
+#define SYSCON_STARTER_SMARTCARD0_MASK           (0x800000U)
+#define SYSCON_STARTER_SMARTCARD0_SHIFT          (23U)
+#define SYSCON_STARTER_SMARTCARD0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK)
+#define SYSCON_STARTER_ADC0_SEQB_MASK            (0x800000U)
+#define SYSCON_STARTER_ADC0_SEQB_SHIFT           (23U)
+#define SYSCON_STARTER_ADC0_SEQB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK)
+#define SYSCON_STARTER_ADC0_THCMP_MASK           (0x1000000U)
+#define SYSCON_STARTER_ADC0_THCMP_SHIFT          (24U)
+#define SYSCON_STARTER_ADC0_THCMP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK)
+#define SYSCON_STARTER_SMARTCARD1_MASK           (0x1000000U)
+#define SYSCON_STARTER_SMARTCARD1_SHIFT          (24U)
+#define SYSCON_STARTER_SMARTCARD1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK)
+#define SYSCON_STARTER_DMIC_MASK                 (0x2000000U)
+#define SYSCON_STARTER_DMIC_SHIFT                (25U)
+#define SYSCON_STARTER_DMIC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
+#define SYSCON_STARTER_HWVAD_MASK                (0x4000000U)
+#define SYSCON_STARTER_HWVAD_SHIFT               (26U)
+#define SYSCON_STARTER_HWVAD(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
+#define SYSCON_STARTER_USB0_NEEDCLK_MASK         (0x8000000U)
+#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT        (27U)
+#define SYSCON_STARTER_USB0_NEEDCLK(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
+#define SYSCON_STARTER_USB0_MASK                 (0x10000000U)
+#define SYSCON_STARTER_USB0_SHIFT                (28U)
+#define SYSCON_STARTER_USB0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
+#define SYSCON_STARTER_RTC_MASK                  (0x20000000U)
+#define SYSCON_STARTER_RTC_SHIFT                 (29U)
+#define SYSCON_STARTER_RTC(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
+
+/* The count of SYSCON_STARTER */
+#define SYSCON_STARTER_COUNT                     (2U)
+
+/*! @name STARTERSET - Set bits in STARTER */
+#define SYSCON_STARTERSET_START_SET_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERSET_START_SET_SHIFT        (0U)
+#define SYSCON_STARTERSET_START_SET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
+
+/* The count of SYSCON_STARTERSET */
+#define SYSCON_STARTERSET_COUNT                  (2U)
+
+/*! @name STARTERCLR - Clear bits in STARTER0 */
+#define SYSCON_STARTERCLR_START_CLR_MASK         (0xFFFFFFFFU)
+#define SYSCON_STARTERCLR_START_CLR_SHIFT        (0U)
+#define SYSCON_STARTERCLR_START_CLR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
+
+/* The count of SYSCON_STARTERCLR */
+#define SYSCON_STARTERCLR_COUNT                  (2U)
+
+/*! @name HWWAKE - Configures special cases of hardware wake-up */
+#define SYSCON_HWWAKE_FORCEWAKE_MASK             (0x1U)
+#define SYSCON_HWWAKE_FORCEWAKE_SHIFT            (0U)
+#define SYSCON_HWWAKE_FORCEWAKE(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
+#define SYSCON_HWWAKE_FCWAKE_MASK                (0x2U)
+#define SYSCON_HWWAKE_FCWAKE_SHIFT               (1U)
+#define SYSCON_HWWAKE_FCWAKE(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
+#define SYSCON_HWWAKE_WAKEDMIC_MASK              (0x4U)
+#define SYSCON_HWWAKE_WAKEDMIC_SHIFT             (2U)
+#define SYSCON_HWWAKE_WAKEDMIC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
+#define SYSCON_HWWAKE_WAKEDMA_MASK               (0x8U)
+#define SYSCON_HWWAKE_WAKEDMA_SHIFT              (3U)
+#define SYSCON_HWWAKE_WAKEDMA(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
+
+/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
+#define SYSCON_AUTOCGOR_RAM0X_MASK               (0x2U)
+#define SYSCON_AUTOCGOR_RAM0X_SHIFT              (1U)
+#define SYSCON_AUTOCGOR_RAM0X(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
+#define SYSCON_AUTOCGOR_RAM1_MASK                (0x4U)
+#define SYSCON_AUTOCGOR_RAM1_SHIFT               (2U)
+#define SYSCON_AUTOCGOR_RAM1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
+#define SYSCON_AUTOCGOR_RAM2_MASK                (0x8U)
+#define SYSCON_AUTOCGOR_RAM2_SHIFT               (3U)
+#define SYSCON_AUTOCGOR_RAM2(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
+#define SYSCON_AUTOCGOR_RAM3_MASK                (0x10U)
+#define SYSCON_AUTOCGOR_RAM3_SHIFT               (4U)
+#define SYSCON_AUTOCGOR_RAM3(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
+
+/*! @name JTAGIDCODE - JTAG ID code register */
+#define SYSCON_JTAGIDCODE_JTAGID_MASK            (0xFFFFFFFFU)
+#define SYSCON_JTAGIDCODE_JTAGID_SHIFT           (0U)
+#define SYSCON_JTAGIDCODE_JTAGID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
+
+/*! @name DEVICE_ID0 - Part ID register */
+#define SYSCON_DEVICE_ID0_PARTID_MASK            (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID0_PARTID_SHIFT           (0U)
+#define SYSCON_DEVICE_ID0_PARTID(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
+
+/*! @name DEVICE_ID1 - Boot ROM and die revision register */
+#define SYSCON_DEVICE_ID1_REVID_MASK             (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID1_REVID_SHIFT            (0U)
+#define SYSCON_DEVICE_ID1_REVID(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
+
+/*! @name BODCTRL - Brown-Out Detect control */
+#define SYSCON_BODCTRL_BODRSTLEV_MASK            (0x3U)
+#define SYSCON_BODCTRL_BODRSTLEV_SHIFT           (0U)
+#define SYSCON_BODCTRL_BODRSTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
+#define SYSCON_BODCTRL_BODRSTENA_MASK            (0x4U)
+#define SYSCON_BODCTRL_BODRSTENA_SHIFT           (2U)
+#define SYSCON_BODCTRL_BODRSTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
+#define SYSCON_BODCTRL_BODINTLEV_MASK            (0x18U)
+#define SYSCON_BODCTRL_BODINTLEV_SHIFT           (3U)
+#define SYSCON_BODCTRL_BODINTLEV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
+#define SYSCON_BODCTRL_BODINTENA_MASK            (0x20U)
+#define SYSCON_BODCTRL_BODINTENA_SHIFT           (5U)
+#define SYSCON_BODCTRL_BODINTENA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
+#define SYSCON_BODCTRL_BODRSTSTAT_MASK           (0x40U)
+#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT          (6U)
+#define SYSCON_BODCTRL_BODRSTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
+#define SYSCON_BODCTRL_BODINTSTAT_MASK           (0x80U)
+#define SYSCON_BODCTRL_BODINTSTAT_SHIFT          (7U)
+#define SYSCON_BODCTRL_BODINTSTAT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Register_Masks */
+
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE                              (0x40000000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS                         { SYSCON }
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CFG;                               /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
+  __IO uint32_t CTL;                               /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
+  __IO uint32_t STAT;                              /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
+  __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
+  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t BRG;                               /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
+  __I  uint32_t INTSTAT;                           /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
+  __IO uint32_t OSR;                               /**< Oversample selection register for asynchronous communication., offset: 0x28 */
+  __IO uint32_t ADDR;                              /**< Address register for automatic address matching., offset: 0x2C */
+       uint8_t RESERVED_1[3536];
+  __IO uint32_t FIFOCFG;                           /**< FIFO configuration and enable register., offset: 0xE00 */
+  __IO uint32_t FIFOSTAT;                          /**< FIFO status register., offset: 0xE04 */
+  __IO uint32_t FIFOTRIG;                          /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t FIFOINTENSET;                      /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+  __IO uint32_t FIFOINTENCLR;                      /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+  __I  uint32_t FIFOINTSTAT;                       /**< FIFO interrupt status register., offset: 0xE18 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FIFOWR;                            /**< FIFO write data., offset: 0xE20 */
+       uint8_t RESERVED_4[12];
+  __I  uint32_t FIFORD;                            /**< FIFO read data., offset: 0xE30 */
+       uint8_t RESERVED_5[12];
+  __I  uint32_t FIFORDNOPOP;                       /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+       uint8_t RESERVED_6[440];
+  __I  uint32_t ID;                                /**< Peripheral identification register., offset: 0xFFC */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
+#define USART_CFG_ENABLE_MASK                    (0x1U)
+#define USART_CFG_ENABLE_SHIFT                   (0U)
+#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+#define USART_CFG_DATALEN_MASK                   (0xCU)
+#define USART_CFG_DATALEN_SHIFT                  (2U)
+#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+#define USART_CFG_PARITYSEL_MASK                 (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT                (4U)
+#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+#define USART_CFG_STOPLEN_MASK                   (0x40U)
+#define USART_CFG_STOPLEN_SHIFT                  (6U)
+#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+#define USART_CFG_MODE32K_MASK                   (0x80U)
+#define USART_CFG_MODE32K_SHIFT                  (7U)
+#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+#define USART_CFG_LINMODE_MASK                   (0x100U)
+#define USART_CFG_LINMODE_SHIFT                  (8U)
+#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+#define USART_CFG_CTSEN_MASK                     (0x200U)
+#define USART_CFG_CTSEN_SHIFT                    (9U)
+#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+#define USART_CFG_SYNCEN_MASK                    (0x800U)
+#define USART_CFG_SYNCEN_SHIFT                   (11U)
+#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+#define USART_CFG_CLKPOL_MASK                    (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT                   (12U)
+#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+#define USART_CFG_SYNCMST_MASK                   (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT                  (14U)
+#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+#define USART_CFG_LOOP_MASK                      (0x8000U)
+#define USART_CFG_LOOP_SHIFT                     (15U)
+#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+#define USART_CFG_OETA_MASK                      (0x40000U)
+#define USART_CFG_OETA_SHIFT                     (18U)
+#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT                 (19U)
+#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+#define USART_CFG_OESEL_MASK                     (0x100000U)
+#define USART_CFG_OESEL_SHIFT                    (20U)
+#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+#define USART_CFG_OEPOL_MASK                     (0x200000U)
+#define USART_CFG_OEPOL_SHIFT                    (21U)
+#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+#define USART_CFG_RXPOL_MASK                     (0x400000U)
+#define USART_CFG_RXPOL_SHIFT                    (22U)
+#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+#define USART_CFG_TXPOL_MASK                     (0x800000U)
+#define USART_CFG_TXPOL_SHIFT                    (23U)
+#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
+#define USART_CTL_TXBRKEN_MASK                   (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT                  (1U)
+#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+#define USART_CTL_ADDRDET_MASK                   (0x4U)
+#define USART_CTL_ADDRDET_SHIFT                  (2U)
+#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+#define USART_CTL_TXDIS_MASK                     (0x40U)
+#define USART_CTL_TXDIS_SHIFT                    (6U)
+#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+#define USART_CTL_CC_MASK                        (0x100U)
+#define USART_CTL_CC_SHIFT                       (8U)
+#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT                (9U)
+#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
+#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
+#define USART_STAT_RXIDLE_MASK                   (0x2U)
+#define USART_STAT_RXIDLE_SHIFT                  (1U)
+#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+#define USART_STAT_TXIDLE_MASK                   (0x8U)
+#define USART_STAT_TXIDLE_SHIFT                  (3U)
+#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+#define USART_STAT_CTS_MASK                      (0x10U)
+#define USART_STAT_CTS_SHIFT                     (4U)
+#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+#define USART_STAT_DELTACTS_MASK                 (0x20U)
+#define USART_STAT_DELTACTS_SHIFT                (5U)
+#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+#define USART_STAT_TXDISSTAT_MASK                (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT               (6U)
+#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+#define USART_STAT_RXBRK_MASK                    (0x400U)
+#define USART_STAT_RXBRK_SHIFT                   (10U)
+#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+#define USART_STAT_DELTARXBRK_MASK               (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT              (11U)
+#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+#define USART_STAT_START_MASK                    (0x1000U)
+#define USART_STAT_START_SHIFT                   (12U)
+#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT              (13U)
+#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT            (14U)
+#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT              (15U)
+#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+#define USART_STAT_ABERR_MASK                    (0x10000U)
+#define USART_STAT_ABERR_SHIFT                   (16U)
+#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
+#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
+#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+#define USART_INTENSET_TXDISEN_MASK              (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT             (6U)
+#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
+#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+#define USART_INTENSET_STARTEN_MASK              (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT             (12U)
+#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
+#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
+#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
+#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+#define USART_INTENSET_ABERREN_MASK              (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT             (16U)
+#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
+#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
+#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
+#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
+#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
+#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
+#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
+#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
+#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
+#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
+#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
+#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT                   (0U)
+#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
+#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
+#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
+#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
+#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
+#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+#define USART_INTSTAT_START_MASK                 (0x1000U)
+#define USART_INTSTAT_START_SHIFT                (12U)
+#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
+#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
+#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
+#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
+#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+
+/*! @name OSR - Oversample selection register for asynchronous communication. */
+#define USART_OSR_OSRVAL_MASK                    (0xFU)
+#define USART_OSR_OSRVAL_SHIFT                   (0U)
+#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+
+/*! @name ADDR - Address register for automatic address matching. */
+#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT                 (0U)
+#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
+#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
+#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
+#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT                (12U)
+#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT                (13U)
+#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
+#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
+#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
+#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
+#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+#define USART_FIFOCFG_POPDBG_MASK                (0x40000U)
+#define USART_FIFOCFG_POPDBG_SHIFT               (18U)
+#define USART_FIFOCFG_POPDBG(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
+#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
+#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
+#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
+#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
+#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
+#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
+#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
+#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
+#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
+#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
+#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
+#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
+#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
+#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
+#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
+#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
+#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
+#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
+#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
+#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
+#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
+#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
+#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
+#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
+#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
+#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT                (0U)
+#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT                (0U)
+#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT               (13U)
+#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT             (14U)
+#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT               (15U)
+#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
+#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
+#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
+#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
+#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define USART_ID_APERTURE_MASK                   (0xFFU)
+#define USART_ID_APERTURE_SHIFT                  (0U)
+#define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+#define USART_ID_MINOR_REV_MASK                  (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT                 (8U)
+#define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+#define USART_ID_MAJOR_REV_MASK                  (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT                 (12U)
+#define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+#define USART_ID_ID_MASK                         (0xFFFF0000U)
+#define USART_ID_ID_SHIFT                        (16U)
+#define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+/** Peripheral USART0 base address */
+#define USART0_BASE                              (0x40086000u)
+/** Peripheral USART0 base pointer */
+#define USART0                                   ((USART_Type *)USART0_BASE)
+/** Peripheral USART1 base address */
+#define USART1_BASE                              (0x40087000u)
+/** Peripheral USART1 base pointer */
+#define USART1                                   ((USART_Type *)USART1_BASE)
+/** Peripheral USART2 base address */
+#define USART2_BASE                              (0x40088000u)
+/** Peripheral USART2 base pointer */
+#define USART2                                   ((USART_Type *)USART2_BASE)
+/** Peripheral USART3 base address */
+#define USART3_BASE                              (0x40089000u)
+/** Peripheral USART3 base pointer */
+#define USART3                                   ((USART_Type *)USART3_BASE)
+/** Peripheral USART4 base address */
+#define USART4_BASE                              (0x4008A000u)
+/** Peripheral USART4 base pointer */
+#define USART4                                   ((USART_Type *)USART4_BASE)
+/** Peripheral USART5 base address */
+#define USART5_BASE                              (0x40096000u)
+/** Peripheral USART5 base pointer */
+#define USART5                                   ((USART_Type *)USART5_BASE)
+/** Peripheral USART6 base address */
+#define USART6_BASE                              (0x40097000u)
+/** Peripheral USART6 base pointer */
+#define USART6                                   ((USART_Type *)USART6_BASE)
+/** Peripheral USART7 base address */
+#define USART7_BASE                              (0x40098000u)
+/** Peripheral USART7 base pointer */
+#define USART7                                   ((USART_Type *)USART7_BASE)
+/** Peripheral USART8 base address */
+#define USART8_BASE                              (0x40099000u)
+/** Peripheral USART8 base pointer */
+#define USART8                                   ((USART_Type *)USART8_BASE)
+/** Peripheral USART9 base address */
+#define USART9_BASE                              (0x4009A000u)
+/** Peripheral USART9 base pointer */
+#define USART9                                   ((USART_Type *)USART9_BASE)
+/** Array initializer of USART peripheral base addresses */
+#define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
+/** Array initializer of USART peripheral base pointers */
+#define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
+  __IO uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
+  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
+  __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
+  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
+  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
+  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
+  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
+  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
+  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK             (0x7FU)
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT            (0U)
+#define USB_DEVCMDSTAT_DEV_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USB_DEVCMDSTAT_DEV_EN_MASK               (0x80U)
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT              (7U)
+#define USB_DEVCMDSTAT_DEV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
+#define USB_DEVCMDSTAT_SETUP_MASK                (0x100U)
+#define USB_DEVCMDSTAT_SETUP_SHIFT               (8U)
+#define USB_DEVCMDSTAT_SETUP(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK        (0x200U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT       (9U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USB_DEVCMDSTAT_LPM_SUP_MASK              (0x800U)
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT             (11U)
+#define USB_DEVCMDSTAT_LPM_SUP(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK          (0x1000U)
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT         (12U)
+#define USB_DEVCMDSTAT_INTONNAK_AO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK          (0x2000U)
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT         (13U)
+#define USB_DEVCMDSTAT_INTONNAK_AI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK          (0x4000U)
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT         (14U)
+#define USB_DEVCMDSTAT_INTONNAK_CO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK          (0x8000U)
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT         (15U)
+#define USB_DEVCMDSTAT_INTONNAK_CI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USB_DEVCMDSTAT_DCON_MASK                 (0x10000U)
+#define USB_DEVCMDSTAT_DCON_SHIFT                (16U)
+#define USB_DEVCMDSTAT_DCON(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
+#define USB_DEVCMDSTAT_DSUS_MASK                 (0x20000U)
+#define USB_DEVCMDSTAT_DSUS_SHIFT                (17U)
+#define USB_DEVCMDSTAT_DSUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
+#define USB_DEVCMDSTAT_LPM_SUS_MASK              (0x80000U)
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT             (19U)
+#define USB_DEVCMDSTAT_LPM_SUS(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
+#define USB_DEVCMDSTAT_LPM_REWP_MASK             (0x100000U)
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT            (20U)
+#define USB_DEVCMDSTAT_LPM_REWP(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
+#define USB_DEVCMDSTAT_DCON_C_MASK               (0x1000000U)
+#define USB_DEVCMDSTAT_DCON_C_SHIFT              (24U)
+#define USB_DEVCMDSTAT_DCON_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
+#define USB_DEVCMDSTAT_DSUS_C_MASK               (0x2000000U)
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT              (25U)
+#define USB_DEVCMDSTAT_DSUS_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
+#define USB_DEVCMDSTAT_DRES_C_MASK               (0x4000000U)
+#define USB_DEVCMDSTAT_DRES_C_SHIFT              (26U)
+#define USB_DEVCMDSTAT_DRES_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK        (0x10000000U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT       (28U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
+
+/*! @name INFO - USB Info register */
+#define USB_INFO_FRAME_NR_MASK                   (0x7FFU)
+#define USB_INFO_FRAME_NR_SHIFT                  (0U)
+#define USB_INFO_FRAME_NR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
+#define USB_INFO_ERR_CODE_MASK                   (0x7800U)
+#define USB_INFO_ERR_CODE_SHIFT                  (11U)
+#define USB_INFO_ERR_CODE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
+#define USB_INFO_MINREV_MASK                     (0xFF0000U)
+#define USB_INFO_MINREV_SHIFT                    (16U)
+#define USB_INFO_MINREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
+#define USB_INFO_MAJREV_MASK                     (0xFF000000U)
+#define USB_INFO_MAJREV_SHIFT                    (24U)
+#define USB_INFO_MAJREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+#define USB_EPLISTSTART_EP_LIST_MASK             (0xFFFFFF00U)
+#define USB_EPLISTSTART_EP_LIST_SHIFT            (8U)
+#define USB_EPLISTSTART_EP_LIST(x)               (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+#define USB_DATABUFSTART_DA_BUF_MASK             (0xFFC00000U)
+#define USB_DATABUFSTART_DA_BUF_SHIFT            (22U)
+#define USB_DATABUFSTART_DA_BUF(x)               (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
+
+/*! @name LPM - USB Link Power Management register */
+#define USB_LPM_HIRD_HW_MASK                     (0xFU)
+#define USB_LPM_HIRD_HW_SHIFT                    (0U)
+#define USB_LPM_HIRD_HW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
+#define USB_LPM_HIRD_SW_MASK                     (0xF0U)
+#define USB_LPM_HIRD_SW_SHIFT                    (4U)
+#define USB_LPM_HIRD_SW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
+#define USB_LPM_DATA_PENDING_MASK                (0x100U)
+#define USB_LPM_DATA_PENDING_SHIFT               (8U)
+#define USB_LPM_DATA_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
+
+/*! @name EPSKIP - USB Endpoint skip */
+#define USB_EPSKIP_SKIP_MASK                     (0x3FFU)
+#define USB_EPSKIP_SKIP_SHIFT                    (0U)
+#define USB_EPSKIP_SKIP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+#define USB_EPINUSE_BUF_MASK                     (0x3FCU)
+#define USB_EPINUSE_BUF_SHIFT                    (2U)
+#define USB_EPINUSE_BUF(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+#define USB_EPBUFCFG_BUF_SB_MASK                 (0x3FCU)
+#define USB_EPBUFCFG_BUF_SB_SHIFT                (2U)
+#define USB_EPBUFCFG_BUF_SB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
+
+/*! @name INTSTAT - USB interrupt status register */
+#define USB_INTSTAT_EP0OUT_MASK                  (0x1U)
+#define USB_INTSTAT_EP0OUT_SHIFT                 (0U)
+#define USB_INTSTAT_EP0OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
+#define USB_INTSTAT_EP0IN_MASK                   (0x2U)
+#define USB_INTSTAT_EP0IN_SHIFT                  (1U)
+#define USB_INTSTAT_EP0IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
+#define USB_INTSTAT_EP1OUT_MASK                  (0x4U)
+#define USB_INTSTAT_EP1OUT_SHIFT                 (2U)
+#define USB_INTSTAT_EP1OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
+#define USB_INTSTAT_EP1IN_MASK                   (0x8U)
+#define USB_INTSTAT_EP1IN_SHIFT                  (3U)
+#define USB_INTSTAT_EP1IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
+#define USB_INTSTAT_EP2OUT_MASK                  (0x10U)
+#define USB_INTSTAT_EP2OUT_SHIFT                 (4U)
+#define USB_INTSTAT_EP2OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
+#define USB_INTSTAT_EP2IN_MASK                   (0x20U)
+#define USB_INTSTAT_EP2IN_SHIFT                  (5U)
+#define USB_INTSTAT_EP2IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
+#define USB_INTSTAT_EP3OUT_MASK                  (0x40U)
+#define USB_INTSTAT_EP3OUT_SHIFT                 (6U)
+#define USB_INTSTAT_EP3OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
+#define USB_INTSTAT_EP3IN_MASK                   (0x80U)
+#define USB_INTSTAT_EP3IN_SHIFT                  (7U)
+#define USB_INTSTAT_EP3IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
+#define USB_INTSTAT_EP4OUT_MASK                  (0x100U)
+#define USB_INTSTAT_EP4OUT_SHIFT                 (8U)
+#define USB_INTSTAT_EP4OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
+#define USB_INTSTAT_EP4IN_MASK                   (0x200U)
+#define USB_INTSTAT_EP4IN_SHIFT                  (9U)
+#define USB_INTSTAT_EP4IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
+#define USB_INTSTAT_FRAME_INT_MASK               (0x40000000U)
+#define USB_INTSTAT_FRAME_INT_SHIFT              (30U)
+#define USB_INTSTAT_FRAME_INT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
+#define USB_INTSTAT_DEV_INT_MASK                 (0x80000000U)
+#define USB_INTSTAT_DEV_INT_SHIFT                (31U)
+#define USB_INTSTAT_DEV_INT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
+
+/*! @name INTEN - USB interrupt enable register */
+#define USB_INTEN_EP_INT_EN_MASK                 (0x3FFU)
+#define USB_INTEN_EP_INT_EN_SHIFT                (0U)
+#define USB_INTEN_EP_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
+#define USB_INTEN_FRAME_INT_EN_MASK              (0x40000000U)
+#define USB_INTEN_FRAME_INT_EN_SHIFT             (30U)
+#define USB_INTEN_FRAME_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
+#define USB_INTEN_DEV_INT_EN_MASK                (0x80000000U)
+#define USB_INTEN_DEV_INT_EN_SHIFT               (31U)
+#define USB_INTEN_DEV_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+#define USB_INTSETSTAT_EP_SET_INT_MASK           (0x3FFU)
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT          (0U)
+#define USB_INTSETSTAT_EP_SET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK        (0x40000000U)
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT       (30U)
+#define USB_INTSETSTAT_FRAME_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USB_INTSETSTAT_DEV_SET_INT_MASK          (0x80000000U)
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT         (31U)
+#define USB_INTSETSTAT_DEV_SET_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+#define USB_EPTOGGLE_TOGGLE_MASK                 (0x3FFU)
+#define USB_EPTOGGLE_TOGGLE_SHIFT                (0U)
+#define USB_EPTOGGLE_TOGGLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40084000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+#define USB_NEEDCLK_IRQS                         { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBFSH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBFSH - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t HCREVISION;                        /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
+  __IO uint32_t HCCONTROL;                         /**< Defines the operating modes of the HC, offset: 0x4 */
+  __IO uint32_t HCCOMMANDSTATUS;                   /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
+  __IO uint32_t HCINTERRUPTSTATUS;                 /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
+  __IO uint32_t HCINTERRUPTENABLE;                 /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
+  __IO uint32_t HCINTERRUPTDISABLE;                /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
+  __IO uint32_t HCHCCA;                            /**< Contains the physical address of the host controller communication area, offset: 0x18 */
+  __IO uint32_t HCPERIODCURRENTED;                 /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
+  __IO uint32_t HCCONTROLHEADED;                   /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
+  __IO uint32_t HCCONTROLCURRENTED;                /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
+  __IO uint32_t HCBULKHEADED;                      /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
+  __IO uint32_t HCBULKCURRENTED;                   /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
+  __IO uint32_t HCDONEHEAD;                        /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
+  __IO uint32_t HCFMINTERVAL;                      /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
+  __IO uint32_t HCFMREMAINING;                     /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
+  __IO uint32_t HCFMNUMBER;                        /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
+  __IO uint32_t HCPERIODICSTART;                   /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
+  __IO uint32_t HCLSTHRESHOLD;                     /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
+  __IO uint32_t HCRHDESCRIPTORA;                   /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
+  __IO uint32_t HCRHDESCRIPTORB;                   /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
+  __IO uint32_t HCRHSTATUS;                        /**< This register is divided into two parts, offset: 0x50 */
+  __IO uint32_t HCRHPORTSTATUS;                    /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
+} USBFSH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBFSH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
+ * @{
+ */
+
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
+#define USBFSH_HCREVISION_REV_MASK               (0xFFU)
+#define USBFSH_HCREVISION_REV_SHIFT              (0U)
+#define USBFSH_HCREVISION_REV(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
+
+/*! @name HCCONTROL - Defines the operating modes of the HC */
+#define USBFSH_HCCONTROL_CBSR_MASK               (0x3U)
+#define USBFSH_HCCONTROL_CBSR_SHIFT              (0U)
+#define USBFSH_HCCONTROL_CBSR(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
+#define USBFSH_HCCONTROL_PLE_MASK                (0x4U)
+#define USBFSH_HCCONTROL_PLE_SHIFT               (2U)
+#define USBFSH_HCCONTROL_PLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
+#define USBFSH_HCCONTROL_IE_MASK                 (0x8U)
+#define USBFSH_HCCONTROL_IE_SHIFT                (3U)
+#define USBFSH_HCCONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
+#define USBFSH_HCCONTROL_CLE_MASK                (0x10U)
+#define USBFSH_HCCONTROL_CLE_SHIFT               (4U)
+#define USBFSH_HCCONTROL_CLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
+#define USBFSH_HCCONTROL_BLE_MASK                (0x20U)
+#define USBFSH_HCCONTROL_BLE_SHIFT               (5U)
+#define USBFSH_HCCONTROL_BLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
+#define USBFSH_HCCONTROL_HCFS_MASK               (0xC0U)
+#define USBFSH_HCCONTROL_HCFS_SHIFT              (6U)
+#define USBFSH_HCCONTROL_HCFS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
+#define USBFSH_HCCONTROL_IR_MASK                 (0x100U)
+#define USBFSH_HCCONTROL_IR_SHIFT                (8U)
+#define USBFSH_HCCONTROL_IR(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
+#define USBFSH_HCCONTROL_RWC_MASK                (0x200U)
+#define USBFSH_HCCONTROL_RWC_SHIFT               (9U)
+#define USBFSH_HCCONTROL_RWC(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
+#define USBFSH_HCCONTROL_RWE_MASK                (0x400U)
+#define USBFSH_HCCONTROL_RWE_SHIFT               (10U)
+#define USBFSH_HCCONTROL_RWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
+
+/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK          (0x1U)
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT         (0U)
+#define USBFSH_HCCOMMANDSTATUS_HCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK          (0x2U)
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT         (1U)
+#define USBFSH_HCCOMMANDSTATUS_CLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK          (0x4U)
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT         (2U)
+#define USBFSH_HCCOMMANDSTATUS_BLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK          (0x8U)
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT         (3U)
+#define USBFSH_HCCOMMANDSTATUS_OCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK          (0xC0U)
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT         (6U)
+#define USBFSH_HCCOMMANDSTATUS_SOC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
+
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK         (0x1U)
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT        (0U)
+#define USBFSH_HCINTERRUPTSTATUS_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK        (0x2U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT       (1U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK         (0x4U)
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT        (2U)
+#define USBFSH_HCINTERRUPTSTATUS_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK         (0x8U)
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT        (3U)
+#define USBFSH_HCINTERRUPTSTATUS_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK         (0x10U)
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT        (4U)
+#define USBFSH_HCINTERRUPTSTATUS_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK        (0x20U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT       (5U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK       (0x40U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT      (6U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK         (0xFFFFFC00U)
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT        (10U)
+#define USBFSH_HCINTERRUPTSTATUS_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
+
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK         (0x1U)
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT        (0U)
+#define USBFSH_HCINTERRUPTENABLE_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK        (0x2U)
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT       (1U)
+#define USBFSH_HCINTERRUPTENABLE_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK         (0x4U)
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT        (2U)
+#define USBFSH_HCINTERRUPTENABLE_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK         (0x8U)
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT        (3U)
+#define USBFSH_HCINTERRUPTENABLE_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK         (0x10U)
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT        (4U)
+#define USBFSH_HCINTERRUPTENABLE_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK        (0x20U)
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT       (5U)
+#define USBFSH_HCINTERRUPTENABLE_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK       (0x40U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT      (6U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK         (0x40000000U)
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT        (30U)
+#define USBFSH_HCINTERRUPTENABLE_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK        (0x80000000U)
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT       (31U)
+#define USBFSH_HCINTERRUPTENABLE_MIE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
+
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK        (0x1U)
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT       (0U)
+#define USBFSH_HCINTERRUPTDISABLE_SO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK       (0x2U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT      (1U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK        (0x4U)
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT       (2U)
+#define USBFSH_HCINTERRUPTDISABLE_SF(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK        (0x8U)
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT       (3U)
+#define USBFSH_HCINTERRUPTDISABLE_RD(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK        (0x10U)
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT       (4U)
+#define USBFSH_HCINTERRUPTDISABLE_UE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK       (0x20U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT      (5U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK      (0x40U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT     (6U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK        (0x40000000U)
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT       (30U)
+#define USBFSH_HCINTERRUPTDISABLE_OC(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK       (0x80000000U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT      (31U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
+
+/*! @name HCHCCA - Contains the physical address of the host controller communication area */
+#define USBFSH_HCHCCA_HCCA_MASK                  (0xFFFFFF00U)
+#define USBFSH_HCHCCA_HCCA_SHIFT                 (8U)
+#define USBFSH_HCHCCA_HCCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
+
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK       (0xFFFFFFF0U)
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT      (4U)
+#define USBFSH_HCPERIODCURRENTED_PCED(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
+
+/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
+#define USBFSH_HCCONTROLHEADED_CHED_MASK         (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT        (4U)
+#define USBFSH_HCCONTROLHEADED_CHED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
+
+/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK      (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT     (4U)
+#define USBFSH_HCCONTROLCURRENTED_CCED(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
+
+/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
+#define USBFSH_HCBULKHEADED_BHED_MASK            (0xFFFFFFF0U)
+#define USBFSH_HCBULKHEADED_BHED_SHIFT           (4U)
+#define USBFSH_HCBULKHEADED_BHED(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
+
+/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
+#define USBFSH_HCBULKCURRENTED_BCED_MASK         (0xFFFFFFF0U)
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT        (4U)
+#define USBFSH_HCBULKCURRENTED_BCED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
+
+/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
+#define USBFSH_HCDONEHEAD_DH_MASK                (0xFFFFFFF0U)
+#define USBFSH_HCDONEHEAD_DH_SHIFT               (4U)
+#define USBFSH_HCDONEHEAD_DH(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
+
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
+#define USBFSH_HCFMINTERVAL_FI_MASK              (0x3FFFU)
+#define USBFSH_HCFMINTERVAL_FI_SHIFT             (0U)
+#define USBFSH_HCFMINTERVAL_FI(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK           (0x7FFF0000U)
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT          (16U)
+#define USBFSH_HCFMINTERVAL_FSMPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
+#define USBFSH_HCFMINTERVAL_FIT_MASK             (0x80000000U)
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT            (31U)
+#define USBFSH_HCFMINTERVAL_FIT(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
+
+/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
+#define USBFSH_HCFMREMAINING_FR_MASK             (0x3FFFU)
+#define USBFSH_HCFMREMAINING_FR_SHIFT            (0U)
+#define USBFSH_HCFMREMAINING_FR(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
+#define USBFSH_HCFMREMAINING_FRT_MASK            (0x80000000U)
+#define USBFSH_HCFMREMAINING_FRT_SHIFT           (31U)
+#define USBFSH_HCFMREMAINING_FRT(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
+
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
+#define USBFSH_HCFMNUMBER_FN_MASK                (0xFFFFU)
+#define USBFSH_HCFMNUMBER_FN_SHIFT               (0U)
+#define USBFSH_HCFMNUMBER_FN(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
+
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
+#define USBFSH_HCPERIODICSTART_PS_MASK           (0x3FFFU)
+#define USBFSH_HCPERIODICSTART_PS_SHIFT          (0U)
+#define USBFSH_HCPERIODICSTART_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
+
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
+#define USBFSH_HCLSTHRESHOLD_LST_MASK            (0xFFFU)
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT           (0U)
+#define USBFSH_HCLSTHRESHOLD_LST(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
+
+/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK          (0xFFU)
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT         (0U)
+#define USBFSH_HCRHDESCRIPTORA_NDP(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK          (0x100U)
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT         (8U)
+#define USBFSH_HCRHDESCRIPTORA_PSM(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK          (0x200U)
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT         (9U)
+#define USBFSH_HCRHDESCRIPTORA_NPS(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK           (0x400U)
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT          (10U)
+#define USBFSH_HCRHDESCRIPTORA_DT(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK         (0x800U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT        (11U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK         (0x1000U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT        (12U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK       (0xFF000000U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT      (24U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
+
+/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK           (0xFFFFU)
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT          (0U)
+#define USBFSH_HCRHDESCRIPTORB_DR(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK         (0xFFFF0000U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT        (16U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
+
+/*! @name HCRHSTATUS - This register is divided into two parts */
+#define USBFSH_HCRHSTATUS_LPS_MASK               (0x1U)
+#define USBFSH_HCRHSTATUS_LPS_SHIFT              (0U)
+#define USBFSH_HCRHSTATUS_LPS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
+#define USBFSH_HCRHSTATUS_OCI_MASK               (0x2U)
+#define USBFSH_HCRHSTATUS_OCI_SHIFT              (1U)
+#define USBFSH_HCRHSTATUS_OCI(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
+#define USBFSH_HCRHSTATUS_DRWE_MASK              (0x8000U)
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT             (15U)
+#define USBFSH_HCRHSTATUS_DRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
+#define USBFSH_HCRHSTATUS_LPSC_MASK              (0x10000U)
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT             (16U)
+#define USBFSH_HCRHSTATUS_LPSC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
+#define USBFSH_HCRHSTATUS_OCIC_MASK              (0x20000U)
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT             (17U)
+#define USBFSH_HCRHSTATUS_OCIC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
+#define USBFSH_HCRHSTATUS_CRWE_MASK              (0x80000000U)
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT             (31U)
+#define USBFSH_HCRHSTATUS_CRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
+
+/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK           (0x1U)
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT          (0U)
+#define USBFSH_HCRHPORTSTATUS_CCS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PES_MASK           (0x2U)
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT          (1U)
+#define USBFSH_HCRHPORTSTATUS_PES(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK           (0x4U)
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT          (2U)
+#define USBFSH_HCRHPORTSTATUS_PSS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK          (0x8U)
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT         (3U)
+#define USBFSH_HCRHPORTSTATUS_POCI(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK           (0x10U)
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT          (4U)
+#define USBFSH_HCRHPORTSTATUS_PRS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK           (0x100U)
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT          (8U)
+#define USBFSH_HCRHPORTSTATUS_PPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK          (0x200U)
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT         (9U)
+#define USBFSH_HCRHPORTSTATUS_LSDA(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK           (0x10000U)
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT          (16U)
+#define USBFSH_HCRHPORTSTATUS_CSC(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK          (0x20000U)
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT         (17U)
+#define USBFSH_HCRHPORTSTATUS_PESC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK          (0x40000U)
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT         (18U)
+#define USBFSH_HCRHPORTSTATUS_PSSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK          (0x80000U)
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT         (19U)
+#define USBFSH_HCRHPORTSTATUS_OCIC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK          (0x100000U)
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT         (20U)
+#define USBFSH_HCRHPORTSTATUS_PRSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+#define USBFSH_PORTMODE_ID_MASK                  (0x1U)
+#define USBFSH_PORTMODE_ID_SHIFT                 (0U)
+#define USBFSH_PORTMODE_ID(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
+#define USBFSH_PORTMODE_ID_EN_MASK               (0x100U)
+#define USBFSH_PORTMODE_ID_EN_SHIFT              (8U)
+#define USBFSH_PORTMODE_ID_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
+#define USBFSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Register_Masks */
+
+
+/* USBFSH - Peripheral instance base addresses */
+/** Peripheral USBFSH base address */
+#define USBFSH_BASE                              (0x400A2000u)
+/** Peripheral USBFSH base pointer */
+#define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
+/** Array initializer of USBFSH peripheral base addresses */
+#define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
+/** Array initializer of USBFSH peripheral base pointers */
+#define USBFSH_BASE_PTRS                         { USBFSH }
+/** Interrupt vectors for the USBFSH peripheral type */
+#define USBFSH_IRQS                              { USB0_IRQn }
+#define USBFSH_NEEDCLK_IRQS                      { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHSD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status register, offset: 0x0 */
+  __I  uint32_t INFO;                              /**< USB Info register, offset: 0x4 */
+  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
+  __I  uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
+  __IO uint32_t LPM;                               /**< USB Link Power Management register, offset: 0x10 */
+  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
+  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
+  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+  __IO uint32_t INTSTAT;                           /**< USB interrupt status register, offset: 0x20 */
+  __IO uint32_t INTEN;                             /**< USB interrupt enable register, offset: 0x24 */
+  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status register, offset: 0x28 */
+       uint8_t RESERVED_0[8];
+  __I  uint32_t EPTOGGLE;                          /**< USB Endpoint toggle register, offset: 0x34 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t ULPIDEBUG;                         /**< UTMI/ULPI debug register, offset: 0x3C */
+} USBHSD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHSD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK          (0x7FU)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT         (0U)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK            (0x80U)
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT           (7U)
+#define USBHSD_DEVCMDSTAT_DEV_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
+#define USBHSD_DEVCMDSTAT_SETUP_MASK             (0x100U)
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT            (8U)
+#define USBHSD_DEVCMDSTAT_SETUP(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK     (0x200U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT    (9U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK        (0x400U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT       (10U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK           (0x800U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT          (11U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK       (0x1000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT      (12U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK       (0x2000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT      (13U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK       (0x4000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT      (14U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK       (0x8000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT      (15U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_MASK              (0x10000U)
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT             (16U)
+#define USBHSD_DEVCMDSTAT_DCON(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_MASK              (0x20000U)
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT             (17U)
+#define USBHSD_DEVCMDSTAT_DSUS(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK           (0x80000U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT          (19U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK          (0x100000U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT         (20U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
+#define USBHSD_DEVCMDSTAT_Speed_MASK             (0xC00000U)
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT            (22U)
+#define USBHSD_DEVCMDSTAT_Speed(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK            (0x1000000U)
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT           (24U)
+#define USBHSD_DEVCMDSTAT_DCON_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK            (0x2000000U)
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT           (25U)
+#define USBHSD_DEVCMDSTAT_DSUS_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK            (0x4000000U)
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT           (26U)
+#define USBHSD_DEVCMDSTAT_DRES_C(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK    (0x10000000U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT   (28U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK     (0xE0000000U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT    (29U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
+
+/*! @name INFO - USB Info register */
+#define USBHSD_INFO_FRAME_NR_MASK                (0x7FFU)
+#define USBHSD_INFO_FRAME_NR_SHIFT               (0U)
+#define USBHSD_INFO_FRAME_NR(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
+#define USBHSD_INFO_ERR_CODE_MASK                (0x7800U)
+#define USBHSD_INFO_ERR_CODE_SHIFT               (11U)
+#define USBHSD_INFO_ERR_CODE(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
+#define USBHSD_INFO_Minrev_MASK                  (0xFF0000U)
+#define USBHSD_INFO_Minrev_SHIFT                 (16U)
+#define USBHSD_INFO_Minrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
+#define USBHSD_INFO_Majrev_MASK                  (0xFF000000U)
+#define USBHSD_INFO_Majrev_SHIFT                 (24U)
+#define USBHSD_INFO_Majrev(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK      (0xFFF00U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT     (8U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x)        (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK    (0xFFF00000U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT   (20U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x)      (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+#define USBHSD_DATABUFSTART_DA_BUF_MASK          (0xFFFFFFFFU)
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT         (0U)
+#define USBHSD_DATABUFSTART_DA_BUF(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
+
+/*! @name LPM - USB Link Power Management register */
+#define USBHSD_LPM_HIRD_HW_MASK                  (0xFU)
+#define USBHSD_LPM_HIRD_HW_SHIFT                 (0U)
+#define USBHSD_LPM_HIRD_HW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
+#define USBHSD_LPM_HIRD_SW_MASK                  (0xF0U)
+#define USBHSD_LPM_HIRD_SW_SHIFT                 (4U)
+#define USBHSD_LPM_HIRD_SW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
+#define USBHSD_LPM_DATA_PENDING_MASK             (0x100U)
+#define USBHSD_LPM_DATA_PENDING_SHIFT            (8U)
+#define USBHSD_LPM_DATA_PENDING(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
+
+/*! @name EPSKIP - USB Endpoint skip */
+#define USBHSD_EPSKIP_SKIP_MASK                  (0xFFFU)
+#define USBHSD_EPSKIP_SKIP_SHIFT                 (0U)
+#define USBHSD_EPSKIP_SKIP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+#define USBHSD_EPINUSE_BUF_MASK                  (0xFFCU)
+#define USBHSD_EPINUSE_BUF_SHIFT                 (2U)
+#define USBHSD_EPINUSE_BUF(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+#define USBHSD_EPBUFCFG_BUF_SB_MASK              (0xFFCU)
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT             (2U)
+#define USBHSD_EPBUFCFG_BUF_SB(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
+
+/*! @name INTSTAT - USB interrupt status register */
+#define USBHSD_INTSTAT_EP0OUT_MASK               (0x1U)
+#define USBHSD_INTSTAT_EP0OUT_SHIFT              (0U)
+#define USBHSD_INTSTAT_EP0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
+#define USBHSD_INTSTAT_EP0IN_MASK                (0x2U)
+#define USBHSD_INTSTAT_EP0IN_SHIFT               (1U)
+#define USBHSD_INTSTAT_EP0IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
+#define USBHSD_INTSTAT_EP1OUT_MASK               (0x4U)
+#define USBHSD_INTSTAT_EP1OUT_SHIFT              (2U)
+#define USBHSD_INTSTAT_EP1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
+#define USBHSD_INTSTAT_EP1IN_MASK                (0x8U)
+#define USBHSD_INTSTAT_EP1IN_SHIFT               (3U)
+#define USBHSD_INTSTAT_EP1IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
+#define USBHSD_INTSTAT_EP2OUT_MASK               (0x10U)
+#define USBHSD_INTSTAT_EP2OUT_SHIFT              (4U)
+#define USBHSD_INTSTAT_EP2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
+#define USBHSD_INTSTAT_EP2IN_MASK                (0x20U)
+#define USBHSD_INTSTAT_EP2IN_SHIFT               (5U)
+#define USBHSD_INTSTAT_EP2IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
+#define USBHSD_INTSTAT_EP3OUT_MASK               (0x40U)
+#define USBHSD_INTSTAT_EP3OUT_SHIFT              (6U)
+#define USBHSD_INTSTAT_EP3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
+#define USBHSD_INTSTAT_EP3IN_MASK                (0x80U)
+#define USBHSD_INTSTAT_EP3IN_SHIFT               (7U)
+#define USBHSD_INTSTAT_EP3IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
+#define USBHSD_INTSTAT_EP4OUT_MASK               (0x100U)
+#define USBHSD_INTSTAT_EP4OUT_SHIFT              (8U)
+#define USBHSD_INTSTAT_EP4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
+#define USBHSD_INTSTAT_EP4IN_MASK                (0x200U)
+#define USBHSD_INTSTAT_EP4IN_SHIFT               (9U)
+#define USBHSD_INTSTAT_EP4IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
+#define USBHSD_INTSTAT_EP5OUT_MASK               (0x400U)
+#define USBHSD_INTSTAT_EP5OUT_SHIFT              (10U)
+#define USBHSD_INTSTAT_EP5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
+#define USBHSD_INTSTAT_EP5IN_MASK                (0x800U)
+#define USBHSD_INTSTAT_EP5IN_SHIFT               (11U)
+#define USBHSD_INTSTAT_EP5IN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
+#define USBHSD_INTSTAT_FRAME_INT_MASK            (0x40000000U)
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT           (30U)
+#define USBHSD_INTSTAT_FRAME_INT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
+#define USBHSD_INTSTAT_DEV_INT_MASK              (0x80000000U)
+#define USBHSD_INTSTAT_DEV_INT_SHIFT             (31U)
+#define USBHSD_INTSTAT_DEV_INT(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
+
+/*! @name INTEN - USB interrupt enable register */
+#define USBHSD_INTEN_EP_INT_EN_MASK              (0xFFFU)
+#define USBHSD_INTEN_EP_INT_EN_SHIFT             (0U)
+#define USBHSD_INTEN_EP_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
+#define USBHSD_INTEN_FRAME_INT_EN_MASK           (0x40000000U)
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT          (30U)
+#define USBHSD_INTEN_FRAME_INT_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
+#define USBHSD_INTEN_DEV_INT_EN_MASK             (0x80000000U)
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT            (31U)
+#define USBHSD_INTEN_DEV_INT_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK        (0xFFFU)
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT       (0U)
+#define USBHSD_INTSETSTAT_EP_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK     (0x40000000U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT    (30U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x)       (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK       (0x80000000U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT      (31U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x)         (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+#define USBHSD_EPTOGGLE_TOGGLE_MASK              (0x3FFFFFFFU)
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT             (0U)
+#define USBHSD_EPTOGGLE_TOGGLE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
+
+/*! @name ULPIDEBUG - UTMI/ULPI debug register */
+#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK           (0xFFU)
+#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT          (0U)
+#define USBHSD_ULPIDEBUG_PHY_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK)
+#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK          (0xFF00U)
+#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT         (8U)
+#define USBHSD_ULPIDEBUG_PHY_WDATA(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK)
+#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK          (0xFF0000U)
+#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT         (16U)
+#define USBHSD_ULPIDEBUG_PHY_RDATA(x)            (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK)
+#define USBHSD_ULPIDEBUG_PHY_RW_MASK             (0x1000000U)
+#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT            (24U)
+#define USBHSD_ULPIDEBUG_PHY_RW(x)               (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK         (0x2000000U)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT        (25U)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK)
+#define USBHSD_ULPIDEBUG_PHY_MODE_MASK           (0x80000000U)
+#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT          (31U)
+#define USBHSD_ULPIDEBUG_PHY_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Register_Masks */
+
+
+/* USBHSD - Peripheral instance base addresses */
+/** Peripheral USBHSD base address */
+#define USBHSD_BASE                              (0x40094000u)
+/** Peripheral USBHSD base pointer */
+#define USBHSD                                   ((USBHSD_Type *)USBHSD_BASE)
+/** Array initializer of USBHSD peripheral base addresses */
+#define USBHSD_BASE_ADDRS                        { USBHSD_BASE }
+/** Array initializer of USBHSD peripheral base pointers */
+#define USBHSD_BASE_PTRS                         { USBHSD }
+/** Interrupt vectors for the USBHSD peripheral type */
+#define USBHSD_IRQS                              { USB1_IRQn }
+#define USBHSD_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHSH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSH - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CAPLENGTH_CHIPID;                  /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
+  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x4 */
+  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x8 */
+  __IO uint32_t FLADJ_FRINDEX;                     /**< Frame Length Adjustment, offset: 0xC */
+  __IO uint32_t ATL_PTD_BASE_ADDR;                 /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
+  __IO uint32_t ISO_PTD_BASE_ADDR;                 /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
+  __IO uint32_t INT_PTD_BASE_ADDR;                 /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
+  __IO uint32_t DATA_PAYLOAD_BASE_ADDR;            /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
+  __IO uint32_t USBCMD;                            /**< USB Command register, offset: 0x20 */
+  __IO uint32_t USBSTS;                            /**< USB Interrupt Status register, offset: 0x24 */
+  __IO uint32_t USBINTR;                           /**< USB Interrupt Enable register, offset: 0x28 */
+  __IO uint32_t PORTSC1;                           /**< Port Status and Control register, offset: 0x2C */
+  __IO uint32_t ATL_PTD_DONE_MAP;                  /**< Done map for each ATL PTD, offset: 0x30 */
+  __IO uint32_t ATL_PTD_SKIP_MAP;                  /**< Skip map for each ATL PTD, offset: 0x34 */
+  __IO uint32_t ISO_PTD_DONE_MAP;                  /**< Done map for each ISO PTD, offset: 0x38 */
+  __IO uint32_t ISO_PTD_SKIP_MAP;                  /**< Skip map for each ISO PTD, offset: 0x3C */
+  __IO uint32_t INT_PTD_DONE_MAP;                  /**< Done map for each INT PTD, offset: 0x40 */
+  __IO uint32_t INT_PTD_SKIP_MAP;                  /**< Skip map for each INT PTD, offset: 0x44 */
+  __IO uint32_t LAST_PTD_INUSE;                    /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
+  __IO uint32_t UTMIPLUS_ULPI_DEBUG;               /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */
+  __IO uint32_t PORTMODE;                          /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
+} USBHSH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHSH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
+ * @{
+ */
+
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK   (0xFFU)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT  (0U)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK      (0xFFFF0000U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT     (16U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters */
+#define USBHSH_HCSPARAMS_N_PORTS_MASK            (0xFU)
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT           (0U)
+#define USBHSH_HCSPARAMS_N_PORTS(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
+#define USBHSH_HCSPARAMS_PPC_MASK                (0x10U)
+#define USBHSH_HCSPARAMS_PPC_SHIFT               (4U)
+#define USBHSH_HCSPARAMS_PPC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK        (0x10000U)
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT       (16U)
+#define USBHSH_HCSPARAMS_P_INDICATOR(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
+
+/*! @name HCCPARAMS - Host Controller Capability Parameters */
+#define USBHSH_HCCPARAMS_LPMC_MASK               (0x20000U)
+#define USBHSH_HCCPARAMS_LPMC_SHIFT              (17U)
+#define USBHSH_HCCPARAMS_LPMC(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
+
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK          (0x3FU)
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT         (0U)
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK        (0x3FFF0000U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT       (16U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x)          (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
+
+/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK    (0x1F0U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT   (4U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK   (0xFFFFFE00U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT  (9U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
+
+/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK  (0x3E0U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK   (0xFFFFFC00U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT  (10U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
+
+/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK  (0x3E0U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x)    (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK   (0xFFFFFC00U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT  (10U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
+
+/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
+
+/*! @name USBCMD - USB Command register */
+#define USBHSH_USBCMD_RS_MASK                    (0x1U)
+#define USBHSH_USBCMD_RS_SHIFT                   (0U)
+#define USBHSH_USBCMD_RS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
+#define USBHSH_USBCMD_HCRESET_MASK               (0x2U)
+#define USBHSH_USBCMD_HCRESET_SHIFT              (1U)
+#define USBHSH_USBCMD_HCRESET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
+#define USBHSH_USBCMD_FLS_MASK                   (0xCU)
+#define USBHSH_USBCMD_FLS_SHIFT                  (2U)
+#define USBHSH_USBCMD_FLS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
+#define USBHSH_USBCMD_LHCR_MASK                  (0x80U)
+#define USBHSH_USBCMD_LHCR_SHIFT                 (7U)
+#define USBHSH_USBCMD_LHCR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
+#define USBHSH_USBCMD_ATL_EN_MASK                (0x100U)
+#define USBHSH_USBCMD_ATL_EN_SHIFT               (8U)
+#define USBHSH_USBCMD_ATL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
+#define USBHSH_USBCMD_ISO_EN_MASK                (0x200U)
+#define USBHSH_USBCMD_ISO_EN_SHIFT               (9U)
+#define USBHSH_USBCMD_ISO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
+#define USBHSH_USBCMD_INT_EN_MASK                (0x400U)
+#define USBHSH_USBCMD_INT_EN_SHIFT               (10U)
+#define USBHSH_USBCMD_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
+#define USBHSH_USBCMD_HIRD_MASK                  (0xF000000U)
+#define USBHSH_USBCMD_HIRD_SHIFT                 (24U)
+#define USBHSH_USBCMD_HIRD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
+#define USBHSH_USBCMD_LPM_RWU_MASK               (0x10000000U)
+#define USBHSH_USBCMD_LPM_RWU_SHIFT              (28U)
+#define USBHSH_USBCMD_LPM_RWU(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)
+
+/*! @name USBSTS - USB Interrupt Status register */
+#define USBHSH_USBSTS_PCD_MASK                   (0x4U)
+#define USBHSH_USBSTS_PCD_SHIFT                  (2U)
+#define USBHSH_USBSTS_PCD(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
+#define USBHSH_USBSTS_FLR_MASK                   (0x8U)
+#define USBHSH_USBSTS_FLR_SHIFT                  (3U)
+#define USBHSH_USBSTS_FLR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
+#define USBHSH_USBSTS_ATL_IRQ_MASK               (0x10000U)
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT              (16U)
+#define USBHSH_USBSTS_ATL_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
+#define USBHSH_USBSTS_ISO_IRQ_MASK               (0x20000U)
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT              (17U)
+#define USBHSH_USBSTS_ISO_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
+#define USBHSH_USBSTS_INT_IRQ_MASK               (0x40000U)
+#define USBHSH_USBSTS_INT_IRQ_SHIFT              (18U)
+#define USBHSH_USBSTS_INT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
+#define USBHSH_USBSTS_SOF_IRQ_MASK               (0x80000U)
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT              (19U)
+#define USBHSH_USBSTS_SOF_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
+
+/*! @name USBINTR - USB Interrupt Enable register */
+#define USBHSH_USBINTR_PCDE_MASK                 (0x4U)
+#define USBHSH_USBINTR_PCDE_SHIFT                (2U)
+#define USBHSH_USBINTR_PCDE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
+#define USBHSH_USBINTR_FLRE_MASK                 (0x8U)
+#define USBHSH_USBINTR_FLRE_SHIFT                (3U)
+#define USBHSH_USBINTR_FLRE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK            (0x10000U)
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT           (16U)
+#define USBHSH_USBINTR_ATL_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK            (0x20000U)
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT           (17U)
+#define USBHSH_USBINTR_ISO_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
+#define USBHSH_USBINTR_INT_IRQ_E_MASK            (0x40000U)
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT           (18U)
+#define USBHSH_USBINTR_INT_IRQ_E(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
+#define USBHSH_USBINTR_SOF_E_MASK                (0x80000U)
+#define USBHSH_USBINTR_SOF_E_SHIFT               (19U)
+#define USBHSH_USBINTR_SOF_E(x)                  (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
+
+/*! @name PORTSC1 - Port Status and Control register */
+#define USBHSH_PORTSC1_CCS_MASK                  (0x1U)
+#define USBHSH_PORTSC1_CCS_SHIFT                 (0U)
+#define USBHSH_PORTSC1_CCS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
+#define USBHSH_PORTSC1_CSC_MASK                  (0x2U)
+#define USBHSH_PORTSC1_CSC_SHIFT                 (1U)
+#define USBHSH_PORTSC1_CSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
+#define USBHSH_PORTSC1_PED_MASK                  (0x4U)
+#define USBHSH_PORTSC1_PED_SHIFT                 (2U)
+#define USBHSH_PORTSC1_PED(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
+#define USBHSH_PORTSC1_PEDC_MASK                 (0x8U)
+#define USBHSH_PORTSC1_PEDC_SHIFT                (3U)
+#define USBHSH_PORTSC1_PEDC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
+#define USBHSH_PORTSC1_OCA_MASK                  (0x10U)
+#define USBHSH_PORTSC1_OCA_SHIFT                 (4U)
+#define USBHSH_PORTSC1_OCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
+#define USBHSH_PORTSC1_OCC_MASK                  (0x20U)
+#define USBHSH_PORTSC1_OCC_SHIFT                 (5U)
+#define USBHSH_PORTSC1_OCC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
+#define USBHSH_PORTSC1_FPR_MASK                  (0x40U)
+#define USBHSH_PORTSC1_FPR_SHIFT                 (6U)
+#define USBHSH_PORTSC1_FPR(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
+#define USBHSH_PORTSC1_SUSP_MASK                 (0x80U)
+#define USBHSH_PORTSC1_SUSP_SHIFT                (7U)
+#define USBHSH_PORTSC1_SUSP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
+#define USBHSH_PORTSC1_PR_MASK                   (0x100U)
+#define USBHSH_PORTSC1_PR_SHIFT                  (8U)
+#define USBHSH_PORTSC1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
+#define USBHSH_PORTSC1_SUS_L1_MASK               (0x200U)
+#define USBHSH_PORTSC1_SUS_L1_SHIFT              (9U)
+#define USBHSH_PORTSC1_SUS_L1(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
+#define USBHSH_PORTSC1_LS_MASK                   (0xC00U)
+#define USBHSH_PORTSC1_LS_SHIFT                  (10U)
+#define USBHSH_PORTSC1_LS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
+#define USBHSH_PORTSC1_PP_MASK                   (0x1000U)
+#define USBHSH_PORTSC1_PP_SHIFT                  (12U)
+#define USBHSH_PORTSC1_PP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
+#define USBHSH_PORTSC1_PIC_MASK                  (0xC000U)
+#define USBHSH_PORTSC1_PIC_SHIFT                 (14U)
+#define USBHSH_PORTSC1_PIC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
+#define USBHSH_PORTSC1_PTC_MASK                  (0xF0000U)
+#define USBHSH_PORTSC1_PTC_SHIFT                 (16U)
+#define USBHSH_PORTSC1_PTC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
+#define USBHSH_PORTSC1_PSPD_MASK                 (0x300000U)
+#define USBHSH_PORTSC1_PSPD_SHIFT                (20U)
+#define USBHSH_PORTSC1_PSPD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
+#define USBHSH_PORTSC1_WOO_MASK                  (0x400000U)
+#define USBHSH_PORTSC1_WOO_SHIFT                 (22U)
+#define USBHSH_PORTSC1_WOO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
+#define USBHSH_PORTSC1_SUS_STAT_MASK             (0x1800000U)
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT            (23U)
+#define USBHSH_PORTSC1_SUS_STAT(x)               (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
+#define USBHSH_PORTSC1_DEV_ADD_MASK              (0xFE000000U)
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT             (25U)
+#define USBHSH_PORTSC1_DEV_ADD(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
+
+/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT   (0U)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
+
+/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT   (0U)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
+
+/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT   (0U)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
+
+/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT   (0U)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
+
+/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK    (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT   (0U)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
+
+/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK    (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT   (0U)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x)      (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
+
+/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK      (0x1FU)
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT     (0U)
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK      (0x1F00U)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT     (8U)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK      (0x1F0000U)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT     (16U)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST(x)        (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)
+
+/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x)  (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x)  (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK   (0x1000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT  (24U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x)     (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK)
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+#define USBHSH_PORTMODE_ID0_MASK                 (0x1U)
+#define USBHSH_PORTMODE_ID0_SHIFT                (0U)
+#define USBHSH_PORTMODE_ID0(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
+#define USBHSH_PORTMODE_ID0_EN_MASK              (0x100U)
+#define USBHSH_PORTMODE_ID0_EN_SHIFT             (8U)
+#define USBHSH_PORTMODE_ID0_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
+#define USBHSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK       (0x40000U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT      (18U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
+#define USBHSH_PORTMODE_SW_PDCOM_MASK            (0x80000U)
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT           (19U)
+#define USBHSH_PORTMODE_SW_PDCOM(x)              (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Register_Masks */
+
+
+/* USBHSH - Peripheral instance base addresses */
+/** Peripheral USBHSH base address */
+#define USBHSH_BASE                              (0x400A3000u)
+/** Peripheral USBHSH base pointer */
+#define USBHSH                                   ((USBHSH_Type *)USBHSH_BASE)
+/** Array initializer of USBHSH peripheral base addresses */
+#define USBHSH_BASE_ADDRS                        { USBHSH_BASE }
+/** Array initializer of USBHSH peripheral base pointers */
+#define USBHSH_BASE_PTRS                         { USBHSH }
+/** Interrupt vectors for the USBHSH peripheral type */
+#define USBHSH_IRQS                              { USB1_IRQn }
+#define USBHSH_NEEDCLK_IRQS                      { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CTRL;                              /**< Control register., offset: 0x0 */
+  __IO uint32_t STAT;                              /**< Status register., offset: 0x4 */
+  __IO uint32_t CFG;                               /**< Capture configuration register., offset: 0x8 */
+  __O  uint32_t CAPCLR;                            /**< Capture clear register., offset: 0xC */
+  __I  uint32_t CAP[4];                            /**< Capture register ., array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UTICK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register. */
+#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
+#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
+#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+
+/*! @name STAT - Status register. */
+#define UTICK_STAT_INTR_MASK                     (0x1U)
+#define UTICK_STAT_INTR_SHIFT                    (0U)
+#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
+#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+
+/*! @name CFG - Capture configuration register. */
+#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
+#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
+#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
+#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
+#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
+#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
+#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
+#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
+#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+
+/*! @name CAPCLR - Capture clear register. */
+#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
+#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
+#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
+#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
+#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+
+/*! @name CAP - Capture register . */
+#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
+#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+#define UTICK_CAP_VALID_MASK                     (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT                    (31U)
+#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE                              (0x4000E000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS                          { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS                               { UTICK0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MOD;                               /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
+  __IO uint32_t TC;                                /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
+  __O  uint32_t FEED;                              /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
+  __I  uint32_t TV;                                /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t WARNINT;                           /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
+  __IO uint32_t WINDOW;                            /**< Watchdog Window compare value., offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WWDT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+#define WWDT_MOD_WDEN_MASK                       (0x1U)
+#define WWDT_MOD_WDEN_SHIFT                      (0U)
+#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+#define WWDT_MOD_WDRESET_MASK                    (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT                   (1U)
+#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+#define WWDT_MOD_WDTOF_MASK                      (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT                     (2U)
+#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+#define WWDT_MOD_WDINT_MASK                      (0x8U)
+#define WWDT_MOD_WDINT_SHIFT                     (3U)
+#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
+#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_LOCK_MASK                       (0x20U)
+#define WWDT_MOD_LOCK_SHIFT                      (5U)
+#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
+#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT                      (0U)
+#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
+#define WWDT_FEED_FEED_MASK                      (0xFFU)
+#define WWDT_FEED_FEED_SHIFT                     (0U)
+#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT                      (0U)
+#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
+#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
+#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+
+/*! @name WINDOW - Watchdog Window compare value. */
+#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
+#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT base address */
+#define WWDT_BASE                                (0x4000C000u)
+/** Peripheral WWDT base pointer */
+#define WWDT                                     ((WWDT_Type *)WWDT_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS                          { WWDT_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS                           { WWDT }
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS                                { WDT_BOD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/** EMC CS base address */
+#define EMC_CS0_BASE                                (0x80000000u)
+#define EMC_CS1_BASE                                (0x90000000u)
+#define EMC_CS2_BASE                                (0x98000000u)
+#define EMC_CS3_BASE                                (0x9C000000u)
+#define EMC_DYCS0_BASE                              (0xA0000000u)
+#define EMC_DYCS1_BASE                              (0xB0000000u)
+#define EMC_DYCS2_BASE                              (0xC0000000u)
+#define EMC_DYCS3_BASE                              (0xD0000000u)
+#define EMC_CS_ADDRESS                              {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
+#define EMC_DYCS_ADDRESS                            {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
+
+/** OTP API */
+typedef struct {
+  uint32_t (*otpInit)(void);                                    /** Initializes OTP controller */
+  uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask);        /** Unlock one or more OTP banks for write access */
+  uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask);       /** Lock one or more OTP banks for write access */
+  uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+                                          uint32_t lockWrite);  /** Locks or unlocks write access to a register of an OTP bank and the write lock */
+  uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+                                         uint32_t lockWrite);   /** Locks or unlocks read access to a register of an OTP bank and the write lock */
+  uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value);  /** Program a single register in an OTP bank */
+  uint32_t RESERVED_0[5];
+  uint32_t (*rngRead)(void);                                    /** Returns 32-bit number from hardware random number generator */
+  uint32_t (*otpGetDriverVersion)(void);                        /** Returns the version of the OTP driver in ROM */
+} OTP_API_Type;
+
+/** ROM API */
+typedef struct {
+  __I uint32_t usbdApiBase;                      /** USB API Base */
+      uint32_t RESERVED_0[13];
+  __I OTP_API_Type *otpApiBase;                  /** OTP API Base */
+  __I uint32_t aesApiBase;                       /** AES API Base */
+  __I uint32_t secureApiBase;                    /** Secure API Base */
+} ROM_API_Type;
+
+/** ROM API base address */
+#define ROM_API_BASE                             (0x03000200u)
+/** ROM API base pointer */
+#define ROM_API                                  (*(ROM_API_Type**) ROM_API_BASE)
+/** OTP API base pointer */
+#define OTP_API                                  (ROM_API->otpApiBase)
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _LPC54608_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,231 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b170112
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+#ifndef _LPC54608_FEATURES_H_
+#define _LPC54608_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (10)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (10)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (10)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief EEPROM availability on the SoC. */
+#define FSL_FEATURE_SOC_EEPROM_COUNT (1)
+/* @brief EMC availability on the SoC. */
+#define FSL_FEATURE_SOC_EMC_COUNT (1)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SMARTCARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
+/* @brief LCD availability on the SoC. */
+#define FSL_FEATURE_SOC_LCD_COUNT (1)
+/* @brief CAN availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2)
+/* @brief SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (0)
+/* @brief AES availability on the SoC. */
+#define FSL_FEATURE_SOC_AES_COUNT (0)
+/* @brief RIT availability on the SoC. */
+#define FSL_FEATURE_SOC_RIT_COUNT (1)
+/* @brief FMC availability on the SoC. */
+#define FSL_FEATURE_SOC_FMC_COUNT (1)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
+
+/* CAN module features */
+
+/* @brief Support CANFD or not */
+#define FSL_FEATURE_CAN_SUPPORT_CANFD (0)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+
+/* EEPROM module features */
+
+/* @brief Size of the EEPROM */
+#define FSL_FEATURE_EEPROM_SIZE (0x00004000)
+/* @brief Base address of the EEPROM */
+#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000)
+/* @brief Page count of the EEPROM */
+#define FSL_FEATURE_EEPROM_PAGE_COUNT (128)
+/* @brief Command number for eeprom program */
+#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6)
+/* @brief EEPROM internal clock freqency */
+#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+
+/* SPIFI module features */
+
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+
+#endif /* _LPC54608_FEATURES_H_ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,121 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          LPC54608J512BD208
+**                          LPC54608J512ET180
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b161227
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+#define __ram_vector_table__            1
+
+#if (defined(__ram_vector_table__))
+  #define __ram_vector_table_size__    0x00000400
+#else
+  #define __ram_vector_table_size__    0x00000000
+#endif
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x00000400
+#define m_text_size                    0x0007FC00
+
+#define m_interrupts_ram_start         0x20000000
+#define m_interrupts_ram_size          __ram_vector_table_size__
+
+#define m_data_start                   (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size                    (0x00028000 - m_interrupts_ram_size)
+
+#define m_usb_sram_start               0x40100000
+#define m_usb_sram_size                0x00002000
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+#if (defined(__ram_vector_table__))
+  VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
+  }
+#else
+  VECTOR_RAM m_interrupts_start EMPTY 0 {
+  }
+#endif
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  RW_IRAM1 +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+}
+
+LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
+  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (m_usb_bdt)
+  }
+}
+
+LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
+  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (m_usb_global)
+  }
+}
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,713 @@
+;/*****************************************************************************
+; * @file:    startup_LPC54608.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; *           LPC54608
+; * @version: 1.1
+; * @date:    2016-11-25
+; *
+; * Copyright 1997 - 2016 Freescale Semiconductor, Inc.
+; * Copyright 2016 - 2017 NXP
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; *   of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; *   list of conditions and the following disclaimer in the documentation and/or
+; *   other materials provided with the distribution.
+; *
+; * o Neither the name of the copyright holder nor the names of its
+; *   contributors may be used to endorse or promote products derived from this
+; *   software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
+                DCD     MemManage_Handler
+                DCD     BusFault_Handler
+                DCD     UsageFault_Handler
+__vector_table_0x1c
+                DCD     0                         ; Checksum of the first 7 words
+                DCD     0xFFFFFFFF                ; ECRP
+                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
+                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
+                DCD     SVC_Handler
+                DCD     DebugMon_Handler
+                DCD     0
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
+
+                ; External Interrupts
+                DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
+                DCD     DMA0_IRQHandler  ; DMA controller
+                DCD     GINT0_IRQHandler  ; GPIO group 0
+                DCD     GINT1_IRQHandler  ; GPIO group 1
+                DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
+                DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
+                DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
+                DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
+                DCD     UTICK0_IRQHandler  ; Micro-tick Timer
+                DCD     MRT0_IRQHandler  ; Multi-rate timer
+                DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
+                DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
+                DCD     SCT0_IRQHandler  ; SCTimer/PWM
+                DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
+                DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+                DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+                DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+                DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
+                DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
+                DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
+                DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
+                DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
+                DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
+                DCD     USB0_IRQHandler  ; USB device
+                DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
+                DCD     Reserved46_IRQHandler  ; Reserved interrupt
+                DCD     Reserved47_IRQHandler  ; Reserved interrupt
+                DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
+                DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
+                DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
+                DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
+                DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
+                DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
+                DCD     RIT_IRQHandler  ; Repetitive Interrupt Timer
+                DCD     SPIFI0_IRQHandler  ; SPI flash interface
+                DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+                DCD     FLEXCOMM9_IRQHandler  ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+                DCD     SDIO_IRQHandler  ; SD/MMC
+                DCD     CAN0_IRQ0_IRQHandler  ; CAN0 interrupt0
+                DCD     CAN0_IRQ1_IRQHandler  ; CAN0 interrupt1
+                DCD     CAN1_IRQ0_IRQHandler  ; CAN1 interrupt0
+                DCD     CAN1_IRQ1_IRQHandler  ; CAN1 interrupt1
+                DCD     USB1_IRQHandler  ; USB1 interrupt
+                DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
+                DCD     ETHERNET_IRQHandler  ; Ethernet
+                DCD     ETHERNET_PMT_IRQHandler  ; Ethernet power management interrupt
+                DCD     ETHERNET_MACLP_IRQHandler  ; Ethernet MAC interrupt
+                DCD     EEPROM_IRQHandler  ; EEPROM interrupt
+                DCD     LCD_IRQHandler  ; LCD interrupt
+                DCD     SHA_IRQHandler  ; SHA interrupt
+                DCD     SMARTCARD0_IRQHandler  ; Smart card 0 interrupt
+                DCD     SMARTCARD1_IRQHandler  ; Smart card 1 interrupt
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler               [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+                LDR     r0, =SystemInit
+                BLX     r0
+                LDR     r0, =__main
+                BX      r0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler \
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+
+MemManage_Handler     PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+
+BusFault_Handler PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+
+UsageFault_Handler PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+
+DebugMon_Handler PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+WDT_BOD_IRQHandler\
+                PROC
+                EXPORT     WDT_BOD_IRQHandler        [WEAK]
+                LDR        R0, =WDT_BOD_DriverIRQHandler
+                BX         R0
+                ENDP
+
+DMA0_IRQHandler\
+                PROC
+                EXPORT     DMA0_IRQHandler        [WEAK]
+                LDR        R0, =DMA0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+GINT0_IRQHandler\
+                PROC
+                EXPORT     GINT0_IRQHandler        [WEAK]
+                LDR        R0, =GINT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+GINT1_IRQHandler\
+                PROC
+                EXPORT     GINT1_IRQHandler        [WEAK]
+                LDR        R0, =GINT1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT0_IRQHandler\
+                PROC
+                EXPORT     PIN_INT0_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT1_IRQHandler\
+                PROC
+                EXPORT     PIN_INT1_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT2_IRQHandler\
+                PROC
+                EXPORT     PIN_INT2_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT3_IRQHandler\
+                PROC
+                EXPORT     PIN_INT3_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+UTICK0_IRQHandler\
+                PROC
+                EXPORT     UTICK0_IRQHandler        [WEAK]
+                LDR        R0, =UTICK0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+MRT0_IRQHandler\
+                PROC
+                EXPORT     MRT0_IRQHandler        [WEAK]
+                LDR        R0, =MRT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER0_IRQHandler\
+                PROC
+                EXPORT     CTIMER0_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER1_IRQHandler\
+                PROC
+                EXPORT     CTIMER1_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SCT0_IRQHandler\
+                PROC
+                EXPORT     SCT0_IRQHandler        [WEAK]
+                LDR        R0, =SCT0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER3_IRQHandler\
+                PROC
+                EXPORT     CTIMER3_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM0_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM0_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM1_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM1_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM2_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM2_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM3_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM3_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM3_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM4_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM4_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM5_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM5_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM5_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM6_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM6_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM6_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM7_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM7_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM7_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_SEQA_IRQHandler\
+                PROC
+                EXPORT     ADC0_SEQA_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_SEQA_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_SEQB_IRQHandler\
+                PROC
+                EXPORT     ADC0_SEQB_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_SEQB_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ADC0_THCMP_IRQHandler\
+                PROC
+                EXPORT     ADC0_THCMP_IRQHandler        [WEAK]
+                LDR        R0, =ADC0_THCMP_DriverIRQHandler
+                BX         R0
+                ENDP
+
+DMIC0_IRQHandler\
+                PROC
+                EXPORT     DMIC0_IRQHandler        [WEAK]
+                LDR        R0, =DMIC0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+HWVAD0_IRQHandler\
+                PROC
+                EXPORT     HWVAD0_IRQHandler        [WEAK]
+                LDR        R0, =HWVAD0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB0_NEEDCLK_IRQHandler\
+                PROC
+                EXPORT     USB0_NEEDCLK_IRQHandler        [WEAK]
+                LDR        R0, =USB0_NEEDCLK_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB0_IRQHandler\
+                PROC
+                EXPORT     USB0_IRQHandler        [WEAK]
+                LDR        R0, =USB0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+RTC_IRQHandler\
+                PROC
+                EXPORT     RTC_IRQHandler        [WEAK]
+                LDR        R0, =RTC_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Reserved46_IRQHandler\
+                PROC
+                EXPORT     Reserved46_IRQHandler        [WEAK]
+                LDR        R0, =Reserved46_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Reserved47_IRQHandler\
+                PROC
+                EXPORT     Reserved47_IRQHandler        [WEAK]
+                LDR        R0, =Reserved47_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT4_IRQHandler\
+                PROC
+                EXPORT     PIN_INT4_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT5_IRQHandler\
+                PROC
+                EXPORT     PIN_INT5_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT5_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT6_IRQHandler\
+                PROC
+                EXPORT     PIN_INT6_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT6_DriverIRQHandler
+                BX         R0
+                ENDP
+
+PIN_INT7_IRQHandler\
+                PROC
+                EXPORT     PIN_INT7_IRQHandler        [WEAK]
+                LDR        R0, =PIN_INT7_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER2_IRQHandler\
+                PROC
+                EXPORT     CTIMER2_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER2_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CTIMER4_IRQHandler\
+                PROC
+                EXPORT     CTIMER4_IRQHandler        [WEAK]
+                LDR        R0, =CTIMER4_DriverIRQHandler
+                BX         R0
+                ENDP
+
+RIT_IRQHandler\
+                PROC
+                EXPORT     RIT_IRQHandler        [WEAK]
+                LDR        R0, =RIT_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SPIFI0_IRQHandler\
+                PROC
+                EXPORT     SPIFI0_IRQHandler        [WEAK]
+                LDR        R0, =SPIFI0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM8_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM8_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM8_DriverIRQHandler
+                BX         R0
+                ENDP
+
+FLEXCOMM9_IRQHandler\
+                PROC
+                EXPORT     FLEXCOMM9_IRQHandler        [WEAK]
+                LDR        R0, =FLEXCOMM9_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SDIO_IRQHandler\
+                PROC
+                EXPORT     SDIO_IRQHandler        [WEAK]
+                LDR        R0, =SDIO_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN0_IRQ0_IRQHandler\
+                PROC
+                EXPORT     CAN0_IRQ0_IRQHandler        [WEAK]
+                LDR        R0, =CAN0_IRQ0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN0_IRQ1_IRQHandler\
+                PROC
+                EXPORT     CAN0_IRQ1_IRQHandler        [WEAK]
+                LDR        R0, =CAN0_IRQ1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN1_IRQ0_IRQHandler\
+                PROC
+                EXPORT     CAN1_IRQ0_IRQHandler        [WEAK]
+                LDR        R0, =CAN1_IRQ0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+CAN1_IRQ1_IRQHandler\
+                PROC
+                EXPORT     CAN1_IRQ1_IRQHandler        [WEAK]
+                LDR        R0, =CAN1_IRQ1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB1_IRQHandler\
+                PROC
+                EXPORT     USB1_IRQHandler        [WEAK]
+                LDR        R0, =USB1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+USB1_NEEDCLK_IRQHandler\
+                PROC
+                EXPORT     USB1_NEEDCLK_IRQHandler        [WEAK]
+                LDR        R0, =USB1_NEEDCLK_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ETHERNET_IRQHandler\
+                PROC
+                EXPORT     ETHERNET_IRQHandler        [WEAK]
+                LDR        R0, =ETHERNET_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ETHERNET_PMT_IRQHandler\
+                PROC
+                EXPORT     ETHERNET_PMT_IRQHandler        [WEAK]
+                LDR        R0, =ETHERNET_PMT_DriverIRQHandler
+                BX         R0
+                ENDP
+
+ETHERNET_MACLP_IRQHandler\
+                PROC
+                EXPORT     ETHERNET_MACLP_IRQHandler        [WEAK]
+                LDR        R0, =ETHERNET_MACLP_DriverIRQHandler
+                BX         R0
+                ENDP
+
+EEPROM_IRQHandler\
+                PROC
+                EXPORT     EEPROM_IRQHandler        [WEAK]
+                LDR        R0, =EEPROM_DriverIRQHandler
+                BX         R0
+                ENDP
+
+LCD_IRQHandler\
+                PROC
+                EXPORT     LCD_IRQHandler        [WEAK]
+                LDR        R0, =LCD_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SHA_IRQHandler\
+                PROC
+                EXPORT     SHA_IRQHandler        [WEAK]
+                LDR        R0, =SHA_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SMARTCARD0_IRQHandler\
+                PROC
+                EXPORT     SMARTCARD0_IRQHandler        [WEAK]
+                LDR        R0, =SMARTCARD0_DriverIRQHandler
+                BX         R0
+                ENDP
+
+SMARTCARD1_IRQHandler\
+                PROC
+                EXPORT     SMARTCARD1_IRQHandler        [WEAK]
+                LDR        R0, =SMARTCARD1_DriverIRQHandler
+                BX         R0
+                ENDP
+
+Default_Handler PROC
+                EXPORT     WDT_BOD_DriverIRQHandler        [WEAK]
+                EXPORT     DMA0_DriverIRQHandler        [WEAK]
+                EXPORT     GINT0_DriverIRQHandler        [WEAK]
+                EXPORT     GINT1_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT0_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT1_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT2_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT3_DriverIRQHandler        [WEAK]
+                EXPORT     UTICK0_DriverIRQHandler        [WEAK]
+                EXPORT     MRT0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER1_DriverIRQHandler        [WEAK]
+                EXPORT     SCT0_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER3_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM0_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM1_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM2_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM3_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM4_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM5_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM6_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM7_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_SEQA_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_SEQB_DriverIRQHandler        [WEAK]
+                EXPORT     ADC0_THCMP_DriverIRQHandler        [WEAK]
+                EXPORT     DMIC0_DriverIRQHandler        [WEAK]
+                EXPORT     HWVAD0_DriverIRQHandler        [WEAK]
+                EXPORT     USB0_NEEDCLK_DriverIRQHandler        [WEAK]
+                EXPORT     USB0_DriverIRQHandler        [WEAK]
+                EXPORT     RTC_DriverIRQHandler        [WEAK]
+                EXPORT     Reserved46_DriverIRQHandler        [WEAK]
+                EXPORT     Reserved47_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT4_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT5_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT6_DriverIRQHandler        [WEAK]
+                EXPORT     PIN_INT7_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER2_DriverIRQHandler        [WEAK]
+                EXPORT     CTIMER4_DriverIRQHandler        [WEAK]
+                EXPORT     RIT_DriverIRQHandler        [WEAK]
+                EXPORT     SPIFI0_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM8_DriverIRQHandler        [WEAK]
+                EXPORT     FLEXCOMM9_DriverIRQHandler        [WEAK]
+                EXPORT     SDIO_DriverIRQHandler        [WEAK]
+                EXPORT     CAN0_IRQ0_DriverIRQHandler        [WEAK]
+                EXPORT     CAN0_IRQ1_DriverIRQHandler        [WEAK]
+                EXPORT     CAN1_IRQ0_DriverIRQHandler        [WEAK]
+                EXPORT     CAN1_IRQ1_DriverIRQHandler        [WEAK]
+                EXPORT     USB1_DriverIRQHandler        [WEAK]
+                EXPORT     USB1_NEEDCLK_DriverIRQHandler        [WEAK]
+                EXPORT     ETHERNET_DriverIRQHandler        [WEAK]
+                EXPORT     ETHERNET_PMT_DriverIRQHandler        [WEAK]
+                EXPORT     ETHERNET_MACLP_DriverIRQHandler        [WEAK]
+                EXPORT     EEPROM_DriverIRQHandler        [WEAK]
+                EXPORT     LCD_DriverIRQHandler        [WEAK]
+                EXPORT     SHA_DriverIRQHandler        [WEAK]
+                EXPORT     SMARTCARD0_DriverIRQHandler        [WEAK]
+                EXPORT     SMARTCARD1_DriverIRQHandler        [WEAK]
+
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+                END
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/sys.cpp	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,288 @@
+/*
+** ###################################################################
+**     Processors:          LPC54608J512
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    LPC54608 Series Reference Manual, Rev. 0 , 06/2017
+**     Version:             rev. 1.0, 2017-6-06
+**     Build:               b161214
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright (c) 2016 - 2017 , NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Copyright (c) 2016 NXP Semiconductors, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of NXP Semiconductors, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+__ram_vector_table__ = 1;
+
+__stack_size__ = 0x8000;
+__heap_size__ = 0xC000;
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x400 : 0x0;
+
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x00000400, LENGTH = 0x0007FC00
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00028000
+  m_sramx               (RW)  : ORIGIN = 0x04000000, LENGTH = 0x00008000
+  m_usb_sram            (RW)  : ORIGIN = 0x40100000, LENGTH = 0x00002000
+
+
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.ramfunc*)             /* for functions in ram */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  m_usb_bdt (NOLOAD) :
+  {
+    . = ALIGN(512);
+    *(m_usb_bdt)
+  } > m_usb_sram
+
+  m_usb_global (NOLOAD) :
+  {
+    *(m_usb_global)
+  } > m_usb_sram
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,892 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_LPC54608.S                                                          */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            LPC54608                                                                    */
+/*  @version: 1.0                                                                         */
+/*  @date:    2017-6-6                                                                    */
+/*  @build:   b161214                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.                              */
+/* Copyright (c) 2016 - 2017 , NXP                                                        */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of copyright holder nor the names of its                            */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*                                                                                        */
+/* Copyright (c) 2016 , NXP Semiconductors, Inc.                                          */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of NXP Semiconductors, Inc. nor the names of its                    */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler */
+    .long   HardFault_Handler                               /* Hard Fault Handler */
+    .long   MemManage_Handler                               /* MPU Fault Handler */
+    .long   BusFault_Handler                                /* Bus Fault Handler */
+    .long   UsageFault_Handler                              /* Usage Fault Handler */
+    .long   0                                               /* Reserved */
+    .long   0xFFFFFFFF                                      /* ECRP */
+    .long   0                                               /* Reserved */
+    .long   0                                               /* Reserved */
+    .long   SVC_Handler                                     /* SVCall Handler */
+    .long   DebugMon_Handler                                /* Debug Monitor Handler */
+    .long   0
+    .long   PendSV_Handler                                  /* PendSV Handler */
+    .long   SysTick_Handler                                 /* SysTick Handler */
+
+     /* External Interrupts */
+    .long   WDT_BOD_IRQHandler                              /* Windowed watchdog timer, Brownout detect */
+    .long   DMA0_IRQHandler                                 /* DMA controller */
+    .long   GINT0_IRQHandler                                /* GPIO group 0 */
+    .long   GINT1_IRQHandler                                /* GPIO group 1 */
+    .long   PIN_INT0_IRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
+    .long   PIN_INT1_IRQHandler                             /* Pin interrupt 1 or pattern match engine slice 1 */
+    .long   PIN_INT2_IRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
+    .long   PIN_INT3_IRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
+    .long   UTICK0_IRQHandler                               /* Micro-tick Timer */
+    .long   MRT0_IRQHandler                                 /* Multi-rate timer */
+    .long   CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
+    .long   CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
+    .long   SCT0_IRQHandler                                 /* SCTimer/PWM */
+    .long   CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
+    .long   FLEXCOMM0_IRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM1_IRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM2_IRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM3_IRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM4_IRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM5_IRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+    .long   FLEXCOMM6_IRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    .long   FLEXCOMM7_IRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    .long   ADC0_SEQA_IRQHandler                            /* ADC0 sequence A completion. */
+    .long   ADC0_SEQB_IRQHandler                            /* ADC0 sequence B completion. */
+    .long   ADC0_THCMP_IRQHandler                           /* ADC0 threshold compare and error. */
+    .long   DMIC0_IRQHandler                                /* Digital microphone and DMIC subsystem */
+    .long   HWVAD0_IRQHandler                               /* Hardware Voice Activity Detector */
+    .long   USB0_NEEDCLK_IRQHandler                         /* USB Activity Wake-up Interrupt */
+    .long   USB0_IRQHandler                                 /* USB device */
+    .long   RTC_IRQHandler                                  /* RTC alarm and wake-up interrupts */
+    .long   0                                               /* Reserved interrupt */
+    .long   0                                               /* Reserved interrupt */
+    .long   PIN_INT4_IRQHandler                             /* Pin interrupt 4 or pattern match engine slice 4 int */
+    .long   PIN_INT5_IRQHandler                             /* Pin interrupt 5 or pattern match engine slice 5 int */
+    .long   PIN_INT6_IRQHandler                             /* Pin interrupt 6 or pattern match engine slice 6 int */
+    .long   PIN_INT7_IRQHandler                             /* Pin interrupt 7 or pattern match engine slice 7 int */
+    .long   CTIMER2_IRQHandler                              /* Standard counter/timer CTIMER2 */
+    .long   CTIMER4_IRQHandler                              /* Standard counter/timer CTIMER4 */
+    .long   RIT_IRQHandler                                  /* Repetitive Interrupt Timer */
+    .long   SPIFI0_IRQHandler                               /* SPI flash interface */
+    .long   FLEXCOMM8_IRQHandler                            /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+    .long   FLEXCOMM9_IRQHandler                            /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+    .long   SDIO_IRQHandler                                 /* SD/MMC */
+    .long   CAN0_IRQ0_IRQHandler                            /* CAN0 interrupt0 */
+    .long   CAN0_IRQ1_IRQHandler                            /* CAN0 interrupt1 */
+    .long   CAN1_IRQ0_IRQHandler                            /* CAN1 interrupt0 */
+    .long   CAN1_IRQ1_IRQHandler                            /* CAN1 interrupt1 */
+    .long   USB1_IRQHandler                                 /* USB1 interrupt */
+    .long   USB1_NEEDCLK_IRQHandler                         /* USB1 activity */
+    .long   ETHERNET_IRQHandler                             /* Ethernet */
+    .long   ETHERNET_PMT_IRQHandler                         /* Ethernet power management interrupt */
+    .long   ETHERNET_MACLP_IRQHandler                       /* Ethernet MAC interrupt */
+    .long   EEPROM_IRQHandler                               /* EEPROM interrupt */
+    .long   LCD_IRQHandler                                  /* LCD interrupt */
+    .long   SHA_IRQHandler                                  /* SHA interrupt */
+    .long   SMARTCARD0_IRQHandler                           /* Smart card 0 interrupt */
+    .long   SMARTCARD1_IRQHandler                           /* Smart card 1 interrupt */
+    .size   __Vectors, . - __Vectors
+
+
+    
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+
+    /*      Loop to copy data from read only memory to RAM. The ranges
+     *      of copy from/to are specified by following symbols evaluated in
+     *      linker script.
+     *      __etext: End of code section, i.e., begin of data sections to copy from.
+     *      __data_start__/__data_end__: RAM address range that data should be
+     *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+#if 1
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one.
+ * Change to "#if 0" to use the second one */
+.LC0:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC0
+#else
+    subs    r3, r2
+    ble    .LC1
+.LC0:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC0
+.LC1:
+#endif
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    movs    r0, 0
+.LC2:
+    cmp     r1, r2
+    itt    lt
+    strlt   r0, [r1], #4
+    blt    .LC2
+#endif /* __STARTUP_CLEAR_BSS */
+
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak MemManage_Handler
+    .type MemManage_Handler, %function
+MemManage_Handler:
+    ldr   r0,=MemManage_Handler
+    bx    r0
+    .size MemManage_Handler, . - MemManage_Handler
+
+    .align 1
+    .thumb_func
+    .weak BusFault_Handler
+    .type BusFault_Handler, %function
+BusFault_Handler:
+    ldr   r0,=BusFault_Handler
+    bx    r0
+    .size BusFault_Handler, . - BusFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak UsageFault_Handler
+    .type UsageFault_Handler, %function
+UsageFault_Handler:
+    ldr   r0,=UsageFault_Handler
+    bx    r0
+    .size UsageFault_Handler, . - UsageFault_Handler
+    
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak DebugMon_Handler
+    .type DebugMon_Handler, %function
+DebugMon_Handler:
+    ldr   r0,=DebugMon_Handler
+    bx    r0
+    .size DebugMon_Handler, . - DebugMon_Handler
+    
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak WDT_BOD_IRQHandler
+    .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+    ldr   r0,=WDT_BOD_DriverIRQHandler
+    bx    r0
+    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT0_IRQHandler
+    .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+    ldr   r0,=GINT0_DriverIRQHandler
+    bx    r0
+    .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT1_IRQHandler
+    .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+    ldr   r0,=GINT1_DriverIRQHandler
+    bx    r0
+    .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT0_IRQHandler
+    .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+    ldr   r0,=PIN_INT0_DriverIRQHandler
+    bx    r0
+    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT1_IRQHandler
+    .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+    ldr   r0,=PIN_INT1_DriverIRQHandler
+    bx    r0
+    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT2_IRQHandler
+    .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+    ldr   r0,=PIN_INT2_DriverIRQHandler
+    bx    r0
+    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT3_IRQHandler
+    .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+    ldr   r0,=PIN_INT3_DriverIRQHandler
+    bx    r0
+    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UTICK0_IRQHandler
+    .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+    ldr   r0,=UTICK0_DriverIRQHandler
+    bx    r0
+    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MRT0_IRQHandler
+    .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+    ldr   r0,=MRT0_DriverIRQHandler
+    bx    r0
+    .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER0_IRQHandler
+    .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+    ldr   r0,=CTIMER0_DriverIRQHandler
+    bx    r0
+    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER1_IRQHandler
+    .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+    ldr   r0,=CTIMER1_DriverIRQHandler
+    bx    r0
+    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SCT0_IRQHandler
+    .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+    ldr   r0,=SCT0_DriverIRQHandler
+    bx    r0
+    .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER3_IRQHandler
+    .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+    ldr   r0,=CTIMER3_DriverIRQHandler
+    bx    r0
+    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM0_IRQHandler
+    .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+    ldr   r0,=FLEXCOMM0_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM1_IRQHandler
+    .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+    ldr   r0,=FLEXCOMM1_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM2_IRQHandler
+    .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+    ldr   r0,=FLEXCOMM2_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM3_IRQHandler
+    .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+    ldr   r0,=FLEXCOMM3_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM4_IRQHandler
+    .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+    ldr   r0,=FLEXCOMM4_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM5_IRQHandler
+    .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+    ldr   r0,=FLEXCOMM5_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM6_IRQHandler
+    .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+    ldr   r0,=FLEXCOMM6_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM7_IRQHandler
+    .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+    ldr   r0,=FLEXCOMM7_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQA_IRQHandler
+    .type ADC0_SEQA_IRQHandler, %function
+ADC0_SEQA_IRQHandler:
+    ldr   r0,=ADC0_SEQA_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_SEQB_IRQHandler
+    .type ADC0_SEQB_IRQHandler, %function
+ADC0_SEQB_IRQHandler:
+    ldr   r0,=ADC0_SEQB_DriverIRQHandler
+    bx    r0
+    .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_THCMP_IRQHandler
+    .type ADC0_THCMP_IRQHandler, %function
+ADC0_THCMP_IRQHandler:
+    ldr   r0,=ADC0_THCMP_DriverIRQHandler
+    bx    r0
+    .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMIC0_IRQHandler
+    .type DMIC0_IRQHandler, %function
+DMIC0_IRQHandler:
+    ldr   r0,=DMIC0_DriverIRQHandler
+    bx    r0
+    .size DMIC0_IRQHandler, . - DMIC0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak HWVAD0_IRQHandler
+    .type HWVAD0_IRQHandler, %function
+HWVAD0_IRQHandler:
+    ldr   r0,=HWVAD0_DriverIRQHandler
+    bx    r0
+    .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_NEEDCLK_IRQHandler
+    .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_IRQHandler
+    .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+    ldr   r0,=USB0_DriverIRQHandler
+    bx    r0
+    .size USB0_IRQHandler, . - USB0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RTC_IRQHandler
+    .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+    ldr   r0,=RTC_DriverIRQHandler
+    bx    r0
+    .size RTC_IRQHandler, . - RTC_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT4_IRQHandler
+    .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+    ldr   r0,=PIN_INT4_DriverIRQHandler
+    bx    r0
+    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak PIN_INT5_IRQHandler
+    .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+    ldr   r0,=PIN_INT5_DriverIRQHandler
+    bx    r0
+    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT6_IRQHandler
+    .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+    ldr   r0,=PIN_INT6_DriverIRQHandler
+    bx    r0
+    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT7_IRQHandler
+    .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+    ldr   r0,=PIN_INT7_DriverIRQHandler
+    bx    r0
+    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CTIMER2_IRQHandler
+    .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+    ldr   r0,=CTIMER2_DriverIRQHandler
+    bx    r0
+    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CTIMER4_IRQHandler
+    .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+    ldr   r0,=CTIMER4_DriverIRQHandler
+    bx    r0
+    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RIT_IRQHandler
+    .type RIT_IRQHandler, %function
+RIT_IRQHandler:
+    ldr   r0,=RIT_DriverIRQHandler
+    bx    r0
+    .size RIT_IRQHandler, . - RIT_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SPIFI0_IRQHandler
+    .type SPIFI0_IRQHandler, %function
+SPIFI0_IRQHandler:
+    ldr   r0,=SPIFI0_DriverIRQHandler
+    bx    r0
+    .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler
+ 
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM8_IRQHandler
+    .type FLEXCOMM8_IRQHandler, %function
+FLEXCOMM8_IRQHandler:
+    ldr   r0,=FLEXCOMM8_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM9_IRQHandler
+    .type FLEXCOMM9_IRQHandler, %function
+FLEXCOMM9_IRQHandler:
+    ldr   r0,=FLEXCOMM9_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM9_IRQHandler, . - FLEXCOMM9_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SDIO_IRQHandler
+    .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+    ldr   r0,=SDIO_DriverIRQHandler
+    bx    r0
+    .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CAN0_IRQ0_IRQHandler
+    .type CAN0_IRQ0_IRQHandler, %function
+CAN0_IRQ0_IRQHandler:
+    ldr   r0,=CAN0_IRQ0_DriverIRQHandler
+    bx    r0
+    .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CAN0_IRQ1_IRQHandler
+    .type CAN0_IRQ1_IRQHandler, %function
+CAN0_IRQ1_IRQHandler:
+    ldr   r0,=CAN0_IRQ1_DriverIRQHandler
+    bx    r0
+    .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CAN1_IRQ0_IRQHandler
+    .type CAN1_IRQ0_IRQHandler, %function
+CAN1_IRQ0_IRQHandler:
+    ldr   r0,=CAN1_IRQ0_DriverIRQHandler
+    bx    r0
+    .size CAN1_IRQ0_IRQHandler, . - CAN1_IRQ0_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak CAN1_IRQ1_IRQHandler
+    .type CAN1_IRQ1_IRQHandler, %function
+CAN1_IRQ1_IRQHandler:
+    ldr   r0,=CAN1_IRQ1_DriverIRQHandler
+    bx    r0
+    .size CAN1_IRQ1_IRQHandler, . - CAN1_IRQ1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_IRQHandler
+    .type USB1_IRQHandler, %function
+USB1_IRQHandler:
+    ldr   r0,=USB1_DriverIRQHandler
+    bx    r0
+    .size USB1_IRQHandler, . - USB1_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak USB1_NEEDCLK_IRQHandler
+    .type USB1_NEEDCLK_IRQHandler, %function
+USB1_NEEDCLK_IRQHandler:
+    ldr   r0,=USB1_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak ETHERNET_IRQHandler
+    .type ETHERNET_IRQHandler, %function
+ETHERNET_IRQHandler:
+    ldr   r0,=ETHERNET_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_IRQHandler, . - ETHERNET_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak ETHERNET_PMT_IRQHandler
+    .type ETHERNET_PMT_IRQHandler, %function
+ETHERNET_PMT_IRQHandler:
+    ldr   r0,=ETHERNET_PMT_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_PMT_IRQHandler, . - ETHERNET_PMT_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak ETHERNET_MACLP_IRQHandler
+    .type ETHERNET_MACLP_IRQHandler, %function
+ETHERNET_MACLP_IRQHandler:
+    ldr   r0,=ETHERNET_MACLP_DriverIRQHandler
+    bx    r0
+    .size ETHERNET_MACLP_IRQHandler, . - ETHERNET_MACLP_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak EEPROM_IRQHandler
+    .type EEPROM_IRQHandler, %function
+EEPROM_IRQHandler:
+    ldr   r0,=EEPROM_DriverIRQHandler
+    bx    r0
+    .size EEPROM_IRQHandler, . - EEPROM_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak LCD_IRQHandler
+    .type LCD_IRQHandler, %function
+LCD_IRQHandler:
+    ldr   r0,=LCD_DriverIRQHandler
+    bx    r0
+    .size LCD_IRQHandler, . - LCD_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SHA_IRQHandler
+    .type SHA_IRQHandler, %function
+SHA_IRQHandler:
+    ldr   r0,=SHA_DriverIRQHandler
+    bx    r0
+    .size SHA_IRQHandler, . - SHA_IRQHandler
+    
+    .align 1
+    .thumb_func
+    .weak SMARTCARD0_IRQHandler
+    .type SMARTCARD0_IRQHandler, %function
+SMARTCARD0_IRQHandler:
+    ldr   r0,=SMARTCARD0_DriverIRQHandler
+    bx    r0
+    .size SMARTCARD0_IRQHandler, . - SMARTCARD0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SMARTCARD1_IRQHandler
+    .type SMARTCARD1_IRQHandler, %function
+SMARTCARD1_IRQHandler:
+    ldr   r0,=SMARTCARD1_DriverIRQHandler
+    bx    r0
+    .size SMARTCARD1_IRQHandler, . - SMARTCARD1_IRQHandler
+    
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler   WDT_BOD_DriverIRQHandler                              /* Windowed watchdog timer, Brownout detect */
+    def_irq_handler   DMA0_DriverIRQHandler                                 /* DMA controller */
+    def_irq_handler   GINT0_DriverIRQHandler                                /* GPIO group 0 */
+    def_irq_handler   GINT1_DriverIRQHandler                                /* GPIO group 1 */
+    def_irq_handler   PIN_INT0_DriverIRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
+    def_irq_handler   PIN_INT1_DriverIRQHandler                             /* Pin interrupt 1or pattern match engine slice 1 */
+    def_irq_handler   PIN_INT2_DriverIRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
+    def_irq_handler   PIN_INT3_DriverIRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
+    def_irq_handler   UTICK0_DriverIRQHandler                               /* Micro-tick Timer */
+    def_irq_handler   MRT0_DriverIRQHandler                                 /* Multi-rate timer */
+    def_irq_handler   CTIMER0_DriverIRQHandler                              /* Standard counter/timer CTIMER0 */
+    def_irq_handler   CTIMER1_DriverIRQHandler                              /* Standard counter/timer CTIMER1 */
+    def_irq_handler   SCT0_DriverIRQHandler                                 /* SCTimer/PWM */
+    def_irq_handler   CTIMER3_DriverIRQHandler                              /* Standard counter/timer CTIMER3 */
+    def_irq_handler   FLEXCOMM0_DriverIRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM1_DriverIRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM2_DriverIRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM3_DriverIRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM4_DriverIRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM5_DriverIRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM6_DriverIRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM7_DriverIRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+    def_irq_handler   ADC0_SEQA_DriverIRQHandler                            /* ADC0 sequence A completion. */
+    def_irq_handler   ADC0_SEQB_DriverIRQHandler                            /* ADC0 sequence B completion. */
+    def_irq_handler   ADC0_THCMP_DriverIRQHandler                           /* ADC0 threshold compare and error. */
+    def_irq_handler   DMIC0_DriverIRQHandler                                /* Digital microphone and DMIC subsystem */
+    def_irq_handler   HWVAD0_DriverIRQHandler                               /* Hardware Voice Activity Detector */
+    def_irq_handler   USB0_NEEDCLK_DriverIRQHandler                         /* USB Activity Wake-up Interrupt */
+    def_irq_handler   USB0_DriverIRQHandler                                 /* USB device */
+    def_irq_handler   RTC_DriverIRQHandler                                  /* RTC alarm and wake-up interrupts */
+    def_irq_handler   Reserved46_DriverIRQHandler                           /* Reserved interrupt */
+    def_irq_handler   Reserved47_DriverIRQHandler                           /* Reserved interrupt */
+    def_irq_handler   PIN_INT4_DriverIRQHandler                             /* Pin interrupt 4 or pattern match engine slice 4 int */
+    def_irq_handler   PIN_INT5_DriverIRQHandler                             /* Pin interrupt 5 or pattern match engine slice 5 int */
+    def_irq_handler   PIN_INT6_DriverIRQHandler                             /* Pin interrupt 6 or pattern match engine slice 6 int */
+    def_irq_handler   PIN_INT7_DriverIRQHandler                             /* Pin interrupt 7 or pattern match engine slice 7 int */
+    def_irq_handler   CTIMER2_DriverIRQHandler                              /* Standard counter/timer CTIMER2 */
+    def_irq_handler   CTIMER4_DriverIRQHandler                              /* Standard counter/timer CTIMER4 */
+    def_irq_handler   RIT_DriverIRQHandler                                  /* Repetitive Interrupt Timer */
+    def_irq_handler   SPIFI0_DriverIRQHandler                               /* SPI flash interface */
+    def_irq_handler   FLEXCOMM8_DriverIRQHandler                            /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   FLEXCOMM9_DriverIRQHandler                            /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+    def_irq_handler   SDIO_DriverIRQHandler                                 /* SD/MMC */
+    def_irq_handler   CAN0_IRQ0_DriverIRQHandler                            /* CAN0 interrupt0 */
+    def_irq_handler   CAN0_IRQ1_DriverIRQHandler                            /* CAN0 interrupt1 */
+    def_irq_handler   CAN1_IRQ0_DriverIRQHandler                            /* CAN1 interrupt0 */
+    def_irq_handler   CAN1_IRQ1_DriverIRQHandler                            /* CAN1 interrupt1 */
+    def_irq_handler   USB1_DriverIRQHandler                                 /* USB1 interrupt */
+    def_irq_handler   USB1_NEEDCLK_DriverIRQHandler                         /* USB1 activity */
+    def_irq_handler   ETHERNET_DriverIRQHandler                             /* Ethernet */
+    def_irq_handler   ETHERNET_PMT_DriverIRQHandler                         /* Ethernet power management interrupt */
+    def_irq_handler   ETHERNET_MACLP_DriverIRQHandler                       /* Ethernet MAC interrupt */
+    def_irq_handler   EEPROM_DriverIRQHandler                               /* EEPROM interrupt */
+    def_irq_handler   LCD_DriverIRQHandler                                  /* LCD interrupt */
+    def_irq_handler   SHA_DriverIRQHandler                                  /* SHA interrupt */
+    def_irq_handler   SMARTCARD0_DriverIRQHandler                           /* Smart card 0 interrupt */
+    def_irq_handler   SMARTCARD1_DriverIRQHandler                           /* Smart card 1 interrupt */
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,123 @@
+/*
+** ###################################################################
+**     Processors:          LPC54608J512BD208
+**                          LPC54608J512ET180
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b161227
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+define symbol __ram_vector_table__ = 1;
+
+define symbol __stack_size__=0x8000;
+define symbol __heap_size__=0xC000;
+
+define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
+define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
+
+define symbol m_interrupts_start       = 0x00000000;
+define symbol m_interrupts_end         = 0x000003FF;
+
+define symbol m_text_start             = 0x00000400;
+define symbol m_text_end               = 0x0007FFFF;
+
+define symbol m_interrupts_ram_start   = 0x20000000;
+define symbol m_interrupts_ram_end     = 0x20000000 + __ram_vector_table_offset__;
+
+define symbol m_data_start             = m_interrupts_ram_start + __ram_vector_table_size__;
+define symbol m_data_end               = 0x20027FFF;
+
+define symbol m_usb_sram_start         = 0x40100000;
+define symbol m_usb_sram_end           = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size             = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE  = m_interrupts_start;
+define exported symbol __VECTOR_RAM    = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region                     { section m_usb_bdt };
+place in USB_SRAM_region                    { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  /* Required in a multi-threaded application */
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize  { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in CSTACK_region                      { block CSTACK };
+place in m_interrupts_ram_region            { section m_interrupts_ram };
+

Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,615 @@
+;/*****************************************************************************
+; * @file:    startup_LPC54608.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File
+; *           LPC54608
+; * @version: 1.1
+; * @date:    2016-11-25
+; *----------------------------------------------------------------------------
+; *
+; * Copyright 1997 - 2016 Freescale Semiconductor.
+; * Copyright 2016 - 2017 NXP
+; *
+; Redistribution and use in source and binary forms, with or without modification,
+; are permitted provided that the following conditions are met:
+;
+; o Redistributions of source code must retain the above copyright notice, this list
+;   of conditions and the following disclaimer.
+;
+; o Redistributions in binary form must reproduce the above copyright notice, this
+;   list of conditions and the following disclaimer in the documentation and/or
+;   other materials provided with the distribution.
+;
+; o Neither the name of the copyright holder nor the names of its
+;   contributors may be used to endorse or promote products derived from this
+;   software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0xFFFFFFFF ;ECRP
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     WDT_BOD_IRQHandler  ; Windowed watchdog timer, Brownout detect
+        DCD     DMA0_IRQHandler  ; DMA controller
+        DCD     GINT0_IRQHandler  ; GPIO group 0
+        DCD     GINT1_IRQHandler  ; GPIO group 1
+        DCD     PIN_INT0_IRQHandler  ; Pin interrupt 0 or pattern match engine slice 0
+        DCD     PIN_INT1_IRQHandler  ; Pin interrupt 1or pattern match engine slice 1
+        DCD     PIN_INT2_IRQHandler  ; Pin interrupt 2 or pattern match engine slice 2
+        DCD     PIN_INT3_IRQHandler  ; Pin interrupt 3 or pattern match engine slice 3
+        DCD     UTICK0_IRQHandler  ; Micro-tick Timer
+        DCD     MRT0_IRQHandler  ; Multi-rate timer
+        DCD     CTIMER0_IRQHandler  ; Standard counter/timer CTIMER0
+        DCD     CTIMER1_IRQHandler  ; Standard counter/timer CTIMER1
+        DCD     SCT0_IRQHandler  ; SCTimer/PWM
+        DCD     CTIMER3_IRQHandler  ; Standard counter/timer CTIMER3
+        DCD     FLEXCOMM0_IRQHandler  ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM1_IRQHandler  ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM2_IRQHandler  ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM3_IRQHandler  ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM4_IRQHandler  ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM5_IRQHandler  ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+        DCD     FLEXCOMM6_IRQHandler  ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     FLEXCOMM7_IRQHandler  ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+        DCD     ADC0_SEQA_IRQHandler  ; ADC0 sequence A completion.
+        DCD     ADC0_SEQB_IRQHandler  ; ADC0 sequence B completion.
+        DCD     ADC0_THCMP_IRQHandler  ; ADC0 threshold compare and error.
+        DCD     DMIC0_IRQHandler  ; Digital microphone and DMIC subsystem
+        DCD     HWVAD0_IRQHandler  ; Hardware Voice Activity Detector
+        DCD     USB0_NEEDCLK_IRQHandler  ; USB Activity Wake-up Interrupt
+        DCD     USB0_IRQHandler  ; USB device
+        DCD     RTC_IRQHandler  ; RTC alarm and wake-up interrupts
+        DCD     Reserved46_IRQHandler  ; Reserved interrupt
+        DCD     Reserved47_IRQHandler  ; Reserved interrupt
+        DCD     PIN_INT4_IRQHandler  ; Pin interrupt 4 or pattern match engine slice 4 int
+        DCD     PIN_INT5_IRQHandler  ; Pin interrupt 5 or pattern match engine slice 5 int
+        DCD     PIN_INT6_IRQHandler  ; Pin interrupt 6 or pattern match engine slice 6 int
+        DCD     PIN_INT7_IRQHandler  ; Pin interrupt 7 or pattern match engine slice 7 int
+        DCD     CTIMER2_IRQHandler  ; Standard counter/timer CTIMER2
+        DCD     CTIMER4_IRQHandler  ; Standard counter/timer CTIMER4
+        DCD     RIT_IRQHandler  ; Repetitive Interrupt Timer
+        DCD     SPIFI0_IRQHandler  ; SPI flash interface
+        DCD     FLEXCOMM8_IRQHandler  ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+        DCD     FLEXCOMM9_IRQHandler  ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+        DCD     SDIO_IRQHandler  ; SD/MMC
+        DCD     CAN0_IRQ0_IRQHandler  ; CAN0 interrupt0
+        DCD     CAN0_IRQ1_IRQHandler  ; CAN0 interrupt1
+        DCD     CAN1_IRQ0_IRQHandler  ; CAN1 interrupt0
+        DCD     CAN1_IRQ1_IRQHandler  ; CAN1 interrupt1
+        DCD     USB1_IRQHandler  ; USB1 interrupt
+        DCD     USB1_NEEDCLK_IRQHandler  ; USB1 activity
+        DCD     ETHERNET_IRQHandler  ; Ethernet
+        DCD     ETHERNET_PMT_IRQHandler  ; Ethernet power management interrupt
+        DCD     ETHERNET_MACLP_IRQHandler  ; Ethernet MAC interrupt
+        DCD     EEPROM_IRQHandler  ; EEPROM interrupt
+        DCD     LCD_IRQHandler  ; LCD interrupt
+        DCD     SHA_IRQHandler  ; SHA interrupt
+        DCD     SMARTCARD0_IRQHandler  ; Smart card 0 interrupt
+        DCD     SMARTCARD1_IRQHandler  ; Smart card 1 interrupt
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR     r0, =SystemInit
+                BLX     r0
+                LDR     r0, =__iar_program_start
+                BX      r0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+        PUBWEAK WDT_BOD_IRQHandler
+        PUBWEAK WDT_BOD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+WDT_BOD_IRQHandler
+        LDR     R0, =WDT_BOD_DriverIRQHandler
+        BX      R0
+        PUBWEAK DMA0_IRQHandler
+        PUBWEAK DMA0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMA0_IRQHandler
+        LDR     R0, =DMA0_DriverIRQHandler
+        BX      R0
+        PUBWEAK GINT0_IRQHandler
+        PUBWEAK GINT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT0_IRQHandler
+        LDR     R0, =GINT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK GINT1_IRQHandler
+        PUBWEAK GINT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+GINT1_IRQHandler
+        LDR     R0, =GINT1_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT0_IRQHandler
+        PUBWEAK PIN_INT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT0_IRQHandler
+        LDR     R0, =PIN_INT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT1_IRQHandler
+        PUBWEAK PIN_INT1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT1_IRQHandler
+        LDR     R0, =PIN_INT1_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT2_IRQHandler
+        PUBWEAK PIN_INT2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT2_IRQHandler
+        LDR     R0, =PIN_INT2_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT3_IRQHandler
+        PUBWEAK PIN_INT3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT3_IRQHandler
+        LDR     R0, =PIN_INT3_DriverIRQHandler
+        BX      R0
+        PUBWEAK UTICK0_IRQHandler
+        PUBWEAK UTICK0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+UTICK0_IRQHandler
+        LDR     R0, =UTICK0_DriverIRQHandler
+        BX      R0
+        PUBWEAK MRT0_IRQHandler
+        PUBWEAK MRT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+MRT0_IRQHandler
+        LDR     R0, =MRT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER0_IRQHandler
+        PUBWEAK CTIMER0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER0_IRQHandler
+        LDR     R0, =CTIMER0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER1_IRQHandler
+        PUBWEAK CTIMER1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER1_IRQHandler
+        LDR     R0, =CTIMER1_DriverIRQHandler
+        BX      R0
+        PUBWEAK SCT0_IRQHandler
+        PUBWEAK SCT0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SCT0_IRQHandler
+        LDR     R0, =SCT0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER3_IRQHandler
+        PUBWEAK CTIMER3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER3_IRQHandler
+        LDR     R0, =CTIMER3_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM0_IRQHandler
+        PUBWEAK FLEXCOMM0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM0_IRQHandler
+        LDR     R0, =FLEXCOMM0_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM1_IRQHandler
+        PUBWEAK FLEXCOMM1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM1_IRQHandler
+        LDR     R0, =FLEXCOMM1_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM2_IRQHandler
+        PUBWEAK FLEXCOMM2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM2_IRQHandler
+        LDR     R0, =FLEXCOMM2_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM3_IRQHandler
+        PUBWEAK FLEXCOMM3_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM3_IRQHandler
+        LDR     R0, =FLEXCOMM3_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM4_IRQHandler
+        PUBWEAK FLEXCOMM4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM4_IRQHandler
+        LDR     R0, =FLEXCOMM4_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM5_IRQHandler
+        PUBWEAK FLEXCOMM5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM5_IRQHandler
+        LDR     R0, =FLEXCOMM5_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM6_IRQHandler
+        PUBWEAK FLEXCOMM6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM6_IRQHandler
+        LDR     R0, =FLEXCOMM6_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM7_IRQHandler
+        PUBWEAK FLEXCOMM7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM7_IRQHandler
+        LDR     R0, =FLEXCOMM7_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_SEQA_IRQHandler
+        PUBWEAK ADC0_SEQA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQA_IRQHandler
+        LDR     R0, =ADC0_SEQA_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_SEQB_IRQHandler
+        PUBWEAK ADC0_SEQB_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_SEQB_IRQHandler
+        LDR     R0, =ADC0_SEQB_DriverIRQHandler
+        BX      R0
+        PUBWEAK ADC0_THCMP_IRQHandler
+        PUBWEAK ADC0_THCMP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ADC0_THCMP_IRQHandler
+        LDR     R0, =ADC0_THCMP_DriverIRQHandler
+        BX      R0
+        PUBWEAK DMIC0_IRQHandler
+        PUBWEAK DMIC0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DMIC0_IRQHandler
+        LDR     R0, =DMIC0_DriverIRQHandler
+        BX      R0
+        PUBWEAK HWVAD0_IRQHandler
+        PUBWEAK HWVAD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HWVAD0_IRQHandler
+        LDR     R0, =HWVAD0_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB0_NEEDCLK_IRQHandler
+        PUBWEAK USB0_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_NEEDCLK_IRQHandler
+        LDR     R0, =USB0_NEEDCLK_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB0_IRQHandler
+        PUBWEAK USB0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB0_IRQHandler
+        LDR     R0, =USB0_DriverIRQHandler
+        BX      R0
+        PUBWEAK RTC_IRQHandler
+        PUBWEAK RTC_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RTC_IRQHandler
+        LDR     R0, =RTC_DriverIRQHandler
+        BX      R0
+        PUBWEAK Reserved46_IRQHandler
+        PUBWEAK Reserved46_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved46_IRQHandler
+        LDR     R0, =Reserved46_DriverIRQHandler
+        BX      R0
+        PUBWEAK Reserved47_IRQHandler
+        PUBWEAK Reserved47_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reserved47_IRQHandler
+        LDR     R0, =Reserved47_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT4_IRQHandler
+        PUBWEAK PIN_INT4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT4_IRQHandler
+        LDR     R0, =PIN_INT4_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT5_IRQHandler
+        PUBWEAK PIN_INT5_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT5_IRQHandler
+        LDR     R0, =PIN_INT5_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT6_IRQHandler
+        PUBWEAK PIN_INT6_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT6_IRQHandler
+        LDR     R0, =PIN_INT6_DriverIRQHandler
+        BX      R0
+        PUBWEAK PIN_INT7_IRQHandler
+        PUBWEAK PIN_INT7_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PIN_INT7_IRQHandler
+        LDR     R0, =PIN_INT7_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER2_IRQHandler
+        PUBWEAK CTIMER2_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER2_IRQHandler
+        LDR     R0, =CTIMER2_DriverIRQHandler
+        BX      R0
+        PUBWEAK CTIMER4_IRQHandler
+        PUBWEAK CTIMER4_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CTIMER4_IRQHandler
+        LDR     R0, =CTIMER4_DriverIRQHandler
+        BX      R0
+        PUBWEAK RIT_IRQHandler
+        PUBWEAK RIT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+RIT_IRQHandler
+        LDR     R0, =RIT_DriverIRQHandler
+        BX      R0
+        PUBWEAK SPIFI0_IRQHandler
+        PUBWEAK SPIFI0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SPIFI0_IRQHandler
+        LDR     R0, =SPIFI0_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM8_IRQHandler
+        PUBWEAK FLEXCOMM8_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM8_IRQHandler
+        LDR     R0, =FLEXCOMM8_DriverIRQHandler
+        BX      R0
+        PUBWEAK FLEXCOMM9_IRQHandler
+        PUBWEAK FLEXCOMM9_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+FLEXCOMM9_IRQHandler
+        LDR     R0, =FLEXCOMM9_DriverIRQHandler
+        BX      R0
+        PUBWEAK SDIO_IRQHandler
+        PUBWEAK SDIO_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SDIO_IRQHandler
+        LDR     R0, =SDIO_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN0_IRQ0_IRQHandler
+        PUBWEAK CAN0_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ0_IRQHandler
+        LDR     R0, =CAN0_IRQ0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN0_IRQ1_IRQHandler
+        PUBWEAK CAN0_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN0_IRQ1_IRQHandler
+        LDR     R0, =CAN0_IRQ1_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN1_IRQ0_IRQHandler
+        PUBWEAK CAN1_IRQ0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ0_IRQHandler
+        LDR     R0, =CAN1_IRQ0_DriverIRQHandler
+        BX      R0
+        PUBWEAK CAN1_IRQ1_IRQHandler
+        PUBWEAK CAN1_IRQ1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CAN1_IRQ1_IRQHandler
+        LDR     R0, =CAN1_IRQ1_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB1_IRQHandler
+        PUBWEAK USB1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_IRQHandler
+        LDR     R0, =USB1_DriverIRQHandler
+        BX      R0
+        PUBWEAK USB1_NEEDCLK_IRQHandler
+        PUBWEAK USB1_NEEDCLK_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+USB1_NEEDCLK_IRQHandler
+        LDR     R0, =USB1_NEEDCLK_DriverIRQHandler
+        BX      R0
+        PUBWEAK ETHERNET_IRQHandler
+        PUBWEAK ETHERNET_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_IRQHandler
+        LDR     R0, =ETHERNET_DriverIRQHandler
+        BX      R0
+        PUBWEAK ETHERNET_PMT_IRQHandler
+        PUBWEAK ETHERNET_PMT_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_PMT_IRQHandler
+        LDR     R0, =ETHERNET_PMT_DriverIRQHandler
+        BX      R0
+        PUBWEAK ETHERNET_MACLP_IRQHandler
+        PUBWEAK ETHERNET_MACLP_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+ETHERNET_MACLP_IRQHandler
+        LDR     R0, =ETHERNET_MACLP_DriverIRQHandler
+        BX      R0
+        PUBWEAK EEPROM_IRQHandler
+        PUBWEAK EEPROM_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+EEPROM_IRQHandler
+        LDR     R0, =EEPROM_DriverIRQHandler
+        BX      R0
+        PUBWEAK LCD_IRQHandler
+        PUBWEAK LCD_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+LCD_IRQHandler
+        LDR     R0, =LCD_DriverIRQHandler
+        BX      R0
+        PUBWEAK SHA_IRQHandler
+        PUBWEAK SHA_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SHA_IRQHandler
+        LDR     R0, =SHA_DriverIRQHandler
+        BX      R0
+        PUBWEAK SMARTCARD0_IRQHandler
+        PUBWEAK SMARTCARD0_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD0_IRQHandler
+        LDR     R0, =SMARTCARD0_DriverIRQHandler
+        BX      R0
+        PUBWEAK SMARTCARD1_IRQHandler
+        PUBWEAK SMARTCARD1_DriverIRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SMARTCARD1_IRQHandler
+        LDR     R0, =SMARTCARD1_DriverIRQHandler
+        BX      R0
+WDT_BOD_DriverIRQHandler
+DMA0_DriverIRQHandler
+GINT0_DriverIRQHandler
+GINT1_DriverIRQHandler
+PIN_INT0_DriverIRQHandler
+PIN_INT1_DriverIRQHandler
+PIN_INT2_DriverIRQHandler
+PIN_INT3_DriverIRQHandler
+UTICK0_DriverIRQHandler
+MRT0_DriverIRQHandler
+CTIMER0_DriverIRQHandler
+CTIMER1_DriverIRQHandler
+SCT0_DriverIRQHandler
+CTIMER3_DriverIRQHandler
+FLEXCOMM0_DriverIRQHandler
+FLEXCOMM1_DriverIRQHandler
+FLEXCOMM2_DriverIRQHandler
+FLEXCOMM3_DriverIRQHandler
+FLEXCOMM4_DriverIRQHandler
+FLEXCOMM5_DriverIRQHandler
+FLEXCOMM6_DriverIRQHandler
+FLEXCOMM7_DriverIRQHandler
+ADC0_SEQA_DriverIRQHandler
+ADC0_SEQB_DriverIRQHandler
+ADC0_THCMP_DriverIRQHandler
+DMIC0_DriverIRQHandler
+HWVAD0_DriverIRQHandler
+USB0_NEEDCLK_DriverIRQHandler
+USB0_DriverIRQHandler
+RTC_DriverIRQHandler
+Reserved46_DriverIRQHandler
+Reserved47_DriverIRQHandler
+PIN_INT4_DriverIRQHandler
+PIN_INT5_DriverIRQHandler
+PIN_INT6_DriverIRQHandler
+PIN_INT7_DriverIRQHandler
+CTIMER2_DriverIRQHandler
+CTIMER4_DriverIRQHandler
+RIT_DriverIRQHandler
+SPIFI0_DriverIRQHandler
+FLEXCOMM8_DriverIRQHandler
+FLEXCOMM9_DriverIRQHandler
+SDIO_DriverIRQHandler
+CAN0_IRQ0_DriverIRQHandler
+CAN0_IRQ1_DriverIRQHandler
+CAN1_IRQ0_DriverIRQHandler
+CAN1_IRQ1_DriverIRQHandler
+USB1_DriverIRQHandler
+USB1_NEEDCLK_DriverIRQHandler
+ETHERNET_DriverIRQHandler
+ETHERNET_PMT_DriverIRQHandler
+ETHERNET_MACLP_DriverIRQHandler
+EEPROM_DriverIRQHandler
+LCD_DriverIRQHandler
+SHA_DriverIRQHandler
+SMARTCARD0_DriverIRQHandler
+SMARTCARD1_DriverIRQHandler
+DefaultISR
+        B .
+
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC54608 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "fsl_device_registers.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis_nvic.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if defined(__CC_ARM)
+extern uint32_t Image$$VECTOR_RAM$$Base[];
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#else
+extern uint32_t __VECTOR_RAM[];
+#endif
+
+/* Symbols defined by the linker script */
+#define NVIC_NUM_VECTORS        (16 + 57)         // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM)    // Vectors positioned at start of RAM
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017 NXP
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC54608J512BD208) || defined(CPU_LPC54608J512ET180))
+
+#define LPC54608_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC54608.h"
+/* CPU specific feature definitions */
+#include "LPC54608_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,361 @@
+/*
+** ###################################################################
+**     Processors:          LPC54608J512BD208
+**                          LPC54608J512ET180
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b170214
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54608
+ * @version 1.1
+ * @date 2016-11-25
+ * @brief Device specific configuration file for LPC54608 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define NVALMAX (0x100)
+#define PVALMAX (0x20)
+#define MVALMAX (0x8000)
+#define PLL_MDEC_VAL_P (0)                                       /* MDEC is in bits  16:0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
+#define PLL_NDEC_VAL_P (0)                                       /* NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0)                                       /* PDEC is in bits  6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+extern void *__Vectors;
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
+                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/* Get WATCH DOG Clk */
+static uint32_t getWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
+        freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+    }
+}
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0x3FF:
+            n = 0;
+            break;
+        case 0x302:
+            n = 1;
+            break;
+        case 0x202:
+            n = 2;
+            break;
+        default:
+            x = 0x080;
+            n = 0xFFFFFFFFU;
+            for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+            }
+            break;
+    }
+    return n;
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0x7F:
+            p = 0;
+            break;
+        case 0x62:
+            p = 1;
+            break;
+        case 0x42:
+            p = 2;
+            break;
+        default:
+            x = 0x10;
+            p = 0xFFFFFFFFU;
+            for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xFU);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+            }
+            break;
+    }
+    return p;
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0x1FFFF:
+            m = 0;
+            break;
+        case 0x18003:
+            m = 1;
+            break;
+        case 0x10003:
+            m = 2;
+            break;
+        default:
+            x = 0x04000;
+            m = 0xFFFFFFFFU;
+            for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFFU);
+                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+            }
+            break;
+    }
+    return m;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FF);
+        if (preDiv == 0)
+        {
+            preDiv = 1;
+        }
+    }
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
+        if (postDiv == 0)
+        {
+            postDiv = 2;
+        }
+    }
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFF);
+    if (mMult == 0)
+    {
+        mMult = 1;
+    }
+    return mMult;
+}
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if defined(__MCUXPRESSO)
+    extern void(*const g_pfnVectors[]) (void);
+    SCB->VTOR = (uint32_t) &g_pfnVectors;
+#else
+    extern void *__Vectors;
+    SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+    SYSCON->ARMTRACECLKDIV = 0;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+  SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+uint32_t clkRate = 0;
+    uint32_t prediv, postdiv;
+    uint64_t workRate;
+
+    switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+    {
+        case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+            switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
+                    if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
+                    {
+                        clkRate = CLK_FRO_96MHZ;
+                    }
+                    else
+                    {
+                        clkRate = CLK_FRO_48MHZ;
+                    }
+                    break;
+            }
+            break;
+        case 0x02: /* System PLL clock (pll_clk)*/
+            switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+                    clkRate = CLK_RTC_32K_CLK;
+                    break;
+                default:
+                    break;
+            }
+            if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
+            {
+                /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+                prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
+                postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
+                /* Adjust input clock */
+                clkRate = clkRate / prediv;
+
+                /* MDEC used for rate */
+                workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
+                clkRate = workRate / ((uint64_t)postdiv);
+                clkRate = workRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
+            }
+            break;
+        case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+            clkRate = CLK_RTC_32K_CLK;
+            break;
+        default:
+            break;
+    }
+    SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,121 @@
+/*
+** ###################################################################
+**     Processors:          LPC54608J512BD208
+**                          LPC54608J512ET180
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
+**     Version:             rev. 1.1, 2016-11-25
+**     Build:               b161227
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54608
+ * @version 1.1
+ * @date 2016-11-25
+ * @brief Device specific configuration file for LPC54608 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC54608_H_
+#define _SYSTEM_LPC54608_H_                      /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN                            0u           /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_LPC54608_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_adc.h"
+#include "fsl_clock.h"
+
+static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+static uint32_t ADC_GetInstance(ADC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
+    {
+        if (s_adcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_adcBases));
+
+    return instance;
+}
+
+void ADC_Init(ADC_Type *base, const adc_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32 = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable clock. */
+    CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable the interrupts. */
+    base->INTEN = 0U; /* Quickly disable all the interrupts. */
+
+    /* Configure the ADC block. */
+    tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber);
+
+    /* Async or Sync clock mode. */
+    switch (config->clockMode)
+    {
+        case kADC_ClockAsynchronousMode:
+            tmp32 |= ADC_CTRL_ASYNMODE_MASK;
+            break;
+        default: /* kADC_ClockSynchronousMode */
+            break;
+    }
+
+    /* Resolution. */
+    tmp32 |= ADC_CTRL_RESOL(config->resolution);
+
+    /* Bypass calibration. */
+    if (config->enableBypassCalibration)
+    {
+        tmp32 |= ADC_CTRL_BYPASSCAL_MASK;
+    }
+
+    /* Sample time clock count. */
+    tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber);
+
+    base->CTRL = tmp32;
+}
+
+void ADC_GetDefaultConfig(adc_config_t *config)
+{
+    config->clockMode = kADC_ClockSynchronousMode;
+    config->clockDividerNumber = 0U;
+    config->resolution = kADC_Resolution12bit;
+    config->enableBypassCalibration = false;
+    config->sampleTimeNumber = 0U;
+}
+
+void ADC_Deinit(ADC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+bool ADC_DoSelfCalibration(ADC_Type *base)
+{
+    uint32_t i;
+
+    /* Enable the converter. */
+    /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down.
+       This bit should be set after at least 10 ms after the ADC is powered on. */
+    base->STARTUP = ADC_STARTUP_ADC_ENA_MASK;
+    for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */
+    {
+        __ASM("NOP");
+    }
+    if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK))
+    {
+        return false; /* ADC is not powered up. */
+    }
+
+    /* If not in by-pass mode, do the calibration. */
+    if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) &&
+        (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK)))
+    {
+        /* Calibration is needed, do it now. */
+        base->CALIB = ADC_CALIB_CALIB_MASK;
+        i = 0xF0000;
+        while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i))
+        {
+        }
+        if (i == 0U)
+        {
+            return false; /* Calibration timeout. */
+        }
+    }
+
+    /* A dummy conversion cycle will be performed. */
+    base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK;
+    i = 0x7FFFF;
+    while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i))
+    {
+    }
+    if (i == 0U)
+    {
+        return false;
+    }
+
+    return true;
+}
+
+void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
+            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
+
+    /* Polarity for tirgger signal. */
+    switch (config->triggerPolarity)
+    {
+        case kADC_TriggerPolarityPositiveEdge:
+            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
+            break;
+        default: /* kADC_TriggerPolarityNegativeEdge */
+            break;
+    }
+
+    /* Bypass the clock Sync. */
+    if (config->enableSyncBypass)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
+    }
+
+    /* Interrupt point. */
+    switch (config->interruptMode)
+    {
+        case kADC_InterruptForEachSequence:
+            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
+            break;
+        default: /* kADC_InterruptForEachConversion */
+            break;
+    }
+
+    /* One trigger for a conversion, or for a sequence. */
+    if (config->enableSingleStep)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
+    }
+
+    base->SEQ_CTRL[0] = tmp32;
+}
+
+void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32;
+
+    tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask)   /* Channel mask. */
+            | ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
+
+    /* Polarity for tirgger signal. */
+    switch (config->triggerPolarity)
+    {
+        case kADC_TriggerPolarityPositiveEdge:
+            tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
+            break;
+        default: /* kADC_TriggerPolarityPositiveEdge */
+            break;
+    }
+
+    /* Bypass the clock Sync. */
+    if (config->enableSyncBypass)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
+    }
+
+    /* Interrupt point. */
+    switch (config->interruptMode)
+    {
+        case kADC_InterruptForEachSequence:
+            tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
+            break;
+        default: /* kADC_InterruptForEachConversion */
+            break;
+    }
+
+    /* One trigger for a conversion, or for a sequence. */
+    if (config->enableSingleStep)
+    {
+        tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
+    }
+
+    base->SEQ_CTRL[1] = tmp32;
+}
+
+bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
+{
+    assert(info != NULL);
+
+    uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */
+
+    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
+
+    return true;
+}
+
+bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
+{
+    assert(info != NULL);
+
+    uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */
+
+    if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
+
+    return true;
+}
+
+bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info)
+{
+    assert(info != NULL);
+    assert(channel < ADC_DAT_COUNT);
+
+    uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */
+
+    if (0U == (ADC_DAT_DATAVALID_MASK & tmp32))
+    {
+        return false;
+    }
+
+    info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT;
+    info->thresholdCompareStatus =
+        (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT);
+    info->thresholdCorssingStatus =
+        (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT);
+    info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT;
+    info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK);
+
+    return true;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,664 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ADC_H__
+#define __FSL_ADC_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_adc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief ADC driver version 2.0.0. */
+#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief Flags
+ */
+enum _adc_status_flags
+{
+    kADC_ThresholdCompareFlagOnChn0 = 1U << 0U,   /*!< Threshold comparison event on Channel 0. */
+    kADC_ThresholdCompareFlagOnChn1 = 1U << 1U,   /*!< Threshold comparison event on Channel 1. */
+    kADC_ThresholdCompareFlagOnChn2 = 1U << 2U,   /*!< Threshold comparison event on Channel 2. */
+    kADC_ThresholdCompareFlagOnChn3 = 1U << 3U,   /*!< Threshold comparison event on Channel 3. */
+    kADC_ThresholdCompareFlagOnChn4 = 1U << 4U,   /*!< Threshold comparison event on Channel 4. */
+    kADC_ThresholdCompareFlagOnChn5 = 1U << 5U,   /*!< Threshold comparison event on Channel 5. */
+    kADC_ThresholdCompareFlagOnChn6 = 1U << 6U,   /*!< Threshold comparison event on Channel 6. */
+    kADC_ThresholdCompareFlagOnChn7 = 1U << 7U,   /*!< Threshold comparison event on Channel 7. */
+    kADC_ThresholdCompareFlagOnChn8 = 1U << 8U,   /*!< Threshold comparison event on Channel 8. */
+    kADC_ThresholdCompareFlagOnChn9 = 1U << 9U,   /*!< Threshold comparison event on Channel 9. */
+    kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */
+    kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */
+    kADC_OverrunFlagForChn0 =
+        1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */
+    kADC_OverrunFlagForChn1 =
+        1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */
+    kADC_OverrunFlagForChn2 =
+        1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */
+    kADC_OverrunFlagForChn3 =
+        1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */
+    kADC_OverrunFlagForChn4 =
+        1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */
+    kADC_OverrunFlagForChn5 =
+        1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */
+    kADC_OverrunFlagForChn6 =
+        1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */
+    kADC_OverrunFlagForChn7 =
+        1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */
+    kADC_OverrunFlagForChn8 =
+        1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */
+    kADC_OverrunFlagForChn9 =
+        1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */
+    kADC_OverrunFlagForChn10 =
+        1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */
+    kADC_OverrunFlagForChn11 =
+        1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */
+    kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */
+    kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */
+    kADC_ConvSeqAInterruptFlag = 1U << 28U,    /*!< Sequence A interrupt/DMA trigger. */
+    kADC_ConvSeqBInterruptFlag = 1U << 29U,    /*!< Sequence B interrupt/DMA trigger. */
+    kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */
+    kADC_OverrunInterruptFlag = 1U << 31U,          /*!< Overrun interrupt flag. */
+};
+
+/*!
+ * @brief Interrupts
+ * @note Not all the interrupt options are listed here
+ */
+enum _adc_interrupt_enable
+{
+    kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
+                                                                   conversion in sequence A, or entire sequence. */
+    kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
+                                                                   conversion in sequence B, or entire sequence. */
+    kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of
+                                                                 the channel data registers will cause an overrun
+                                                                 interrupt/DMA trigger. */
+};
+
+/*!
+ * @brief Define selection of clock mode.
+ */
+typedef enum _adc_clock_mode
+{
+    kADC_ClockSynchronousMode =
+        0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */
+    kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */
+} adc_clock_mode_t;
+
+/*!
+ * @brief Define selection of resolution.
+ */
+typedef enum _adc_resolution
+{
+    kADC_Resolution6bit = 0U,  /*!< 6-bit resolution. */
+    kADC_Resolution8bit = 1U,  /*!< 8-bit resolution. */
+    kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */
+    kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */
+} adc_resolution_t;
+
+/*!
+ * @brief Define selection of polarity of selected input trigger for conversion sequence.
+ */
+typedef enum _adc_trigger_polarity
+{
+    kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */
+    kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */
+} adc_trigger_polarity_t;
+
+/*!
+ * @brief Define selection of conversion sequence's priority.
+ */
+typedef enum _adc_priority
+{
+    kADC_PriorityLow = 0U,  /*!< This sequence would be preempted when another sequence is started. */
+    kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */
+} adc_priority_t;
+
+/*!
+ * @brief Define selection of conversion sequence's interrupt.
+ */
+typedef enum _adc_seq_interrupt_mode
+{
+    kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each
+                                               individual ADC conversion inside this conversion sequence. */
+    kADC_InterruptForEachSequence = 1U,   /*!< The sequence interrupt/DMA trigger will be set when the entire set of
+                                               this sequence conversions completes. */
+} adc_seq_interrupt_mode_t;
+
+/*!
+ * @brief Define status of threshold compare result.
+ */
+typedef enum _adc_threshold_compare_status
+{
+    kADC_ThresholdCompareInRange = 0U,    /*!< LOW threshold <= conversion value <= HIGH threshold. */
+    kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */
+    kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */
+} adc_threshold_compare_status_t;
+
+/*!
+ * @brief Define status of threshold crossing detection result.
+ */
+typedef enum _adc_threshold_crossing_status
+{
+    /* The conversion on this channel had the same relationship (above or below) to the threshold value established by
+     * the designated LOW threshold value as did the previous conversion on this channel. */
+    kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */
+
+    /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this
+     * channel was above the threshold value established by the designated LOW threshold value and the current sample is
+     * below that threshold. */
+    kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */
+
+    /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this
+     * channel was below the threshold value established by the designated LOW threshold value and the current sample is
+     * above that threshold. */
+    kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */
+} adc_threshold_crossing_status_t;
+
+/*!
+ * @brief Define interrupt mode for threshold compare event.
+ */
+typedef enum _adc_threshold_interrupt_mode
+{
+    kADC_ThresholdInterruptDisabled = 0U,   /*!< Threshold comparison interrupt is disabled. */
+    kADC_ThresholdInterruptOnOutside = 1U,  /*!< Threshold comparison interrupt is enabled on outside threshold. */
+    kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */
+} adc_threshold_interrupt_mode_t;
+
+/*!
+ * @brief Define structure for configuring the block.
+ */
+typedef struct _adc_config
+{
+    adc_clock_mode_t clockMode;   /*!< Select the clock mode for ADC converter. */
+    uint32_t clockDividerNumber;  /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode"
+                                       field. The divider would be plused by 1 based on the value in this field. The
+                                       available range is in 8 bits. */
+    adc_resolution_t resolution;  /*!< Select the conversion bits. */
+    bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is
+                                       powered-up. Re-calibration may be warranted periodically - especially if
+                                       operating conditions have changed. To enable this option would avoid the need to
+                                       calibrate if offset error is not a concern in the application. */
+    uint32_t sampleTimeNumber;    /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then,
+                                       to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/
+} adc_config_t;
+
+/*!
+ * @brief Define structure for configuring conversion sequence.
+ */
+typedef struct _adc_conv_seq_config
+{
+    uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this
+                               sequence is launched. The masked channels would be involved in current conversion
+                               sequence, beginning with the lowest-order. The available range is in 12-bit. */
+    uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this
+                               conversion sequence to be initiated. The available range is 6-bit.*/
+    adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */
+    bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization
+                                flip-flop stages and therefore shorten the time between the trigger input signal and the
+                                start of a conversion. */
+    bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next
+                                channel in the sequence instead of the default response of launching an entire sequence
+                                of conversions. */
+    adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */
+} adc_conv_seq_config_t;
+
+/*!
+ * @brief Define structure of keeping conversion result information.
+ */
+typedef struct _adc_result_info
+{
+    uint32_t result;                                         /*!< Keey the conversion data value. */
+    adc_threshold_compare_status_t thresholdCompareStatus;   /*!< Keep the threshold compare status. */
+    adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
+    uint32_t channelNumber;                                  /*!< Keep the channel number for this conversion. */
+    bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */
+    /* The data available flag would be returned by the reading result API. */
+} adc_result_info_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization and Deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initialize the ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_config_t.
+ */
+void ADC_Init(ADC_Type *base, const adc_config_t *config);
+
+/*!
+ * @brief Deinitialize the ADC module.
+ *
+ * @param base ADC peripheral base address.
+ */
+void ADC_Deinit(ADC_Type *base);
+
+/*!
+ * @brief Gets an available pre-defined settings for initial configuration.
+ *
+ * This function initializes the initial configuration structure with an available settings. The default values are:
+ * @code
+ *   config->clockMode = kADC_ClockSynchronousMode;
+ *   config->clockDividerNumber = 0U;
+ *   config->resolution = kADC_Resolution12bit;
+ *   config->enableBypassCalibration = false;
+ *   config->sampleTimeNumber = 0U;
+ * @endcode
+ * @param config Pointer to configuration structure.
+ */
+void ADC_GetDefaultConfig(adc_config_t *config);
+
+/*!
+ * @brief Do the self hardware calibration.
+ *
+ * @param base ADC peripheral base address.
+ * @retval true  Calibration succeed.
+ * @retval false Calibration failed.
+ */
+bool ADC_DoSelfCalibration(ADC_Type *base);
+
+/*!
+ * @brief Enable the internal temperature sensor measurement.
+ *
+ * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor
+ * instead of external pin.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3);
+    }
+    else
+    {
+        base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Control conversion sequence A.
+ * @{
+ */
+
+/*!
+ * @brief Enable the conversion sequence A.
+ *
+ * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
+ * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
+ * sequence during changing the sequence's setting.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+}
+
+/*!
+ * @brief Configure the conversion sequence A.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
+ */
+void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
+
+/*!
+ * @brief Do trigger the sequence's conversion by software.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK;
+}
+
+/*!
+ * @brief Enable the burst conversion of sequence A.
+ *
+ * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be
+ * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
+ * currently in process will be completed before cnversions are terminated.
+ * Note that a new sequence could begin just before the burst mode is disabled.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable this feature.
+ */
+static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK;
+    }
+}
+
+/*!
+ * @brief Set the high priority for conversion sequence A.
+ *
+ * @param base ADC peripheral bass address.
+ */
+static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Control conversion sequence B.
+ * @{
+ */
+
+/*!
+ * @brief Enable the conversion sequence B.
+ *
+ * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
+ * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
+ * sequence during changing the sequence's setting.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable the feature or not.
+ */
+static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
+    }
+}
+
+/*!
+ * @brief Configure the conversion sequence B.
+ *
+ * @param base ADC peripheral base address.
+ * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
+ */
+void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
+
+/*!
+ * @brief Do trigger the sequence's conversion by software.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base)
+{
+    base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK;
+}
+
+/*!
+ * @brief Enable the burst conversion of sequence B.
+ *
+ * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be
+ * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
+ * currently in process will be completed before cnversions are terminated.
+ * Note that a new sequence could begin just before the burst mode is disabled.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Switcher to enable this feature.
+ */
+static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK;
+    }
+    else
+    {
+        base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK;
+    }
+}
+
+/*!
+ * @brief Set the high priority for conversion sequence B.
+ *
+ * @param base ADC peripheral bass address.
+ */
+static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base)
+{
+    base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Data result.
+ * @{
+ */
+
+/*!
+ * @brief Get the global ADC conversion infomation of sequence A.
+ *
+ * @param base ADC peripheral base address.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
+
+/*!
+ * @brief Get the global ADC conversion infomation of sequence B.
+ *
+ * @param base ADC peripheral base address.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
+
+/*!
+ * @brief Get the channel's ADC conversion completed under each conversion sequence.
+ *
+ * @param base ADC peripheral base address.
+ * @param channel The indicated channel number.
+ * @param info Pointer to information structure, see to #adc_result_info_t;
+ * @retval true  The conversion result is ready.
+ * @retval false The conversion result is not ready yet.
+ */
+bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info);
+
+/* @} */
+
+/*!
+ * @name Threshold function.
+ * @{
+ */
+
+/*!
+ * @brief Set the threshhold pair 0 with low and high value.
+ *
+ * @param base ADC peripheral base address.
+ * @param lowValue LOW threshold value.
+ * @param highValue HIGH threshold value.
+ */
+static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
+{
+    base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue);
+    base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue);
+}
+
+/*!
+ * @brief Set the threshhold pair 1 with low and high value.
+ *
+ * @param base ADC peripheral base address.
+ * @param lowValue LOW threshold value. The available value is with 12-bit.
+ * @param highValue HIGH threshold value. The available value is with 12-bit.
+ */
+static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
+{
+    base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue);
+    base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue);
+}
+
+/*!
+ * @brief Set given channels to apply the threshold pare 0.
+ *
+ * @param base ADC peripheral base address.
+ * @param channelMask Indicated channels' mask.
+ */
+static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask)
+{
+    base->CHAN_THRSEL &= ~(channelMask);
+}
+
+/*!
+ * @brief Set given channels to apply the threshold pare 1.
+ *
+ * @param base ADC peripheral base address.
+ * @param channelMask Indicated channels' mask.
+ */
+static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask)
+{
+    base->CHAN_THRSEL |= channelMask;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts.
+ * @{
+ */
+
+/*!
+ * @brief Enable interrupts for conversion sequences.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable.
+ */
+static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
+{
+    base->INTEN |= (0x7 & mask);
+}
+
+/*!
+ * @brief Disable interrupts for conversion sequence.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable.
+ */
+static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
+{
+    base->INTEN &= ~(0x7 & mask);
+}
+
+/*!
+ * @brief Enable the interrupt of shreshold compare event for each channel.
+ *
+ * @param base ADC peripheral base address.
+ * @param channel Channel number.
+ * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
+ */
+static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
+                                                       uint32_t channel,
+                                                       adc_threshold_interrupt_mode_t mode)
+{
+    base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
+}
+
+/* @} */
+
+/*!
+ * @name Status.
+ * @{
+ */
+
+/*!
+ * @brief Get status flags of ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @return Mask of status flags of module, see to #_adc_status_flags.
+ */
+static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
+{
+    return base->FLAGS;
+}
+
+/*!
+ * @brief Clear status flags of ADC module.
+ *
+ * @param base ADC peripheral base address.
+ * @param mask Mask of status flags of module, see to #_adc_status_flags.
+ */
+static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
+{
+    base->FLAGS = mask; /* Write 1 to clear. */
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* __FSL_ADC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,2106 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_clock.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define NVALMAX (0x100U)
+#define PVALMAX (0x20U)
+#define MVALMAX (0x8000U)
+
+#define USB_NVALMAX (0x4U)
+#define USB_PVALMAX (0x8U)
+#define USB_MVALMAX (0x100U)
+
+#define PLL_MAX_N_DIV 0x100U
+#define USB_PLL_MAX_N_DIV 0x100U
+
+#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000448U)
+#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x0100044CU)
+/*--------------------------------------------------------------------------
+!!! If required these #defines can be moved to chip library file
+----------------------------------------------------------------------------*/
+
+#define PLL_MDEC_VAL_P (0U)                                      /*!<  MDEC is in bits  16 downto 0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)             /*!<  NDEC is in bits  9 downto 0 */
+#define PLL_NDEC_VAL_P (0U)                                      /*!<  NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0U)                                      /*!<  PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+#define PLL_MIN_CCO_FREQ_MHZ (275000000U)
+#define PLL_MAX_CCO_FREQ_MHZ (550000000U)
+#define PLL_LOWER_IN_LIMIT (4000U)                               /*!<  Minimum PLL input rate */
+#define PLL_MIN_IN_SSMODE (2000000U)
+#define PLL_MAX_IN_SSMODE (4000000U)
+
+/*!<  Middle of the range values for spread-spectrum */
+#define PLL_SSCG_MF_FREQ_VALUE 4U
+#define PLL_SSCG_MC_COMP_VALUE 2U
+#define PLL_SSCG_MR_DEPTH_VALUE 4U
+#define PLL_SSCG_DITHER_VALUE 0U
+
+/*!<  USB PLL CCO MAX AND MIN FREQ */
+#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U)
+#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U)
+#define USB_PLL_LOWER_IN_LIMIT (1000000U)                             /*!<  Minimum PLL input rate */
+
+#define USB_PLL_MSEL_VAL_P (0U)                                       /*!<  MSEL is in bits  7 downto 0 */
+#define USB_PLL_MSEL_VAL_M (0xFFU)
+#define USB_PLL_PSEL_VAL_P (8U)                                       /*!<  PDEC is in bits 9:8 */
+#define USB_PLL_PSEL_VAL_M (0x3U)
+#define USB_PLL_NSEL_VAL_P (10U)                                      /*!<  NDEC is in bits  11:10 */
+#define USB_PLL_NSEL_VAL_M (0x3U)
+
+/*!<  SWITCH USB POSTDIVIDER FOR REGITSER WRITING */
+#define SWITCH_USB_PSEL(x)    ((x==0x0U) ? 0x1U : (x==0x1U) ? 0x02U : (x==0x2U) ? 0x4U : (x==3U) ? 0x8U : 0U)
+
+/*!<  SYS PLL NDEC reg */
+#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)
+/*!<  SYS PLL PDEC reg */
+#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)
+/*!<  SYS PLL MDEC reg */
+#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M)
+
+/*!<  SYS PLL NSEL reg */
+#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P)
+/*!<  SYS PLL PSEL reg */
+#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P)
+/*!<  SYS PLL MSEL reg */
+#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P)
+
+/*!<  FRAC control */
+#define AUDIO_PLL_FRACT_MD_P (0U)
+#define AUDIO_PLL_FRACT_MD_INT_P (15U)
+#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P)
+#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P)
+
+#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M)
+#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M)
+
+/* Saved value of PLL output rate, computed whenever needed to save run-time
+   computation on each call to retrive the PLL rate. */
+static uint32_t s_Pll_Freq;
+static uint32_t s_Usb_Pll_Freq;
+static uint32_t s_Audio_Pll_Freq;
+
+
+/** External clock rate on the CLKIN pin in Hz. If not used,
+    set this to 0. Otherwise, set it to the exact rate in Hz this pin is
+    being driven at. */
+const uint32_t g_I2S_Mclk_Freq = 0U;
+const uint32_t g_Ext_Clk_Freq = 12000000U;
+const uint32_t g_Lcd_Clk_In_Freq = 0U;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N);
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC);
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P);
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC);
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M);
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC);
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg);
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);
+/* Get the greatest common divisor */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
+/* Set PLL output based on desired output rate */
+static pll_error_t CLOCK_GetPllConfig(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup);
+
+/* Update local PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup);
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
+                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Clock Selection for IP */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+    bool final_descriptor = false;
+    uint8_t mux;
+    uint8_t pos;
+    uint32_t i;
+    volatile uint32_t *pClkSel;
+
+    pClkSel = &(SYSCON->MAINCLKSELA);
+
+    for (i = 0U; (i <= 2U) && (!final_descriptor); i++)
+    {
+        connection = (clock_attach_id_t)(connection >> (i * 12U)); /*!<  pick up next descriptor */
+        mux = (uint8_t)connection;
+        if (connection)
+        {
+            pos = ((connection & 0xf00U) >> 8U) - 1U;
+            if (mux == CM_ASYNCAPB)
+            {
+                SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+                ASYNC_SYSCON->ASYNCAPBCLKSELA = pos;
+            }
+            else
+            {
+                pClkSel[mux] = pos;
+            }
+        }
+        else
+        {
+            final_descriptor = true;
+        }
+    }
+}
+
+/* Set IP Clock Divider */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)
+{
+    volatile uint32_t *pClkDiv;
+
+    pClkDiv = &(SYSCON->SYSTICKCLKDIV);
+    if (reset)
+    {
+        pClkDiv[div_name] = 1U << 29U;
+    }
+    if (divided_by_value == 0U) /*!<  halt */
+    {
+        pClkDiv[div_name] = 1U << 30U;
+    }
+    else
+    {
+        pClkDiv[div_name] = (divided_by_value - 1U);
+    }
+}
+
+/* Set FRO Clocking */
+status_t CLOCK_SetupFROClocking(uint32_t iFreq)
+{
+    uint32_t usb_adj;
+    if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U))
+    {
+        return kStatus_Fail;
+    }
+    /* Power up the FRO and set this as the base clock */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
+    /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */
+    usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT;
+    if (iFreq > 12000000U)
+    {
+        if (iFreq == 96000000U)
+        {
+            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) |
+                                SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
+                                SYSCON_FROCTRL_HSPDCLK(1);
+        }
+        else
+        {
+            SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) |
+                                SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) |
+                                SYSCON_FROCTRL_HSPDCLK(1);
+        }
+    }
+    else
+    {
+        SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1);
+    }
+
+    return 0U;
+}
+
+/* Get CLOCK OUT Clk */
+uint32_t CLOCK_GetClockOutClkFreq(void)
+{
+    return (SYSCON->CLKOUTSELA == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->CLKOUTSELA == 1U) ? CLOCK_GetExtClkFreq():
+           (SYSCON->CLKOUTSELA == 2U) ? CLOCK_GetWdtOscFreq():
+           (SYSCON->CLKOUTSELA == 3U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->CLKOUTSELA == 4U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->CLKOUTSELA == 5U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->CLKOUTSELA == 6U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->CLKOUTSELA == 7U) ? CLOCK_GetOsc32KFreq():0U;
+}
+
+/* Get SPIFI Clk */
+uint32_t CLOCK_GetSpifiClkFreq(void)
+{
+    return (SYSCON->SPIFICLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->SPIFICLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->SPIFICLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->SPIFICLKSEL == 3U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->SPIFICLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->SPIFICLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get ADC Clk */
+uint32_t CLOCK_GetAdcClkFreq(void)
+{
+    return (SYSCON->ADCCLKSEL == 0U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->ADCCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->ADCCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->ADCCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->ADCCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get USB0 Clk */
+uint32_t CLOCK_GetUsb0ClkFreq(void)
+{
+    return (SYSCON->USB0CLKSEL == 0U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->USB0CLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->USB0CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->USB0CLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get USB1 Clk */
+uint32_t CLOCK_GetUsb1ClkFreq(void)
+{
+
+    return (SYSCON->USB1CLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->USB1CLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->USB1CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->USB1CLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get MCLK Clk */
+uint32_t CLOCK_GetMclkClkFreq(void)
+{
+    return (SYSCON->MCLKCLKSEL == 0U) ? CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & 0xffu) + 1U):
+           (SYSCON->MCLKCLKSEL == 1U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->MCLKCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get SCTIMER Clk */
+uint32_t CLOCK_GetSctClkFreq(void)
+{
+    return (SYSCON->SCTCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->SCTCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->SCTCLKSEL == 2U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->SCTCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->SCTCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get SDIO Clk */
+uint32_t CLOCK_GetSdioClkFreq(void)
+{
+    return (SYSCON->SDIOCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->SDIOCLKSEL == 1U) ? CLOCK_GetPllOutFreq():
+           (SYSCON->SDIOCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq():
+           (SYSCON->SDIOCLKSEL == 3U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->SDIOCLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq():
+           (SYSCON->SDIOCLKSEL == 7U) ? 0U:0U;
+}
+
+/* Get LCD Clk */
+uint32_t CLOCK_GetLcdClkFreq(void)
+{
+    return (SYSCON->LCDCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq():
+           (SYSCON->LCDCLKSEL == 1U) ? CLOCK_GetLcdClkIn():
+           (SYSCON->LCDCLKSEL == 2U) ? CLOCK_GetFroHfFreq():
+           (SYSCON->LCDCLKSEL == 3U) ? 0U:0U;
+}
+
+/* Get LCD CLK IN Clk */
+uint32_t CLOCK_GetLcdClkIn(void)
+{
+  return g_Lcd_Clk_In_Freq;
+}
+
+/* Get FRO 12M Clk */
+uint32_t CLOCK_GetFro12MFreq(void)
+{
+    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U;
+}
+
+/* Get EXT OSC Clk */
+uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return g_Ext_Clk_Freq;
+}
+
+/* Get WATCH DOG Clk */
+uint32_t CLOCK_GetWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
+        freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+    }
+}
+
+/* Get HF FRO Clk */
+uint32_t CLOCK_GetFroHfFreq(void)
+{
+    return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : 
+          !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 :
+           (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U;
+}
+
+/* Get SYSTEM PLL Clk */
+uint32_t CLOCK_GetPllOutFreq(void)
+{
+    return s_Pll_Freq;
+}
+
+/* Get AUDIO PLL Clk */
+uint32_t CLOCK_GetAudioPllOutFreq(void)
+{
+    return s_Audio_Pll_Freq;
+}
+
+/* Get USB PLL Clk */
+uint32_t CLOCK_GetUsbPllOutFreq(void)
+{
+    return s_Usb_Pll_Freq;
+}
+
+/* Get RTC OSC Clk */
+uint32_t CLOCK_GetOsc32KFreq(void)
+{
+    return CLK_RTC_32K_CLK;               /* Needs to be corrected to check that RTC Clock is enabled */
+}
+
+/* Get MAIN Clk */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? CLOCK_GetFro12MFreq() :
+           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? CLOCK_GetExtClkFreq() :
+           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? CLOCK_GetWdtOscFreq() :
+           ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? CLOCK_GetFroHfFreq() :
+           (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() :
+           (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U;
+}
+
+/* Get I2S MCLK Clk */
+uint32_t CLOCK_GetI2SMClkFreq(void)
+{
+    return g_I2S_Mclk_Freq;
+}
+
+/* Get ASYNC APB Clk */
+uint32_t CLOCK_GetAsyncApbClkFreq(void)
+{
+    async_clock_src_t clkSrc;
+    uint32_t clkRate;
+
+    clkSrc = CLOCK_GetAsyncApbClkSrc();
+
+    switch (clkSrc)
+    {
+        case kCLOCK_AsyncMainClk:
+            clkRate = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_AsyncFro12Mhz:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Get FLEXCOMM Clk */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
+{
+    return (SYSCON->FCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : 
+           (SYSCON->FCLKSEL[id] == 1U) ? CLOCK_GetFroHfFreq() :
+           (SYSCON->FCLKSEL[id] == 2U) ? CLOCK_GetPllOutFreq() :
+           (SYSCON->FCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() :
+           (SYSCON->FCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U;
+}
+
+/* Get FRG Clk */
+uint32_t CLOCK_GetFRGInputClock(void)
+{
+    return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : 
+           (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() :
+           (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : 
+           (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U;
+}
+
+/* Set FRG Clk */
+uint32_t CLOCK_SetFRGClock(uint32_t freq)
+{
+    uint32_t input = CLOCK_GetFRGInputClock();
+    uint32_t mul;
+
+    if ((freq > 48000000) || (freq > input) || (input / freq >= 2))
+    {
+        /* FRG output frequency should be less than equal to 48MHz */
+        return 0;
+    }
+    else
+    {
+        mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);
+        SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK;
+        return 1;
+    }
+}
+
+/* Set IP Clk */
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+    switch (clockName)
+    {
+        case kCLOCK_CoreSysClk:
+            freq = CLOCK_GetCoreSysClkFreq();
+            break;
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_ClockOut:
+            freq = CLOCK_GetClockOutClkFreq() / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_SpiFi:
+            freq = CLOCK_GetSpifiClkFreq() / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Adc:
+            freq = CLOCK_GetAdcClkFreq() / ((SYSCON->ADCCLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Usb0:
+            freq = CLOCK_GetUsb0ClkFreq() / ((SYSCON->USB0CLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Usb1:
+            freq = CLOCK_GetUsb1ClkFreq() / ((SYSCON->USB1CLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_Mclk:
+            freq = CLOCK_GetMclkClkFreq() / ((SYSCON->MCLKDIV & 0xffU) + 1U );
+            break;
+        case kCLOCK_FroHf:
+            freq = CLOCK_GetFroHfFreq();
+            break;
+        case kCLOCK_Fro12M:
+            freq = CLOCK_GetFro12MFreq();
+            break;
+        case kCLOCK_ExtClk:
+            freq = CLOCK_GetExtClkFreq();
+            break;
+        case kCLOCK_PllOut:
+            freq = CLOCK_GetPllOutFreq();
+            break;
+        case kClock_WdtOsc:
+            freq = CLOCK_GetWdtOscFreq();
+            break;
+        case kCLOCK_Frg:
+            freq = (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : 
+                   (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() :
+                   (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() :
+                   (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U;
+            break;
+        case kCLOCK_Dmic:
+            freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : 
+                   (SYSCON->DMICCLKSEL == 1U) ? CLOCK_GetFroHfFreq() :
+                   (SYSCON->DMICCLKSEL == 2U) ? CLOCK_GetPllOutFreq() :
+                   (SYSCON->DMICCLKSEL == 3U) ? CLOCK_GetI2SMClkFreq() :
+                   (SYSCON->DMICCLKSEL == 4U) ? CLOCK_GetCoreSysClkFreq() :
+                   (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U;
+            freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U);
+            break;
+
+        case kCLOCK_AsyncApbClk:
+            freq = CLOCK_GetAsyncApbClkFreq();
+            break;
+        case kCLOCK_Sct:
+            freq = CLOCK_GetSctClkFreq() / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_SDio:
+            freq = CLOCK_GetSdioClkFreq() / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_EMC:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U) / ((SYSCON->EMCCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_LCD:
+            freq = CLOCK_GetLcdClkFreq() / ((SYSCON->LCDCLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_MCAN0:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_MCAN1:
+            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U);
+            break;
+        case kCLOCK_FlexI2S:
+            freq = CLOCK_GetI2SMClkFreq();
+            break;
+        case kCLOCK_Flexcomm0:
+            freq = CLOCK_GetFlexCommClkFreq(0U);
+            break;
+        case kCLOCK_Flexcomm1:
+            freq = CLOCK_GetFlexCommClkFreq(1U);
+            break;
+        case kCLOCK_Flexcomm2:
+            freq = CLOCK_GetFlexCommClkFreq(2U);
+            break;
+        case kCLOCK_Flexcomm3:
+            freq = CLOCK_GetFlexCommClkFreq(3U);
+            break;
+        case kCLOCK_Flexcomm4:
+            freq = CLOCK_GetFlexCommClkFreq(4U);
+            break;
+        case kCLOCK_Flexcomm5:
+            freq = CLOCK_GetFlexCommClkFreq(5U);
+            break;
+        case kCLOCK_Flexcomm6:
+            freq = CLOCK_GetFlexCommClkFreq(6U);
+            break;
+        case kCLOCK_Flexcomm7:
+            freq = CLOCK_GetFlexCommClkFreq(7U);
+            break;
+        case kCLOCK_Flexcomm8:
+            freq = CLOCK_GetFlexCommClkFreq(8U);
+            break;
+        case kCLOCK_Flexcomm9:
+            freq = CLOCK_GetFlexCommClkFreq(9U);
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    return freq;
+}
+
+/* Set the FLASH wait states for the passed frequency */
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
+{
+    if (iFreq <= 12000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle);
+    }
+    else if (iFreq <= 24000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle);
+    }
+    else if (iFreq <= 36000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle);
+    }
+    else if (iFreq <= 60000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle);
+    }
+    else if (iFreq <= 96000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle);
+    }
+    else if (iFreq <= 120000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle);
+    }
+    else if (iFreq <= 144000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash7Cycle);
+    }
+    else if (iFreq <= 168000000U)
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash8Cycle);
+    }
+    else
+    {
+        CLOCK_SetFLASHAccessCycles(kCLOCK_Flash9Cycle);
+    }
+}
+
+/* Find encoded NDEC value for raw N value, max N = NVALMAX */
+static uint32_t pllEncodeN(uint32_t N)
+{
+    uint32_t x, i;
+
+    /* Find NDec */
+    switch (N)
+    {
+        case 0U:
+            x = 0x3FFU;
+            break;
+
+        case 1U:
+            x = 0x302U;
+            break;
+
+        case 2U:
+            x = 0x202U;
+            break;
+
+        default:
+            x = 0x080U;
+            for (i = N; i <= NVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+            }
+            break;
+    }
+
+    return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P);
+}
+
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0x3FFU:
+            n = 0U;
+            break;
+
+        case 0x302U:
+            n = 1U;
+            break;
+
+        case 0x202U:
+            n = 2U;
+            break;
+
+        default:
+            x = 0x080U;
+            n = 0xFFFFFFFFU;
+            for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+            }
+            break;
+    }
+
+    return n;
+}
+
+/* Find encoded PDEC value for raw P value, max P = PVALMAX */
+static uint32_t pllEncodeP(uint32_t P)
+{
+    uint32_t x, i;
+
+    /* Find PDec */
+    switch (P)
+    {
+        case 0U:
+            x = 0x7FU;
+            break;
+
+        case 1U:
+            x = 0x62U;
+            break;
+
+        case 2U:
+            x = 0x42U;
+            break;
+
+        default:
+            x = 0x10U;
+            for (i = P; i <= PVALMAX; i++)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+            }
+            break;
+    }
+
+    return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P);
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0x7FU:
+            p = 0U;
+            break;
+
+        case 0x62U:
+            p = 1U;
+            break;
+
+        case 0x42U:
+            p = 2U;
+            break;
+
+        default:
+            x = 0x10U;
+            p = 0xFFFFFFFFU;
+            for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+            }
+            break;
+    }
+
+    return p;
+}
+
+/* Find encoded MDEC value for raw M value, max M = MVALMAX */
+static uint32_t pllEncodeM(uint32_t M)
+{
+    uint32_t i, x;
+
+    /* Find MDec */
+    switch (M)
+    {
+        case 0U:
+            x = 0x1FFFFU;
+            break;
+
+        case 1U:
+            x = 0x18003U;
+            break;
+
+        case 2U:
+            x = 0x10003U;
+            break;
+
+        default:
+            x = 0x04000U;
+            for (i = M; i <= MVALMAX; i++)
+            {
+                x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU);
+            }
+            break;
+    }
+
+    return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P);
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0x1FFFFU:
+            m = 0U;
+            break;
+
+        case 0x18003U:
+            m = 1U;
+            break;
+
+        case 0x10003U:
+            m = 2U;
+            break;
+
+        default:
+            x = 0x04000U;
+            m = 0xFFFFFFFFU;
+            for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--)
+            {
+                x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU);
+                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+            }
+            break;
+    }
+
+    return m;
+}
+
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)
+{
+    /* bandwidth: compute selP from Multiplier */
+    if (M < 60U)
+    {
+        *pSelP = (M >> 1U) + 1U;
+    }
+    else
+    {
+        *pSelP = PVALMAX - 1U;
+    }
+
+    /* bandwidth: compute selI from Multiplier */
+    if (M > 16384U)
+    {
+        *pSelI = 1U;
+    }
+    else if (M > 8192U)
+    {
+        *pSelI = 2U;
+    }
+    else if (M > 2048U)
+    {
+        *pSelI = 4U;
+    }
+    else if (M >= 501U)
+    {
+        *pSelI = 8U;
+    }
+    else if (M >= 60U)
+    {
+        *pSelI = 4U * (1024U / (M + 9U));
+    }
+    else
+    {
+        *pSelI = (M & 0x3CU) + 4U;
+    }
+
+    if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT))
+    {
+        *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT);
+    }
+
+    *pSelR = 0U;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FFU);
+        if (preDiv == 0U)
+        {
+            preDiv = 1U;
+        }
+    }
+
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1U;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2U * pllDecodeP(pDecReg & 0x7FU);
+        if (postDiv == 0U)
+        {
+            postDiv = 2U;
+        }
+    }
+
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1U;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFFU);
+
+    if (mMult == 0U)
+    {
+        mMult = 1U;
+    }
+
+    return mMult;
+}
+
+/* Find greatest common divisor between m and n */
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
+{
+    uint32_t tmp;
+
+    while (n != 0U)
+    {
+        tmp = n;
+        n = m % n;
+        m = tmp;
+    }
+
+    return m;
+}
+
+/* Set PLL output based on desired output rate */
+static pll_error_t CLOCK_GetPllConfig(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+    uint32_t nDivOutHz, fccoHz, multFccoDiv;
+    uint32_t pllPreDivider, pllMultiplier, pllPostDivider;
+    uint32_t pllDirectInput, pllDirectOutput;
+    uint32_t pllSelP, pllSelI, pllSelR, uplimoff;
+
+    /* Baseline parameters (no input or output dividers) */
+    pllPreDivider = 1U;  /* 1 implies pre-divider will be disabled */
+    pllPostDivider = 0U; /* 0 implies post-divider will be disabled */
+    pllDirectOutput = 1U;
+    multFccoDiv = 2U;
+
+    /* Verify output rate parameter */
+    if (foutHz > PLL_MAX_CCO_FREQ_MHZ)
+    {
+        /* Maximum PLL output with post divider=1 cannot go above this frequency */
+        return kStatus_PLL_OutputTooHigh;
+    }
+    if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))
+    {
+        /* Minmum PLL output with maximum post divider cannot go below this frequency */
+        return kStatus_PLL_OutputTooLow;
+    }
+
+    /* Verify input rate parameter */
+    if (finHz < PLL_LOWER_IN_LIMIT)
+    {
+        /* Input clock into the PLL cannot be lower than this */
+        return kStatus_PLL_InputTooLow;
+    }
+
+    /* Find the optimal CCO frequency for the output and input that
+       will keep it inside the PLL CCO range. This may require
+       tweaking the post-divider for the PLL. */
+    fccoHz = foutHz;
+    while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)
+    {
+        /* CCO output is less than minimum CCO range, so the CCO output
+           needs to be bumped up and the post-divider is used to bring
+           the PLL output back down. */
+        pllPostDivider++;
+        if (pllPostDivider > PVALMAX)
+        {
+            return kStatus_PLL_OutsideIntLimit;
+        }
+
+        /* Target CCO goes up, PLL output goes down */
+        fccoHz = foutHz * (pllPostDivider * 2U);
+        pllDirectOutput = 0U;
+    }
+
+    /* Determine if a pre-divider is needed to get the best frequency */
+    if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz))
+    {
+        uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz));
+
+        if (a > 20000U)
+        {
+            a = (multFccoDiv * finHz) / a;
+            if ((a != 0U) && (a < PLL_MAX_N_DIV))
+            {
+                pllPreDivider = a;
+            }
+        }
+    }
+
+    /* Bypass pre-divider hardware if pre-divider is 1 */
+    if (pllPreDivider > 1U)
+    {
+        pllDirectInput = 0U;
+    }
+    else
+    {
+        pllDirectInput = 1U;
+    }
+
+    /* Determine PLL multipler */
+    nDivOutHz = (finHz / pllPreDivider);
+    pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv;
+
+    /* Find optimal values for filter */
+    /* Will bumping up M by 1 get us closer to the desired CCO frequency? */
+    if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))
+    {
+        pllMultiplier++;
+    }
+
+    /* Setup filtering */
+    pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);
+    uplimoff = 0U;
+
+    /* Get encoded value for M (mult) and use manual filter, disable SS mode */
+    pSetup->pllmdec =
+        PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) ;
+
+    /* Get encoded values for N (prediv) and P (postdiv) */
+    pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider));
+    pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider));
+
+    /* PLL control */
+    pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) |                  /* Filter coefficient */
+                         (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) |                  /* Filter coefficient */
+                         (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) |                  /* Filter coefficient */
+                         (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) |                      /* PLL bypass mode disabled */
+                         (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) |             /* SS/fractional mode disabled */
+                         (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */
+                         (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */
+
+    return kStatus_PLL_Success;
+}
+
+
+/* Update SYSTEM PLL rate variable */
+static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup);
+}
+
+/* Update AUDIO PLL rate variable */
+static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup)
+{
+    s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup);
+}
+
+/* Update USB PLL rate variable */
+static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup)
+{
+    s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup);
+}
+
+/* Return System PLL input clock rate */
+uint32_t CLOCK_GetSystemPLLInClockRate(void)
+{
+    uint32_t clkRate = 0U;
+
+    switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK))
+    {
+        case 0x00U:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+
+        case 0x01U:
+            clkRate = CLOCK_GetExtClkFreq();
+            break;
+
+        case 0x02U:
+            clkRate = CLOCK_GetWdtOscFreq();
+            break;
+
+        case 0x03U:
+            clkRate = CLOCK_GetOsc32KFreq();
+            break;
+
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Return Audio PLL input clock rate */
+uint32_t CLOCK_GetAudioPLLInClockRate(void)
+{
+    uint32_t clkRate = 0U;
+
+    switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK))
+    {
+        case 0x00U:
+            clkRate = CLK_FRO_12MHZ;
+            break;
+
+        case 0x01U:
+            clkRate = CLOCK_GetExtClkFreq();
+            break;
+            
+        default:
+            clkRate = 0U;
+            break;
+    }
+
+    return clkRate;
+}
+
+/* Return System PLL output clock rate from setup structure */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, mMult, inPllRate;
+    uint64_t workRate;
+
+    inPllRate = CLOCK_GetSystemPLLInClockRate();
+    /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/
+    if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+        /*
+         * 1. Pre-divider
+         * Pre-divider is only available when the DIRECTI is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK))
+        {
+            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+        }
+        else
+        {
+            prediv = 1U; /* The pre-divider is bypassed. */
+        }
+        /*
+         * 2. Post-divider
+         * Post-divider is only available when the DIRECTO is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK))
+        {
+            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+        }
+        else
+        {
+            postdiv = 1U;           /* The post-divider is bypassed. */
+        }
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        /* MDEC used for rate */
+        mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+        workRate = workRate / ((uint64_t)postdiv);
+        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Return Usb PLL output clock rate from setup structure */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup)
+{
+    uint32_t nsel, psel, msel, inPllRate;
+    uint64_t workRate;
+    inPllRate = CLOCK_GetExtClkFreq();
+    msel = pSetup->msel;
+    psel = pSetup->psel;
+    nsel = pSetup->nsel;
+
+    if (pSetup->fbsel == 1U)
+       {   
+           /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
+           workRate = (inPllRate) * (msel + 1U) / (nsel + 1U);
+       }
+       else
+       {
+           /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+           workRate = (inPllRate / (nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel));
+       }
+   
+    return (uint32_t)workRate;
+}
+
+/* Return Audio PLL output clock rate from setup structure */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup)
+{
+    uint32_t prediv, postdiv, mMult, inPllRate;
+    uint64_t workRate;
+
+    inPllRate = CLOCK_GetAudioPLLInClockRate();
+    if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+    {
+        /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+        /*
+         * 1. Pre-divider
+         * Pre-divider is only available when the DIRECTI is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
+        {
+            prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+        }
+        else
+        {
+            prediv = 1U; /* The pre-divider is bypassed. */
+        }
+        /*
+         * 2. Post-divider
+         * Post-divider is only available when the DIRECTO is disabled.
+         */
+        if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
+        {
+            postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+        }
+        else
+        {
+            postdiv = 1U;           /* The post-divider is bypassed. */
+        }
+        /* Adjust input clock */
+        inPllRate = inPllRate / prediv;
+
+        /* MDEC used for rate */
+        mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec);
+        workRate = (uint64_t)inPllRate * (uint64_t)mMult;
+
+        workRate = workRate / ((uint64_t)postdiv);
+        workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+    }
+    else
+    {
+        /* In bypass mode */
+        workRate = (uint64_t)inPllRate;
+    }
+
+    return (uint32_t)workRate;
+}
+
+/* Set the current PLL Rate */
+void CLOCK_SetStoredPLLClockRate(uint32_t rate)
+{
+    s_Pll_Freq = rate;
+}
+
+/* Set the current Audio PLL Rate */
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate)
+{
+    s_Audio_Pll_Freq = rate;
+}
+
+/* Set the current Usb PLL Rate */
+void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate)
+{
+    s_Usb_Pll_Freq = rate;
+}
+
+/* Return System PLL output clock rate */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute)
+{
+    pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Pll_Freq == 0U))
+    {
+        Setup.pllctrl = SYSCON->SYSPLLCTRL;
+        Setup.pllndec = SYSCON->SYSPLLNDEC;
+        Setup.pllpdec = SYSCON->SYSPLLPDEC;
+        Setup.pllmdec = SYSCON->SYSPLLMDEC;
+
+        CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Pll_Freq;
+
+    return rate;
+}
+
+/* Return AUDIO PLL output clock rate */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute)
+{
+    pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Audio_Pll_Freq == 0U))
+    {
+        Setup.pllctrl = SYSCON->AUDPLLCTRL;
+        Setup.pllndec = SYSCON->AUDPLLNDEC;
+        Setup.pllpdec = SYSCON->AUDPLLPDEC;
+        Setup.pllmdec = SYSCON->AUDPLLMDEC;
+
+        CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Audio_Pll_Freq;
+    return rate;
+}
+
+/* Return USB PLL output clock rate */
+uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute)
+{
+    usb_pll_setup_t Setup;
+    uint32_t rate;
+
+    if ((recompute) || (s_Usb_Pll_Freq == 0U))
+    {
+        Setup.msel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK;
+        Setup.psel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK;
+        Setup.nsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK;
+        Setup.fbsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK;
+        Setup.bypass = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK;
+        Setup.direct = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK; 
+        CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup);
+    }
+
+    rate = s_Usb_Pll_Freq;
+    return rate;
+}
+
+/* Set PLL output based on the passed PLL setup data */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+    uint32_t inRate;
+    pll_error_t pllError;
+
+    /* Determine input rate for the PLL */
+    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+    {
+        inRate = pControl->inputRate;
+    }
+    else
+    {
+        inRate = CLOCK_GetSystemPLLInClockRate();
+    }
+
+    /* PLL flag options */
+    pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+    pSetup->pllRate = pControl->desiredRate;
+    return pllError;
+}
+
+/* Set PLL output from PLL setup structure */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+    /*!< Set FLASH waitstates for core */
+    CLOCK_SetFLASHAccessCyclesForFreq(pSetup->pllRate);
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup);
+
+    /* System voltage adjustment, occurs prior to setting main system clock */
+    if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)
+    {
+        POWER_SetVoltageForFreq(s_Pll_Freq);
+    }
+
+    return kStatus_PLL_Success;
+}
+
+
+/* Set AUDIO PLL output from AUDIO PLL setup structure */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    pSetup->flags = flagcfg;
+
+    /* Write PLL setup data */
+    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->AUDPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+        /* Set mreq to activate */
+        SYSCON->AUDPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->AUDPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->AUDPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsAudioPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup);
+
+    return kStatus_PLL_Success;
+}
+
+/* Set Audio PLL output based on the passed Audio PLL setup data */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
+{
+    uint32_t inRate;
+    pll_error_t pllError;
+
+    /* Determine input rate for the PLL */
+    if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)
+    {
+        inRate = pControl->inputRate;
+    }
+    else
+    {
+        inRate = CLOCK_GetAudioPLLInClockRate();
+    }
+
+    /* PLL flag options */
+    pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup);
+    pSetup->pllRate = pControl->desiredRate;
+    return pllError;
+}
+
+
+
+/* Setup PLL Frequency from pre-calculated value */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup)
+{
+    if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+    /* Write PLL setup data */
+    SYSCON->SYSPLLCTRL = pSetup->pllctrl;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec;
+    SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec;
+    SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec;
+    SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsSystemPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    s_Pll_Freq = pSetup->pllRate;
+
+    return kStatus_PLL_Success;
+}
+
+/* Setup Audio PLL Frequency from pre-calculated value */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup)
+{
+    if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+    {
+       /* Turn on the ext clock if system pll input select clk_in */
+       CLOCK_Enable_SysOsc(true);
+    }
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    /* Power off Audio PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+    /* Write Audio PLL setup data */
+    SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
+    SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT);  /* latch */
+    SYSCON->AUDPLLNDEC = pSetup->pllndec;
+    SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_AUDPLLNDEC_NREQ_SHIFT);    /* latch */
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+    SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_AUDPLLPDEC_PREQ_SHIFT);    /* latch */
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+    SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_AUDPLLMDEC_MREQ_SHIFT);    /* latch */
+    SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1);                              /* disable fractional function */
+
+    /* Flags for lock or power on */
+    if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0)
+    {
+        /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
+        volatile uint32_t delayX;
+        uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
+        uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U);
+
+        /* Initialize  and power up PLL */
+        SYSCON->SYSPLLMDEC = maxCCO;
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+        /* Set mreq to activate */
+        SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U);
+
+        /* Delay for 72 uSec @ 12Mhz */
+        for (delayX = 0U; delayX < 172U; ++delayX)
+        {
+        }
+
+        /* clear mreq to prepare for restoring mreq */
+        SYSCON->SYSPLLMDEC = curSSCTRL;
+
+        /* set original value back and activate */
+        SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U);
+
+        /* Enable peripheral states by setting low */
+        POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+    }
+    if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+    {
+        while (CLOCK_IsAudioPLLLocked() == false)
+        {
+        }
+    }
+
+    /* Update current programmed PLL rate var */
+    s_Audio_Pll_Freq = pSetup->pllRate;
+
+    return kStatus_PLL_Success;
+}
+
+/* Setup USB PLL Frequency from pre-calculated value */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup)
+{       
+    uint32_t usbpllctrl, fccoHz;
+    uint8_t msel, psel, nsel;
+    bool pllDirectInput, pllDirectOutput, pllfbsel;
+    volatile uint32_t delayX;
+
+    msel = pSetup->msel;
+    psel = pSetup->psel;
+    nsel = pSetup->nsel;
+    pllDirectInput = pSetup->direct;
+    pllDirectOutput = pSetup->bypass;
+    pllfbsel = pSetup->fbsel;
+    
+    /* Input clock into the PLL cannot be lower than this */
+    if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT )
+    {
+        return kStatus_PLL_InputTooLow;
+    }
+    
+    if (pllfbsel == 1U)
+    {   
+        /*integer_mode: Fout = M*(Fin/N),  Fcco = 2*P*M*(Fin/N) */
+        fccoHz = (pSetup->inputRate / (nsel + 1U)) * 2 * (msel + 1U) * SWITCH_USB_PSEL(psel) ;
+        
+        /* USB PLL CCO out rate cannot be lower than this */        
+        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+        {       
+            return kStatus_PLL_CCOTooLow;
+        }
+        /* USB PLL CCO out rate cannot be Higher than this */
+        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+        { 
+            return kStatus_PLL_CCOTooHigh;
+        }
+    }
+    else
+    {
+        /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */
+        fccoHz = pSetup->inputRate / (nsel + 1U) * (msel + 1U);
+        
+        /* USB PLL CCO out rate cannot be lower than this */        
+        if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ)
+        {       
+            return kStatus_PLL_CCOTooLow;
+        }
+        /* USB PLL CCO out rate cannot be Higher than this */
+        if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ)
+        { 
+            return kStatus_PLL_CCOTooHigh;
+        }       
+    }
+    
+    /* If configure the USB HOST clock, VD5 power for USB PHY should be enable 
+       before the the PLL is working */
+    /* Turn on the ext clock for usb pll input */
+    CLOCK_Enable_SysOsc(true);
+    
+    /* Enable power VD3 for PLLs */
+    POWER_SetPLL();
+    
+    /* Power on the VD5 for USB PHY */    
+    POWER_SetUsbPhy();
+
+    /* Power off USB PLL during setup changes */
+    POWER_EnablePD(kPDRUNCFG_PD_USB_PLL);
+      
+    /* Write USB PLL setup data */
+    usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel)  |                  /* NSEL VALUE */
+                 USB_PLL_PSEL_VAL_SET(psel)  |                  /* PSEL VALUE */
+                 USB_PLL_MSEL_VAL_SET(msel)  |                  /* MSEL VALUE */
+                 (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT  |            /* BYPASS DISABLE */
+                 (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT |            /* DIRECTO DISABLE */
+                 (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT;                     /* FBSEL SELECT */   
+    
+    SYSCON->USBPLLCTRL = usbpllctrl;
+    
+    POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+  
+    /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */
+    for (delayX = 0U; delayX < 172U; ++delayX)
+    {
+    }
+    
+    while (CLOCK_IsUsbPLLLocked() == false)
+    {
+    }
+    CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup);
+    return kStatus_PLL_Success;
+}
+
+/* Set System PLL clock based on the input frequency and multiplier */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq)
+{
+    uint32_t cco_freq = input_freq * multiply_by;
+    uint32_t pdec = 1U;
+    uint32_t selr;
+    uint32_t seli;
+    uint32_t selp;
+    uint32_t mdec, ndec;
+
+    uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1);
+
+    while (cco_freq < 275000000U)
+    {
+        multiply_by <<= 1U; /* double value in each iteration */
+        pdec <<= 1U;        /* correspondingly double pdec to cancel effect of double msel */
+        cco_freq = input_freq * multiply_by;
+    }
+    selr = 0U;
+    if (multiply_by < 60U)
+    {
+        seli = (multiply_by & 0x3cU) + 4U;
+        selp = (multiply_by >> 1U) + 1U;
+    }
+    else
+    {
+        selp = 31U;
+        if (multiply_by > 16384U)
+        {
+            seli = 1U;
+        }
+        else if (multiply_by > 8192U)
+        {
+            seli = 2U;
+        }
+        else if (multiply_by > 2048U)
+        {
+            seli = 4U;
+        }
+        else if (multiply_by >= 501U)
+        {
+            seli = 8U;
+        }
+        else
+        {
+            seli = 4U * (1024U / (multiply_by + 9U));
+        }
+    }
+
+    if (pdec > 1U)
+    {
+        directo = 0U;     /* use post divider */
+        pdec = pdec / 2U; /* Account for minus 1 encoding */
+                          /* Translate P value */
+        switch (pdec)
+        {
+            case 1U:
+                pdec = 0x62U; /* 1  * 2 */
+                break;
+            case 2U:
+                pdec = 0x42U; /* 2  * 2 */
+                break;
+            case 4U:
+                pdec = 0x02U; /* 4  * 2 */
+                break;
+            case 8U:
+                pdec = 0x0bU; /* 8  * 2 */
+                break;
+            case 16U:
+                pdec = 0x11U; /* 16 * 2 */
+                break;
+            case 32U:
+                pdec = 0x08U; /* 32 * 2 */
+                break;
+            default:
+                pdec = 0x08U;
+                break;
+        }
+    }
+
+    mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by));
+    ndec = 0x302U; /* pre divide by 1 (hardcoded) */
+
+    SYSCON->SYSPLLCTRL = directo |
+                         (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) |
+                         (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT);
+    SYSCON->SYSPLLPDEC = pdec | (1U << 7U);  /* set Pdec value and assert preq */
+    SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */
+    SYSCON->SYSPLLMDEC = (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */
+}
+
+/* Enable USB DEVICE FULL SPEED clock */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbd0);
+
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+    }
+    else
+    {
+        /*Set the USB PLL as the Usb0 CLK*/
+        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+        uint32_t delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }
+    }
+    CLOCK_EnableClock(kCLOCK_Usbd0);
+    CLOCK_EnableClock(kCLOCK_UsbRam1);
+    
+    return ret;
+}
+
+/* Enable USB HOST FULL SPEED clock */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_DisableClock(kCLOCK_Usbhmr0);
+    CLOCK_DisableClock(kCLOCK_Usbhsl0);
+
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+    }
+    else
+    {
+        /*Set the USB PLL as the Usb0 CLK*/
+        POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
+    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK);
+        uint32_t delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }
+    }
+    CLOCK_EnableClock(kCLOCK_Usbhmr0);
+    CLOCK_EnableClock(kCLOCK_Usbhsl0);
+    CLOCK_EnableClock(kCLOCK_UsbRam1); 
+
+    return ret;
+}
+
+/* Enable USB DEVICE HIGH SPEED clock */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+    uint32_t delay;
+    CLOCK_DisableClock(kCLOCK_Usbd1);
+    /* Power on the VD5 for USB PHY */    
+    POWER_SetUsbPhy();
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+    }
+    else
+    {    
+        delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+      
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        
+        /* Select USB PLL output as USB clock src */
+        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);  
+    }
+
+    delay = 100000;
+    while (delay --)
+    {
+        __asm("nop");
+    }
+    /* Enable USB1D and USB1RAM */
+    CLOCK_EnableClock(kCLOCK_Usbd1);
+    CLOCK_EnableClock(kCLOCK_UsbRam1); 
+    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+    return ret;
+}
+
+
+/* Enable USB HOST HIGH SPEED clock */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+    uint32_t delay;
+    CLOCK_DisableClock(kCLOCK_Usbh1);
+    /* Power on the VD5 for USB PHY */    
+    POWER_SetUsbPhy();
+    if (kCLOCK_UsbSrcFro == src)
+    {
+        switch (freq)
+        {
+            case 96000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */
+                break;
+            
+            case 48000000U:
+                CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */
+                break;
+            
+            default:
+                ret = false;
+                break;
+        }
+        /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */
+        SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK |
+                          SYSCON_FROCTRL_USBCLKADJ_MASK;
+        /* Select FRO 96 or 48 MHz */
+        CLOCK_AttachClk(kFRO_HF_to_USB1_CLK);
+    }
+    else
+    {
+        delay = 100000;
+        while (delay --)
+        {
+            __asm("nop");
+        }    
+        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };
+
+        CLOCK_SetUsbPLLFreq(&pll_setup);
+        
+        /* Select USB PLL output as USB clock src */
+        CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false);
+        CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK);
+    }
+
+    delay = 100000;
+    while (delay --)
+    {
+        __asm("nop");
+    }
+    /* Enable USBh1 and USB1RAM */
+    CLOCK_EnableClock(kCLOCK_Usbh1);
+    CLOCK_EnableClock(kCLOCK_UsbRam1); 
+    POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */
+    return ret;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1265 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name ofcopyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_device_registers.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could contol the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+/*! @brief Clock ip name array for ROM. */
+#define ADC_CLOCKS \
+    {              \
+        kCLOCK_Adc0 \
+    }
+/*! @brief Clock ip name array for ROM. */
+#define ROM_CLOCKS \
+    {              \
+        kCLOCK_Rom \
+    }
+/*! @brief Clock ip name array for SRAM. */
+#define SRAM_CLOCKS \
+    {               \
+        kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
+    }
+/*! @brief Clock ip name array for FLASH. */
+#define FLASH_CLOCKS \
+    {                \
+        kCLOCK_Flash \
+    }
+/*! @brief Clock ip name array for FMC. */
+#define FMC_CLOCKS \
+    {              \
+        kCLOCK_Fmc \
+    }
+/*! @brief Clock ip name array for EEPROM. */
+#define EEPROM_CLOCKS  \
+    {                  \
+        kCLOCK_Eeprom  \
+    }
+/*! @brief Clock ip name array for SPIFI. */
+#define SPIFI_CLOCKS  \
+    {                 \
+        kCLOCK_Spifi  \
+    }
+/*! @brief Clock ip name array for INPUTMUX. */
+#define INPUTMUX_CLOCKS      \
+    {                        \
+        kCLOCK_InputMux      \
+    }
+/*! @brief Clock ip name array for IOCON. */
+#define IOCON_CLOCKS         \
+    {                        \
+        kCLOCK_Iocon         \
+    }
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS          \
+    {                        \
+        kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5     \
+    }
+/*! @brief Clock ip name array for PINT. */
+#define PINT_CLOCKS          \
+    {                        \
+        kCLOCK_Pint          \
+    }
+/*! @brief Clock ip name array for GINT. */
+#define GINT_CLOCKS          \
+    {                        \
+        kCLOCK_Gint, kCLOCK_Gint          \
+    }
+/*! @brief Clock ip name array for DMA. */
+#define DMA_CLOCKS          \
+    {                       \
+        kCLOCK_Dma          \
+    }
+/*! @brief Clock ip name array for CRC. */
+#define CRC_CLOCKS          \
+    {                       \
+        kCLOCK_Crc          \
+    }
+/*! @brief Clock ip name array for WWDT. */
+#define WWDT_CLOCKS          \
+    {                        \
+        kCLOCK_Wwdt          \
+    }
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS          \
+    {                       \
+        kCLOCK_Rtc          \
+    }
+/*! @brief Clock ip name array for ADC0. */
+#define ADC0_CLOCKS          \
+    {                        \
+        kCLOCK_Adc0          \
+    }
+/*! @brief Clock ip name array for MRT. */
+#define MRT_CLOCKS           \
+    {                        \
+        kCLOCK_Mrt           \
+    }
+/*! @brief Clock ip name array for RIT. */
+#define RIT_CLOCKS           \
+    {                        \
+        kCLOCK_Rit           \
+    }
+/*! @brief Clock ip name array for SCT0. */
+#define SCT_CLOCKS          \
+    {                        \
+        kCLOCK_Sct0          \
+    }
+/*! @brief Clock ip name array for MCAN. */
+#define MCAN_CLOCKS          \
+    {                        \
+        kCLOCK_Mcan0, kCLOCK_Mcan1          \
+    }
+/*! @brief Clock ip name array for UTICK. */
+#define UTICK_CLOCKS         \
+    {                        \
+        kCLOCK_Utick         \
+    }
+/*! @brief Clock ip name array for FLEXCOMM. */
+#define FLEXCOMM_CLOCKS                                                        \
+    {                                                                          \
+        kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \
+					kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7, \
+                                        kCLOCK_FlexComm8, kCLOCK_FlexComm9 \
+    }
+/*! @brief Clock ip name array for LPUART. */
+#define LPUART_CLOCKS                                                                                         \
+    {                                                                                                         \
+        kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
+            kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8,kCLOCK_MinUart9     \
+    }
+
+/*! @brief Clock ip name array for BI2C. */
+#define BI2C_CLOCKS                                                                                                     \
+    {                                                                                                                   \
+        kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7, \
+        kCLOCK_BI2c8, kCLOCK_BI2c9  \
+    }
+/*! @brief Clock ip name array for LSPI. */
+#define LPSI_CLOCKS                                                                                                     \
+    {                                                                                                                   \
+        kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7, \
+        kCLOCK_LSpi8, kCLOCK_LSpi9  \
+    }
+/*! @brief Clock ip name array for FLEXI2S. */
+#define FLEXI2S_CLOCKS                                                                                        \
+    {                                                                                                         \
+        kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
+            kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9                                                                  \
+    }
+/*! @brief Clock ip name array for DMIC. */
+#define DMIC_CLOCKS \
+    {               \
+        kCLOCK_DMic \
+    }
+/*! @brief Clock ip name array for CT32B. */
+#define CTIMER_CLOCKS                                                               \
+    {                                                                               \
+        kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4   \
+    }
+/*! @brief Clock ip name array for LCD. */
+#define LCD_CLOCKS  \
+    {               \
+        kCLOCK_Lcd  \
+    }
+/*! @brief Clock ip name array for SDIO. */
+#define SDIO_CLOCKS  \
+    {                \
+        kCLOCK_Sdio  \
+    }
+/*! @brief Clock ip name array for USBRAM. */
+#define USBRAM_CLOCKS    \
+    {                    \
+        kCLOCK_UsbRam1   \
+    }
+/*! @brief Clock ip name array for EMC. */
+#define EMC_CLOCKS       \
+    {                    \
+        kCLOCK_Emc       \
+    }
+/*! @brief Clock ip name array for ETH. */
+#define ETH_CLOCKS       \
+    {                    \
+        kCLOCK_Eth       \
+    }
+/*! @brief Clock ip name array for AES. */
+#define AES_CLOCKS       \
+    {                    \
+        kCLOCK_Aes       \
+    }
+/*! @brief Clock ip name array for OTP. */
+#define OTP_CLOCKS       \
+    {                    \
+        kCLOCK_Otp       \
+    }
+/*! @brief Clock ip name array for RNG. */
+#define RNG_CLOCKS       \
+    {                    \
+        kCLOCK_Rng       \
+    }
+/*! @brief Clock ip name array for USBHMR0. */
+#define USBHMR0_CLOCKS       \
+    {                        \
+        kCLOCK_Usbhmr0       \
+    }
+/*! @brief Clock ip name array for USBHSL0. */
+#define USBHSL0_CLOCKS       \
+    {                        \
+        kCLOCK_Usbhsl0       \
+    }
+/*! @brief Clock ip name array for SHA0. */
+#define SHA0_CLOCKS       \
+    {                     \
+        kCLOCK_Sha0       \
+    }
+/*! @brief Clock ip name array for SMARTCARD. */
+#define SMARTCARD_CLOCKS  \
+    {                     \
+        kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
+    }
+/*! @brief Clock ip name array for USBD. */
+#define USBD_CLOCKS  \
+    {                \
+        kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
+    }
+/*! @brief Clock ip name array for USBH. */
+#define USBH_CLOCKS  \
+    {                \
+        kCLOCK_Usbh1 \
+    }
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+/*------------------------------------------------------------------------------
+ clock_ip_name_t definition:
+------------------------------------------------------------------------------*/
+
+#define CLK_GATE_REG_OFFSET_SHIFT 8U
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+
+#define CLK_GATE_DEFINE(reg_offset, bit_shift)                                  \
+    ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
+     (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
+
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
+
+#define AHB_CLK_CTRL0 0
+#define AHB_CLK_CTRL1 1
+#define AHB_CLK_CTRL2 2
+#define ASYNC_CLK_CTRL0 3
+
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
+typedef enum _clock_ip_name
+{
+    kCLOCK_IpInvalid = 0U,
+    kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
+    kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
+    kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
+    kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
+    kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
+    kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
+    kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9),
+    kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
+    kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
+    kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
+    kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
+    kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
+    kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
+    kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
+    kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
+    kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
+    kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
+    kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
+    kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
+    kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
+    kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
+    kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
+    kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
+    kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
+    kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
+    kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
+    kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
+    kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
+    kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
+    kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
+    kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
+    kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
+    kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
+    kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
+    kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
+    kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
+    kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
+    kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
+    kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
+    kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
+    kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
+    kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
+    kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
+    kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
+    kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
+    kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
+    kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
+    kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
+    kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2,8),
+    kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
+    kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
+    kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
+    kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
+    kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
+    kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
+    kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
+    kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
+    kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
+    kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
+    kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
+    kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
+
+    kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
+    kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
+} clock_ip_name_t;
+
+/*! @brief Clock name used to get clock frequency. */
+typedef enum _clock_name
+{
+    kCLOCK_CoreSysClk,  /*!< Core/system clock  (aka MAIN_CLK)                       */
+    kCLOCK_BusClk,      /*!< Bus clock (AHB clock)                                   */
+    kCLOCK_ClockOut,    /*!< CLOCKOUT                                                */
+    kCLOCK_FroHf,       /*!< FRO48/96                                                */
+    kCLOCK_SpiFi,       /*!< SPIFI                                                   */
+    kCLOCK_Adc,         /*!< ADC                                                     */
+    kCLOCK_Usb0,        /*!< USB0                                                    */
+    kCLOCK_Usb1,        /*!< USB1                                                    */
+    kCLOCK_UsbPll,      /*!< USB1 PLL                                                */
+    kCLOCK_Mclk,        /*!< MCLK                                                    */
+    kCLOCK_Sct,         /*!< SCT                                                     */
+    kCLOCK_SDio,        /*!< SDIO                                                    */
+    kCLOCK_EMC,         /*!< EMC                                                     */
+    kCLOCK_LCD,         /*!< LCD                                                     */
+    kCLOCK_MCAN0,       /*!< MCAN0                                                   */
+    kCLOCK_MCAN1,       /*!< MCAN1                                                   */
+    kCLOCK_Fro12M,      /*!< FRO12M                                                  */
+    kCLOCK_ExtClk,      /*!< External Clock                                          */
+    kCLOCK_PllOut,      /*!< PLL Output                                              */
+    kCLOCK_UsbClk,      /*!< USB input                                               */
+    kClock_WdtOsc,      /*!< Watchdog Oscillator                                     */
+    kCLOCK_Frg,         /*!< Frg Clock                                               */
+    kCLOCK_Dmic,        /*!< Digital Mic clock                                       */
+    kCLOCK_AsyncApbClk, /*!< Async APB clock										 */
+    kCLOCK_FlexI2S,     /*!< FlexI2S clock                                           */
+    kCLOCK_Flexcomm0,   /*!< Flexcomm0Clock                                          */
+    kCLOCK_Flexcomm1,   /*!< Flexcomm1Clock                                          */
+    kCLOCK_Flexcomm2,   /*!< Flexcomm2Clock                                          */
+    kCLOCK_Flexcomm3,   /*!< Flexcomm3Clock                                          */
+    kCLOCK_Flexcomm4,   /*!< Flexcomm4Clock                                          */
+    kCLOCK_Flexcomm5,   /*!< Flexcomm5Clock                                          */
+    kCLOCK_Flexcomm6,   /*!< Flexcomm6Clock                                          */
+    kCLOCK_Flexcomm7,   /*!< Flexcomm7Clock                                          */
+    kCLOCK_Flexcomm8,   /*!< Flexcomm8Clock                                          */
+    kCLOCK_Flexcomm9,   /*!< Flexcomm9Clock                                          */
+
+} clock_name_t;
+
+/**
+ * Clock source selections for the asynchronous APB clock
+ */
+typedef enum _async_clock_src
+{
+    kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
+    kCLOCK_AsyncFro12Mhz,    /*!< 12MHz FRO */
+    kCLOCK_AsyncAudioPllClk,
+    kCLOCK_AsyncI2cClkFc6,
+
+} async_clock_src_t;
+
+/*! @brief Clock Mux Switches
+*  The encoding is as follows each connection identified is 64bits wide
+*  starting from LSB upwards
+*
+*  [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
+*
+*/
+
+#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
+#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
+#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
+#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
+#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
+
+#define CM_MAINCLKSELA 0
+#define CM_MAINCLKSELB 1
+#define CM_CLKOUTCLKSELA 2
+#define CM_SYSPLLCLKSEL 4
+#define CM_AUDPLLCLKSEL 6
+#define CM_SPIFICLKSEL 8
+#define CM_ADCASYNCCLKSEL 9
+#define CM_USB0CLKSEL 10
+#define CM_USB1CLKSEL 11
+#define CM_FXCOMCLKSEL0 12
+#define CM_FXCOMCLKSEL1 13
+#define CM_FXCOMCLKSEL2 14
+#define CM_FXCOMCLKSEL3 15
+#define CM_FXCOMCLKSEL4 16
+#define CM_FXCOMCLKSEL5 17
+#define CM_FXCOMCLKSEL6 18
+#define CM_FXCOMCLKSEL7 19
+#define CM_FXCOMCLKSEL8 20
+#define CM_FXCOMCLKSEL9 21
+#define CM_MCLKCLKSEL 24
+#define CM_FRGCLKSEL 26
+#define CM_DMICCLKSEL 27
+#define CM_SCTCLKSEL  28
+#define CM_LCDCLKSEL  29
+#define CM_SDIOCLKSEL 30
+
+#define CM_ASYNCAPB 31
+
+typedef enum _clock_attach_id
+{
+
+    kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
+    kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
+    kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
+    kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0),
+    kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
+    kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
+
+    kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
+    kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
+    kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
+    kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
+    kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
+    kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
+    kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
+    kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
+
+    kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
+    kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
+    kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
+    kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
+    kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
+
+    kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
+    kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
+    kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
+
+    kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
+    kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
+    kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
+    kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
+    kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
+    kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
+
+    kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
+    kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
+    kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
+    kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
+    kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
+
+    kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
+    kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
+    kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
+    kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
+
+    kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
+    kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
+    kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
+    kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
+
+    kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
+    kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
+    kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
+    kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
+    kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
+    kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
+
+    kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
+    kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
+    kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
+    kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
+    kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
+    kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
+
+    kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
+    kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
+    kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
+    kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
+    kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
+    kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
+
+    kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
+    kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
+    kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
+    kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
+    kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
+    kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
+
+    kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
+    kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
+    kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
+    kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
+    kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
+    kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
+
+    kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
+    kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
+    kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
+    kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
+    kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
+    kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
+
+    kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
+    kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
+    kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
+    kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
+    kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
+    kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
+
+    kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
+    kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
+    kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
+    kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
+    kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
+    kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
+
+    kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
+    kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
+    kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
+    kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
+    kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
+    kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
+
+    kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
+    kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
+    kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
+    kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
+    kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
+    kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
+
+    kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
+    kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
+    kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
+
+    kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
+    kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
+    kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
+    kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
+    kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
+
+    kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
+    kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
+    kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
+    kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
+    kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
+
+    kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
+    kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
+    kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
+    kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
+    kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
+
+    kMCLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
+    kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
+    kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
+    kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
+    kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
+    kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
+
+    kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
+    kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
+    kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
+    kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
+
+    kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
+    kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
+    kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
+    kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
+    kNONE_to_NONE = 0x80000000U,
+} clock_attach_id_t;
+
+/*  Clock dividers */
+typedef enum _clock_div_name
+{
+    kCLOCK_DivSystickClk = 0,
+    kCLOCK_DivArmTrClkDiv = 1,
+    kCLOCK_DivCan0Clk = 2,
+    kCLOCK_DivCan1Clk = 3,
+    kCLOCK_DivSmartCard0Clk = 4,
+    kCLOCK_DivSmartCard1Clk = 5,
+    kCLOCK_DivAhbClk = 32,
+    kCLOCK_DivClkOut = 33,
+    kCLOCK_DivFrohfClk = 34,
+    kCLOCK_DivSpifiClk = 36,
+    kCLOCK_DivAdcAsyncClk = 37,
+    kCLOCK_DivUsb0Clk = 38,
+    kCLOCK_DivUsb1Clk = 39,
+    kCLOCK_DivFrg = 40,
+    kCLOCK_DivDmicClk = 42,
+    kCLOCK_DivMClk = 43,
+    kCLOCK_DivLcdClk = 44,
+    kCLOCK_DivSctClk = 45,
+    kCLOCK_DivEmcClk = 46,
+    kCLOCK_DivSdioClk = 47
+} clock_div_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 3)
+    {
+        SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+}
+
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)
+{
+    uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
+    if (index < 3)
+    {
+        SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+    }
+    else
+    {
+        ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
+        SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
+
+    }
+}
+/**
+ * @brief FLASH Access time definitions
+ */
+typedef enum _clock_flashtim
+{
+    kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */
+    kCLOCK_Flash2Cycle,     /*!< Flash accesses use 2 CPU clocks */
+    kCLOCK_Flash3Cycle,     /*!< Flash accesses use 3 CPU clocks */
+    kCLOCK_Flash4Cycle,     /*!< Flash accesses use 4 CPU clocks */
+    kCLOCK_Flash5Cycle,     /*!< Flash accesses use 5 CPU clocks */
+    kCLOCK_Flash6Cycle,     /*!< Flash accesses use 6 CPU clocks */
+    kCLOCK_Flash7Cycle,     /*!< Flash accesses use 7 CPU clocks */
+    kCLOCK_Flash8Cycle,     /*!< Flash accesses use 8 CPU clocks */
+    kCLOCK_Flash9Cycle      /*!< Flash accesses use 9 CPU clocks */
+} clock_flashtim_t;
+
+/**
+ * @brief	Set FLASH memory access time in clocks
+ * @param	clks	: Clock cycles for FLASH access
+ * @return	Nothing
+ */
+static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
+{
+    uint32_t tmp;
+
+    tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
+
+    /* Don't alter lower bits */
+    SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
+}
+
+/**
+ * @brief	Initialize the Core clock to given frequency (12, 48 or 96 MHz).
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
+ * enabled.
+ * @param	iFreq	: Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
+ * @return	returns success or fail status.
+ */
+status_t CLOCK_SetupFROClocking(uint32_t iFreq);
+/**
+ * @brief	Configure the clock selection muxes.
+ * @param	connection	: Clock to be configured.
+ * @return	Nothing
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+/**
+ * @brief	Setup peripheral clock dividers.
+ * @param	div_name	: Clock divider name
+ * @param divided_by_value: Value to be divided
+ * @param reset :  Whether to reset the divider counter.
+ * @return	Nothing
+ */
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
+/**
+ * @brief	Set the flash wait states for the input freuqency.
+ * @param	iFreq	: Input frequency
+ * @return	Nothing
+ */
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
+/*! @brief	Return Frequency of selected clock
+ *  @return	Frequency of selected clock
+ */
+uint32_t CLOCK_GetFreq(clock_name_t clockName);
+/*! @brief	Return Frequency of FRO 12MHz
+ *  @return	Frequency of FRO 12MHz
+ */
+uint32_t CLOCK_GetFro12MFreq(void);
+/*! @brief	Return Frequency of ClockOut
+ *  @return	Frequency of ClockOut
+ */
+uint32_t CLOCK_GetClockOutClkFreq(void);
+/*! @brief	Return Frequency of Spifi Clock
+ *  @return	Frequency of Spifi.
+ */
+uint32_t CLOCK_GetSpifiClkFreq(void);
+/*! @brief	Return Frequency of Adc Clock
+ *  @return	Frequency of Adc Clock.
+ */
+uint32_t CLOCK_GetAdcClkFreq(void);
+/*! @brief	Return Frequency of Usb0 Clock
+ *  @return	Frequency of Usb0 Clock.
+ */
+uint32_t CLOCK_GetUsb0ClkFreq(void);
+/*! @brief	Return Frequency of Usb1 Clock
+ *  @return	Frequency of Usb1 Clock.
+ */
+uint32_t CLOCK_GetUsb1ClkFreq(void);
+/*! @brief	Return Frequency of MClk Clock
+ *  @return	Frequency of MClk Clock.
+ */
+uint32_t CLOCK_GetMclkClkFreq(void);
+/*! @brief	Return Frequency of SCTimer Clock
+ *  @return	Frequency of SCTimer Clock.
+ */
+uint32_t CLOCK_GetSctClkFreq(void);
+/*! @brief	Return Frequency of SDIO Clock
+ *  @return	Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void);
+/*! @brief	Return Frequency of LCD Clock
+ *  @return	Frequency of LCD Clock.
+ */
+uint32_t CLOCK_GetLcdClkFreq(void);
+/*! @brief	Return Frequency of LCD CLKIN Clock
+ *  @return	Frequency of LCD CLKIN Clock.
+ */
+uint32_t CLOCK_GetLcdClkIn(void);
+/*! @brief	Return Frequency of External Clock
+ *  @return	Frequency of External Clock. If no external clock is used returns 0.
+ */
+uint32_t CLOCK_GetExtClkFreq(void);
+/*! @brief	Return Frequency of Watchdog Oscillator
+ *  @return	Frequency of Watchdog Oscillator
+ */
+uint32_t CLOCK_GetWdtOscFreq(void);
+/*! @brief	Return Frequency of High-Freq output of FRO
+ *  @return	Frequency of High-Freq output of FRO
+ */
+uint32_t CLOCK_GetFroHfFreq(void);
+/*! @brief	Return Frequency of PLL
+ *  @return	Frequency of PLL
+ */
+uint32_t CLOCK_GetPllOutFreq(void);
+/*! @brief	Return Frequency of USB PLL
+ *  @return	Frequency of PLL
+ */
+uint32_t CLOCK_GetUsbPllOutFreq(void);
+/*! @brief	Return Frequency of AUDIO PLL
+ *  @return	Frequency of PLL
+ */
+uint32_t CLOCK_GetAudioPllOutFreq(void);
+/*! @brief	Return Frequency of 32kHz osc
+ *  @return	Frequency of 32kHz osc
+ */
+uint32_t CLOCK_GetOsc32KFreq(void);
+/*! @brief	Return Frequency of Core System
+ *  @return	Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void);
+/*! @brief	Return Frequency of I2S MCLK Clock
+ *  @return	Frequency of I2S MCLK Clock
+ */
+uint32_t CLOCK_GetI2SMClkFreq(void);
+/*! @brief	Return Frequency of Flexcomm functional Clock
+ *  @return	Frequency of Flexcomm functional Clock
+ */
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
+/*! @brief	Return Asynchronous APB Clock source
+ *  @return	Asynchronous APB CLock source
+ */
+__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
+{
+    return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3);
+}
+/*! @brief	Return Frequency of Asynchronous APB Clock
+ *  @return	Frequency of Asynchronous APB Clock Clock
+ */
+uint32_t CLOCK_GetAsyncApbClkFreq(void);
+/*! @brief	Return Audio PLL input clock rate
+ *  @return	Audio PLL input clock rate
+ */
+uint32_t CLOCK_GetAudioPLLInClockRate(void);
+/*! @brief	Return System PLL input clock rate
+ *  @return	System PLL input clock rate
+ */
+uint32_t CLOCK_GetSystemPLLInClockRate(void);
+
+/*! @brief	Return System PLL output clock rate
+ *  @param	recompute	: Forces a PLL rate recomputation if true
+ *  @return	System PLL output clock rate
+ *  @note	The PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
+
+/*! @brief	Return System AUDIO PLL output clock rate
+ *  @param	recompute	: Forces a AUDIO PLL rate recomputation if true
+ *  @return	System AUDIO PLL output clock rate
+ *  @note	The AUDIO PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
+
+/*! @brief	Return System USB PLL output clock rate
+ *  @param	recompute	: Forces a USB PLL rate recomputation if true
+ *  @return	System USB PLL output clock rate
+ *  @note	The USB PLL rate is cached in the driver in a variable as
+ *  the rate computation function can take some time to perform. It
+ *  is recommended to use 'false' with the 'recompute' parameter.
+ */
+uint32_t CLOCK_GetUSbPLLOutClockRate(bool recompute);
+
+/*! @brief	Enables and disables PLL bypass mode
+ *  @brief	bypass	: true to bypass PLL (PLL output = PLL input, false to disable bypass
+ *  @return	System PLL output clock rate
+ */
+__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
+{
+    if (bypass)
+    {
+        SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+    else
+    {
+        SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
+    }
+}
+
+/*! @brief	Check if PLL is locked or not
+ *  @return	true if the PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
+{
+    return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0);
+}
+
+/*! @brief	Check if USB PLL is locked or not
+ *  @return	true if the USB PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
+{
+    return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0);
+}
+
+/*! @brief	Check if AUDIO PLL is locked or not
+ *  @return	true if the AUDIO PLL is locked, false if not locked
+ */
+__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
+{
+    return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0);
+}
+
+/*! @brief	Enables and disables SYS OSC
+ *  @brief	enable	: true to enable SYS OSC, false to disable SYS OSC
+*/
+__STATIC_INLINE  void CLOCK_Enable_SysOsc(bool enable)
+{
+    if(enable)
+    {
+        SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+        SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+    }
+
+    else
+    {
+        SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+        SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
+
+    }
+}
+
+/*! @brief Store the current PLL rate
+ *  @param	rate: Current rate of the PLL
+ *  @return	Nothing
+ **/
+void CLOCK_SetStoredPLLClockRate(uint32_t rate);
+
+/*! @brief Store the current AUDIO PLL rate
+ *  @param	rate: Current rate of the PLL
+ *  @return	Nothing
+ **/
+void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
+
+/*! @brief PLL configuration structure flags for 'flags' field
+ * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
+ *
+ * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
+ * configuration structure must be assigned with the expected PLL frequency. If the
+ * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
+ * function and the driver will determine the PLL rate from the currently selected
+ * PLL source. This flag might be used to configure the PLL input clock more accurately
+ * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
+ *
+ * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
+ * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
+ * are not used.<br>
+ */
+#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
+#define PLL_CONFIGFLAG_FORCENOFRACT                                                                                    \
+    (1                                                                                                                 \
+     << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \
+                \ \ \                                                                                                                     \
+                  \ \ \ \ \                                                                                                                     \
+                    \ \ \ \ \ \ \                                                                                                                     \
+                      hardware */
+
+/*! @brief PLL configuration structure
+ *
+ * This structure can be used to configure the settings for a PLL
+ * setup structure. Fill in the desired configuration for the PLL
+ * and call the PLL setup function to fill in a PLL setup structure.
+ */
+typedef struct _pll_config
+{
+    uint32_t desiredRate; /*!< Desired PLL rate in Hz */
+    uint32_t inputRate;   /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
+    uint32_t flags;       /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
+} pll_config_t;
+
+/*! @brief PLL setup structure flags for 'flags' field
+* These flags control how the PLL setup function sets up the PLL
+*/
+#define PLL_SETUPFLAG_POWERUP (1 << 0)  /*!< Setup will power on the PLL after setup */
+#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
+#define PLL_SETUPFLAG_ADGVOLT (1 << 2)  /*!< Optimize system voltage for the new PLL rate */
+
+/*! @brief PLL setup structure
+* This structure can be used to pre-build a PLL setup configuration
+* at run-time and quickly set the PLL to the configuration. It can be
+* populated with the PLL setup function. If powering up or waiting
+* for PLL lock, the PLL input clock source should be configured prior
+* to PLL setup.
+*/
+typedef struct _pll_setup
+{
+    uint32_t pllctrl;         /*!< PLL control register SYSPLLCTRL */
+    uint32_t pllndec;         /*!< PLL NDEC register SYSPLLNDEC */
+    uint32_t pllpdec;         /*!< PLL PDEC register SYSPLLPDEC */
+    uint32_t pllmdec;         /*!< PLL MDEC registers SYSPLLPDEC */
+    uint32_t pllRate;         /*!< Acutal PLL rate */
+    uint32_t audpllfrac;      /*!< only aduio PLL has this function*/
+    uint32_t flags;           /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
+} pll_setup_t;
+
+/*! @brief PLL status definitions
+ */
+typedef enum _pll_error
+{
+    kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0),         /*!< PLL operation was successful */
+    kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1),    /*!< PLL output rate request was too low */
+    kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2),   /*!< PLL output rate request was too high */
+    kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3),     /*!< PLL input rate is too low */
+    kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4),    /*!< PLL input rate is too high */
+    kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
+    kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6),       /*!< Requested CCO rate isn't possible */
+    kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7)       /*!< Requested CCO rate isn't possible */
+} pll_error_t;
+
+/*! @brief USB clock source definition. */
+typedef enum _clock_usb_src
+{
+    kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf,            /*!< Use FRO 96 or 48 MHz. */
+    kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut,     /*!< Use System PLL output. */
+    kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock.    */
+    kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll,        /*!< Use USB PLL clock.    */
+
+    kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(7)          /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
+} clock_usb_src_t;
+
+/*! @brief USB PDEL Divider. */
+typedef enum _usb_pll_psel
+{
+    pSel_Divide_1 = 0U,
+    pSel_Divide_2,
+    pSel_Divide_4,
+    pSel_Divide_8
+}usb_pll_psel;
+
+/*! @brief PLL setup structure
+* This structure can be used to pre-build a USB PLL setup configuration
+* at run-time and quickly set the usb PLL to the configuration. It can be
+* populated with the USB PLL setup function. If powering up or waiting
+* for USB PLL lock, the PLL input clock source should be configured prior
+* to USB PLL setup.
+*/
+typedef struct _usb_pll_setup
+{
+  uint8_t msel;           /*!< USB PLL control register msel:1U-256U */
+  uint8_t psel;           /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
+  uint8_t nsel;           /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
+  bool direct;            /*!< USB PLL CCO output control */
+  bool bypass;            /*!< USB PLL inout clock bypass control  */
+  bool fbsel;             /*!< USB PLL ineter mode and non-integer mode control*/
+  uint32_t inputRate;     /*!< USB PLL input rate */
+} usb_pll_setup_t;
+
+/*! @brief	Return System PLL output clock rate from setup structure
+ *  @param	pSetup	: Pointer to a PLL setup structure
+ *  @return	System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief	Return System AUDIO PLL output clock rate from setup structure
+ *  @param	pSetup	: Pointer to a PLL setup structure
+ *  @return	System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
+
+/*! @brief	Return System USB PLL output clock rate from setup structure
+ *  @param	pSetup	: Pointer to a PLL setup structure
+ *  @return	System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output based on the passed PLL setup data
+ *  @param	pControl	: Pointer to populated PLL control structure to generate setup with
+ *  @param	pSetup		: Pointer to PLL setup structure to be filled
+ *  @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  @note	Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief	Set AUDIO PLL output based on the passed AUDIO PLL setup data
+ *  @param	pControl	: Pointer to populated PLL control structure to generate setup with
+ *  @param	pSetup		: Pointer to PLL setup structure to be filled
+ *  @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ *  @note	Actual frequency for setup may vary from the desired frequency based on the
+ *  accuracy of input clocks, rounding, non-fractional PLL mode, etc.
+ */
+pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output from PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+* @param flagcfg : Flag configuration for PLL config structure
+ * @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/*! @brief	Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+* @param flagcfg : Flag configuration for PLL config structure
+ * @return	PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+
+/**
+ * @brief	Set PLL output from PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+ * @return	kStatus_PLL_Success on success, or PLL setup error code
+ * @note	This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief	Set Audio PLL output from Audio PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated PLL setup structure
+ * @return	kStatus_PLL_Success on success, or Audio PLL setup error code
+ * @note	This function will power off the PLL, setup the Audio PLL with the
+ * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
+ * and adjust system voltages to the new PLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
+
+/**
+ * @brief	Set USB PLL output from USB PLL setup structure (precise frequency)
+ * @param	pSetup	: Pointer to populated USB PLL setup structure
+ * @return	kStatus_PLL_Success on success, or USB PLL setup error code
+ * @note	This function will power off the USB PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
+ * and adjust system voltages to the new USB PLL rate. The function will not
+ * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
+
+/*! @brief	Set PLL output based on the multiplier and input frequency
+ * @param	multiply_by	: multiplier
+ * @param	input_freq	: Clock input frequency of the PLL
+ * @return	Nothing
+ * @note	Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
+ * function does not disable or enable PLL power, wait for PLL lock,
+ * or adjust system voltages. These must be done in the application.
+ * The function will not alter any source clocks (ie, main systen clock)
+ * that may use the PLL, so these should be setup prior to and after
+ * exiting the function.
+ */
+void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
+
+/*! @brief Disable USB clock.
+ *
+ * Disable USB clock.
+ */
+static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
+{
+    CLOCK_DisableClock(clk);
+}
+
+/*! @brief Enable USB Device FS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB Device Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST FS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB HOST Full Speed clock.
+ */
+bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB Device HS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB Device High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
+
+/*! @brief Enable USB HOST HS clock.
+ * @param	src	: clock source
+ * @param	freq: clock frequency
+ * Enable USB HOST High Speed clock.
+ */
+bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+/* This is not needed for mbed */
+#if 0
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif(defined(__REDLIB__))
+
+#if SDK_DEBUGCONSOLE
+void __assertion_failed(char *_Expr)
+{
+    PRINTF("%s\n", _Expr);
+    for (;;)
+    {
+        __asm("bkpt #0");
+    }
+}
+#endif
+
+#elif(defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
+#endif /* NDEBUG */
+#endif
+#ifndef __GIC_PRIO_BITS
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif
+
+#ifndef CPU_QN908X
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1u << intNumber;
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+#else
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    /*   SYSCON->STARTERSET[index] = 1u << intNumber; */
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+                           /*   SYSCON->STARTERCLR[index] = 1u << intNumber; */
+}
+#endif /*CPU_QN908X */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void EnableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_EnableIRQ(interrupt);
+#endif
+    }
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable the interrupt not routed from intmux.
+ *
+ * @param interrupt The IRQ number.
+ */
+static inline void DisableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
+#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
+    if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#endif
+    {
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
+        NVIC_DisableIRQ(interrupt);
+#endif
+    }
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+#if defined(CPSR_I_Msk)
+    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+    __disable_irq();
+
+    return cpsr;
+#else
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+#endif
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+    __set_PRIMASK(primask);
+#endif
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
+/* @brief Default user configuration structure for CRC-CCITT */
+#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
+/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
+#define CRC_DRIVER_DEFAULT_REVERSE_IN false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
+/*< Default is without complement of written data */
+#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
+/*< Default is no bit reverse */
+#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
+/*< Default is without complement of CRC data register read data */
+#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
+/*< Default initial checksum */
+#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void CRC_Init(CRC_Type *base, const crc_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable clock to CRC */
+    CLOCK_EnableClock(kCLOCK_Crc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* configure CRC module and write the seed */
+    base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
+                 CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
+                 CRC_MODE_CMPL_SUM(config->complementOut);
+    base->SEED = config->seed;
+}
+
+void CRC_GetDefaultConfig(crc_config_t *config)
+{
+    static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL,     CRC_DRIVER_DEFAULT_REVERSE_IN,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_IN,  CRC_DRIVER_DEFAULT_REVERSE_OUT,
+                                                CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
+
+    *config = default_config;
+}
+
+void CRC_Reset(CRC_Type *base)
+{
+    crc_config_t config;
+    CRC_GetDefaultConfig(&config);
+    CRC_Init(base, &config);
+}
+
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
+{
+    /* extract CRC mode settings */
+    uint32_t mode = base->MODE;
+    config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
+    config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
+    config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
+    config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
+    config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
+
+    /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
+    base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
+
+    /* now we can obtain intermediate raw CRC sum value */
+    config->seed = base->SUM;
+
+    /* restore original CRC sum bit reverse and 1's complement setting */
+    base->MODE = mode;
+}
+
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
+{
+    const uint32_t *data32;
+
+    /* 8-bit reads and writes till source address is aligned 4 bytes */
+    while ((dataSize) && ((uint32_t)data & 3U))
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+
+    /* use 32-bit reads and writes as long as possible */
+    data32 = (const uint32_t *)data;
+    while (dataSize >= sizeof(uint32_t))
+    {
+        *((__O uint32_t *)&(base->WR_DATA)) = *data32;
+        data32++;
+        dataSize -= sizeof(uint32_t);
+    }
+
+    data = (const uint8_t *)data32;
+
+    /* 8-bit reads and writes till end of data buffer */
+    while (dataSize)
+    {
+        *((__O uint8_t *)&(base->WR_DATA)) = *data;
+        data++;
+        dataSize--;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CRC driver version. Version 2.0.1.
+ *
+ * Current version: 2.0.1
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ * - Version 2.0.1
+ *   - add explicit type cast when writing to WR_DATA
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
+#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC polynomials to use. */
+typedef enum _crc_polynomial
+{
+    kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
+    kCRC_Polynomial_CRC_16 = 1U,    /*!< x^16+x^15+x^2+1 */
+    kCRC_Polynomial_CRC_32 = 2U     /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
+} crc_polynomial_t;
+
+/*!
+* @brief CRC protocol configuration.
+*
+* This structure holds the configuration for the CRC protocol.
+*
+*/
+typedef struct _crc_config
+{
+    crc_polynomial_t polynomial; /*!< CRC polynomial. */
+    bool reverseIn;              /*!< Reverse bits on input. */
+    bool complementIn;           /*!< Perform 1's complement on input. */
+    bool reverseOut;             /*!< Reverse bits on output. */
+    bool complementOut;          /*!< Perform 1's complement on output. */
+    uint32_t seed;               /*!< Starting checksum value. */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enables and configures the CRC peripheral module.
+ *
+ * This functions enables the CRC peripheral clock in the LPC SYSCON block.
+ * It also configures the CRC engine and starts checksum computation by writing the seed.
+ *
+ * @param base   CRC peripheral address.
+ * @param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disables the CRC peripheral module.
+ *
+ * This functions disables the CRC peripheral clock in the LPC SYSCON block.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* disable clock to CRC */
+    CLOCK_DisableClock(kCLOCK_Crc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief resets CRC peripheral module.
+ *
+ * @param base   CRC peripheral address.
+ */
+void CRC_Reset(CRC_Type *base);
+
+/*!
+ * @brief Loads default values to CRC protocol configuration structure.
+ *
+ * Loads default values to CRC protocol configuration structure. The default values are:
+ * @code
+ *   config->polynomial = kCRC_Polynomial_CRC_CCITT;
+ *   config->reverseIn = false;
+ *   config->complementIn = false;
+ *   config->reverseOut = false;
+ *   config->complementOut = false;
+ *   config->seed = 0xFFFFU;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
+ *
+ * The values, including seed, can be used to resume CRC calculation later.
+
+ * @param base   CRC peripheral address.
+ * @param config CRC protocol configuration structure
+ */
+void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
+
+/*!
+ * @brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to CRC data register.
+ *
+ * @param base     CRC peripheral address.
+ * @param data     Input data stream, MSByte in data[0].
+ * @param dataSize Size of the input data buffer in bytes.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Reads 32-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 32-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->SUM;
+}
+
+/*!
+ * @brief Reads 16-bit checksum from the CRC module.
+ *
+ * Reads CRC data register.
+ *
+ * @param base CRC peripheral address.
+ * @return final 16-bit checksum, after configured bit reverse and complement operations.
+ */
+static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
+{
+    return (uint16_t)base->SUM;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_ctimer.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The Timer instance
+ */
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to Timer bases for each instance. */
+static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to Timer clocks for each instance. */
+static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to Timer resets for each instance. */
+static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
+
+/*! @brief Pointers real ISRs installed by drivers for each instance. */
+static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
+
+/*! @brief Callback type installed by drivers for each instance. */
+static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
+
+/*! @brief Array to map timer instance to IRQ number. */
+static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
+{
+    uint32_t instance;
+    uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ctimerArrayCount; instance++)
+    {
+        if (s_ctimerBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ctimerArrayCount);
+
+    return instance;
+}
+
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the timer clock*/
+    CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
+
+    /* Setup the cimer mode and count select */
+    base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
+
+    /* Setup the timer prescale value */
+    base->PR = CTIMER_PR_PRVAL(config->prescale);
+}
+
+void CTIMER_Deinit(CTIMER_Type *base)
+{
+    uint32_t index = CTIMER_GetInstance(base);
+    /* Stop the timer */
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the timer clock*/
+    CLOCK_DisableClock(s_ctimerClocks[index]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Disable IRQ at NVIC Level */
+    DisableIRQ(s_ctimerIRQ[index]);
+}
+
+void CTIMER_GetDefaultConfig(ctimer_config_t *config)
+{
+    assert(config);
+
+    /* Run as a timer */
+    config->mode = kCTIMER_TimerMode;
+    /* This field is ignored when mode is timer */
+    config->input = kCTIMER_Capture_0;
+    /* Timer counter is incremented on every APB bus clock */
+    config->prescale = 0;
+}
+
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt)
+{
+    assert(pwmFreq_Hz > 0);
+
+    uint32_t reg;
+    uint32_t period, pulsePeriod = 0;
+    uint32_t timerClock = srcClock_Hz / (base->PR + 1);
+    uint32_t index = CTIMER_GetInstance(base);
+
+    if (matchChannel == kCTIMER_Match_3)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Enable PWM mode on the channel */
+    base->PWMC |= (1U << matchChannel);
+
+    /* Clear the stop, reset and interrupt bits for this channel */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+
+    /* If call back function is valid then enable match interrupt for the channel */
+    if (enableInt)
+    {
+        reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    }
+
+    /* Reset the counter when match on channel 3 */
+    reg |= CTIMER_MCR_MR3R_MASK;
+
+    base->MCR = reg;
+
+    /* Calculate PWM period match value */
+    period = (timerClock / pwmFreq_Hz) - 1;
+
+    /* Calculate pulse width match value */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Match on channel 3 will define the PWM period */
+    base->MR[kCTIMER_Match_3] = period;
+
+    /* This will define the PWM pulse period */
+    base->MR[matchChannel] = pulsePeriod;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If call back function is valid then enable interrupt and update the call back function */
+    if (enableInt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+
+    return kStatus_Success;
+}
+
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
+{
+    uint32_t pulsePeriod = 0, period;
+
+    /* Match channel 3 defines the PWM period */
+    period = base->MR[kCTIMER_Match_3];
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * dutyCyclePercent) / 100;
+
+    /* For 0% dutycyle, make pulse period greater than period so the event will never occur */
+    if (dutyCyclePercent == 0)
+    {
+        pulsePeriod = period + 1;
+    }
+    else
+    {
+        pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
+    }
+
+    /* Update dutycycle */
+    base->MR[matchChannel] = pulsePeriod;
+}
+
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
+{
+    uint32_t reg;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the counter operation when a match on this channel occurs */
+    reg = base->MCR;
+    reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
+    reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
+    base->MCR = reg;
+
+    reg = base->EMR;
+    /* Set the match output operation when a match on this channel occurs */
+    reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
+    reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
+
+    /* Set the initial state of the EM bit/output */
+    reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
+    reg |= (uint32_t)config->outPinInitState << matchChannel;
+    base->EMR = reg;
+
+    /* Set the match value */
+    base->MR[matchChannel] = config->matchValue;
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
+    /* If interrupt is enabled then enable interrupt and update the call back function */
+    if (config->enableInterrupt)
+    {
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+}
+
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt)
+{
+    uint32_t reg = base->CCR;
+    uint32_t index = CTIMER_GetInstance(base);
+
+    /* Set the capture edge */
+    reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
+    reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
+    /* Clear status flags */
+    CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
+    /* If call back function is valid then enable capture interrupt for the channel and update the call back function */
+    if (enableInt)
+    {
+        reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
+        EnableIRQ(s_ctimerIRQ[index]);
+    }
+    base->CCR = reg;
+}
+
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
+{
+    uint32_t index = CTIMER_GetInstance(base);
+    s_ctimerCallback[index] = cb_func;
+    ctimerCallbackType[index] = cb_type;
+}
+
+void CTIMER_GenericIRQHandler(uint32_t index)
+{
+    uint32_t int_stat, i, mask;
+    /* Get Interrupt status flags */
+    int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
+    /* Clear the status flags that were set */
+    CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
+    if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
+    {
+        if (s_ctimerCallback[index][0])
+        {
+            s_ctimerCallback[index][0](int_stat);
+        }
+    }
+    else
+    {
+        for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
+        {
+            mask = 0x01 << i;
+            /* For each status flag bit that was set call the callback function if it is valid */
+            if ((int_stat & mask) && (s_ctimerCallback[index][i]))
+            {
+                s_ctimerCallback[index][i](int_stat);
+            }
+        }
+    }
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(CTIMER0)
+void CTIMER0_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(0);
+}
+#endif
+
+#if defined(CTIMER1)
+void CTIMER1_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(1);
+}
+#endif
+
+#if defined(CTIMER2)
+void CTIMER2_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(2);
+}
+#endif
+
+#if defined(CTIMER3)
+void CTIMER3_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(3);
+}
+#endif
+
+#if defined(CTIMER4)
+void CTIMER4_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(4);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_CTIMER_H_
+#define _FSL_CTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup ctimer
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of Timer capture channels */
+typedef enum _ctimer_capture_channel
+{
+    kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
+    kCTIMER_Capture_1,      /*!< Timer capture channel 1 */
+    kCTIMER_Capture_2,      /*!< Timer capture channel 2 */
+    kCTIMER_Capture_3       /*!< Timer capture channel 3 */
+} ctimer_capture_channel_t;
+
+/*! @brief List of capture edge options */
+typedef enum _ctimer_capture_edge
+{
+    kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
+    kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
+    kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
+} ctimer_capture_edge_t;
+
+/*! @brief List of Timer match registers */
+typedef enum _ctimer_match
+{
+    kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
+    kCTIMER_Match_1,      /*!< Timer match register 1 */
+    kCTIMER_Match_2,      /*!< Timer match register 2 */
+    kCTIMER_Match_3       /*!< Timer match register 3 */
+} ctimer_match_t;
+
+/*! @brief List of output control options */
+typedef enum _ctimer_match_output_control
+{
+    kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
+    kCTIMER_Output_Clear,         /*!< Clear the EM bit/output to 0 */
+    kCTIMER_Output_Set,           /*!< Set the EM bit/output to 1 */
+    kCTIMER_Output_Toggle         /*!< Toggle the EM bit/output */
+} ctimer_match_output_control_t;
+
+/*! @brief List of Timer modes */
+typedef enum _ctimer_timer_mode
+{
+    kCTIMER_TimerMode = 0U,     /* TC is incremented every rising APB bus clock edge */
+    kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
+    kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
+    kCTIMER_IncreaseOnBothEdge  /* TC is incremented on both edges of input signal */
+} ctimer_timer_mode_t;
+
+/*! @brief List of Timer interrupts */
+typedef enum _ctimer_interrupt_enable
+{
+    kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK,    /*!< Match 0 interrupt */
+    kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK,    /*!< Match 1 interrupt */
+    kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK,    /*!< Match 2 interrupt */
+    kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK,    /*!< Match 3 interrupt */
+    kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
+    kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
+    kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
+    kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
+} ctimer_interrupt_enable_t;
+
+/*! @brief List of Timer flags */
+typedef enum _ctimer_status_flags
+{
+    kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK,   /*!< Match 0 interrupt flag */
+    kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK,   /*!< Match 1 interrupt flag */
+    kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK,   /*!< Match 2 interrupt flag */
+    kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK,   /*!< Match 3 interrupt flag */
+    kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
+    kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
+    kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
+    kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
+} ctimer_status_flags_t;
+
+typedef void (*ctimer_callback_t)(uint32_t flags);
+
+/*! @brief Callback type when registering for a callback. When registering a callback
+ *         an array of function pointers is passed the size could be 1 or 8, the callback
+ *         type will tell that.
+ */
+typedef enum
+{
+    kCTIMER_SingleCallback,  /*!< Single Callback type where there is only one callback for the timer. 
+                                 based on the status flags different channels needs to be handled differently */
+    kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. 
+                                 for both match/capture */
+} ctimer_callback_type_t;
+
+/*!
+ * @brief Match configuration
+ *
+ * This structure holds the configuration settings for each match register.
+ */
+typedef struct _ctimer_match_config
+{
+    uint32_t matchValue;                      /*!< This is stored in the match register */
+    bool enableCounterReset;                  /*!< true: Match will reset the counter
+                                                   false: Match will not reser the counter */
+    bool enableCounterStop;                   /*!< true: Match will stop the counter
+                                                   false: Match will not stop the counter */
+    ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
+    bool outPinInitState;                     /*!< Initial value of the EM bit/output */
+    bool enableInterrupt;                     /*!< true: Generate interrupt upon match
+                                                   false: Do not generate interrupt on match */
+
+} ctimer_match_config_t;
+
+/*!
+ * @brief Timer configuration structure
+ *
+ * This structure holds the configuration settings for the Timer peripheral. To initialize this
+ * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _ctimer_config
+{
+    ctimer_timer_mode_t mode;       /*!< Timer mode */
+    ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
+                                        modes that rely on this input signal to increment TC */
+    uint32_t prescale;              /*!< Prescale value */
+} ctimer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application before using the driver.
+ *
+ * @param base   Ctimer peripheral base address
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
+
+/*!
+ * @brief Gates the timer clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+void CTIMER_Deinit(CTIMER_Type *base);
+
+/*!
+ * @brief  Fills in the timers configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ *   config->mode = kCTIMER_TimerMode;
+ *   config->input = kCTIMER_Capture_0;
+ *   config->prescale = 0;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void CTIMER_GetDefaultConfig(ctimer_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name PWM setup operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Enables PWM mode on the match channel passed in and will then setup the match value
+ * and other match parameters to generate a PWM signal.
+ * This function will assign match channel 3 to set the PWM cycle.
+ *
+ * @note When setting PWM output from multiple output pins, all should use the same PWM
+ * frequency
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
+ * @param pwmFreq_Hz       PWM signal frequency in Hz
+ * @param srcClock_Hz      Timer counter clock in Hz
+ * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
+ *                         if it is 0 then no interrupt is generated
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ */
+status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         ctimer_match_t matchChannel,
+                         uint8_t dutyCyclePercent,
+                         uint32_t pwmFreq_Hz,
+                         uint32_t srcClock_Hz,
+                         bool enableInt);
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base             Ctimer peripheral base address
+ * @param matchChannel     Match pin to be used to output the PWM signal
+ * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
+ */
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
+
+/*! @}*/
+
+/*!
+ * @brief Setup the match register.
+ *
+ * User configuration is used to setup the match value and action to be taken when a match occurs.
+ *
+ * @param base         Ctimer peripheral base address
+ * @param matchChannel Match register to configure
+ * @param config       Pointer to the match configuration structure
+ */
+void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
+
+/*!
+ * @brief Setup the capture.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param capture   Capture channel to configure
+ * @param edge      Edge on the channel that will trigger a capture
+ * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
+ *                  is called upon capture
+ */
+void CTIMER_SetupCapture(CTIMER_Type *base,
+                         ctimer_capture_channel_t capture,
+                         ctimer_capture_edge_t edge,
+                         bool enableInt);
+
+/*!
+ * @brief Register callback.
+ *
+ * @param base      Ctimer peripheral base address
+ * @param cb_func   callback function
+ * @param cb_type   callback function type, singular or multiple
+ */
+void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Enable match interrupts */
+    base->MCR |= mask;
+
+    /* Enable capture interrupts */
+    base->CCR |= mask;
+}
+
+/*!
+ * @brief Disables the selected Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::ctimer_interrupt_enable_t
+ */
+static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
+{
+    /* Disable match interrupts */
+    base->MCR &= ~mask;
+
+    /* Disable capture interrupts */
+    base->CCR &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled Timer interrupts.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::ctimer_interrupt_enable_t
+ */
+static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
+{
+    uint32_t enabledIntrs = 0;
+
+    /* Get all the match interrupts enabled */
+    enabledIntrs =
+        base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT);
+
+    /* Get all the capture interrupts enabled */
+    enabledIntrs |=
+        base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT);
+
+    return enabledIntrs;
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::ctimer_status_flags_t
+ */
+static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
+{
+    return base->IR;
+}
+
+/*!
+ * @brief Clears the Timer status flags.
+ *
+ * @param base Ctimer peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::ctimer_status_flags_t
+ */
+static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
+{
+    base->IR = mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Counter Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StartTimer(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CEN_MASK;
+}
+
+/*!
+ * @brief Stops the Timer counter.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_StopTimer(CTIMER_Type *base)
+{
+    base->TCR &= ~CTIMER_TCR_CEN_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Reset the counter.
+ *
+ * The timer counter and prescale counter are reset on the next positive edge of the APB clock.
+ *
+ * @param base Ctimer peripheral base address
+ */
+static inline void CTIMER_Reset(CTIMER_Type *base)
+{
+    base->TCR |= CTIMER_TCR_CRST_MASK;
+    base->TCR &= ~CTIMER_TCR_CRST_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CTIMER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get instance number for DMA.
+ *
+ * @param base DMA peripheral base address.
+ */
+static int32_t DMA_GetInstance(DMA_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map DMA instance number to base pointer. */
+static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
+
+/*! @brief Array to map DMA instance number to IRQ number. */
+static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
+
+/*! @brief Pointers to transfer handle for each DMA channel. */
+static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS];
+
+/*! @brief Static table of descriptors */
+#if defined(__ICCARM__)
+#pragma data_alignment = 512
+dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static int32_t DMA_GetInstance(DMA_Type *base)
+{
+    int32_t instance;
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
+    {
+        if (s_dmaBases[instance] == base)
+        {
+            break;
+        }
+    }
+    assert(instance < ARRAY_SIZE(s_dmaBases));
+    return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1;
+}
+
+void DMA_Init(DMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable dma clock gate */
+    CLOCK_EnableClock(kCLOCK_Dma);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    /* set descriptor table */
+    base->SRAMBASE = (uint32_t)s_dma_descriptor_table;
+    /* enable dma peripheral */
+    base->CTRL |= DMA_CTRL_ENABLE_MASK;
+}
+
+void DMA_Deinit(DMA_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable DMA peripheral */
+    base->CTRL &= ~(DMA_CTRL_ENABLE_MASK);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
+{
+    assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger));
+
+    uint32_t tmp = (
+        DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
+        DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
+        DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK
+    );
+    tmp = base->CHANNEL[channel].CFG & (~tmp);
+    tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
+    base->CHANNEL[channel].CFG = tmp;
+}
+
+/*!
+ * @brief Gets the remaining bytes of the current DMA descriptor transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The number of bytes which have not been transferred yet.
+ */
+uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+
+    /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes 
+     * impossible to distinguish between:
+     * - transfer finishes (represented by value '0x3FF')
+     * - and remaining 1024 bytes to transfer (value 0x3FF)
+     * for all descriptor in chain, except the last one.
+     * If you decide to use this function, please use 1023 transfers as maximal value */
+
+    /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
+    if (
+        (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && 
+        (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))
+    )
+    {
+        return 0;
+    }
+
+    return base->CHANNEL[channel].XFERCFG + 1;
+}
+
+static void DMA_SetupDescriptor(
+    dma_descriptor_t    *desc,
+    uint32_t            xfercfg,
+    void                *srcEndAddr,
+    void                *dstEndAddr,
+    void                *nextDesc
+)
+{
+    desc->xfercfg = xfercfg;
+    desc->srcEndAddr = srcEndAddr;
+    desc->dstEndAddr = dstEndAddr;
+    desc->linkToNextDesc = nextDesc;
+}
+
+/* Verify and convert dma_xfercfg_t to XFERCFG register */
+static void DMA_SetupXferCFG(
+    dma_xfercfg_t *xfercfg,
+    uint32_t *xfercfg_addr
+)
+{
+    assert(xfercfg != NULL);
+    /* check source increment */
+    assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4));
+    /* check destination increment */
+    assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4));
+    /* check data width */
+    assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4));
+    /* check transfer count */
+    assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
+
+    uint32_t xfer = 0, tmp;
+    /* set valid flag - descriptor is ready now */
+    xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0);
+    /* set reload - allow link to next descriptor */
+    xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0);
+    /* set swtrig flag - start transfer */
+    xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0);
+    /* set transfer count */
+    xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0);
+    /* set INTA */
+    xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0);
+    /* set INTB */
+    xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0);
+    /* set data width */
+    tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1;
+    xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp);
+    /* set source increment value */
+    tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc;
+    xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp);
+    /* set destination increment value */
+    tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc;
+    xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp);
+    /* set transfer count */
+    xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
+
+    /* store xferCFG */
+    *xfercfg_addr = xfer;
+}
+
+void DMA_CreateDescriptor(
+    dma_descriptor_t    *desc,
+    dma_xfercfg_t       *xfercfg,
+    void                *srcAddr,
+    void                *dstAddr,
+    void                *nextDesc
+)
+{
+    uint32_t xfercfg_reg = 0;
+
+    assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg));
+    assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
+    assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
+    assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16));
+
+    /* Setup channel configuration */
+    DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
+
+    /* Set descriptor structure */
+    DMA_SetupDescriptor(desc, xfercfg_reg,
+        (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
+        (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
+        nextDesc
+    );
+}
+
+void DMA_AbortTransfer(dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    DMA_DisableChannel(handle->base, handle->channel);
+    while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel)))
+    { }
+    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel);
+    DMA_EnableChannel(handle->base, handle->channel);
+}
+
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
+{
+    int32_t dmaInstance;
+    assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS));
+
+    /* base address is invalid DMA instance */
+    dmaInstance = DMA_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    handle->base = base;
+    handle->channel = channel;
+    s_DMAHandle[channel] = handle;
+    /* Enable NVIC interrupt */
+    EnableIRQ(s_dmaIRQNumber[dmaInstance]);
+}
+
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
+{
+    assert(handle != NULL);
+
+    handle->callback = callback;
+    handle->userData = userData;
+}
+
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                          void *srcAddr,
+                          void *dstAddr,
+                          uint32_t byteWidth,
+                          uint32_t transferBytes,
+                          dma_transfer_type_t type,
+                          void *nextDesc)
+{
+    uint32_t xfer_count;
+    assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
+    assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
+
+    /* check max */
+    xfer_count = transferBytes / byteWidth;
+    assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
+
+    memset(config, 0, sizeof(*config));
+    switch (type)
+    {
+    case kDMA_MemoryToMemory:
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph = false;
+        break;
+    case kDMA_PeripheralToMemory:
+        /* Peripheral register - source doesn't increment */
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 1;
+        config->isPeriph = true;
+        break;
+    case kDMA_MemoryToPeripheral:
+        /* Peripheral register - destination doesn't increment */
+        config->xfercfg.srcInc = 1;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph = true;
+        break;
+    case kDMA_StaticToStatic:
+        config->xfercfg.srcInc = 0;
+        config->xfercfg.dstInc = 0;
+        config->isPeriph = true;
+        break;
+    default:
+        return;
+    }
+
+    config->dstAddr = (uint8_t*)dstAddr;
+    config->srcAddr = (uint8_t*)srcAddr;
+    config->nextDesc = (uint8_t*)nextDesc;
+    config->xfercfg.transferCount = xfer_count;
+    config->xfercfg.byteWidth = byteWidth;
+    config->xfercfg.intA = true;
+    config->xfercfg.reload = nextDesc != NULL;
+    config->xfercfg.valid = true;
+}
+
+status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
+{
+    assert((NULL != handle) && (NULL != config));
+
+    /* Previous transfer has not finished */
+    if (DMA_ChannelIsActive(handle->base, handle->channel))
+    {
+         return kStatus_DMA_Busy;
+    }
+
+    /* enable/disable peripheral request */
+    if (config->isPeriph)
+    {
+        DMA_EnableChannelPeriphRq(handle->base, handle->channel);
+    }
+    else
+    {
+        DMA_DisableChannelPeriphRq(handle->base, handle->channel);
+    }
+
+    DMA_CreateDescriptor(
+        &s_dma_descriptor_table[ handle->channel ], &config->xfercfg,
+        config->srcAddr, config->dstAddr, config->nextDesc
+    );
+
+    return kStatus_Success;
+}
+
+void DMA_StartTransfer(dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Enable channel interrupt */
+    handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel);
+
+    /* If HW trigger is enabled - disable SW trigger */
+    if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+    {
+        s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
+    }
+    /* Otherwise enable SW trigger */
+    else
+    {
+        s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
+    }
+
+    /* Set channel XFERCFG register according first channel descriptor. */
+    handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg;
+    /* At this moment, the channel ACTIVE bit is set and application cannot modify 
+     * or start another transfer using this channel. Channel ACTIVE bit is cleared by 
+    * 'AbortTransfer' function or when the transfer finishes */
+}
+
+void DMA0_DriverIRQHandler(void)
+{
+    dma_handle_t *handle;
+    int32_t channel_group;
+    int32_t channel_index;
+
+    /* Find channels that have completed transfer */
+    for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++)
+    {
+        handle = s_DMAHandle[i];
+        /* Handle is not present */
+        if (NULL == handle)
+        {
+            continue;
+        }
+        channel_group = DMA_CHANNEL_GROUP(handle->channel);
+        channel_index = DMA_CHANNEL_INDEX(handle->channel);
+        /* Channel uses INTA flag */
+        if (handle->base->COMMON[channel_group].INTA & (1U << channel_index))
+        {
+            /* Clear INTA flag */
+            handle->base->COMMON[channel_group].INTA = 1U << channel_index;
+            if (handle->callback)
+            {
+                (handle->callback)(handle, handle->userData, true, kDMA_IntA);
+            }
+        }
+        /* Channel uses INTB flag */
+        if (handle->base->COMMON[channel_group].INTB & (1U << channel_index))
+        {
+            /* Clear INTB flag */
+            handle->base->COMMON[channel_group].INTB = 1U << channel_index;
+            if (handle->callback)
+            {
+                (handle->callback)(handle, handle->userData, true, kDMA_IntB);
+            }
+        }
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,476 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_DMA_H_
+#define _FSL_DMA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dma
+ * @{
+ */
+
+/*! @file */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief DMA driver version */
+#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+#define DMA_MAX_TRANSFER_COUNT 0x400
+
+/* Channel group consists of 32 channels. channel_group = (channel / 32) */
+#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U)
+/* Channel index in channel group. channel_index = (channel % 32) */
+#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
+
+
+/*! @brief DMA descriptor structure */
+typedef struct _dma_descriptor {
+    uint32_t xfercfg;       /*!< Transfer configuration */
+    void *srcEndAddr;       /*!< Last source address of DMA transfer */
+    void *dstEndAddr;       /*!< Last destination address of DMA transfer */
+    void *linkToNextDesc;   /*!< Address of next DMA descriptor in chain */
+} dma_descriptor_t;
+
+/*! @brief DMA transfer configuration */
+typedef struct _dma_xfercfg {
+    bool valid;             /*!< Descriptor is ready to transfer */
+    bool reload;            /*!< Reload channel configuration register after
+                                 current descriptor is exhausted */
+    bool swtrig;            /*!< Perform software trigger. Transfer if fired
+                                 when 'valid' is set */
+    bool clrtrig;           /*!< Clear trigger */
+    bool intA;              /*!< Raises IRQ when transfer is done and set IRQA status register flag */
+    bool intB;              /*!< Raises IRQ when transfer is done and set IRQB status register flag */
+    uint8_t byteWidth;      /*!< Byte width of data to transfer */
+    uint8_t srcInc;         /*!< Increment source address by 'srcInc' x 'byteWidth' */
+    uint8_t dstInc;         /*!< Increment destination address by 'dstInc' x 'byteWidth' */
+    uint16_t transferCount; /*!< Number of transfers */
+} dma_xfercfg_t;
+
+/*! @brief DMA channel priority */
+typedef enum _dma_priority {
+    kDMA_ChannelPriority0 = 0,  /*!< Highest channel priority - priority 0 */
+    kDMA_ChannelPriority1,      /*!< Channel priority 1 */
+    kDMA_ChannelPriority2,      /*!< Channel priority 2 */
+    kDMA_ChannelPriority3,      /*!< Channel priority 3 */
+    kDMA_ChannelPriority4,      /*!< Channel priority 4 */
+    kDMA_ChannelPriority5,      /*!< Channel priority 5 */
+    kDMA_ChannelPriority6,      /*!< Channel priority 6 */
+    kDMA_ChannelPriority7,      /*!< Lowest channel priority - priority 7 */
+} dma_priority_t;
+
+/*! @brief DMA interrupt flags */
+typedef enum _dma_int {
+    kDMA_IntA,  /*!< DMA interrupt flag A */
+    kDMA_IntB,  /*!< DMA interrupt flag B */
+} dma_irq_t;
+
+/*! @brief DMA trigger type*/
+typedef enum _dma_trigger_type {
+    kDMA_NoTrigger = 0, /*!< Trigger is disabled */
+    kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
+    kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
+    kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
+    kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
+} dma_trigger_type_t;
+
+/*! @brief DMA trigger burst */
+typedef enum _dma_trigger_burst {
+    kDMA_SingleTransfer = 0,                                                    /*!< Single transfer */
+    kDMA_LevelBurstTransfer  = DMA_CHANNEL_CFG_TRIGBURST(1),                            /*!< Burst transfer driven by level trigger */
+    kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1),                             /*!< Perform 1 transfer by edge trigger */
+    kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1),     /*!< Perform 2 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2),     /*!< Perform 4 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3),     /*!< Perform 8 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4),    /*!< Perform 16 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5),    /*!< Perform 32 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6),    /*!< Perform 64 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7),   /*!< Perform 128 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8),   /*!< Perform 256 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9),   /*!< Perform 512 transfers by edge trigger */
+    kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
+} dma_trigger_burst_t;  
+
+/*! @brief DMA burst wrapping */
+typedef enum _dma_burst_wrap {
+    kDMA_NoWrap = 0,                                                            /*!< Wrapping is disabled */
+    kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1),                                     /*!< Wrapping is enabled for source */
+    kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1),                                     /*!< Wrapping is enabled for destination */
+    kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1),     /*!< Wrapping is enabled for source and destination */
+} dma_burst_wrap_t;
+
+/*! @brief DMA transfer type */
+typedef enum _dma_transfer_type
+{
+    kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
+    kDMA_PeripheralToMemory,    /*!< Transfer from peripheral to memory (increment only destination) */
+    kDMA_MemoryToPeripheral,    /*!< Transfer from memory to peripheral (increment only source)*/
+    kDMA_StaticToStatic,        /*!< Peripheral to static memory (do not increment source or destination) */
+} dma_transfer_type_t;
+
+/*! @brief DMA channel trigger */
+typedef struct _dma_channel_trigger {
+    dma_trigger_type_t type;
+    dma_trigger_burst_t burst;
+    dma_burst_wrap_t wrap;
+} dma_channel_trigger_t;
+
+/*! @brief DMA transfer status */
+enum _dma_transfer_status
+{
+    kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0),      /*!< Channel is busy and can't handle the
+                                                                     transfer request. */
+};
+
+/*! @brief DMA transfer configuration */
+typedef struct _dma_transfer_config
+{
+    uint8_t             *srcAddr;       /*!< Source data address */
+    uint8_t             *dstAddr;       /*!< Destination data address */
+    uint8_t             *nextDesc;      /*!< Chain custom descriptor */
+    dma_xfercfg_t       xfercfg;        /*!< Transfer options */
+    bool                isPeriph;       /*!< DMA transfer is driven by peripheral */
+} dma_transfer_config_t;
+
+/*! @brief Callback for DMA */
+struct _dma_handle;
+
+/*! @brief Define Callback function for DMA. */
+typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*! @brief DMA transfer handle structure */
+typedef struct _dma_handle
+{
+    dma_callback callback;  /*!< Callback function. Invoked when transfer 
+                                of descriptor with interrupt flag finishes */
+    void *userData;         /*!< Callback function parameter */
+    DMA_Type *base;         /*!< DMA peripheral base address */
+    uint8_t channel;        /*!< DMA channel number */
+} dma_handle_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMA initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes DMA peripheral.
+ *
+ * This function enable the DMA clock, set descriptor table and
+ * enable DMA peripheral.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Init(DMA_Type *base);
+
+/*!
+ * @brief Deinitializes DMA peripheral.
+ *
+ * This function gates the DMA clock.
+ *
+ * @param base DMA peripheral base address.
+ */
+void DMA_Deinit(DMA_Type *base);
+
+/* @} */
+/*!
+ * @name DMA Channel Operation
+ * @{
+ */
+
+ /*!
+ * @brief Return whether DMA channel is processing transfer
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return True for active state, false otherwise.
+ */
+static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
+}
+
+/*!
+ * @brief Enables the interrupt source for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Disables the interrupt source for the DMA transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Enable DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Disable DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel);
+}
+
+/*!
+ * @brief Set PERIPHREQEN of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
+}
+
+/*!
+ * @brief Get PERIPHREQEN value of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return True for enabled PeriphRq, false for disabled.
+ */
+static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
+}
+
+/*!
+ * @brief Set trigger settings of DMA channel.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param trigger trigger configuration.
+ */
+void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
+
+/*!
+ * @brief Gets the remaining bytes of the current DMA descriptor transfer.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return The number of bytes which have not been transferred yet.
+ */
+uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Set priority of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @param priority Channel priority value.
+ */
+static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
+}
+
+/*!
+ * @brief Get priority of channel configuration register.
+ *
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ * @return Channel priority value.
+ */
+static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
+{
+    assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
+    return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
+}
+
+/*!
+ * @brief Create application specific DMA descriptor 
+ *        to be used in a chain in transfer
+ *
+ * @param desc DMA descriptor address.
+ * @param xfercfg Transfer configuration for DMA descriptor.
+ * @param srcAddr Address of last item to transmit
+ * @param dstAddr Address of last item to receive.
+ * @param nextDesc Address of next descriptor in chain.
+ */
+void DMA_CreateDescriptor(
+    dma_descriptor_t    *desc,
+    dma_xfercfg_t       *xfercfg,
+    void                *srcAddr,
+    void                *dstAddr,
+    void                *nextDesc
+);
+
+/* @} */
+
+/*!
+ * @name DMA Transactional Operation
+ * @{
+ */
+
+/*!
+ * @brief Abort running transfer by handle.
+ *
+ * This function aborts DMA transfer specified by handle.
+ *
+ * @param handle DMA handle pointer. 
+ */
+void DMA_AbortTransfer(dma_handle_t *handle);
+
+/*!
+ * @brief Creates the DMA handle.
+ *
+ * This function is called if using transaction API for DMA. This function
+ * initializes the internal state of DMA handle.
+ *
+ * @param handle DMA handle pointer. The DMA handle stores callback function and
+ *               parameters.
+ * @param base DMA peripheral base address.
+ * @param channel DMA channel number.
+ */
+void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
+
+/*!
+ * @brief Installs a callback function for the DMA transfer.
+ *
+ * This callback is called in DMA IRQ handler. Use the callback to do something after
+ * the current major loop transfer completes.
+ *
+ * @param handle DMA handle pointer.
+ * @param callback DMA callback function pointer.
+ * @param userData Parameter for callback function.
+ */
+void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
+
+/*!
+ * @brief Prepares the DMA transfer structure.
+ *
+ * This function prepares the transfer configuration structure according to the user input.
+ *
+ * @param config The user configuration structure of type dma_transfer_t.
+ * @param srcAddr DMA transfer source address.
+ * @param dstAddr DMA transfer destination address.
+ * @param byteWidth DMA transfer destination address width(bytes).
+ * @param transferBytes DMA transfer bytes to be transferred.
+ * @param type DMA transfer type.
+ * @param nextDesc Chain custom descriptor to transfer.
+ * @note The data address and the data width must be consistent. For example, if the SRC
+ *       is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
+ *       source address error(SAE).
+ */
+void DMA_PrepareTransfer(dma_transfer_config_t *config,
+                          void *srcAddr,
+                          void *dstAddr,
+                          uint32_t byteWidth,
+                          uint32_t transferBytes,
+                          dma_transfer_type_t type,
+                          void *nextDesc);
+
+/*!
+ * @brief Submits the DMA transfer request.
+ *
+ * This function submits the DMA transfer request according to the transfer configuration structure.
+ * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
+ * a TCD and enables scatter/gather feature to process it in the next time.
+ *
+ * @param handle DMA handle pointer.
+ * @param config Pointer to DMA transfer configuration structure.
+ * @retval kStatus_DMA_Success It means submit transfer request succeed.
+ * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
+ * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
+ */
+status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
+
+/*!
+ * @brief DMA start transfer.
+ *
+ * This function enables the channel request. User can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * @param handle DMA handle pointer.
+ */
+void DMA_StartTransfer(dma_handle_t *handle);
+
+/*!
+ * @brief DMA IRQ handler for descriptor transfer complete.
+ *
+ * This function clears the channel major interrupt flag and call
+ * the callback function if it is not NULL.
+ */
+void DMA_HandleIRQ(void);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+#endif /*_FSL_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dmic.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of DMIC peripheral base address. */
+static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS;
+
+/* Array of DMIC clock name. */
+static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS;
+
+/* Array of DMIC IRQ number. */
+static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS;
+
+/*! @brief Callback function array for DMIC(s). */
+static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT];
+
+/* Array of HWVAD IRQ number. */
+static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS;
+
+/*! @brief Callback function array for HWVAD(s). */
+static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+uint32_t DMIC_GetInstance(DMIC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++)
+    {
+        if (s_dmicBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_dmicBases));
+
+    return instance;
+}
+
+void DMIC_Init(DMIC_Type *base)
+{
+    assert(base);
+
+    /* Enable the clock to the register interface */
+    CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]);
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn);
+
+    /* Disable DMA request*/
+    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+
+    /* Disable DMIC interrupt. */
+    base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+    base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+}
+
+void DMIC_DeInit(DMIC_Type *base)
+{
+    assert(base);
+    /* Disable the clock to the register interface */
+    CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]);
+}
+
+void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config)
+{
+    base->IOCFG = config;
+}
+
+void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode)
+{
+    if (mode == kDMIC_OperationModeInterrupt)
+    {
+        /* Enable DMIC interrupt. */
+        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
+    }
+    if (mode == kDMIC_OperationModeDma)
+    {
+        /* enable DMA request*/
+        base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+        base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
+    }
+}
+
+void DMIC_ConfigChannel(DMIC_Type *base,
+                        dmic_channel_t channel,
+                        stereo_side_t side,
+                        dmic_channel_config_t *channel_config)
+{
+    base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk;
+    base->CHANNEL[channel].OSR = channel_config->osr;
+    base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft;
+    base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef;
+    base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef;
+    base->CHANNEL[channel].PHY_CTRL =
+        DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate);
+    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) |
+                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) |
+                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit);
+}
+
+void DMIC_CfgChannelDc(DMIC_Type *base,
+                       dmic_channel_t channel,
+                       dc_removal_t dc_cut_level,
+                       uint32_t post_dc_gain_reduce,
+                       bool saturate16bit)
+{
+    base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) |
+                                     DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) |
+                                     DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit);
+}
+
+void DMIC_Use2fs(DMIC_Type *base, bool use2fs)
+{
+    base->USE2FS = (use2fs) ? 0x1 : 0x0;
+}
+
+void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask)
+{
+    base->CHANEN = channelmask;
+}
+
+void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn)
+{
+    base->CHANNEL[channel].FIFO_CTRL |=
+        (base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) |
+        DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) |
+        DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn);
+}
+
+void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
+    /* Save callback pointer */
+    s_dmicCallback[instance] = cb;
+    EnableIRQ(s_dmicIRQ[instance]);
+}
+
+void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    DisableIRQ(s_dmicIRQ[instance]);
+    s_dmicCallback[instance] = NULL;
+    NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
+}
+
+void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
+    /* Save callback pointer */
+    s_dmicHwvadCallback[instance] = vadcb;
+    EnableIRQ(s_dmicHwvadIRQ[instance]);
+}
+
+void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
+{
+    uint32_t instance;
+
+    instance = DMIC_GetInstance(base);
+    DisableIRQ(s_dmicHwvadIRQ[instance]);
+    s_dmicHwvadCallback[instance] = NULL;
+    NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(DMIC0)
+/*DMIC0 IRQ handler */
+void DMIC0_DriverIRQHandler(void)
+{
+    if (s_dmicCallback[0] != NULL)
+    {
+        s_dmicCallback[0]();
+    }
+}
+/*DMIC0 HWVAD IRQ handler */
+void HWVAD0_IRQHandler(void)
+{
+    if (s_dmicHwvadCallback[0] != NULL)
+    {
+        s_dmicHwvadCallback[0]();
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_DMIC_H_
+#define _FSL_DMIC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dmic_driver
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @name DMIC version
+ * @{
+ */
+
+/*! @brief DMIC driver version 2.0.0. */
+#define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief DMIC different operation modes. */
+typedef enum _operation_mode
+{
+    kDMIC_OperationModePoll = 0U,      /*!< Polling mode */
+    kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */
+    kDMIC_OperationModeDma = 2U,       /*!< DMA mode */
+} operation_mode_t;
+
+/*! @brief DMIC left/right values. */
+typedef enum _stereo_side
+{
+    kDMIC_Left = 0U,  /*!< Left Stereo channel */
+    kDMIC_Right = 1U, /*!< Right Stereo channel */
+} stereo_side_t;
+
+/*! @brief DMIC Clock pre-divider values. */
+typedef enum
+{
+    kDMIC_PdmDiv1 = 0U,    /*!< DMIC pre-divider set in divide by 1 */
+    kDMIC_PdmDiv2 = 1U,    /*!< DMIC pre-divider set in divide by 2 */
+    kDMIC_PdmDiv3 = 2U,    /*!< DMIC pre-divider set in divide by 3 */
+    kDMIC_PdmDiv4 = 3U,    /*!< DMIC pre-divider set in divide by 4 */
+    kDMIC_PdmDiv6 = 4U,    /*!< DMIC pre-divider set in divide by 6 */
+    kDMIC_PdmDiv8 = 5U,    /*!< DMIC pre-divider set in divide by 8 */
+    kDMIC_PdmDiv12 = 6U,   /*!< DMIC pre-divider set in divide by 12 */
+    kDMIC_PdmDiv16 = 7U,   /*!< DMIC pre-divider set in divide by 16*/
+    kDMIC_PdmDiv24 = 8U,   /*!< DMIC pre-divider set in divide by 24*/
+    kDMIC_PdmDiv32 = 9U,   /*!< DMIC pre-divider set in divide by 32 */
+    kDMIC_PdmDiv48 = 10U,  /*!< DMIC pre-divider set in divide by 48 */
+    kDMIC_PdmDiv64 = 11U,  /*!< DMIC pre-divider set in divide by 64*/
+    kDMIC_PdmDiv96 = 12U,  /*!< DMIC pre-divider set in divide by 96*/
+    kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */
+} pdm_div_t;
+
+/*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */
+typedef enum _compensation
+{
+    kDMIC_CompValueZero = 0U,            /*!< Compensation 0 */
+    kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */
+    kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */
+    kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */
+} compensation_t;
+
+/*! @brief DMIC DC filter control values. */
+typedef enum _dc_removal
+{
+    kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */
+    kDMIC_DcCut155 = 1U,   /*!< Cut off Frequency is 155 Hz  */
+    kDMIC_DcCut78 = 2U,    /*!< Cut off Frequency is 78 Hz  */
+    kDMIC_DcCut39 = 3U,    /*!< Cut off Frequency is 39 Hz  */
+} dc_removal_t;
+
+/*! @brief DMIC IO configiration. */
+typedef enum _dmic_io
+{
+    kDMIC_PdmDual = 0U,       /*!< Two separate pairs of PDM wires */
+    kDMIC_PdmStereo = 4U,     /*!< Stereo Mic */
+    kDMIC_PdmBypass = 3U,     /*!< Clk Bypass clocks both channels */
+    kDMIC_PdmBypassClk0 = 1U, /*!< Clk Bypass clocks only channel0 */
+    kDMIC_PdmBypassClk1 = 2U, /*!< Clk Bypas clocks only channel1 */
+} dmic_io_t;
+
+/*! @brief DMIC Channel number. */
+typedef enum _dmic_channel
+{
+    kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */
+    kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */
+} dmic_channel_t;
+
+/*! @brief DMIC and decimator sample rates. */
+typedef enum _dmic_phy_sample_rate
+{
+    kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */
+    kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */
+} dmic_phy_sample_rate_t;
+
+/*! @brief DMIC transfer status.*/
+enum _dmic_status
+{
+    kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0),          /*!< DMIC is busy */
+    kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1),          /*!< DMIC is idle */
+    kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2),  /*!< DMIC  over run Error */
+    kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */
+};
+
+/*! @brief DMIC Channel configuration structure. */
+typedef struct _dmic_channel_config
+{
+    pdm_div_t divhfclk;                 /*!< DMIC Clock pre-divider values */
+    uint32_t osr;                       /*!< oversampling rate(CIC decimation rate) for PCM */
+    int32_t gainshft;                   /*!< 4FS PCM data gain control */
+    compensation_t preac2coef;          /*!< Pre-emphasis Filter coefficient value for 2FS */
+    compensation_t preac4coef;          /*!< Pre-emphasis Filter coefficient value for 4FS */
+    dc_removal_t dc_cut_level;          /*!< DMIC DC filter control values. */
+    uint32_t post_dc_gain_reduce;       /*!< Fine gain adjustment in the form of a number of bits to downshift */
+    dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */
+    bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate.
+                1 means if the result overflows, it saturates at 0xFFFF for positive overflow and
+                0x8000 for negative overflow.*/
+} dmic_channel_config_t;
+
+/*! @brief DMIC Callback function. */
+typedef void (*dmic_callback_t)(void);
+
+/*! @brief HWVAD Callback function. */
+typedef void (*dmic_hwvad_callback_t)(void);
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+uint32_t DMIC_GetInstance(DMIC_Type *base);
+
+/*!
+ * @brief	Turns DMIC Clock on
+ * @param	base	: DMIC base
+ * @return	Nothing
+ */
+void DMIC_Init(DMIC_Type *base);
+
+/*!
+ * @brief	Turns DMIC Clock off
+ * @param	base	: DMIC base
+ * @return	Nothing
+ */
+void DMIC_DeInit(DMIC_Type *base);
+
+/*!
+ * @brief	Configure DMIC io
+ * @param	base	: The base address of DMIC interface
+ * @param	config		: DMIC io configuration
+ * @return	Nothing
+ */
+void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config);
+
+/*!
+ * @brief	Set DMIC operating mode
+ * @param	base	: The base address of DMIC interface
+ * @param	mode	: DMIC mode
+ * @return	Nothing
+ */
+void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode);
+
+/*!
+ * @brief	Configure DMIC channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param side     : stereo_side_t, choice of left or right
+ * @param	channel_config	: Channel configuration
+ * @return	Nothing
+ */
+void DMIC_ConfigChannel(DMIC_Type *base,
+                        dmic_channel_t channel,
+                        stereo_side_t side,
+                        dmic_channel_config_t *channel_config);
+
+/*!
+ * @brief	Configure Clock scaling
+ * @param	base		: The base address of DMIC interface
+ * @param	use2fs		: clock scaling
+ * @return	Nothing
+ */
+void DMIC_Use2fs(DMIC_Type *base, bool use2fs);
+
+/*!
+ * @brief	Enable a particualr channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channelmask	: Channel selection
+ * @return	Nothing
+ */
+void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask);
+
+/*!
+ * @brief	Configure fifo settings for DMIC channel
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param	trig_level	: FIFO trigger level
+ * @param	enable		: FIFO level
+ * @param	resetn		: FIFO reset
+ * @return	Nothing
+ */
+void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn);
+
+/*!
+ * @brief	Get FIFO status
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @return	FIFO status
+ */
+static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel)
+{
+    return base->CHANNEL[channel].FIFO_STATUS;
+}
+
+/*!
+ * @brief	Clear FIFO status
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @param	mask		: Bits to be cleared
+ * @return	FIFO status
+ */
+static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].FIFO_STATUS = mask;
+}
+
+/*!
+ * @brief	Get FIFO data
+ * @param	base		: The base address of DMIC interface
+ * @param	channel		: DMIC channel
+ * @return	FIFO data
+ */
+static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel)
+{
+    return base->CHANNEL[channel].FIFO_DATA;
+}
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected DMIC peripheral.
+ * The callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param cb callback Pointer to store callback function.
+ * @retval None.
+ */
+void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected DMIC peripheral.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param cb callback Pointer to store callback function..
+ * @retval None.
+ */
+void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb);
+
+/**
+ * @}
+ */
+
+/*!
+ * @name hwvad
+ * @{
+ */
+
+/*!
+ * @brief Sets the gain value for the noise estimator.
+ *
+ * @param base DMIC base pointer
+ * @param value gain value for the noise estimator.
+ * @retval None.
+ */
+static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADTHGN = value & 0xFu;
+}
+
+/*!
+ * @brief Sets the gain value for the signal estimator.
+ *
+ * @param base DMIC base pointer
+ * @param value gain value for the signal estimator.
+ * @retval None.
+ */
+static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADTHGS = value & 0xFu;
+}
+
+/*!
+ * @brief Sets the hwvad filter cutoff frequency parameter.
+ *
+ * @param base DMIC base pointer
+ * @param value cut off frequency value.
+ * @retval None.
+ */
+static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADHPFS = value & 0x3u;
+}
+
+/*!
+ * @brief Sets the input gain of hwvad.
+ *
+ * @param base DMIC base pointer
+ * @param value input gain value for hwvad.
+ * @retval None.
+ */
+static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value)
+{
+    assert(NULL != base);
+    base->HWVADGAIN = value & 0xFu;
+}
+
+/*!
+ * @brief Clears hwvad internal interrupt flag.
+ *
+ * @param base DMIC base pointer
+ * @param st10 bit value.
+ * @retval None.
+ */
+static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10)
+{
+    assert(NULL != base);
+    base->HWVADST10 = (st10) ? 0x1 : 0x0;
+}
+
+/*!
+ * @brief Resets hwvad filters.
+ *
+ * @param base DMIC base pointer
+ * @param rstt Reset bit value.
+ * @retval None.
+ */
+static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt)
+{
+    assert(NULL != base);
+    base->HWVADRSTT = (rstt) ? 0x1 : 0x0;
+}
+
+/*!
+ * @brief Gets the value from output of the filter z7.
+ *
+ * @param base DMIC base pointer
+ * @retval output of filter z7.
+ */
+static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base)
+{
+    assert(NULL != base);
+    return (base->HWVADLOWZ & 0xFFFFu);
+}
+
+/*!
+ * @brief	Enable hwvad callback.
+
+ * This function enables the hwvad interrupt for the selected DMIC  peripheral.
+ * The callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param vadcb callback Pointer to store callback function.
+ * @retval None.
+ */
+void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the hwvad interrupt for the selected DMIC peripheral.
+ *
+ * @param base Base address of the DMIC peripheral.
+ * @param vadcb callback Pointer to store callback function..
+ * @retval None.
+ */
+void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_DMIC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dmic_dma.h"
+#include "fsl_dmic.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define DMIC_HANDLE_ARRAY_SIZE 1
+
+/*<! Structure definition for dmic_dma_handle_t. The structure is private. */
+typedef struct _dmic_dma_private_handle
+{
+    DMIC_Type *base;
+    dmic_dma_handle_t *handle;
+} dmic_dma_private_handle_t;
+
+/*! @brief DMIC transfer state, which is used for DMIC transactiaonl APIs' internal state. */
+enum _dmic_dma_states_t
+{
+    kDMIC_Idle = 0x0, /*!< DMIC is idle state */
+    kDMIC_Busy        /*!< DMIC is busy tranferring data. */
+};
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the DMIC instance from peripheral base address.
+ *
+ * @param base DMIC peripheral base address.
+ * @return DMIC instance.
+ */
+extern uint32_t DMIC_GetInstance(DMIC_Type *base);
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*<! Private handle only used for internally. */
+static dmic_dma_private_handle_t s_dmaPrivateHandle[DMIC_HANDLE_ARRAY_SIZE];
+
+/*******************************************************************************
+ * Code
+********************************************************************************/
+
+static void DMIC_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    dmic_dma_private_handle_t *dmicPrivateHandle = (dmic_dma_private_handle_t *)param;
+    dmicPrivateHandle->handle->state = kDMIC_Idle;
+
+    if (dmicPrivateHandle->handle->callback)
+    {
+        dmicPrivateHandle->handle->callback(dmicPrivateHandle->base, dmicPrivateHandle->handle, kStatus_DMIC_Idle,
+                                            dmicPrivateHandle->handle->userData);
+    }
+}
+
+status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
+                                      dmic_dma_handle_t *handle,
+                                      dmic_dma_transfer_callback_t callback,
+                                      void *userData,
+                                      dma_handle_t *rxDmaHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check DMIC instance by 'base'*/
+    instance = DMIC_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    /* assign 'base' and 'handle' */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->rxDmaHandle = rxDmaHandle;
+
+    /* Set DMIC state to idle */
+    handle->state = kDMIC_Idle;
+    /* Configure RX. */
+    if (rxDmaHandle)
+    {
+        DMA_SetCallback(rxDmaHandle, DMIC_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    return kStatus_Success;
+}
+
+status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
+                                 dmic_dma_handle_t *handle,
+                                 dmic_transfer_t *xfer,
+                                 uint32_t dmic_channel)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* Check if the device is busy. If previous RX not finished.*/
+    if (handle->state == kDMIC_Busy)
+    {
+        status = kStatus_DMIC_Busy;
+    }
+    else
+    {
+        handle->state = kDMIC_Busy;
+        handle->transferSize = xfer->dataSize;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t),
+                            xfer->dataSize, kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        status = kStatus_Success;
+    }
+    return status;
+}
+
+void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->rxDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+    handle->state = kDMIC_Idle;
+}
+
+status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(count);
+
+    if (kDMIC_Idle == handle->state)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->transferSize - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DMIC_DMA_H_
+#define _FSL_DMIC_DMA_H_
+
+#include "fsl_common.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup dmic_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief DMIC transfer structure. */
+typedef struct _dmic_transfer
+{
+    uint16_t *data;  /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} dmic_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _dmic_dma_handle dmic_dma_handle_t;
+
+/*! @brief DMIC transfer callback function. */
+typedef void (*dmic_dma_transfer_callback_t)(DMIC_Type *base,
+                                             dmic_dma_handle_t *handle,
+                                             status_t status,
+                                             void *userData);
+
+/*!
+* @brief DMIC DMA handle
+*/
+struct _dmic_dma_handle
+{
+    DMIC_Type *base;                       /*!< DMIC peripheral base address. */
+    dma_handle_t *rxDmaHandle;             /*!< The DMA RX channel used. */
+    dmic_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                        /*!< DMIC callback function parameter.*/
+    size_t transferSize;                   /*!< Size of the data to receive. */
+    volatile uint8_t state;                /*!< Internal state of DMIC DMA transfer */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name DMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the DMIC handle which is used in transactional functions.
+ * @param base DMIC peripheral base address.
+ * @param handle Pointer to dmic_dma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+status_t DMIC_TransferCreateHandleDMA(DMIC_Type *base,
+                                      dmic_dma_handle_t *handle,
+                                      dmic_dma_transfer_callback_t callback,
+                                      void *userData,
+                                      dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer DMIC DMA transfer structure. See #dmic_transfer_t.
+ * @param dmic_channel DMIC channel 
+ * @retval kStatus_Success
+ */
+status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
+                                 dmic_dma_handle_t *handle,
+                                 dmic_transfer_t *xfer,
+                                 uint32_t dmic_channel);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * @param base DMIC peripheral base address
+ * @param handle Pointer to dmic_dma_handle_t structure
+ */
+void DMIC_TransferAbortReceiveDMA(DMIC_Type *base, dmic_dma_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base DMIC peripheral base address.
+ * @param handle DMIC handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter count;
+ */
+status_t DMIC_TransferGetReceiveCountDMA(DMIC_Type *base, dmic_dma_handle_t *handle, uint32_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_DMIC_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_eeprom.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the EEPROM instance from peripheral base address.
+ *
+ * @param base EEPROM peripheral base address.
+ * @return EEPROM instance.
+ */
+static uint32_t EEPROM_GetInstance(EEPROM_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of EEPROM peripheral base address. */
+static EEPROM_Type *const s_eepromBases[] = EEPROM_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of EEPROM clock name. */
+static const clock_ip_name_t s_eepromClock[] = EEPROM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t EEPROM_GetInstance(EEPROM_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_eepromBases); instance++)
+    {
+        if (s_eepromBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_eepromBases));
+
+    return instance;
+}
+
+void EEPROM_GetDefaultConfig(eeprom_config_t *config)
+{
+    config->autoProgram = kEEPROM_AutoProgramWriteWord;
+    config->writeWaitPhase1 = 0x5U;
+    config->writeWaitPhase2 = 0x9U;
+    config->writeWaitPhase3 = 0x3U;
+    config->readWaitPhase1 = 0xFU;
+    config->readWaitPhase2 = 0x8U;
+    config->lockTimingParam = false;
+}
+
+void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz)
+{
+    assert(config);
+
+    uint32_t clockDiv = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_EnableClock(s_eepromClock[EEPROM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Set the clock divider */
+    clockDiv = sourceClock_Hz / FSL_FEATURE_EEPROM_INTERNAL_FREQ;
+    if ((sourceClock_Hz % FSL_FEATURE_EEPROM_INTERNAL_FREQ) > (FSL_FEATURE_EEPROM_INTERNAL_FREQ / 2U))
+    {
+        clockDiv += 1U;
+    }
+    base->CLKDIV = clockDiv - 1U;
+
+    /* Set the auto program feature */
+    EEPROM_SetAutoProgram(base, config->autoProgram);
+
+    /* Set time delay parameter */
+    base->RWSTATE =
+        EEPROM_RWSTATE_RPHASE1(config->readWaitPhase1 - 1U) | EEPROM_RWSTATE_RPHASE2(config->readWaitPhase2 - 1U);
+    base->WSTATE = EEPROM_WSTATE_PHASE1(config->writeWaitPhase1 - 1U) |
+                   EEPROM_WSTATE_PHASE2(config->writeWaitPhase2 - 1U) |
+                   EEPROM_WSTATE_PHASE3(config->writeWaitPhase3 - 1U);
+    base->WSTATE |= EEPROM_WSTATE_LCK_PARWEP(config->lockTimingParam);
+ 
+    /* Clear the remaining write operation  */
+    base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
+    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
+    {}
+}
+
+void EEPROM_Deinit(EEPROM_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_DisableClock(s_eepromClock[EEPROM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data)
+{
+    uint32_t *addr = 0;
+
+    if ((offset % 4U) || (offset > FSL_FEATURE_EEPROM_SIZE))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set auto program settings */
+    if (base->AUTOPROG != kEEPROM_AutoProgramDisable)
+    {
+        EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramWriteWord);
+    }
+
+    EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable);
+
+    /* Compute the page */
+    addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + offset);
+    *addr = data;
+
+    /* Check if need to do program erase manually */
+    if (base->AUTOPROG != kEEPROM_AutoProgramWriteWord)
+    {
+        base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
+    }
+
+    /* Waiting for operation finished */
+    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
+    {}
+
+    return kStatus_Success;
+}
+
+status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data)
+{
+    uint32_t i = 0;
+    uint32_t *addr = NULL;
+
+    if ((pageNum > FSL_FEATURE_EEPROM_PAGE_COUNT) || (!data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set auto program settings */
+    if (base->AUTOPROG != kEEPROM_AutoProgramDisable)
+    {
+        EEPROM_SetAutoProgram(base, kEEPROM_AutoProgramLastWord);
+    }
+
+    EEPROM_ClearInterruptFlag(base, kEEPROM_ProgramFinishInterruptEnable);
+
+    addr = (uint32_t *)(FSL_FEATURE_EEPROM_BASE_ADDRESS + pageNum * (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT));
+    for (i = 0; i < (FSL_FEATURE_EEPROM_SIZE/FSL_FEATURE_EEPROM_PAGE_COUNT) / 4U; i++)
+    {
+        addr[i] = data[i];
+    }
+
+    if (base->AUTOPROG == kEEPROM_AutoProgramDisable)
+    {
+        base->CMD = FSL_FEATURE_EEPROM_PROGRAM_CMD;
+    }
+
+    /* Waiting for operation finished */
+    while ((EEPROM_GetInterruptStatus(base) & kEEPROM_ProgramFinishInterruptEnable) == 0U)
+    {}
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_EEPROM_H_
+#define _FSL_EEPROM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup eeprom
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief EEPROM driver version 2.0.0. */
+#define FSL_EEPROM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief EEPROM automatic program option */
+typedef enum _eeprom_auto_program
+{
+    kEEPROM_AutoProgramDisable = 0x0,   /*!< Disable auto program */
+    kEEPROM_AutoProgramWriteWord = 0x1, /*!< Auto program triggered after 1 word is written */
+    kEEPROM_AutoProgramLastWord = 0x2   /*!< Auto program triggered after last word of a page written */
+} eeprom_auto_program_t;
+
+/*! @brief EEPROM interrupt source */
+typedef enum _eeprom_interrupt_enable
+{
+    kEEPROM_ProgramFinishInterruptEnable = EEPROM_INTENSET_PROG_SET_EN_MASK, /*!< Interrupt while program finished */
+} eeprom_interrupt_enable_t;
+
+/*!
+ * @brief EEPROM region configuration structure.
+ */
+typedef struct _eeprom_config
+{
+    eeprom_auto_program_t autoProgram; /*!< Automatic program feature. */
+    uint8_t readWaitPhase1;            /*!< EEPROM read waiting phase 1 */
+    uint8_t readWaitPhase2;            /*!< EEPROM read waiting phase 2 */
+    uint8_t writeWaitPhase1;           /*!< EEPROM write waiting phase 1 */
+    uint8_t writeWaitPhase2;           /*!< EEPROM write waiting phase 2 */
+    uint8_t writeWaitPhase3;           /*!< EEPROM write waiting phase 3 */
+    bool lockTimingParam;              /*!< If lock the read and write wait phase settings */
+} eeprom_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the EEPROM with the user configuration structure.
+ *
+ * This function configures the EEPROM module with the user-defined configuration. This function also sets the
+ * internal clock frequency to about 155kHz according to the source clock frequency.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param config   The pointer to the configuration structure.
+ * @param sourceClock_Hz EEPROM source clock frequency in Hz.
+ */
+void EEPROM_Init(EEPROM_Type *base, const eeprom_config_t *config, uint32_t sourceClock_Hz);
+
+/*!
+ * @brief Get EEPROM default configure settings.
+ *
+ * @param config  EEPROM config structure pointer.
+ */
+void EEPROM_GetDefaultConfig(eeprom_config_t *config);
+
+/*!
+ * @brief Deinitializes the EEPROM regions.
+ *
+ * @param base     EEPROM peripheral base address.
+ */
+void EEPROM_Deinit(EEPROM_Type *base);
+
+/* @}*/
+
+/*!
+ * @name Basic Control Operations
+ * @{
+ */
+
+/*!
+ * @brief Set EEPROM automatic program feature.
+ *
+ * EEPROM write always needs a program and erase cycle to write the data into EEPROM. This program and erase cycle can
+ * be finished automaticlly or manually. If users want to use or disable auto program feature, users can call this API.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param autoProgram EEPROM auto program feature need to set.
+ */
+static inline void EEPROM_SetAutoProgram(EEPROM_Type *base, eeprom_auto_program_t autoProgram)
+{
+    base->AUTOPROG = autoProgram;
+}
+
+/*!
+ * @brief Set EEPROM to in/out power down mode.
+ *
+ * This function make EEPROM eneter or out of power mode. Notice that, users shall not put EEPROM into power down mode
+ * while there is still any pending EEPROM operation. While EEPROM is wakes up from power down mode, any EEPROM
+ * operation has to be suspended for 100 us.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param enable   True means enter to power down mode, false means wake up.
+ */
+static inline void EEPROM_SetPowerDownMode(EEPROM_Type *base, bool enable)
+{
+    base->PWRDWN = enable;
+}
+
+/*!
+ * @brief Enable EEPROM interrupt.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_EnableInterrupt(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTENSET = mask;
+}
+
+/*!
+ * @brief Disable EEPROM interrupt.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_DisableInterrupt(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTENCLR = mask;
+}
+
+/*!
+ * @brief Get the status of all interrupt flags for ERPROM.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @return EEPROM interrupt flag status
+ */
+static inline uint32_t EEPROM_GetInterruptStatus(EEPROM_Type *base)
+{
+    return base->INTSTAT;
+}
+
+/*!
+ * @brief Get the status of enabled interrupt flags for ERPROM.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @return EEPROM enabled interrupt flag status
+ */
+static inline uint32_t EEPROM_GetEnabledInterruptStatus(EEPROM_Type *base)
+{
+    return base->INTEN;
+}
+
+/*!
+ * @brief Set interrupt flags manually.
+ *
+ * This API trigger a interrupt manually, users can no need to wait for hardware trigger interrupt. Call this API will
+ * set the corresponding bit in INSTAT register.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt flag need to be set. It is a logic OR of members of
+ *                 enumeration:: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_SetInterruptFlag(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTSTATSET = mask;
+}
+
+/*!
+ * @brief Clear interrupt flags manually.
+ *
+ * This API clears interrupt flags manually. Call this API will clear the corresponding bit in INSTAT register.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param mask     EEPROM interrupt flag need to be cleared. It is a logic OR of members of
+ *                 enumeration:: eeprom_interrupt_enable_t
+ */
+static inline void EEPROM_ClearInterruptFlag(EEPROM_Type *base, uint32_t mask)
+{
+    base->INTSTATCLR = mask;
+}
+
+/*!
+ * @brief Write a word data in address of EEPROM.
+ *
+ * Users can write a page or at least a word data into EEPROM address.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param offset   Offset from the begining address of EEPROM. This value shall be 4-byte aligned.
+ * @param data     Data need be write.
+ */
+status_t EEPROM_WriteWord(EEPROM_Type *base, uint32_t offset, uint32_t data);
+
+/*!
+ * @brief Write a page data into EEPROM.
+ *
+ * Users can write a page or at least a word data into EEPROM address.
+ *
+ * @param base     EEPROM peripheral base address.
+ * @param pageNum  Page number to be written.
+ * @param data     Data need be write. This array data size shall equals to the page size.
+ */
+status_t EEPROM_WritePage(EEPROM_Type *base, uint32_t pageNum, uint32_t *data);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_EEPROM_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_emc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Define macros for EMC driver. */
+#define EMC_REFRESH_CLOCK_PARAM   (16U)
+#define EMC_SDRAM_WAIT_CYCLES  (2000U)
+#define EMC_DYNCTL_COLUMNBASE_OFFSET  (0U)
+#define EMC_DYNCTL_COLUMNBASE_MASK    (0x3U)
+#define EMC_DYNCTL_COLUMNPLUS_OFFSET  (3U)
+#define EMC_DYNCTL_COLUMNPLUS_MASK    (0x18U)
+#define EMC_DYNCTL_BUSWIDTH_MASK      (0x80U)
+#define EMC_DYNCTL_BUSADDRMAP_MASK    (0x20U)
+#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU)
+#define EMC_SDRAM_BANKCS_BA0_MASK   (uint32_t)(0x2000)
+#define EMC_SDRAM_BANKCS_BA1_MASK   (uint32_t)(0x4000)
+#define EMC_SDRAM_BANKCS_BA_MASK    (EMC_SDRAM_BANKCS_BA0_MASK|EMC_SDRAM_BANKCS_BA1_MASK)
+#define EMC_DIV_ROUND_UP(n, m)   ((n + m -1)/m)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for EMC module.
+ *
+ * @param base EMC peripheral base address
+ */
+static uint32_t EMC_GetInstance(EMC_Type *base);
+
+/*!
+ * @brief Get the clock cycles of EMC clock.
+ * The function is used to calculate the multiple of the 
+ * 16 EMCCLKs between the timer_Ns period.
+ *
+ * @param base EMC peripheral base address
+ * @param timer_Ns The timer/period in unit of nanosecond
+ * @param plus The plus added to the register settings to reach the calculated cycles.
+ * @return The calculated cycles. 
+ */
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus);
+
+/*!
+ * @brief Get the shift value to shift the mode register content by.
+ *
+ * @param addrMap EMC address map for the dynamic memory configuration. 
+ *                It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG.
+ * @return The offset value to shift the mode register content by. 
+ */
+static uint32_t EMC_ModeOffset(uint32_t addrMap);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to EMC clocks for each instance. */
+static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS;
+
+/*! @brief Pointers to EMC bases for each instance. */
+static EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS;
+
+/*! @brief Define the the start address for each chip controlled by EMC. */
+static uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t EMC_GetInstance(EMC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++)
+    {
+        if (s_EMCBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_EMCBases));
+
+    return instance;
+}
+
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus)
+{
+    uint32_t cycles;
+
+    cycles = CLOCK_GetFreq(kCLOCK_EMC) / EMC_HZ_ONEMHZ * timer_Ns;
+    cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */
+
+    /* Decrese according to the plus. */
+    if (cycles >= plus)
+    {
+        cycles = cycles - plus;
+    }
+    else
+    {
+        cycles = 0;
+    }
+    
+    return cycles;
+}
+
+static uint32_t EMC_ModeOffset(uint32_t addrMap)
+{
+    uint8_t offset = 0;
+    uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK;
+
+    /* First calculate the column length. */
+    if (columbase == 0x10)
+    {
+        offset = 8;
+    }
+    else
+    {
+        if (!columbase)
+        {
+            offset = 9;          
+        }
+        else
+        {
+            offset = 8;
+        }
+        /* Add column length increase check. */
+        if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 1)
+        {
+            offset += 1;   
+        }
+        else if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 2)
+        {
+            offset += 2;
+        }
+        else
+        {
+            /* To avoid MISRA rule 14.10 error. */
+        }        
+    }
+
+    /* Add Buswidth/16. */
+    if (addrMap & EMC_DYNCTL_BUSWIDTH_MASK)
+    {
+        offset += 2;
+    }
+    else
+    {
+        offset += 1;
+    }
+
+    /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */
+    if (!(addrMap & EMC_DYNCTL_BUSADDRMAP_MASK))
+    {
+        if (!(addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK))
+        {
+          offset += 1; 
+        }
+        else
+        {
+          offset += 2;
+        }
+    }
+
+    return offset;
+}
+
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config)
+{
+    /* Enable EMC clock. */
+    CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)]));
+
+    /* Reset the EMC. */
+    SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK;
+    SYSCON->PRESETCTRL[2] &= ~ SYSCON_PRESETCTRL_EMC_RESET_MASK;
+    
+    /* Set the EMC sytem configure. */
+    SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv);
+
+    SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc);
+
+    /* Set the endian mode. */
+    base->CONFIG = config->endian;
+    /* Enable the EMC module with normal memory map mode and normal work mode. */
+    base->CONTROL = EMC_CONTROL_E_MASK;
+}
+
+void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, 
+        emc_dynamic_chip_config_t *config, uint32_t totalChips)
+{
+    assert(config);
+    assert(timing);
+    assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM);
+
+    uint32_t count;
+    uint8_t casLatency;
+    uint32_t addr;
+    uint32_t offset;
+    uint32_t data;
+    emc_dynamic_chip_config_t *dynamicConfig = config;
+
+    /* Setting for dynamic memory controller chip independent configuration. */
+    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+    {
+        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG  = EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) |
+            EMC_ADDRMAP(dynamicConfig->devAddrMap);
+        /* Abstract CAS latency from the sdram mode reigster setting values. */
+        casLatency = (dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;
+        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS  =  EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) |
+        EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency);
+        
+        dynamicConfig ++;
+    }
+
+    /* Configure the Dynamic Memory controller timing/latency for all chips. */
+    base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig);
+    base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK;
+    base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK;
+    base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK;
+    base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK;
+    base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK;
+    base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK;
+    base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK;
+    base->DYNAMICRFC = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) &EMC_DYNAMICRFC_TRFC_MASK;
+    base->DYNAMICXSR = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK;
+    base->DYNAMICRRD = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK;
+    base->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0)?timing->tMrd_Nclk - 1:0);
+
+    /* Initialize the SDRAM.*/ 
+    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES;  count ++)
+    {
+    }
+    /* Step 2. issue nop command. */
+    base->DYNAMICCONTROL  = 0x00000183;
+    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES;  count ++)
+    {
+    }
+    /* Step 3. issue precharge all command. */
+    base->DYNAMICCONTROL  = 0x00000103;
+
+    /* Step 4. issue two auto-refresh command. */
+    base->DYNAMICREFRESH = 2;
+    for (count = 0; count < EMC_SDRAM_WAIT_CYCLES/2; count ++)
+    {
+    }
+
+    base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0)/EMC_REFRESH_CLOCK_PARAM;
+
+    /* Step 5. issue a mode command and set the mode value. */
+    base->DYNAMICCONTROL  = 0x00000083;
+
+    /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */
+    dynamicConfig = config;
+    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+    {
+        /* Get the shift value first. */
+        offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+        addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | 
+            ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK ) << offset));
+        /* Set the right mode setting value. */
+        data = *(volatile uint32_t *)addr;
+        data = data;
+        dynamicConfig ++;
+    }
+
+    if (config->dynamicDevice)
+    {
+        /* Add extended mode register if the low-power sdram is used. */
+        base->DYNAMICCONTROL  = 0x00000083;
+        /* Calculate the mode settings for extended mode register. */
+        dynamicConfig = config;
+        for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+        {
+            /* Get the shift value first. */
+            offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+            addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) |
+                EMC_SDRAM_BANKCS_BA1_MASK) << offset));
+            /* Set the right mode setting value. */
+            data = *(volatile uint32_t *)addr;
+            data = data;
+            dynamicConfig ++;
+        }        
+    }
+
+    /* Step 6. issue normal operation command. */
+    base->DYNAMICCONTROL  = 0x00000000; /* Issue NORMAL command */
+
+    /* The buffer shall be disabled when do the sdram initialization and
+     * enabled after the initialization during normal opeation.
+     */
+    dynamicConfig = config;
+    for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++)
+    {
+        base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK;        
+        dynamicConfig ++;
+    }
+}
+
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, 
+         emc_static_chip_config_t *config, uint32_t totalChips)
+{
+    assert(config);
+
+    uint32_t count;
+    emc_static_chip_config_t *staticConfig = config;
+
+    /* Initialize extended wait. */
+    if (extWait_Ns)
+    {   
+        for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++)
+        {
+            assert(staticConfig->specailConfig & kEMC_AsynchronosPageEnable);
+        }
+
+        base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1);
+        staticConfig ++;
+    }
+
+    /* Initialize the static memory chip specific configure. */
+    staticConfig = config;
+    for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++)
+    {
+
+        base->STATIC[staticConfig->chipIndex].STATICCONFIG = 
+            (staticConfig->specailConfig | staticConfig->memWidth);
+        base->STATIC[staticConfig->chipIndex].STATICWAITWEN =
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1);
+        base->STATIC[staticConfig->chipIndex].STATICWAITOEN = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0);
+        base->STATIC[staticConfig->chipIndex].STATICWAITRD = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1);
+        base->STATIC[staticConfig->chipIndex].STATICWAITPAGE = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1);
+        base->STATIC[staticConfig->chipIndex].STATICWAITWR = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2);
+        base->STATIC[staticConfig->chipIndex].STATICWAITTURN = 
+            EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1);
+        
+        staticConfig ++;
+    }
+}   
+
+void EMC_Deinit(EMC_Type *base)
+{
+    /* Deinit the EMC. */
+    base->CONTROL &= ~EMC_CONTROL_E_MASK;
+
+    /* Disable EMC clock. */
+    CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_EMC_H_
+#define _FSL_EMC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup emc
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief EMC driver version 2.0.0. */
+#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Define the chip numbers for dynamic and static memory devices. */
+#define EMC_STATIC_MEMDEV_NUM        (4U)
+#define EMC_DYNAMIC_MEMDEV_NUM       (4U)
+#define EMC_ADDRMAP_SHIFT        EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT
+#define EMC_ADDRMAP_MASK         (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK |EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_ADDRMAP(x)    (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK)     
+#define EMC_HZ_ONEMHZ   (1000000U)
+#define EMC_MILLISECS_ONESEC   (1000U)
+#define EMC_SDRAM_MODE_CL_SHIFT   (4U)
+#define EMC_SDRAM_MODE_CL_MASK   (0x70U)
+
+/*!
+ * @brief Define EMC memory width for static memory device.
+ */
+typedef enum _emc_static_memwidth
+{
+    kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */
+    kEMC_16BitWidth,       /*!< 16 bit memory width. */
+    kEMC_32BitWidth        /*!< 32 bit memory width. */
+} emc_static_memwidth_t;
+
+/*!
+ * @brief Define EMC static configuration.
+ */
+typedef enum _emc_static_special_config
+{ 
+    kEMC_AsynchronosPageEnable = 0x0008U,/*!< Enable the asynchronous page mode. page length four. */
+    kEMC_ActiveHighChipSelect = 0x0040U, /*!< Chip select active high. */
+    kEMC_ByteLaneStateAllLow = 0x0080U,  /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */
+    kEMC_ExtWaitEnable = 0x0100U,        /*!< Extended wait enable. */
+    kEMC_BufferEnable = 0x80000U         /*!< Buffer enable. */
+} emc_static_special_config_t;
+
+/*! @brief EMC dynamic memory device. */
+typedef enum _emc_dynamic_device
+{
+    kEMC_Sdram = 0x0U,   /*!< Dynamic memory device: SDRAM. */
+    kEMC_Lpsdram,        /*!< Dynamic memory device: Low-power SDRAM. */
+} emc_dynamic_device_t;
+
+/*! @brief EMC dynamic read strategy. */
+typedef enum _emc_dynamic_read
+{
+    kEMC_NoDelay = 0x0U,        /*!< No delay. */ 
+    kEMC_Cmddelay,              /*!< Command delayed strategy, using EMCCLKDELAY. */
+    kEMC_CmdDelayPulseOneclk,   /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */
+    kEMC_CmddelayPulsetwoclk,   /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */
+} emc_dynamic_read_t;
+
+/*! @brief EMC endian mode. */
+typedef enum _emc_endian_mode
+{
+    kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */
+    kEMC_BigEndian,           /*!< Big endian mode. */
+} emc_endian_mode_t;
+
+/*! @brief EMC Feedback clock input source select. */
+typedef enum _emc_fbclk_src
+{
+    kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */
+    kEMC_EMCFbclkInput    /*!< Use the external EMC_FBCLK input. */
+} emc_fbclk_src_t;
+
+/*! @brief EMC dynamic timing/delay configure structure. */
+typedef struct _emc_dynamic_timing_config
+{
+    emc_dynamic_read_t readConfig;   /* Dynamic read strategy. */
+    uint32_t refreshPeriod_Nanosec;  /*!< The refresh period in unit of nanosecond. */
+    uint32_t tRp_Ns;      /*!< Precharge command period in unit of nanosecond. */
+    uint32_t tRas_Ns;     /*!< Active to precharge command period in unit of nanosecond. */
+    uint32_t tSrex_Ns;    /*!< Self-refresh exit time in unit of nanosecond. */
+    uint32_t tApr_Ns;     /*!< Last data out to active command time in unit of nanosecond. */
+    uint32_t tDal_Ns;     /*!< Data-in to active command in unit of nanosecond. */
+    uint32_t tWr_Ns;      /*!< Write recovery time in unit of nanosecond. */
+    uint32_t tRc_Ns;      /*!< Active to active command period in unit of nanosecond. */       
+    uint32_t tRfc_Ns;     /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */
+    uint32_t tXsr_Ns;     /*!< Exit self-refresh to active command time in unit of nanosecond. */
+    uint32_t tRrd_Ns;     /*!< Active bank A to active bank B latency in unit of nanosecond. */
+    uint8_t tMrd_Nclk;     /*!< Load mode register to active command time in unit of EMCCLK cycles.*/
+} emc_dynamic_timing_config_t;
+
+/*!
+ * @brief EMC dynamic memory controller independent chip configuration structure.
+ * Please take refer to the address mapping table in the RM in EMC chapter when you 
+ * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table
+ * according to the bus width/banks/row/colum length for you device.
+ * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7) 
+ * and inset the bit 13 with 0.
+ * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the
+ * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length. 
+ * Set devAddrMap with 0x81.
+ */
+typedef struct _emc_dynamic_chip_config
+{
+    uint8_t chipIndex;    /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */
+    emc_dynamic_device_t dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */
+    uint8_t rAS_Nclk;    /*!< Active to read/write delay tRCD. */
+    uint16_t sdramModeReg;   /*!< Sdram mode register setting. */
+    uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */
+    uint8_t devAddrMap;  /*!< dynamic device address mapping, choose the address mapping for your specific device. */
+} emc_dynamic_chip_config_t;
+
+/*!
+ * @brief EMC static memory controller independent chip configuration structure.
+ */
+typedef struct _emc_static_chip_config
+{
+    uint8_t chipIndex;
+    emc_static_memwidth_t memWidth; /*!< Memory width. */
+    uint32_t specailConfig;     /*!< Static configuration,a logical OR of "emc_static_special_config_t". */
+    uint32_t tWaitWriteEn_Ns;/*!< The delay form chip select to write enable in unit of nanosecond. */
+    uint32_t tWaitOutEn_Ns;  /*!< The delay from chip selcet to output enable in unit of nanosecond. */
+    uint32_t tWaitReadNoPage_Ns;/*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */
+    uint32_t tWaitReadPage_Ns;  /*!< In page mode, the read after the first read wait states in unit of nanosecond. */ 
+    uint32_t tWaitWrite_Ns;     /*!< The delay from chip select to write access in unit of nanosecond. */
+    uint32_t tWaitTurn_Ns;      /*!< The Bus turn-around time in unit of nanosecond. */
+} emc_static_chip_config_t;
+
+/*!
+ * @brief EMC module basic configuration structure.
+ *
+ * Defines the static memory controller configure structure and 
+ * uses the EMC_Init() function to make necessary initializations.
+ *
+ */
+typedef struct _emc_basic_config
+{
+    emc_endian_mode_t endian;   /*!< Endian mode . */
+    emc_fbclk_src_t fbClkSrc;    /*!< The feedback clock source. */
+    uint8_t emcClkDiv; /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */
+} emc_basic_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name EMC Initialize and de-initialize opeartion
+ * @{
+ */
+/*!
+ * @brief Initializes the basic for EMC.
+ * This function ungates the EMC clock, initializes the emc system configure
+ * and enable the EMC module. This function must be called in the first step to initialize
+ * the external memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param config The EMC basic configuration.
+ */
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config);
+
+/*!
+ * @brief Initializes the dynamic memory controller.
+ * This function initializes the dynamic memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param timing The timing and latency for dynamica memory controller setting. It shall
+ *        be used for all dynamica memory chips, threfore the worst timing value for all
+ *        used chips must be given.
+ * @param configure The EMC dynamic memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * @param totalChips The total dynamic memory chip numbers been used or the length of the 
+ *        "emc_dynamic_chip_config_t" type memory.
+ */
+void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, 
+        emc_dynamic_chip_config_t *config, uint32_t totalChips);
+
+/*!
+ * @brief Initializes the static memory controller.
+ * This function initializes the static memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external static memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param extWait_Ns The extended wait timeout or the read/write transfer time.
+ *        This is common for all static memory chips and set with NULL if not required.
+ * @param configure The EMC static memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * @param totalChips The total static memory chip numbers been used or the length of the 
+ *        "emc_static_chip_config_t" type memory.
+ */
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips);
+
+/*!
+ * @brief Deinitializes the EMC module and gates the clock.
+ * This function gates the EMC controller clock. As a result, the EMC
+ * module doesn't work after calling this function.
+ *
+ * @param base EMC peripheral base address.
+ */
+void EMC_Deinit(EMC_Type *base);
+
+/* @} */
+
+/*!
+ * @name EMC Basic Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the EMC module.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC module, false disable.
+ */
+static inline void EMC_Enable(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CONTROL |= EMC_CONTROL_E_MASK;
+    }
+    else
+    {
+        base->CONTROL &= ~EMC_CONTROL_E_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/disables the EMC Dynaimc memory controller.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC dynamic memory controller, false disable.
+ */
+static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+    }
+    else
+    {
+        base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+    }
+}
+
+/*!
+ * @brief Enables/disables the EMC address mirror.
+ * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0
+ * and EMC_DYCS0 memory areas. Disable the address mirror enables
+ * EMC_cS0 and EMC_DYCS0 memory to be accessed.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable the address mirror, false disable the address mirror.
+ */
+static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable)
+{
+    if (enable) 
+    {
+        base->CONTROL |= EMC_CONTROL_M_MASK;
+    }
+    else 
+    {
+        base->CONTROL &= ~EMC_CONTROL_M_MASK;
+    }
+}
+
+/*!
+ * @brief Enter the self-refresh mode for dynamic memory controller.
+ * This function provided self-refresh mode enter or exit for application. 
+ *
+ * @param base EMC peripheral base address.
+ * @param enable   True enter the self-refresh mode, false to exit self-refresh
+ *                 and enter the normal mode.
+ */
+static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK;
+    }
+    else
+    {
+        base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK;
+    }
+}
+
+/*!
+ * @brief Get the operating mode of the EMC.
+ * This function can be used to get the operating mode of the EMC. 
+ *
+ * @param base EMC peripheral base address.
+ * @return The EMC in self-refresh mode if true, else in normal mode.
+ */
+static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base)
+{
+    return ((base->STATUS & EMC_STATUS_SA_MASK) ? true : false);
+}
+
+/*!
+ * @brief Enter/exit the low-power mode.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True Enter the low-power mode, false exit low-power mode
+ *        and return to normal mode. 
+ */
+static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CONTROL |= EMC_CONTROL_L_MASK;
+    }
+    else
+    {
+        base->CONTROL &= ~ EMC_CONTROL_L_MASK;
+    }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_EMC_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1810 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_enet.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief IPv4 PTP message IP version offset. */
+#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU
+/*! @brief IPv4 PTP message UDP protocol offset. */
+#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U
+/*! @brief IPv4 PTP message UDP port offset. */
+#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U
+/*! @brief IPv4 PTP message UDP message type offset. */
+#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU
+/*! @brief IPv4 PTP message UDP version offset. */
+#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU
+/*! @brief IPv4 PTP message UDP clock id offset. */
+#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU
+/*! @brief IPv4 PTP message UDP sequence id offset. */
+#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U
+/*! @brief IPv4 PTP message UDP control offset. */
+#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU
+/*! @brief IPv6 PTP message UDP protocol offset. */
+#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U
+/*! @brief IPv6 PTP message UDP port offset. */
+#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U
+/*! @brief IPv6 PTP message UDP message type offset. */
+#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU
+/*! @brief IPv6 PTP message UDP version offset. */
+#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU
+/*! @brief IPv6 PTP message UDP clock id offset. */
+#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U
+/*! @brief IPv6 PTP message UDP sequence id offset. */
+#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU
+/*! @brief IPv6 PTP message UDP control offset. */
+#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU
+/*! @brief PTPv2 message Ethernet packet type offset. */
+#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU
+/*! @brief PTPv2 message Ethernet message type offset. */
+#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU
+/*! @brief PTPv2 message Ethernet version type offset. */
+#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU
+/*! @brief PTPv2 message Ethernet clock id offset. */
+#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22
+/*! @brief PTPv2 message Ethernet sequence id offset. */
+#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c
+/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */
+#define ENET_ETHERNETL2 0x88F7U
+/*! @brief Packet type IPv4. */
+#define ENET_IPV4 0x0800U
+/*! @brief Packet type IPv6. */
+#define ENET_IPV6 0x86ddU
+/*! @brief Packet type VLAN. */
+#define ENET_8021QVLAN 0x8100U
+/*! @brief UDP protocol type. */
+#define ENET_UDPVERSION 0x0011U
+/*! @brief Packet IP version IPv4. */
+#define ENET_IPV4VERSION 0x0004U
+/*! @brief Packet IP version IPv6. */
+#define ENET_IPV6VERSION 0x0006U
+
+/*! @brief Defines 10^9 nanosecond. */
+#define ENET_NANOSECS_ONESECOND (1000000000U)
+/*! @brief Defines 10^6 microsecond.*/
+#define ENET_MICRSECS_ONESECOND (1000000U)
+
+/*! @brief Rx buffer LSB ignore bits. */
+#define ENET_RXBUFF_IGNORELSB_BITS (2U)
+/*! @brief ENET FIFO size unit. */
+#define ENET_FIFOSIZE_UNIT (256U)
+/*! @brief ENET half-dulpex default IPG. */
+#define ENET_HALFDUPLEX_DEFAULTIPG (4U)
+/*! @breif ENET miminum ring length. */
+#define ENET_MIN_RINGLEN (4U)
+/*! @breif ENET wakeup filter numbers. */
+#define ENET_WAKEUPFILTER_NUM (8U)
+/*! @breif Requried systime timer frequency. */
+#define ENET_SYSTIME_REQUIRED_CLK_MHZ (50U)
+/*! @brief Ethernet VLAN tag length. */
+#define ENET_FRAME_VLAN_TAGLEN 4U
+
+/*! @brief AVB TYPE */
+#define ENET_AVBTYPE 0x22F0U
+#define ENET_HEAD_TYPE_OFFSET (12)
+#define ENET_HEAD_AVBTYPE_OFFSET (16)
+
+/*! @brief Defines the macro for converting constants from host byte order to network byte order. */
+#define ENET_HTONS(n) __REV16(n)
+#define ENET_HTONL(n) __REV(n)
+#define ENET_NTOHS(n) __REV16(n)
+#define ENET_NTOHL(n) __REV(n)
+
+/* Typedef for interrupt handler. */
+typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the ENET instance from peripheral base address.
+ *
+ * @param base ENET peripheral base address.
+ * @return ENET instance.
+ */
+uint32_t ENET_GetInstance(ENET_Type *base);
+
+/*!
+ * @brief Increase the index in the ring.
+ *
+ * @param index The current index.
+ * @param max The size.
+ * @return the increased index.
+ */
+static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max);
+
+/*!
+ * @brief Set ENET system configuration.
+ *  This function reset the ethernet module and set the phy selection.
+ *  It should be called before any other ethernet operation.
+ *
+ * @param miiMode  The MII/RMII mode for interface between the phy and ethernet.
+ */
+static void ENET_SetSYSControl(enet_mii_mode_t miiMode);
+
+/*!
+ * @brief Set ENET DMA controller with the configuration.
+ *
+ * @param base ENET peripheral base address.
+ * @param config ENET Mac configuration.
+ */
+static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config);
+
+/*!
+ * @brief Set ENET MAC controller with the configuration.
+ *
+ * @param base ENET peripheral base address.
+ * @param config ENET Mac configuration.
+ * @param macAddr ENET six-byte mac address.
+ */
+static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr);
+/*!
+ * @brief Set ENET MTL with the configuration.
+ *
+ * @param base ENET peripheral base address.
+ * @param config ENET Mac configuration.
+ */
+static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config);
+
+/*!
+ * @brief Set ENET DMA transmit buffer descriptors for one channel.
+ *
+ * @param base ENET peripheral base address.
+ * @param bufferConfig ENET buffer configuration.
+ * @param intTxEnable tx interrupt enable.
+ * @param channel The channel number, 0 , 1.
+ */
+static status_t ENET_TxDescriptorsInit(ENET_Type *base,
+                                       const enet_buffer_config_t *bufferConfig,
+                                       bool intTxEnable,
+                                       uint8_t channel);
+
+/*!
+ * @brief Set ENET DMA receive buffer descriptors for one channel.
+ *
+ * @param base ENET peripheral base address.
+ * @param bufferConfig ENET buffer configuration.
+ * @param intRxEnable tx interrupt enable.
+ * @param channel The channel number, 0 , 1.
+ * @param doubleBuffEnable Two buffers are enabled.
+ */
+static status_t ENET_RxDescriptorsInit(ENET_Type *base,
+                                       const enet_buffer_config_t *bufferConfig,
+                                       bool intRxEnable,
+                                       uint8_t channel,
+                                       bool doubleBuffEnable);
+
+/*!
+ * @brief Set ENET get transmit ring descriptors.
+ *
+ * @param data The ENET data to be transfered.
+ * @param handle ENET handler.
+ */
+static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle);
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/*!
+ * @brief Sets the ENET 1588 feature.
+ *
+ * Enable the enhacement 1588 buffer descriptor mode and start
+ * the 1588 timer.
+ *
+ * @param base ENET peripheral base address.
+ * @param config The ENET configuration.
+ * @param refClk_Hz The reference clock for ptp 1588.
+ */
+static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz);
+
+/*!
+ * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame.
+ *
+ * @param data  The ENET read data for frame parse.
+ * @param ptpTsData The ENET PTP message and time-stamp data pointer.
+ * @param isFastEnabled The fast parse flag.
+ *        - true , Fast processing, only check if this is a PTP message.
+ *        - false, Store the PTP message data after check the PTP message.
+ */
+static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled);
+
+/*!
+ * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring.
+ *
+ * @param ptpTsDataRing The PTP message and time-stamp data ring pointer.
+ * @param ptpTimeData   The new PTP 1588 time-stamp data pointer.
+ */
+static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData);
+
+/*!
+ * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring.
+ *
+ * @param ptpTsDataRing The PTP message and time-stamp data ring pointer.
+ * @param ptpTimeData   The find out right PTP 1588 time-stamp data pointer with the specific PTP message.
+ */
+static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata);
+
+/*!
+ * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring.
+ *
+ * @param base   ENET peripheral base address.
+ * @param handle ENET handler.
+ * @param rxDesc The ENET receive descriptor pointer.
+ * @param channel The rx channel.
+ * @param ptpTimeData The PTP 1588 time-stamp data pointer.
+ */
+static status_t ENET_StoreRxFrameTime(ENET_Type *base,
+                                      enet_handle_t *handle,
+                                      enet_rx_bd_struct_t *rxDesc,
+                                      uint8_t channel,
+                                      enet_ptp_time_data_t *ptpTimeData);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to enet handles for each instance. */
+static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_LPC_ENET_COUNT] = {NULL};
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to enet clocks for each instance. */
+const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT] = ETH_CLOCKS;
+#endif /*  FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to enet bases for each instance. */
+static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS;
+
+/*! @brief Pointers to enet IRQ number for each instance. */
+static const IRQn_Type s_enetIrqId[] = ENET_IRQS;
+
+/* ENET ISR for transactional APIs. */
+static enet_isr_t s_enetIsr;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max)
+{
+    /* Increase the index. */
+    index++;
+    if (index >= max)
+    {
+        index = 0;
+    }
+    return index;
+}
+
+static void ENET_SetSYSControl(enet_mii_mode_t miiMode)
+{
+    /* Reset first. */
+    SYSCON->PRESETCTRL[2] = SYSCON_PRESETCTRL_ETH_RST_MASK;
+    SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_ETH_RST_MASK;
+    /* Set MII/RMII before the peripheral ethernet dma reset. */
+    SYSCON->ETHPHYSEL = (SYSCON->ETHPHYSEL & ~SYSCON_ETHPHYSEL_PHY_SEL_MASK) | SYSCON_ETHPHYSEL_PHY_SEL(miiMode);
+}
+
+static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config)
+{
+    assert(config);
+
+    uint8_t index;
+    uint32_t reg;
+    uint32_t burstLen;
+
+    /* Reset first and wait for the complete
+     * The reset bit will automatically be cleared after complete. */
+    base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK;
+    while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK)
+    {
+    }
+
+    /* Set the burst length. */
+    for (index = 0; index < ENET_RING_NUM_MAX; index++)
+    {
+        burstLen = kENET_BurstLen1;
+        if (config->multiqueueCfg)
+        {
+            burstLen = config->multiqueueCfg->burstLen;
+        }
+        base->DMA_CH[index].DMA_CHX_CTRL = burstLen & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK;
+
+        reg = base->DMA_CH[index].DMA_CHX_TX_CTRL & ~ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK;
+        base->DMA_CH[index].DMA_CHX_TX_CTRL = reg | ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(burstLen & 0x3F);
+
+        reg = base->DMA_CH[index].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK;
+        base->DMA_CH[index].DMA_CHX_RX_CTRL = reg | ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(burstLen & 0x3F);
+    }
+}
+
+static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config)
+{
+    assert(config);
+
+    uint32_t txqOpreg = 0;
+    uint32_t rxqOpReg = 0;
+    enet_multiqueue_config_t *multiqCfg = config->multiqueueCfg;
+    uint8_t index;
+
+    /* Set transmit operation mode. */
+    if (config->specialControl & kENET_StoreAndForward)
+    {
+        txqOpreg = ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK;
+        rxqOpReg = ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK;
+    }
+    txqOpreg |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK |
+                ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(ENET_MTL_TXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1);
+    base->MTL_QUEUE[0].MTL_TXQX_OP_MODE = txqOpreg | ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2);
+    base->MTL_QUEUE[1].MTL_TXQX_OP_MODE = txqOpreg;
+
+    /* Set receive operation mode. */
+    rxqOpReg |= ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK |
+                ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(ENET_MTL_RXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1);
+    base->MTL_QUEUE[0].MTL_RXQX_OP_MODE = rxqOpReg;
+
+    /* Set the schedule/arbitration(set for multiple queues). */
+    if (multiqCfg)
+    {
+        base->MTL_OP_MODE = ENET_MTL_OP_MODE_SCHALG(multiqCfg->mtltxSche) | ENET_MTL_OP_MODE_RAA(multiqCfg->mtlrxSche);
+        /* Set the rx queue mapping to dma channel. */
+        base->MTL_RXQ_DMA_MAP = multiqCfg->mtlrxQuemap;
+        /* Set the tx/rx queue operation mode for multi-queue. */
+        base->MTL_QUEUE[1].MTL_TXQX_OP_MODE |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2);
+        base->MTL_QUEUE[1].MTL_RXQX_OP_MODE = rxqOpReg;
+
+        /* Set the tx/rx queue weight. */
+        for (index = 0; index < ENET_RING_NUM_MAX; index++)
+        {
+            base->MTL_QUEUE[index].MTL_TXQX_QNTM_WGHT = multiqCfg->txqueweight[index];
+            base->MTL_QUEUE[index].MTL_RXQX_CTRL = ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(multiqCfg->rxqueweight[index]);
+        }
+    }
+}
+
+static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr)
+{
+    assert(config);
+
+    uint32_t reg = 0;
+
+    /* Set Macaddr */
+    /* The dma channel 0 is set as to which the rx packet
+     * whose DA matches the MAC address content is routed. */
+    if (macAddr)
+    {
+        ENET_SetMacAddr(base, macAddr);
+    }
+
+    /* Set the receive filter. */
+    reg = ENET_MAC_FRAME_FILTER_PR(!!(config->specialControl & kENET_PromiscuousEnable)) |
+          ENET_MAC_FRAME_FILTER_DBF(!!(config->specialControl & kENET_BroadCastRxDisable)) |
+          ENET_MAC_FRAME_FILTER_PM(!!(config->specialControl & kENET_MulticastAllEnable));
+    base->MAC_FRAME_FILTER = reg;
+    /* Flow control. */
+    if (config->specialControl & kENET_FlowControlEnable)
+    {
+        base->MAC_RX_FLOW_CTRL = ENET_MAC_RX_FLOW_CTRL_RFE_MASK | ENET_MAC_RX_FLOW_CTRL_UP_MASK;
+        base->MAC_TX_FLOW_CTRL_Q[0] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration);
+        base->MAC_TX_FLOW_CTRL_Q[1] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration);
+    }
+
+    /* Set the 1us ticket. */
+    reg = CLOCK_GetFreq(kCLOCK_CoreSysClk) / ENET_MICRSECS_ONESECOND - 1;
+    base->MAC_1US_TIC_COUNTR = ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(reg);
+
+    /* Set the speed and duplex. */
+    reg = ENET_MAC_CONFIG_ECRSFD_MASK | ENET_MAC_CONFIG_PS_MASK | ENET_MAC_CONFIG_DM(config->miiDuplex) |
+          ENET_MAC_CONFIG_FES(config->miiSpeed) |
+          ENET_MAC_CONFIG_S2KP(!!(config->specialControl & kENET_8023AS2KPacket));
+    if (config->miiDuplex == kENET_MiiHalfDuplex)
+    {
+        reg |= ENET_MAC_CONFIG_IPG(ENET_HALFDUPLEX_DEFAULTIPG);
+    }
+    base->MAC_CONFIG = reg;
+
+    /* Enable channel. */
+    base->MAC_RXQ_CTRL[0] = ENET_MAC_RXQ_CTRL_RXQ0EN(1) | ENET_MAC_RXQ_CTRL_RXQ1EN(1);
+}
+
+static status_t ENET_TxDescriptorsInit(ENET_Type *base,
+                                       const enet_buffer_config_t *bufferConfig,
+                                       bool intTxEnable,
+                                       uint8_t channel)
+{
+    uint16_t j;
+    enet_tx_bd_struct_t *txbdPtr;
+    uint32_t control = intTxEnable ? ENET_TXDESCRIP_RD_IOC_MASK : 0;
+    const enet_buffer_config_t *buffCfg = bufferConfig;
+
+    if (!buffCfg)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check the ring length. */
+    if (buffCfg->txRingLen < ENET_MIN_RINGLEN)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Set the tx descriptor start/tail pointer, shall be word aligned. */
+    base->DMA_CH[channel].DMA_CHX_TXDESC_LIST_ADDR =
+        (uint32_t)buffCfg->txDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;
+    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR =
+        (uint32_t)buffCfg->txDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK;
+    /* Set the tx ring length. */
+    base->DMA_CH[channel].DMA_CHX_TXDESC_RING_LENGTH =
+        (uint16_t)(buffCfg->txRingLen - 1) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK;
+
+    /* Init the txbdPtr to the transmit descriptor start address. */
+    txbdPtr = (enet_tx_bd_struct_t *)(buffCfg->txDescStartAddrAlign);
+    for (j = 0; j < buffCfg->txRingLen; j++)
+    {
+        txbdPtr->buff1Addr = 0;
+        txbdPtr->buff2Addr = 0;
+        txbdPtr->buffLen = control;
+        txbdPtr->controlStat = 0;
+        txbdPtr++;
+    }
+
+    return kStatus_Success;
+}
+
+static status_t ENET_RxDescriptorsInit(
+    ENET_Type *base, const enet_buffer_config_t *bufferConfig, bool intRxEnable, uint8_t channel, bool doubleBuffEnable)
+{
+    uint16_t j;
+    uint32_t reg;
+    enet_rx_bd_struct_t *rxbdPtr;
+    uint16_t index;
+    const enet_buffer_config_t *buffCfg = bufferConfig;
+    uint32_t control = ENET_RXDESCRIP_WR_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK;
+
+    if (!buffCfg)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (intRxEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_IOC_MASK;
+    }
+
+    if (doubleBuffEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK;
+    }
+
+    /* Check the ring length. */
+    if (buffCfg->rxRingLen < ENET_MIN_RINGLEN)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set the rx descriptor start/tail pointer, shall be word aligned. */
+    base->DMA_CH[channel].DMA_CHX_RXDESC_LIST_ADDR =
+        (uint32_t)buffCfg->rxDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;
+    base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR =
+        (uint32_t)buffCfg->rxDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK;
+    base->DMA_CH[channel].DMA_CHX_RXDESC_RING_LENGTH =
+        (uint16_t)(buffCfg->rxRingLen - 1) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK;
+    reg = base->DMA_CH[channel].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK;
+    reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BITS);
+    base->DMA_CH[channel].DMA_CHX_RX_CTRL = reg;
+
+    /* Init the rxbdPtr to the receive descriptor start address. */
+    rxbdPtr = (enet_rx_bd_struct_t *)(buffCfg->rxDescStartAddrAlign);
+
+    for (j = 0; j < buffCfg->rxRingLen; j++)
+    {
+        if (doubleBuffEnable)
+        {
+            index = 2 * j;
+        }
+        else
+        {
+            index = j;
+        }
+        rxbdPtr->buff1Addr = *(buffCfg->rxBufferStartAddr + index);
+        /* The second buffer is set with 0 because it is not required for normal case. */
+        if (doubleBuffEnable)
+        {
+            rxbdPtr->buff2Addr = *(buffCfg->rxBufferStartAddr + index + 1);
+        }
+        else
+        {
+            rxbdPtr->buff2Addr = 0;
+        }
+
+        /* Set the valid and DMA own flag.*/
+        rxbdPtr->control = control;
+        rxbdPtr++;
+    }
+
+    return kStatus_Success;
+}
+
+static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle)
+{
+    /* Defuault use the queue/ring 0. */
+    uint8_t ringId = 0;
+
+    if (handle->multiQueEnable)
+    {
+        /* Parse the frame and choose the queue id for different avb frames
+         *  AVB Class frame in queue 1.
+         *  non-AVB frame in queue 0.
+         */
+        if ((*(uint16_t *)(data + ENET_HEAD_TYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) &&
+            ((*(uint16_t *)(data + ENET_HEAD_AVBTYPE_OFFSET)) == ENET_HTONS(ENET_AVBTYPE)))
+        {
+            /* AVBTP stream data frame. */
+            ringId = 1;
+        }
+    }
+
+    return ringId;
+}
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz)
+{
+    assert(config);
+    assert(config->ptpConfig);
+    assert(refClk_Hz);
+
+    uint32_t control;
+    enet_ptp_config_t *ptpConfig = config->ptpConfig;
+
+    /* Clear the timestamp interrupt first. */
+    base->MAC_INTR_EN &= ~ENET_MAC_INTR_EN_TSIE_MASK;
+
+    if (ptpConfig->fineUpdateEnable)
+    {
+        base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK;
+        /* Set the initial added value for the fine update. */
+        control = 100000000U / (refClk_Hz / ENET_MICRSECS_ONESECOND / ENET_SYSTIME_REQUIRED_CLK_MHZ);
+        base->MAC_SYS_TIMESTMP_ADDEND = control;
+        base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK;
+        while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
+        {
+        }
+    }
+
+    /* Enable the IEEE 1588 timestamping and snapshot for event message. */
+    control = ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK |
+              ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK |
+              ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK | ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK |
+              ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(ptpConfig->tsRollover);
+
+    if (ptpConfig->ptp1588V2Enable)
+    {
+        control |= ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK;
+    }
+
+    /* Initialize the sub-second increment register. */
+    if (ptpConfig->tsRollover)
+    {
+        base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(ENET_NANOSECS_ONESECOND / refClk_Hz);
+        base->MAC_SYS_TIME_NSCND_UPD = 0;
+    }
+    else
+    {
+        /* round up. */
+        uint32_t data = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK / refClk_Hz;
+        base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(data);
+        base->MAC_SYS_TIME_NSCND_UPD = 0;
+    }
+    /* Set the second.*/
+    base->MAC_SYS_TIME_SCND_UPD = 0;
+    base->MAC_SYS_TIME_HWORD_SCND = 0;
+
+    /* Initialize the system timer. */
+    base->MAC_TIMESTAMP_CTRL = control | ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK;
+}
+
+static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled)
+{
+    assert(data);
+    if (!isFastEnabled)
+    {
+        assert(ptpTsData);
+    }
+
+    bool isPtpMsg = false;
+    uint8_t *buffer = data;
+    uint16_t ptpType;
+
+    /* Check for VLAN frame. */
+    if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN))
+    {
+        buffer += ENET_FRAME_VLAN_TAGLEN;
+    }
+
+    ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET);
+    switch (ENET_HTONS(ptpType))
+    { /* Ethernet layer 2. */
+        case ENET_ETHERNETL2:
+            if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType)
+            {
+                isPtpMsg = true;
+                if (!isFastEnabled)
+                {
+                    /* It's a ptpv2 message and store the ptp header information. */
+                    ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F;
+                    ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F;
+                    ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET));
+                    memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET),
+                           kENET_PtpSrcPortIdLen);
+                }
+            }
+            break;
+        /* IPV4. */
+        case ENET_IPV4:
+            if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION)
+            {
+                if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) &&
+                    (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION))
+                {
+                    /* Set the PTP message flag. */
+                    isPtpMsg = true;
+                    if (!isFastEnabled)
+                    {
+                        /* It's a IPV4 ptp message and store the ptp header information. */
+                        ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F;
+                        ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F;
+                        ptpTsData->sequenceId =
+                            ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET));
+                        memcpy((void *)&ptpTsData->sourcePortId[0],
+                               (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen);
+                    }
+                }
+            }
+            break;
+        /* IPV6. */
+        case ENET_IPV6:
+            if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION)
+            {
+                if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) &&
+                    (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION))
+                {
+                    /* Set the PTP message flag. */
+                    isPtpMsg = true;
+                    if (!isFastEnabled)
+                    {
+                        /* It's a IPV6 ptp message and store the ptp header information. */
+                        ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F;
+                        ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F;
+                        ptpTsData->sequenceId =
+                            ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET));
+                        memcpy((void *)&ptpTsData->sourcePortId[0],
+                               (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen);
+                    }
+                }
+            }
+            break;
+        default:
+            break;
+    }
+    return isPtpMsg;
+}
+
+static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(ptpTsDataRing);
+    assert(ptpTsDataRing->ptpTsData);
+    assert(ptpTimeData);
+
+    uint16_t usedBuffer = 0;
+
+    /* Check if the buffers ring is full. */
+    if (ptpTsDataRing->end >= ptpTsDataRing->front)
+    {
+        usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
+    }
+    else
+    {
+        usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
+    }
+
+    if (usedBuffer == ptpTsDataRing->size)
+    {
+        return kStatus_ENET_PtpTsRingFull;
+    }
+
+    /* Copy the new data into the buffer. */
+    memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t));
+
+    /* Increase the buffer pointer to the next empty one. */
+    ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size;
+
+    return kStatus_Success;
+}
+
+static status_t ENET_StoreRxFrameTime(ENET_Type *base,
+                                      enet_handle_t *handle,
+                                      enet_rx_bd_struct_t *rxDesc,
+                                      uint8_t channel,
+                                      enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(ptpTimeData);
+
+    uint32_t nanosecond;
+    uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */
+
+    /* Get transmit time stamp second. */
+    nanosecond = rxDesc->reserved | rxDesc->buff1Addr;
+    if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
+    {
+        /* Binary rollover. */
+        nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
+    }
+    ptpTimeData->timeStamp.second = nanosecond / nanoOverSize;
+    ptpTimeData->timeStamp.nanosecond = nanosecond % nanoOverSize;
+
+    /* Store the timestamp to the receive time stamp ring. */
+    /* Check if the buffers ring is full. */
+    return ENET_Ptp1588UpdateTimeRing(&handle->rxBdRing[channel].rxPtpTsDataRing, ptpTimeData);
+}
+
+static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata)
+{
+    assert(ptpTsDataRing);
+    assert(ptpTsDataRing->ptpTsData);
+    assert(ptpTimedata);
+
+    uint32_t index;
+    uint32_t size;
+    uint16_t usedBuffer = 0;
+
+    /* Check the PTP 1588 timestamp ring. */
+    if (ptpTsDataRing->front == ptpTsDataRing->end)
+    {
+        return kStatus_ENET_PtpTsRingEmpty;
+    }
+
+    /* Search the element in the ring buffer */
+    index = ptpTsDataRing->front;
+    size = ptpTsDataRing->size;
+    while (index != ptpTsDataRing->end)
+    {
+        if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) &&
+            (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]),
+                     (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) &&
+            ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) &&
+            ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType))
+        {
+            break;
+        }
+
+        /* Increase the ptp ring index. */
+        index = (index + 1) % size;
+    }
+
+    if (index == ptpTsDataRing->end)
+    {
+        /* Check if buffers is full. */
+        if (ptpTsDataRing->end >= ptpTsDataRing->front)
+        {
+            usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front;
+        }
+        else
+        {
+            usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end);
+        }
+
+        if (usedBuffer == ptpTsDataRing->size)
+        { /* Drop one in the front. */
+            ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
+        }
+        return kStatus_ENET_PtpTsRingFull;
+    }
+
+    /* Get the right timestamp of the required ptp messag. */
+    ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second;
+    ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond;
+
+    /* Increase the index. */
+    ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size;
+
+    return kStatus_Success;
+}
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+uint32_t ENET_GetInstance(ENET_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < FSL_FEATURE_SOC_LPC_ENET_COUNT; instance++)
+    {
+        if (s_enetBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < FSL_FEATURE_SOC_LPC_ENET_COUNT);
+
+    return instance;
+}
+
+void ENET_GetDefaultConfig(enet_config_t *config)
+{
+    /* Checks input parameter. */
+    assert(config);
+
+    /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */
+    config->miiMode = kENET_RmiiMode;
+    config->miiSpeed = kENET_MiiSpeed100M;
+    config->miiDuplex = kENET_MiiFullDuplex;
+
+    /* Sets default configuration for other options. */
+    config->specialControl = false;
+    config->multiqueueCfg = NULL;
+    config->pauseDuration = 0;
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    config->ptpConfig = NULL;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+}
+
+void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz)
+{
+    assert(config);
+
+    uint32_t instance = ENET_GetInstance(base);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate ENET clock. */
+    CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    /* System configure fistly. */
+    ENET_SetSYSControl(config->miiMode);
+
+    /* Initializes the ENET DMA with basic function. */
+    ENET_SetDMAControl(base, config);
+
+    /* Initializes the ENET MTL with basic function. */
+    ENET_SetMTL(base, config);
+
+    /* Initializes the ENET MAC with basic function. */
+    ENET_SetMacControl(base, config, macAddr);
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    ENET_SetPtp1588(base, config, refclkSrc_Hz);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+}
+
+void ENET_Deinit(ENET_Type *base)
+{
+    /* Reset first and wait for the complete
+     * The reset bit will automatically be cleared after complete. */
+    base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK;
+    while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK)
+    {
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disables the clock source. */
+    CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig)
+{
+    assert(config);
+    assert(bufferConfig);
+
+    bool intTxEnable;
+    bool intRxEnable;
+    bool doubleBuffEnable = (config->specialControl & kENET_DescDoubleBuffer) ? true : false;
+    uint8_t ringNum = config->multiqueueCfg == NULL ? 1 : 2;
+    uint8_t channel;
+
+    for (channel = 0; channel < ringNum; channel++)
+    {
+        intRxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) ? true : false;
+
+        if (ENET_TxDescriptorsInit(base, bufferConfig, intTxEnable, channel) != kStatus_Success)
+        {
+            return kStatus_Fail;
+        }
+        intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false;
+
+        if (ENET_RxDescriptorsInit(base, bufferConfig, intRxEnable, channel, doubleBuffEnable) != kStatus_Success)
+        {
+            return kStatus_Fail;
+        }
+
+        bufferConfig++;
+        if (!bufferConfig)
+        {
+            return kStatus_InvalidArgument;
+        }
+    }
+    return kStatus_Success;
+}
+
+void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum)
+{
+    assert(txRingNum);
+    assert(rxRingNum);
+
+    uint8_t index;
+
+    if (txRingNum > ENET_RING_NUM_MAX)
+    {
+        txRingNum = ENET_RING_NUM_MAX;
+    }
+    if (rxRingNum > ENET_RING_NUM_MAX)
+    {
+        rxRingNum = ENET_RING_NUM_MAX;
+    }
+    /* Start/Acive the DMA first. */
+    for (index = 0; index < rxRingNum; index++)
+    {
+        base->DMA_CH[index].DMA_CHX_RX_CTRL |= ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK;
+    }
+    for (index = 0; index < txRingNum; index++)
+    {
+        base->DMA_CH[index].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    }
+
+    /* Enable the RX/TX then. */
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK;
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK;
+}
+
+void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
+{
+    uint32_t interrupt = mask & 0xFFFFU;
+    uint8_t index;
+
+    /* For dma interrupt. */
+    if (interrupt)
+    {
+        for (index = 0; index < ENET_RING_NUM_MAX; index++)
+        {
+            /* Set for all abnormal interrupts. */
+            if (ENET_ABNORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK;
+            }
+            /* Set for all normal interrupts. */
+            if (ENET_NORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
+            }
+            base->DMA_CH[index].DMA_CHX_INT_EN = interrupt;
+        }
+    }
+    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
+    if (interrupt)
+    {
+        /* MAC interrupt */
+        base->MAC_INTR_EN |= interrupt;
+    }
+}
+
+void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask)
+{
+    volatile uint32_t dummy;
+
+    if (mask & kENET_MacTimestamp)
+    {
+       dummy = base->MAC_SYS_TIMESTMP_STAT;
+    }
+    else if (mask & kENET_MacPmt)
+    {
+       dummy = base->MAC_PMT_CRTL_STAT;
+    }
+    else
+    {
+        /* Add for avoid the misra 2004 rule 14.10 */
+    }
+    (void)dummy;
+}
+
+void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)
+{
+    uint32_t interrupt = mask & 0xFFFFU;
+    uint8_t index;
+
+    /* For dma interrupt. */
+    if (interrupt)
+    {
+        for (index = 0; index < ENET_RING_NUM_MAX; index++)
+        {
+            /* Set for all abnormal interrupts. */
+            if (ENET_ABNORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK;
+            }
+            /* Set for all normal interrupts. */
+            if (ENET_NORM_INT_MASK & interrupt)
+            {
+                interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
+            }
+            base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt;
+        }
+    }
+    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
+    if (interrupt)
+    {
+        /* MAC interrupt */
+        base->MAC_INTR_EN &= ~interrupt;
+    }
+}
+
+void ENET_CreateHandler(ENET_Type *base,
+                        enet_handle_t *handle,
+                        enet_config_t *config,
+                        enet_buffer_config_t *bufferConfig,
+                        enet_callback_t callback,
+                        void *userData)
+{
+    assert(config);
+    assert(bufferConfig);
+    assert(callback);
+
+    uint8_t ringNum = 1;
+    uint8_t count = 0;
+    uint8_t rxIntEnable = 0;
+    enet_buffer_config_t *buffConfig = bufferConfig;
+
+    if (config->multiqueueCfg)
+    {
+        ringNum = 2;
+        handle->multiQueEnable = true;
+    }
+
+    /* Store transfer parameters in handle pointer. */
+    memset(handle, 0, sizeof(enet_handle_t));
+    if (config->specialControl & kENET_DescDoubleBuffer)
+    {
+        handle->doubleBuffEnable = true;
+    }
+    if (config->multiqueueCfg)
+    {
+        handle->multiQueEnable = true;
+    }
+    for (count = 0; count < ringNum; count++)
+    {
+        handle->rxBdRing[count].rxBdBase = buffConfig->rxDescStartAddrAlign;
+        handle->rxBdRing[count].rxGenIdx = 0;
+        handle->rxBdRing[count].rxRingLen = buffConfig->rxRingLen;
+        handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign;
+
+        handle->txBdRing[count].txBdBase = buffConfig->txDescStartAddrAlign;
+        handle->txBdRing[count].txRingLen = buffConfig->txRingLen;
+        handle->txBdRing[count].txGenIdx = 0;
+        handle->txBdRing[count].txConsumIdx = 0;
+        handle->txBdRing[count].txDescUsed = 0;
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+        assert(bufferConfig->rxPtpTsData);
+        assert(bufferConfig->txPtpTsData);
+        assert(buffConfig->rxRingLen <= ENET_RXBUFFSTORE_NUM);
+
+        uint32_t index;
+
+        handle->rxBdRing[count].rxPtpTsDataRing.ptpTsData = buffConfig->rxPtpTsData;
+        handle->rxBdRing[count].rxPtpTsDataRing.front = 0;
+        handle->rxBdRing[count].rxPtpTsDataRing.end = 0;
+        handle->rxBdRing[count].rxPtpTsDataRing.size = buffConfig->ptpTsRxBuffNum;
+        handle->txBdRing[count].txPtpTsDataRing.ptpTsData = buffConfig->txPtpTsData;
+        handle->txBdRing[count].txPtpTsDataRing.front = 0;
+        handle->txBdRing[count].txPtpTsDataRing.end = 0;
+        handle->txBdRing[count].txPtpTsDataRing.size = buffConfig->ptpTsTxBuffNum;
+
+        for (index = 0; index < buffConfig->rxRingLen; index++)
+        {
+            handle->rxbuffers[index] = *(buffConfig->rxBufferStartAddr + index);
+        }
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+        /* Enable tx interrupt for use transactional API to do tx buffer free/requeue. */
+        base->DMA_CH[count].DMA_CHX_INT_EN |= ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK;
+        /* Check if the rx interrrupt is enabled. */
+        rxIntEnable |= (base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK);
+        buffConfig++;
+    }
+
+    handle->rxintEnable = rxIntEnable ? true : false;
+
+    /* Save the handle pointer in the global variables. */
+    s_ENETHandle[ENET_GetInstance(base)] = handle;
+
+    /* Set callback and userData. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable the NVIC for tx. */
+    s_enetIsr = ENET_IRQHandler;
+    EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
+}
+
+void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr)
+{
+    assert(macAddr);
+
+    uint32_t address = base->MAC_ADDR_LOW;
+
+    /* Get from physical address lower register. */
+    macAddr[2] = 0xFFU & (address >> 24U);
+    macAddr[3] = 0xFFU & (address >> 16U);
+    macAddr[4] = 0xFFU & (address >> 8U);
+    macAddr[5] = 0xFFU & address;
+
+    /* Get from physical address high register. */
+    address = base->MAC_ADDR_HIGH;
+    macAddr[0] = 0xFFU & (address >> 8U);
+    macAddr[1] = 0xFFU & address;
+}
+
+void ENET_SetSMI(ENET_Type *base)
+{
+    uint32_t crDiv;
+    uint32_t srcClock_Hz = CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000000U;
+
+    if ((srcClock_Hz >= 20U) && (srcClock_Hz < 35))
+    {
+        crDiv = 2;
+    }
+    else if ((srcClock_Hz >= 35) && (srcClock_Hz < 60))
+    {
+        crDiv = 3;
+    }
+    else if ((srcClock_Hz >= 100) && (srcClock_Hz < 150))
+    {
+        crDiv = 1;
+    }
+    else
+    {
+        crDiv = 0;
+    }
+
+    base->MAC_MDIO_ADDR = ENET_MAC_MDIO_ADDR_CR(crDiv);
+}
+
+void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+    uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK;
+
+    /* Build MII write command. */
+    base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiWriteFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) |
+                          ENET_MAC_MDIO_ADDR_RDA(phyReg);
+    base->MAC_MDIO_DATA = data;
+    base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK;
+}
+
+void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg)
+{
+    uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK;
+
+    /* Build MII read command. */
+    base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiReadFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) |
+                          ENET_MAC_MDIO_ADDR_RDA(phyReg);
+    base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK;
+}
+
+void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter)
+{
+    uint8_t index;
+    uint32_t *reg = wakeFilter;
+
+    /* Disable the tx dma. */
+    base->DMA_CH[0].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    base->DMA_CH[1].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+
+    /* Disable the mac tx/rx. */
+    base->MAC_CONFIG &= ~(ENET_MAC_CONFIG_RE_MASK | ENET_MAC_CONFIG_TE_MASK);
+    /* Enable the remote wakeup packet and enable the power down mode. */
+    if (wakeFilter)
+    {
+        for (index = 0; index < ENET_WAKEUPFILTER_NUM; index++)
+        {
+            base->MAC_RWAKE_FRFLT = *reg;
+            reg++;
+        }
+    }
+    base->MAC_PMT_CRTL_STAT = ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK | ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK |
+                              ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK;
+
+    /* Enable the MAC rx. */
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK;
+}
+
+status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel)
+{
+    assert(handle);
+    assert(length);
+
+    enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel];
+    enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+    uint16_t index;
+
+    /* Reset the length to zero. */
+    *length = 0;
+
+    if (rxDesc->control & ENET_RXDESCRIP_WR_OWN_MASK)
+    {
+        return kStatus_ENET_RxFrameEmpty;
+    }
+    else
+    {
+        do
+        {
+            /* Application owns the buffer descriptor, get the length. */
+            if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK)
+            {
+                if (rxDesc->control & ENET_RXDESCRIP_WR_ERRSUM_MASK)
+                {
+                    return kStatus_ENET_RxFrameError;
+                }
+                *length = rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK;
+                return kStatus_Success;
+            }
+
+            index = ENET_IncreaseIndex(index, rxBdRing->rxRingLen);
+            rxDesc = rxBdRing->rxBdBase + index;
+        } while (index != rxBdRing->rxGenIdx);
+
+        return kStatus_ENET_RxFrameError;
+    }
+}
+
+status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel)
+{
+    assert(handle);
+
+    uint32_t len = 0;
+    uint32_t offset = 0;
+    uint32_t control;
+    bool isLastBuff = false;
+    enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel];
+    enet_rx_bd_struct_t *rxDesc;
+    status_t result = kStatus_Fail;
+    uint16_t index = rxBdRing->rxGenIdx;
+    bool suspend = false;
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    uint32_t buffer;
+    uint32_t bufferAdd;
+#endif /* ENET_PTP1588FEATURE_REQUIRED  */
+
+    /* Suspend and command for rx. */
+    if (base->DMA_CH[channel].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
+    {
+        suspend = true;
+    }
+
+    /* For data-NULL input, only update the buffer descriptor. */
+    if ((!data))
+    {
+        do
+        {
+            /* Get the control flag. */
+            rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+            rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+            control = rxDesc->control;
+            /* Updates the receive buffer descriptors. */
+            ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+
+            /* Find the last buffer descriptor for the frame. */
+            if (control & ENET_RXDESCRIP_WR_LD_MASK)
+            {
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+                /* Reinit for the context descritor which has been updated by DMA. */
+                rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+                if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK)
+                {
+                    if (!handle->doubleBuffEnable)
+                    {
+                        buffer = handle->rxbuffers[rxBdRing->rxGenIdx];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    else
+                    {
+                        buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx];
+                        bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+                }
+#endif /*  ENET_PTP1588FEATURE_REQUIRED */
+                break;
+            }
+        } while (rxBdRing->rxGenIdx != index);
+
+        result = kStatus_Success;
+    }
+    else
+    {
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+        enet_ptp_time_data_t ptpTsData;
+        bool ptp1588 = false;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+        while ((!isLastBuff))
+        {
+            /* The last buffer descriptor of a frame. */
+            rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+            rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+            if (rxDesc->control & ENET_RXDESCRIP_WR_FD_MASK)
+            {
+                ptp1588 = ENET_Ptp1588ParseFrame((uint8_t *)rxDesc->buff1Addr, &ptpTsData, false);
+            }
+#endif
+            if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK)
+            {
+                /* This is a valid frame. */
+                isLastBuff = true;
+                if (length == (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK))
+                {
+                    /* Copy the frame to user's buffer. */
+                    len = (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK) - offset;
+                    if (len > rxBdRing->rxBuffSizeAlign)
+                    {
+                        memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign);
+                        offset += rxBdRing->rxBuffSizeAlign;
+                        memcpy(data + offset, (void *)rxDesc->buff2Addr, len - rxBdRing->rxBuffSizeAlign);
+                    }
+                    else
+                    {
+                        memcpy(data + offset, (void *)rxDesc->buff1Addr, len);
+                    }
+
+                    result = kStatus_Success;
+                }
+
+                /* Updates the receive buffer descriptors. */
+                ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+                /* Store the rx timestamp which is in the next buffer descriptor of the last
+                 * descriptor of a frame. */
+                rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
+
+                /* Reinit for the context descritor which has been updated by DMA. */
+                if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK)
+                {
+                    if (ptp1588)
+                    {
+                        ENET_StoreRxFrameTime(base, handle, rxDesc, channel, &ptpTsData);
+                    }
+
+                    if (!handle->doubleBuffEnable)
+                    {
+                        buffer = handle->rxbuffers[rxBdRing->rxGenIdx];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    else
+                    {
+                        buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx];
+                        bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1];
+                        ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable,
+                                                handle->doubleBuffEnable);
+                    }
+                    rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
+                }
+                base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+            }
+            else
+            {
+                /* Store a frame on several buffer descriptors. */
+                isLastBuff = false;
+                /* Length check. */
+                if (offset >= length)
+                {
+                    /* Updates the receive buffer descriptors. */
+                    ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+                    break;
+                }
+
+                memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign);
+                offset += rxBdRing->rxBuffSizeAlign;
+                if ((rxDesc->buff2Addr) && (handle->doubleBuffEnable))
+                {
+                    memcpy(data + offset, (void *)rxDesc->buff2Addr, rxBdRing->rxBuffSizeAlign);
+                    offset += rxBdRing->rxBuffSizeAlign;
+                }
+
+                /* Updates the receive buffer descriptors. */
+                ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
+            }
+        }
+    }
+
+    /* Set command for rx when it is suspend. */
+    if (suspend)
+    {
+        base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR;
+    }
+
+    return result;
+}
+
+void ENET_UpdateRxDescriptor(
+    enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable)
+{
+    assert(rxDesc);
+    uint32_t control = ENET_RXDESCRIP_RD_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK;
+
+    if (intEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_IOC_MASK;
+    }
+
+    if (doubleBuffEnable)
+    {
+        control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK;
+    }
+
+    /* Update the buffer if needed. */
+    if (buffer1)
+    {
+        rxDesc->buff1Addr = (uint32_t)buffer1;
+    }
+    if (buffer2)
+    {
+        rxDesc->buff2Addr = (uint32_t)buffer2;
+    }
+    else
+    {
+        rxDesc->buff2Addr = 0;
+    }
+
+    rxDesc->reserved = 0;
+    rxDesc->control = control;
+}
+
+void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
+                            void *buffer1,
+                            uint32_t bytes1,
+                            void *buffer2,
+                            uint32_t bytes2,
+                            uint32_t framelen,
+                            bool intEnable,
+                            bool tsEnable,
+                            enet_desc_flag flag,
+                            uint8_t slotNum)
+{
+    uint32_t control = ENET_TXDESCRIP_RD_BL1(bytes1) | ENET_TXDESCRIP_RD_BL2(bytes2);
+
+    if (tsEnable)
+    {
+        control |= ENET_TXDESCRIP_RD_TTSE_MASK;
+    }
+    else
+    {
+        control &= ~ENET_TXDESCRIP_RD_TTSE_MASK;
+    }
+
+    if (intEnable)
+    {
+        control |= ENET_TXDESCRIP_RD_IOC_MASK;
+    }
+    else
+    {
+        control &= ~ENET_TXDESCRIP_RD_IOC_MASK;
+    }
+
+    /* Preare the descriptor for transmit. */
+    txDesc->buff1Addr = (uint32_t)buffer1;
+    txDesc->buff2Addr = (uint32_t)buffer2;
+    txDesc->buffLen = control;
+
+    control = ENET_TXDESCRIP_RD_FL(framelen) | ENET_TXDESCRIP_RD_LDFD(flag) | ENET_TXDESCRIP_RD_OWN_MASK;
+
+    txDesc->controlStat = control;
+}
+
+void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel)
+{
+    enet_tx_bd_ring_t *txBdRing = &handle->txBdRing[channel];
+    enet_tx_bd_struct_t *txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx;
+
+    /* Need to update the first index for transmit buffer free. */
+    while ((txBdRing->txDescUsed > 0) && (!(txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK)))
+    {
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+        uint32_t nanosecond;
+        uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */
+
+        if (txDesc->controlStat & ENET_TXDESCRIP_RD_LD_MASK)
+        {
+            enet_ptp_time_data_t *ptpTsData = txBdRing->txPtpTsDataRing.ptpTsData + txBdRing->txPtpTsDataRing.end;
+            if (txDesc->controlStat & ENET_TXDESCRIP_WB_TTSS_MASK)
+            {
+                /* Get transmit time stamp second. */
+                nanosecond = txDesc->buff2Addr | txDesc->buff1Addr;
+                if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
+                {
+                    /* Binary rollover. */
+                    nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
+                }
+                ptpTsData->timeStamp.second = nanosecond / nanoOverSize;
+                ptpTsData->timeStamp.nanosecond = nanosecond % nanoOverSize;
+
+                /* Store the timestamp to the transmit timestamp ring. */
+                ENET_Ptp1588UpdateTimeRing(&txBdRing->txPtpTsDataRing, ptpTsData);
+            }
+        }
+#endif  /* ENET_PTP1588FEATURE_REQUIRED */
+
+        /* For tx buffer free or requeue for each descriptor.
+         * The tx interrupt callback should free/requeue the tx buffer. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kENET_TxIntEvent, channel, handle->userData);
+        }
+
+        txBdRing->txDescUsed--;
+
+        /* Update the txConsumIdx/txDesc. */
+        txBdRing->txConsumIdx = ENET_IncreaseIndex(txBdRing->txConsumIdx, txBdRing->txRingLen);
+        txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx;
+    }
+}
+
+status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length)
+{
+    assert(handle);
+    assert(data);
+
+    enet_tx_bd_ring_t *txBdRing;
+    enet_tx_bd_struct_t *txDesc;
+    uint8_t channel = 0;
+    bool ptp1588 = false;
+
+    if (length > 2 * ENET_TXDESCRIP_RD_BL1_MASK)
+    {
+        return kStatus_ENET_TxFrameOverLen;
+    }
+
+    /* Choose the transit queue. */
+    channel = ENET_GetTxRingId(data, handle);
+
+    /* Check if the DMA owns the descriptor. */
+    txBdRing = (enet_tx_bd_ring_t *)&handle->txBdRing[channel];
+    txDesc = txBdRing->txBdBase + txBdRing->txGenIdx;
+    if (txBdRing->txRingLen == txBdRing->txDescUsed)
+    {
+        return kStatus_ENET_TxFrameBusy;
+    }
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_time_data_t ptpTsData;
+
+    ptp1588 = ENET_Ptp1588ParseFrame(data, &ptpTsData, true);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+    /* Fill the descriptor. */
+    if (length <= ENET_TXDESCRIP_RD_BL1_MASK)
+    {
+        ENET_SetupTxDescriptor(txDesc, data, length, NULL, 0, length, true, ptp1588, kENET_FirstLastFlag, 0);
+    }
+    else
+    {
+        ENET_SetupTxDescriptor(txDesc, data, ENET_TXDESCRIP_RD_BL1_MASK, data + ENET_TXDESCRIP_RD_BL1_MASK,
+                               (length - ENET_TXDESCRIP_RD_BL1_MASK), length, true, ptp1588, kENET_FirstLastFlag, 0);
+    }
+
+    /* Increase the index. */
+    txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen);
+    /* Disable interrupt first and then enable interrupt to avoid the race condition. */
+    DisableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
+    txBdRing->txDescUsed++;
+    EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]);
+
+    /* Update the transmit tail address. */
+    txDesc = txBdRing->txBdBase + txBdRing->txGenIdx;
+    if (!txBdRing->txGenIdx)
+    {
+        txDesc = txBdRing->txBdBase + txBdRing->txRingLen;
+    }
+    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = (uint32_t)txDesc & ~ENET_ADDR_ALIGNMENT;
+
+    return kStatus_Success;
+}
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond)
+{
+    assert(second);
+    assert(nanosecond);
+
+    uint32_t primask;
+
+    /* Disables the interrupt. */
+    primask = DisableGlobalIRQ();
+
+    /* Get the current PTP time. */
+    *second = ((uint64_t)(base->MAC_SYS_TIME_HWORD_SCND & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) << 32U) |
+              base->MAC_SYS_TIME_SCND;
+    *nanosecond = base->MAC_SYS_TIME_NSCND & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK;
+    if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK))
+    {
+        /* Binary rollover, the unit of the increment is ~ 0.466 ns. */
+        *nanosecond = *nanosecond / 1000U * 466U;
+    }
+
+    /* Enables the interrupt. */
+    EnableGlobalIRQ(primask);
+}
+
+void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond)
+{
+    uint32_t corrSecond = second;
+    uint32_t corrNanosecond;
+
+    /* Set the system timer. */
+    if (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
+    {
+        if (operation == kENET_SystimeSubtract)
+        {
+            /* Set with the complement of the sub-second. */
+            corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1);
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK |
+                             ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_NANOSECS_ONESECOND - nanosecond);
+        }
+        else
+        {
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond);
+        }
+    }
+    else
+    {
+        nanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK / ENET_NANOSECS_ONESECOND * nanosecond;
+        if (operation == kENET_SystimeSubtract)
+        {
+            /* Set with the complement of the sub-second. */
+            corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1);
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK |
+                             ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK + 1 - nanosecond);
+        }
+        else
+        {
+            corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond);
+        }
+    }
+
+    base->MAC_SYS_TIME_SCND_UPD = corrSecond;
+    base->MAC_SYS_TIME_NSCND_UPD = corrNanosecond;
+
+    /* Update the timer. */
+    base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK;
+    while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
+        ;
+}
+
+status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(handle);
+    assert(ptpTimeData);
+
+    uint32_t result = kStatus_Success;
+    uint8_t count;
+    uint8_t index = handle->multiQueEnable ? 2 : 1;
+
+    for (count = 0; count < index; count++)
+    {
+        result = ENET_Ptp1588SearchTimeRing(&handle->txBdRing[count].txPtpTsDataRing, ptpTimeData);
+        if (result == kStatus_Success)
+        {
+            break;
+        }
+    }
+
+    return result;
+}
+
+status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData)
+{
+    assert(handle);
+    assert(ptpTimeData);
+
+    uint32_t result = kStatus_Success;
+    uint8_t count;
+    uint8_t index = handle->multiQueEnable ? 2 : 1;
+
+    for (count = 0; count < index; count++)
+    {
+        result = ENET_Ptp1588SearchTimeRing(&handle->rxBdRing[count].rxPtpTsDataRing, ptpTimeData);
+        if (result == kStatus_Success)
+        {
+            break;
+        }
+    }
+
+    return result;
+}
+
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle)
+{
+    /* Check for the interrupt source type. */
+    /* DMA CHANNEL 0. */
+    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC0IS_MASK)
+    {
+        uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT;
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+        {
+            base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kENET_RxIntEvent, 0, handle->userData);
+            }
+        }
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+        {
+            base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            ENET_ReclaimTxDescriptor(base, handle, 0);
+        }
+    }
+
+    /* DMA CHANNEL 1. */
+    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC1IS_MASK)
+    {
+        uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT;
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+        {
+            base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kENET_RxIntEvent, 1, handle->userData);
+            }
+        }
+        if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+        {
+            base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK;
+            ENET_ReclaimTxDescriptor(base, handle, 1);
+        }
+    }
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    /* MAC TIMESTAMP. */
+    if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_MACIS_MASK)
+    {
+        if (base->MAC_INTR_STAT & ENET_MAC_INTR_STAT_TSIS_MASK)
+        {
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kENET_TimeStampIntEvent, 0, handle->userData);
+            }
+        }
+    }
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+}
+
+void ETHERNET_DriverIRQHandler(void)
+{
+    s_enetIsr(ENET, s_ENETHandle[0]);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1178 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_ENET_H_
+#define _FSL_ENET_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_enet
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines the driver version. */
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+/*! @name Control and status region bit masks of the receive buffer descriptor. */
+/*@{*/
+/*! @brief Defines for read format. */
+#define ENET_RXDESCRIP_RD_BUFF1VALID_MASK (1U << 24) /*!< Buffer1 address valid. */
+#define ENET_RXDESCRIP_RD_BUFF2VALID_MASK (1U << 25) /*!< Buffer2 address valid. */
+#define ENET_RXDESCRIP_RD_IOC_MASK (1U << 30)        /*!< Interrupt enable on complete. */
+#define ENET_RXDESCRIP_RD_OWN_MASK (1U << 31)        /*!< Own bit. */
+
+/*! @brief Defines for write back format. */
+#define ENET_RXDESCRIP_WR_ERR_MASK ((1U << 3) | (1U << 7))
+#define ENET_RXDESCRIP_WR_PYLOAD_MASK (0x7U)
+#define ENET_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00U)
+#define ENET_RXDESCRIP_WR_PTPTYPE_MASK (1U << 12)
+#define ENET_RXDESCRIP_WR_PTPVERSION_MASK (1U << 13)
+#define ENET_RXDESCRIP_WR_PTPTSA_MASK (1U << 14)
+#define ENET_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFU)
+#define ENET_RXDESCRIP_WR_ERRSUM_MASK (1U << 15)
+#define ENET_RXDESCRIP_WR_TYPE_MASK (0x30000U)
+#define ENET_RXDESCRIP_WR_DE_MASK (1U << 19)
+#define ENET_RXDESCRIP_WR_RE_MASK (1U << 20)
+#define ENET_RXDESCRIP_WR_OE_MASK (1U << 21)
+#define ENET_RXDESCRIP_WR_RS0V_MASK (1U << 25)
+#define ENET_RXDESCRIP_WR_RS1V_MASK (1U << 26)
+#define ENET_RXDESCRIP_WR_RS2V_MASK (1U << 27)
+#define ENET_RXDESCRIP_WR_LD_MASK (1U << 28)
+#define ENET_RXDESCRIP_WR_FD_MASK (1U << 29)
+#define ENET_RXDESCRIP_WR_CTXT_MASK (1U << 30)
+#define ENET_RXDESCRIP_WR_OWN_MASK (1U << 31)
+/*@}*/
+
+/*! @name Control and status bit masks of the transmit buffer descriptor. */
+/*@{*/
+/*! @brief Defines for read format. */
+#define ENET_TXDESCRIP_RD_BL1_MASK (0x3fffU)
+#define ENET_TXDESCRIP_RD_BL2_MASK (ENET_TXDESCRIP_RD_BL1_MASK << 16)
+#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK)
+#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16)
+#define ENET_TXDESCRIP_RD_TTSE_MASK (1U << 30)
+#define ENET_TXDESCRIP_RD_IOC_MASK (1U << 31)
+
+#define ENET_TXDESCRIP_RD_FL_MASK (0x7FFFU)
+#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK)
+#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3) << 16)
+#define ENET_TXDESCRIP_RD_TSE_MASK (1U << 18)
+#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0f) << 19)
+#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07) << 23)
+#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03) << 26)
+#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03) << 28)
+#define ENET_TXDESCRIP_RD_LD_MASK (1U << 28)
+#define ENET_TXDESCRIP_RD_FD_MASK (1U << 29)
+#define ENET_TXDESCRIP_RD_CTXT_MASK (1U << 30)
+#define ENET_TXDESCRIP_RD_OWN_MASK (1UL << 31)
+
+/*! @brief Defines for write back format. */
+#define ENET_TXDESCRIP_WB_TTSS_MASK (1UL << 17)
+/*@}*/
+
+/*! @name Bit mask for interrupt enable type. */
+/*@{*/
+#define ENET_ABNORM_INT_MASK                                                      \
+    (ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK | \
+     ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK | \
+     ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
+#define ENET_NORM_INT_MASK                                                        \
+    (ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK | \
+     ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
+/*@}*/
+
+/*! @name Defines some Ethernet parameters. */
+/*@{*/
+
+#define ENET_FRAME_MAX_FRAMELEN (1518U)/*!< Default maximum Ethernet frame size. */
+#define ENET_ADDR_ALIGNMENT (0x3U)     /*!< Recommended ethernet buffer alignment. */
+#define ENET_BUFF_ALIGNMENT (4U)       /*!< Receive buffer alignment shall be 4bytes-aligned. */
+#define ENET_RING_NUM_MAX (2U)         /*!< The Maximum number of tx/rx descriptor rings. */
+#define ENET_MTL_RXFIFOSIZE (2048U)    /*!< The rx fifo size. */
+#define ENET_MTL_TXFIFOSIZE (2048U)    /*!< The tx fifo size. */
+#define ENET_MACINT_ENUM_OFFSET (16U)  /*!< The offest for mac interrupt in enum type. */
+/*@}*/
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/* Define the buffer length to store the rx buffers address.
+ * because the context descriptor will be updated for store the time
+ * stamp for rx frame. so we need to reinit the descriptors.
+ * This macro shall at least equal to the rxRingLen
+ * assigned in the enet_buffer_config. That means if the rx descriptor
+ * length is larger than 5, please increse this macro.  */
+#define ENET_RXBUFFSTORE_NUM (6)
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+/*! @brief Defines the status return codes for transaction. */
+enum _enet_status
+{
+    kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U),  /*!< A frame received but data error happen. */
+    kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U),   /*!< Failed to receive a frame. */
+    kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U),  /*!< No frame arrive. */
+    kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 3U),   /*!< Transmit descriptors are under process. */
+    kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U),   /*!< Transmit frame fail. */
+    kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit oversize. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    ,
+    kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */
+    kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */
+#endif                                                               /* ENET_PTP1588FEATURE_REQUIRED */
+};
+
+/*! @brief Defines the MII/RMII mode for data interface between the MAC and the PHY. */
+typedef enum _enet_mii_mode {
+    kENET_MiiMode = 0U, /*!< MII mode for data interface. */
+    kENET_RmiiMode = 1U /*!< RMII mode for data interface. */
+} enet_mii_mode_t;
+
+/*! @brief Defines the 10/100 Mbps speed for the MII data interface. */
+typedef enum _enet_mii_speed {
+    kENET_MiiSpeed10M = 0U,  /*!< Speed 10 Mbps. */
+    kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */
+} enet_mii_speed_t;
+
+/*! @brief Defines the half or full duplex for the MII data interface. */
+typedef enum _enet_mii_duplex {
+    kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
+    kENET_MiiFullDuplex       /*!< Full duplex mode. */
+} enet_mii_duplex_t;
+
+/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
+typedef enum _enet_mii_normal_opcode {
+    kENET_MiiWriteFrame = 1U, /*!< Write frame operation for a valid MII management frame. */
+    kENET_MiiReadFrame = 3U   /*!< Read frame operation for a valid MII management frame. */
+} enet_mii_normal_opcode;
+
+/*! @brief Define the DMA maximum transmit burst length. */
+typedef enum _enet_dma_burstlen {
+    kENET_BurstLen1 = 0x00001U,   /*!< DMA burst length 1. */
+    kENET_BurstLen2 = 0x00002U,   /*!< DMA burst length 2. */
+    kENET_BurstLen4 = 0x00004U,   /*!< DMA burst length 4. */
+    kENET_BurstLen8 = 0x00008U,   /*!< DMA burst length 8. */
+    kENET_BurstLen16 = 0x00010U,  /*!< DMA burst length 16. */
+    kENET_BurstLen32 = 0x00020U,  /*!< DMA burst length 32. */
+    kENET_BurstLen64 = 0x10008U,  /*!< DMA burst length 64. eight times enabled. */
+    kENET_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */
+    kENET_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */
+} enet_dma_burstlen;
+
+/*! @brief Define the flag for the descriptor. */
+typedef enum _enet_desc_flag {
+    kENET_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */
+    kENET_FirstFlagOnly,  /*!< It's the first descriptor of the frame. */
+    kENET_LastFlagOnly,   /*!< It's the last descriptor of the frame. */
+    kENET_FirstLastFlag   /*!< It's the first and last descriptor of the frame. */
+} enet_desc_flag;
+
+/*! @brief Define the system time adjust operation control. */
+typedef enum _enet_systime_op {
+    kENET_SystimeAdd = 0U,     /*!< System time add to. */
+    kENET_SystimeSubtract = 1U /*!< System time subtract. */
+} enet_systime_op;
+
+/*! @brief Define the system time rollover control. */
+typedef enum _enet_ts_rollover_type {
+    kENET_BinaryRollover = 0, /*!< System time binary rollover.*/
+    kENET_DigitalRollover = 1 /*!< System time digital rollover.*/
+} enet_ts_rollover_type;
+
+/*! @brief Defines some special configuration for ENET.
+ *
+ * These control flags are provided for special user requirements.
+ * Normally, these is no need to set this control flags for ENET initialization.
+ * But if you have some special requirements, set the flags to specialControl
+ * in the enet_config_t.
+ * @note "kENET_StoreAndForward" is recommended to be set when the
+ * ENET_PTP1588FEATURE_REQUIRED is defined or else the timestamp will be mess-up
+ * when the overflow happens.
+ */
+typedef enum _enet_special_config {
+
+    /***********************DMA CONFGI**********************************************/
+    kENET_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */
+    /**************************MTL************************************/
+    kENET_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */
+    /***********************MAC****************************************/
+    kENET_PromiscuousEnable = 0x0004U,  /*!< The promiscuous enabled. */
+    kENET_FlowControlEnable = 0x0008U,  /*!< The flow control enabled. */
+    kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
+    kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
+    kENET_8023AS2KPacket = 0x0040U      /*!< 8023as support for 2K packets. */
+} enet_special_config_t;
+
+/*! @brief List of DMA interrupts supported by the ENET interrupt. This
+ * enumeration uses one-bot encoding to allow a logical OR of multiple
+ * members.
+ */
+typedef enum _enet_dma_interrupt_enable {
+    kENET_DmaTx = ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK,                 /*!< Tx interrupt. */
+    kENET_DmaTxStop = ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK,             /*!< Tx stop interrupt. */
+    kENET_DmaTxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK,     /*!< Tx buffer unavailable. */
+    kENET_DmaRx = ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK,                 /*!< Rx interrupt. */
+    kENET_DmaRxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK,     /*!< Rx buffer unavailable. */
+    kENET_DmaRxStop = ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK,             /*!< Rx stop. */
+    kENET_DmaRxWatchdogTimeout = ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */
+    kENET_DmaEarlyTx = ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK,           /*!< Early transmit. */
+    kENET_DmaEarlyRx = ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK,           /*!< Early receive. */
+    kENET_DmaBusErr = ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK,            /*!< Fatal bus error. */
+} enet_dma_interrupt_enable_t;
+
+/*! @brief List of mac interrupts supported by the ENET interrupt. This
+ * enumeration uses one-bot encoding to allow a logical OR of multiple
+ * members.
+ */
+typedef enum _enet_mac_interrupt_enable {
+    kENET_MacPmt = (ENET_MAC_INTR_EN_PMTIE_MASK << ENET_MACINT_ENUM_OFFSET),
+    kENET_MacTimestamp = (ENET_MAC_INTR_EN_TSIE_MASK << ENET_MACINT_ENUM_OFFSET),
+} enet_mac_interrupt_enable_t;
+
+/*! @brief Defines the common interrupt event for callback use. */
+typedef enum _enet_event {
+    kENET_RxIntEvent,     /*!< Receive interrupt event. */
+    kENET_TxIntEvent,     /*!< Transmit interrupt event. */
+    kENET_WakeUpIntEvent, /*!< Wake up interrupt event. */
+    kENET_TimeStampIntEvent, /*!< Time stamp interrupt event. */
+} enet_event_t;
+
+/*! @brief Define the DMA transmit arbitration for multi-queue. */
+typedef enum _enet_dma_tx_sche {
+    kENET_FixPri = 0,      /*!< Fixed priority. channel 0 has lower priority than channel 1. */
+    kENET_WeightStrPri,    /*!< Weighted(burst length) strict priority. */
+    kENET_WeightRoundRobin /*!< Weighted (weight factor) round robin. */
+} enet_dma_tx_sche;
+
+/*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */
+typedef enum _enet_mtl_multiqueue_txsche {
+    kENET_txWeightRR = 0U, /*!< Tx weight round-robin. */
+    kENET_txStrPrio = 3U,  /*!< Tx strict priority. */
+} enet_mtl_multiqueue_txsche;
+
+/*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */
+typedef enum _enet_mtl_multiqueue_rxsche {
+    kENET_rxStrPrio = 0U,  /*!< Tx weight round-robin, rx strict priority. */
+    kENET_rxWeightStrPrio, /*!< Tx strict priority, rx weight strict priority. */
+} enet_mtl_multiqueue_rxsche;
+
+/*! @brief Define the MTL rx queue and DMA channel mapping. */
+typedef enum _enet_mtl_rxqueuemap {
+    kENET_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) direclty map to dma channel n. */
+    kENET_DynamicMap =
+        0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.
+                    */
+} enet_mtl_rxqueuemap;
+
+/*! @brief Defines the ENET PTP message related constant. */
+typedef enum _enet_ptp_event_type {
+    kENET_PtpEventMsgType = 3U,  /*!< PTP event message type. */
+    kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
+    kENET_PtpEventPort = 319U,   /*!< PTP event port number. */
+    kENET_PtpGnrlPort = 320U     /*!< PTP general port number. */
+} enet_ptp_event_type_t;
+
+/*! @brief Defines the receive descriptor structure
+ *  has the read-format and write-back format structure. They both
+ *  has the same size with different region definition. so
+ *  we define the read-format region as the recive descriptor structure
+ *  Use the read-format region mask bits in the descriptor initialization
+ *  Use the write-back format region mask bits in the receive data process.
+ */
+typedef struct _enet_rx_bd_struct
+{
+    __IO uint32_t buff1Addr; /*!< Buffer 1 address */
+    __IO uint32_t reserved;  /*!< Reserved */
+    __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */
+    __IO uint32_t control;   /*!< Buffer 1/2 byte counts and control */
+} enet_rx_bd_struct_t;
+
+/*! @brief Defines the transmit descriptor structure
+ *  has the read-format and write-back format structure. They both
+ *  has the same size with different region definition. so
+ *  we define the read-format region as the transmit descriptor structure
+ *  Use the read-format region mask bits in the descriptor initialization
+ *  Use the write-back format region mask bits in the transmit data process.
+ */
+typedef struct _enet_tx_bd_struct
+{
+    __IO uint32_t buff1Addr;   /*!< Buffer 1 address */
+    __IO uint32_t buff2Addr;   /*!< Buffer 2 address */
+    __IO uint32_t buffLen;     /*!< Buffer 1/2 byte counts */
+    __IO uint32_t controlStat; /*!< TDES control and status word */
+} enet_tx_bd_struct_t;
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/*! @brief Defines the ENET PTP time stamp structure. */
+typedef struct _enet_ptp_time
+{
+    uint64_t second;     /*!< Second. */
+    uint32_t nanosecond; /*!< Nanosecond. */
+} enet_ptp_time_t;
+
+/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/
+typedef struct _enet_ptp_time_data
+{
+    uint8_t version;                             /*!< PTP version. */
+    uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */
+    uint16_t sequenceId;                         /*!< PTP sequence ID. */
+    uint8_t messageType;                         /*!< PTP message type. */
+    enet_ptp_time_t timeStamp;                   /*!< PTP timestamp. */
+} enet_ptp_time_data_t;
+
+/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/
+typedef struct _enet_ptp_time_data_ring
+{
+    uint32_t front;                  /*!< The first index of the ring. */
+    uint32_t end;                    /*!< The end index of the ring. */
+    uint32_t size;                   /*!< The size of the ring. */
+    enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */
+} enet_ptp_time_data_ring_t;
+
+/*! @brief Defines the ENET PTP configuration structure. */
+typedef struct _enet_ptp_config
+{
+    bool fineUpdateEnable;            /*!< Use the fine update. */
+    bool ptp1588V2Enable;             /*!< ptp 1588 version 2 is used. */
+    enet_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */
+} enet_ptp_config_t;
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+
+/*! @brief Defines the buffer descriptor configure structure.
+ *
+ * Notes:
+ * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
+ * 2. The recommended minimum tx/rx ring length is 4.
+ * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end
+ *    of the last last descriptor. because only the descriptors between the start address and the
+ *    tail address will be used by DMA.
+ * 4. The decriptor address is the start address of all used contiguous memory.
+ *    for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memorise
+ *    for rx descriptor ring 0.
+ * 5. The "*rxBufferstartAddr" is the first element of  rxRingLen (2*rxRingLen for double buffers)
+ *    rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor
+ *    the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for
+ *    the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the
+ *    address of a rxRingLen or 2*rxRingLen array.
+ */
+typedef struct _enet_buffer_config
+{
+    uint8_t rxRingLen;                         /*!< The length of receive buffer descriptor ring. */
+    uint8_t txRingLen;                         /*!< The length of transmit buffer descriptor ring. */
+    enet_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */
+    enet_tx_bd_struct_t *txDescTailAddrAlign;  /*!< Aligned transmit descriptor tail address. */
+    enet_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */
+    enet_rx_bd_struct_t *rxDescTailAddrAlign;  /*!< Aligned receive descriptor tail address. */
+    uint32_t *rxBufferStartAddr;               /*!< Start address of the rx buffers. */
+    uint32_t rxBuffSizeAlign;                  /*!< Aligned receive data buffer size. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    uint8_t ptpTsRxBuffNum;            /*!< Receive 1588 timestamp buffer number*/
+    uint8_t ptpTsTxBuffNum;            /*!< Transmit 1588 timestamp buffer number*/
+    enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */
+    enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */
+#endif                                 /* ENET_PTP1588FEATURE_REQUIRED */
+} enet_buffer_config_t;
+
+/*! @brief Defines the configuration when multi-queue is used. */
+typedef struct enet_multiqueue_config
+{
+    /***********************DMA block*******************************/
+    enet_dma_tx_sche dmaTxSche;                /*!< Transmit arbitation. */
+    enet_dma_burstlen burstLen;                /*!< Burset len for the queue 1. */
+    uint8_t txdmaChnWeight[ENET_RING_NUM_MAX]; /*!< Transmit channel weight. */
+    /***********************MTL block*******************************/
+    enet_mtl_multiqueue_txsche mtltxSche;    /*!< Transmit schedule for multi-queue. */
+    enet_mtl_multiqueue_rxsche mtlrxSche;    /*!< Receive schedule for multi-queue. */
+    uint8_t rxqueweight[ENET_RING_NUM_MAX];  /*!< Refer to the MTL RxQ Control register. */
+    uint32_t txqueweight[ENET_RING_NUM_MAX]; /*!< Refer to the MTL TxQ Quantum Weight register. */
+    uint8_t rxqueuePrio[ENET_RING_NUM_MAX];  /*!< Receive queue priority. */
+    uint8_t txqueuePrio[ENET_RING_NUM_MAX];  /*!< Refer to Transmit Queue Priority Mapping register. */
+    enet_mtl_rxqueuemap mtlrxQuemap;         /*!< Rx queue DMA Channel mapping. */
+} enet_multiqueue_config_t;
+
+/*! @brief Defines the basic configuration structure for the ENET device.
+ *
+ * Note:
+ *  1. Default the signal queue is used so the "*multiqueueCfg" is set default
+ *  with NULL. Set the pointer with a valid configration pointer if the multiple
+ *  queues are required. If multiple queue is enabled, please make sure the
+ *  buffer configuration for all are prepared also.
+ */
+typedef struct _enet_config
+{
+    uint16_t specialControl;                 /*!< The logicl or of enet_special_config_t */
+    enet_multiqueue_config_t *multiqueueCfg; /*!< Use both tx/rx queue(dma channel) 0 and 1. */
+    /* -----------------MAC block-------------------------------*/
+    enet_mii_mode_t miiMode;     /*!< MII mode. */
+    enet_mii_speed_t miiSpeed;   /*!< MII Speed. */
+    enet_mii_duplex_t miiDuplex; /*!< MII duplex. */
+    uint16_t pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_FlowControlEnable is set. */
+/* -----------------Timestamp -------------------------------*/
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */
+#endif                            /* ENET_PTP1588FEATURE_REQUIRED */
+} enet_config_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _enet_handle enet_handle_t;
+
+/*! @brief ENET callback function. */
+typedef void (*enet_callback_t)(
+    ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *userData);
+
+/*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */
+typedef struct _enet_tx_bd_ring
+{
+    enet_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */
+    uint16_t txGenIdx;             /*!< tx generate index. */
+    uint16_t txConsumIdx;          /*!< tx consum index. */
+    volatile uint16_t txDescUsed;  /*!< tx descriptor used number. */
+    uint16_t txRingLen;            /*!< tx ring length. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */
+#endif                                         /* ENET_PTP1588FEATURE_REQUIRED */
+} enet_tx_bd_ring_t;
+
+/*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */
+typedef struct _enet_rx_bd_ring
+{
+    enet_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */
+    uint16_t rxGenIdx;             /*!< The current available receive buffer descriptor pointer. */
+    uint16_t rxRingLen;            /*!< Receive ring length. */
+    uint32_t rxBuffSizeAlign;      /*!< Receive buffer size. */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */
+#endif                                         /* ENET_PTP1588FEATURE_REQUIRED*/
+} enet_rx_bd_ring_t;
+
+/*! @brief Defines the ENET handler structure. */
+struct _enet_handle
+{
+    bool multiQueEnable;                           /*!< Enable multi-queue. */
+    bool doubleBuffEnable;                         /*!< The double buffer is used in the descriptor. */
+    bool rxintEnable;                              /*!< Rx interrup enabled. */
+    enet_rx_bd_ring_t rxBdRing[ENET_RING_NUM_MAX]; /*!< Receive buffer descriptor.  */
+    enet_tx_bd_ring_t txBdRing[ENET_RING_NUM_MAX]; /*!< Transmit buffer descriptor.  */
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+    uint32_t rxbuffers[ENET_RXBUFFSTORE_NUM]; /*!< The Initi-rx buffers will be used for reInitialize. */
+#endif
+    enet_callback_t callback; /*!< Callback function. */
+    void *userData;           /*!< Callback function parameter.*/
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+  * @name Initialization and De-initialization
+  * @{
+  */
+
+/*!
+ * @brief Gets the ENET default configuration structure.
+ *
+ * The purpose of this API is to get the default ENET configure
+ * structure for ENET_Init(). User may use the initialized
+ * structure unchanged in ENET_Init(), or modify some fields of the
+ * structure before calling ENET_Init().
+ * Example:
+   @code
+   enet_config_t config;
+   ENET_GetDefaultConfig(&config);
+   @endcode
+ * @param config The ENET mac controller configuration structure pointer.
+ */
+void ENET_GetDefaultConfig(enet_config_t *config);
+
+/*!
+ * @brief Initializes the ENET module.
+ *
+ * This function ungates the module clock and initializes it with the ENET basic
+ * configuration.
+ *
+ * @param base    ENET peripheral base address.
+ * @param config  ENET mac configuration structure pointer.
+ *        The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig
+ *        can be used directly. It is also possible to verify the Mac configuration using other methods.
+ * @param macAddr  ENET mac address of Ethernet device. This MAC address should be
+ *        provided.
+ * @param refclkSrc_Hz ENET input reference clock.
+ */
+void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz);
+
+/*!
+ * @brief Deinitializes the ENET module.
+
+ * This function gates the module clock and disables the ENET module.
+ *
+ * @param base  ENET peripheral base address.
+ */
+void ENET_Deinit(ENET_Type *base);
+
+/*!
+ * @brief Initialize for all ENET descriptors.
+ *
+ * @note This function is do all tx/rx descriptors initialization. Because this API 
+ *  read all interrupt registers first and then set the interrupt flag for all descriptos, 
+ * if the interrupt register is set. so the descriptor initialization should be called
+ * after ENET_Init(), ENET_EnableInterrupts() and ENET_CreateHandle()(if transactional APIs
+ * are used).
+ *
+ * @param base  ENET peripheral base address.
+ * @param config The configuration for ENET.
+ * @param bufferConfig All buffers configuration.
+ */
+status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig);
+
+/*!
+ * @brief Starts the ENET rx/tx.
+ *  This function enable the tx/rx and starts the rx/tx DMA.
+ * This shall be set after ENET initialization and before
+ * starting to receive the data.
+ *
+ * @param base  ENET peripheral base address.
+ * @param rxRingNum  The number of the used rx rings. It shall not be
+ * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with
+ * 1, the ring 0 will be used.
+ * @param txRingNum  The number of the used tx rings. It shall not be
+ * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with
+ * 1, the ring 0 will be used.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ */
+void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum);
+
+/* @} */
+
+/*!
+ * @name MII interface operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the ENET MII speed and duplex.
+ *
+ * This API is provided to dynamically change the speed and dulpex for MAC.
+ *
+ * @param base  ENET peripheral base address.
+ * @param speed The speed of the RMII mode.
+ * @param duplex The duplex of the RMII mode.
+ */
+static inline void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex)
+{
+    uint32_t reg = base->MAC_CONFIG & ~(ENET_MAC_CONFIG_DM_MASK | ENET_MAC_CONFIG_FES_MASK);
+    reg |= ENET_MAC_CONFIG_DM(duplex) | ENET_MAC_CONFIG_FES(speed);
+
+    base->MAC_CONFIG = reg;
+}
+
+/*!
+ * @brief Sets the ENET SMI(serial management interface)- MII management interface.
+ *
+ * @param base  ENET peripheral base address.
+ */
+void ENET_SetSMI(ENET_Type *base);
+
+/*!
+ * @brief Checks if the SMI is busy.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The status of MII Busy status.
+ */
+static inline bool ENET_IsSMIBusy(ENET_Type *base)
+{
+    return (base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_MB_MASK) ? true : false;
+}
+
+/*!
+ * @brief Reads data from the PHY register through SMI interface.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The data read from PHY
+ */
+static inline uint16_t ENET_ReadSMIData(ENET_Type *base)
+{
+    return (uint16_t)(base->MAC_MDIO_DATA & ENET_MAC_MDIO_DATA_MD_MASK);
+}
+
+/*!
+ * @brief Starts an SMI read command.
+ * support both MDIO IEEE802.3 Clause 22 and clause 45.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ */
+void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg);
+
+/*!
+ * @brief Starts a SMI write command.
+ * support both MDIO IEEE802.3 Clause 22 and clause 45.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param data The data written to PHY.
+ */
+void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+/* @} */
+
+/*!
+ * @name Other basic operation
+ * @{
+ */
+
+/*!
+ * @brief Sets the ENET module Mac address.
+ *
+ * @param base  ENET peripheral base address.
+ * @param macAddr The six-byte Mac address pointer.
+ *        The pointer is allocated by application and input into the API.
+ */
+static inline void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr)
+{
+    assert(macAddr);
+
+    /* Set Macaddr */
+    base->MAC_ADDR_LOW = ((uint32_t)macAddr[3] << 24) | ((uint32_t)macAddr[2] << 16) | ((uint32_t)macAddr[1] << 8) |
+                         ((uint32_t)macAddr[0]);
+    base->MAC_ADDR_HIGH = ((uint32_t)macAddr[5] << 8) | ((uint32_t)macAddr[4]);
+}
+
+/*!
+ * @brief Gets the ENET module Mac address.
+ *
+ * @param base  ENET peripheral base address.
+ * @param macAddr The six-byte Mac address pointer.
+ *        The pointer is allocated by application and input into the API.
+ */
+void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr);
+
+/*!
+ * @brief Set the MAC to enter into power down mode.
+ * the remote power wake up frame and magic frame can wake up
+ * the ENET from the power down mode.
+ *
+ * @param base    ENET peripheral base address.
+ * @param wakeFilter  The wakeFilter provided to configure the wake up frame fitlter.
+ *  Set the wakeFilter to NULL is not required. But if you have the filter requirement,
+ *  please make sure the wakeFilter pointer shall be eight continous
+ *  32-bits configuration.
+ */
+void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter);
+
+/*!
+ * @brief Set the MAC to exit power down mode.
+ * Eixt from the power down mode and recover to noraml work mode.
+ *
+ * @param base    ENET peripheral base address.
+ */
+static inline void ENET_ExitPowerDown(ENET_Type *base)
+{
+    /* Clear and status ans reset the power down. */
+    base->MAC_PMT_CRTL_STAT &= ~ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK;
+
+    /* Restore the tx which is disabled when enter power down mode. */
+    base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK;
+    base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts.
+ * @{
+ */
+
+/*!
+ * @brief Enables the ENET DMA and MAC interrupts.
+ *
+ * This function enables the ENET interrupt according to the provided mask. The mask
+ * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ * For example, to enable the dma and mac interrupt, do the following.
+ * @code
+ *     ENET_EnableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt);
+ * @endcode
+ *
+ * @param base  ENET peripheral base address.
+ * @param mask  ENET interrupts to enable. This is a logical OR of both 
+ *             enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ */
+void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the ENET DMA and MAC interrupts.
+ *
+ * This function disables the ENET interrupt according to the provided mask. The mask
+ * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ * For example, to disable the dma and mac interrupt, do the following.
+ * @code
+ *     ENET_DisableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt);
+ * @endcode
+ *
+ * @param base  ENET peripheral base address.
+ * @param mask  ENET interrupts to disables. This is a logical OR of both 
+ *             enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t.
+ */
+void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask);
+    
+/*!
+ * @brief Gets the ENET DMA interrupt status flag.
+ *
+ * @param base  ENET peripheral base address.
+ * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX.
+ * @return The event status of the interrupt source. This is the logical OR of members
+ *         of the enumeration :: enet_dma_interrupt_enable_t.
+ */
+static inline uint32_t ENET_GetDmaInterruptStatus(ENET_Type *base, uint8_t channel)
+{
+    return base->DMA_CH[channel].DMA_CHX_STAT;
+}
+
+/*!
+ * @brief Clear the ENET DMA interrupt status flag.
+ *
+ * @param base  ENET peripheral base address.
+ * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX.
+ * @return The event status of the interrupt source. This is the logical OR of members
+ *         of the enumeration :: enet_dma_interrupt_enable_t.
+ */
+static inline void ENET_ClearDmaInterruptStatus(ENET_Type *base, uint8_t channel, uint32_t mask)
+{
+    /* Clear the dam interrupt status bit in dma channel interrupt status register. */
+    base->DMA_CH[channel].DMA_CHX_STAT = mask;
+}
+
+/*!
+ * @brief Gets the ENET MAC interrupt status flag.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The event status of the interrupt source. 
+ *       Use the enum in enet_mac_interrupt_enable_t and right shift
+ *       ENET_MACINT_ENUM_OFFSET to mask the returned value to get the 
+ *       exact interrupt status.
+ */
+static inline uint32_t ENET_GetMacInterruptStatus(ENET_Type *base)
+{
+    return base->MAC_INTR_STAT;
+}
+
+/*!
+ * @brief Clears the ENET mac interrupt events status flag.
+ *
+ * This function clears enabled ENET interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See the @ref enet_mac_interrupt_enable_t.
+ * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
+ * @code
+ *     ENET_ClearMacInterruptStatus(ENET, kENET_MacPmt);
+ * @endcode
+ *
+ * @param base  ENET peripheral base address.
+ * @param mask  ENET interrupt source to be cleared.
+ * This is the logical OR of members of the enumeration :: enet_mac_interrupt_enable_t.
+ */
+void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Functional operation.
+ * @{
+ */
+
+/*!
+ * @brief Get the tx descriptor DMA Own flag.
+ *
+ * @param txDesc  The given tx descriptor.
+ * @retval True the dma own tx descriptor, false application own tx descriptor.
+ *
+ */
+static inline bool ENET_IsTxDescriptorDmaOwn(enet_tx_bd_struct_t *txDesc)
+{
+    return (txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK) ? true : false;
+}
+
+/*!
+ * @brief Setup a given tx descriptor.
+ *  This function is a low level functional API to setup or prepare
+ *  a given tx descriptor.
+ *
+ * @param txDesc  The given tx descriptor.
+ * @param buffer1  The first buffer address in the descriptor.
+ * @param bytes1  The bytes in the fist buffer.
+ * @param buffer2  The second buffer address in the descriptor.
+ * @param bytes1  The bytes in the second buffer.
+ * @param framelen  The length of the frame to be transmitted.
+ * @param intEnable Interrupt enable flag.
+ * @param tsEnable The timestamp enable.
+ * @param flag The flag of this tx desciriptor, see "enet_desc_flag" .
+ * @param slotNum The slot num used for AV  only.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
+ * memory until the packet has been fully transmitted. The buffers
+ * should be free or requeued in the transmit interrupt irq handler.
+ */
+void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
+                            void *buffer1,
+                            uint32_t bytes1,
+                            void *buffer2,
+                            uint32_t bytes2,
+                            uint32_t framelen,
+                            bool intEnable,
+                            bool tsEnable,
+                            enet_desc_flag flag,
+                            uint8_t slotNum);
+
+/*!
+ * @brief Update the tx descriptor tail pointer.
+ *  This function is a low level functional API to update the
+ *  the tx descriptor tail.
+ *  This is called after you setup a new tx descriptor to update
+ *  the tail pointer to make the new descritor accessable by DMA.
+ *
+ * @param base    ENET peripheral base address.
+ * @param channel  The tx DMA channel.
+ * @param txDescTailAddrAlign  The new tx tail pointer address.
+ *
+ */
+static inline void ENET_UpdateTxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)
+{
+    base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT;
+}
+
+/*!
+ * @brief Update the rx descriptor tail pointer.
+ *  This function is a low level functional API to update the
+ *  the rx descriptor tail.
+ *  This is called after you setup a new rx descriptor to update
+ *  the tail pointer to make the new descritor accessable by DMA
+ *  and to anouse the rx poll command for DMA.
+ *
+ * @param base    ENET peripheral base address.
+ * @param channel  The rx DMA channel.
+ * @param rxDescTailAddrAlign  The new rx tail pointer address.
+ *
+ */
+static inline void ENET_UpdateRxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)
+{
+    base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT;
+}
+
+/*!
+ * @brief Gets the context in the ENET rx descriptor.
+ *  This function is a low level functional API to get the
+ *  the status flag from a given rx descriptor.
+ *
+ * @param rxDesc  The given rx descriptor.
+ * @retval The RDES3 regions for write-back format rx buffer descriptor.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ */
+static inline uint32_t ENET_GetRxDescriptor(enet_rx_bd_struct_t *rxDesc)
+{
+    assert(rxDesc);
+
+    return rxDesc->control;
+}
+/*!
+ * @brief Updates the buffers and the own status for a given rx descriptor.
+ *  This function is a low level functional API to Updates the
+ *  buffers and the own status for a given rx descriptor.
+ *
+ * @param rxDesc  The given rx descriptor.
+ * @param buffer1  The first buffer address in the descriptor.
+ * @param buffer2  The second buffer address in the descriptor.
+ * @param intEnable Interrupt enable flag.
+ * @param doubleBuffEnable The double buffer enable flag.
+ *
+ * @note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ */
+void ENET_UpdateRxDescriptor(
+    enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable);
+
+/* @} */
+
+/*!
+ * @name Transactional operation
+ * @{
+ */
+
+/*!
+ * @brief Create ENET Handler 
+ *
+ * This is a transactional API and it's provided to store all datas which are needed
+ * during the whole transactional process. This API should not be used when you use
+ * functional APIs to do data tx/rx. This is funtion will store many data/flag for 
+ * transactional use, so all configure API such as ENET_Init(), ENET_DescriptorInit(),
+ * ENET_EnableInterrupts() etc.
+ *
+ * @note as our transactional transmit API use the zero-copy transmit buffer.
+ * so there are two thing we emphasize here:
+ *  1. tx buffer free/requeue for application should be done in the tx 
+ *  interrupt handler. Please set callback: kENET_TxIntEvent with tx buffer free/requeue
+ *  process APIs.
+ *  2. the tx interrupt is forced to open.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle ENET handler.
+ * @param config ENET configuration.
+ * @param bufferConfig ENET buffer configuration.
+ * @param callback The callback function.
+ * @param userData The application data.
+ */
+void ENET_CreateHandler(ENET_Type *base,
+                        enet_handle_t *handle,
+                        enet_config_t *config,
+                        enet_buffer_config_t *bufferConfig,
+                        enet_callback_t callback,
+                        void *userData);
+
+/*!
+* @brief Gets the size of the read frame.
+* This function gets a received frame size from the ENET buffer descriptors.
+* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
+* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
+* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
+*
+* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+* @param length The length of the valid frame received.
+* @param channel The DMAC channel for the rx.
+* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
+* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
+*         and NULL length to update the receive buffers.
+* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+*         should be called with the right data buffer and the captured data length input.
+*/
+status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel);
+
+/*!
+ * @brief Reads a frame from the ENET device.
+ * This function reads a frame from the ENET DMA descriptors.
+ * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer.
+ * For example use rx dma channel 0:
+ * @code
+ *       uint32_t length;
+ *       enet_handle_t g_handle;
+ *       //Get the received frame size firstly.
+ *       status = ENET_GetRxFrameSize(&g_handle, &length, 0);
+ *       if (length != 0)
+ *       {
+ *           //Allocate memory here with the size of "length"
+ *           uint8_t *data = memory allocate interface;
+ *           if (!data)
+ *           {
+ *               ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0);
+ *               //Add the console warning log.
+ *           }
+ *           else
+ *           {
+ *              status = ENET_ReadFrame(ENET, &g_handle, data, length, 0);
+ *              //Call stack input API to deliver the data to stack
+ *           }
+ *       }
+ *       else if (status == kStatus_ENET_RxFrameError)
+ *       {
+ *          //Update the received buffer when a error frame is received.
+ *           ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0);
+ *       }
+ * @endcode
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+ * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
+ * @param length The size of the data buffer which is still the length of the received frame.
+ * @param channel The rx DMA channel. shall not be larger than 2.
+ * @return The execute status, successful or failure.
+ */
+status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel);
+
+/*!
+ * @brief Transmits an ENET frame.
+ * @note The CRC is automatically appended to the data. Input the data
+ * to send without the CRC.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
+ * @param data The data buffer provided by user to be send.
+ * @param length The length of the data to be send.
+ * @retval kStatus_Success  Send frame succeed.
+ * @retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmission.
+ *         The transmit busy happens when the data send rate is over the MAC capacity.
+ *         The waiting mechanism is recommended to be added after each call return with
+ *         kStatus_ENET_TxFrameBusy.
+ */
+status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Reclaim tx descriptors.
+ *  This function is used to update the tx descriptor status and
+ *  store the tx timestamp when the 1588 feature is enabled.
+ *  This is called by the transmit interupt IRQ handler after the
+ *  complete of a frame transmission.
+ *
+ * @param base    ENET peripheral base address.
+ * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
+ * @param channel  The tx DMA channnel.
+ *
+ */
+void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel);
+
+/*!
+ * @brief The ENET PMT IRQ handler.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler pointer.
+ */
+void ENET_PMTIRQHandler(ENET_Type *base, enet_handle_t *handle);
+
+/*!
+ * @brief The ENET IRQ handler.
+ *
+ * @param base  ENET peripheral base address.
+ * @param handle The ENET handler pointer.
+ */
+void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle);
+
+/* @} */
+
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+/*!
+ * @name ENET Enhanced function operation
+ * @{
+ */
+
+/*!
+ * @brief Starts the ENET PTP 1588 Timer.
+ * This function is used to initialize the PTP timer. After the PTP starts,
+ * the PTP timer starts running.
+ *
+ * @param base  ENET peripheral base address.
+ * @param ptpClkSrc The clock source of the PTP timer.
+ */
+void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc);
+
+/*!
+ * @brief Coreect the ENET PTP 1588 timer in coarse method.
+ *
+ * @param base  ENET peripheral base address.
+ * @param operation The system time operation, refer to "enet_systime_op"
+ * @param second The correction second.
+ * @param nanosecond The correction nanosecond.
+ */
+void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond);
+
+/*!
+ * @brief Coreect the ENET PTP 1588 timer in fine method.
+ *
+ *
+ * @param base  ENET peripheral base address.
+ * @param addend The addend value to be set in the fine method
+ * @note Should take refer to the chapter "System time corretion" and
+ * see the description for the "fine correction method".
+ */
+static inline void ENET_Ptp1588CorrectTimerInFine(ENET_Type *base, uint32_t addend)
+{
+    /* Set the freqCompensation value. */
+    base->MAC_SYS_TIMESTMP_ADDEND = addend;
+    base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK;
+}
+
+/*!
+ * @brief Get the ENET Time stamp current addend value.
+ *
+ * @param base  ENET peripheral base address.
+ * @return The addend value.
+ */
+static inline uint32_t ENET_Ptp1588GetAddend(ENET_Type *base)
+{
+    return base->MAC_SYS_TIMESTMP_ADDEND;
+}
+
+/*!
+ * @brief Gets the current ENET time from the PTP 1588 timer.
+ *
+ * @param base  ENET peripheral base address.
+ * @param second The PTP 1588 system timer second.
+ * @param nanosecond The PTP 1588 system timer nanosecond.
+ * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.
+ */
+void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond);
+
+/*!
+ * @brief Gets the time stamp of the received frame.
+ *
+ * This function is used for PTP stack to get the timestamp captured by the ENET driver.
+ *
+ * @param handle The ENET handler pointer.This is the same state pointer used in
+ *        ENET_Init.
+ * @param ptpTimeData The special PTP timestamp data for search the receive timestamp.
+ * @retval kStatus_Success Get 1588 timestamp success.
+ * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
+ * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
+ */
+status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData);
+
+/*!
+ * @brief Gets the time stamp of the transmit frame.
+ *
+ * This function is used for PTP stack to get the timestamp captured by the ENET driver.
+ *
+ * @param handle The ENET handler pointer.This is the same state pointer used in
+ *        ENET_Init.
+ * @param ptpTimeData The special PTP timestamp data for search the receive timestamp.
+ * @retval kStatus_Success Get 1588 timestamp success.
+ * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty.
+ * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full.
+ */
+status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData);
+#endif /* ENET_PTP1588FEATURE_REQUIRED */
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_ENET_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_flashiap.h"
+
+#define HZ_TO_KHZ_DIV 1000
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static status_t translate_iap_status(uint32_t status)
+{
+    /* Translate IAP return code to sdk status code */
+    if (status == kStatus_Success)
+    {
+        return status;
+    }
+    else
+    {
+        return MAKE_STATUS(kStatusGroup_FLASHIAP, status);
+    }
+}
+
+status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite;
+    command[1] = startSector;
+    command[2] = endSector;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_CopyRamToFlash;
+    command[1] = dstAddr;
+    command[2] = (uint32_t)srcAddr;
+    command[3] = numOfBytes;
+    command[4] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_EraseSector;
+    command[1] = startSector;
+    command[2] = endSector;
+    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_ErasePage;
+    command[1] = startPage;
+    command[2] = endPage;
+    command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_BlankCheckSector;
+    command[1] = startSector;
+    command[2] = endSector;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}
+
+status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes)
+{
+    uint32_t command[5], result[4];
+
+    command[0] = kIapCmd_FLASHIAP_Compare;
+    command[1] = dstAddr;
+    command[2] = (uint32_t)srcAddr;
+    command[3] = numOfBytes;
+    iap_entry(command, result);
+
+    return translate_iap_status(result[0]);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FLASHIAP_H_
+#define _FSL_FLASHIAP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flashiap_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+                                                            /*@}*/
+
+/*!
+ * @brief Flashiap status codes.
+ */
+enum _flashiap_status
+{
+    kStatus_FLASHIAP_Success = kStatus_Success,                               /*!< Api is executed successfully */
+    kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */
+    kStatus_FLASHIAP_SrcAddrError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */
+    kStatus_FLASHIAP_DstAddrError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */
+    kStatus_FLASHIAP_SrcAddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */
+    kStatus_FLASHIAP_DstAddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */
+    kStatus_FLASHIAP_CountError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */
+    kStatus_FLASHIAP_InvalidSector =
+        MAKE_STATUS(kStatusGroup_FLASHIAP,
+                    7), /*!< Sector number is invalid or end sector number is greater than start sector number */
+    kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */
+    kStatus_FLASHIAP_NotPrepared =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */
+    kStatus_FLASHIAP_CompareError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */
+    kStatus_FLASHIAP_Busy =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */
+    kStatus_FLASHIAP_ParamError =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */
+    kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */
+    kStatus_FLASHIAP_AddrNotMapped =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 14U),                        /*!< Address is not mapped in the memory map */
+    kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */
+    kStatus_FLASHIAP_NoClock =
+        MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */
+};
+
+/*!
+ * @brief Flashiap command codes.
+ */
+enum _flashiap_commands
+{
+    kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */
+    kIapCmd_FLASHIAP_CopyRamToFlash = 51U,        /*!< Copy RAM to flash */
+    kIapCmd_FLASHIAP_EraseSector = 52U,           /*!< Erase Sector */
+    kIapCmd_FLASHIAP_BlankCheckSector = 53U,      /*!< Blank check sector */
+    kIapCmd_FLASHIAP_ReadPartId = 54U,            /*!< Read part id */
+    kIapCmd_FLASHIAP_Read_BootromVersion = 55U,   /*!< Read bootrom version */
+    kIapCmd_FLASHIAP_Compare = 56U,               /*!< Compare */
+    kIapCmd_FLASHIAP_ReinvokeISP = 57U,           /*!< Reinvoke ISP */
+    kIapCmd_FLASHIAP_ReadUid = 58U,               /*!< Read Uid isp */
+    kIapCmd_FLASHIAP_ErasePage = 59U,             /*!< Erase Page */
+    kIapCmd_FLASHIAP_ReadMisr = 70U,              /*!< Read Misr */
+    kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U      /*!< Reinvoke I2C/SPI isp */
+};
+
+/*! @brief IAP_ENTRY API function type */
+typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief IAP_ENTRY API function type
+ *
+ * Wrapper for rom iap call
+ *
+ * @param cmd_param IAP command and relevant parameter array.
+ * @param status_result IAP status result array.
+ *
+ * @retval None. Status/Result is returned via status_result array.
+ */
+static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result)
+{
+    ((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result);
+}
+
+/*!
+ * @brief	Prepare sector for write operation
+
+ * This function prepares sector(s) for write/erase operation. This function must be
+ * called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or
+ * FLASHIAP_ErasePage() function. The end sector must be greater than or equal to
+ * start sector number.
+ *
+ * @param startSector Start sector number.
+ * @param endSector End sector number.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
+ *         is greater than start sector number.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector);
+
+/*!
+ * @brief	Copy RAM to flash.
+
+ * This function programs the flash memory. Corresponding sectors must be prepared
+ * via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses
+ * should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096.
+ *
+ * @param dstAddr Destination flash address where data bytes are to be written.
+ * @param srcAddr Source ram address from where data bytes are to be read.
+ * @param numOfBytes Number of bytes to be written.
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary.
+ * @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary.
+ * @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock);
+
+/*!
+ * @brief	Erase sector
+
+ * This function erases sector(s). The end sector must be greater than or equal to
+ * start sector number. FLASHIAP_PrepareSectorForWrite must be called before
+ * calling this function.
+ *
+ * @param startSector Start sector number.
+ * @param endSector End sector number.
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
+ *         is greater than start sector number.
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock);
+
+/*!
+
+ * This function erases page(s). The end page must be greater than or equal to
+ * start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite
+ * before calling calling this function.
+ *
+ * @param startPage Start page number
+ * @param endPage End page number
+ * @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
+ *                        rom IAP function.
+ *
+ * @retval #kStatus_FLASHIAP_Success Api was executed successfully.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number
+ *         is greater than start page number
+ * @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
+ * @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
+ */
+status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock);
+
+/*!
+ * @brief Blank check sector(s)
+ *
+ * Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to
+ * start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call.
+ *
+ * @param	startSector	: Start sector number. Must be greater than or equal to start sector number
+ * @param	endSector	: End sector number
+ * @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank.
+ */
+status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector);
+
+/*!
+ * @brief Compare memory contents of flash with ram.
+
+ * This function compares the contents of flash and ram. It can be used to verify the flash
+ * memory contents after FLASHIAP_CopyRamToFlash call.
+ *
+ * @param dstAddr Destination flash address.
+ * @param srcAddr Source ram address.
+ * @param numOfBytes Number of bytes to be compared.
+ *
+ * @retval #kStatus_FLASHIAP_Success Contents of flash and ram match.
+ * @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
+ * @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
+ * @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary.
+ * @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map.
+ * @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
+ * @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match.
+ */
+status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLASHIAP_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+    if (periph == FLEXCOMM_PERIPH_NONE)
+    {
+        return true;
+    }
+    else if ((periph >= FLEXCOMM_PERIPH_USART) && (periph <= FLEXCOMM_PERIPH_I2S_TX))
+    {
+        return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > 0 ? true : false;
+    }
+    else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+    {
+        return (base->PSELID & (1 << 7)) > 0 ? true : false;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+    {
+        if ((uint32_t)base == s_flexcommBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+/* Changes FLEXCOMM mode */
+status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+    /* Check whether peripheral type is present */
+    if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Flexcomm is locked to different peripheral type than expected  */
+    if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check if we are asked to lock */
+    if (lock)
+    {
+        base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+    }
+    else
+    {
+        base->PSELID = (uint32_t)periph;
+    }
+
+    return kStatus_Success;
+}
+
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+    int idx = FLEXCOMM_GetInstance(base);
+
+    if (idx < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_flexcommClocks[idx]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Set the FLEXCOMM to given peripheral */
+    return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(base);
+
+    /* Clear handler first to avoid execution of the handler with wrong handle */
+    s_flexcommIrqHandler[instance] = NULL;
+    s_flexcommHandle[instance] = handle;
+    s_flexcommIrqHandler[instance] = handler;
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[0]);
+    s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
+}
+#endif
+
+#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[1]);
+    s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
+}
+#endif
+
+#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[2]);
+    s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
+}
+#endif
+
+#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[3]);
+    s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
+}
+#endif
+
+#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[4]);
+    s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
+}
+
+#endif
+
+#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[5]);
+    s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
+}
+#endif
+
+#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[6]);
+    s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
+}
+#endif
+
+#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[7]);
+    s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
+}
+#endif
+
+#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[8]);
+    s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
+}
+#endif
+
+#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[9]);
+    s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fmc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void FMC_GetDefaultConfig(fmc_config_t *config)
+{
+    config->waitStates = 0x05;
+}
+
+void FMC_Init(FMC_Type *base, fmc_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable clock to FMC */
+    CLOCK_EnableClock(kCLOCK_Fmc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Set control register, FS_RD0 = 0, FS_RD1 = 1. */
+    base->FCTR &= ~(FMC_FCTR_FS_RD0_MASK | FMC_FCTR_FS_RD1_MASK);
+    base->FCTR |= FMC_FCTR_FS_RD1_MASK;
+
+    /* Set wait state, same as FLASHTIM in SYSCON->FLASHCFG register. */
+    base->FBWST &= ~FMC_FBWST_WAITSTATES_MASK;
+    base->FBWST |= config->waitStates;
+}
+
+void FMC_Denit(FMC_Type *base)
+{
+    /* Reset FMC module */
+    RESET_PeripheralReset(kFMC_RST_SHIFT_RSTn);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* enable clock to FMC */
+    CLOCK_DisableClock(kCLOCK_Fmc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void FMC_GenerateFlashSignature(FMC_Type *base,
+                                uint32_t startAddress,
+                                uint32_t length,
+                                fmc_flash_signature_t *flashSignature)
+{
+    uint32_t stopAddress;
+
+    /* Clear generation done flag. */
+    base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag;
+
+    /* Calculate flash stop address */
+    stopAddress = ((startAddress + length - 1) >> 4) & FMC_FMSSTOP_STOP_MASK;
+
+    /* Calculate flash start address. */
+    startAddress = (startAddress >> 4) & FMC_FMSSTART_START_MASK;
+
+    /* Start flash signature generation. */
+    base->FMSSTART = startAddress;
+    base->FMSSTOP = stopAddress;
+
+    base->FMSSTOP |= FMC_FMSSTOP_SIG_START_MASK;
+
+    /* Wait for signature done. */
+    while ((base->FMSTAT & kFMC_SignatureGenerationDoneFlag) != kFMC_SignatureGenerationDoneFlag)
+    {
+    }
+
+    /* Clear generation done flag. */
+    base->FMSTATCLR = kFMC_SignatureGenerationDoneFlag;
+
+    /* Get the generated flash signature. */
+    flashSignature->word0 = base->FMSW[0];
+    flashSignature->word1 = base->FMSW[1];
+    flashSignature->word2 = base->FMSW[2];
+    flashSignature->word3 = base->FMSW[3];
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_FMC_H_
+#define _FSL_FMC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup fmc
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_FMC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
+/*@}*/
+
+/*!
+ * @addtogroup fmc_driver
+ * @{
+ */
+
+/*!
+ * @brief fmc peripheral flag.
+ *
+ */
+enum _fmc_flags
+{
+    kFMC_SignatureGenerationDoneFlag = FMC_FMSTAT_SIG_DONE_MASK, /*!< Flash signature generation done. */
+};
+
+/*! @brief Defines the generated 128-bit signature. */
+typedef struct _fmc_flash_signature
+{
+    uint32_t word0; /* Signature bits [31:0]. */
+    uint32_t word1; /* Signature bits [63:32]. */
+    uint32_t word2; /* Signature bits [95:64]. */
+    uint32_t word3; /* Signature bits [127:96]. */
+} fmc_flash_signature_t;
+
+/*! @brief fmc config structure. */
+typedef struct _fmc_config
+{
+    uint8_t waitStates; /* flash timing value for flash signature generation. */
+} fmc_config_t;
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize FMC module.
+ *
+ * This function initialize FMC module with user configuration
+ *
+ * @param base The FMC peripheral base address.
+ * @param config pointer to user configuration structure.
+ */
+void FMC_Init(FMC_Type *base, fmc_config_t *config);
+
+/*!
+ * @brief Deinit FMC module.
+ *
+ * This function De-initialize FMC module.
+ *
+ * @param base The FMC peripheral base address.
+ */
+void FMC_Deinit(FMC_Type *base);
+
+/*!
+ * @brief Provides default configuration for fmc module.
+ *
+ * This function provides default configuration for fmc module, the default wait states value is
+ * 5.
+ *
+ * @param config pointer to user configuration structure.
+ */
+void FMC_GetDefaultConfig(fmc_config_t *config);
+
+/*!
+ * @brief Generate hardware flash signature.
+ *
+ * This function generates hardware flash signature for specified address range.
+ *
+ * @note This function needs to be excuted out of flash memory.
+ * @param base The FMC peripheral base address.
+ * @param startAddress Flash start address for signature generation.
+ * @param length Length of address range.
+ * @param flashSignature Pointer which stores the generated flash signarue.
+ */
+void FMC_GenerateFlashSignature(FMC_Type *base,
+                                uint32_t startAddress,
+                                uint32_t length,
+                                fmc_flash_signature_t *flashSignature);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fmeas.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Target clock counter value.
+ * According to user manual, 2 has to be subtracted from captured value (CAPVAL). */
+#define TARGET_CLOCK_COUNT(base) \
+    ((uint32_t)(                 \
+        ((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2))
+
+/*! @brief Reference clock counter value. */
+#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1))
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate)
+{
+    uint32_t targetClockCount = TARGET_CLOCK_COUNT(base);
+    uint64_t clkrate = 0;
+
+    if (targetClockCount > 0)
+    {
+        clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT;
+    }
+
+    return (uint32_t)clkrate;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_FMEAS_H_
+#define _FSL_FMEAS_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup fmeas
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines LPC Frequency Measure driver version 2.0.0.
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name FMEAS Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief    Starts a frequency measurement cycle.
+ *
+ * @param    base : SYSCON peripheral base address.
+ */
+static inline void FMEAS_StartMeasure(SYSCON_Type *base)
+{
+    base->FREQMECTRL = 0;
+    base->FREQMECTRL = (1UL << 31);
+}
+
+/*!
+ * @brief    Indicates when a frequency measurement cycle is complete.
+ *
+ * @param    base : SYSCON peripheral base address.
+ * @return   true if a measurement cycle is active, otherwise false.
+ */
+static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base)
+{
+    return (bool)((base->FREQMECTRL & (1UL << 31)) == 0);
+}
+
+/*!
+ * @brief    Returns the computed value for a frequency measurement cycle
+ *
+ * @param    base         : SYSCON peripheral base address.
+ * @param    refClockRate : Reference clock rate used during the frequency measurement cycle.
+ *
+ * @return   Frequency in Hz.
+ */
+uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_FMEAS_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gint.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to GINT bases for each instance. */
+static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Clocks for each instance. */
+static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Resets for each instance. */
+static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS;
+
+/* @brief Irq number for each instance */
+static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS;
+
+/*! @brief Callback function array for GINT(s). */
+static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GINT_GetInstance(GINT_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++)
+    {
+        if (s_gintBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gintBases));
+
+    return instance;
+}
+
+void GINT_Init(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    s_gintCallback[instance] = NULL;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_gintClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(s_gintResets[instance]);
+}
+
+void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig));
+
+    /* Save callback pointer */
+    s_gintCallback[instance] = callback;
+}
+
+void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
+    *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
+    *callback = s_gintCallback[instance];
+}
+
+void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask)
+{
+    base->PORT_POL[port] = polarityMask;
+    base->PORT_ENA[port] = enableMask;
+}
+
+void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask)
+{
+    *polarityMask = base->PORT_POL[port];
+    *enableMask = base->PORT_ENA[port];
+}
+
+void GINT_EnableCallback(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+    /* If GINT is configured in "AND" mode a spurious interrupt is generated.
+       Clear status and pending interrupt before enabling the irq in NVIC. */
+    GINT_ClrStatus(base);
+    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
+    EnableIRQ(s_gintIRQ[instance]);
+}
+
+void GINT_DisableCallback(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+    DisableIRQ(s_gintIRQ[instance]);
+    GINT_ClrStatus(base);
+    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
+}
+
+void GINT_Deinit(GINT_Type *base)
+{
+    uint32_t instance;
+
+    instance = GINT_GetInstance(base);
+
+    /* Cleanup */
+    GINT_DisableCallback(base);
+    s_gintCallback[instance] = NULL;
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(s_gintResets[instance]);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the peripheral clock */
+    CLOCK_DisableClock(s_gintClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(GINT0)
+void GINT0_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[0] != NULL)
+    {
+        s_gintCallback[0]();
+    }
+}
+#endif
+
+#if defined(GINT1)
+void GINT1_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[1] != NULL)
+    {
+        s_gintCallback[1]();
+    }
+}
+#endif
+
+#if defined(GINT2)
+void GINT2_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[2] != NULL)
+    {
+        s_gintCallback[2]();
+    }
+}
+#endif
+
+#if defined(GINT3)
+void GINT3_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[3] != NULL)
+    {
+        s_gintCallback[3]();
+    }
+}
+#endif
+
+#if defined(GINT4)
+void GINT4_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[4] != NULL)
+    {
+        s_gintCallback[4]();
+    }
+}
+#endif
+
+#if defined(GINT5)
+void GINT5_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[5] != NULL)
+    {
+        s_gintCallback[5]();
+    }
+}
+#endif
+
+#if defined(GINT6)
+void GINT6_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[6] != NULL)
+    {
+        s_gintCallback[6]();
+    }
+}
+#endif
+
+#if defined(GINT7)
+void GINT7_DriverIRQHandler(void)
+{
+    /* Clear interrupt before callback */
+    s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK;
+    /* Call user function */
+    if (s_gintCallback[7] != NULL)
+    {
+        s_gintCallback[7]();
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_GINT_H_
+#define _FSL_GINT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gint_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+/*@}*/
+
+/*! @brief GINT combine inputs type */
+typedef enum _gint_comb
+{
+    kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */
+    kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */
+} gint_comb_t;
+
+/*! @brief GINT trigger type */
+typedef enum _gint_trig
+{
+    kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */
+    kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */
+} gint_trig_t;
+
+/* @brief GINT port type */
+typedef enum _gint_port
+{
+    kGINT_Port0 = 0U,
+    kGINT_Port1 = 1U,
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U)
+    kGINT_Port2 = 2U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U)
+    kGINT_Port3 = 3U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U)
+    kGINT_Port4 = 4U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U)
+    kGINT_Port5 = 5U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U)
+    kGINT_Port6 = 6U,
+#endif
+#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U)
+    kGINT_Port7 = 7U,
+#endif
+} gint_port_t;
+
+/*! @brief GINT Callback function. */
+typedef void (*gint_cb_t)(void);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize GINT peripheral.
+
+ * This function initializes the GINT peripheral and enables the clock.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_Init(GINT_Type *base);
+
+/*!
+ * @brief	Setup GINT peripheral control parameters.
+
+ * This function sets the control parameters of GINT peripheral.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
+ * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
+ * @param callback This function is called when configured group interrupt is generated.
+ *
+ * @retval None.
+ */
+void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback);
+
+/*!
+ * @brief	Get GINT peripheral control parameters.
+
+ * This function returns the control parameters of GINT peripheral.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param comb Pointer to store combine input value.
+ * @param trig Pointer to store trigger value.
+ * @param callback Pointer to store callback function.
+ *
+ * @retval None.
+ */
+void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback);
+
+/*!
+ * @brief	Configure GINT peripheral pins.
+
+ * This function enables and controls the polarity of enabled pin(s) of a given port.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param port Port number.
+ * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
+ *        0 = The pin is active LOW. 1 = The pin is active HIGH.
+ * @param enableMask Each bit position selects if the corresponding pin is enabled or not.
+ *        0 = The pin is disabled. 1 = The pin is enabled.
+ *
+ * @retval None.
+ */
+void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask);
+
+/*!
+ * @brief	Get GINT peripheral pin configuration.
+
+ * This function returns the pin configuration of a given port.
+ *
+ * @param base Base address of the GINT peripheral.
+ * @param port Port number.
+ * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
+ enabled pin.
+ *        0 = The pin is active LOW. 1 = The pin is active HIGH.
+ * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
+ or not.
+ *        0 = The pin is disabled. 1 = The pin is enabled.
+ *
+ * @retval None.
+ */
+void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask);
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
+ * as soon as they are enabled, the callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_EnableCallback(GINT_Type *base);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected GINT peripheral. Although the pins are still
+ * being monitored but the callback function is not called.
+ *
+ * @param base Base address of the peripheral.
+ *
+ * @retval None.
+ */
+void GINT_DisableCallback(GINT_Type *base);
+
+/*!
+ * @brief	Clear GINT status.
+
+ * This function clears the GINT status bit.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void GINT_ClrStatus(GINT_Type *base)
+{
+    base->CTRL |= GINT_CTRL_INT_MASK;
+}
+
+/*!
+ * @brief	Get GINT status.
+
+ * This function returns the GINT status.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval status = 0 No group interrupt request.  = 1 Group interrupt request active.
+ */
+static inline uint32_t GINT_GetStatus(GINT_Type *base)
+{
+    return (base->CTRL & GINT_CTRL_INT_MASK);
+}
+
+/*!
+ * @brief	Deinitialize GINT peripheral.
+
+ * This function disables the GINT clock.
+ *
+ * @param base Base address of the GINT peripheral.
+ *
+ * @retval None.
+ */
+void GINT_Deinit(GINT_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_GINT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+* Prototypes
+************ ******************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->DIR[port] &= ~(1U << pin);
+    }
+    else
+    {
+        /* Set default output value */
+        if (config->outputLogic == 0U)
+        {
+            base->CLR[port] = (1U << pin);
+        }
+        else
+        {
+            base->SET[port] = (1U << pin);
+        }
+        /* Set pin direction */
+        base->DIR[port] |= 1U << pin;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPC GPIO driver version 2.0.0. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+    base->B[port][pin] = output;
+}
+/*@}*/
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+    return (uint32_t)base->B[port][pin];
+}
+/*@}*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->NOT[port] = mask;
+}
+/*@}*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->PIN[port];
+}
+
+/*@}*/
+/*! @name GPIO Mask Operations */
+/*@{*/
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param output  GPIO port output value.
+ */
+static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+    base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @retval       masked GPIO port value
+ */
+static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->MPIN[port];
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1398 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c.h"
+#include "fsl_flexcomm.h"
+#include <stdlib.h>
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Common sets of flags used by the driver. */
+enum _i2c_flag_constants
+{
+    kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK,
+    kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK,
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+static void I2C_SlaveInternalStateMachineReset(I2C_Type *base);
+static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal);
+static uint32_t I2C_SlavePollPending(I2C_Type *base);
+static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event);
+static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
+static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
+                                                     i2c_slave_handle_t *handle,
+                                                     const void *txData,
+                                                     size_t txSize,
+                                                     void *rxData,
+                                                     size_t rxSize,
+                                                     uint32_t eventMask);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Array to map i2c instance number to base address. */
+static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS;
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief Returns an instance number given a base address.
+ *
+ * If an invalid base address is passed, debug builds will assert. Release builds will just return
+ * instance number 0.
+ *
+ * @param base The I2C peripheral base address.
+ * @return I2C instance number starting from 0.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base)
+{
+    int i;
+    for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++)
+    {
+        if ((uint32_t)base == s_i2cBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+    assert(false);
+    return 0;
+}
+
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
+{
+    masterConfig->enableMaster = true;
+    masterConfig->baudRate_Bps = 100000U;
+    masterConfig->enableTimeout = false;
+}
+
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
+{
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
+    I2C_MasterEnable(base, masterConfig->enableMaster);
+    I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
+}
+
+void I2C_MasterDeinit(I2C_Type *base)
+{
+    I2C_MasterEnable(base, false);
+}
+
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t scl, divider;
+    uint32_t best_scl, best_div;
+    uint32_t err, best_err;
+
+    best_err = 0;
+
+    for (scl = 9; scl >= 2; scl--)
+    {
+        /* calculated ideal divider value for given scl */
+        divider = srcClock_Hz / (baudRate_Bps * scl * 2u);
+
+        /* adjust it if it is out of range */
+        divider = (divider > 0x10000u) ? 0x10000 : divider;
+
+        /* calculate error */
+        err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider);
+        if ((err < best_err) || (best_err == 0))
+        {
+            best_div = divider;
+            best_scl = scl;
+            best_err = err;
+        }
+
+        if ((err == 0) || (divider >= 0x10000u))
+        {
+            /* either exact value was found
+               or divider is at its max (it would even greater in the next iteration for sure) */
+            break;
+        }
+    }
+
+    base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1);
+    base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u);
+}
+
+static uint32_t I2C_PendingStatusWait(I2C_Type *base)
+{
+    uint32_t status;
+
+    do
+    {
+        status = I2C_GetStatusFlags(base);
+    } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+    /* Clear controller state. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    return status;
+}
+
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    I2C_PendingStatusWait(base);
+
+    /* Write Address and RW bit to data register */
+    base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u);
+    /* Start the transfer */
+    base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterStop(I2C_Type *base)
+{
+    I2C_PendingStatusWait(base);
+
+    base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+    return kStatus_Success;
+}
+
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags)
+{
+    uint32_t status;
+    uint32_t master_state;
+    status_t err;
+
+    const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff;
+
+    assert(txBuff);
+
+    err = kStatus_Success;
+    while (txSize)
+    {
+        status = I2C_PendingStatusWait(base);
+
+        if (status & I2C_STAT_MSTARBLOSS_MASK)
+        {
+            return kStatus_I2C_ArbitrationLost;
+        }
+
+        if (status & I2C_STAT_MSTSTSTPERR_MASK)
+        {
+            return kStatus_I2C_StartStopError;
+        }
+
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+        switch (master_state)
+        {
+            case I2C_STAT_MSTCODE_TXREADY:
+                /* ready to send next byte */
+                base->MSTDAT = *buf++;
+                txSize--;
+                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+                break;
+
+            case I2C_STAT_MSTCODE_NACKADR:
+            case I2C_STAT_MSTCODE_NACKDAT:
+                /* slave nacked the last byte */
+                err = kStatus_I2C_Nak;
+                break;
+
+            default:
+                /* unexpected state */
+                err = kStatus_I2C_UnexpectedState;
+                break;
+        }
+
+        if (err != kStatus_Success)
+        {
+            return err;
+        }
+    }
+
+    status = I2C_PendingStatusWait(base);
+
+    if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0)
+    {
+        if (!(flags & kI2C_TransferNoStopFlag))
+        {
+            /* Initiate stop */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            status = I2C_PendingStatusWait(base);
+        }
+    }
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        return kStatus_I2C_StartStopError;
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)
+{
+    uint32_t status = 0;
+    uint32_t master_state;
+    status_t err;
+
+    uint8_t *buf = (uint8_t *)(rxBuff);
+
+    assert(rxBuff);
+
+    err = kStatus_Success;
+    while (rxSize)
+    {
+        status = I2C_PendingStatusWait(base);
+
+        if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK))
+        {
+            break;
+        }
+
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+        switch (master_state)
+        {
+            case I2C_STAT_MSTCODE_RXREADY:
+                /* ready to send next byte */
+                *(buf++) = base->MSTDAT;
+                if (--rxSize)
+                {
+                    base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+                }
+                else
+                {
+                    if ((flags & kI2C_TransferNoStopFlag) == 0)
+                    {
+                        /* initiate NAK and stop */
+                        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+                        status = I2C_PendingStatusWait(base);
+                    }
+                }
+                break;
+
+            case I2C_STAT_MSTCODE_NACKADR:
+            case I2C_STAT_MSTCODE_NACKDAT:
+                /* slave nacked the last byte */
+                err = kStatus_I2C_Nak;
+                break;
+
+            default:
+                /* unexpected state */
+                err = kStatus_I2C_UnexpectedState;
+                break;
+        }
+
+        if (err != kStatus_Success)
+        {
+            return err;
+        }
+    }
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        return kStatus_I2C_StartStopError;
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
+{
+    status_t result = kStatus_Success;
+    uint32_t subaddress;
+    uint8_t subaddrBuf[4];
+    int i;
+
+    assert(xfer);
+
+    /* If repeated start is requested, send repeated start. */
+    if (!(xfer->flags & kI2C_TransferNoStartFlag))
+    {
+        if (xfer->subaddressSize)
+        {
+            result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write);
+            if (result == kStatus_Success)
+            {
+                /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+                subaddress = xfer->subaddress;
+                for (i = xfer->subaddressSize - 1; i >= 0; i--)
+                {
+                    subaddrBuf[i] = subaddress & 0xff;
+                    subaddress >>= 8;
+                }
+                /* Send subaddress. */
+                result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag);
+                if ((result == kStatus_Success) && (xfer->direction == kI2C_Read))
+                {
+                    result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
+                }
+            }
+        }
+        else if (xfer->flags & kI2C_TransferRepeatedStartFlag)
+        {
+            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction);
+        }
+        else
+        {
+            result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction);
+        }
+    }
+
+    if (result == kStatus_Success)
+    {
+        if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
+        {
+            /* Transmit data. */
+            result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
+        }
+        else
+        {
+            if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
+            {
+                /* Receive Data. */
+                result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
+            }
+        }
+    }
+
+    if (result == kStatus_I2C_Nak)
+    {
+        I2C_MasterStop(base);
+    }
+
+    return result;
+}
+
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData)
+{
+    uint32_t instance;
+
+    assert(handle);
+
+    /* Clear out the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Save base and instance. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+    EnableIRQ(s_i2cIRQ[instance]);
+}
+
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result;
+
+    assert(handle);
+    assert(xfer);
+    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->state != kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+    /* Prepare transfer state machine. */
+    result = I2C_InitTransferStateMachine(base, handle, xfer);
+
+    /* Clear error flags. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    /* Enable I2C internal IRQ sources. */
+    I2C_EnableInterrupts(base, kI2C_MasterIrqFlags);
+
+    return result;
+}
+
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == kIdleState)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* There is no necessity to disable interrupts as we read a single integer value */
+    *count = handle->transferCount;
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    uint32_t status;
+    uint32_t master_state;
+
+    if (handle->state != kIdleState)
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+        /* Wait until module is ready */
+        status = I2C_PendingStatusWait(base);
+
+        /* Get the state of the I2C module */
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+        if (master_state != I2C_STAT_MSTCODE_IDLE)
+        {
+            /* Send a stop command to finalize the transfer. */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+
+            /* Wait until the STOP is completed */
+            I2C_PendingStatusWait(base);
+        }
+
+        /* Reset handle. */
+        handle->state = kIdleState;
+    }
+}
+
+/*!
+ * @brief Prepares the transfer state machine and fills in the command buffer.
+ * @param handle Master nonblocking driver handle.
+ */
+static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    struct _i2c_master_transfer *transfer;
+
+    handle->transfer = *xfer;
+    transfer = &(handle->transfer);
+
+    handle->transferCount = 0;
+    handle->remainingBytes = transfer->dataSize;
+    handle->buf = (uint8_t *)transfer->data;
+    handle->remainingSubaddr = 0;
+
+    if (transfer->flags & kI2C_TransferNoStartFlag)
+    {
+        /* Start condition shall be ommited, switch directly to next phase */
+        if (transfer->dataSize == 0)
+        {
+            handle->state = kStopState;
+        }
+        else if (handle->transfer.direction == kI2C_Write)
+        {
+            handle->state = kTransmitDataState;
+        }
+        else if (handle->transfer.direction == kI2C_Read)
+        {
+            handle->state = kReceiveDataState;
+        }
+        else
+        {
+            return kStatus_I2C_InvalidParameter;
+        }
+    }
+    else
+    {
+        if (transfer->subaddressSize != 0)
+        {
+            int i;
+            uint32_t subaddress;
+
+            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
+            {
+                return kStatus_I2C_InvalidParameter;
+            }
+
+            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+            subaddress = xfer->subaddress;
+            for (i = xfer->subaddressSize - 1; i >= 0; i--)
+            {
+                handle->subaddrBuf[i] = subaddress & 0xff;
+                subaddress >>= 8;
+            }
+            handle->remainingSubaddr = transfer->subaddressSize;
+        }
+        handle->state = kStartState;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Execute states until FIFOs are exhausted.
+ * @param handle Master nonblocking driver handle.
+ * @param[out] isDone Set to true if the transfer has completed.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_ArbitrationLost
+ * @retval #kStatus_I2C_Nak
+ */
+static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
+{
+    uint32_t status;
+    uint32_t master_state;
+    struct _i2c_master_transfer *transfer;
+    status_t err;
+
+    transfer = &(handle->transfer);
+
+    *isDone = false;
+
+    status = I2C_GetStatusFlags(base);
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
+        return kStatus_I2C_StartStopError;
+    }
+
+    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Get the state of the I2C module */
+    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
+    {
+        /* Slave NACKed last byte, issue stop and return error */
+        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+        handle->state = kWaitForCompletionState;
+        return kStatus_I2C_Nak;
+    }
+
+    err = kStatus_Success;
+    switch (handle->state)
+    {
+        case kStartState:
+            if (handle->remainingSubaddr)
+            {
+                /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */
+                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+                handle->state = kTransmitSubaddrState;
+            }
+            else if (transfer->direction == kI2C_Write)
+            {
+                base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+                handle->state = handle->remainingBytes ? kTransmitDataState : kStopState;
+            }
+            else
+            {
+                base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
+                handle->state = handle->remainingBytes ? kReceiveDataState : kStopState;
+            }
+            /* Send start condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+            break;
+
+        case kTransmitSubaddrState:
+            if (master_state != I2C_STAT_MSTCODE_TXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            /* Most significant subaddress byte comes first */
+            base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr];
+            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            if (--(handle->remainingSubaddr))
+            {
+                /* There are still subaddress bytes to be transmitted */
+                break;
+            }
+            if (handle->remainingBytes)
+            {
+                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
+                 * repeated start */
+                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
+            }
+            else
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            break;
+
+        case kTransmitDataState:
+            if (master_state != I2C_STAT_MSTCODE_TXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+            base->MSTDAT = *(handle->buf)++;
+            base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            if (--handle->remainingBytes == 0)
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            handle->transferCount++;
+            break;
+
+        case kReceiveDataState:
+            if (master_state != I2C_STAT_MSTCODE_RXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+            *(handle->buf)++ = base->MSTDAT;
+            if (--handle->remainingBytes)
+            {
+                base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK;
+            }
+            else
+            {
+                /* No more data expected, issue NACK and STOP right away */
+                base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+                handle->state = kWaitForCompletionState;
+            }
+            handle->transferCount++;
+            break;
+
+        case kStopState:
+            if (transfer->flags & kI2C_TransferNoStopFlag)
+            {
+                /* Stop condition is omitted, we are done */
+                *isDone = true;
+                handle->state = kIdleState;
+                break;
+            }
+            /* Send stop condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kWaitForCompletionState:
+            *isDone = true;
+            handle->state = kIdleState;
+            break;
+
+        case kIdleState:
+        default:
+            /* State machine shall not be invoked again once it enters the idle state */
+            err = kStatus_I2C_UnexpectedState;
+            break;
+    }
+
+    return err;
+}
+
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle)
+{
+    bool isDone;
+    status_t result;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    result = I2C_RunTransferStateMachine(base, handle, &isDone);
+
+    if (isDone || (result != kStatus_Success))
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base, kI2C_MasterIrqFlags);
+
+        /* Invoke callback. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+/*!
+ * @brief Sets the hardware slave state machine to reset
+ *
+ * Per documentation, the only the state machine is reset, the configuration settings remain.
+ *
+ * @param base The I2C peripheral base address.
+ */
+static void I2C_SlaveInternalStateMachineReset(I2C_Type *base)
+{
+    I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */
+}
+
+/*!
+ * @brief Compute CLKDIV
+ *
+ * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency.
+ * This setting is used by hardware during slave clock stretching.
+ *
+ * @param base The I2C peripheral base address.
+ * @return status of the operation
+ */
+static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal)
+{
+    uint32_t dataSetupTime_ns;
+
+    switch (busSpeed)
+    {
+        case kI2C_SlaveStandardMode:
+            dataSetupTime_ns = 250u;
+            break;
+
+        case kI2C_SlaveFastMode:
+            dataSetupTime_ns = 100u;
+            break;
+
+        case kI2C_SlaveFastModePlus:
+            dataSetupTime_ns = 50u;
+            break;
+
+        case kI2C_SlaveHsMode:
+            dataSetupTime_ns = 10u;
+            break;
+
+        default:
+            dataSetupTime_ns = 0;
+            break;
+    }
+
+    if (0 == dataSetupTime_ns)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */
+    *divVal = srcClock_Hz / 1000u;
+    *divVal = (*divVal) * dataSetupTime_ns;
+    *divVal = (*divVal) / 1000000u;
+
+    if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK)
+    {
+        *divVal = I2C_CLKDIV_DIVVAL_MASK;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Poll wait for the SLVPENDING flag.
+ *
+ * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register.
+ *
+ * @param base The I2C peripheral base address.
+ * @return status register at time the SLVPENDING bit is read as set
+ */
+static uint32_t I2C_SlavePollPending(I2C_Type *base)
+{
+    uint32_t stat;
+
+    do
+    {
+        stat = base->STAT;
+    } while (0u == (stat & I2C_STAT_SLVPENDING_MASK));
+
+    return stat;
+}
+
+/*!
+ * @brief Invoke event from I2C_SlaveTransferHandleIRQ().
+ *
+ * Sets the event type to transfer structure and invokes the event callback, if it has been
+ * enabled by eventMask.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle The I2C slave handle for non-blocking APIs.
+ * @param event The I2C slave event to invoke.
+ */
+static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event)
+{
+    handle->transfer.event = event;
+    if ((handle->callback) && (handle->transfer.eventMask & event))
+    {
+        handle->callback(base, &handle->transfer, handle->userData);
+
+        /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */
+        if (false == handle->isBusy)
+        {
+            if (((handle->transfer.txData) && (handle->transfer.txSize)) ||
+                ((handle->transfer.rxData) && (handle->transfer.rxSize)))
+            {
+                handle->isBusy = true;
+            }
+        }
+
+        /* Clear the transferred count now that we have a new buffer. */
+        if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent))
+        {
+            handle->transfer.transferredCount = 0;
+        }
+    }
+}
+
+/*!
+ * @brief Handle slave address match event.
+ *
+ * Called by Slave interrupt routine to ACK or NACK the matched address.
+ * It also determines master direction (read or write).
+ *
+ * @param base The I2C peripheral base address.
+ * @return true if the matched address is ACK'ed
+ * @return false if the matched address is NACK'ed
+ */
+static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    uint8_t addressByte0;
+
+    addressByte0 = (uint8_t)base->SLVDAT;
+
+    /* store the matched address */
+    handle->transfer.receivedAddress = addressByte0;
+
+    /* R/nW */
+    if (addressByte0 & 1u)
+    {
+        /* if we have no data in this transfer, call callback to get new */
+        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+        {
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
+        }
+
+        /* NACK if we have no data in this transfer. */
+        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+        {
+            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+            return false;
+        }
+
+        /* master wants to read, so slave transmit is next state */
+        handle->slaveFsm = kI2C_SlaveFsmTransmit;
+    }
+    else
+    {
+        /* if we have no receive buffer in this transfer, call callback to get new */
+        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+        {
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
+        }
+
+        /* NACK if we have no data in this transfer */
+        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+        {
+            base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+            return false;
+        }
+
+        /* master wants write, so slave receive is next state */
+        handle->slaveFsm = kI2C_SlaveFsmReceive;
+    }
+
+    /* continue transaction */
+    base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+    return true;
+}
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
+ * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only.
+ * @param txSize Size of txData buffer in bytes.
+ * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL
+ *               if slave TX only.
+ * @param rxSize Size of rxData buffer in bytes.
+ *
+ * @retval #kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base,
+                                                     i2c_slave_handle_t *handle,
+                                                     const void *txData,
+                                                     size_t txSize,
+                                                     void *rxData,
+                                                     size_t rxSize,
+                                                     uint32_t eventMask)
+{
+    status_t status;
+
+    assert(handle);
+
+    status = kStatus_Success;
+
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->isBusy)
+    {
+        status = kStatus_I2C_Busy;
+    }
+
+    /* Save transfer into handle. */
+    handle->transfer.txData = (const uint8_t *)(uintptr_t)txData;
+    handle->transfer.txSize = txSize;
+    handle->transfer.rxData = (uint8_t *)rxData;
+    handle->transfer.rxSize = rxSize;
+    handle->transfer.transferredCount = 0;
+    handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent;
+    handle->isBusy = true;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* Clear w1c flags. */
+    base->STAT |= 0u;
+
+    /* Enable I2C internal IRQ sources. */
+    I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    return status;
+}
+
+status_t I2C_SlaveSetSendBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask);
+}
+
+status_t I2C_SlaveSetReceiveBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask);
+}
+
+void I2C_SlaveSetAddress(I2C_Type *base,
+                         i2c_slave_address_register_t addressRegister,
+                         uint8_t address,
+                         bool addressDisable)
+{
+    base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable);
+}
+
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
+{
+    assert(slaveConfig);
+
+    i2c_slave_config_t mySlaveConfig = {0};
+
+    /* default config enables slave address 0 match to general I2C call address zero */
+    mySlaveConfig.enableSlave = true;
+    mySlaveConfig.address1.addressDisable = true;
+    mySlaveConfig.address2.addressDisable = true;
+    mySlaveConfig.address3.addressDisable = true;
+
+    *slaveConfig = mySlaveConfig;
+}
+
+status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
+{
+    status_t status;
+    uint32_t divVal = 0;
+
+    /* configure data setup time used when slave stretches clock */
+    status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C);
+
+    /* I2C Clock Divider register */
+    base->CLKDIV = divVal;
+
+    /* set Slave address */
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address,
+                        slaveConfig->address0.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address,
+                        slaveConfig->address1.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address,
+                        slaveConfig->address2.addressDisable);
+    I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address,
+                        slaveConfig->address3.addressDisable);
+
+    /* set Slave address 0 qual */
+    base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress);
+
+    /* set Slave enable */
+    base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave);
+
+    return status;
+}
+
+void I2C_SlaveDeinit(I2C_Type *base)
+{
+    I2C_SlaveEnable(base, false);
+}
+
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+{
+    const uint8_t *buf = txBuff;
+    uint32_t stat;
+    bool slaveAddress;
+    bool slaveTransmit;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* wait for SLVPENDING */
+    stat = I2C_SlavePollPending(base);
+
+    /* Get slave machine state */
+    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+    slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+    /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */
+    if (!(slaveAddress || slaveTransmit))
+    {
+        I2C_SlaveInternalStateMachineReset(base);
+        return kStatus_Fail;
+    }
+
+    if (slaveAddress)
+    {
+        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* wait for SLVPENDING */
+        stat = I2C_SlavePollPending(base);
+    }
+
+    /* send bytes up to txSize */
+    while (txSize)
+    {
+        slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+        if (!slaveTransmit)
+        {
+            I2C_SlaveInternalStateMachineReset(base);
+            return kStatus_Fail;
+        }
+
+        /* Write 8 bits of data to the SLVDAT register */
+        base->SLVDAT = I2C_SLVDAT_DATA(*buf);
+
+        /* continue transaction */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* advance counters and pointers for next data */
+        buf++;
+        txSize--;
+
+        if (txSize)
+        {
+            /* wait for SLVPENDING */
+            stat = I2C_SlavePollPending(base);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+{
+    uint8_t *buf = rxBuff;
+    uint32_t stat;
+    bool slaveAddress;
+    bool slaveReceive;
+
+    /* Set the SLVEN bit to 1 in the CFG register. */
+    I2C_SlaveEnable(base, true);
+
+    /* wait for SLVPENDING */
+    stat = I2C_SlavePollPending(base);
+
+    /* Get slave machine state */
+    slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+    slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+    /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */
+    if (!(slaveAddress || slaveReceive))
+    {
+        I2C_SlaveInternalStateMachineReset(base);
+        return kStatus_Fail;
+    }
+
+    if (slaveAddress)
+    {
+        /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* wait for SLVPENDING */
+        stat = I2C_SlavePollPending(base);
+    }
+
+    /* receive bytes up to rxSize */
+    while (rxSize)
+    {
+        slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+        if (!slaveReceive)
+        {
+            I2C_SlaveInternalStateMachineReset(base);
+            return kStatus_Fail;
+        }
+
+        /* Read 8 bits of data from the SLVDAT register */
+        *buf = (uint8_t)base->SLVDAT;
+
+        /* continue transaction */
+        base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+
+        /* advance counters and pointers for next data */
+        buf++;
+        rxSize--;
+
+        if (rxSize)
+        {
+            /* wait for SLVPENDING */
+            stat = I2C_SlavePollPending(base);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData)
+{
+    uint32_t instance;
+
+    assert(handle);
+
+    /* Clear out the handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Save base and instance. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* initialize fsm */
+    handle->slaveFsm = kI2C_SlaveFsmAddressMatch;
+
+    /* store pointer to handle into transfer struct */
+    handle->transfer.handle = handle;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_SlaveTransferHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+    EnableIRQ(s_i2cIRQ[instance]);
+}
+
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
+{
+    return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask);
+}
+
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (!handle->isBusy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* For an active transfer, just return the count from the handle. */
+    *count = handle->transfer.transferredCount;
+
+    return kStatus_Success;
+}
+
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    /* Disable I2C IRQ sources while we configure stuff. */
+    I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags);
+
+    /* Set the SLVEN bit to 0 in the CFG register. */
+    I2C_SlaveEnable(base, false);
+
+    handle->isBusy = false;
+    handle->transfer.txSize = 0;
+    handle->transfer.rxSize = 0;
+}
+
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+    uint32_t i2cStatus = base->STAT;
+
+    if (i2cStatus & I2C_STAT_SLVDESEL_MASK)
+    {
+        I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent);
+        I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK);
+    }
+
+    /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */
+    if (i2cStatus & I2C_STAT_SLVPENDING_MASK)
+    {
+        bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
+
+        if (slaveAddress)
+        {
+            I2C_SlaveAddressIRQ(base, handle);
+            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent);
+        }
+        else
+        {
+            switch (handle->slaveFsm)
+            {
+                case kI2C_SlaveFsmReceive:
+                {
+                    bool slaveReceive =
+                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX);
+
+                    if (slaveReceive)
+                    {
+                        /* if we have no receive buffer in this transfer, call callback to get new */
+                        if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0))
+                        {
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent);
+                        }
+
+                        /* receive a byte */
+                        if ((handle->transfer.rxData) && (handle->transfer.rxSize))
+                        {
+                            *(handle->transfer.rxData) = (uint8_t)base->SLVDAT;
+                            (handle->transfer.rxSize)--;
+                            (handle->transfer.rxData)++;
+                            (handle->transfer.transferredCount)++;
+
+                            /* continue transaction */
+                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+                        }
+
+                        /* is this last transaction for this transfer? allow next transaction */
+                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
+                        {
+                            handle->isBusy = false;
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
+                        }
+                    }
+                    else
+                    {
+                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+                    }
+                }
+                break;
+
+                case kI2C_SlaveFsmTransmit:
+                {
+                    bool slaveTransmit =
+                        (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX);
+
+                    if (slaveTransmit)
+                    {
+                        /* if we have no data in this transfer, call callback to get new */
+                        if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0))
+                        {
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent);
+                        }
+
+                        /* transmit a byte */
+                        if ((handle->transfer.txData) && (handle->transfer.txSize))
+                        {
+                            base->SLVDAT = *(handle->transfer.txData);
+                            (handle->transfer.txSize)--;
+                            (handle->transfer.txData)++;
+                            (handle->transfer.transferredCount)++;
+
+                            /* continue transaction */
+                            base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK;
+                        }
+
+                        /* is this last transaction for this transfer? allow next transaction */
+                        if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize))
+                        {
+                            handle->isBusy = false;
+                            I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent);
+                        }
+                    }
+                    else
+                    {
+                        base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK;
+                    }
+                }
+                break;
+
+                default:
+                    /* incorrect state, slv_abort()? */
+                    break;
+            }
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1039 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_H_
+#define _FSL_I2C_H_
+
+#include <stddef.h>
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define I2C_CFG_MASK 0x1f
+
+/*!
+ * @addtogroup i2c_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C driver version 1.0.0. */
+#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*@}*/
+
+/* definitions for MSTCODE bits in I2C Status register STAT */
+#define I2C_STAT_MSTCODE_IDLE (0)    /*!< Master Idle State Code */
+#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
+#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */
+#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */
+#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */
+
+/* definitions for SLVSTATE bits in I2C Status register STAT */
+#define I2C_STAT_SLVST_ADDR (0)
+#define I2C_STAT_SLVST_RX (1)
+#define I2C_STAT_SLVST_TX (2)
+
+/*! @brief I2C status return codes. */
+enum _i2c_status
+{
+    kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */
+    kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */
+    kStatus_I2C_Nak =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */
+    kStatus_I2C_InvalidParameter =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */
+    kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */
+    kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */
+    kStatus_I2C_NoTransferInProgress =
+        MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */
+    kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */
+    kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8),
+    kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9),
+};
+
+/*! @} */
+
+/*!
+ * @addtogroup i2c_master_driver
+ * @{
+ */
+
+/*!
+ * @brief I2C master peripheral flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _i2c_master_flags
+{
+    kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
+    kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */
+    kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */
+};
+
+/*! @brief Direction of master and slave transfers. */
+typedef enum _i2c_direction
+{
+    kI2C_Write = 0U, /*!< Master transmit. */
+    kI2C_Read = 1U   /*!< Master receive. */
+} i2c_direction_t;
+
+/*!
+ * @brief Structure with settings to initialize the I2C master module.
+ *
+ * This structure holds configuration settings for the I2C peripheral. To initialize this
+ * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and
+ * pass a pointer to your configuration structure instance.
+ *
+ * The configuration structure can be made constant so it resides in flash.
+ */
+typedef struct _i2c_master_config
+{
+    bool enableMaster;     /*!< Whether to enable master mode. */
+    uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */
+    bool enableTimeout;    /*!< Enable internal timeout function. */
+} i2c_master_config_t;
+
+/* Forward declaration of the transfer descriptor and handle typedefs. */
+/*! @brief I2C master transfer typedef */
+typedef struct _i2c_master_transfer i2c_master_transfer_t;
+
+/*! @brief I2C master handle typedef */
+typedef struct _i2c_master_handle i2c_master_handle_t;
+
+/*!
+ * @brief Master completion callback function pointer type.
+ *
+ * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use
+ * in the call to I2C_MasterTransferCreateHandle().
+ *
+ * @param base The I2C peripheral base address.
+ * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed.
+ * @param userData Arbitrary pointer-sized value passed from the application.
+ */
+typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
+                                               i2c_master_handle_t *handle,
+                                               status_t completionStatus,
+                                               void *userData);
+
+/*!
+ * @brief Transfer option flags.
+ *
+ * @note These enumerations are intended to be OR'd together to form a bit mask of options for
+ * the #_i2c_master_transfer::flags field.
+ */
+enum _i2c_master_transfer_flags
+{
+    kI2C_TransferDefaultFlag = 0x00U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
+    kI2C_TransferNoStartFlag = 0x01U,       /*!< Don't send a start condition, address, and sub address */
+    kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
+    kI2C_TransferNoStopFlag = 0x04U,        /*!< Don't send a stop condition. */
+};
+
+/*! @brief States for the state machine used by transactional APIs. */
+enum _i2c_transfer_states
+{
+    kIdleState = 0,
+    kTransmitSubaddrState,
+    kTransmitDataState,
+    kReceiveDataState,
+    kReceiveLastDataState,
+    kStartState,
+    kStopState,
+    kWaitForCompletionState
+};
+
+/*!
+ * @brief Non-blocking transfer descriptor structure.
+ *
+ * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API.
+ */
+struct _i2c_master_transfer
+{
+    uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available
+                       options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */
+    uint16_t slaveAddress;     /*!< The 7-bit slave address. */
+    i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */
+    uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
+    size_t subaddressSize;     /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
+    void *data;                /*!< Pointer to data to transfer. */
+    size_t dataSize;           /*!< Number of bytes to transfer. */
+};
+
+/*!
+ * @brief Driver handle for master non-blocking APIs.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i2c_master_handle
+{
+    uint8_t state;           /*!< Transfer state machine current state. */
+    uint32_t transferCount;  /*!< Indicates progress of the transfer */
+    uint32_t remainingBytes; /*!< Remaining byte count in current state. */
+    uint8_t *buf;            /*!< Buffer pointer for current state. */
+    uint32_t remainingSubaddr;
+    uint8_t subaddrBuf[4];
+    i2c_master_transfer_t transfer;                    /*!< Copy of the current transfer info. */
+    i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */
+    void *userData;                                    /*!< Application data passed to callback. */
+};
+
+/*! @} */
+
+/*!
+ * @addtogroup i2c_slave_driver
+ * @{
+ */
+
+ /*!
+ * @brief I2C slave peripheral flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+enum _i2c_slave_flags
+{
+    kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
+    kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */
+    kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */
+    kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */
+};
+ 
+/*! @brief I2C slave address register. */
+typedef enum _i2c_slave_address_register
+{
+    kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */
+    kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */
+    kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */
+    kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */
+} i2c_slave_address_register_t;
+
+/*! @brief Data structure with 7-bit Slave address and Slave address disable. */
+typedef struct _i2c_slave_address
+{
+    uint8_t address;     /*!< 7-bit Slave address SLVADR. */
+    bool addressDisable; /*!< Slave address disable SADISABLE. */
+} i2c_slave_address_t;
+
+/*! @brief I2C slave address match options. */
+typedef enum _i2c_slave_address_qual_mode
+{
+    kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */
+    kI2C_QualModeExtend =
+        1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */
+} i2c_slave_address_qual_mode_t;
+
+/*! @brief I2C slave bus speed options. */
+typedef enum _i2c_slave_bus_speed
+{
+    kI2C_SlaveStandardMode = 0U,
+    kI2C_SlaveFastMode = 1U,
+    kI2C_SlaveFastModePlus = 2U,
+    kI2C_SlaveHsMode = 3U,
+} i2c_slave_bus_speed_t;
+
+/*!
+ * @brief Structure with settings to initialize the I2C slave module.
+ *
+ * This structure holds configuration settings for the I2C slave peripheral. To initialize this
+ * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and
+ * pass a pointer to your configuration structure instance.
+ *
+ * The configuration structure can be made constant so it resides in flash.
+ */
+typedef struct _i2c_slave_config
+{
+    i2c_slave_address_t address0;           /*!< Slave's 7-bit address and disable. */
+    i2c_slave_address_t address1;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_t address2;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_t address3;           /*!< Alternate slave 7-bit address and disable. */
+    i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */
+    uint8_t qualAddress;                    /*!< Slave address qualifier for address 0. */
+    i2c_slave_bus_speed_t
+        busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must
+                       provide sufficient data setup time to the master before releasing the stretched clock.
+                       This is accomplished by inserting one clock time of CLKDIV at that point.
+                       The #busSpeed value is used to configure CLKDIV
+                       such that one clock time is greater than the tSU;DAT value noted
+                       in the I2C bus specification for the I2C mode that is being used.
+                       If the #busSpeed mode is unknown at compile time, use the longest data setup time
+                       kI2C_SlaveStandardMode (250 ns) */
+    bool enableSlave; /*!< Enable slave mode. */
+} i2c_slave_config_t;
+
+/*!
+ * @brief Set of events sent to the callback for non blocking slave transfers.
+ *
+ * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
+ * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
+ * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
+ * parameter.
+ *
+ * @note These enumerations are meant to be OR'd together to form a bit mask of events.
+ */
+typedef enum _i2c_slave_transfer_event
+{
+    kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
+    kI2C_SlaveTransmitEvent = 0x02U,     /*!< Callback is requested to provide data to transmit
+                                                (slave-transmitter role). */
+    kI2C_SlaveReceiveEvent = 0x04U,      /*!< Callback is requested to provide a buffer in which to place received
+                                                 data (slave-receiver role). */
+    kI2C_SlaveCompletionEvent = 0x20U,   /*!< All data in the active transfer have been consumed. */
+    kI2C_SlaveDeselectedEvent =
+        0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */
+
+    /*! Bit mask of all available events. */
+    kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
+                          kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent,
+} i2c_slave_transfer_event_t;
+
+/*! @brief I2C slave handle typedef. */
+typedef struct _i2c_slave_handle i2c_slave_handle_t;
+
+/*! @brief I2C slave transfer structure */
+typedef struct _i2c_slave_transfer
+{
+    i2c_slave_handle_t *handle;       /*!< Pointer to handle that contains this transfer. */
+    i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
+    uint8_t receivedAddress;          /*!< Matching address send by master. 7-bits plus R/nW bit0 */
+    uint32_t eventMask;               /*!< Mask of enabled events. */
+    uint8_t *rxData;                  /*!< Transfer buffer for receive data */
+    const uint8_t *txData;            /*!< Transfer buffer for transmit data */
+    size_t txSize;                    /*!< Transfer size */
+    size_t rxSize;                    /*!< Transfer size */
+    size_t transferredCount;          /*!< Number of bytes transferred during this transfer. */
+    status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
+                                         #kI2C_SlaveCompletionEvent. */
+} i2c_slave_transfer_t;
+
+/*!
+ * @brief Slave event callback function pointer type.
+ *
+ * This callback is used only for the slave non-blocking transfer API. To install a callback,
+ * use the I2C_SlaveSetCallback() function after you have created a handle.
+ *
+ * @param base Base address for the I2C instance on which the event occurred.
+ * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
+ * @param userData Arbitrary pointer-sized value passed from the application.
+ */
+typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData);
+
+/*!
+ * @brief I2C slave software finite state machine states.
+ */
+typedef enum _i2c_slave_fsm
+{
+    kI2C_SlaveFsmAddressMatch = 0u,
+    kI2C_SlaveFsmReceive = 2u,
+    kI2C_SlaveFsmTransmit = 3u,
+} i2c_slave_fsm_t;
+
+/*!
+ * @brief I2C slave handle structure.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i2c_slave_handle
+{
+    volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */
+    volatile bool isBusy;                   /*!< Whether transfer is busy. */
+    volatile i2c_slave_fsm_t slaveFsm;      /*!< slave transfer state machine. */
+    i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
+    void *userData;                         /*!< Callback parameter passed to callback. */
+};
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup i2c_master_driver
+ * @{
+ */
+
+/*! @name Initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Provides a default configuration for the I2C master peripheral.
+ *
+ * This function provides the following default configuration for the I2C master peripheral:
+ * @code
+ *  masterConfig->enableMaster            = true;
+ *  masterConfig->baudRate_Bps            = 100000U;
+ *  masterConfig->enableTimeout           = false;
+ * @endcode
+ *
+ * After calling this function, you can override any settings in order to customize the configuration,
+ * prior to initializing the master driver with I2C_MasterInit().
+ *
+ * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t.
+ */
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief Initializes the I2C master peripheral.
+ *
+ * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user
+ * provided configuration. A software reset is performed prior to configuration.
+ *
+ * @param base The I2C peripheral base address.
+ * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of
+ * defaults
+ *      that you can override.
+ * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors,
+ *      filter widths, and timeout periods.
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
+
+/*!
+* @brief Deinitializes the I2C master peripheral.
+*
+ * This function disables the I2C master peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+void I2C_MasterDeinit(I2C_Type *base);
+
+/*!
+ * @brief Performs a software reset.
+ *
+ * Restores the I2C master peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+static inline void I2C_MasterReset(I2C_Type *base)
+{
+}
+
+/*!
+ * @brief Enables or disables the I2C module as master.
+ *
+ * @param base The I2C peripheral base address.
+ * @param enable Pass true to enable or false to disable the specified I2C as master.
+ */
+static inline void I2C_MasterEnable(I2C_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK;
+    }
+    else
+    {
+        base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK;
+    }
+}
+
+/*@}*/
+
+/*! @name Status */
+/*@{*/
+
+/*!
+ * @brief Gets the I2C status flags.
+ *
+ * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit
+ * in the return value is set if the flag is asserted.
+ *
+ * @param base The I2C peripheral base address.
+ * @return State of the status flags:
+ *         - 1: related status flag is set.
+ *         - 0: related status flag is not set.
+ * @see _i2c_master_flags
+ */
+static inline uint32_t I2C_GetStatusFlags(I2C_Type *base)
+{
+    return base->STAT;
+}
+
+/*!
+ * @brief Clears the I2C master status flag state.
+ *
+ * The following status register flags can be cleared:
+ * - #kI2C_MasterArbitrationLostFlag
+ * - #kI2C_MasterStartStopErrorFlag
+ *
+ * Attempts to clear other flags has no effect.
+ *
+ * @param base The I2C peripheral base address.
+ * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
+ *  #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  I2C_GetStatusFlags().
+ * @see _i2c_master_flags.
+ */
+static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    /* Allow clearing just master status flags */
+    base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+}
+
+/*@}*/
+
+/*! @name Interrupts */
+/*@{*/
+
+/*!
+ * @brief Enables the I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask)
+{
+    base->INTENSET = interruptMask;
+}
+
+/*!
+ * @brief Disables the I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask)
+{
+    base->INTENCLR = interruptMask;
+}
+
+/*!
+ * @brief Returns the set of currently enabled I2C master interrupt requests.
+ *
+ * @param base The I2C peripheral base address.
+ * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the
+ *      set of enabled interrupts.
+ */
+static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base)
+{
+    return base->INTSTAT;
+}
+
+/*@}*/
+
+/*! @name Bus operations */
+/*@{*/
+
+/*!
+ * @brief Sets the I2C bus frequency for master transactions.
+ *
+ * The I2C master is automatically disabled and re-enabled as necessary to configure the baud
+ * rate. Do not call this function during a transfer, or the transfer is aborted.
+ *
+ * @param base The I2C peripheral base address.
+ * @param srcClock_Hz I2C functional clock frequency in Hertz.
+ * @param baudRate_Bps Requested bus frequency in bits per second.
+ */
+void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Returns whether the bus is idle.
+ *
+ * Requires the master mode to be enabled.
+ *
+ * @param base The I2C peripheral base address.
+ * @retval true Bus is busy.
+ * @retval false Bus is idle.
+ */
+static inline bool I2C_MasterGetBusIdleState(I2C_Type *base)
+{
+    /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */
+    return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK);
+}
+
+/*!
+ * @brief Sends a START on the I2C bus.
+ *
+ * This function is used to initiate a new master mode transfer by sending the START signal.
+ * The slave address is sent following the I2C START signal.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy.
+ */
+status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
+
+/*!
+ * @brief Sends a STOP signal on the I2C bus.
+ *
+ * @retval kStatus_Success Successfully send the stop signal.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterStop(I2C_Type *base);
+
+/*!
+ * @brief Sends a REPEATED START on the I2C bus.
+ *
+ * @param base I2C peripheral base pointer
+ * @param address 7-bit slave device address.
+ * @param direction Master transfer directions(transmit/receive).
+ * @retval kStatus_Success Successfully send the start signal.
+ * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
+ */
+static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
+{
+    return I2C_MasterStart(base, address, direction);
+}
+
+/*!
+ * @brief Performs a polling send transfer on the I2C bus.
+ *
+ * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may
+ * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
+ * function returns #kStatus_I2C_Nak.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @retval kStatus_Success Data was sent successfully.
+ * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
+ * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
+ * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags);
+
+/*!
+ * @brief Performs a polling receive transfer on the I2C bus.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param rxBuff The pointer to the data to be transferred.
+ * @param rxSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @retval kStatus_Success Data was received successfully.
+ * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
+ * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
+ * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags);
+
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due
+ * to arbitration lost or receiving a NAK.
+ *
+ * @param base I2C peripheral base address.
+ * @param xfer Pointer to the transfer structure.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
+
+/*@}*/
+
+/*! @name Non-blocking */
+/*@{*/
+
+/*!
+ * @brief Creates a new handle for the I2C master non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I2C_MasterTransferAbort() API shall be called.
+ *
+ * @param base The I2C peripheral base address.
+ * @param[out] handle Pointer to the I2C master driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+                                    i2c_master_handle_t *handle,
+                                    i2c_master_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Performs a non-blocking transaction on the I2C bus.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @param xfer The pointer to the transfer descriptor.
+ * @retval kStatus_Success The transaction was started successfully.
+ * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking
+ *      transaction is already in progress.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Returns number of bytes transferred so far.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @param[out] count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_Success
+ * @retval #kStatus_I2C_Busy
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Terminates a non-blocking I2C master transmission early.
+ *
+ * @note It is not safe to call this function from an IRQ handler that has a higher priority than the
+ *      I2C peripheral's IRQ priority.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ * @retval kStatus_Success A transaction was successfully aborted.
+ * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress.
+ */
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*@}*/
+
+/*! @name IRQ handler */
+/*@{*/
+
+/*!
+ * @brief Reusable routine to handle master interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  nonblocking API's interrupt handler routines to add special functionality.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to the I2C master driver handle.
+ */
+void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*@}*/
+
+/*! @} */ /* end of i2c_master_driver */
+
+/*!
+ * @addtogroup i2c_slave_driver
+ * @{
+ */
+
+/*! @name Slave initialization and deinitialization */
+/*@{*/
+
+/*!
+ * @brief Provides a default configuration for the I2C slave peripheral.
+ *
+ * This function provides the following default configuration for the I2C slave peripheral:
+ * @code
+ *  slaveConfig->enableSlave = true;
+ *  slaveConfig->address0.disable = false;
+ *  slaveConfig->address0.address = 0u;
+ *  slaveConfig->address1.disable = true;
+ *  slaveConfig->address2.disable = true;
+ *  slaveConfig->address3.disable = true;
+ *  slaveConfig->busSpeed = kI2C_SlaveStandardMode;
+ * @endcode
+ *
+ * After calling this function, override any settings  to customize the configuration,
+ * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a
+ * address0.address member of the configuration structure with the desired slave address.
+ *
+ * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to
+ *      #i2c_slave_config_t.
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Initializes the I2C slave peripheral.
+ *
+ * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user
+ * provided configuration.
+ *
+ * @param base The I2C peripheral base address.
+ * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults
+ *      that you can override.
+ * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide
+ * enough
+ *                       data setup time for master when slave stretches the clock.
+ */
+status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Configures Slave Address n register.
+ *
+ * This function writes new value to Slave Address register.
+ *
+ * @param base The I2C peripheral base address.
+ * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed.
+ * @param address The slave address to be stored to the address register for matching.
+ * @param addressDisable Disable matching of the specified address register.
+  */
+void I2C_SlaveSetAddress(I2C_Type *base,
+                         i2c_slave_address_register_t addressRegister,
+                         uint8_t address,
+                         bool addressDisable);
+
+/*!
+* @brief Deinitializes the I2C slave peripheral.
+*
+ * This function disables the I2C slave peripheral and gates the clock. It also performs a software
+ * reset to restore the peripheral to reset conditions.
+ *
+ * @param base The I2C peripheral base address.
+ */
+void I2C_SlaveDeinit(I2C_Type *base);
+
+/*!
+ * @brief Enables or disables the I2C module as slave.
+ *
+ * @param base The I2C peripheral base address.
+ * @param enable True to enable or flase to disable.
+ */
+static inline void I2C_SlaveEnable(I2C_Type *base, bool enable)
+{
+    /* Set or clear the SLVEN bit in the CFG register. */
+    base->CFG = I2C_CFG_SLVEN(enable);
+}
+
+/*@}*/ /* end of Slave initialization and deinitialization */
+
+/*! @name Slave status */
+/*@{*/
+
+/*!
+ * @brief Clears the I2C status flag state.
+ *
+ * The following status register flags can be cleared:
+ * - slave deselected flag
+ *
+ * Attempts to clear other flags has no effect.
+ *
+ * @param base The I2C peripheral base address.
+ * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
+ *  #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
+ *  I2C_SlaveGetStatusFlags().
+ * @see _i2c_slave_flags.
+ */
+static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)
+{
+    /* Allow clearing just slave status flags */
+    base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK;
+}
+
+/*@}*/ /* end of Slave status */
+
+/*! @name Slave bus operations */
+/*@{*/
+
+/*!
+ * @brief Performs a polling send transfer on the I2C bus.
+ *
+ * The function executes blocking address phase and blocking data phase.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param txBuff The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @return kStatus_Success Data has been sent.
+ * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected).
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+
+/*!
+ * @brief Performs a polling receive transfer on the I2C bus.
+ *
+ * The function executes blocking address phase and blocking data phase.
+ *
+ * @param base  The I2C peripheral base address.
+ * @param rxBuff The pointer to the data to be transferred.
+ * @param rxSize The length in bytes of the data to be transferred.
+ * @return kStatus_Success Data has been received.
+ * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected).
+ */
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+
+/*@}*/ /* end of Slave bus operations */
+
+/*! @name Slave non-blocking */
+/*@{*/
+
+/*!
+ * @brief Creates a new handle for the I2C slave non-blocking APIs.
+ *
+ * The creation of a handle is for use with the non-blocking APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called.
+ *
+ * @param base The I2C peripheral base address.
+ * @param[out] handle Pointer to the I2C slave driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+                                   i2c_slave_handle_t *handle,
+                                   i2c_slave_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Starts accepting slave transfers.
+ *
+ * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
+ * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
+ * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
+ * from the interrupt context.
+ *
+ * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback.
+ * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask);
+
+/*!
+ * @brief Starts accepting master read from slave requests.
+ *
+ * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer
+ * from within the transfer callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer Pointer to #i2c_slave_transfer_t structure.
+ * @param txData Pointer to data to send to master.
+ * @param txSize Size of txData in bytes.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveSetSendBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask);
+
+/*!
+ * @brief Starts accepting master write to slave requests.
+  *
+ * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer
+ * from within the transfer callback.
+ *
+ * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
+ * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
+ * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need
+ * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
+ * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
+ * a convenient way to enable all events.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer Pointer to #i2c_slave_transfer_t structure.
+ * @param rxData Pointer to data to store data from master.
+ * @param rxSize Size of rxData in bytes.
+ * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. Other accepted values are 0 to get a default set of
+ *      only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
+ *
+ * @retval kStatus_Success Slave transfers were successfully started.
+ * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
+ */
+status_t I2C_SlaveSetReceiveBuffer(
+    I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask);
+
+/*!
+ * @brief Returns the slave address sent by the I2C master.
+ *
+ * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent.
+ *
+ * @param base The I2C peripheral base address.
+ * @param transfer The I2C slave transfer.
+ * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and
+ *      the 7-bit slave address is in the upper 7 bits.
+ */
+static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer)
+{
+    return transfer->receivedAddress;
+}
+
+/*!
+ * @brief Aborts the slave non-blocking transfers.
+ * @note This API could be called at any time to stop slave for handling the bus events.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ * @retval kStatus_Success
+ * @retval #kStatus_I2C_Idle
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*!
+ * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure.
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
+
+/*@}*/ /* end of Slave non-blocking */
+
+/*! @name Slave IRQ handler */
+/*@{*/
+
+/*!
+ * @brief Reusable routine to handle slave interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  non blocking API's interrupt handler routines to add special functionality.
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle);
+
+/*@}*/ /* end of Slave IRQ handler */
+
+/*! @} */ /* end of i2c_slave_driver */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2C_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,579 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2c_dma.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
+typedef struct _i2c_master_dma_private_handle
+{
+    I2C_Type *base;
+    i2c_master_dma_handle_t *handle;
+} i2c_master_dma_private_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA callback for I2C master DMA driver.
+ *
+ * @param handle DMA handler for I2C master DMA driver
+ * @param userData user param passed to the callback function
+ */
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
+
+/*!
+ * @brief Set up master transfer, send slave address and sub address(if any), wait until the
+ * wait until address sent status return.
+ *
+ * @param base I2C peripheral base address.
+ * @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
+ * @param xfer pointer to i2c_master_transfer_t structure.
+ */
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get the I2C instance from peripheral base address.
+ *
+ * @param base I2C peripheral base address.
+ * @return I2C instance.
+ */
+extern uint32_t I2C_GetInstance(I2C_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+/*!
+ * @brief Prepares the transfer state machine and fills in the command buffer.
+ * @param handle Master nonblocking driver handle.
+ */
+static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
+                                                i2c_master_dma_handle_t *handle,
+                                                i2c_master_transfer_t *xfer)
+{
+    struct _i2c_master_transfer *transfer;
+
+    handle->transfer = *xfer;
+    transfer = &(handle->transfer);
+
+    handle->transferCount = 0;
+    handle->remainingBytesDMA = 0;
+    handle->buf = (uint8_t *)transfer->data;
+    handle->remainingSubaddr = 0;
+
+    if (transfer->flags & kI2C_TransferNoStartFlag)
+    {
+        /* Start condition shall be ommited, switch directly to next phase */
+        if (transfer->dataSize == 0)
+        {
+            handle->state = kStopState;
+        }
+        else if (handle->transfer.direction == kI2C_Write)
+        {
+            handle->state = xfer->dataSize = kTransmitDataState;
+        }
+        else if (handle->transfer.direction == kI2C_Read)
+        {
+            handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState;
+        }
+        else
+        {
+            return kStatus_I2C_InvalidParameter;
+        }
+    }
+    else
+    {
+        if (transfer->subaddressSize != 0)
+        {
+            int i;
+            uint32_t subaddress;
+
+            if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
+            {
+                return kStatus_I2C_InvalidParameter;
+            }
+
+            /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
+            subaddress = xfer->subaddress;
+            for (i = xfer->subaddressSize - 1; i >= 0; i--)
+            {
+                handle->subaddrBuf[i] = subaddress & 0xff;
+                subaddress >>= 8;
+            }
+            handle->remainingSubaddr = transfer->subaddressSize;
+        }
+
+        handle->state = kStartState;
+    }
+
+    return kStatus_Success;
+}
+
+static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    int transfer_size;
+    dma_transfer_config_t xferConfig;
+
+    /* Update transfer count */
+    handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data;
+
+    /* Check if there is anything to be transferred at all */
+    if (handle->remainingBytesDMA == 0)
+    {
+        /* No data to be transferrred, disable DMA */
+        base->MSTCTL = 0;
+        return;
+    }
+
+    /* Calculate transfer size */
+    transfer_size = handle->remainingBytesDMA;
+    if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
+    {
+        transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
+    }
+
+    switch (handle->transfer.direction)
+    {
+        case kI2C_Write:
+            DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size,
+                                kDMA_MemoryToPeripheral, NULL);
+            break;
+
+        case kI2C_Read:
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size,
+                                kDMA_PeripheralToMemory, NULL);
+            break;
+
+        default:
+            /* This should never happen */
+            assert(0);
+            break;
+    }
+
+    DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+    DMA_StartTransfer(handle->dmaHandle);
+
+    handle->remainingBytesDMA -= transfer_size;
+    handle->buf += transfer_size;
+}
+
+/*!
+ * @brief Execute states until the transfer is done.
+ * @param handle Master nonblocking driver handle.
+ * @param[out] isDone Set to true if the transfer has completed.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_ArbitrationLost
+ * @retval #kStatus_I2C_Nak
+ */
+static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
+{
+    uint32_t status;
+    uint32_t master_state;
+    struct _i2c_master_transfer *transfer;
+    dma_transfer_config_t xferConfig;
+    status_t err;
+    uint32_t start_flag = 0;
+
+    transfer = &(handle->transfer);
+
+    *isDone = false;
+
+    status = I2C_GetStatusFlags(base);
+
+    if (status & I2C_STAT_MSTARBLOSS_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_ArbitrationLost;
+    }
+
+    if (status & I2C_STAT_MSTSTSTPERR_MASK)
+    {
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = 0;
+        return kStatus_I2C_StartStopError;
+    }
+
+    if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Get the state of the I2C module */
+    master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+    if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
+    {
+        /* Slave NACKed last byte, issue stop and return error */
+        DMA_AbortTransfer(handle->dmaHandle);
+        base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+        handle->state = kWaitForCompletionState;
+        return kStatus_I2C_Nak;
+    }
+
+    err = kStatus_Success;
+
+    if (handle->state == kStartState)
+    {
+        /* set start flag for later use */
+        start_flag = I2C_MSTCTL_MSTSTART_MASK;
+
+        if (handle->remainingSubaddr)
+        {
+            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+            handle->state = kTransmitSubaddrState;
+        }
+        else if (transfer->direction == kI2C_Write)
+        {
+            base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
+            if (transfer->dataSize == 0)
+            {
+                /* No data to be transferred, initiate start and schedule stop */
+                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+                handle->state = kStopState;
+                return err;
+            }
+            handle->state = kTransmitDataState;
+        }
+        else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0))
+        {
+            base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
+            if (transfer->dataSize == 1)
+            {
+                /* The very last byte is always received by means of SW */
+                base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+                handle->state = kReceiveLastDataState;
+                return err;
+            }
+            handle->state = kReceiveDataState;
+        }
+        else
+        {
+            handle->state = kIdleState;
+            err = kStatus_I2C_UnexpectedState;
+            return err;
+        }
+    }
+
+    switch (handle->state)
+    {
+        case kTransmitSubaddrState:
+            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+
+            /* Prepare and submit DMA transfer. */
+            DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
+                                handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
+            DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+
+            handle->remainingSubaddr = 0;
+            if (transfer->dataSize)
+            {
+                /* There is data to be transferred, if there is write to read turnaround it is necessary to perform
+                 * repeated start */
+                handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
+            }
+            else
+            {
+                /* No more data, schedule stop condition */
+                handle->state = kStopState;
+            }
+            break;
+
+        case kTransmitDataState:
+            if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+            handle->remainingBytesDMA = handle->transfer.dataSize;
+
+            I2C_RunDMATransfer(base, handle);
+
+            /* Schedule stop condition */
+            handle->state = kStopState;
+            break;
+
+        case kReceiveDataState:
+            if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag))
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
+            handle->remainingBytesDMA = handle->transfer.dataSize - 1;
+
+            I2C_RunDMATransfer(base, handle);
+
+            /* Schedule reception of last data byte */
+            handle->state = kReceiveLastDataState;
+            break;
+
+        case kReceiveLastDataState:
+            if (master_state != I2C_STAT_MSTCODE_RXREADY)
+            {
+                return kStatus_I2C_UnexpectedState;
+            }
+
+            ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT;
+            handle->transferCount++;
+
+            /* No more data expected, issue NACK and STOP right away */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kStopState:
+            if (transfer->flags & kI2C_TransferNoStopFlag)
+            {
+                /* Stop condition is omitted, we are done */
+                *isDone = true;
+                handle->state = kIdleState;
+                break;
+            }
+            /* Send stop condition */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+            handle->state = kWaitForCompletionState;
+            break;
+
+        case kWaitForCompletionState:
+            *isDone = true;
+            handle->state = kIdleState;
+            break;
+
+        case kStartState:
+        case kIdleState:
+        default:
+            /* State machine shall not be invoked again once it enters the idle state */
+            err = kStatus_I2C_UnexpectedState;
+            break;
+    }
+
+    return err;
+}
+
+void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    bool isDone;
+    status_t result;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
+
+    if (isDone || (result != kStatus_Success))
+    {
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base,
+                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+
+        /* Invoke callback. */
+        if (handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, result, handle->userData);
+        }
+    }
+}
+
+static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
+{
+    i2c_master_dma_private_handle_t *dmaPrivateHandle;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (!handle)
+    {
+        return;
+    }
+
+    dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
+    I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle);
+}
+
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle)
+{
+    uint32_t instance;
+
+    assert(handle);
+    assert(dmaHandle);
+
+    /* Zero handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I2C_GetInstance(base);
+
+    /* Set the user callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2C_MasterTransferDMAHandleIRQ, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I2C_DisableInterrupts(base,
+                          I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+    EnableIRQ(s_i2cIRQ[instance]);
+
+    /* Set the handle for DMA. */
+    handle->dmaHandle = dmaHandle;
+
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    DMA_SetCallback(dmaHandle, (dma_callback)(uintptr_t)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
+}
+
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+    status_t result;
+
+    assert(handle);
+    assert(xfer);
+    assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->state != kIdleState)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    /* Prepare transfer state machine. */
+    result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
+
+    /* Clear error flags. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    /* Enable I2C internal IRQ sources */
+    I2C_EnableInterrupts(base,
+                         I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
+
+    return result;
+}
+
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == kIdleState)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* There is no necessity to disable interrupts as we read a single integer value */
+    *count = handle->transferCount;
+    return kStatus_Success;
+}
+
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
+{
+    uint32_t status;
+    uint32_t master_state;
+
+    if (handle->state != kIdleState)
+    {
+        DMA_AbortTransfer(handle->dmaHandle);
+
+        /* Disable DMA */
+        base->MSTCTL = 0;
+
+        /* Disable internal IRQ enables. */
+        I2C_DisableInterrupts(base,
+                              I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
+
+        /* Wait until module is ready */
+        do
+        {
+            status = I2C_GetStatusFlags(base);
+        } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+        /* Clear controller state. */
+        I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+        /* Get the state of the I2C module */
+        master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
+
+        if (master_state != I2C_STAT_MSTCODE_IDLE)
+        {
+            /* Send a stop command to finalize the transfer. */
+            base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+
+            /* Wait until module is ready */
+            do
+            {
+                status = I2C_GetStatusFlags(base);
+            } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+            /* Clear controller state. */
+            I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+        }
+
+        /* Reset the state to idle. */
+        handle->state = kIdleState;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2C_DMA_H_
+#define _FSL_I2C_DMA_H_
+
+#include "fsl_i2c.h"
+#include "fsl_dma.h"
+
+/*!
+ * @addtogroup i2c_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
+#define I2C_MAX_DMA_TRANSFER_COUNT 1024
+
+/*! @brief I2C master dma handle typedef. */
+typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
+
+/*! @brief I2C master dma transfer callback typedef. */
+typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
+                                                   i2c_master_dma_handle_t *handle,
+                                                   status_t status,
+                                                   void *userData);
+
+/*! @brief I2C master dma transfer structure. */
+struct _i2c_master_dma_handle
+{
+    uint8_t state;              /*!< Transfer state machine current state. */
+    uint32_t transferCount;     /*!< Indicates progress of the transfer */
+    uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */
+    uint8_t *buf;               /*!< Buffer pointer for current state. */
+    uint32_t remainingSubaddr;
+    uint8_t subaddrBuf[4];
+    dma_handle_t *dmaHandle;                               /*!< The DMA handler used. */
+    i2c_master_transfer_t transfer;                        /*!< Copy of the current transfer info. */
+    i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
+    void *userData;                                        /*!< Callback parameter passed to callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name I2C Block DMA Transfer Operation
+ * @{
+ */
+
+/*!
+ * @brief Init the I2C handle which is used in transcational functions
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param callback pointer to user callback function
+ * @param userData user param passed to the callback function
+ * @param dmaHandle DMA handle pointer
+ */
+void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
+                                       i2c_master_dma_handle_t *handle,
+                                       i2c_master_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Performs a master dma non-blocking transfer on the I2C bus
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param xfer pointer to transfer structure of i2c_master_transfer_t
+ * @retval kStatus_Success Sucessully complete the data transmission.
+ * @retval kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
+ */
+status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Get master transfer status during a dma non-blocking transfer
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ * @param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a master dma non-blocking transfer in a early time
+ *
+ * @param base I2C peripheral base address
+ * @param handle pointer to i2c_master_dma_handle_t structure
+ */
+void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+#endif /*_FSL_I2C_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,825 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_i2s.h"
+#include "fsl_flexcomm.h"
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* TODO - absent in device header files, should be there */
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+
+/*! @brief I2S states. */
+enum _i2s_state
+{
+    kI2S_StateIdle = 0x0,             /*!< Not performing transfer */
+    kI2S_StateTx,                     /*!< Performing transmit */
+    kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */
+    kI2S_StateTxWaitForEmptyFifo,     /*!< Wait for FIFO to be flushed */
+    kI2S_StateRx,                     /*!< Performing receive */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static void I2S_Config(I2S_Type *base, const i2s_config_t *config);
+static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void I2S_TxInit(I2S_Type *base, const i2s_config_t *config)
+{
+    uint32_t cfg = 0U;
+    uint32_t trig = 0U;
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX);
+    I2S_Config(base, config);
+
+    /* Configure FIFO */
+
+    cfg |= I2S_FIFOCFG_ENABLETX(1U);                 /* enable TX FIFO */
+    cfg |= I2S_FIFOCFG_EMPTYTX(1U);                  /* empty TX FIFO */
+    cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */
+    cfg |= I2S_FIFOCFG_PACK48(config->pack48);       /* set pack 48-bit format or not */
+    trig |= I2S_FIFOTRIG_TXLVLENA(1U);               /* enable TX FIFO trigger */
+    trig |= I2S_FIFOTRIG_TXLVL(config->watermark);   /* set TX FIFO trigger level */
+
+    base->FIFOCFG = cfg;
+    base->FIFOTRIG = trig;
+}
+
+void I2S_RxInit(I2S_Type *base, const i2s_config_t *config)
+{
+    uint32_t cfg = 0U;
+    uint32_t trig = 0U;
+
+    FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX);
+    I2S_Config(base, config);
+
+    /* Configure FIFO */
+
+    cfg |= I2S_FIFOCFG_ENABLERX(1U);               /* enable RX FIFO */
+    cfg |= I2S_FIFOCFG_EMPTYRX(1U);                /* empty RX FIFO */
+    cfg |= I2S_FIFOCFG_PACK48(config->pack48);     /* set pack 48-bit format or not */
+    trig |= I2S_FIFOTRIG_RXLVLENA(1U);             /* enable RX FIFO trigger */
+    trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */
+
+    base->FIFOCFG = cfg;
+    base->FIFOTRIG = trig;
+}
+
+void I2S_TxGetDefaultConfig(i2s_config_t *config)
+{
+    config->masterSlave = kI2S_MasterSlaveNormalMaster;
+    config->mode = kI2S_ModeI2sClassic;
+    config->rightLow = false;
+    config->leftJust = false;
+    config->pdmData = false;
+    config->sckPol = false;
+    config->wsPol = false;
+    config->divider = 1U;
+    config->oneChannel = false;
+    config->dataLength = 16U;
+    config->frameLength = 32U;
+    config->position = 0U;
+    config->watermark = 4U;
+    config->txEmptyZero = true;
+    config->pack48 = false;
+}
+
+void I2S_RxGetDefaultConfig(i2s_config_t *config)
+{
+    config->masterSlave = kI2S_MasterSlaveNormalSlave;
+    config->mode = kI2S_ModeI2sClassic;
+    config->rightLow = false;
+    config->leftJust = false;
+    config->pdmData = false;
+    config->sckPol = false;
+    config->wsPol = false;
+    config->divider = 1U;
+    config->oneChannel = false;
+    config->dataLength = 16U;
+    config->frameLength = 32U;
+    config->position = 0U;
+    config->watermark = 4U;
+    config->txEmptyZero = false;
+    config->pack48 = false;
+}
+
+static void I2S_Config(I2S_Type *base, const i2s_config_t *config)
+{
+    assert(config);
+
+    uint32_t cfg1 = 0U;
+    uint32_t cfg2 = 0U;
+
+    /* set master/slave configuration */
+    cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave);
+
+    /* set I2S mode */
+    cfg1 |= I2S_CFG1_MODE(config->mode);
+
+    /* set right low (channel swap) */
+    cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow);
+
+    /* set data justification */
+    cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust);
+
+    /* set source to PDM dmic */
+    cfg1 |= I2S_CFG1_PDMDATA(config->pdmData);
+
+    /* set SCLK polarity */
+    cfg1 |= I2S_CFG1_SCK_POL(config->sckPol);
+
+    /* set WS polarity */
+    cfg1 |= I2S_CFG1_WS_POL(config->wsPol);
+
+    /* set mono mode */
+    cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel);
+
+    /* set data length */
+    cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U);
+
+    /* set frame length */
+    cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U);
+
+    /* set data position of this channel pair within the frame */
+    cfg2 |= I2S_CFG2_POSITION(config->position);
+
+    /* write to registers */
+    base->CFG1 = cfg1;
+    base->CFG2 = cfg2;
+
+    /* set the clock divider */
+    base->DIV = I2S_DIV_DIV(config->divider - 1U);
+}
+
+void I2S_Deinit(I2S_Type *base)
+{
+    /* TODO gate FLEXCOMM clock via FLEXCOMM driver */
+}
+
+void I2S_TxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+        I2S_Enable(base);
+    }
+    else
+    {
+        I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+        I2S_Disable(base);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+    }
+}
+
+void I2S_RxEnable(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+        I2S_Enable(base);
+    }
+    else
+    {
+        I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+        I2S_Disable(base);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+    }
+}
+
+static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer)
+{
+    assert(transfer->data);
+    if (!transfer->data)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(transfer->dataSize > 0U);
+    if (transfer->dataSize <= 0U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->dataLength == 4U)
+    {
+        /* No alignment and data length requirements */
+    }
+    else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U))
+    {
+        assert((((uint32_t)transfer->data) % 2U) == 0U);
+        if ((((uint32_t)transfer->data) % 2U) != 0U)
+        {
+            /* Data not 2-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        assert((transfer->dataSize % 2U) == 0U);
+        if ((transfer->dataSize % 2U) != 0U)
+        {
+            /* Data not in pairs of left/right channel bytes */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U))
+    {
+        assert((((uint32_t)transfer->data) % 4U) == 0U);
+        if ((((uint32_t)transfer->data) % 4U) != 0U)
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        assert((transfer->dataSize % 4U) == 0U);
+        if ((transfer->dataSize % 4U) != 0U)
+        {
+            /* Data lenght not multiply of 4 */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U))
+    {
+        assert((transfer->dataSize % 6U) == 0U);
+        if ((transfer->dataSize % 6U) != 0U)
+        {
+            /* Data lenght not multiply of 6 */
+            return kStatus_InvalidArgument;
+        }
+
+        assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)));
+        if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+    }
+    else /* if (handle->dataLength >= 25U) */
+    {
+        assert((((uint32_t)transfer->data) % 4U) == 0U);
+        if ((((uint32_t)transfer->data) % 4U) != 0U)
+        {
+            /* Data not 4-bytes aligned */
+            return kStatus_InvalidArgument;
+        }
+
+        if (handle->oneChannel)
+        {
+            assert((transfer->dataSize % 4U) == 0U);
+            if ((transfer->dataSize % 4U) != 0U)
+            {
+                /* Data lenght not multiply of 4 */
+                return kStatus_InvalidArgument;
+            }
+        }
+        else
+        {
+            assert((transfer->dataSize % 8U) == 0U);
+            if ((transfer->dataSize % 8U) != 0U)
+            {
+                /* Data lenght not multiply of 8 */
+                return kStatus_InvalidArgument;
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    /* Clear out the handle */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Save callback and user data */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Remember some items set previously by configuration */
+    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT);
+    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
+    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
+    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
+
+    handle->useFifo48H = false;
+
+    /* Register IRQ handling */
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_TxHandleIRQ, handle);
+}
+
+status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    status_t result;
+
+    result = I2S_ValidateBuffer(handle, &transfer);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet */
+        return kStatus_I2S_Busy;
+    }
+
+    handle->state = kI2S_StateTx;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark);
+    I2S_TxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable I2S operation and interrupts */
+    I2S_TxEnable(base, false);
+
+    /* Reset state */
+    handle->state = kI2S_StateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+}
+
+void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    /* Clear out the handle */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Save callback and user data */
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    /* Remember some items set previously by configuration */
+    handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT);
+    handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT);
+    handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U;
+    handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT);
+
+    handle->useFifo48H = false;
+
+    /* Register IRQ handling */
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)I2S_RxHandleIRQ, handle);
+}
+
+status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    status_t result;
+
+    result = I2S_ValidateBuffer(handle, &transfer);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet */
+        return kStatus_I2S_Busy;
+    }
+
+    handle->state = kI2S_StateRx;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark);
+    I2S_RxEnable(base, true);
+
+    return kStatus_Success;
+}
+
+void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle)
+{
+    assert(handle);
+
+    /* Disable I2S operation and interrupts */
+    I2S_RxEnable(base, false);
+
+    /* Reset state */
+    handle->state = kI2S_StateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS);
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+}
+
+status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(count);
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->state == kI2S_StateIdle)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->transferCount;
+
+    return kStatus_Success;
+}
+
+status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count)
+{
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert(count);
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->state == kI2S_StateIdle)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->errorCount;
+
+    return kStatus_Success;
+}
+
+void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
+{
+    uint32_t intstat = base->FIFOINTSTAT;
+    uint32_t data;
+
+    if (intstat & I2S_FIFOINTSTAT_TXERR_MASK)
+    {
+        handle->errorCount++;
+
+        /* Clear TX error interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U);
+    }
+
+    if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK)
+    {
+        if (handle->state == kI2S_StateTx)
+        {
+            /* Send data */
+
+            while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) &&
+                   (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
+            {
+                /* Write output data */
+                if (handle->dataLength == 4U)
+                {
+                    data = *(handle->i2sQueue[handle->queueDriver].data);
+                    base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU);
+                    handle->i2sQueue[handle->queueDriver].data++;
+                    handle->transferCount++;
+                    handle->i2sQueue[handle->queueDriver].dataSize--;
+                }
+                else if (handle->dataLength <= 8U)
+                {
+                    data = *((uint16_t *)handle->i2sQueue[handle->queueDriver].data);
+                    base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU);
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                    handle->transferCount += sizeof(uint16_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                }
+                else if (handle->dataLength <= 16U)
+                {
+                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                    handle->transferCount += sizeof(uint32_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                }
+                else if (handle->dataLength <= 24U)
+                {
+                    if (handle->pack48)
+                    {
+                        if (handle->useFifo48H)
+                        {
+                            base->FIFOWR48H = *((uint16_t *)(handle->i2sQueue[handle->queueDriver].data));
+                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                            handle->transferCount += sizeof(uint16_t);
+                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                            handle->useFifo48H = false;
+                        }
+                        else
+                        {
+                            base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                            handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                            handle->transferCount += sizeof(uint32_t);
+                            handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                            handle->useFifo48H = true;
+                        }
+                    }
+                    else
+                    {
+                        data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++));
+                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U;
+                        data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U;
+                        if (handle->useFifo48H)
+                        {
+                            base->FIFOWR48H = data;
+                            handle->useFifo48H = false;
+                        }
+                        else
+                        {
+                            base->FIFOWR = data;
+                            handle->useFifo48H = true;
+                        }
+                        handle->transferCount += 3U;
+                        handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
+                    }
+                }
+                else /* if (handle->dataLength <= 32U) */
+                {
+                    base->FIFOWR = *((uint32_t *)(handle->i2sQueue[handle->queueDriver].data));
+                    handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                    handle->transferCount += sizeof(uint32_t);
+                    handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                }
+
+                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                {
+                    /* Actual data buffer sent out, switch to a next one */
+                    handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+                    /* Notify user */
+                    if (handle->completionCallback)
+                    {
+                        handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
+                    }
+
+                    /* Check if the next buffer contains anything to send */
+                    if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                    {
+                        /* Everything has been written to FIFO */
+                        handle->state = kI2S_StateTxWaitToWriteDummyData;
+                        break;
+                    }
+                }
+            }
+        }
+        else if (handle->state == kI2S_StateTxWaitToWriteDummyData)
+        {
+            /* Write dummy data */
+            if ((handle->dataLength > 16U) && (handle->dataLength < 25U))
+            {
+                if (handle->useFifo48H)
+                {
+                    base->FIFOWR48H = 0U;
+                    handle->useFifo48H = false;
+                }
+                else
+                {
+                    base->FIFOWR = 0U;
+                    base->FIFOWR48H = 0U;
+                }
+            }
+            else
+            {
+                base->FIFOWR = 0U;
+            }
+
+            /* Next time invoke this handler when FIFO becomes empty (TX level 0) */
+            base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK;
+            handle->state = kI2S_StateTxWaitForEmptyFifo;
+        }
+        else if (handle->state == kI2S_StateTxWaitForEmptyFifo)
+        {
+            /* FIFO, including additional dummy data, has been emptied now,
+             * all relevant data should have been output from peripheral */
+
+            /* Stop transfer */
+            I2S_Disable(base);
+            I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag);
+            base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+
+            /* Reset state */
+            handle->state = kI2S_StateIdle;
+
+            /* Notify user */
+            if (handle->completionCallback)
+            {
+                handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+
+        /* Clear TX level interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U);
+    }
+}
+
+void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle)
+{
+    uint32_t intstat = base->FIFOINTSTAT;
+    uint32_t data;
+
+    if (intstat & I2S_FIFOINTSTAT_RXERR_MASK)
+    {
+        handle->errorCount++;
+
+        /* Clear RX error interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U);
+    }
+
+    if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK)
+    {
+        while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U))
+        {
+            /* Read input data */
+            if (handle->dataLength == 4U)
+            {
+                data = base->FIFORD;
+                *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU);
+                handle->i2sQueue[handle->queueDriver].data++;
+                handle->transferCount++;
+                handle->i2sQueue[handle->queueDriver].dataSize--;
+            }
+            else if (handle->dataLength <= 8U)
+            {
+                data = base->FIFORD;
+                *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = ((data >> 8U) & 0xFF00U) | (data & 0xFFU);
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                handle->transferCount += sizeof(uint16_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+            }
+            else if (handle->dataLength <= 16U)
+            {
+                data = base->FIFORD;
+                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                handle->transferCount += sizeof(uint32_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+            }
+            else if (handle->dataLength <= 24U)
+            {
+                if (handle->pack48)
+                {
+                    if (handle->useFifo48H)
+                    {
+                        data = base->FIFORD48H;
+                        handle->useFifo48H = false;
+
+                        *((uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t);
+                        handle->transferCount += sizeof(uint16_t);
+                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t);
+                    }
+                    else
+                    {
+                        data = base->FIFORD;
+                        handle->useFifo48H = true;
+
+                        *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                        handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                        handle->transferCount += sizeof(uint32_t);
+                        handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+                    }
+                }
+                else
+                {
+                    if (handle->useFifo48H)
+                    {
+                        data = base->FIFORD48H;
+                        handle->useFifo48H = false;
+                    }
+                    else
+                    {
+                        data = base->FIFORD;
+                        handle->useFifo48H = true;
+                    }
+
+                    *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU;
+                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU;
+                    *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU;
+                    handle->transferCount += 3U;
+                    handle->i2sQueue[handle->queueDriver].dataSize -= 3U;
+                }
+            }
+            else /* if (handle->dataLength <= 32U) */
+            {
+                data = base->FIFORD;
+                *((uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data;
+                handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t);
+                handle->transferCount += sizeof(uint32_t);
+                handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t);
+            }
+
+            if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+            {
+                /* Actual data buffer filled with input data, switch to a next one */
+                handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+                /* Notify user */
+                if (handle->completionCallback)
+                {
+                    handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData);
+                }
+
+                if (handle->i2sQueue[handle->queueDriver].dataSize == 0U)
+                {
+                    /* No other buffer prepared to receive data into */
+
+                    /* Disable I2S operation and interrupts */
+                    I2S_Disable(base);
+                    I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag);
+                    base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+
+                    /* Reset state */
+                    handle->state = kI2S_StateIdle;
+
+                    /* Notify user */
+                    if (handle->completionCallback)
+                    {
+                        handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData);
+                    }
+
+                    /* Clear RX level interrupt flag */
+                    base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
+
+                    return;
+                }
+            }
+        }
+
+        /* Clear RX level interrupt flag */
+        base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2S_H_
+#define _FSL_I2S_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup i2s_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2S driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#ifndef I2S_NUM_BUFFERS
+
+/*! @brief Number of buffers . */
+#define I2S_NUM_BUFFERS (4)
+
+#endif
+
+/*! @brief I2S status codes. */
+enum _i2s_status
+{
+    kStatus_I2S_BufferComplete =
+        MAKE_STATUS(kStatusGroup_I2S, 0),                /*!< Transfer from/into a single buffer has completed */
+    kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */
+    kStatus_I2S_Busy =
+        MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */
+};
+
+/*!
+ * @brief I2S flags.
+ *
+ * @note These enums are meant to be OR'd together to form a bit mask.
+ */
+typedef enum _i2s_flags
+{
+    kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */
+    kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */
+    kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */
+    kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK  /*!< RX level interrupt */
+} i2s_flags_t;
+
+/*! @brief Master / slave mode. */
+typedef enum _i2s_master_slave
+{
+    kI2S_MasterSlaveNormalSlave = 0x0,  /*!< Normal slave */
+    kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */
+    kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */
+    kI2S_MasterSlaveNormalMaster = 0x3  /*!< Normal master */
+} i2s_master_slave_t;
+
+/*! @brief I2S mode. */
+typedef enum _i2s_mode
+{
+    kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */
+    kI2S_ModeDspWs50 = 0x1,    /*!< DSP mode, WS having 50% duty cycle */
+    kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */
+    kI2S_ModeDspWsLong = 0x3   /*!< DSP mode, WS having one data slot long pulse */
+} i2s_mode_t;
+
+/*! @brief I2S configuration structure. */
+typedef struct _i2s_config
+{
+    i2s_master_slave_t masterSlave; /*!< Master / slave configuration */
+    i2s_mode_t mode;                /*!< I2S mode */
+    bool rightLow;                  /*!< Right channel data in low portion of FIFO */
+    bool leftJust;                  /*!< Left justify data in FIFO */
+    bool pdmData;                   /*!< Data source is the D-Mic subsystem */
+    bool sckPol;                    /*!< SCK polarity */
+    bool wsPol;                     /*!< WS polarity */
+    uint16_t divider;               /*!< Flexcomm function clock divider (1 - 4096) */
+    bool oneChannel;                /*!< true mono, false stereo */
+    uint8_t dataLength;             /*!< Data length (4 - 32) */
+    uint16_t frameLength;           /*!< Frame width (4 - 512) */
+    uint16_t position;              /*!< Data position in the frame */
+    uint8_t watermark;              /*!< FIFO trigger level */
+    bool txEmptyZero;               /*!< Transmit zero when buffer becomes empty or last item */
+    bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                    values) */
+} i2s_config_t;
+
+/*! @brief Buffer to transfer from or receive audio data into. */
+typedef struct _i2s_transfer
+{
+    volatile uint8_t *data;   /*!< Pointer to data buffer. */
+    volatile size_t dataSize; /*!< Buffer size in bytes. */
+} i2s_transfer_t;
+
+/*! @brief Transactional state of the intialized transfer or receive I2S operation. */
+typedef struct _i2s_handle i2s_handle_t;
+
+/*!
+ * @brief Callback function invoked from transactional API
+ *        on completion of a single buffer transfer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to I2S transaction.
+ * @param completionStatus status of the transaction.
+ * @param userData optional pointer to user arguments data.
+ */
+typedef void (*i2s_transfer_callback_t)(I2S_Type *base,
+                                        i2s_handle_t *handle,
+                                        status_t completionStatus,
+                                        void *userData);
+
+/*! @brief Members not to be accessed / modified outside of the driver. */
+struct _i2s_handle
+{
+    uint32_t state;                             /*!< State of transfer */
+    i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */
+    void *userData;                             /*!< Application data passed to callback */
+    bool oneChannel;                            /*!< true mono, false stereo */
+    uint8_t dataLength;                         /*!< Data length (4 - 32) */
+    bool pack48;     /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                        values) */
+    bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
+    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
+    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
+    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+    volatile uint32_t errorCount;                      /*!< Number of buffer underruns/overruns */
+    volatile uint32_t transferCount;                   /*!< Number of bytes transferred */
+    volatile uint8_t watermark;                        /*!< FIFO trigger level */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality.
+ *
+ * Ungates the FLEXCOMM clock and configures the module
+ * for I2S transmission using a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * I2S_TxGetDefaultConfig().
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2S driver.
+ *
+ * @param base I2S base pointer.
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_TxInit(I2S_Type *base, const i2s_config_t *config);
+
+/*!
+ * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality.
+ *
+ * Ungates the FLEXCOMM clock and configures the module
+ * for I2S receive using a configuration structure.
+ * The configuration structure can be custom filled or set with default values by
+ * I2S_RxGetDefaultConfig().
+ *
+ * @note This API should be called at the beginning of the application to use
+ * the I2S driver.
+ *
+ * @param base I2S base pointer.
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_RxInit(I2S_Type *base, const i2s_config_t *config);
+
+/*!
+ * @brief Sets the I2S Tx configuration structure to default values.
+ *
+ * This API initializes the configuration structure for use in I2S_TxInit().
+ * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified
+ * before calling I2S_TxInit().
+ * Example:
+   @code
+   i2s_config_t config;
+   I2S_TxGetDefaultConfig(&config);
+   @endcode
+ *
+ * Default values:
+ * @code
+ *   config->masterSlave = kI2S_MasterSlaveNormalMaster;
+ *   config->mode = kI2S_ModeI2sClassic;
+ *   config->rightLow = false;
+ *   config->leftJust = false;
+ *   config->pdmData = false;
+ *   config->sckPol = false;
+ *   config->wsPol = false;
+ *   config->divider = 1;
+ *   config->oneChannel = false;
+ *   config->dataLength = 16;
+ *   config->frameLength = 32;
+ *   config->position = 0;
+ *   config->watermark = 4;
+ *   config->txEmptyZero = true;
+ *   config->pack48 = false;
+ * @endcode
+ *
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_TxGetDefaultConfig(i2s_config_t *config);
+
+/*!
+ * @brief Sets the I2S Rx configuration structure to default values.
+ *
+ * This API initializes the configuration structure for use in I2S_RxInit().
+ * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified
+ * before calling I2S_RxInit().
+ * Example:
+   @code
+   i2s_config_t config;
+   I2S_RxGetDefaultConfig(&config);
+   @endcode
+ *
+ * Default values:
+ * @code
+ *   config->masterSlave = kI2S_MasterSlaveNormalSlave;
+ *   config->mode = kI2S_ModeI2sClassic;
+ *   config->rightLow = false;
+ *   config->leftJust = false;
+ *   config->pdmData = false;
+ *   config->sckPol = false;
+ *   config->wsPol = false;
+ *   config->divider = 1;
+ *   config->oneChannel = false;
+ *   config->dataLength = 16;
+ *   config->frameLength = 32;
+ *   config->position = 0;
+ *   config->watermark = 4;
+ *   config->txEmptyZero = false;
+ *   config->pack48 = false;
+ * @endcode
+ *
+ * @param config pointer to I2S configuration structure.
+ */
+void I2S_RxGetDefaultConfig(i2s_config_t *config);
+
+/*!
+ * @brief De-initializes the I2S peripheral.
+ *
+ * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit
+ * or I2S_RxInit is called to enable the clock.
+ *
+ * @param base I2S base pointer.
+ */
+void I2S_Deinit(I2S_Type *base);
+
+/*! @} */
+
+/*!
+ * @name Non-blocking API
+ * @{
+ */
+
+/*!
+ * @brief Initializes handle for transfer of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Begins or queue sending of the given data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
+ */
+status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts sending of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Initializes handle for reception of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Begins or queue reception of data into given buffer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full.
+ */
+status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts receiving of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Returns number of bytes transferred so far.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param[out] count number of bytes transferred so far by the non-blocking transaction.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
+ */
+status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Returns number of buffer underruns or overruns.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param[out] count number of transmit errors encountered so far by the non-blocking transaction.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress.
+ */
+status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count);
+
+/*! @} */
+
+/*!
+ * @name Enable / disable
+ * @{
+ */
+
+/*!
+ * @brief Enables I2S operation.
+ *
+ * @param base I2S base pointer.
+ */
+static inline void I2S_Enable(I2S_Type *base)
+{
+    base->CFG1 |= I2S_CFG1_MAINENABLE(1U);
+}
+
+/*!
+ * @brief Disables I2S operation.
+ *
+ * @param base I2S base pointer.
+ */
+static inline void I2S_Disable(I2S_Type *base)
+{
+    base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U));
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask)
+{
+    base->FIFOINTENSET = interruptMask;
+}
+
+/*!
+ * @brief Disables I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set
+ *      of constants that should be OR'd together to form the bit mask.
+ */
+static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask)
+{
+    base->FIFOINTENCLR = interruptMask;
+}
+
+/*!
+ * @brief Returns the set of currently enabled I2S FIFO interrupts.
+ *
+ * @param base I2S base pointer.
+ *
+ * @return A bitmask composed of #i2s_flags_t enumerators OR'd together
+ *         to indicate the set of enabled interrupts.
+ */
+static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base)
+{
+    return base->FIFOINTENSET;
+}
+
+/*!
+ * @brief Invoked from interrupt handler when transmit FIFO level decreases.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
+
+/*!
+ * @brief Invoked from interrupt handler when receive FIFO level decreases.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle);
+
+/*! @} */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2S_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,626 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_dma.h"
+#include "fsl_i2s_dma.h"
+#include "fsl_flexcomm.h"
+#include <string.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t))
+#define DMA_DESCRIPTORS (2U)
+
+/*<! @brief Structure for statically allocated private data. */
+typedef struct _i2s_dma_private_handle
+{
+    I2S_Type *base;           /*!< I2S base address */
+    i2s_dma_handle_t *handle; /*!< I2S handle */
+
+    volatile uint16_t enqueuedBytes[DMA_DESCRIPTORS]; /*!< Number of bytes being transferred by DMA descriptors */
+    volatile uint8_t enqueuedBytesStart;              /*!< First item in enqueuedBytes (for reading) */
+    volatile uint8_t enqueuedBytesEnd;                /*!< Last item in enqueuedBytes (for adding) */
+
+    volatile uint8_t
+        dmaDescriptorsUsed; /*!< Number of DMA descriptors with valid data (in queue, excluding initial descriptor) */
+    volatile uint8_t
+        descriptor; /*!< Index of next DMA descriptor in s_DmaDescriptors to be configured with data (does not include
+                       I2S instance offset) */
+
+    volatile uint8_t queueDescriptor;                         /*!< Queue index of buffer to be actually consumed by DMA
+                                                                * (queueUser - advanced when user adds a buffer,
+                                                                *  queueDescriptor - advanced when user buffer queued to DMA,
+                                                                *  queueDriver - advanced when DMA queued buffer sent out to I2S) */
+    volatile i2s_transfer_t descriptorQueue[I2S_NUM_BUFFERS]; /*!< Transfer data to be queued to DMA */
+
+    volatile bool intA; /*!< If next scheduled DMA transfer will cause interrupt A or B */
+} i2s_dma_private_handle_t;
+
+/*! @brief I2S DMA transfer private state. */
+enum _i2s_dma_state
+{
+    kI2S_DmaStateIdle = 0x0U, /*!< I2S is in idle state */
+    kI2S_DmaStateTx,          /*!< I2S is busy transmitting data */
+    kI2S_DmaStateRx,          /*!< I2S is busy receiving data */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+static uint32_t I2S_GetInstance(I2S_Type *base);
+static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle);
+static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle);
+static void I2S_TxEnableDMA(I2S_Type *base, bool enable);
+static void I2S_RxEnableDMA(I2S_Type *base, bool enable);
+static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer);
+static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*<! @brief DMA transfer descriptors. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 16
+static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#elif defined(__CC_ARM)
+__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#elif defined(__GNUC__)
+__attribute__((aligned(16))) static dma_descriptor_t s_DmaDescriptors[DMA_DESCRIPTORS * FSL_FEATURE_SOC_I2S_COUNT];
+#endif
+
+/*<! @brief Buffer with dummy TX data. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint32_t s_DummyBufferTx = 0U;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferTx = 0U;
+#endif
+
+/*<! @brief Buffer to fill with RX data to discard. */
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint32_t s_DummyBufferRx = 0U;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint32_t s_DummyBufferRx = 0U;
+#endif
+
+/*<! @brief Private array of data associated with available I2S peripherals. */
+static i2s_dma_private_handle_t s_DmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT];
+
+/*<! @brief Base addresses of available I2S peripherals. */
+static const uint32_t s_I2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static status_t I2S_EnqueueUserBuffer(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    /* Validate input data and tranfer buffer */
+
+    assert(handle);
+    if (!handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    assert((((uint32_t)transfer.data) % 4U) == 0U);
+    if ((((uint32_t)transfer.data) % 4U) != 0U)
+    {
+        /* Data not 4-bytes aligned */
+        return kStatus_InvalidArgument;
+    }
+
+    assert(transfer.dataSize != 0U);
+    if (transfer.dataSize == 0U)
+    {
+        /* No data to send or receive */
+        return kStatus_InvalidArgument;
+    }
+
+    assert((transfer.dataSize % 4U) == 0U);
+    if ((transfer.dataSize % 4U) != 0U)
+    {
+        /* Data length not multiply of 4 bytes */
+        return kStatus_InvalidArgument;
+    }
+
+    if (handle->i2sQueue[handle->queueUser].dataSize)
+    {
+        /* Previously prepared buffers not processed yet, reject request */
+        return kStatus_I2S_Busy;
+    }
+
+    /* Enqueue data */
+    privateHandle->descriptorQueue[handle->queueUser].data = transfer.data;
+    privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->i2sQueue[handle->queueUser].data = transfer.data;
+    handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize;
+    handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS;
+
+    return kStatus_Success;
+}
+
+static uint32_t I2S_GetInstance(I2S_Type *base)
+{
+    uint32_t i;
+
+    for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++)
+    {
+        if ((uint32_t)base == s_I2sBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0U;
+}
+
+static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle)
+{
+    DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
+}
+
+static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle)
+{
+    if (handle->state != kI2S_DmaStateIdle)
+    {
+        DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+}
+
+void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData)
+{
+    assert(handle);
+    assert(dmaHandle);
+
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    memset(handle, 0U, sizeof(*handle));
+    handle->state = kI2S_DmaStateIdle;
+    handle->dmaHandle = dmaHandle;
+    handle->completionCallback = callback;
+    handle->userData = userData;
+
+    memset(privateHandle, 0U, sizeof(*privateHandle));
+    privateHandle->base = base;
+    privateHandle->handle = handle;
+
+    DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle);
+}
+
+status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    status_t status;
+
+    I2S_DisableDMAInterrupts(handle);
+
+    /* Enqueue transfer buffer */
+    status = I2S_EnqueueUserBuffer(base, handle, transfer);
+    if (status != kStatus_Success)
+    {
+        I2S_EnableDMAInterrupts(handle);
+        return status;
+    }
+
+    /* Initialize DMA transfer */
+    if (handle->state == kI2S_DmaStateIdle)
+    {
+        handle->state = kI2S_DmaStateTx;
+        status = I2S_StartTransferDMA(base, handle);
+        if (status != kStatus_Success)
+        {
+            I2S_EnableDMAInterrupts(handle);
+            return status;
+        }
+    }
+
+    I2S_AddTransferDMA(base, handle);
+    I2S_EnableDMAInterrupts(handle);
+
+    return kStatus_Success;
+}
+
+void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    assert(handle);
+    assert(handle->dmaHandle);
+
+    uint32_t instance = I2S_GetInstance(base);
+    i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    I2S_DisableDMAInterrupts(handle);
+
+    /* Abort operation */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    if (handle->state == kI2S_DmaStateTx)
+    {
+        /* Wait until all transmitted data get out of FIFO */
+        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
+        {
+        }
+        /* The last piece of valid data can be still being transmitted from I2S at this moment */
+
+        /* Write additional data to FIFO */
+        base->FIFOWR = 0U;
+        while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U)
+        {
+        }
+        /* At this moment the additional data are out of FIFO, starting being transmitted.
+         * This means the preceding valid data has been just transmitted and we can stop I2S. */
+        I2S_TxEnableDMA(base, false);
+    }
+    else
+    {
+        I2S_RxEnableDMA(base, false);
+    }
+
+    I2S_Disable(base);
+
+    /* Reset state */
+    handle->state = kI2S_DmaStateIdle;
+
+    /* Clear transfer queue */
+    memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue));
+    handle->queueDriver = 0U;
+    handle->queueUser = 0U;
+
+    /* Clear internal state */
+    memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue));
+    memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes));
+    privateHandle->enqueuedBytesStart = 0U;
+    privateHandle->enqueuedBytesEnd = 0U;
+    privateHandle->dmaDescriptorsUsed = 0U;
+    privateHandle->descriptor = 0U;
+    privateHandle->queueDescriptor = 0U;
+    privateHandle->intA = false;
+}
+
+void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData)
+{
+    I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData);
+}
+
+status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer)
+{
+    status_t status;
+
+    I2S_DisableDMAInterrupts(handle);
+
+    /* Enqueue transfer buffer */
+    status = I2S_EnqueueUserBuffer(base, handle, transfer);
+    if (status != kStatus_Success)
+    {
+        I2S_EnableDMAInterrupts(handle);
+        return status;
+    }
+
+    /* Initialize DMA transfer */
+    if (handle->state == kI2S_DmaStateIdle)
+    {
+        handle->state = kI2S_DmaStateRx;
+        status = I2S_StartTransferDMA(base, handle);
+        if (status != kStatus_Success)
+        {
+            I2S_EnableDMAInterrupts(handle);
+            return status;
+        }
+    }
+
+    I2S_AddTransferDMA(base, handle);
+    I2S_EnableDMAInterrupts(handle);
+
+    return kStatus_Success;
+}
+
+static void I2S_TxEnableDMA(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK;
+    }
+}
+
+static void I2S_RxEnableDMA(I2S_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK);
+        base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK;
+    }
+}
+
+static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer)
+{
+    assert(transfer);
+
+    uint16_t transferBytes;
+
+    if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES))
+    {
+        transferBytes = DMA_MAX_TRANSFER_BYTES;
+    }
+    else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES)
+    {
+        transferBytes = transfer->dataSize / 2U;
+        if ((transferBytes % 4U) != 0U)
+        {
+            transferBytes -= (transferBytes % 4U);
+        }
+    }
+    else
+    {
+        transferBytes = transfer->dataSize;
+    }
+
+    return transferBytes;
+}
+
+static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    status_t status;
+    dma_transfer_config_t xferConfig = {0};
+    i2s_dma_private_handle_t *privateHandle;
+    volatile i2s_transfer_t *transfer;
+    uint16_t transferBytes;
+    uint32_t instance;
+    int i;
+    dma_descriptor_t *descriptor;
+    dma_descriptor_t *nextDescriptor;
+    dma_xfercfg_t xfercfg;
+
+    instance = I2S_GetInstance(base);
+    privateHandle = &(s_DmaPrivateHandle[instance]);
+    transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
+
+    transferBytes = I2S_GetTransferBytes(transfer);
+
+    /* Prepare transfer of data via initial DMA transfer descriptor */
+    DMA_PrepareTransfer(
+        &xferConfig, (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
+        (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data, sizeof(uint32_t),
+        transferBytes, (handle->state == kI2S_DmaStateTx) ? kDMA_MemoryToPeripheral : kDMA_PeripheralToMemory,
+        (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U]));
+
+    /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */
+    privateHandle->dmaDescriptorsUsed = 1U;
+    privateHandle->intA = false;
+
+    privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
+    privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
+
+    transfer->dataSize -= transferBytes;
+    transfer->data += transferBytes;
+
+    if (transfer->dataSize == 0U)
+    {
+        transfer->data = NULL;
+        privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
+    }
+
+    /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes */
+    for (i = 0; i < DMA_DESCRIPTORS; i++)
+    {
+        descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]);
+        nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)]);
+
+        xfercfg.valid = true;
+        xfercfg.reload = true;
+        xfercfg.swtrig = false;
+        xfercfg.clrtrig = false;
+        xfercfg.intA = false;
+        xfercfg.intB = false;
+        xfercfg.byteWidth = sizeof(uint32_t);
+        xfercfg.srcInc = 0U;
+        xfercfg.dstInc = 0U;
+        xfercfg.transferCount = 8U;
+
+        DMA_CreateDescriptor(descriptor, &xfercfg,
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&s_DummyBufferTx : (void *)&(base->FIFORD),
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)&s_DummyBufferRx,
+                             (void *)nextDescriptor);
+    }
+
+    /* Submit and start initial DMA transfer */
+
+    if (handle->state == kI2S_DmaStateTx)
+    {
+        I2S_TxEnableDMA(base, true);
+    }
+    else
+    {
+        I2S_RxEnableDMA(base, true);
+    }
+
+    status = DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    DMA_StartTransfer(handle->dmaHandle);
+
+    I2S_Enable(base);
+    return kStatus_Success;
+}
+
+static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle)
+{
+    dma_xfercfg_t xfercfg;
+    volatile i2s_transfer_t *transfer;
+    uint16_t transferBytes;
+    uint32_t instance;
+    i2s_dma_private_handle_t *privateHandle;
+    dma_descriptor_t *descriptor;
+    dma_descriptor_t *nextDescriptor;
+
+    instance = I2S_GetInstance(base);
+    privateHandle = &(s_DmaPrivateHandle[instance]);
+
+    while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS)
+    {
+        transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]);
+
+        if (transfer->dataSize == 0U)
+        {
+            /* Nothing to be added */
+            return;
+        }
+
+        /* Determine currently configured descriptor and the other which it will link to */
+        descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
+        privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS;
+        nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]);
+
+        transferBytes = I2S_GetTransferBytes(transfer);
+        privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes;
+        privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS;
+
+        /* Configure descriptor */
+
+        xfercfg.valid = true;
+        xfercfg.reload = true;
+        xfercfg.swtrig = false;
+        xfercfg.clrtrig = false;
+        xfercfg.intA = privateHandle->intA;
+        xfercfg.intB = !privateHandle->intA;
+        xfercfg.byteWidth = sizeof(uint32_t);
+        xfercfg.srcInc = (handle->state == kI2S_DmaStateTx) ? 1U : 0U;
+        xfercfg.dstInc = (handle->state == kI2S_DmaStateTx) ? 0U : 1U;
+        xfercfg.transferCount = transferBytes / sizeof(uint32_t);
+
+        DMA_CreateDescriptor(descriptor, &xfercfg,
+                             (handle->state == kI2S_DmaStateTx) ? (void *)transfer->data : (void *)&(base->FIFORD),
+                             (handle->state == kI2S_DmaStateTx) ? (void *)&(base->FIFOWR) : (void *)transfer->data,
+                             (void *)nextDescriptor);
+
+        /* Advance internal state */
+
+        privateHandle->dmaDescriptorsUsed++;
+        privateHandle->intA = !privateHandle->intA;
+
+        transfer->dataSize -= transferBytes;
+        transfer->data += transferBytes;
+        if (transfer->dataSize == 0U)
+        {
+            transfer->data = NULL;
+            privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS;
+        }
+    }
+}
+
+void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds)
+{
+    i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData;
+    i2s_dma_handle_t *i2sHandle = privateHandle->handle;
+    I2S_Type *base = privateHandle->base;
+
+    if (!transferDone || (i2sHandle->state == kI2S_DmaStateIdle))
+    {
+        return;
+    }
+
+    if (privateHandle->dmaDescriptorsUsed > 0U)
+    {
+        /* Finished descriptor, decrease amount of data to be processed */
+
+        i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -=
+            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+        i2sHandle->i2sQueue[i2sHandle->queueDriver].data +=
+            privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart];
+        privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U;
+        privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS;
+
+        privateHandle->dmaDescriptorsUsed--;
+
+        if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+        {
+            /* Entire user buffer sent or received - advance to next one */
+            i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL;
+            i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS;
+
+            /* Notify user about buffer completion */
+            if (i2sHandle->completionCallback)
+            {
+                (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData);
+            }
+        }
+    }
+
+    if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U)
+    {
+        /* All user buffers processed */
+        I2S_TransferAbortDMA(base, i2sHandle);
+
+        /* Notify user about completion of the final buffer */
+        if (i2sHandle->completionCallback)
+        {
+            (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_Done, i2sHandle->userData);
+        }
+    }
+    else
+    {
+        /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */
+        I2S_AddTransferDMA(base, i2sHandle);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_I2S_DMA_H_
+#define _FSL_I2S_DMA_H_
+
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+#include "fsl_dma.h"
+#include "fsl_i2s.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup i2s_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2S DMA driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Members not to be accessed / modified outside of the driver. */
+typedef struct _i2s_dma_handle i2s_dma_handle_t;
+
+/*!
+ * @brief Callback function invoked from DMA API on completion.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to I2S transaction.
+ * @param completionStatus status of the transaction.
+ * @param userData optional pointer to user arguments data.
+ */
+typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base,
+                                            i2s_dma_handle_t *handle,
+                                            status_t completionStatus,
+                                            void *userData);
+
+struct _i2s_dma_handle
+{
+    uint32_t state;                                    /*!< Internal state of I2S DMA transfer */
+    i2s_dma_transfer_callback_t completionCallback;    /*!< Callback function pointer */
+    void *userData;                                    /*!< Application data passed to callback */
+    dma_handle_t *dmaHandle;                           /*!< DMA handle */
+    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
+    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
+    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*! @} */
+
+/*!
+ * @name DMA API
+ * @{
+ */
+
+/*!
+ * @brief Initializes handle for transfer of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param dmaHandle pointer to dma handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_TxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Begins or queue sending of the given data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers.
+ */
+status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Aborts transfer of data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ */
+void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle);
+
+/*!
+ * @brief Initializes handle for reception of audio data.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param dmaHandle pointer to dma handle structure.
+ * @param callback function to be called back when transfer is done or fails.
+ * @param userData pointer to data passed to callback.
+ */
+void I2S_RxTransferCreateHandleDMA(I2S_Type *base,
+                                   i2s_dma_handle_t *handle,
+                                   dma_handle_t *dmaHandle,
+                                   i2s_dma_transfer_callback_t callback,
+                                   void *userData);
+
+/*!
+ * @brief Begins or queue reception of data into given buffer.
+ *
+ * @param base I2S base pointer.
+ * @param handle pointer to handle structure.
+ * @param transfer data buffer.
+ *
+ * @retval kStatus_Success
+ * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers
+ *         which are not full.
+ */
+status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer);
+
+/*!
+ * @brief Invoked from DMA interrupt handler.
+ *
+ * @param handle pointer to DMA handle structure.
+ * @param userData argument for user callback.
+ * @param transferDone if transfer was done.
+ * @param tcds
+ */
+void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);
+
+/*! @} */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_I2S_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_inputmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void INPUTMUX_Init(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_InputMux);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
+{
+    uint32_t pmux_id;
+    uint32_t output_id;
+
+    /* extract pmux to be used */
+    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
+    /*  extract function number */
+    output_id = ((uint32_t)(connection)) & 0xffffU;
+    /* programm signal */
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
+}
+
+void INPUTMUX_Deinit(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(kCLOCK_InputMux);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INPUTMUX_H_
+#define _FSL_INPUTMUX_H_
+
+#include "fsl_inputmux_connections.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*! @file */
+/*! @file fsl_inputmux_connections.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Group interrupt driver version for SDK */
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+                                                            /*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base);
+
+/*!
+ * @brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param index Destination peripheral to attach the signal to.
+ * @param connection Selects connection.
+ *
+ * @retval None.
+*/
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
+
+/*!
+ * @brief	Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_INPUTMUX_CONNECTIONS_
+#define _FSL_INPUTMUX_CONNECTIONS_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*!
+ * @name Input multiplexing connections
+ * @{
+ */
+
+/*! @brief Periphinmux IDs */
+#define SCT0_PMUX_ID 0x00U
+#define PINTSEL_PMUX_ID 0xC0U
+#define DMA_TRIG0_PMUX_ID 0xE0U
+#define DMA_OTRIG_PMUX_ID 0x160U
+#define FREQMEAS_PMUX_ID 0x180U
+#define PMUX_SHIFT 20U
+
+/*! @brief INPUTMUX connections type */
+typedef enum _inputmux_connection_t
+{
+    /*!< SCT INMUX. */
+    kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T0Out0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T1Out0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T2Out0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T3Out0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_T4Out0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_AdcThcmpIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_ArmTxevToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DebugHaltedToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard0TxActivreToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard0RxActivreToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard1TxActivreToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_SmartCard1RxActivreToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_I2s6SclkToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_I2sS7clkToSct0 = 24U + (SCT0_PMUX_ID << PMUX_SHIFT),
+
+    /*!< Frequency measure. */
+    kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Fro96MhzToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_a = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_FreqmeGpioClk_b = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+
+    /*!< Pin Interrupt. */
+    kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA ITRIG. */
+    kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+    /*!< DMA OTRIG. */
+    kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaChannel9_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm8RxTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm8TxTrigoutToTriginChannels = 21U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm9RxTrigoutToTriginChannels = 22U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaFlexcomm9TxTrigoutToTriginChannels = 23U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard0RxTrigoutToTriginChannels = 24U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard0TxTrigoutToTriginChannels = 25U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard1RxTrigoutToTriginChannels = 26U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+    kINPUTMUX_DmaSmartcard1TxTrigoutToTriginChannels = 27U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
+} inputmux_connection_t;
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_CONNECTIONS_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_iocon.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_IOCON_H_
+#define _FSL_IOCON_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_iocon
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOCON driver version 2.0.0. */
+#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/**
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
+ */
+typedef struct _iocon_group
+{
+    uint32_t port : 8;      /* Pin port */
+    uint32_t pin : 8;       /* Pin number */
+    uint32_t modefunc : 16; /* Function and mode */
+} iocon_group_t;
+
+/**
+ * @brief IOCON function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+    #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH== 4)
+    #define IOCON_FUNC0             0x0             /*!< Selects pin function 0 */
+    #define IOCON_FUNC1             0x1             /*!< Selects pin function 1 */
+    #define IOCON_FUNC2             0x2             /*!< Selects pin function 2 */
+    #define IOCON_FUNC3             0x3             /*!< Selects pin function 3 */
+    #define IOCON_FUNC4             0x4             /*!< Selects pin function 4 */
+    #define IOCON_FUNC5             0x5             /*!< Selects pin function 5 */
+    #define IOCON_FUNC6             0x6             /*!< Selects pin function 6 */
+    #define IOCON_FUNC7             0x7             /*!< Selects pin function 7 */
+    #define IOCON_FUNC8             0x8             /*!< Selects pin function 8 */
+    #define IOCON_FUNC9             0x9             /*!< Selects pin function 9 */
+    #define IOCON_FUNC10            0xA             /*!< Selects pin function 10 */
+    #define IOCON_FUNC11            0xB             /*!< Selects pin function 11 */
+    #define IOCON_FUNC12            0xC             /*!< Selects pin function 12 */
+    #define IOCON_FUNC13            0xD             /*!< Selects pin function 13 */
+    #define IOCON_FUNC14            0xE             /*!< Selects pin function 14 */
+    #define IOCON_FUNC15            0xF             /*!< Selects pin function 15 */
+    #define IOCON_MODE_INACT        (0x0 << 4)      /*!< No addition pin function */
+    #define IOCON_MODE_PULLDOWN     (0x1 << 4)      /*!< Selects pull-down function */
+    #define IOCON_MODE_PULLUP       (0x2 << 4)      /*!< Selects pull-up function */
+    #define IOCON_MODE_REPEATER     (0x3 << 4)      /*!< Selects pin repeater function */
+    #define IOCON_HYS_EN            (0x1 << 6)      /*!< Enables hysteresis */
+    #define IOCON_GPIO_MODE         (0x1 << 6)      /*!< GPIO Mode */
+    #define IOCON_I2C_SLEW          (0x1 << 6)      /*!< I2C Slew Rate Control */
+    #define IOCON_INV_EN            (0x1 << 7)      /*!< Enables invert function on input */
+    #define IOCON_ANALOG_EN         (0x0 << 8)      /*!< Enables analog function by setting 0 to bit 7 */
+    #define IOCON_DIGITAL_EN        (0x1 << 8)      /*!< Enables digital function by setting 1 to bit 7(default) */
+    #define IOCON_STDI2C_EN         (0x1 << 9)      /*!< I2C standard mode/fast-mode */
+    #define IOCON_FASTI2C_EN        (0x3 << 9)      /*!< I2C Fast-mode Plus and high-speed slave */
+    #define IOCON_INPFILT_OFF       (0x1 << 9)      /*!< Input filter Off for GPIO pins */
+    #define IOCON_INPFILT_ON        (0x0 << 9)      /*!< Input filter On for GPIO pins */
+    #define IOCON_OPENDRAIN_EN      (0x1 << 11)      /*!< Enables open-drain function */
+    #define IOCON_S_MODE_0CLK       (0x0 << 12)      /*!< Bypass input filter */
+    #define IOCON_S_MODE_1CLK       (0x1 << 12)      /*!< Input pulses shorter than 1 filter clock are rejected */
+    #define IOCON_S_MODE_2CLK       (0x2 << 12)      /*!< Input pulses shorter than 2 filter clock2 are rejected */
+    #define IOCON_S_MODE_3CLK       (0x3 << 12)      /*!< Input pulses shorter than 3 filter clock2 are rejected */
+    #define IOCON_S_MODE(clks)      ((clks) << 12)   /*!< Select clocks for digital input filter mode */
+    #define IOCON_CLKDIV(div)       ((div) << 14)    /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#else
+    #define IOCON_FUNC0 0x0                   /*!< Selects pin function 0 */
+    #define IOCON_FUNC1 0x1                   /*!< Selects pin function 1 */
+    #define IOCON_FUNC2 0x2                   /*!< Selects pin function 2 */
+    #define IOCON_FUNC3 0x3                   /*!< Selects pin function 3 */
+    #define IOCON_FUNC4 0x4                   /*!< Selects pin function 4 */
+    #define IOCON_FUNC5 0x5                   /*!< Selects pin function 5 */
+    #define IOCON_FUNC6 0x6                   /*!< Selects pin function 6 */
+    #define IOCON_FUNC7 0x7                   /*!< Selects pin function 7 */
+    #define IOCON_MODE_INACT (0x0 << 3)       /*!< No addition pin function */
+    #define IOCON_MODE_PULLDOWN (0x1 << 3)    /*!< Selects pull-down function */
+    #define IOCON_MODE_PULLUP (0x2 << 3)      /*!< Selects pull-up function */
+    #define IOCON_MODE_REPEATER (0x3 << 3)    /*!< Selects pin repeater function */
+    #define IOCON_HYS_EN (0x1 << 5)           /*!< Enables hysteresis */
+    #define IOCON_GPIO_MODE (0x1 << 5)        /*!< GPIO Mode */
+    #define IOCON_I2C_SLEW (0x1 << 5)         /*!< I2C Slew Rate Control */
+    #define IOCON_INV_EN (0x1 << 6)           /*!< Enables invert function on input */
+    #define IOCON_ANALOG_EN (0x0 << 7)        /*!< Enables analog function by setting 0 to bit 7 */
+    #define IOCON_DIGITAL_EN (0x1 << 7)       /*!< Enables digital function by setting 1 to bit 7(default) */
+    #define IOCON_STDI2C_EN (0x1 << 8)        /*!< I2C standard mode/fast-mode */
+    #define IOCON_FASTI2C_EN (0x3 << 8)       /*!< I2C Fast-mode Plus and high-speed slave */
+    #define IOCON_INPFILT_OFF (0x1 << 8)      /*!< Input filter Off for GPIO pins */
+    #define IOCON_INPFILT_ON (0x0 << 8)       /*!< Input filter On for GPIO pins */
+    #define IOCON_OPENDRAIN_EN (0x1 << 10)    /*!< Enables open-drain function */
+    #define IOCON_S_MODE_0CLK (0x0 << 11)     /*!< Bypass input filter */
+    #define IOCON_S_MODE_1CLK (0x1 << 11)     /*!< Input pulses shorter than 1 filter clock are rejected */
+    #define IOCON_S_MODE_2CLK (0x2 << 11)     /*!< Input pulses shorter than 2 filter clock2 are rejected */
+    #define IOCON_S_MODE_3CLK (0x3 << 11)     /*!< Input pulses shorter than 3 filter clock2 are rejected */
+    #define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
+    #define IOCON_CLKDIV(div) \
+        ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#endif
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief   Sets I/O Control pin mux
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   port        : GPIO port to mux
+ * @param   pin         : GPIO pin to mux
+ * @param   modefunc    : OR'ed values of type IOCON_*
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+    base->PIO[port][pin] = modefunc;
+}
+
+/**
+ * @brief   Set all I/O Control pin muxing
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   pinArray    : Pointer to array of pin mux selections
+ * @param   arrayLength : Number of entries in pinArray
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
+{
+    uint32_t i;
+
+    for (i = 0; i < arrayLength; i++)
+    {
+        IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
+    }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_IOCON_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_lcdc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Max value of LCD_POL[PCD]. */
+#define LCD_PCD_MAX                                  \
+    ((LCD_POL_PCD_LO_MASK >> LCD_POL_PCD_LO_SHIFT) | \
+     (LCD_POL_PCD_HI_MASK >> (LCD_POL_PCD_HI_SHIFT - LCD_POL_PCD_LO_SHIFT)))
+
+/* Macro to contruct the LCD_POL[PCD]. */
+#if (LCD_POL_PCD_LO_MASK != 0x1F)
+#error LCD_POL_PCD_LO is not 5-bit. The macro LCD_POL_PCD_LO_WIDTH should be updated.
+#endif
+#define LCD_POL_PCD_LO_WIDTH 5U
+#define LCD_POL_PCD(pcd) (LCD_POL_PCD_LO(pcd) | LCD_POL_PCD_HI((pcd) >> LCD_POL_PCD_LO_WIDTH))
+
+/* Cursor interrupt. */
+#define LCDC_CURSOR_INT_MASK LCD_CRSR_INTMSK_CRSRIM_MASK
+
+/* Interrupts except cursor interrupt. */
+#define LCDC_NORMAL_INT_MASK \
+    (LCD_INTMSK_FUFIM_MASK | LCD_INTMSK_LNBUIM_MASK | LCD_INTMSK_VCOMPIM_MASK | LCD_INTMSK_BERIM_MASK)
+
+/* Detect the cursor interrupt and normal interrupt bits overlap. */
+#if (LCDC_CURSOR_INT_MASK & LCDC_NORMAL_INT_MASK)
+#error Cursor interrupt and normal interrupt overlap. The driver should be updated.
+#endif
+
+/* The max cursor clip value. */
+#define LCDC_CLIP_MAX (LCD_CRSR_CLIP_CRSRCLIPX_MASK >> LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static LCD_Type *const s_lcdBases[] = LCD_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static const clock_ip_name_t s_lcdClocks[] = LCD_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+static const reset_ip_name_t s_lcdResets[] = LCD_RSTS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+
+/*!
+ * @brief Gets the LCD instance according to the LCD base
+ *
+ * @param base LCD peripheral base address.
+ * @return LCD instance.
+ */
+static uint32_t LCDC_GetInstance(LCD_Type *base);
+
+/*!
+ * @brief Calculate the clock divider to generate desired panel clock.
+ *
+ * @param config Pointer to the LCD configuration.
+ * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz.
+ * @param divider The divider result.
+ * @return Return false if no divider available to generate the desired clock,
+ * otherwise return true;
+ */
+static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t LCDC_GetInstance(LCD_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_lcdBases); instance++)
+    {
+        if (s_lcdBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_lcdBases));
+
+    return instance;
+}
+
+static bool LCDC_GetClockDivider(const lcdc_config_t *config, uint32_t srcClock_Hz, uint32_t *divider)
+{
+    uint16_t cpl;
+    uint32_t pcd;
+
+    *divider = 0U;
+
+    /* Find the PCD. */
+    pcd = (srcClock_Hz + (config->panelClock_Hz / 2U)) / config->panelClock_Hz;
+
+    if (pcd <= 1U)
+    {
+        if (kLCDC_DisplayTFT == config->display)
+        {
+            pcd = 0U;
+            *divider = LCD_POL_BCD_MASK;
+        }
+        else
+        {
+            return false;
+        }
+    }
+    else
+    {
+        pcd -= 2U;
+
+        /* Verify the PCD value. */
+        if (pcd > LCD_PCD_MAX)
+        {
+            return false;
+        }
+
+        if (((kLCDC_DisplaySingleColorSTN8Bit == config->display) && (pcd < 1U)) ||
+            ((kLCDC_DisplayDualColorSTN8Bit == config->display) && (pcd < 4U)) ||
+            ((kLCDC_DisplaySingleMonoSTN4Bit == config->display) && (pcd < 2U)) ||
+            ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 8U)) ||
+            ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 8U)) ||
+            ((kLCDC_DisplayDualMonoSTN8Bit == config->display) && (pcd < 14U)))
+        {
+            return false;
+        }
+    }
+
+    if (config->display & LCD_CTRL_LCDTFT_MASK)
+    {
+        /* TFT panel. */
+        cpl = config->ppl - 1U;
+    }
+    else
+    {
+        if (config->display & LCD_CTRL_LCDBW_MASK)
+        {
+            if (config->display & LCD_CTRL_LCDMONO8_MASK)
+            {
+                /* 8-bit monochrome STN panel. */
+                cpl = (config->ppl / 8U) - 1U;
+            }
+            else
+            {
+                /* 4-bit monochrome STN panel. */
+                cpl = (config->ppl / 4U) - 1U;
+            }
+        }
+        else
+        {
+            /* Color STN panel. */
+            cpl = ((config->ppl * 3U) / 8U) - 1U;
+        }
+    }
+
+    *divider |= (LCD_POL_CPL(cpl) | LCD_POL_PCD(pcd));
+
+    return true;
+}
+
+status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz)
+{
+    assert(config);
+    assert(srcClock_Hz);
+    assert((config->ppl & 0xFU) == 0U);
+    assert((config->upperPanelAddr & 0x07U) == 0U);
+    assert((config->lowerPanelAddr & 0x07U) == 0U);
+
+    uint32_t reg;
+    uint32_t divider;
+    uint32_t instance;
+
+    /* Verify the clock here. */
+    if (!LCDC_GetClockDivider(config, srcClock_Hz, &divider))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = LCDC_GetInstance(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_lcdClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_lcdResets[instance]);
+
+    /* Set register CTRL. */
+    reg = base->CTRL & (LCD_CTRL_LCDVCOMP_MASK | LCD_CTRL_WATERMARK_MASK);
+    reg |= (uint32_t)(config->dataFormat) | (uint32_t)(config->display) | LCD_CTRL_LCDBPP(config->bpp);
+
+    if (config->swapRedBlue)
+    {
+        reg |= LCD_CTRL_BGR_MASK;
+    }
+
+    base->CTRL = reg;
+
+    /* Clean pending interrupts and disable all interrupts. */
+    base->INTCLR = LCDC_NORMAL_INT_MASK;
+    base->CRSR_INTCLR = LCDC_CURSOR_INT_MASK;
+    base->INTMSK = 0U;
+    base->CRSR_INTMSK = 0U;
+
+    /* Configure timing. */
+    base->TIMH = LCD_TIMH_PPL((config->ppl / 16U) - 1U) | LCD_TIMH_HSW(config->hsw - 1U) |
+                 LCD_TIMH_HFP(config->hfp - 1U) | LCD_TIMH_HBP(config->hbp - 1U);
+
+    base->TIMV = LCD_TIMV_LPP(config->lpp - 1U) | LCD_TIMV_VSW(config->vsw - 1U) | LCD_TIMV_VFP(config->vfp - 1U) |
+                 LCD_TIMV_VBP(config->vbp - 1U);
+
+    base->POL = (uint32_t)(config->polarityFlags) | LCD_POL_ACB(config->acBiasFreq - 1U) | divider;
+
+    /* Line end configuration. */
+    if (config->enableLineEnd)
+    {
+        base->LE = LCD_LE_LED(config->lineEndDelay - 1U) | LCD_LE_LEE_MASK;
+    }
+    else
+    {
+        base->LE = 0U;
+    }
+
+    /* Set panel frame base address. */
+    base->UPBASE = config->upperPanelAddr;
+    base->LPBASE = config->lowerPanelAddr;
+
+    return kStatus_Success;
+}
+
+void LCDC_Deinit(LCD_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(s_lcdClocks[LCDC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void LCDC_GetDefaultConfig(lcdc_config_t *config)
+{
+    config->panelClock_Hz = 0U;
+    config->ppl = 0U;
+    config->hsw = 0U;
+    config->hfp = 0U;
+    config->hbp = 0U;
+    config->lpp = 0U;
+    config->vsw = 0U;
+    config->vfp = 0U;
+    config->vbp = 0U;
+    config->acBiasFreq = 1U;
+    config->polarityFlags = 0U;
+    config->enableLineEnd = false;
+    config->lineEndDelay = 0U;
+    config->upperPanelAddr = 0U;
+    config->lowerPanelAddr = 0U;
+    config->bpp = kLCDC_1BPP;
+    config->dataFormat = kLCDC_LittleEndian;
+    config->swapRedBlue = false;
+    config->display = kLCDC_DisplayTFT;
+}
+
+void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr)
+{
+    /* The base address must be doubleword aligned. */
+    assert((addr & 0x07U) == 0U);
+
+    if (kLCDC_UpperPanel == panel)
+    {
+        base->UPBASE = addr;
+    }
+    else
+    {
+        base->LPBASE = addr;
+    }
+}
+
+void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words)
+{
+    assert(count_words <= ARRAY_SIZE(base->PAL));
+
+    uint32_t i;
+
+    for (i = 0; i < count_words; i++)
+    {
+        base->PAL[i] = palette[i];
+    }
+}
+
+void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask)
+{
+    uint32_t reg;
+
+    reg = mask & LCDC_CURSOR_INT_MASK;
+    if (reg)
+    {
+        base->CRSR_INTMSK |= reg;
+    }
+
+    reg = mask & LCDC_NORMAL_INT_MASK;
+    if (reg)
+    {
+        base->INTMSK |= reg;
+    }
+}
+
+void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask)
+{
+    uint32_t reg;
+
+    reg = mask & LCDC_CURSOR_INT_MASK;
+    if (reg)
+    {
+        base->CRSR_INTMSK &= ~reg;
+    }
+
+    reg = mask & LCDC_NORMAL_INT_MASK;
+    if (reg)
+    {
+        base->INTMSK &= ~reg;
+    }
+}
+
+uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->CRSR_INTRAW;
+    reg |= base->INTRAW;
+
+    return reg;
+}
+
+uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->CRSR_INTSTAT;
+    reg |= base->INTSTAT;
+
+    return reg;
+}
+
+void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask)
+{
+    uint32_t reg;
+
+    reg = mask & LCDC_CURSOR_INT_MASK;
+    if (reg)
+    {
+        base->CRSR_INTCLR = reg;
+    }
+
+    reg = mask & LCDC_NORMAL_INT_MASK;
+    if (reg)
+    {
+        base->INTCLR = reg;
+    }
+}
+
+void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config)
+{
+    assert(config);
+
+    uint32_t i;
+
+    base->CRSR_CFG = LCD_CRSR_CFG_CRSRSIZE(config->size) | LCD_CRSR_CFG_FRAMESYNC(config->syncMode);
+
+    /* Set position. */
+    LCDC_SetCursorPosition(base, 0, 0);
+
+    /* Palette. */
+    base->CRSR_PAL0 = ((uint32_t)config->palette0.red << LCD_CRSR_PAL0_RED_SHIFT) |
+                      ((uint32_t)config->palette0.blue << LCD_CRSR_PAL0_BLUE_SHIFT) |
+                      ((uint32_t)config->palette0.green << LCD_CRSR_PAL0_GREEN_SHIFT);
+    base->CRSR_PAL1 = ((uint32_t)config->palette1.red << LCD_CRSR_PAL1_RED_SHIFT) |
+                      ((uint32_t)config->palette1.blue << LCD_CRSR_PAL1_BLUE_SHIFT) |
+                      ((uint32_t)config->palette1.green << LCD_CRSR_PAL1_GREEN_SHIFT);
+
+    /* Image of cursors. */
+    if (kLCDC_CursorSize64 == config->size)
+    {
+        assert(config->image[0]);
+        LCDC_SetCursorImage(base, config->size, 0, config->image[0]);
+    }
+    else
+    {
+        for (i = 0; i < LCDC_CURSOR_COUNT; i++)
+        {
+            if (config->image[i])
+            {
+                LCDC_SetCursorImage(base, config->size, i, config->image[i]);
+            }
+        }
+    }
+}
+
+void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config)
+{
+    uint32_t i;
+
+    config->size = kLCDC_CursorSize32;
+    config->syncMode = kLCDC_CursorAsync;
+    config->palette0.red = 0U;
+    config->palette0.green = 0U;
+    config->palette0.blue = 0U;
+    config->palette1.red = 255U;
+    config->palette1.green = 255U;
+    config->palette1.blue = 255U;
+
+    for (i = 0; i < LCDC_CURSOR_COUNT; i++)
+    {
+        config->image[i] = (uint32_t *)0;
+    }
+}
+
+void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY)
+{
+    uint32_t clipX;
+    uint32_t clipY;
+
+    if (positionX < 0)
+    {
+        clipX = -positionX;
+        positionX = 0U;
+
+        /* If clip value too large, set to the max value. */
+        if (clipX > LCDC_CLIP_MAX)
+        {
+            clipX = LCDC_CLIP_MAX;
+        }
+    }
+    else
+    {
+        clipX = 0U;
+    }
+
+    if (positionY < 0)
+    {
+        clipY = -positionY;
+        positionY = 0U;
+
+        /* If clip value too large, set to the max value. */
+        if (clipY > LCDC_CLIP_MAX)
+        {
+            clipY = LCDC_CLIP_MAX;
+        }
+    }
+    else
+    {
+        clipY = 0U;
+    }
+
+    base->CRSR_CLIP = LCD_CRSR_CLIP_CRSRCLIPX(clipX) | LCD_CRSR_CLIP_CRSRCLIPY(clipY);
+    base->CRSR_XY = LCD_CRSR_XY_CRSRX(positionX) | LCD_CRSR_XY_CRSRY(positionY);
+}
+
+void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image)
+{
+    uint32_t regStart;
+    uint32_t i;
+    uint32_t len;
+
+    if (kLCDC_CursorSize64 == size)
+    {
+        regStart = 0U;
+        len = LCDC_CURSOR_IMG_64X64_WORDS;
+    }
+    else
+    {
+        regStart = index * LCDC_CURSOR_IMG_32X32_WORDS;
+        len = LCDC_CURSOR_IMG_32X32_WORDS;
+    }
+
+    for (i = 0U; i < len; i++)
+    {
+        base->CRSR_IMG[regStart + i] = image[i];
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,608 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_LCDC_H__
+#define __FSL_LCDC_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_lcdc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LCDC driver version 2.0.0. */
+#define LPC_LCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!@brief How many hardware cursors supports. */
+#define LCDC_CURSOR_COUNT 4
+
+/*!@brief LCD cursor image bits per pixel. */
+#define LCDC_CURSOR_IMG_BPP 2
+
+/*!@brief LCD 32x32 cursor image size in word(32-bit). */
+#define LCDC_CURSOR_IMG_32X32_WORDS (32 * 32 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
+
+/*!@brief LCD 64x64 cursor image size in word(32-bit). */
+#define LCDC_CURSOR_IMG_64X64_WORDS (64 * 64 * LCDC_CURSOR_IMG_BPP / (8 * sizeof(uint32_t)))
+
+/*!@brief LCD palette size in words(32-bit). */
+#define LCDC_PALETTE_SIZE_WORDS (ARRAY_SIZE(((LCD_Type *)0)->PAL))
+
+/*!
+ * @brief LCD sigal polarity flags.
+ */
+enum _lcdc_polarity_flags
+{
+    kLCDC_InvertVsyncPolarity = LCD_POL_IVS_MASK, /*!< Invert the VSYNC polarity, set to active low. */
+    kLCDC_InvertHsyncPolarity = LCD_POL_IHS_MASK, /*!< Invert the HSYNC polarity, set to active low. */
+    kLCDC_InvertClkPolarity = LCD_POL_IPC_MASK,   /*!< Invert the panel clock polarity, set to
+                                                      drive data on falling edge. */
+    kLCDC_InvertDePolarity = LCD_POL_IOE_MASK,    /*!< Invert the data enable (DE) polarity, set to active low. */
+};
+
+/*!
+ * @brief LCD bits per pixel.
+ */
+typedef enum _lcdc_bpp
+{
+    kLCDC_1BPP = 0U,     /*!< 1 bpp. */
+    kLCDC_2BPP = 1U,     /*!< 2 bpp. */
+    kLCDC_4BPP = 2U,     /*!< 4 bpp. */
+    kLCDC_8BPP = 3U,     /*!< 8 bpp. */
+    kLCDC_16BPP = 4U,    /*!< 16 bpp. */
+    kLCDC_24BPP = 5U,    /*!< 24 bpp, TFT panel only. */
+    kLCDC_16BPP565 = 6U, /*!< 16 bpp, 5:6:5 mode. */
+    kLCDC_12BPP = 7U,    /*!< 12 bpp, 4:4:4 mode. */
+} lcdc_bpp_t;
+
+/*!
+ * @brief The types of display panel.
+ */
+typedef enum _lcdc_display
+{
+    kLCDC_DisplayTFT = LCD_CTRL_LCDTFT_MASK, /*!< Active matrix TFT panels with up to 24-bit bus interface. */
+    kLCDC_DisplaySingleMonoSTN4Bit = LCD_CTRL_LCDBW_MASK, /*!< Single-panel monochrome STN (4-bit bus interface). */
+    kLCDC_DisplaySingleMonoSTN8Bit =
+        LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK, /*!< Single-panel monochrome STN (8-bit bus interface). */
+    kLCDC_DisplayDualMonoSTN4Bit =
+        LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (4-bit bus interface). */
+    kLCDC_DisplayDualMonoSTN8Bit = LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK |
+                                  LCD_CTRL_LCDDUAL_MASK,  /*!< Dual-panel monochrome STN (8-bit bus interface). */
+    kLCDC_DisplaySingleColorSTN8Bit = 0U,                  /*!< Single-panel color STN (8-bit bus interface). */
+    kLCDC_DisplayDualColorSTN8Bit = LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel coor STN (8-bit bus interface). */
+} lcdc_display_t;
+
+/*!
+ * @brief LCD panel buffer data format.
+ */
+typedef enum _lcdc_data_format
+{
+    kLCDC_LittleEndian = 0U,                                   /*!< Little endian byte, little endian pixel. */
+    kLCDC_BigEndian = LCD_CTRL_BEPO_MASK | LCD_CTRL_BEBO_MASK, /*!< Big endian byte, big endian pixel. */
+    kLCDC_WinCeMode = LCD_CTRL_BEPO_MASK, /*!< little-endian byte, big-endian pixel for Windows CE mode. */
+} lcdc_data_format_t;
+
+/*!
+ * @brief LCD configuration structure.
+ */
+typedef struct _lcdc_config
+{
+    uint32_t panelClock_Hz;  /*!< Panel clock in Hz. */
+    uint16_t ppl;            /*!< Pixels per line, it must could be divided by 16. */
+    uint8_t hsw;             /*!< HSYNC pulse width. */
+    uint8_t hfp;             /*!< Horizontal front porch. */
+    uint8_t hbp;             /*!< Horizontal back porch. */
+    uint16_t lpp;            /*!< Lines per panal. */
+    uint8_t vsw;             /*!< VSYNC pulse width. */
+    uint8_t vfp;             /*!< Vrtical front porch. */
+    uint8_t vbp;             /*!< Vertical back porch. */
+    uint8_t acBiasFreq;      /*!< The number of line clocks between AC bias pin toggling. Only used for STN display. */
+    uint16_t polarityFlags;  /*!< OR'ed value of @ref _lcdc_polarity_flags, used to contol the signal polarity. */
+    bool enableLineEnd;      /*!< Enable line end or not, the line end is a positive pulse with 4 panel clock. */
+    uint8_t lineEndDelay;    /*!< The panel clocks between the last pixel of line and the start of line end. */
+    uint32_t upperPanelAddr; /*!< LCD upper panel base address, must be double-word(64-bit) align. */
+    uint32_t lowerPanelAddr; /*!< LCD lower panel base address, must be double-word(64-bit) align. */
+    lcdc_bpp_t bpp;           /*!< LCD bits per pixel. */
+    lcdc_data_format_t dataFormat; /*!< Data format. */
+    bool swapRedBlue;             /*!< Set true to use BGR format, set false to choose RGB format. */
+    lcdc_display_t display;        /*!< The display type. */
+} lcdc_config_t;
+
+/*!
+ * @brief LCD vertical compare interrupt mode.
+ */
+typedef enum _lcdc_vertical_compare_interrupt_mode
+{
+    kLCDC_StartOfVsync,       /*!< Generate vertical compare interrupt at start of VSYNC. */
+    kLCDC_StartOfBackPorch,   /*!< Generate vertical compare interrupt at start of back porch. */
+    kLCDC_StartOfActiveVideo, /*!< Generate vertical compare interrupt at start of active video. */
+    kLCDC_StartOfFrontPorch,  /*!< Generate vertical compare interrupt at start of front porch. */
+} lcdc_vertical_compare_interrupt_mode_t;
+
+/*!
+ * @brief LCD interrupts.
+ */
+enum _lcdc_interrupts
+{
+    kLCDC_CursorInterrupt = LCD_CRSR_INTMSK_CRSRIM_MASK,      /*!< Cursor image read finished interrupt. */
+    kLCDC_FifoUnderflowInterrupt = LCD_INTMSK_FUFIM_MASK,     /*!< FIFO underflow interrupt. */
+    kLCDC_BaseAddrUpdateInterrupt = LCD_INTMSK_LNBUIM_MASK,   /*!< Panel frame base address update interrupt. */
+    kLCDC_VerticalCompareInterrupt = LCD_INTMSK_VCOMPIM_MASK, /*!< Vertical compare interrupt. */
+    kLCDC_AhbErrorInterrupt = LCD_INTMSK_BERIM_MASK,          /*!< AHB master error interrupt. */
+};
+
+/*!
+ * @brief LCD panel frame.
+ */
+typedef enum _lcdc_panel
+{
+    kLCDC_UpperPanel, /*!< Upper panel frame. */
+    kLCDC_LowerPanel  /*!< Lower panel frame. */
+} lcdc_panel_t;
+
+/*!
+ * @brief LCD hardware cursor size
+ */
+typedef enum _lcdc_cursor_size
+{
+    kLCDC_CursorSize32, /*!< 32x32 pixel cursor. */
+    kLCDC_CursorSize64, /*!< 64x64 pixel cursor. */
+} lcdc_cursor_size_t;
+
+/*!
+ * @brief LCD hardware cursor palette
+ */
+typedef struct _lcdc_cursor_palette
+{
+    uint8_t red;   /*!< Red color component. */
+    uint8_t green; /*!< Red color component. */
+    uint8_t blue;  /*!< Red color component. */
+} lcdc_cursor_palette_t;
+
+/*!
+ * @brief LCD hardware cursor frame synchronization mode.
+ */
+typedef enum _lcdc_cursor_sync_mode
+{
+    kLCDC_CursorAsync, /*!< Cursor change will be displayed immediately. */
+    kLCDC_CursorSync,  /*!< Cursor change will be displayed in next frame. */
+} lcdc_cursor_sync_mode_t;
+
+/*!
+ * @brief LCD hardware cursor configuration structure.
+ */
+typedef struct _lcdc_cursor_config
+{
+    lcdc_cursor_size_t size;            /*!< Cursor size. */
+    lcdc_cursor_sync_mode_t syncMode;   /*!< Cursor synchronization mode. */
+    lcdc_cursor_palette_t palette0;     /*!< Cursor palette 0. */
+    lcdc_cursor_palette_t palette1;     /*!< Cursor palette 1. */
+    uint32_t *image[LCDC_CURSOR_COUNT]; /*!< Pointer to cursor image data. */
+} lcdc_cursor_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @name Initialization and Deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initialize the LCD module.
+ *
+ * @param base LCD peripheral base address.
+ * @param config Pointer to configuration structure, see to @ref lcdc_config_t.
+ * @param srcClock_Hz The LCD input clock (LCDCLK) frequency in Hz.
+ * @retval kStatus_Success LCD is initialized successfully.
+ * @retval kStatus_InvalidArgument Initlialize failed because of invalid argument.
+ */
+status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitialize the LCD module.
+ *
+ * @param base LCD peripheral base address.
+ */
+void LCDC_Deinit(LCD_Type *base);
+
+/*!
+ * @brief Gets default pre-defined settings for initial configuration.
+ *
+ * This function initializes the configuration structure. The default values are:
+ *
+   @code
+    config->panelClock_Hz = 0U;
+    config->ppl = 0U;
+    config->hsw = 0U;
+    config->hfp = 0U;
+    config->hbp = 0U;
+    config->lpp = 0U;
+    config->vsw = 0U;
+    config->vfp = 0U;
+    config->vbp = 0U;
+    config->acBiasFreq = 1U;
+    config->polarityFlags = 0U;
+    config->enableLineEnd = false;
+    config->lineEndDelay = 0U;
+    config->upperPanelAddr = 0U;
+    config->lowerPanelAddr = 0U;
+    config->bpp = kLCDC_1BPP;
+    config->dataFormat = kLCDC_LittleEndian;
+    config->swapRedBlue = false;
+    config->display = kLCDC_DisplayTFT;
+   @endcode
+ *
+ * @param config Pointer to configuration structure.
+ */
+void LCDC_GetDefaultConfig(lcdc_config_t *config);
+
+/* @} */
+
+/*!
+ * @name Start and stop
+ * @{
+ */
+
+/*!
+ * @brief Start to output LCD timing signal.
+ *
+ * The LCD power up sequence should be:
+ * 1. Apply power to LCD, here all output signals are held low.
+ * 2. When LCD power stablized, call @ref LCDC_Start to output the timing signals.
+ * 3. Apply contrast voltage to LCD panel. Delay if the display requires.
+ * 4. Call @ref LCDC_PowerUp.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_Start(LCD_Type *base)
+{
+    base->CTRL |= LCD_CTRL_LCDEN_MASK;
+}
+
+/*!
+ * @brief Stop the LCD timing signal.
+ *
+ * The LCD power down sequence should be:
+ * 1. Call @ref LCDC_PowerDown.
+ * 2. Delay if the display requires. Disable contrast voltage to LCD panel.
+ * 3. Call @ref LCDC_Stop to disable the timing signals.
+ * 4. Disable power to LCD.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_Stop(LCD_Type *base)
+{
+    base->CTRL &= ~LCD_CTRL_LCDEN_MASK;
+}
+
+/*!
+ * @brief Power up the LCD and output the pixel signal.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_PowerUp(LCD_Type *base)
+{
+    base->CTRL |= LCD_CTRL_LCDPWR_MASK;
+}
+
+/*!
+ * @brief Power down the LCD and disable the output pixel signal.
+ *
+ * @param base LCD peripheral base address.
+ */
+static inline void LCDC_PowerDown(LCD_Type *base)
+{
+    base->CTRL &= ~LCD_CTRL_LCDPWR_MASK;
+}
+
+/* @} */
+
+/*!
+ * @name LCD control
+ * @{
+ */
+
+/*!
+ * @brief Sets panel frame base address
+ *
+ * @param base LCD peripheral base address.
+ * @param panel Which panel to set.
+ * @param addr Frame base address, must be doubleword(64-bit) aligned.
+ */
+void LCDC_SetPanelAddr(LCD_Type *base, lcdc_panel_t panel, uint32_t addr);
+
+/*!
+ * @brief Sets palette
+ *
+ * @param base LCD peripheral base address.
+ * @param palette Pointer to the palette array.
+ * @param count_words Length of the palette array to set (how many words), it should
+ * not be larger than LCDC_PALETTE_SIZE_WORDS.
+ */
+void LCDC_SetPalette(LCD_Type *base, const uint32_t *palette, uint8_t count_words);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Sets the vertical compare interrupt mode.
+ *
+ * @param base LCD peripheral base address.
+ * @param mode The vertical compare interrupt mode.
+ */
+static inline void LCDC_SetVerticalInterruptMode(LCD_Type *base, lcdc_vertical_compare_interrupt_mode_t mode)
+{
+    base->CTRL = (base->CTRL & ~LCD_CTRL_LCDVCOMP_MASK) | LCD_CTRL_LCDVCOMP(mode);
+}
+
+/*!
+ * @brief Enable LCD interrupts.
+ *
+ * Example to enable LCD base address update interrupt and vertical compare
+ * interrupt:
+ *
+ * @code
+   LCDC_EnableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @param mask Interrupts to enable, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+void LCDC_EnableInterrupts(LCD_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disable LCD interrupts.
+ *
+ * Example to disable LCD base address update interrupt and vertical compare
+ * interrupt:
+ *
+ * @code
+   LCDC_DisableInterrupts(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+void LCDC_DisableInterrupts(LCD_Type *base, uint32_t mask);
+
+/*!
+ * @brief Get LCD interrupt pending status.
+ *
+ * Example:
+ *
+ * @code
+   uint32_t status;
+
+   status = LCDC_GetInterruptsPendingStatus(LCD);
+
+   if (kLCDC_BaseAddrUpdateInterrupt & status)
+   {
+       // LCD base address update interrupt occurred.
+   }
+
+   if (kLCDC_VerticalCompareInterrupt & status)
+   {
+       // LCD vertical compare interrupt occurred.
+   }
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+uint32_t LCDC_GetInterruptsPendingStatus(LCD_Type *base);
+
+/*!
+ * @brief Get LCD enabled interrupt pending status.
+ *
+ * This function is similar with @ref LCDC_GetInterruptsPendingStatus, the only
+ * difference is, this function only returns the pending status of the
+ * interrupts that have been enabled using @ref LCDC_EnableInterrupts.
+ *
+ * @param base LCD peripheral base address.
+ * @return Interrupts pending status, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+uint32_t LCDC_GetEnabledInterruptsPendingStatus(LCD_Type *base);
+
+/*!
+ * @brief Clear LCD interrupts pending status.
+ *
+ * Example to clear LCD base address update interrupt and vertical compare
+ * interrupt pending status:
+ *
+ * @code
+   LCDC_ClearInterruptsStatus(LCD, kLCDC_BaseAddrUpdateInterrupt | kLCDC_VerticalCompareInterrupt);
+   @endcode
+ *
+ * @param base LCD peripheral base address.
+ * @param mask Interrupts to disable, it is OR'ed value of @ref _lcdc_interrupts.
+ */
+void LCDC_ClearInterruptsStatus(LCD_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Hardware cursor
+ * @{
+ */
+
+/*!
+ * @brief Set the hardware cursor configuration
+ *
+ * This function should be called before enabling the hardware cursor.
+ * It supports initializing multiple cursor images at a time when using
+ * 32x32 pixels cursor.
+ *
+ * For example:
+ *
+ * @code
+   uint32_t cursor0Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...};
+   uint32_t cursor2Img[LCDC_CURSOR_IMG_32X32_WORDS] = {...};
+
+   lcdc_cursor_config_t cursorConfig;
+
+   LCDC_CursorGetDefaultConfig(&cursorConfig);
+
+   cursorConfig.image[0] = cursor0Img;
+   cursorConfig.image[2] = cursor2Img;
+
+   LCDC_SetCursorConfig(LCD, &cursorConfig);
+
+   LCDC_ChooseCursor(LCD, 0);
+   LCDC_SetCursorPosition(LCD, 0, 0);
+
+   LCDC_EnableCursor(LCD);
+   @endcode
+ *
+ * In this example, cursor 0 and cursor 2 image data are initialized, but cursor 1
+ * and cursor 3 image data are not initialized because image[1] and image[2] are
+ * all NULL. With this, application could initializes all cursor images it will
+ * use at the beginning and call @ref LCDC_SetCursorImage directly to display the
+ * one which it needs.
+ *
+ * @param base LCD peripheral base address.
+ * @param config Pointer to the hardware cursor configuration structure.
+ */
+void LCDC_SetCursorConfig(LCD_Type *base, const lcdc_cursor_config_t *config);
+
+/*!
+ * @brief Get the hardware cursor default configuration
+ *
+ * The default configuration values are:
+ *
+ * @code
+    config->size = kLCDC_CursorSize32;
+    config->syncMode = kLCDC_CursorAsync;
+    config->palette0.red = 0U;
+    config->palette0.green = 0U;
+    config->palette0.blue = 0U;
+    config->palette1.red = 255U;
+    config->palette1.green = 255U;
+    config->palette1.blue = 255U;
+    config->image[0] = (uint32_t *)0;
+    config->image[1] = (uint32_t *)0;
+    config->image[2] = (uint32_t *)0;
+    config->image[3] = (uint32_t *)0;
+   @endcode
+ *
+ * @param config Pointer to the hardware cursor configuration structure.
+ */
+void LCDC_CursorGetDefaultConfig(lcdc_cursor_config_t *config);
+
+/*!
+ * @brief Enable or disable the cursor.
+ *
+ * @param base LCD peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LCDC_EnableCursor(LCD_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CRSR_CTRL |= LCD_CRSR_CTRL_CRSRON_MASK;
+    }
+    else
+    {
+        base->CRSR_CTRL &= ~LCD_CRSR_CTRL_CRSRON_MASK;
+    }
+}
+
+/*!
+ * @brief Choose which cursor to display.
+ *
+ * When using 32x32 cursor, the number of cursors supports is @ref LCDC_CURSOR_COUNT.
+ * When using 64x64 cursor, the LCD only supports one cursor.
+ * This function selects which cursor to display when using 32x32 cursor.
+ * When synchronization mode is @ref kLCDC_CursorSync, the change effects in the
+ * next frame. When synchronization mode is @ref * kLCDC_CursorAsync, change effects
+ * immediately.
+ *
+ * @param base LCD peripheral base address.
+ * @param index Index of the cursor to display.
+ * @note The function @ref LCDC_SetCursorPosition must be called after this function
+ * to show the new cursor.
+ */
+static inline void LCDC_ChooseCursor(LCD_Type *base, uint8_t index)
+{
+    base->CRSR_CTRL = (base->CRSR_CTRL & ~LCD_CRSR_CTRL_CRSRNUM1_0_MASK) | LCD_CRSR_CTRL_CRSRNUM1_0(index);
+}
+
+/*!
+ * @brief Set the position of cursor
+ *
+ * When synchronization mode is @ref kLCDC_CursorSync, position change effects
+ * in the next frame. When synchronization mode is @ref kLCDC_CursorAsync,
+ * position change effects immediately.
+ *
+ * @param base LCD peripheral base address.
+ * @param positionX X ordinate of the cursor top-left measured in pixels
+ * @param positionY Y ordinate of the cursor top-left measured in pixels
+ */
+void LCDC_SetCursorPosition(LCD_Type *base, int32_t positionX, int32_t positionY);
+
+/*!
+ * @brief Set the cursor image.
+ *
+ * The interrupt @ref kLCDC_CursorInterrupt indicates that last cursor pixel is
+ * displayed. When the hardware cursor is enabled,
+ *
+ * @param base LCD peripheral base address.
+ * @param size The cursor size.
+ * @param index Index of the cursor to set when using 32x32 cursor.
+ * @param image Pointer to the cursor image. When using 32x32 cursor, the image
+ * size should be LCDC_CURSOR_IMG_32X32_WORDS. When using 64x64 cursor, the image
+ * size should be LCDC_CURSOR_IMG_64X64_WORDS.
+ */
+void LCDC_SetCursorImage(LCD_Type *base, lcdc_cursor_size_t size, uint8_t index, const uint32_t *image);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __FSL_LCDC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,862 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mcan.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+
+#define MCAN_TIME_QUANTA_NUM (16U)
+
+/*! @brief MCAN Internal State. */
+enum _mcan_state
+{
+    kMCAN_StateIdle = 0x0,     /*!< MB/RxFIFO idle.*/
+    kMCAN_StateRxData = 0x1,   /*!< MB receiving.*/
+    kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/
+    kMCAN_StateTxData = 0x3,   /*!< MB transmitting.*/
+    kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/
+    kMCAN_StateRxFifo = 0x5,   /*!< RxFIFO receiving.*/
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the MCAN instance from peripheral base address.
+ *
+ * @param base MCAN peripheral base address.
+ * @return MCAN instance.
+ */
+uint32_t MCAN_GetInstance(CAN_Type *base);
+
+/*!
+ * @brief Reset the MCAN instance.
+ *
+ * @param base MCAN peripheral base address.
+ */
+static void MCAN_Reset(CAN_Type *base);
+
+/*!
+ * @brief Set Baud Rate of MCAN.
+ *
+ * This function set the baud rate of MCAN.
+ *
+ * @param base MCAN peripheral base address.
+ * @param sourceClock_Hz Source Clock in Hz.
+ * @param baudRate_Bps Baud Rate in Bps.
+ */
+static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps);
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+/*!
+ * @brief Set Baud Rate of MCAN FD.
+ *
+ * This function set the baud rate of MCAN FD.
+ *
+ * @param base MCAN peripheral base address.
+ * @param sourceClock_Hz Source Clock in Hz.
+ * @param baudRateD_Bps Baud Rate in Bps.
+ */
+static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps);
+#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
+
+/*!
+ * @brief Get the element's address when read receive fifo 0.
+ *
+ * @param base MCAN peripheral base address.
+ * @return Address of the element in receive fifo 0.
+ */
+static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base);
+
+/*!
+ * @brief Get the element's address when read receive fifo 1.
+ *
+ * @param base MCAN peripheral base address.
+ * @return Address of the element in receive fifo 1.
+ */
+static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base);
+
+/*!
+ * @brief Get the element's address when read receive buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Number of the erceive buffer element.
+ * @return Address of the element in receive buffer.
+ */
+static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx);
+
+/*!
+ * @brief Get the element's address when read transmit buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Number of the transmit buffer element.
+ * @return Address of the element in transmit buffer.
+ */
+static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of MCAN handle. */
+static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT];
+
+/* Array of MCAN peripheral base address. */
+static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS;
+
+/* Array of MCAN IRQ number. */
+static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of MCAN clock name. */
+static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* MCAN ISR for transactional APIs. */
+static mcan_isr_t s_mcanIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t MCAN_GetInstance(CAN_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++)
+    {
+        if (s_mcanBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_mcanBases));
+
+    return instance;
+}
+
+static void MCAN_Reset(CAN_Type *base)
+{
+    /* Set INIT bit. */
+    base->CCCR |= CAN_CCCR_INIT_MASK;
+    /* Confirm the value has been accepted. */
+    while (!((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT))
+    {
+    }
+
+    /* Set CCE bit to have access to the protected configuration registers,
+       and clear some status registers. */
+    base->CCCR |= CAN_CCCR_CCE_MASK;
+}
+
+static void MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateA_Bps)
+{
+    mcan_timing_config_t timingConfigA;
+    uint32_t preDivA = baudRateA_Bps * MCAN_TIME_QUANTA_NUM;
+
+    if (0 == preDivA)
+    {
+        preDivA = 1U;
+    }
+
+    preDivA = (sourceClock_Hz / preDivA) - 1U;
+
+    /* Desired baud rate is too low. */
+    if (preDivA > 0x1FFU)
+    {
+        preDivA = 0x1FFU;
+    }
+
+    /* MCAN timing setting formula:
+     * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1));
+     */
+    timingConfigA.preDivider = preDivA;
+    timingConfigA.seg1 = 0xAU;
+    timingConfigA.seg2 = 0x3U;
+    timingConfigA.rJumpwidth = 0x3U;
+
+    /* Update actual timing characteristic. */
+    MCAN_SetArbitrationTimingConfig(base, &timingConfigA);
+}
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+static void MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateD_Bps)
+{
+    mcan_timing_config_t timingConfigD;
+    uint32_t preDivD = baudRateD_Bps * MCAN_TIME_QUANTA_NUM;
+
+    if (0 == preDivD)
+    {
+        preDivD = 1U;
+    }
+
+    preDivD = (sourceClock_Hz / preDivD) - 1U;
+
+    /* Desired baud rate is too low. */
+    if (preDivD > 0x1FU)
+    {
+        preDivD = 0x1FU;
+    }
+
+    /* MCAN timing setting formula:
+     * MCAN_TIME_QUANTA_NUM = 1 + (xTSEG1 + 1) + (xTSEG2 + 1));
+     */
+    timingConfigD.preDivider = preDivD;
+    timingConfigD.seg1 = 0xAU;
+    timingConfigD.seg2 = 0x3U;
+    timingConfigD.rJumpwidth = 0x3U;
+
+    /* Update actual timing characteristic. */
+    MCAN_SetDataTimingConfig(base, &timingConfigD);
+}
+#endif
+
+void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable MCAN clock. */
+    CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    MCAN_Reset(base);
+
+    if (config->enableLoopBackInt)
+    {
+        base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK;
+        base->TEST |= CAN_TEST_LBCK_MASK;
+    }
+    if (config->enableLoopBackExt)
+    {
+        base->CCCR |= CAN_CCCR_TEST_MASK;
+        base->TEST |= CAN_TEST_LBCK_MASK;
+    }
+    if (config->enableBusMon)
+    {
+        base->CCCR |= CAN_CCCR_MON_MASK;
+    }
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+    if (config->enableCanfdNormal)
+    {
+        base->CCCR |= CAN_CCCR_FDOE_MASK;
+    }
+    if (config->enableCanfdSwitch)
+    {
+        base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK;
+    }
+#endif
+
+    /* Set baud rate of arbitration and data phase. */
+    MCAN_SetBaudRate(base, sourceClock_Hz, config->baudRateA);
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+    MCAN_SetBaudRateFD(base, sourceClock_Hz, config->baudRateD);
+#endif
+}
+
+void MCAN_Deinit(CAN_Type *base)
+{
+    /* Reset all Register Contents. */
+    MCAN_Reset(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable MCAN clock. */
+    CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void MCAN_EnterNormalMode(CAN_Type *base)
+{
+    /* Reset INIT bit to enter normal mode. */
+    base->CCCR &= ~CAN_CCCR_INIT_MASK;
+    while (((base->CCCR & CAN_CCCR_INIT_MASK) >> CAN_CCCR_INIT_SHIFT))
+    {
+    }
+}
+
+void MCAN_GetDefaultConfig(mcan_config_t *config)
+{
+    /* Assertion. */
+    assert(config);
+
+    /* Initialize MCAN Module config struct with default value. */
+    config->baudRateA = 500000U;
+    config->baudRateD = 500000U;
+    config->enableCanfdNormal = false;
+    config->enableCanfdSwitch = false;
+    config->enableLoopBackInt = false;
+    config->enableLoopBackExt = false;
+    config->enableBusMon = false;
+}
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config)
+{
+    /* Assertion. */
+    assert(config);
+
+    /* Cleaning previous Timing Setting. */
+    base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK);
+
+    /* Updating Timing Setting according to configuration structure. */
+    base->DBTP |= (CAN_DBTP_DBRP(config->preDivider) | CAN_DBTP_DSJW(config->rJumpwidth) |
+                   CAN_DBTP_DTSEG1(config->seg1) | CAN_DBTP_DTSEG2(config->seg2));
+}
+#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
+
+void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config)
+{
+    /* Assertion. */
+    assert(config);
+
+    /* Cleaning previous Timing Setting. */
+    base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK);
+
+    /* Updating Timing Setting according to configuration structure. */
+    base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) |
+                   CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2));
+}
+
+void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config)
+{
+    /* Set global configuration of remote/nonmasking frames, set filter address and list size. */
+    if (config->idFormat == kMCAN_FrameIDStandard)
+    {
+        base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame);
+        base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize);
+    }
+    else
+    {
+        base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame);
+        base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize);
+    }
+}
+
+void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config)
+{
+    /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */
+    base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) |
+                   CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode);
+    /* Set Rx FIFO 0 data field size */
+    base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize);
+}
+
+void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config)
+{
+    /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */
+    base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) |
+                   CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode);
+    /* Set Rx FIFO 1 data field size */
+    base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize);
+}
+
+void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config)
+{
+    /* Set Rx Buffer start address. */
+    base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT);
+    /* Set Rx Buffer data field size */
+    base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize);
+}
+
+void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config)
+{
+    /* Set TX Event FIFO start address, element size, watermark. */
+    base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) |
+                   CAN_TXEFC_EFWM(config->watermark);
+}
+
+void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config)
+{
+    assert((config->dedicatedSize + config->fqSize) <= 32U);
+
+    /* Set Tx Buffer start address, size, fifo/queue mode. */
+    base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) |
+                  CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode);
+    /* Set Tx Buffer data field size */
+    base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize);
+}
+
+void MCAN_SetSTDFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_std_filter_element_config_t *filter,
+                              uint8_t idx)
+{
+    uint8_t *elementAddress = 0;
+    elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U);
+    memcpy(elementAddress, filter, sizeof(filter));
+}
+
+void MCAN_SetEXTFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_ext_filter_element_config_t *filter,
+                              uint8_t idx)
+{
+    uint8_t *elementAddress = 0;
+    elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U);
+    memcpy(elementAddress, filter, sizeof(filter));
+}
+
+static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base)
+{
+    uint32_t eSize;
+    eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->RXF0C & CAN_RXF0C_F0SA_MASK) +
+           ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U;
+}
+
+static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base)
+{
+    uint32_t eSize;
+    eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->RXF1C & CAN_RXF1C_F1SA_MASK) +
+           ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U;
+}
+
+static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 63U);
+    uint32_t eSize;
+    eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U;
+}
+
+static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 31U);
+    uint32_t eSize;
+    eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT;
+    if (eSize < 5U)
+    {
+        eSize += 4U;
+    }
+    else
+    {
+        eSize = eSize * 4U - 10U;
+    }
+    return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U;
+}
+
+uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx)
+{
+    return (base->TXBRP & (uint32_t)(1U << idx)) >> (uint32_t)idx;
+}
+
+uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx)
+{
+    return (base->TXBTO & (uint32_t)(1U << idx)) >> (uint32_t)idx;
+}
+
+status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame)
+{
+    if (!MCAN_IsTransmitRequestPending(base, idx))
+    {
+        uint8_t *elementAddress = 0;
+        elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx));
+
+        /* Write 2 words configuration field. */
+        memcpy(elementAddress, (uint8_t *)txFrame, 8U);
+        /* Write data field. */
+        memcpy(elementAddress + 8U, txFrame->data, txFrame->size);
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+}
+
+status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *rxFrame)
+{
+    mcan_rx_buffer_frame_t *elementAddress = 0;
+    elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx));
+    memcpy(rxFrame, elementAddress, (rxFrame->size + 8U) * 4U);
+    return kStatus_Success;
+}
+
+status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame)
+{
+    assert((fifoBlock == 0) || (fifoBlock == 1U));
+    mcan_rx_buffer_frame_t *elementAddress = 0;
+    if (0 == fifoBlock)
+    {
+        elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base));
+    }
+    else
+    {
+        elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base));
+    }
+    memcpy(rxFrame, elementAddress, 8U);
+    rxFrame->data = (uint8_t *)elementAddress + 8U;
+    /* Acknowledge the read. */
+    if (0 == fifoBlock)
+    {
+        base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT;
+    }
+    else
+    {
+        base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT;
+    }
+    return kStatus_Success;
+}
+
+status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame)
+{
+    if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, txFrame))
+    {
+        MCAN_TransmitAddRequest(base, idx);
+
+        /* Wait until message sent out. */
+        while (!MCAN_IsTransmitOccurred(base, idx))
+        {
+        }
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+}
+
+status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t bufferIdx, mcan_rx_buffer_frame_t *rxFrame)
+{
+    assert(bufferIdx <= 63U);
+
+    while (!MCAN_GetRxBufferStatusFlag(base, bufferIdx))
+    {
+    }
+    MCAN_ClearRxBufferStatusFlag(base, bufferIdx);
+    return MCAN_ReadRxBuffer(base, bufferIdx, rxFrame);
+}
+
+status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame)
+{
+    assert((fifoBlock == 0) || (fifoBlock == 1U));
+    if (0 == fifoBlock)
+    {
+        while (!MCAN_GetStatusFlag(base, CAN_IR_RF0N_MASK))
+        {
+        }
+        MCAN_ClearStatusFlag(base, CAN_IR_RF0N_MASK);
+    }
+    else
+    {
+        while (!MCAN_GetStatusFlag(base, CAN_IR_RF1N_MASK))
+        {
+        }
+        MCAN_ClearStatusFlag(base, CAN_IR_RF1N_MASK);
+    }
+    return MCAN_ReadRxFifo(base, fifoBlock, rxFrame);
+}
+
+void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData)
+{
+    assert(handle);
+
+    uint8_t instance;
+
+    /* Clean MCAN transfer handle. */
+    memset(handle, 0, sizeof(*handle));
+
+    /* Get instance from peripheral base address. */
+    instance = MCAN_GetInstance(base);
+
+    /* Save the context in global variables to support the double weak mechanism. */
+    s_mcanHandle[instance] = handle;
+
+    /* Register Callback function. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    s_mcanIsr = MCAN_TransferHandleIRQ;
+
+    /* We Enable Error & Status interrupt here, because this interrupt just
+     * report current status of MCAN module through Callback function.
+     * It is insignificance without a available callback function.
+     */
+    if (handle->callback != NULL)
+    {
+        MCAN_EnableInterrupts(base, 0,
+                              kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable);
+    }
+    else
+    {
+        MCAN_DisableInterrupts(base,
+                               kMCAN_BusOffInterruptEnable | kMCAN_ErrorInterruptEnable | kMCAN_WarningInterruptEnable);
+    }
+
+    /* Enable interrupts in NVIC. */
+    EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0]));
+    EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1]));
+}
+
+status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer)
+{
+    /* Assertion. */
+    assert(handle);
+    assert(xfer);
+    assert(xfer->bufferIdx <= 63U);
+
+    /* Check if Tx Buffer is idle. */
+    if (kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx])
+    {
+        handle->txbufferIdx = xfer->bufferIdx;
+        /* Distinguish transmit type. */
+        if (kMCAN_FrameTypeRemote == xfer->frame->xtd)
+        {
+            handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxRemote;
+
+            /* Register user Frame buffer to receive remote Frame. */
+            handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame;
+        }
+        else
+        {
+            handle->bufferState[xfer->bufferIdx] = kMCAN_StateTxData;
+        }
+
+        if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame))
+        {
+            /* Enable Buffer Interrupt. */
+            MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx);
+            MCAN_EnableInterrupts(base, 0, CAN_IE_TCE_MASK);
+
+            MCAN_TransmitAddRequest(base, xfer->bufferIdx);
+
+            return kStatus_Success;
+        }
+        else
+        {
+            handle->bufferState[xfer->bufferIdx] = kMCAN_StateIdle;
+            return kStatus_Fail;
+        }
+    }
+    else
+    {
+        return kStatus_MCAN_TxBusy;
+    }
+}
+
+status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
+                                             uint8_t fifoBlock,
+                                             mcan_handle_t *handle,
+                                             mcan_fifo_transfer_t *xfer)
+{
+    /* Assertion. */
+    assert((fifoBlock == 0) || (fifoBlock == 1U));
+    assert(handle);
+    assert(xfer);
+
+    /* Check if Message Buffer is idle. */
+    if (kMCAN_StateIdle == handle->rxFifoState)
+    {
+        handle->rxFifoState = kMCAN_StateRxFifo;
+
+        /* Register Message Buffer. */
+        handle->rxFifoFrameBuf = xfer->frame;
+
+        /* Enable FIFO Interrupt. */
+        if (fifoBlock)
+        {
+            MCAN_EnableInterrupts(base, 0, CAN_IE_RF1NE_MASK);
+        }
+        else
+        {
+            MCAN_EnableInterrupts(base, 0, CAN_IE_RF0NE_MASK);
+        }
+        return kStatus_Success;
+    }
+    else
+    {
+        return fifoBlock ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy;
+    }
+}
+
+void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx)
+{
+    /* Assertion. */
+    assert(handle);
+    assert(bufferIdx <= 63U);
+
+    /* Disable Buffer Interrupt. */
+    MCAN_DisableTransmitBufferInterrupts(base, bufferIdx);
+    MCAN_DisableInterrupts(base, CAN_IE_TCE_MASK);
+
+    /* Cancel send request. */
+    MCAN_TransmitCancelRequest(base, bufferIdx);
+
+    /* Un-register handle. */
+    handle->bufferFrameBuf[bufferIdx] = 0x0;
+
+    handle->bufferState[bufferIdx] = kMCAN_StateIdle;
+}
+
+void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle)
+{
+    /* Assertion. */
+    assert(handle);
+    assert((fifoBlock == 0) || (fifoBlock == 1));
+
+    /* Check if Rx FIFO is enabled. */
+    if (fifoBlock)
+    {
+        /* Disable Rx Message FIFO Interrupts. */
+        MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK);
+    }
+    else
+    {
+        MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK);
+    }
+    /* Un-register handle. */
+    handle->rxFifoFrameBuf = 0x0;
+
+    handle->rxFifoState = kMCAN_StateIdle;
+}
+
+void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle)
+{
+    /* Assertion. */
+    assert(handle);
+
+    status_t status = kStatus_MCAN_UnHandled;
+    uint32_t result;
+
+    /* Store Current MCAN Module Error and Status. */
+    result = base->IR;
+
+    do
+    {
+        /* Solve Rx FIFO, Tx interrupt. */
+        if (result & kMCAN_TxTransmitCompleteFlag)
+        {
+            status = kStatus_MCAN_TxIdle;
+            MCAN_TransferAbortSend(base, handle, handle->txbufferIdx);
+        }
+        else if (result & kMCAN_RxFifo0NewFlag)
+        {
+            MCAN_ReadRxFifo(base, 0, handle->rxFifoFrameBuf);
+            status = kStatus_MCAN_RxFifo0Idle;
+            MCAN_TransferAbortReceiveFifo(base, 0, handle);
+        }
+        else if (result & kMCAN_RxFifo0LostFlag)
+        {
+            status = kStatus_MCAN_RxFifo0Lost;
+        }
+        else if (result & kMCAN_RxFifo1NewFlag)
+        {
+            MCAN_ReadRxFifo(base, 1, handle->rxFifoFrameBuf);
+            status = kStatus_MCAN_RxFifo1Idle;
+            MCAN_TransferAbortReceiveFifo(base, 1, handle);
+        }
+        else if (result & kMCAN_RxFifo1LostFlag)
+        {
+            status = kStatus_MCAN_RxFifo0Lost;
+        }
+        else
+        {
+            ;
+        }
+
+        /* Clear resolved Rx FIFO, Tx Buffer IRQ. */
+        MCAN_ClearStatusFlag(base, result);
+
+        /* Calling Callback Function if has one. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, status, result, handle->userData);
+        }
+
+        /* Reset return status */
+        status = kStatus_MCAN_UnHandled;
+
+        /* Store Current MCAN Module Error and Status. */
+        result = base->IR;
+    } while ((0 != MCAN_GetStatusFlag(base, 0xFFFFFFFFU)) ||
+             (0 != (result & (kMCAN_ErrorWarningIntFlag | kMCAN_BusOffIntFlag | kMCAN_ErrorPassiveIntFlag))));
+}
+
+#if defined(CAN0)
+void CAN0_IRQ0_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[0]);
+
+    s_mcanIsr(CAN0, s_mcanHandle[0]);
+}
+
+void CAN0_IRQ1_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[0]);
+
+    s_mcanIsr(CAN0, s_mcanHandle[0]);
+}
+#endif
+
+#if defined(CAN1)
+void CAN1_IRQ0_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[1]);
+
+    s_mcanIsr(CAN1, s_mcanHandle[1]);
+}
+
+void CAN1_IRQ1_DriverIRQHandler(void)
+{
+    assert(s_mcanHandle[1]);
+
+    s_mcanIsr(CAN1, s_mcanHandle[1]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,966 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_MCAN_H_
+#define _FSL_MCAN_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mcan
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief MCAN driver version 2.0.0. */
+#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief MCAN transfer status. */
+enum _mcan_status
+{
+    kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0),            /*!< Tx Buffer is Busy. */
+    kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1),            /*!< Tx Buffer is Idle. */
+    kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2),            /*!< Rx Buffer is Busy. */
+    kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3),            /*!< Rx Buffer is Idle. */
+    kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4),        /*!< New message written to Rx FIFO 0. */
+    kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5),       /*!< Rx FIFO 0 is Idle. */
+    kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6),  /*!< Rx FIFO 0 fill level reached watermark. */
+    kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7),       /*!< Rx FIFO 0 full. */
+    kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8),       /*!< Rx FIFO 0 message lost. */
+    kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9),        /*!< New message written to Rx FIFO 1. */
+    kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10),      /*!< Rx FIFO 1 is Idle. */
+    kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */
+    kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12),      /*!< Rx FIFO 1 full. */
+    kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13),      /*!< Rx FIFO 1 message lost. */
+    kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14),      /*!< Rx FIFO 0 is busy. */
+    kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15),      /*!< Rx FIFO 1 is busy. */
+    kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16),      /*!< MCAN Module Error and Status. */
+    kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17),        /*!< UnHadled Interrupt asserted. */
+};
+
+/*!
+ * @brief MCAN status flags.
+ *
+ * This provides constants for the MCAN status flags for use in the MCAN functions.
+ * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to
+ * read MCAN_ErrorFlag and distinguish which error is occur using
+ * @ref _mcan_error_flags enumerations.
+ */
+enum _mcan_flags
+{
+    kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK,    /*!< CAN Synchronization Status. */
+    kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */
+    kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */
+    kMCAN_BusOffIntFlag = CAN_IR_BO_MASK,        /*!< Tx Error Warning Status. */
+    kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK,  /*!< Rx Error Warning Status. */
+    kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK,  /*!< Rx Error Warning Status. */
+};
+
+/*!
+ * @brief MCAN Rx FIFO status flags.
+ *
+ * The MCAN Rx FIFO Status enumerations are used to determine the status of the
+ * Rx FIFO.
+ */
+enum _mcan_rx_fifo_flags
+{
+    kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK,       /*!< Rx FIFO 0 new message flag. */
+    kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */
+    kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK,      /*!< Rx FIFO 0 full flag. */
+    kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK,      /*!< Rx FIFO 0 message lost flag. */
+    kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK,       /*!< Rx FIFO 0 new message flag. */
+    kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */
+    kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK,      /*!< Rx FIFO 0 full flag. */
+    kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK,      /*!< Rx FIFO 0 message lost flag. */
+};
+
+/*!
+ * @brief MCAN Tx status flags.
+ *
+ * The MCAN Tx Status enumerations are used to determine the status of the
+ * Tx Buffer/Event FIFO.
+ */
+enum _mcan_tx_flags
+{
+    kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK,      /*!< Transmission completed flag. */
+    kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */
+    kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK,       /*!< Tx Event FIFO element lost. */
+    kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK,       /*!< Tx Event FIFO full. */
+    kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK,  /*!< Tx Event FIFO fill level reached watermark. */
+    kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK,        /*!< Tx Handler wrote Tx Event FIFO element flag. */
+    kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK,       /*!< Tx FIFO empty flag. */
+};
+
+/*!
+ * @brief MCAN interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all of the MCAN Module interrupt configurations.
+ */
+enum _mcan_interrupt_enable
+{
+    kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK,  /*!< Bus Off interrupt. */
+    kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK,   /*!< Error interrupt. */
+    kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */
+};
+
+/*! @brief MCAN frame format. */
+typedef enum _mcan_frame_idformat
+{
+    kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */
+    kMCAN_FrameIDExtend = 0x1U,   /*!< Extend frame format attribute. */
+} mcan_frame_idformat_t;
+
+/*! @brief MCAN frame type. */
+typedef enum _mcan_frame_type
+{
+    kMCAN_FrameTypeData = 0x0U,   /*!< Data frame type attribute. */
+    kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
+} mcan_frame_type_t;
+
+/*! @brief MCAN frame datafield size. */
+typedef enum _mcan_bytes_in_datafield
+{
+    kMCAN_8ByteDatafield = 0x0U,  /*!< 8 byte data field. */
+    kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */
+    kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */
+    kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */
+    kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */
+    kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */
+    kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */
+    kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */
+} mcan_bytes_in_datafield_t;
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/*! @brief MCAN Tx Buffer structure. */
+typedef struct _mcan_tx_buffer_frame
+{
+    struct
+    {
+        uint32_t id : 29; /*!< CAN Frame Identifier. */
+        uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */
+        uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */
+        uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */
+    };
+    struct
+    {
+        uint32_t : 16;
+        uint32_t dlc : 4; /*!< Data Length Code. */
+        uint32_t brs : 1; /*!< Bit Rate Switch. */
+        uint32_t fdf : 1; /*!< CAN FD format. */
+        uint32_t : 1;     /*!< Reserved. */
+        uint32_t efc : 1; /*!< Event FIFO control. */
+        uint32_t mm : 8;  /*!< Message Marker. */
+    };
+    uint8_t *data;
+    uint8_t size;
+} mcan_tx_buffer_frame_t;
+
+/*! @brief MCAN Rx FIFO/Buffer structure. */
+typedef struct _mcan_rx_buffer_frame
+{
+    struct
+    {
+        uint32_t id : 29; /*!< CAN Frame Identifier. */
+        uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */
+        uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */
+        uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */
+    };
+    struct
+    {
+        uint32_t rxts : 16; /*!< Rx Timestamp. */
+        uint32_t dlc : 4;   /*!< Data Length Code. */
+        uint32_t brs : 1;   /*!< Bit Rate Switch. */
+        uint32_t fdf : 1;   /*!< CAN FD format. */
+        uint32_t : 2;       /*!< Reserved. */
+        uint32_t fidx : 7;  /*!< Filter Index. */
+        uint32_t anmf : 1;  /*!< Accepted Non-matching Frame. */
+    };
+    uint8_t *data;
+    uint8_t size;
+} mcan_rx_buffer_frame_t;
+
+/*! @brief MCAN Rx FIFO block number. */
+typedef enum _mcan_fifo_type
+{
+    kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */
+    kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */
+} mcan_fifo_type_t;
+
+/*! @brief MCAN FIFO Operation Mode. */
+typedef enum _mcan_fifo_opmode_config
+{
+    kMCAN_FifoBlocking = 0,  /*!< FIFO blocking mode. */
+    kMCAN_FifoOverwrite = 1, /*!< FIFO overwrite mode. */
+} mcan_fifo_opmode_config_t;
+
+/*! @brief MCAN Tx FIFO/Queue Mode. */
+typedef enum _mcan_txmode_config
+{
+    kMCAN_txFifo = 0,  /*!< Tx FIFO operation. */
+    kMCAN_txQueue = 1, /*!< Tx Queue operation. */
+} mcan_txmode_config_t;
+
+/*! @brief MCAN remote frames treatment. */
+typedef enum _mcan_remote_frame_config
+{
+    kMCAN_filterFrame = 0, /*!< Filter remote frames. */
+    kMCAN_rejectFrame = 1, /*!< Reject all remote frames. */
+} mcan_remote_frame_config_t;
+
+/*! @brief MCAN non-masking frames treatment. */
+typedef enum _mcan_nonmasking_frame_config
+{
+    kMCAN_acceptinFifo0 = 0, /*!< Accept non-masking frames in Rx FIFO 0. */
+    kMCAN_acceptinFifo1 = 1, /*!< Accept non-masking frames in Rx FIFO 1. */
+    kMCAN_reject0 = 2,       /*!< Reject non-masking frames. */
+    kMCAN_reject1 = 3,       /*!< Reject non-masking frames. */
+} mcan_nonmasking_frame_config_t;
+
+/*! @brief MCAN Filter Element Configuration. */
+typedef enum _mcan_fec_config
+{
+    kMCAN_disable = 0,       /*!< Disable filter element. */
+    kMCAN_storeinFifo0 = 1,  /*!< Store in Rx FIFO 0 if filter matches. */
+    kMCAN_storeinFifo1 = 2,  /*!< Store in Rx FIFO 1 if filter matches. */
+    kMCAN_reject = 3,        /*!< Reject ID if filter matches. */
+    kMCAN_setprio = 4,       /*!< Set priority if filter matches. */
+    kMCAN_setpriofifo0 = 5,  /*!< Set priority and store in FIFO 0 if filter matches. */
+    kMCAN_setpriofifo1 = 6,  /*!< Set priority and store in FIFO 1 if filter matches. */
+    kMCAN_storeinbuffer = 7, /*!< Store into Rx Buffer or as debug message. */
+} mcan_fec_config_t;
+
+/*! @brief MCAN Rx FIFO configuration. */
+typedef struct _mcan_rx_fifo_config
+{
+    uint32_t address;                        /*!< FIFOn start address. */
+    uint32_t elementSize;                    /*!< FIFOn element number. */
+    uint32_t watermark;                      /*!< FIFOn watermark level. */
+    mcan_fifo_opmode_config_t opmode;        /*!< FIFOn blocking/overwrite mode. */
+    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
+} mcan_rx_fifo_config_t;
+
+/*! @brief MCAN Rx Buffer configuration. */
+typedef struct _mcan_rx_buffer_config
+{
+    uint32_t address;                        /*!< Rx Buffer start address. */
+    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
+} mcan_rx_buffer_config_t;
+
+/*! @brief MCAN Tx Event FIFO configuration. */
+typedef struct _mcan_tx_fifo_config
+{
+    uint32_t address;     /*!< Event fifo start address. */
+    uint32_t elementSize; /*!< FIFOn element number. */
+    uint32_t watermark;   /*!< FIFOn watermark level. */
+} mcan_tx_fifo_config_t;
+
+/*! @brief MCAN Tx Buffer configuration. */
+typedef struct _mcan_tx_buffer_config
+{
+    uint32_t address;                        /*!< Tx Buffers Start Address. */
+    uint32_t dedicatedSize;                  /*!< Number of Dedicated Transmit Buffers. */
+    uint32_t fqSize;                         /*!< Transmit FIFO/Queue Size. */
+    mcan_txmode_config_t mode;               /*!< Tx FIFO/Queue Mode.*/
+    mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */
+} mcan_tx_buffer_config_t;
+
+/*! @brief MCAN Filter Type. */
+typedef enum _mcan_std_filter_type
+{
+    kMCAN_range = 0,           /*!< Range filter from SFID1 to SFID2. */
+    kMCAN_dual = 1,            /*!< Dual ID filter for SFID1 or SFID2. */
+    kMCAN_classic = 2,         /*!< Classic filter: SFID1 = filter, SFID2 = mask. */
+    kMCAN_disableORrange2 = 3, /*!< Filter element disabled for standard filter
+                                    or Range filter, XIDAM mask not applied for extended filter. */
+} mcan_filter_type_t;
+
+/*! @brief MCAN Standard Message ID Filter Element. */
+typedef struct _mcan_std_filter_element_config
+{
+    uint32_t sfid2 : 11;        /*!< Standard Filter ID 2. */
+    uint32_t : 5;               /*!< Reserved. */
+    uint32_t sfid1 : 11;        /*!< Standard Filter ID 1. */
+    mcan_fec_config_t sfec : 3; /*!< Standard Filter Element Configuration. */
+    mcan_filter_type_t sft : 2; /*!<  Standard Filter Type/ */
+} mcan_std_filter_element_config_t;
+
+/*! @brief MCAN Extended Message ID Filter Element. */
+typedef struct _mcan_ext_filter_element_config
+{
+    uint32_t efid1 : 29;        /*!< Extended Filter ID 1. */
+    mcan_fec_config_t efec : 3; /*!< Extended Filter Element Configuration. */
+    uint32_t efid2 : 29;        /*!< Extended Filter ID 2. */
+    uint32_t : 1;               /*!< Reserved. */
+    mcan_filter_type_t eft : 2; /*!< Extended Filter Type. */
+} mcan_ext_filter_element_config_t;
+
+/*! @brief MCAN Rx filter configuration. */
+typedef struct _mcan_frame_filter_config
+{
+    uint32_t address;                       /*!< Filter start address. */
+    uint32_t listSize;                      /*!< Filter list size. */
+    mcan_frame_idformat_t idFormat;         /*!< Frame format. */
+    mcan_remote_frame_config_t remFrame;    /*!< Remote frame treatment. */
+    mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */
+} mcan_frame_filter_config_t;
+
+/*! @brief MCAN module configuration structure. */
+typedef struct _mcan_config
+{
+    uint32_t baudRateA;     /*!< Baud rate of Arbitration phase in bps. */
+    uint32_t baudRateD;     /*!< Baud rate of Data phase in bps. */
+    bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */
+    bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */
+    bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */
+    bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */
+    bool enableBusMon;      /*!< Enable or Disable Bus Monitoring Mode. */
+} mcan_config_t;
+
+/*! @brief MCAN protocol timing characteristic configuration structure. */
+typedef struct _mcan_timing_config
+{
+    uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */
+    uint8_t rJumpwidth;  /*!< Re-sync Jump Width. */
+    uint8_t seg1;        /*!< Data Time Segment 1. */
+    uint8_t seg2;        /*!< Data Time Segment 2. */
+} mcan_timing_config_t;
+
+/*! @brief MCAN Buffer transfer. */
+typedef struct _mcan_buffer_transfer
+{
+    mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */
+    uint8_t bufferIdx;             /*!< The index of Message buffer used to transfer Message. */
+} mcan_buffer_transfer_t;
+
+/*! @brief MCAN Rx FIFO transfer. */
+typedef struct _mcan_fifo_transfer
+{
+    mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */
+} mcan_fifo_transfer_t;
+
+/*! @brief MCAN handle structure definition. */
+typedef struct _mcan_handle mcan_handle_t;
+
+/*! @brief MCAN transfer callback function.
+ *
+ *  The MCAN transfer callback returns a value from the underlying layer.
+ *  If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of
+ *  MCAN status register which can be used to get the working status(or error status) of MCAN module.
+ *  If the status equals to other MCAN Message Buffer transfer status, the result is the index of
+ *  Message Buffer that generate transfer event.
+ *  If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be
+ *  Ignored.
+ */
+typedef void (*mcan_transfer_callback_t)(
+    CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData);
+
+/*! @brief MCAN handle structure. */
+struct _mcan_handle
+{
+    mcan_transfer_callback_t callback;                   /*!< Callback function. */
+    void *userData;                                      /*!< MCAN callback function parameter.*/
+    mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */
+    mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf;     /*!< The buffer for received data from Rx FIFO. */
+    volatile uint8_t txbufferIdx;                        /*!< Message Buffer transfer state. */
+    volatile uint8_t bufferState[64];                    /*!< Message Buffer transfer state. */
+    volatile uint8_t rxFifoState;                        /*!< Rx FIFO transfer state. */
+};
+
+/******************************************************************************
+ * API
+ *****************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes an MCAN instance.
+ *
+ * This function initializes the MCAN module with user-defined settings.
+ * This example shows how to set up the mcan_config_t parameters and how
+ * to call the MCAN_Init function by passing in these parameters.
+ *  @code
+ *   mcan_config_t config;
+ *   config->baudRateA = 500000U;
+ *   config->baudRateD = 500000U;
+ *   config->enableCanfdNormal = false;
+ *   config->enableCanfdSwitch = false;
+ *   config->enableLoopBackInt = false;
+ *   config->enableLoopBackExt = false;
+ *   config->enableBusMon = false;
+ *   MCAN_Init(CANFD0, &config, 8000000UL);
+ *   @endcode
+ *
+ * @param base MCAN peripheral base address.
+ * @param config Pointer to the user-defined configuration structure.
+ * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz.
+ */
+void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz);
+
+/*!
+ * @brief Deinitializes an MCAN instance.
+ *
+ * This function deinitializes the MCAN module.
+ *
+ * @param base MCAN peripheral base address.
+ */
+void MCAN_Deinit(CAN_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the MCAN configuration structure to default values. The default
+ * values are as follows.
+ *   config->baudRateA = 500000U;
+ *   config->baudRateD = 500000U;
+ *   config->enableCanfdNormal = false;
+ *   config->enableCanfdSwitch = false;
+ *   config->enableLoopBackInt = false;
+ *   config->enableLoopBackExt = false;
+ *   config->enableBusMon = false;
+ *
+ * @param config Pointer to the MCAN configuration structure.
+ */
+void MCAN_GetDefaultConfig(mcan_config_t *config);
+
+/*!
+ * @brief MCAN enters normal mode.
+ *
+ * After initialization, INIT bit in CCCR register must be cleared to enter
+ * normal mode thus synchronizes to the CAN bus and ready for communication.
+ *
+ * @param base MCAN peripheral base address.
+ */
+void MCAN_EnterNormalMode(CAN_Type *base);
+
+/*!
+ * @name Configuration.
+ * @{
+ */
+
+/*!
+ * @brief Sets the MCAN Message RAM base address.
+ *
+ * This function sets the Message RAM base address.
+ *
+ * @param base MCAN peripheral base address.
+ * @param value Desired Message RAM base.
+ */
+static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value)
+{
+    assert((value >= 0x20000000U) && (value <= 0x20027FFFU));
+
+    base->MRBA = CAN_MRBA_BA(value);
+}
+
+/*!
+ * @brief Gets the MCAN Message RAM base address.
+ *
+ * This function gets the Message RAM base address.
+ *
+ * @param base MCAN peripheral base address.
+ * @return Message RAM base address.
+ */
+static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base)
+{
+    return base->MRBA;
+}
+
+/*!
+ * @brief Sets the MCAN protocol arbitration phase timing characteristic.
+ *
+ * This function gives user settings to CAN bus timing characteristic.
+ * The function is for an experienced user. For less experienced users, call
+ * the MCAN_Init() and fill the baud rate field with a desired value.
+ * This provides the default arbitration phase timing characteristics.
+ *
+ * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate
+ * set in MCAN_Init().
+ *
+ * @param base MCAN peripheral base address.
+ * @param config Pointer to the timing configuration structure.
+ */
+void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config);
+
+#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD)
+/*!
+ * @brief Sets the MCAN protocol data phase timing characteristic.
+ *
+ * This function gives user settings to CAN bus timing characteristic.
+ * The function is for an experienced user. For less experienced users, call
+ * the MCAN_Init() and fill the baud rate field with a desired value.
+ * This provides the default data phase timing characteristics.
+ *
+ * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate
+ * set in MCAN_Init().
+ *
+ * @param base MCAN peripheral base address.
+ * @param config Pointer to the timing configuration structure.
+ */
+void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config);
+#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */
+
+/*!
+ * @brief Configures an MCAN receive fifo 0 buffer.
+ *
+ * This function sets start address, element size, watermark, operation mode
+ * and datafield size of the recieve fifo 0.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The receive fifo 0 configuration structure.
+ */
+void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config);
+
+/*!
+ * @brief Configures an MCAN receive fifo 1 buffer.
+ *
+ * This function sets start address, element size, watermark, operation mode
+ * and datafield size of the recieve fifo 1.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The receive fifo 1 configuration structure.
+ */
+void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config);
+
+/*!
+ * @brief Configures an MCAN receive buffer.
+ *
+ * This function sets start address and datafield size of the recieve buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The receive buffer configuration structure.
+ */
+void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config);
+
+/*!
+ * @brief Configures an MCAN transmit event fifo.
+ *
+ * This function sets start address, element size, watermark of the transmit event fifo.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The transmit event fifo configuration structure.
+ */
+void MCAN_SetTxEventfifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config);
+
+/*!
+ * @brief Configures an MCAN transmit buffer.
+ *
+ * This function sets start address, element size, fifo/queue mode and datafield
+ * size of the transmit buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The transmit buffer configuration structure.
+ */
+void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config);
+
+/*!
+ * @brief Set filter configuration.
+ *
+ * This function sets remote and non masking frames in global filter configuration,
+ * also the start address, list size in standard/extended ID filter configuration.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The MCAN filter configuration.
+ */
+void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config);
+
+/*!
+ * @brief Set filter configuration.
+ *
+ * This function sets remote and non masking frames in global filter configuration,
+ * also the start address, list size in standard/extended ID filter configuration.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The MCAN filter configuration.
+ */
+void MCAN_SetSTDFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_std_filter_element_config_t *filter,
+                              uint8_t idx);
+
+/*!
+ * @brief Set filter configuration.
+ *
+ * This function sets remote and non masking frames in global filter configuration,
+ * also the start address, list size in standard/extended ID filter configuration.
+ *
+ * @param base MCAN peripheral base address.
+ * @param config The MCAN filter configuration.
+ */
+void MCAN_SetEXTFilterElement(CAN_Type *base,
+                              const mcan_frame_filter_config_t *config,
+                              const mcan_ext_filter_element_config_t *filter,
+                              uint8_t idx);
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the MCAN module interrupt flags.
+ *
+ * This function gets all MCAN interrupt status flags.
+ *
+ * @param base MCAN peripheral base address.
+ * @param mask The ORed MCAN interrupt mask.
+ * @return MCAN status flags which are ORed.
+ */
+static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask)
+{
+    return (bool)(base->IR & mask);
+}
+
+/*!
+ * @brief Clears the MCAN module interrupt flags.
+ *
+ * This function clears MCAN interrupt status flags.
+ *
+ * @param base MCAN peripheral base address.
+ * @param mask The ORed MCAN interrupt mask.
+ */
+static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask)
+{
+    /* Write 1 to clear status flag. */
+    base->IR |= mask;
+}
+
+/*!
+ * @brief Gets the new data flag of specific Rx Buffer.
+ *
+ * This function gets new data flag of specific Rx Buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Rx Buffer index.
+ * @return Rx Buffer new data status flag.
+ */
+static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 63U);
+
+    if (idx <= 31U)
+    {
+        return (bool)(base->NDAT1 & (1U << idx));
+    }
+    else
+    {
+        return (bool)(base->NDAT2 & (1U << (idx - 31U)));
+    }
+}
+
+/*!
+ * @brief Clears the new data flag of specific Rx Buffer.
+ *
+ * This function clears new data flag of specific Rx Buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Rx Buffer index.
+ */
+static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx)
+{
+    assert(idx <= 63U);
+
+    if (idx <= 31U)
+    {
+        base->NDAT1 &= ~(1U << idx);
+    }
+    else
+    {
+        base->NDAT2 &= ~(1U << (idx - 31U));
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables MCAN interrupts according to the provided interrupt line and mask.
+ *
+ * This function enables the MCAN interrupts according to the provided interrupt line and mask.
+ * The mask is a logical OR of enumeration members.
+ *
+ * @param base MCAN peripheral base address.
+ * @param line Interrupt line number, 0 or 1.
+ * @param mask The interrupts to enable.
+ */
+static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask)
+{
+    base->ILE |= (1U << line);
+    if (0 == line)
+    {
+        base->ILS &= ~mask;
+    }
+    else
+    {
+        base->ILS |= mask;
+    }
+    base->IE |= mask;
+}
+
+/*!
+ * @brief Enables MCAN Tx Buffer interrupts according to the provided index.
+ *
+ * This function enables the MCAN Tx Buffer interrupts.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx)
+{
+    base->TXBTIE |= (uint32_t)(1U << idx);
+}
+
+/*!
+ * @brief Disables MCAN Tx Buffer interrupts according to the provided index.
+ *
+ * This function disables the MCAN Tx Buffer interrupts.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx)
+{
+    base->TXBTIE &= (uint32_t)(~(1U << idx));
+}
+
+/*!
+ * @brief Disables MCAN interrupts according to the provided mask.
+ *
+ * This function disables the MCAN interrupts according to the provided mask.
+ * The mask is a logical OR of enumeration members.
+ *
+ * @param base MCAN peripheral base address.
+ * @param mask The interrupts to disable.
+ */
+static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
+{
+    base->IE &= ~mask;
+}
+
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes an MCAN Message to the Transmit Buffer.
+ *
+ * This function writes a CAN Message to the specified Transmit Message Buffer
+ * and changes the Message Buffer state to start CAN Message transmit. After
+ * that the function returns immediately.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx The MCAN Tx Buffer index.
+ * @param txFrame Pointer to CAN message frame to be sent.
+ */
+status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *txFrame);
+
+/*!
+ * @brief Reads an MCAN Message from Rx FIFO.
+ *
+ * This function reads a CAN message from the Rx FIFO in the Message RAM.
+ *
+ * @param base MCAN peripheral base address.
+ * @param fifoBlock Rx FIFO block 0 or 1.
+ * @param rxFrame Pointer to CAN message frame structure for reception.
+ * @retval kStatus_Success - Read Message from Rx FIFO successfully.
+ */
+status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Tx Buffer add request to send message out.
+ *
+ * This function add sending request to corresponding Tx Buffer.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx)
+{
+    base->TXBAR |= (uint32_t)(1U << idx);
+}
+
+/*!
+ * @brief Tx Buffer cancel sending request.
+ *
+ * This function clears Tx buffer request pending bit.
+ *
+ * @param base MCAN peripheral base address.
+ * @param idx Tx Buffer index.
+ */
+static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx)
+{
+    base->TXBCR |= (uint32_t)(1U << idx);
+}
+
+/*!
+ * @brief Performs a polling send transaction on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created  before calling this API.
+ *
+ * @param base MCAN peripheral base pointer.
+ * @param idx The MCAN buffer index.
+ * @param txFrame Pointer to CAN message frame to be sent.
+ * @retval kStatus_Success - Write Tx Message Buffer Successfully.
+ * @retval kStatus_Fail    - Tx Message Buffer is currently in use.
+ */
+status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *txFrame);
+
+/*!
+ * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus.
+ *
+ * Note that a transfer handle does not need to be created before calling this API.
+ *
+ * @param base MCAN peripheral base pointer.
+ * @param fifoBlock Rx FIFO block, 0 or 1.
+ * @param rxFrame Pointer to CAN message frame structure for reception.
+ * @retval kStatus_Success - Read Message from Rx FIFO successfully.
+ * @retval kStatus_Fail    - No new message in Rx FIFO.
+ */
+status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *rxFrame);
+
+/*!
+ * @brief Initializes the MCAN handle.
+ *
+ * This function initializes the MCAN handle, which can be used for other MCAN
+ * transactional APIs. Usually, for a specified MCAN instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+void MCAN_TransferCreateHandle(CAN_Type *base,
+                               mcan_handle_t *handle,
+                               mcan_transfer_callback_t callback,
+                               void *userData);
+
+/*!
+ * @brief Sends a message using IRQ.
+ *
+ * This function sends a message using IRQ. This is a non-blocking function, which returns
+ * right away. When messages have been sent out, the send callback function is called.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t.
+ * @retval kStatus_Success        Start Tx Buffer sending process successfully.
+ * @retval kStatus_Fail           Write Tx Buffer failed.
+ * @retval kStatus_MCAN_TxBusy Tx Buffer is in use.
+ */
+status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer);
+
+/*!
+ * @brief Receives a message from Rx FIFO using IRQ.
+ *
+ * This function receives a message using IRQ. This is a non-blocking function, which returns
+ * right away. When all messages have been received, the receive callback function is called.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param fifoBlock Rx FIFO block, 0 or 1.
+ * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t.
+ * @retval kStatus_Success            - Start Rx FIFO receiving process successfully.
+ * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use.
+ * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use.
+ */
+status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
+                                             uint8_t fifoBlock,
+                                             mcan_handle_t *handle,
+                                             mcan_fifo_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the interrupt driven message send process.
+ *
+ * This function aborts the interrupt driven message send process.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ * @param bufferIdx The MCAN Buffer index.
+ */
+void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx);
+
+/*!
+ * @brief Aborts the interrupt driven message receive from Rx FIFO process.
+ *
+ * This function aborts the interrupt driven message receive from Rx FIFO process.
+ *
+ * @param base MCAN peripheral base address.
+ * @param fifoBlock MCAN Fifo block, 0 or 1.
+ * @param handle MCAN handle pointer.
+ */
+void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle);
+
+/*!
+ * @brief MCAN IRQ handle function.
+ *
+ * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request.
+ *
+ * @param base MCAN peripheral base address.
+ * @param handle MCAN handle pointer.
+ */
+void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_MCAN_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_mrt.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base Multi-Rate timer peripheral base address
+ *
+ * @return The MRT instance
+ */
+static uint32_t MRT_GetInstance(MRT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to MRT bases for each instance. */
+static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to MRT clocks for each instance. */
+static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to MRT resets for each instance. */
+static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t MRT_GetInstance(MRT_Type *base)
+{
+    uint32_t instance;
+    uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < mrtArrayCount; instance++)
+    {
+        if (s_mrtBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < mrtArrayCount);
+
+    return instance;
+}
+
+void MRT_Init(MRT_Type *base, const mrt_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate the MRT clock */
+    CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
+
+    /* Set timer operating mode */
+    base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
+}
+
+void MRT_Deinit(MRT_Type *base)
+{
+    /* Stop all the timers */
+    MRT_StopTimer(base, kMRT_Channel_0);
+    MRT_StopTimer(base, kMRT_Channel_1);
+    MRT_StopTimer(base, kMRT_Channel_2);
+    MRT_StopTimer(base, kMRT_Channel_3);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the MRT clock*/
+    CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
+{
+    uint32_t newValue = count;
+    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
+    {
+        /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
+        newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
+    }
+
+    /* Update the timer interval value */
+    base->CHANNEL[channel].INTVAL = newValue;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_MRT_H_
+#define _FSL_MRT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup mrt
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of MRT channels */
+typedef enum _mrt_chnl
+{
+    kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/
+    kMRT_Channel_1,      /*!< MRT channel number 1 */
+    kMRT_Channel_2,      /*!< MRT channel number 2 */
+    kMRT_Channel_3       /*!< MRT channel number 3 */
+} mrt_chnl_t;
+
+/*! @brief List of MRT timer modes */
+typedef enum _mrt_timer_mode
+{
+    kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT),      /*!< Repeat Interrupt mode */
+    kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT),     /*!< One-shot Interrupt mode */
+    kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */
+} mrt_timer_mode_t;
+
+/*! @brief List of MRT interrupts */
+typedef enum _mrt_interrupt_enable
+{
+    kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/
+} mrt_interrupt_enable_t;
+
+/*! @brief List of MRT status flags */
+typedef enum _mrt_status_flags
+{
+    kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */
+    kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK,           /*!< Indicates state of the timer */
+} mrt_status_flags_t;
+
+/*!
+ * @brief MRT configuration structure
+ *
+ * This structure holds the configuration settings for the MRT peripheral. To initialize this
+ * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _mrt_config
+{
+    bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */
+} mrt_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the MRT clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the MRT driver.
+ *
+ * @param base   Multi-Rate timer peripheral base address
+ * @param config Pointer to user's MRT config structure
+ */
+void MRT_Init(MRT_Type *base, const mrt_config_t *config);
+
+/*!
+ * @brief Gate the MRT clock
+ *
+ * @param base Multi-Rate timer peripheral base address
+ */
+void MRT_Deinit(MRT_Type *base);
+
+/*!
+ * @brief Fill in the MRT config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ *     config->enableMultiTask = false;
+ * @endcode
+ * @param config Pointer to user's MRT config structure.
+ */
+static inline void MRT_GetDefaultConfig(mrt_config_t *config)
+{
+    assert(config);
+
+    /* Use hardware status operating mode */
+    config->enableMultiTask = false;
+}
+
+/*!
+ * @brief Sets up an MRT channel mode.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Channel that is being configured.
+ * @param mode    Timer mode to use for the channel.
+ */
+static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
+{
+    uint32_t reg = base->CHANNEL[channel].CTRL;
+
+    /* Clear old value */
+    reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
+    /* Add the new mode */
+    reg |= mode;
+
+    base->CHANNEL[channel].CTRL = reg;
+}
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the MRT interrupt.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to enable. This is a logical OR of members of the
+ *                enumeration ::mrt_interrupt_enable_t
+ */
+static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].CTRL |= mask;
+}
+
+/*!
+ * @brief Disables the selected MRT interrupt.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The interrupts to disable. This is a logical OR of members of the
+ *                enumeration ::mrt_interrupt_enable_t
+ */
+static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].CTRL &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled MRT interrupts.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::mrt_interrupt_enable_t
+ */
+static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
+{
+    return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the MRT status flags
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::mrt_status_flags_t
+ */
+static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
+{
+    return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
+}
+
+/*!
+ * @brief Clears the MRT status flags.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ * @param mask    The status flags to clear. This is a logical OR of members of the
+ *                enumeration ::mrt_status_flags_t
+ */
+static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
+{
+    base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Used to update the timer period in units of count.
+ *
+ * The new value will be immediately loaded or will be loaded at the end of the current time
+ * interval. For one-shot interrupt mode the new value will be immediately loaded.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base          Multi-Rate timer peripheral base address
+ * @param channel       Timer channel number
+ * @param count         Timer period in units of ticks
+ * @param immediateLoad true: Load the new value immediately into the TIMER register;
+ *                      false: Load the new value at the end of current timer interval
+ */
+void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad);
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number
+ *
+ * @return Current timer counting value in ticks
+ */
+static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
+{
+    return base->CHANNEL[channel].TIMER;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load period value, counts down to 0 and
+ * depending on the timer mode it will either load the respective start value again or stop.
+ *
+ * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ * @param count   Timer period in units of ticks
+ */
+static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
+{
+    /* Write the timer interval value */
+    base->CHANNEL[channel].INTVAL = count;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stops the timer from counting.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
+{
+    /* Stop the timer immediately */
+    base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @name Get & release channel
+ * @{
+ */
+
+/*!
+ * @brief Find the available channel.
+ *
+ * This function returns the lowest available channel number.
+ *
+ * @param base Multi-Rate timer peripheral base address
+ */
+static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
+{
+    return base->IDLE_CH;
+}
+
+/*!
+ * @brief Release the channel when the timer is using the multi-task mode.
+ *
+ * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for
+ * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as
+ * long as it is needed and release it by calling this function. This removes the need to ask for
+ * an available channel for every use.
+ *
+ * @param base    Multi-Rate timer peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
+{
+    uint32_t reg = base->CHANNEL[channel].STAT;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK;
+    reg |= MRT_CHANNEL_STAT_INUSE_MASK;
+
+    base->CHANNEL[channel].STAT = reg;
+}
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_MRT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_otp.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_OTP_H_
+#define _FSL_OTP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup otp
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief OTP driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version.
+ */
+#define FSL_OTP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Bank bit flags. */
+typedef enum _otp_bank
+{
+    kOTP_Bank0 = 0x1U, /*!< Bank 0. */
+    kOTP_Bank1 = 0x2U, /*!< Bank 1. */
+    kOTP_Bank2 = 0x4U, /*!< Bank 2. */
+    kOTP_Bank3 = 0x8U  /*!< Bank 3. */
+} otp_bank_t;
+
+/*! @brief Bank word bit flags. */
+typedef enum _otp_word
+{
+    kOTP_Word0 = 0x1U, /*!< Word 0. */
+    kOTP_Word1 = 0x2U, /*!< Word 1. */
+    kOTP_Word2 = 0x4U, /*!< Word 2. */
+    kOTP_Word3 = 0x8U  /*!< Word 3. */
+} otp_word_t;
+
+/*! @brief Lock modifications of a read or write access to a bank register. */
+typedef enum _otp_lock
+{
+    kOTP_LockDontLock = 0U, /*!< Do not lock. */
+    kOTP_LockLock = 1U      /*!< Lock till reset. */
+} otp_lock_t;
+
+/*! @brief OTP error codes. */
+enum _otp_status
+{
+    kStatus_OTP_WrEnableInvalid = MAKE_STATUS(kStatusGroup_OTP, 0x1U),           /*!< Write enable invalid. */
+    kStatus_OTP_SomeBitsAlreadyProgrammed = MAKE_STATUS(kStatusGroup_OTP, 0x2U), /*!< Some bits already programmed. */
+    kStatus_OTP_AllDataOrMaskZero = MAKE_STATUS(kStatusGroup_OTP, 0x3U),         /*!< All data or mask zero. */
+    kStatus_OTP_WriteAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0x4U),         /*!< Write access locked. */
+    kStatus_OTP_ReadDataMismatch = MAKE_STATUS(kStatusGroup_OTP, 0x5U),          /*!< Read data mismatch. */
+    kStatus_OTP_UsbIdEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x6U),              /*!< USB ID enabled. */
+    kStatus_OTP_EthMacEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x7U),             /*!< Ethernet MAC enabled. */
+    kStatus_OTP_AesKeysEnabled = MAKE_STATUS(kStatusGroup_OTP, 0x8U),            /*!< AES keys enabled. */
+    kStatus_OTP_IllegalBank = MAKE_STATUS(kStatusGroup_OTP, 0x9U),               /*!< Illegal bank. */
+    kStatus_OTP_ShufflerConfigNotValid = MAKE_STATUS(kStatusGroup_OTP, 0xAU),    /*!< Shuffler config not valid. */
+    kStatus_OTP_ShufflerNotEnabled = MAKE_STATUS(kStatusGroup_OTP, 0xBU),        /*!< Shuffler not enabled. */
+    kStatus_OTP_ShufflerCanOnlyProgSingleKey =
+        MAKE_STATUS(kStatusGroup_OTP, 0xBU),                              /*!< Shuffler can only program single key. */
+    kStatus_OTP_IllegalProgramData = MAKE_STATUS(kStatusGroup_OTP, 0xCU), /*!< Illegal program data. */
+    kStatus_OTP_ReadAccessLocked = MAKE_STATUS(kStatusGroup_OTP, 0xDU),   /*!< Read access locked. */
+};
+
+#define _OTP_ERR_BASE (0x70000U)
+#define _OTP_MAKE_STATUS(errorCode) \
+    ((errorCode == 0U) ? kStatus_Success : MAKE_STATUS(kStatusGroup_OTP, ((errorCode)-_OTP_ERR_BASE)))
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes OTP controller.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_Init(void)
+{
+    uint32_t status = OTP_API->otpInit();
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Unlock one or more OTP banks for write access.
+ *
+ * @param bankMask bit flag that specifies which banks to unlock.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_EnableBankWriteMask(otp_bank_t bankMask)
+{
+    uint32_t status = OTP_API->otpEnableBankWriteMask(bankMask);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Lock one or more OTP banks for write access.
+ *
+ * @param bankMask bit flag that specifies which banks to lock.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_DisableBankWriteMask(otp_bank_t bankMask)
+{
+    uint32_t status = OTP_API->otpDisableBankWriteMask(bankMask);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Locks or unlocks write access to a register of an OTP bank and possibly lock un/locking of it.
+ *
+ * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
+ * @param regEnableMask bit flag that specifies for which words to enable writing.
+ * @param regDisableMask bit flag that specifies for which words to disable writing.
+ * @param lockWrite specifies if access set can be modified or is locked till reset.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_EnableBankWriteLock(uint32_t bankIndex,
+                                               otp_word_t regEnableMask,
+                                               otp_word_t regDisableMask,
+                                               otp_lock_t lockWrite)
+{
+    uint32_t status = OTP_API->otpEnableBankWriteLock(bankIndex, regEnableMask, regDisableMask, lockWrite);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Locks or unlocks read access to a register of an OTP bank and possibly lock un/locking of it.
+ *
+ * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
+ * @param regEnableMask bit flag that specifies for which words to enable reading.
+ * @param regDisableMask bit flag that specifies for which words to disable reading.
+ * @param lockWrite specifies if access set can be modified or is locked till reset.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_EnableBankReadLock(uint32_t bankIndex,
+                                              otp_word_t regEnableMask,
+                                              otp_word_t regDisableMask,
+                                              otp_lock_t lockWrite)
+{
+    uint32_t status = OTP_API->otpEnableBankReadLock(bankIndex, regEnableMask, regDisableMask, lockWrite);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Program a single register in an OTP bank.
+ *
+ * @param bankIndex OTP bank index, 0 = bank 0, 1 = bank 1 etc.
+ * @param regIndex OTP register index.
+ * @param value value to write.
+ *
+ * @return kStatus_Success upon successful execution, error status otherwise.
+ */
+static inline status_t OTP_ProgramRegister(uint32_t bankIndex, uint32_t regIndex, uint32_t value)
+{
+    uint32_t status = OTP_API->otpProgramReg(bankIndex, regIndex, value);
+    return _OTP_MAKE_STATUS(status);
+}
+
+/*!
+ * @brief Returns the version of the OTP driver in ROM.
+ *
+ * @return version.
+ */
+static inline uint32_t OTP_GetDriverVersion(void)
+{
+    return OTP_API->otpGetDriverVersion();
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_OTP_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_pint.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Irq number array */
+static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
+
+/*! @brief Callback function array for PINT(s). */
+static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void PINT_Init(PINT_Type *base)
+{
+    uint32_t i;
+    uint32_t pmcfg;
+
+    assert(base);
+
+    pmcfg = 0;
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        s_pintCallback[i] = NULL;
+    }
+
+    /* Disable all bit slices */
+    for (i = 0; i < PINT_PIN_INT_COUNT; i++)
+    {
+        pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
+    }
+
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(kCLOCK_Pint);
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
+
+    /* Disable all pattern match bit slices */
+    base->PMCFG = pmcfg;
+}
+
+void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
+{
+    assert(base);
+
+    /* Clear Rise and Fall flags first */
+    PINT_PinInterruptClrRiseFlag(base, intr);
+    PINT_PinInterruptClrFallFlag(base, intr);
+
+    /* select level or edge sensitive */
+    base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U);
+
+    /* enable rising or level interrupt */
+    if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
+    {
+        base->SIENR = 1U << intr;
+    }
+    else
+    {
+        base->CIENR = 1U << intr;
+    }
+
+    /* Enable falling or select high level */
+    if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+    {
+        base->SIENF = 1U << intr;
+    }
+    else
+    {
+        base->CIENF = 1U << intr;
+    }
+
+    s_pintCallback[intr] = callback;
+}
+
+void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
+{
+    uint32_t mask;
+    bool level;
+
+    assert(base);
+
+    *enable = kPINT_PinIntEnableNone;
+    level = false;
+
+    mask = 1U << pintr;
+    if (base->ISEL & mask)
+    {
+        /* Pin interrupt is level sensitive */
+        level = true;
+    }
+
+    if (base->IENR & mask)
+    {
+        if (level)
+        {
+            /* Level interrupt is enabled */
+            *enable = kPINT_PinIntEnableLowLevel;
+        }
+        else
+        {
+            /* Rising edge interrupt */
+            *enable = kPINT_PinIntEnableRiseEdge;
+        }
+    }
+
+    if (base->IENF & mask)
+    {
+        if (level)
+        {
+            /* Level interrupt is active high */
+            *enable = kPINT_PinIntEnableHighLevel;
+        }
+        else
+        {
+            /* Either falling or both edge */
+            if (*enable == kPINT_PinIntEnableRiseEdge)
+            {
+                /* Rising and faling edge */
+                *enable = kPINT_PinIntEnableBothEdges;
+            }
+            else
+            {
+                /* Falling edge */
+                *enable = kPINT_PinIntEnableFallEdge;
+            }
+        }
+    }
+
+    *callback = s_pintCallback[pintr];
+}
+
+void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
+{
+    uint32_t src_shift;
+    uint32_t cfg_shift;
+    uint32_t pmcfg;
+
+    assert(base);
+
+    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
+    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
+
+    /* Input source selection for selected bit slice */
+    base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift);
+
+    /* Bit slice configuration */
+    pmcfg = base->PMCFG;
+    pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
+
+    /* If end point is true, enable the bits */
+    if (bslice != 7U)
+    {
+        if (cfg->end_point)
+        {
+            pmcfg |= (0x1U << bslice);
+        }
+        else
+        {
+            pmcfg &= ~(0x1U << bslice);
+        }
+    }
+
+    base->PMCFG = pmcfg;
+
+    /* Save callback pointer */
+    s_pintCallback[bslice] = cfg->callback;
+}
+
+void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
+{
+    uint32_t src_shift;
+    uint32_t cfg_shift;
+
+    assert(base);
+
+    src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
+    cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
+
+    cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift);
+    cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift);
+
+    if (bslice == 7U)
+    {
+        cfg->end_point = true;
+    }
+    else
+    {
+        cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice;
+    }
+    cfg->callback = s_pintCallback[bslice];
+}
+
+uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
+{
+    uint32_t pmctrl;
+    uint32_t pmstatus;
+    uint32_t pmsrc;
+
+    pmctrl = PINT->PMCTRL;
+    pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
+    if (pmstatus)
+    {
+        /* Reset Pattern match engine detection logic */
+        pmsrc = base->PMSRC;
+        base->PMSRC = pmsrc;
+    }
+    return (pmstatus);
+}
+
+void PINT_EnableCallback(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    PINT_PinInterruptClrStatusAll(base);
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
+        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
+        EnableIRQ(s_pintIRQ[i]);
+    }
+}
+
+void PINT_DisableCallback(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        DisableIRQ(s_pintIRQ[i]);
+        PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
+        NVIC_ClearPendingIRQ(s_pintIRQ[i]);
+    }
+}
+
+void PINT_Deinit(PINT_Type *base)
+{
+    uint32_t i;
+
+    assert(base);
+
+    /* Cleanup */
+    PINT_DisableCallback(base);
+    for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
+    {
+        s_pintCallback[i] = NULL;
+    }
+
+    /* Reset the peripheral */
+    RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
+
+    /* Disable the peripheral clock */
+    CLOCK_DisableClock(kCLOCK_Pint);
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+void PIN_INT0_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt0] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
+    }
+}
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+void PIN_INT1_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt1] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+void PIN_INT2_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt2] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+void PIN_INT3_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt3] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+void PIN_INT4_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt4] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+void PIN_INT5_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt5] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+void PIN_INT6_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt6] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
+    }
+}
+#endif
+
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+void PIN_INT7_DriverIRQHandler(void)
+{
+    uint32_t pmstatus;
+
+    /* Reset pattern match detection */
+    pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
+    /* Call user function */
+    if (s_pintCallback[kPINT_PinInt7] != NULL)
+    {
+        s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_PINT_H_
+#define _FSL_PINT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup pint_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/* Number of interrupt line supported by PINT */
+#define PINT_PIN_INT_COUNT 8U
+
+/* Number of input sources supported by PINT */
+#define PINT_INPUT_COUNT 8U
+
+/* PININT Bit slice source register bits */
+#define PININT_BITSLICE_SRC_START 8U
+#define PININT_BITSLICE_SRC_MASK 7U
+
+/* PININT Bit slice configuration register bits */
+#define PININT_BITSLICE_CFG_START 8U
+#define PININT_BITSLICE_CFG_MASK 7U
+#define PININT_BITSLICE_ENDP_MASK 7U
+
+#define PINT_PIN_INT_LEVEL 0x10U
+#define PINT_PIN_INT_EDGE 0x00U
+#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U
+#define PINT_PIN_INT_RISE 0x01U
+#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE)
+#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL)
+#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
+
+/*! @brief PINT Pin Interrupt enable type */
+typedef enum _pint_pin_enable
+{
+    kPINT_PinIntEnableNone = 0U,                      /*!< Do not generate Pin Interrupt */
+    kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE,  /*!< Generate Pin Interrupt on rising edge */
+    kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE,  /*!< Generate Pin Interrupt on falling edge */
+    kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */
+    kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL,  /*!< Generate Pin Interrupt on low level */
+    kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */
+} pint_pin_enable_t;
+
+/*! @brief PINT Pin Interrupt type */
+typedef enum _pint_int
+{
+    kPINT_PinInt0 = 0U, /*!< Pin Interrupt  0 */
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+    kPINT_PinInt1 = 1U, /*!< Pin Interrupt  1 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+    kPINT_PinInt2 = 2U, /*!< Pin Interrupt  2 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+    kPINT_PinInt3 = 3U, /*!< Pin Interrupt  3 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+    kPINT_PinInt4 = 4U, /*!< Pin Interrupt  4 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+    kPINT_PinInt5 = 5U, /*!< Pin Interrupt  5 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+    kPINT_PinInt6 = 6U, /*!< Pin Interrupt  6 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+    kPINT_PinInt7 = 7U, /*!< Pin Interrupt  7 */
+#endif
+} pint_pin_int_t;
+
+/*! @brief PINT Pattern Match bit slice input source type */
+typedef enum _pint_pmatch_input_src
+{
+    kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */
+    kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */
+    kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */
+    kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */
+    kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */
+    kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */
+    kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */
+    kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */
+} pint_pmatch_input_src_t;
+
+/*! @brief PINT Pattern Match bit slice type */
+typedef enum _pint_pmatch_bslice
+{
+    kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
+    kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
+    kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
+    kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
+    kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
+    kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
+    kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */
+#endif
+#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
+    kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */
+#endif
+} pint_pmatch_bslice_t;
+
+/*! @brief PINT Pattern Match configuration type */
+typedef enum _pint_pmatch_bslice_cfg
+{
+    kPINT_PatternMatchAlways = 0U,          /*!< Always Contributes to product term match */
+    kPINT_PatternMatchStickyRise = 1U,      /*!< Sticky Rising edge */
+    kPINT_PatternMatchStickyFall = 2U,      /*!< Sticky Falling edge */
+    kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */
+    kPINT_PatternMatchHigh = 4U,            /*!< High level */
+    kPINT_PatternMatchLow = 5U,             /*!< Low level */
+    kPINT_PatternMatchNever = 6U,           /*!< Never contributes to product term match */
+    kPINT_PatternMatchBothEdges = 7U,       /*!< Either rising or falling edge */
+} pint_pmatch_bslice_cfg_t;
+
+/*! @brief PINT Callback function. */
+typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status);
+
+typedef struct _pint_pmatch_cfg
+{
+    pint_pmatch_input_src_t bs_src;
+    pint_pmatch_bslice_cfg_t bs_cfg;
+    bool end_point;
+    pint_cb_t callback;
+} pint_pmatch_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief	Initialize PINT peripheral.
+
+ * This function initializes the PINT peripheral and enables the clock.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_Init(PINT_Type *base);
+
+/*!
+ * @brief	Configure PINT peripheral pin interrupt.
+
+ * This function configures a given pin interrupt.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param intr Pin interrupt.
+ * @param enable Selects detection logic.
+ * @param callback Callback.
+ *
+ * @retval None.
+ */
+void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback);
+
+/*!
+ * @brief	Get PINT peripheral pin interrupt configuration.
+
+ * This function returns the configuration of a given pin interrupt.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ * @param enable Pointer to store the detection logic.
+ * @param callback Callback.
+ *
+ * @retval None.
+ */
+void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback);
+
+/*!
+ * @brief	Clear Selected pin interrupt status.
+
+ * This function clears the selected pin interrupt status.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->IST = (1U << pintr);
+}
+
+/*!
+ * @brief	Get Selected pin interrupt status.
+
+ * This function returns the selected pin interrupt status.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval status = 0 No pin interrupt request.  = 1 Selected Pin interrupt request active.
+ */
+static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->IST & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupts status.
+
+ * This function clears the status of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base)
+{
+    base->IST = PINT_IST_PSTAT_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupts status.
+
+ * This function returns the status of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval status Each bit position indicates the status of corresponding pin interrupt.
+ * = 0 No pin interrupt request. = 1 Pin interrupt request active.
+ */
+static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base)
+{
+    return (base->IST);
+}
+
+/*!
+ * @brief	Clear Selected pin interrupt fall flag.
+
+ * This function clears the selected pin interrupt fall flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->FALL = (1U << pintr);
+}
+
+/*!
+ * @brief	Get selected pin interrupt fall flag.
+
+ * This function returns the selected pin interrupt fall flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval flag = 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->FALL & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupt fall flags.
+
+ * This function clears the fall flag for all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base)
+{
+    base->FALL = PINT_FALL_FDET_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupt fall flags.
+
+ * This function returns the fall flag of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt.
+ * 0 Falling edge has not been detected.  = 1 Falling edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base)
+{
+    return (base->FALL);
+}
+
+/*!
+ * @brief	Clear Selected pin interrupt rise flag.
+
+ * This function clears the selected pin interrupt rise flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    base->RISE = (1U << pintr);
+}
+
+/*!
+ * @brief	Get selected pin interrupt rise flag.
+
+ * This function returns the selected pin interrupt rise flag.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param pintr Pin interrupt.
+ *
+ * @retval flag = 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
+{
+    return ((base->RISE & (1U << pintr)) ? 1U : 0U);
+}
+
+/*!
+ * @brief	Clear all pin interrupt rise flags.
+
+ * This function clears the rise flag for all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base)
+{
+    base->RISE = PINT_RISE_RDET_MASK;
+}
+
+/*!
+ * @brief	Get all pin interrupt rise flags.
+
+ * This function returns the rise flag of all pin interrupts.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt.
+ * 0 Rising edge has not been detected.  = 1 Rising edge has been detected.
+ */
+static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base)
+{
+    return (base->RISE);
+}
+
+/*!
+ * @brief	Configure PINT pattern match.
+
+ * This function configures a given pattern match bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ * @param cfg Pointer to bit slice configuration.
+ *
+ * @retval None.
+ */
+void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
+
+/*!
+ * @brief	Get PINT pattern match configuration.
+
+ * This function returns the configuration of a given pattern match bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ * @param cfg Pointer to bit slice configuration.
+ *
+ * @retval None.
+ */
+void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
+
+/*!
+ * @brief	Get pattern match bit slice status.
+
+ * This function returns the status of selected bit slice.
+ *
+ * @param base Base address of the PINT peripheral.
+ * @param bslice Pattern match bit slice number.
+ *
+ * @retval status = 0 Match has not been detected.  = 1 Match has been detected.
+ */
+static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice)
+{
+    return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice;
+}
+
+/*!
+ * @brief	Get status of all pattern match bit slices.
+
+ * This function returns the status of all bit slices.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval status Each bit position indicates the match status of corresponding bit slice.
+ * = 0 Match has not been detected.  = 1 Match has been detected.
+ */
+static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base)
+{
+    return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT;
+}
+
+/*!
+ * @brief	Reset pattern match detection logic.
+
+ * This function resets the pattern match detection logic if any of the product term is matching.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval pmstatus Each bit position indicates the match status of corresponding bit slice.
+ * = 0 Match was detected.  = 1 Match was not detected.
+ */
+uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base);
+
+/*!
+ * @brief	Enable pattern match function.
+
+ * This function enables the pattern match function.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchEnable(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK;
+}
+
+/*!
+ * @brief	Disable pattern match function.
+
+ * This function disables the pattern match function.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchDisable(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK;
+}
+
+/*!
+ * @brief	Enable RXEV output.
+
+ * This function enables the pattern match RXEV output.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK;
+}
+
+/*!
+ * @brief	Disable RXEV output.
+
+ * This function disables the pattern match RXEV output.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval	None.
+ */
+static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base)
+{
+    base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK;
+}
+
+/*!
+ * @brief	Enable callback.
+
+ * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
+ * as soon as they are enabled, the callback function is not enabled until this function is called.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_EnableCallback(PINT_Type *base);
+
+/*!
+ * @brief	Disable callback.
+
+ * This function disables the interrupt for the selected PINT peripheral. Although the pins are still
+ * being monitored but the callback function is not called.
+ *
+ * @param base Base address of the peripheral.
+ *
+ * @retval None.
+ */
+void PINT_DisableCallback(PINT_Type *base);
+
+/*!
+ * @brief	Deinitialize PINT peripheral.
+
+ * This function disables the PINT clock.
+ *
+ * @param base Base address of the PINT peripheral.
+ *
+ * @retval None.
+ */
+void PINT_Deinit(PINT_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_PINT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Empty file since implementation is in header file and power library */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot)
+#define PDRCFG0 0x0U
+#define PDRCFG1 0x1U
+
+typedef enum pd_bits
+{
+    kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
+    kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
+    kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
+    kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
+    kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
+    kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
+    kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
+    kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
+    kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
+    kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
+    kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
+    kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
+    kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
+    kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
+    kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
+    kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
+    kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
+    kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
+    kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
+    kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
+    kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
+    kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
+    kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
+    kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
+
+    kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
+    kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
+    kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
+    kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
+    kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
+    kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
+
+    kPDRUNCFG_ForceUnsigned = 0x80000000U,
+} pd_bit_t;
+
+/* Power mode configuration API parameter */
+typedef enum _power_mode_config
+{
+    kPmu_Sleep = 0U,
+    kPmu_Deep_Sleep = 1U,
+    kPmu_Deep_PowerDown = 2U,
+} power_mode_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @name Power Configuration
+* @{
+*/
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
+ *
+ * @param en    peripheral for which to enable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_EnablePD(pd_bit_t en)
+{
+    /* PDRUNCFGSET */
+    SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU));
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
+ *
+ * @param en    peripheral for which to disable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_DisablePD(pd_bit_t en)
+{
+    /* PDRUNCFGCLR */
+    SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU));
+}
+
+/*!
+ * @brief API to enable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_EnableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to disable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_DisableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to power down flash controller.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_PowerDownFlash(void)
+{
+    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
+    CLOCK_DisableClock(kCLOCK_Flash);
+
+    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
+    CLOCK_DisableClock(kCLOCK_Fmc);
+}
+
+/*!
+ * @brief API to power up flash controller.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_PowerUpFlash(void)
+{
+    /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
+    CLOCK_EnableClock(kCLOCK_Fmc);
+}
+
+/*!
+ * @brief Power Library API to power the PLLs.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetPLL(void);
+
+/*!
+ * @brief Power Library API to power the USB PHY.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetUsbPhy(void);
+
+/*!
+ * @brief Power Library API to enter different power mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during power mode selected.
+ * @return none
+ */
+void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter sleep mode.
+ *
+ * @return none
+ */
+void POWER_EnterSleep(void);
+
+/*!
+ * @brief Power Library API to enter deep sleep mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be powered on during deep sleep
+ * @return none
+ */
+void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter deep power down mode.
+ *
+ * @param exclude_from_pd   Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during deep power 
+ *                          down mode, but this is has no effect as the voltages are cut off.
+ 
+ * @return none
+ */
+void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq  - The desired frequency at which the part would like to operate, 
+ *                note that the voltage and flash wait states should be set before changing frequency
+ * @return none
+ */
+void POWER_SetVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq  - The desired frequency at which the part would like to operate, 
+ *                note that the voltage and flash wait states should be set before changing frequency
+ * @return none
+ */
+void POWER_SetVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @param none
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FSL_POWER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* set bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* set bit */
+        SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1u << bitPos;
+
+    assert(bitPos < 32u);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* clear bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* clear bit */
+        SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+    kFLASH_RST_SHIFT_RSTn = 0 | 7U,          /**< Flash controller reset control */
+    kFMC_RST_SHIFT_RSTn = 0 | 8U,            /**< Flash accelerator reset control */
+    kEEPROM_RST_SHIFT_RSTn = 0 | 9U,         /**< EEPROM reset control */
+    kSPIFI_RST_SHIFT_RSTn = 0 | 10U,         /**< SPIFI reset control */
+    kMUX_RST_SHIFT_RSTn = 0 | 11U,           /**< Input mux reset control */
+    kIOCON_RST_SHIFT_RSTn = 0 | 13U,         /**< IOCON reset control */
+    kGPIO0_RST_SHIFT_RSTn = 0 | 14U,         /**< GPIO0 reset control */
+    kGPIO1_RST_SHIFT_RSTn = 0 | 15U,         /**< GPIO1 reset control */
+    kGPIO2_RST_SHIFT_RSTn = 0 | 16U,         /**< GPIO2 reset control */
+    kGPIO3_RST_SHIFT_RSTn = 0 | 17U,         /**< GPIO3 reset control */
+    kPINT_RST_SHIFT_RSTn = 0 | 18U,          /**< Pin interrupt (PINT) reset control */
+    kGINT_RST_SHIFT_RSTn = 0 | 19U,          /**< Grouped interrupt (PINT) reset control. */
+    kDMA_RST_SHIFT_RSTn = 0 | 20U,           /**< DMA reset control */
+    kCRC_RST_SHIFT_RSTn = 0 | 21U,           /**< CRC reset control */
+    kWWDT_RST_SHIFT_RSTn = 0 | 22U,          /**< Watchdog timer reset control */
+    kADC0_RST_SHIFT_RSTn = 0 | 27U,          /**< ADC0 reset control */
+    
+    kMRT_RST_SHIFT_RSTn = 65536 | 0U,        /**< Multi-rate timer (MRT) reset control */
+    kSCT0_RST_SHIFT_RSTn = 65536 | 2U,       /**< SCTimer/PWM 0 (SCT0) reset control */
+    kMCAN0_RST_SHIFT_RSTn = 65536 | 7U,      /**< MCAN0 reset control */
+    kMCAN1_RST_SHIFT_RSTn = 65536 | 8U,      /**< MCAN1 reset control */
+    kUTICK_RST_SHIFT_RSTn = 65536 | 10U,     /**< Micro-tick timer reset control */
+    kFC0_RST_SHIFT_RSTn = 65536 | 11U,       /**< Flexcomm Interface 0 reset control */
+    kFC1_RST_SHIFT_RSTn = 65536 | 12U,       /**< Flexcomm Interface 1 reset control */
+    kFC2_RST_SHIFT_RSTn = 65536 | 13U,       /**< Flexcomm Interface 2 reset control */
+    kFC3_RST_SHIFT_RSTn = 65536 | 14U,       /**< Flexcomm Interface 3 reset control */
+    kFC4_RST_SHIFT_RSTn = 65536 | 15U,       /**< Flexcomm Interface 4 reset control */
+    kFC5_RST_SHIFT_RSTn = 65536 | 16U,       /**< Flexcomm Interface 5 reset control */
+    kFC6_RST_SHIFT_RSTn = 65536 | 17U,       /**< Flexcomm Interface 6 reset control */
+    kFC7_RST_SHIFT_RSTn = 65536 | 18U,       /**< Flexcomm Interface 7 reset control */
+    kDMIC_RST_SHIFT_RSTn = 65536 | 19U,      /**< Digital microphone interface reset control */
+    kCT32B2_RST_SHIFT_RSTn = 65536 | 22U,    /**< CT32B2 reset control */
+    kUSB0D_RST_SHIFT_RSTn = 65536 | 25U,     /**< USB0D reset control */
+    kCT32B0_RST_SHIFT_RSTn = 65536 | 26U,    /**< CT32B0 reset control */
+    kCT32B1_RST_SHIFT_RSTn = 65536 | 27U,    /**< CT32B1 reset control */
+    
+    kLCD_RST_SHIFT_RSTn = 131072 | 2U,       /**< LCD reset control */
+    kSDIO_RST_SHIFT_RSTn = 131072 | 3U,      /**< SDIO reset control */
+    kUSB1H_RST_SHIFT_RSTn = 131072 | 4U,     /**< USB1H reset control */
+    kUSB1D_RST_SHIFT_RSTn = 131072 | 5U,     /**< USB1D reset control */    
+    kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U,   /**< USB1RAM reset control */
+    kEMC_RST_SHIFT_RSTn = 131072 | 7U,       /**< EMC reset control */
+    kETH_RST_SHIFT_RSTn = 131072 | 8U,       /**< ETH reset control */
+    kGPIO4_RST_SHIFT_RSTn = 131072 | 9U,     /**< GPIO4 reset control */ 
+    kGPIO5_RST_SHIFT_RSTn = 131072 | 10U,    /**< GPIO5 reset control */
+    kAES_RST_SHIFT_RSTn = 131072 | 11U,      /**< AES reset control */
+    kOTP_RST_SHIFT_RSTn = 131072 | 12U,      /**< OTP reset control */
+    kRNG_RST_SHIFT_RSTn = 131072 | 13U,      /**< RNG  reset control */ 
+    kFC8_RST_SHIFT_RSTn = 131072 | 14U,      /**< Flexcomm Interface 8 reset control */
+    kFC9_RST_SHIFT_RSTn = 131072 | 15U,      /**< Flexcomm Interface 9 reset control */
+    kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U,  /**< USB0HMR reset control */
+    kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U,  /**< USB0HSL reset control */
+    kSHA_RST_SHIFT_RSTn = 131072 | 18U,      /**< SHA reset control */
+    kSC0_RST_SHIFT_RSTn = 131072 | 19U,      /**< SC0 reset control */
+    kSC1_RST_SHIFT_RSTn = 131072 | 20U,      /**< SC1 reset control */
+    
+    kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
+    kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS             \
+    {                        \
+        kADC0_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define AES_RSTS             \
+    {                        \
+        kAES_RST_SHIFT_RSTn  \
+    } /* Reset bits for AES peripheral */
+#define CRC_RSTS            \
+    {                       \
+        kCRC_RST_SHIFT_RSTn \
+    } /* Reset bits for CRC peripheral */
+#define CTIMER_RSTS                                                                                     \
+    {                                                                                                   \
+        kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+            kCT32B4_RST_SHIFT_RSTn                                                                      \
+    } /* Reset bits for CTIMER peripheral */
+#define DMA_RSTS            \
+    {                       \
+        kDMA_RST_SHIFT_RSTn \
+    } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS            \
+    {                        \
+        kDMIC_RST_SHIFT_RSTn \
+    } /* Reset bits for DMIC peripheral */
+#define EMC_RSTS             \
+    {                        \
+        kEMC_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define ETH_RST              \
+    {                        \
+        kETH_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define FLEXCOMM_RSTS                                                                                            \
+    {                                                                                                            \
+        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn                                       \
+    } /* Reset bits for FLEXCOMM peripheral */
+#define GINT_RSTS                                  \
+    {                                              \
+        kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
+    } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
+#define GPIO_RSTS                                    \
+    {                                                \
+        kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn,  \
+        kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn                                                 \
+    } /* Reset bits for GPIO peripheral */
+#define INPUTMUX_RSTS       \
+    {                       \
+        kMUX_RST_SHIFT_RSTn \
+    } /* Reset bits for INPUTMUX peripheral */
+#define IOCON_RSTS            \
+    {                         \
+        kIOCON_RST_SHIFT_RSTn \
+    } /* Reset bits for IOCON peripheral */
+#define FLASH_RSTS                                 \
+    {                                              \
+        kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
+    } /* Reset bits for Flash peripheral */
+#define LCD_RSTS                                 \
+    {                                            \
+        kLCD_RST_SHIFT_RSTn                      \
+    } /* Reset bits for LCD peripheral */
+#define MRT_RSTS            \
+    {                       \
+        kMRT_RST_SHIFT_RSTn \
+    } /* Reset bits for MRT peripheral */
+#define MCAN_RSTS                                   \
+    {                                               \
+        kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
+    } /* Reset bits for MCAN0&MACN1 peripheral */
+#define OTP_RSTS            \
+    {                       \
+        kOTP_RST_SHIFT_RSTn \
+    } /* Reset bits for OTP peripheral */
+#define PINT_RSTS            \
+    {                        \
+        kPINT_RST_SHIFT_RSTn \
+    } /* Reset bits for PINT peripheral */
+#define RNG_RSTS             \
+    {                        \
+        kRNG_RST_SHIFT_RSTn  \
+    } /* Reset bits for RNG peripheral */
+#define SDIO_RST             \
+    {                        \
+        kSDIO_RST_SHIFT_RSTn \
+    } /* Reset bits for SDIO peripheral */
+#define SCT_RSTS             \
+    {                        \
+        kSCT0_RST_SHIFT_RSTn \
+    } /* Reset bits for SCT peripheral */
+#define SHA_RST              \
+    {                        \
+        kSHA_RST_SHIFT_RSTn  \
+    } /* Reset bits for SHA peripheral */
+#define USB0D_RST             \
+    {                         \
+        kUSB0D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0D peripheral */
+#define USB0HMR_RST             \
+    {                           \
+        kUSB0HMR_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HMR peripheral */
+#define USB0HSL_RST             \
+    {                           \
+        kUSB0HSL_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HSL peripheral */
+#define USB1H_RST             \
+    {                         \
+        kUSB1H_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1H peripheral */
+#define USB1D_RST             \
+    {                         \
+        kUSB1D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1D peripheral */
+#define USB1RAM_RST             \
+    {                           \
+        kUSB1RAM_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1RAM peripheral */
+#define UTICK_RSTS            \
+    {                         \
+        kUTICK_RST_SHIFT_RSTn \
+    } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for WWDT peripheral */
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rit.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address to be used to gate or ungate the module clock
+ *
+ * @param base RIT peripheral base address
+ *
+ * @return The RIT instance
+ */
+static uint32_t RIT_GetInstance(RIT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to RIT bases for each instance. */
+static RIT_Type *const s_ritBases[] = RIT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to PIT clocks for each instance. */
+static const clock_ip_name_t s_ritClocks[] = RIT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t RIT_GetInstance(RIT_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_ritBases); instance++)
+    {
+        if (s_ritBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_ritBases));
+
+    return instance;
+}
+
+void RIT_GetDefaultConfig(rit_config_t *config)
+{
+    assert(config);
+    /* Timer operation are no effect in Debug mode */
+    config->enableRunInDebug = false;
+}
+
+void RIT_Init(RIT_Type *base, const rit_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate the RIT clock*/
+    CLOCK_EnableClock(s_ritClocks[RIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Enable RIT timers */
+    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
+
+    /* Config timer operation is no effect in debug mode */
+    if (!config->enableRunInDebug)
+    {
+        base->CTRL &= ~RIT_CTRL_RITENBR_MASK;
+    }
+    else
+    {
+        base->CTRL |= RIT_CTRL_RITENBR_MASK;
+    }
+}
+
+void RIT_Deinit(RIT_Type *base)
+{
+    /* Disable RIT timers */
+    base->CTRL |= ~RIT_CTRL_RITEN_MASK;
+#ifdef FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+    /* Gate the RIT clock*/
+    CLOCK_DisableClock(s_ritClocks[RIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void RIT_SetTimerCompare(RIT_Type *base, uint64_t count)
+{
+    /* Disable RIT timers */
+    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
+    base->COMPVAL = (uint32_t)count;
+    base->COMPVAL_H = (uint16_t)(count >> 32U);
+}
+
+void RIT_SetMaskBit(RIT_Type *base, uint64_t count)
+{
+    base->MASK = (uint32_t)count;
+    base->MASK_H = (uint16_t)(count >> 32U);
+}
+
+uint64_t RIT_GetCompareTimerCount(RIT_Type *base)
+{
+    uint16_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* COMPVAL_H should be read before COMPVAL */
+    valueH = base->COMPVAL_H;
+    valueL = base->COMPVAL;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+
+uint64_t RIT_GetCounterTimerCount(RIT_Type *base)
+{
+    uint16_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* COUNTER_H should be read before COUNTER */
+    valueH = base->COUNTER_H;
+    valueL = base->COUNTER;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}
+
+uint64_t RIT_GetMaskTimerCount(RIT_Type *base)
+{
+    uint16_t valueH = 0U;
+    uint32_t valueL = 0U;
+
+    /* MASK_H should be read before MASK */
+    valueH = base->MASK_H;
+    valueL = base->MASK;
+
+    return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RIT_H_
+#define _FSL_RIT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rit
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RIT status flags */
+typedef enum _rit_status_flags
+{
+    kRIT_TimerFlag = RIT_CTRL_RITINT_MASK, /*!< Timer flag */
+} rit_status_flags_t;
+
+/*!
+ * @brief RIT config structure
+ *
+ * This structure holds the configuration settings for the RIT peripheral. To initialize this
+ * structure to reasonable defaults, call the RIT_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _rit_config
+{
+    bool enableRunInDebug; /*!< true: The timer is halted when the processor is halted for debugging.; false: Debug has
+                              no effect on the timer operation. */
+} rit_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RIT clock, enables the RIT module, and configures the peripheral for basic operations.
+ *
+ * @note This API should be called at the beginning of the application using the RIT driver.
+ *
+ * @param base   RIT peripheral base address
+ * @param config Pointer to the user's RIT config structure
+ */
+void RIT_Init(RIT_Type *base, const rit_config_t *config);
+
+/*!
+ * @brief Gates the RIT clock and disables the RIT module.
+ *
+ * @param base RIT peripheral base address
+ */
+void RIT_Deinit(RIT_Type *base);
+
+/*!
+ * @brief Fills in the RIT configuration structure with the default settings.
+ *
+ * The default values are as follows.
+ * @code
+ *     config->enableRunInDebug = false;
+ * @endcode
+ * @param config Pointer to the onfiguration structure.
+ */
+void RIT_GetDefaultConfig(rit_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RIT status flags.
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::rit_status_flags_t
+ */
+static inline uint32_t RIT_GetStatusFlags(RIT_Type *base)
+{
+    return (base->CTRL);
+}
+
+/*!
+ * @brief  Clears the RIT status flags.
+ *
+ * @param base    RIT peripheral base address
+ * @param mask    The status flags to clear. This is a logical OR of members of the
+ *                enumeration ::rit_status_flags_t
+ */
+static inline void RIT_ClearStatusFlags(RIT_Type *base, uint32_t mask)
+{
+    base->CTRL |= mask;
+}
+
+/*! @}*/
+
+/*!
+ * @name Read and Write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of count.
+ *
+ * Timers begin counting from the value set by this function until it XXXXXXX,
+ * then it counting the value again.
+ * Software must stop the counter before reloading it with a new value..
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    RIT peripheral base address
+ * @param count   Timer period in units of ticks
+ */
+void RIT_SetTimerCompare(RIT_Type *base, uint64_t count);
+
+/*!
+ * @brief Sets the mask bit of count compare.
+ *
+ * Timers begin counting from the value set by this function until it XXXXXXX,
+ * then it counting the value again.
+ * Software must stop the counter before reloading it with a new value..
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert to ticks
+ *
+ * @param base    RIT peripheral base address
+ * @param count   Timer period in units of ticks
+ */
+void RIT_SetMaskBit(RIT_Type *base, uint64_t count);
+
+/*!
+ * @brief Reads the current timer counting value of compare register.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return Current timer counting value in ticks
+ */
+uint64_t RIT_GetCompareTimerCount(RIT_Type *base);
+
+/*!
+ * @brief Reads the current timer counting value of counter register.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return Current timer counting value in ticks
+ */
+uint64_t RIT_GetCounterTimerCount(RIT_Type *base);
+
+/*!
+ * @brief Reads the current timer counting value of mask register.
+ *
+ * This function returns the real-time timer counting value, in a range from 0 to a
+ * timer period.
+ *
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ *
+ * @param base    RIT peripheral base address
+ *
+ * @return Current timer counting value in ticks
+ */
+uint64_t RIT_GetMaskTimerCount(RIT_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the timer counting.
+ *
+ * After calling this function, timers load initial value(0U), count up to desired value or over-flow
+ * then the counter will count up again. Each time a timer reaches desired value,
+ * it generates a XXXXXXX and sets XXXXXXX.
+ *
+ * @param base    RIT peripheral base address
+ */
+static inline void RIT_StartTimer(RIT_Type *base)
+{
+    base->CTRL |= RIT_CTRL_RITEN_MASK;
+}
+
+/*!
+ * @brief Stops the timer counting.
+ *
+ * This function stop timer counting. Timer reload their new value
+ * after the next time they call the RIT_StartTimer.
+ *
+ * @param base    RIT peripheral base address
+ * @param channel Timer channel number.
+ */
+static inline void RIT_StopTimer(RIT_Type *base)
+{
+    /* Disable RIT timers */
+    base->CTRL &= ~RIT_CTRL_RITEN_MASK;
+}
+
+/*! @}*/
+
+static inline void RIT_ClearCounter(RIT_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= RIT_CTRL_RITENCLR_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~RIT_CTRL_RITENCLR_MASK;
+    }
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RIT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rng.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RNG_DRIVER_H_
+#define _FSL_RNG_DRIVER_H_
+
+#include "fsl_common.h"
+
+#if defined(FSL_FEATURE_SOC_LPC_RNG_COUNT) && FSL_FEATURE_SOC_LPC_RNG_COUNT
+
+/*!
+ * @addtogroup rng
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief RNG driver version 2.0.0.
+ *
+ * Current version: 2.0.0
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version.
+ */
+#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Gets random data.
+ *
+ * This function returns single 32 bit random number.
+ *
+ * @return random data
+ */
+static inline uint32_t RNG_GetRandomData(void)
+{
+    return OTP_API->rngRead();
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_LPC_RNG_COUNT */
+#endif /*_FSL_TRNG_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SECONDS_IN_A_DAY (86400U)
+#define SECONDS_IN_A_HOUR (3600U)
+#define SECONDS_IN_A_MINUTE (60U)
+#define DAYS_IN_A_YEAR (365U)
+#define YEAR_RANGE_START (1970U)
+#define YEAR_RANGE_END (2099U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Checks whether the date and time passed in is valid
+ *
+ * @param datetime Pointer to structure where the date and time details are stored
+ *
+ * @return Returns false if the date & time details are out of range; true if in range
+ */
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from datetime to seconds
+ *
+ * @param datetime Pointer to datetime structure where the date and time details are stored
+ *
+ * @return The result of the conversion in seconds
+ */
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from seconds to a datetime structure
+ *
+ * @param seconds  Seconds value that needs to be converted to datetime format
+ * @param datetime Pointer to the datetime structure where the result of the conversion is stored
+ */
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Check year, month, hour, minute, seconds */
+    if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
+        (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
+    {
+        /* If not correct then error*/
+        return false;
+    }
+
+    /* Adjust the days in February for a leap year */
+    if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    /* Check the validity of the day */
+    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
+    {
+        return false;
+    }
+
+    return true;
+}
+
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Number of days from begin of the non Leap-year*/
+    /* Number of days from begin of the non Leap-year*/
+    uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
+    uint32_t seconds;
+
+    /* Compute number of days from 1970 till given year*/
+    seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
+    /* Add leap year days */
+    seconds += ((datetime->year / 4) - (1970U / 4));
+    /* Add number of days till given month*/
+    seconds += monthDays[datetime->month];
+    /* Add days in given month. We subtract the current day as it is
+     * represented in the hours, minutes and seconds field*/
+    seconds += (datetime->day - 1);
+    /* For leap year if month less than or equal to Febraury, decrement day counter*/
+    if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
+    {
+        seconds--;
+    }
+
+    seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
+              (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
+
+    return seconds;
+}
+
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t x;
+    uint32_t secondsRemaining, days;
+    uint16_t daysInYear;
+    /* Table of days in a month for a non leap year. First entry in the table is not used,
+     * valid months start from 1
+     */
+    uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+    /* Start with the seconds value that is passed in to be converted to date time format */
+    secondsRemaining = seconds;
+
+    /* Calcuate the number of days, we add 1 for the current day which is represented in the
+     * hours and seconds field
+     */
+    days = secondsRemaining / SECONDS_IN_A_DAY + 1;
+
+    /* Update seconds left*/
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
+
+    /* Calculate the datetime hour, minute and second fields */
+    datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
+    secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
+    datetime->minute = secondsRemaining / 60U;
+    datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
+
+    /* Calculate year */
+    daysInYear = DAYS_IN_A_YEAR;
+    datetime->year = YEAR_RANGE_START;
+    while (days > daysInYear)
+    {
+        /* Decrease day count by a year and increment year by 1 */
+        days -= daysInYear;
+        datetime->year++;
+
+        /* Adjust the number of days for a leap year */
+        if (datetime->year & 3U)
+        {
+            daysInYear = DAYS_IN_A_YEAR;
+        }
+        else
+        {
+            daysInYear = DAYS_IN_A_YEAR + 1;
+        }
+    }
+
+    /* Adjust the days in February for a leap year */
+    if (!(datetime->year & 3U))
+    {
+        daysPerMonth[2] = 29U;
+    }
+
+    for (x = 1U; x <= 12U; x++)
+    {
+        if (days <= daysPerMonth[x])
+        {
+            datetime->month = x;
+            break;
+        }
+        else
+        {
+            days -= daysPerMonth[x];
+        }
+    }
+
+    datetime->day = days;
+}
+
+void RTC_Init(RTC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the RTC peripheral clock */
+    CLOCK_EnableClock(kCLOCK_Rtc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Make sure the reset bit is cleared */
+    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
+
+    /* Make sure the RTC OSC is powered up */
+    base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK;
+}
+
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    /* Return error if the time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(datetime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set time in seconds */
+    base->COUNT = RTC_ConvertDatetimeToSeconds(datetime);
+
+    return kStatus_Success;
+}
+
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t seconds = 0;
+
+    seconds = base->COUNT;
+    RTC_ConvertSecondsToDatetime(seconds, datetime);
+}
+
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
+{
+    assert(alarmTime);
+
+    uint32_t alarmSeconds = 0;
+    uint32_t currSeconds = 0;
+
+    /* Return error if the alarm time provided is not valid */
+    if (!(RTC_CheckDatetimeFormat(alarmTime)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
+
+    /* Get the current time */
+    currSeconds = base->COUNT;
+
+    /* Return error if the alarm time has passed */
+    if (alarmSeconds < currSeconds)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set alarm in seconds*/
+    base->MATCH = alarmSeconds;
+
+    return kStatus_Success;
+}
+
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
+{
+    assert(datetime);
+
+    uint32_t alarmSeconds = 0;
+
+    /* Get alarm in seconds  */
+    alarmSeconds = base->MATCH;
+
+    RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RTC_H_
+#define _FSL_RTC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rtc
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RTC interrupts */
+typedef enum _rtc_interrupt_enable
+{
+    kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/
+    kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK  /*!< Wake-up interrupt.*/
+} rtc_interrupt_enable_t;
+
+/*! @brief List of RTC flags */
+typedef enum _rtc_status_flags
+{
+    kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/
+    kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/
+} rtc_status_flags_t;
+
+/*! @brief Structure is used to hold the date and time */
+typedef struct _rtc_datetime
+{
+    uint16_t year;  /*!< Range from 1970 to 2099.*/
+    uint8_t month;  /*!< Range from 1 to 12.*/
+    uint8_t day;    /*!< Range from 1 to 31 (depending on month).*/
+    uint8_t hour;   /*!< Range from 0 to 23.*/
+    uint8_t minute; /*!< Range from 0 to 59.*/
+    uint8_t second; /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RTC clock and enables the RTC oscillator.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_Init(RTC_Type *base);
+
+/*!
+ * @brief Stop the timer and gate the RTC clock
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Deinit(RTC_Type *base)
+{
+    /* Stop the RTC timer */
+    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the module clock */
+    CLOCK_DisableClock(kCLOCK_Rtc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*! @}*/
+
+/*!
+ * @name Current Time & Alarm
+ * @{
+ */
+
+/*!
+ * @brief Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter must be stopped prior to calling this function as writes to the RTC
+ * seconds register will fail if the RTC counter is running.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details to set are stored
+ *
+ * @return kStatus_Success: Success in setting the time and starting the RTC
+ *         kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Gets the RTC time and stores it in the given time structure.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details are stored.
+ */
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*!
+ * @brief Sets the RTC alarm time
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base      RTC peripheral base address
+ * @param alarmTime Pointer to structure where the alarm time is stored.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ *         kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
+
+/*!
+ * @brief Returns the RTC alarm time.
+ *
+ * @param base     RTC peripheral base address
+ * @param datetime Pointer to structure where the alarm date and time details are stored.
+ */
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*! @}*/
+
+/*!
+ * @brief Enable the RTC high resolution timer and set the wake-up time.
+ *
+ * @param base        RTC peripheral base address
+ * @param wakeupValue The value to be loaded into the RTC WAKE register
+ */
+static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue)
+{
+    /* Enable the 1kHz RTC timer */
+    base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK;
+
+    /* Set the start count value into the wake-up timer */
+    base->WAKE = wakeupValue;
+}
+
+/*!
+ * @brief Read actual RTC counter value.
+ *
+ * @param base        RTC peripheral base address
+ */
+static inline uint16_t RTC_GetWakeupCount(RTC_Type *base)
+{
+    /* Read wake-up counter */
+    return RTC_WAKE_VAL(base->WAKE);
+}
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
+    reg |= mask;
+
+    base->CTRL = reg;
+}
+
+/*!
+ * @brief Disables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask);
+
+    base->CTRL = reg;
+}
+
+/*!
+ * @brief Gets the enabled RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::rtc_interrupt_enable_t
+ */
+static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
+{
+    return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RTC status flags
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::rtc_status_flags_t
+ */
+static inline uint32_t RTC_GetStatusFlags(RTC_Type *base)
+{
+    return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK));
+}
+
+/*!
+ * @brief  Clears the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::rtc_status_flags_t
+ */
+static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
+{
+    uint32_t reg = base->CTRL;
+
+    /* Clear flag bits to prevent accidentally clearing anything when writing back */
+    reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
+
+    /* Write 1 to the flags we wish to clear */
+    reg |= mask;
+
+    base->CTRL = reg;
+}
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * After calling this function, the timer counter increments once a second provided SR[TOF] or
+ * SR[TIF] are not set.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StartTimer(RTC_Type *base)
+{
+    base->CTRL |= RTC_CTRL_RTC_EN_MASK;
+}
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * RTC's seconds register can be written to only when the timer is stopped.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StopTimer(RTC_Type *base)
+{
+    base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Reset(RTC_Type *base)
+{
+    base->CTRL |= RTC_CTRL_SWRESET_MASK;
+    base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
+}
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RTC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,535 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sctimer.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief Typedef for interrupt handler. */
+typedef void (*sctimer_isr_t)(SCT_Type *base);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The SCTimer instance
+ */
+static uint32_t SCTIMER_GetInstance(SCT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to SCT bases for each instance. */
+static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to SCT clocks for each instance. */
+static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to SCT resets for each instance. */
+static const reset_ip_name_t s_sctResets[] = SCT_RSTS;
+
+/*!< @brief SCTimer event Callback function. */
+static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS];
+
+/*!< @brief Keep track of SCTimer event number */
+static uint32_t s_currentEvent;
+
+/*!< @brief Keep track of SCTimer state number */
+static uint32_t s_currentState;
+
+/*!< @brief Keep track of SCTimer match/capture register number */
+static uint32_t s_currentMatch;
+
+/*! @brief Pointer to SCTimer IRQ handler */
+static sctimer_isr_t s_sctimerIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SCTIMER_GetInstance(SCT_Type *base)
+{
+    uint32_t instance;
+    uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < sctArrayCount; instance++)
+    {
+        if (s_sctBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < sctArrayCount);
+
+    return instance;
+}
+
+status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config)
+{
+    assert(config);
+    uint32_t i;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SCTimer clock*/
+    CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module */
+    RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]);
+
+    /* Setup the counter operation */
+    base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) |
+                   SCT_CONFIG_UNIFY(config->enableCounterUnify);
+
+    /* Write to the control register, clear the counter and keep the counters halted */
+    base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) |
+                 SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK;
+
+    if (!(config->enableCounterUnify))
+    {
+        base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) |
+                      SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK;
+    }
+
+    /* Initial state of channel output */
+    base->OUTPUT = config->outInitState;
+
+    /* Clear the global variables */
+    s_currentEvent = 0;
+    s_currentState = 0;
+    s_currentMatch = 0;
+
+    /* Clear the callback array */
+    for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
+    {
+        s_eventCallback[i] = NULL;
+    }
+
+    /* Save interrupt handler */
+    s_sctimerIsr = SCTIMER_EventHandleIRQ;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_Deinit(SCT_Type *base)
+{
+    /* Halt the counters */
+    base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the SCTimer clock*/
+    CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void SCTIMER_GetDefaultConfig(sctimer_config_t *config)
+{
+    assert(config);
+
+    /* SCT operates as a unified 32-bit counter */
+    config->enableCounterUnify = true;
+    /* System clock clocks the entire SCT module */
+    config->clockMode = kSCTIMER_System_ClockMode;
+    /* This is used only by certain clock modes */
+    config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
+    /* Up count mode only for the unified counter */
+    config->enableBidirection_l = false;
+    /* Up count mode only for Counte_H */
+    config->enableBidirection_h = false;
+    /* Prescale factor of 1 */
+    config->prescale_l = 0;
+    /* Prescale factor of 1 for Counter_H*/
+    config->prescale_h = 0;
+    /* Clear outputs */
+    config->outInitState = 0;
+}
+
+status_t SCTIMER_SetupPwm(SCT_Type *base,
+                          const sctimer_pwm_signal_param_t *pwmParams,
+                          sctimer_pwm_mode_t mode,
+                          uint32_t pwmFreq_Hz,
+                          uint32_t srcClock_Hz,
+                          uint32_t *event)
+{
+    assert(pwmParams);
+    assert(srcClock_Hz);
+    assert(pwmFreq_Hz);
+
+    uint32_t period, pulsePeriod = 0;
+    uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1);
+    uint32_t periodEvent, pulseEvent;
+    uint32_t reg;
+
+    /* This function will create 2 events, return an error if we do not have enough events available */
+    if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
+    {
+        return kStatus_Fail;
+    }
+
+    if (pwmParams->dutyCyclePercent == 0)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Set unify bit to operate in 32-bit counter mode */
+    base->CONFIG |= SCT_CONFIG_UNIFY_MASK;
+
+    /* Use bi-directional mode for center-aligned PWM */
+    if (mode == kSCTIMER_CenterAlignedPwm)
+    {
+        base->CTRL |= SCT_CTRL_BIDIR_L_MASK;
+    }
+
+    /* Calculate PWM period match value */
+    if (mode == kSCTIMER_EdgeAlignedPwm)
+    {
+        period = (sctClock / pwmFreq_Hz) - 1;
+    }
+    else
+    {
+        period = sctClock / (pwmFreq_Hz * 2);
+    }
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100;
+
+    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
+    if (pwmParams->dutyCyclePercent >= 100)
+    {
+        pulsePeriod = period + 2;
+    }
+
+    /* Schedule an event when we reach the PWM period */
+    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent);
+
+    /* Schedule an event when we reach the pulse width */
+    SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent);
+
+    /* Reset the counter when we reach the PWM period */
+    SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent);
+
+    /* Return the period event to the user */
+    *event = periodEvent;
+
+    /* For high-true level */
+    if (pwmParams->level == kSCTIMER_HighTrue)
+    {
+        /* Set the initial output level to low which is the inactive state */
+        base->OUTPUT &= ~(1U << pwmParams->output);
+
+        if (mode == kSCTIMER_EdgeAlignedPwm)
+        {
+            /* Set the output when we reach the PWM period */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent);
+            /* Clear the output when we reach the PWM pulse value */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
+        }
+        else
+        {
+            /* Clear the output when we reach the PWM pulse event */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
+            /* Reverse output when down counting */
+            reg = base->OUTPUTDIRCTRL;
+            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
+            reg |= (1U << (2 * pwmParams->output));
+            base->OUTPUTDIRCTRL = reg;
+        }
+    }
+    /* For low-true level */
+    else
+    {
+        /* Set the initial output level to high which is the inactive state */
+        base->OUTPUT |= (1U << pwmParams->output);
+
+        if (mode == kSCTIMER_EdgeAlignedPwm)
+        {
+            /* Clear the output when we reach the PWM period */
+            SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent);
+            /* Set the output when we reach the PWM pulse value */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
+        }
+        else
+        {
+            /* Set the output when we reach the PWM pulse event */
+            SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
+            /* Reverse output when down counting */
+            reg = base->OUTPUTDIRCTRL;
+            reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
+            reg |= (1U << (2 * pwmParams->output));
+            base->OUTPUTDIRCTRL = reg;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event)
+
+{
+    assert(dutyCyclePercent > 0);
+
+    uint32_t periodMatchReg, pulseMatchReg;
+    uint32_t pulsePeriod = 0, period;
+
+    /* Retrieve the match register number for the PWM period */
+    periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
+
+    /* Retrieve the match register number for the PWM pulse period */
+    pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
+
+    period = base->SCTMATCH[periodMatchReg];
+
+    /* Calculate pulse width match value */
+    pulsePeriod = (period * dutyCyclePercent) / 100;
+
+    /* For 100% dutycyle, make pulse period greater than period so the event will never occur */
+    if (dutyCyclePercent >= 100)
+    {
+        pulsePeriod = period + 2;
+    }
+
+    /* Stop the counter before updating match register */
+    SCTIMER_StopTimer(base, kSCTIMER_Counter_L);
+
+    /* Update dutycycle */
+    base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod);
+    base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod);
+
+    /* Restart the counter */
+    SCTIMER_StartTimer(base, kSCTIMER_Counter_L);
+}
+
+status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
+                                        sctimer_event_t howToMonitor,
+                                        uint32_t matchValue,
+                                        uint32_t whichIO,
+                                        sctimer_counter_t whichCounter,
+                                        uint32_t *event)
+{
+    uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT);
+    uint32_t currentCtrlVal = howToMonitor;
+
+    /* Return an error if we have hit the limit in terms of number of events created */
+    if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
+    {
+        return kStatus_Fail;
+    }
+
+    /* IO only mode */
+    if (combMode == 0x2U)
+    {
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO);
+    }
+    /* Match mode only */
+    else if (combMode == 0x1U)
+    {
+        /* Return an error if we have hit the limit in terms of number of number of match registers */
+        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+        {
+            return kStatus_Fail;
+        }
+
+        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch);
+        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+        {
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
+        }
+        else
+        {
+            /* Select the counter, no need for this if operating in 32-bit mode */
+            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
+        }
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
+        /* Increment the match register number */
+        s_currentMatch++;
+    }
+    /* Use both Match & IO */
+    else
+    {
+        /* Return an error if we have hit the limit in terms of number of number of match registers */
+        if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+        {
+            return kStatus_Fail;
+        }
+
+        currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO);
+        /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+        if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+        {
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
+        }
+        else
+        {
+            /* Select the counter, no need for this if operating in 32-bit mode */
+            currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
+            base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
+            base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
+        }
+        base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
+        /* Increment the match register number */
+        s_currentMatch++;
+    }
+
+    /* Enable the event in the current state */
+    base->EVENT[s_currentEvent].STATE = (1U << s_currentState);
+
+    /* Return the event number */
+    *event = s_currentEvent;
+
+    /* Increment the event number */
+    s_currentEvent++;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event)
+{
+    /* Enable event in the current state */
+    base->EVENT[event].STATE |= (1U << s_currentState);
+}
+
+status_t SCTIMER_IncreaseState(SCT_Type *base)
+{
+    /* Return an error if we have hit the limit in terms of states used */
+    if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES)
+    {
+        return kStatus_Fail;
+    }
+
+    s_currentState++;
+
+    return kStatus_Success;
+}
+
+uint32_t SCTIMER_GetCurrentState(SCT_Type *base)
+{
+    return s_currentState;
+}
+
+void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    uint32_t reg;
+
+    /* Set the same event to set and clear the output */
+    base->OUT[whichIO].CLR |= (1U << event);
+    base->OUT[whichIO].SET |= (1U << event);
+
+    /* Set the conflict resolution to toggle output */
+    reg = base->RES;
+    reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO));
+    reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO));
+    base->RES = reg;
+}
+
+status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
+                                    sctimer_counter_t whichCounter,
+                                    uint32_t *captureRegister,
+                                    uint32_t event)
+{
+    /* Return an error if we have hit the limit in terms of number of capture/match registers used */
+    if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        /* Set the bit to enable event */
+        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event);
+
+        /* Set this resource to be a capture rather than match */
+        base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch);
+    }
+    else
+    {
+        /* Set bit to enable event */
+        base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event);
+
+        /* Set this resource to be a capture rather than match */
+        base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch);
+    }
+
+    /* Return the match register number */
+    *captureRegister = s_currentMatch;
+
+    /* Increase the match register number */
+    s_currentMatch++;
+
+    return kStatus_Success;
+}
+
+void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event)
+{
+    s_eventCallback[event] = callback;
+}
+
+void SCTIMER_EventHandleIRQ(SCT_Type *base)
+{
+    uint32_t eventFlag = SCT0->EVFLAG;
+    /* Only clear the flags whose interrupt field is enabled */
+    uint32_t clearFlag = (eventFlag & SCT0->EVEN);
+    uint32_t mask = eventFlag;
+    int i = 0;
+
+    /* Invoke the callback for certain events */
+    for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++)
+    {
+        if (mask & 0x1)
+        {
+            if (s_eventCallback[i] != NULL)
+            {
+                s_eventCallback[i]();
+            }
+        }
+        mask >>= 1;
+    }
+
+    /* Clear event interrupt flag */
+    SCT0->EVFLAG = clearFlag;
+}
+
+void SCT0_IRQHandler(void)
+{
+    s_sctimerIsr(SCT0);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,822 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SCTIMER_H_
+#define _FSL_SCTIMER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sctimer
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief SCTimer PWM operation modes */
+typedef enum _sctimer_pwm_mode
+{
+    kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
+    kSCTIMER_CenterAlignedPwm     /*!< Center-aligned PWM */
+} sctimer_pwm_mode_t;
+
+/*! @brief SCTimer counters when working as two independent 16-bit counters */
+typedef enum _sctimer_counter
+{
+    kSCTIMER_Counter_L = 0U, /*!< Counter L */
+    kSCTIMER_Counter_H       /*!< Counter H */
+} sctimer_counter_t;
+
+/*! @brief List of SCTimer input pins */
+typedef enum _sctimer_input
+{
+    kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */
+    kSCTIMER_Input_1,      /*!< SCTIMER input 1 */
+    kSCTIMER_Input_2,      /*!< SCTIMER input 2 */
+    kSCTIMER_Input_3,      /*!< SCTIMER input 3 */
+    kSCTIMER_Input_4,      /*!< SCTIMER input 4 */
+    kSCTIMER_Input_5,      /*!< SCTIMER input 5 */
+    kSCTIMER_Input_6,      /*!< SCTIMER input 6 */
+    kSCTIMER_Input_7       /*!< SCTIMER input 7 */
+} sctimer_input_t;
+
+/*! @brief List of SCTimer output pins */
+typedef enum _sctimer_out
+{
+    kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/
+    kSCTIMER_Out_1,      /*!< SCTIMER output 1 */
+    kSCTIMER_Out_2,      /*!< SCTIMER output 2 */
+    kSCTIMER_Out_3,      /*!< SCTIMER output 3 */
+    kSCTIMER_Out_4,      /*!< SCTIMER output 4 */
+    kSCTIMER_Out_5,      /*!< SCTIMER output 5 */
+    kSCTIMER_Out_6,      /*!< SCTIMER output 6 */
+    kSCTIMER_Out_7       /*!< SCTIMER output 7 */
+} sctimer_out_t;
+
+/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */
+typedef enum _sctimer_pwm_level_select
+{
+    kSCTIMER_LowTrue = 0U, /*!< Low true pulses */
+    kSCTIMER_HighTrue      /*!< High true pulses */
+} sctimer_pwm_level_select_t;
+
+/*! @brief Options to configure a SCTimer PWM signal */
+typedef struct _sctimer_pwm_signal_param
+{
+    sctimer_out_t output;             /*!< The output pin to use to generate the PWM signal */
+    sctimer_pwm_level_select_t level; /*!< PWM output active level select. */
+    uint8_t dutyCyclePercent;         /*!< PWM pulse width, value should be between 1 to 100
+                                           100 = always active signal (100% duty cycle).*/
+} sctimer_pwm_signal_param_t;
+
+/*! @brief SCTimer clock mode options */
+typedef enum _sctimer_clock_mode
+{
+    kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */
+    kSCTIMER_Sampled_ClockMode,     /*!< Sampled System Clock Mode */
+    kSCTIMER_Input_ClockMode,       /*!< SCT Input Clock Mode */
+    kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */
+} sctimer_clock_mode_t;
+
+/*! @brief SCTimer clock select options */
+typedef enum _sctimer_clock_select
+{
+    kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */
+    kSCTIMER_Clock_On_Fall_Input_0,      /*!< Falling edges on input 0 */
+    kSCTIMER_Clock_On_Rise_Input_1,      /*!< Rising edges on input 1 */
+    kSCTIMER_Clock_On_Fall_Input_1,      /*!< Falling edges on input 1 */
+    kSCTIMER_Clock_On_Rise_Input_2,      /*!< Rising edges on input 2 */
+    kSCTIMER_Clock_On_Fall_Input_2,      /*!< Falling edges on input 2 */
+    kSCTIMER_Clock_On_Rise_Input_3,      /*!< Rising edges on input 3 */
+    kSCTIMER_Clock_On_Fall_Input_3,      /*!< Falling edges on input 3 */
+    kSCTIMER_Clock_On_Rise_Input_4,      /*!< Rising edges on input 4 */
+    kSCTIMER_Clock_On_Fall_Input_4,      /*!< Falling edges on input 4 */
+    kSCTIMER_Clock_On_Rise_Input_5,      /*!< Rising edges on input 5 */
+    kSCTIMER_Clock_On_Fall_Input_5,      /*!< Falling edges on input 5 */
+    kSCTIMER_Clock_On_Rise_Input_6,      /*!< Rising edges on input 6 */
+    kSCTIMER_Clock_On_Fall_Input_6,      /*!< Falling edges on input 6 */
+    kSCTIMER_Clock_On_Rise_Input_7,      /*!< Rising edges on input 7 */
+    kSCTIMER_Clock_On_Fall_Input_7       /*!< Falling edges on input 7 */
+} sctimer_clock_select_t;
+
+/*!
+ * @brief SCTimer output conflict resolution options.
+ *
+ * Specifies what action should be taken if multiple events dictate that a given output should be
+ * both set and cleared at the same time
+ */
+typedef enum _sctimer_conflict_resolution
+{
+    kSCTIMER_ResolveNone = 0U, /*!< No change */
+    kSCTIMER_ResolveSet,       /*!< Set output */
+    kSCTIMER_ResolveClear,     /*!< Clear output */
+    kSCTIMER_ResolveToggle     /*!< Toggle output */
+} sctimer_conflict_resolution_t;
+
+/*! @brief List of SCTimer event types */
+typedef enum _sctimer_event
+{
+    kSCTIMER_InputLowOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_MatchEventOnly =
+        (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_InputLowEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_InputLowAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputRiseAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputFallAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_InputHighAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighOrMatchEvent =
+        (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighEvent =
+        (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+
+    kSCTIMER_OutputLowAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputRiseAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputFallAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
+    kSCTIMER_OutputHighAndMatchEvent =
+        (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT)
+} sctimer_event_t;
+
+/*! @brief SCTimer callback typedef. */
+typedef void (*sctimer_event_callback_t)(void);
+
+/*! @brief List of SCTimer interrupts */
+typedef enum _sctimer_interrupt_enable
+{
+    kSCTIMER_Event0InterruptEnable = (1U << 0),   /*!< Event 0 interrupt */
+    kSCTIMER_Event1InterruptEnable = (1U << 1),   /*!< Event 1 interrupt */
+    kSCTIMER_Event2InterruptEnable = (1U << 2),   /*!< Event 2 interrupt */
+    kSCTIMER_Event3InterruptEnable = (1U << 3),   /*!< Event 3 interrupt */
+    kSCTIMER_Event4InterruptEnable = (1U << 4),   /*!< Event 4 interrupt */
+    kSCTIMER_Event5InterruptEnable = (1U << 5),   /*!< Event 5 interrupt */
+    kSCTIMER_Event6InterruptEnable = (1U << 6),   /*!< Event 6 interrupt */
+    kSCTIMER_Event7InterruptEnable = (1U << 7),   /*!< Event 7 interrupt */
+    kSCTIMER_Event8InterruptEnable = (1U << 8),   /*!< Event 8 interrupt */
+    kSCTIMER_Event9InterruptEnable = (1U << 9),   /*!< Event 9 interrupt */
+    kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */
+    kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */
+    kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */
+} sctimer_interrupt_enable_t;
+
+/*! @brief List of SCTimer flags */
+typedef enum _sctimer_status_flags
+{
+    kSCTIMER_Event0Flag = (1U << 0),   /*!< Event 0 Flag */
+    kSCTIMER_Event1Flag = (1U << 1),   /*!< Event 1 Flag */
+    kSCTIMER_Event2Flag = (1U << 2),   /*!< Event 2 Flag */
+    kSCTIMER_Event3Flag = (1U << 3),   /*!< Event 3 Flag */
+    kSCTIMER_Event4Flag = (1U << 4),   /*!< Event 4 Flag */
+    kSCTIMER_Event5Flag = (1U << 5),   /*!< Event 5 Flag */
+    kSCTIMER_Event6Flag = (1U << 6),   /*!< Event 6 Flag */
+    kSCTIMER_Event7Flag = (1U << 7),   /*!< Event 7 Flag */
+    kSCTIMER_Event8Flag = (1U << 8),   /*!< Event 8 Flag */
+    kSCTIMER_Event9Flag = (1U << 9),   /*!< Event 9 Flag */
+    kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */
+    kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */
+    kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */
+    kSCTIMER_BusErrorLFlag =
+        (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */
+    kSCTIMER_BusErrorHFlag =
+        (1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */
+} sctimer_status_flags_t;
+
+/*!
+ * @brief SCTimer configuration structure
+ *
+ * This structure holds the configuration settings for the SCTimer peripheral. To initialize this
+ * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _sctimer_config
+{
+    bool enableCounterUnify;            /*!< true: SCT operates as a unified 32-bit counter;
+                                             false: SCT operates as two 16-bit counters */
+    sctimer_clock_mode_t clockMode;     /*!< SCT clock mode value */
+    sctimer_clock_select_t clockSelect; /*!< SCT clock select value */
+    bool enableBidirection_l;           /*!< true: Up-down count mode for the L or unified counter
+                                             false: Up count mode only for the L or unified counter */
+    bool enableBidirection_h;           /*!< true: Up-down count mode for the H or unified counter
+                                             false: Up count mode only for the H or unified counter.
+                                             This field is used only if the enableCounterUnify is set
+                                             to false */
+    uint8_t prescale_l;                 /*!< Prescale value to produce the L or unified counter clock */
+    uint8_t prescale_h;                 /*!< Prescale value to produce the H counter clock.
+                                             This field is used only if the enableCounterUnify is set
+                                             to false */
+    uint8_t outInitState;               /*!< Defines the initial output value */
+} sctimer_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the SCTimer clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application using the SCTimer driver.
+ *
+ * @param base   SCTimer peripheral base address
+ * @param config Pointer to the user configuration structure.
+ *
+ * @return kStatus_Success indicates success; Else indicates failure.
+ */
+status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config);
+
+/*!
+ * @brief Gates the SCTimer clock.
+ *
+ * @param base SCTimer peripheral base address
+ */
+void SCTIMER_Deinit(SCT_Type *base);
+
+/*!
+ * @brief  Fills in the SCTimer configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ *  config->enableCounterUnify = true;
+ *  config->clockMode = kSCTIMER_System_ClockMode;
+ *  config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
+ *  config->enableBidirection_l = false;
+ *  config->enableBidirection_h = false;
+ *  config->prescale_l = 0;
+ *  config->prescale_h = 0;
+ *  config->outInitState = 0;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void SCTIMER_GetDefaultConfig(sctimer_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name PWM setup operations
+ * @{
+ */
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This
+ * function will create 2 events; one of the events will trigger on match with the pulse value
+ * and the other will trigger when the counter matches the PWM period. The PWM period event is
+ * also used as a limit event to reset the counter or change direction. Both events are enabled
+ * for the same state. The state number can be retrieved by calling the function
+ * SCTIMER_GetCurrentStateNumber().
+ * The counter is set to operate as one 32-bit counter (unify bit is set to 1).
+ * The counter operates in bi-directional mode when generating a center-aligned PWM.
+ *
+ * @note When setting PWM output from multiple output pins, they all should use the same PWM mode
+ * i.e all PWM's should be either edge-aligned or center-aligned.
+ * When using this API, the PWM signal frequency of all the initialized channels must be the same.
+ * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the 
+ * API's pwmFreq_Hz.
+ *
+ * @param base        SCTimer peripheral base address
+ * @param pwmParams   PWM parameters to configure the output
+ * @param mode        PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t
+ * @param pwmFreq_Hz  PWM signal frequency in Hz
+ * @param srcClock_Hz SCTimer counter clock in Hz
+ * @param event       Pointer to a variable where the PWM period event number is stored
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Fail If we have hit the limit in terms of number of events created or if
+ *                      an incorrect PWM dutycylce is passed in.
+ */
+status_t SCTIMER_SetupPwm(SCT_Type *base,
+                          const sctimer_pwm_signal_param_t *pwmParams,
+                          sctimer_pwm_mode_t mode,
+                          uint32_t pwmFreq_Hz,
+                          uint32_t srcClock_Hz,
+                          uint32_t *event);
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base              SCTimer peripheral base address
+ * @param output            The output to configure
+ * @param dutyCyclePercent  New PWM pulse width; the value should be between 1 to 100
+ * @param event             Event number associated with this PWM signal. This was returned to the user by the
+ *                          function SCTIMER_SetupPwm().
+ */
+void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event);
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::sctimer_interrupt_enable_t
+ */
+static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask)
+{
+    base->EVEN |= mask;
+}
+
+/*!
+ * @brief Disables the selected SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ *             enumeration ::sctimer_interrupt_enable_t
+ */
+static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask)
+{
+    base->EVEN &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled SCTimer interrupts.
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ *         enumeration ::sctimer_interrupt_enable_t
+ */
+static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base)
+{
+    return (base->EVEN & 0xFFFFU);
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the SCTimer status flags.
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::sctimer_status_flags_t
+ */
+static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base)
+{
+    uint32_t statusFlags = 0;
+
+    /* Add the recorded events */
+    statusFlags = (base->EVFLAG & 0xFFFFU);
+
+    /* Add bus error flags */
+    statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
+
+    return statusFlags;
+}
+
+/*!
+ * @brief Clears the SCTimer status flags.
+ *
+ * @param base SCTimer peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::sctimer_status_flags_t
+ */
+static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask)
+{
+    /* Write to the flag registers */
+    base->EVFLAG = (mask & 0xFFFFU);
+    base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Counter Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the SCTimer counter.
+ *
+ * @param base           SCTimer peripheral base address
+ * @param countertoStart SCTimer counter to start; if unify mode is set then function always
+ *                       writes to HALT_L bit
+ */
+static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart)
+{
+    /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L))
+    {
+        base->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
+    }
+    else
+    {
+        /* Start H counter */
+        base->CTRL &= ~(SCT_CTRL_HALT_H_MASK);
+    }
+}
+
+/*!
+ * @brief Halts the SCTimer counter.
+ *
+ * @param base          SCTimer peripheral base address
+ * @param countertoStop SCTimer counter to stop; if unify mode is set then function always
+ *                      writes to HALT_L bit
+ */
+static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop)
+{
+    /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L))
+    {
+        base->CTRL |= (SCT_CTRL_HALT_L_MASK);
+    }
+    else
+    {
+        /* Stop H counter */
+        base->CTRL |= (SCT_CTRL_HALT_H_MASK);
+    }
+}
+
+/*! @}*/
+
+/*!
+ * @name Functions to create a new event and manage the state logic
+ * @{
+ */
+
+/*!
+ * @brief Create an event that is triggered on a match or IO and schedule in current state.
+ *
+ * This function will configure an event using the options provided by the user. If the event type uses
+ * the counter match, then the function will set the user provided match value into a match register
+ * and put this match register number into the event control register.
+ * The event is enabled for the current state and the event number is increased by one at the end.
+ * The function returns the event number; this event number can be used to configure actions to be
+ * done when this event is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t
+ * @param matchValue   The match value that will be programmed to a match register
+ * @param whichIO      The input or output that will be involved in event triggering. This field
+ *                     is ignored if the event type is "match only"
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as we have only 1 unified counter; hence ignored.
+ * @param event        Pointer to a variable where the new event number is stored
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of number of events created or
+                         if we have reached the limit in terms of number of match registers
+ */
+status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
+                                        sctimer_event_t howToMonitor,
+                                        uint32_t matchValue,
+                                        uint32_t whichIO,
+                                        sctimer_counter_t whichCounter,
+                                        uint32_t *event);
+
+/*!
+ * @brief Enable an event in the current state.
+ *
+ * This function will allow the event passed in to trigger in the current state. The event must
+ * be created earlier by either calling the function SCTIMER_SetupPwm() or function
+ * SCTIMER_CreateAndScheduleEvent() .
+ *
+ * @param base  SCTimer peripheral base address
+ * @param event Event number to enable in the current state
+ *
+ */
+void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event);
+
+/*!
+ * @brief Increase the state by 1
+ *
+ * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new
+ * state.
+ *
+ * @param base  SCTimer peripheral base address
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of states used
+
+ */
+status_t SCTIMER_IncreaseState(SCT_Type *base);
+
+/*!
+ * @brief Provides the current state
+ *
+ * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction().
+ *
+ * @param base SCTimer peripheral base address
+ *
+ * @return The current state
+ */
+uint32_t SCTIMER_GetCurrentState(SCT_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Actions to take in response to an event
+ * @{
+ */
+
+/*!
+ * @brief Setup capture of the counter value on trigger of a selected event
+ *
+ * @param base            SCTimer peripheral base address
+ * @param whichCounter    SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                        field has no meaning as only the Counter_L bits are used.
+ * @param captureRegister Pointer to a variable where the capture register number will be returned. User
+ *                        can read the captured value from this register when the specified event is triggered.
+ * @param event           Event number that will trigger the capture
+ *
+ * @return kStatus_Success on success
+ *         kStatus_Error if we have hit the limit in terms of number of match/capture registers available
+ */
+status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
+                                    sctimer_counter_t whichCounter,
+                                    uint32_t *captureRegister,
+                                    uint32_t event);
+
+/*!
+ * @brief Receive noticification when the event trigger an interrupt.
+ *
+ * If the interrupt for the event is enabled by the user, then a callback can be registered
+ * which will be invoked when the event is triggered
+ *
+ * @param base     SCTimer peripheral base address
+ * @param event    Event number that will trigger the interrupt
+ * @param callback Function to invoke when the event is triggered
+ */
+
+void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event);
+
+/*!
+ * @brief Transition to the specified state.
+ *
+ * This transition will be triggered by the event number that is passed in by the user.
+ *
+ * @param base      SCTimer peripheral base address
+ * @param nextState The next state SCTimer will transition to
+ * @param event     Event number that will trigger the state transition
+ */
+static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event)
+{
+    uint32_t reg = base->EVENT[event].CTRL;
+
+    reg &= ~(SCT_EVENT_CTRL_STATEV_MASK);
+    /* Load the STATEV value when the event occurs to be the next state */
+    reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK;
+
+    base->EVENT[event].CTRL = reg;
+}
+
+/*!
+ * @brief Set the Output.
+ *
+ * This output will be set when the event number that is passed in by the user is triggered.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to set
+ * @param event   Event number that will trigger the output change
+ */
+static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    base->OUT[whichIO].SET |= (1U << event);
+}
+
+/*!
+ * @brief Clear the Output.
+ *
+ * This output will be cleared when the event number that is passed in by the user is triggered.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to clear
+ * @param event   Event number that will trigger the output change
+ */
+static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
+{
+    base->OUT[whichIO].CLR |= (1U << event);
+}
+
+/*!
+ * @brief Toggle the output level.
+ *
+ * This change in the output level is triggered by the event number that is passed in by the user.
+ *
+ * @param base    SCTimer peripheral base address
+ * @param whichIO The output to toggle
+ * @param event   Event number that will trigger the output change
+ */
+void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event);
+
+/*!
+ * @brief Limit the running counter.
+ *
+ * The counter is limited when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be limited
+ */
+static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event);
+    }
+    else
+    {
+        base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Stop the running counter.
+ *
+ * The counter is stopped when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be stopped
+ */
+static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->STOP |= SCT_STOP_STOPMSK_L(1U << event);
+    }
+    else
+    {
+        base->STOP |= SCT_STOP_STOPMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Re-start the stopped counter.
+ *
+ * The counter will re-start when the event number that is passed in by the user is triggered.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to re-start
+ */
+static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->START |= SCT_START_STARTMSK_L(1U << event);
+    }
+    else
+    {
+        base->START |= SCT_START_STARTMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Halt the running counter.
+ *
+ * The counter is disabled (halted) when the event number that is passed in by the user is
+ * triggered. When the counter is halted, all further events are disabled. The HALT condition
+ * can only be removed by calling the SCTIMER_StartTimer() function.
+ *
+ * @param base         SCTimer peripheral base address
+ * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
+ *                     field has no meaning as only the Counter_L bits are used.
+ * @param event        Event number that will trigger the counter to be halted
+ */
+static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
+{
+    /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
+    if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
+    {
+        base->HALT |= SCT_HALT_HALTMSK_L(1U << event);
+    }
+    else
+    {
+        base->HALT |= SCT_HALT_HALTMSK_H(1U << event);
+    }
+}
+
+/*!
+ * @brief Generate a DMA request.
+ *
+ * DMA request will be triggered by the event number that is passed in by the user.
+ *
+ * @param base      SCTimer peripheral base address
+ * @param dmaNumber The DMA request to generate
+ * @param event     Event number that will trigger the DMA request
+ */
+static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event)
+{
+    if (dmaNumber == 0)
+    {
+        base->DMA0REQUEST |= (1U << event);
+    }
+    else
+    {
+        base->DMA1REQUEST |= (1U << event);
+    }
+}
+
+/*!
+ * @brief SCTimer interrupt handler.
+ *
+ * @param base SCTimer peripheral base address.
+ */
+void SCTIMER_EventHandleIRQ(SCT_Type *base);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SCTIMER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,1293 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sdif.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Typedef for interrupt handler. */
+typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get the instance.
+ *
+ * @param base SDIF peripheral base address.
+ * @return Instance number.
+ */
+static uint32_t SDIF_GetInstance(SDIF_Type *base);
+
+/*
+* @brief config the SDIF interface before transfer between the card and host
+* @param SDIF base address
+* @param transfer config structure
+*/
+static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer);
+
+/*
+* @brief wait the command done function and check error status
+* @param SDIF base address
+* @param command config structure
+*/
+static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command);
+
+/*
+* @brief transfer data in a blocking way
+* @param SDIF base address
+* @param data config structure
+* @param indicate current transfer mode:DMA or polling
+*/
+static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA);
+
+/*
+* @brief read the command response
+* @param SDIF base address
+* @param sdif command pointer
+*/
+static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command);
+
+/*
+* @brief handle transfer command interrupt
+* @param SDIF base address
+* @param sdif handle
+* @param interrupt mask flags
+*/
+static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
+
+/*
+* @brief handle transfer data interrupt
+* @param SDIF base address
+* @param sdif handle
+* @param interrupt mask flags
+*/
+static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
+
+/*
+* @brief handle DMA transfer
+* @param SDIF base address
+* @param sdif handle
+* @param interrupt mask flag
+*/
+static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags);
+
+/*
+* @brief driver IRQ handler
+* @param SDIF base address
+* @param sdif handle
+*/
+static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle);
+
+/*
+* @brief read data port
+* @param SDIF base address
+* @param sdif data
+* @param the number of data been transferred
+*/
+static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords);
+
+/*
+* @brief write data port
+* @param SDIF base address
+* @param sdif data
+* @param the number of data been transferred
+*/
+static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords);
+
+/*
+* @brief read data by blocking way
+* @param SDIF base address
+* @param sdif data
+*/
+static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data);
+
+/*
+* @brief write data by blocking way
+* @param SDIF base address
+* @param sdif data
+*/
+static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data);
+
+/*
+* @brief handle sdio interrupt
+* This function will call the SDIO interrupt callback
+* @param SDIF handle
+*/
+static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief SDIF internal handle pointer array */
+static sdif_handle_t *s_sdifHandle[FSL_FEATURE_SOC_SDIF_COUNT];
+
+/*! @brief SDIF base pointer array */
+static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS;
+
+/*! @brief SDIF IRQ name array */
+static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS;
+
+/* SDIF ISR for transactional APIs. */
+static sdif_isr_t s_sdifIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SDIF_GetInstance(SDIF_Type *base)
+{
+    uint8_t instance = 0U;
+
+    while ((instance < ARRAY_SIZE(s_sdifBase)) && (s_sdifBase[instance] != base))
+    {
+        instance++;
+    }
+
+    assert(instance < ARRAY_SIZE(s_sdifBase));
+
+    return instance;
+}
+
+static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer)
+{
+    sdif_command_t *command = transfer->command;
+    sdif_data_t *data = transfer->data;
+
+    if ((command == NULL) || (data && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK)))
+    {
+        return kStatue_SDIF_InvalidArgument;
+    }
+
+    if (data != NULL)
+    {
+        /* config the block size register ,the block size maybe smaller than FIFO
+         depth, will test on the board */
+        base->BLKSIZ = SDIF_BLKSIZ_BLOCK_SIZE(data->blockSize);
+        /* config the byte count register */
+        base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount);
+
+        command->flags |= kSDIF_DataExpect; /* need transfer data flag */
+
+        if (data->txData != NULL)
+        {
+            command->flags |= kSDIF_DataWriteToCard; /* data transfer direction */
+        }
+        else
+        {
+            /* config the card read threshold,enable the card read threshold */
+            if (data->blockSize <= (SDIF_FIFO_COUNT * sizeof(uint32_t)))
+            {
+                base->CARDTHRCTL = SDIF_CARDTHRCTL_CARDRDTHREN_MASK | SDIF_CARDTHRCTL_CARDTHRESHOLD(data->blockSize);
+            }
+            else
+            {
+                base->CARDTHRCTL &= ~SDIF_CARDTHRCTL_CARDRDTHREN_MASK;
+            }
+        }
+
+        if (data->streamTransfer)
+        {
+            command->flags |= kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer  */
+        }
+
+        if ((data->enableAutoCommand12) &&
+            (data->blockCount > 1U)) /* indicate if auto stop will send after the data transfer done */
+        {
+            command->flags |= kSDIF_DataTransferAutoStop;
+        }
+    }
+    /* R2 response length long */
+    if (command->responseType == kCARD_ResponseTypeR2)
+    {
+        command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseLengthLong | kSDIF_CmdResponseExpect);
+    }
+    else if ((command->responseType == kCARD_ResponseTypeR3) || (command->responseType == kCARD_ResponseTypeR4))
+    {
+        command->flags |= kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */
+    }
+    else
+    {
+        if (command->responseType != kCARD_ResponseTypeNone)
+        {
+            command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseExpect);
+        }
+    }
+
+    if (command->type == kCARD_CommandTypeAbort)
+    {
+        command->flags |= kSDIF_TransferStopAbort;
+    }
+
+    /* wait pre-transfer complete */
+    command->flags |= kSDIF_WaitPreTransferComplete | kSDIF_CmdDataUseHoldReg;
+
+    return kStatus_Success;
+}
+
+static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *command)
+{
+    /* check if command exsit,if not, do not read the response */
+    if (NULL != command)
+    {
+        /* read reponse */
+        command->response[0U] = base->RESP[0U];
+        if (command->responseType == kCARD_ResponseTypeR2)
+        {
+            command->response[1U] = base->RESP[1U];
+            command->response[2U] = base->RESP[2U];
+            command->response[3U] = base->RESP[3U];
+        }
+
+        if ((command->responseErrorFlags != 0U) &&
+            ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) ||
+             (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5)))
+        {
+            if (((command->responseErrorFlags) & (command->response[0U])) != 0U)
+            {
+                return kStatus_SDIF_ResponseError;
+            }
+        }
+    }
+
+    return kStatus_Success;
+}
+
+static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command)
+{
+    uint32_t status = 0U;
+
+    do
+    {
+        status = SDIF_GetInterruptStatus(base);
+        if ((status &
+             (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != 0u)
+        {
+            SDIF_ClearInterruptStatus(base, status & (kSDIF_ResponseError | kSDIF_ResponseCRCError |
+                                                      kSDIF_ResponseTimeout | kSDIF_HardwareLockError));
+            return kStatus_SDIF_SendCmdFail;
+        }
+    } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone);
+
+    /* clear the command done bit */
+    SDIF_ClearInterruptStatus(base, status & kSDIF_CommandDone);
+
+    return SDIF_ReadCommandResponse(base, command);
+}
+
+status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig)
+{
+    assert(NULL != dmaConfig);
+    assert(NULL != dmaConfig->dmaDesBufferStartAddr);
+
+    sdif_dma_descriptor_t *dmaDesAddr;
+    uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr;
+    uint32_t dmaDesBufferSize = 0U;
+
+    dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+
+    /* chain descriptor mode */
+    if (dmaConfig->mode == kSDIF_ChainDMAMode)
+    {
+        while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorDataBufferEnd) != kSDIF_DMADescriptorDataBufferEnd) &&
+               (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t)))
+        {
+            /* set the OWN bit */
+            dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+            dmaDesAddr++;
+            dmaDesBufferSize += sizeof(sdif_dma_descriptor_t);
+        }
+        /* if access dma des address overflow, return fail */
+        if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t))
+        {
+            return kStatus_Fail;
+        }
+        dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+    }
+    /* dual descriptor mode */
+    else
+    {
+        while (((dmaDesAddr->dmaDesAttribute & kSDIF_DMADescriptorEnd) != kSDIF_DMADescriptorEnd) &&
+               (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t)))
+        {
+            dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+            dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+            tempDMADesBuffer += dmaConfig->dmaDesSkipLen;
+        }
+        /* if access dma des address overflow, return fail */
+        if (dmaDesBufferSize > dmaConfig->dmaDesBufferLen * sizeof(uint32_t))
+        {
+            return kStatus_Fail;
+        }
+        dmaDesAddr->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA;
+    }
+    /* reload DMA descriptor */
+    base->PLDMND = SDIF_POLL_DEMAND_VALUE;
+
+    return kStatus_Success;
+}
+
+static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords)
+{
+    uint32_t i;
+    uint32_t totalWords;
+    uint32_t wordsCanBeRead; /* The words can be read at this time. */
+    uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT);
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */
+    if (readWatermark >= totalWords)
+    {
+        wordsCanBeRead = totalWords;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark,
+    transfers watermark level words. */
+    else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark))
+    {
+        wordsCanBeRead = readWatermark;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left
+    words. */
+    else
+    {
+        wordsCanBeRead = (totalWords - transferredWords);
+    }
+
+    i = 0U;
+    while (i < wordsCanBeRead)
+    {
+        data->rxData[transferredWords++] = base->FIFO[i];
+        i++;
+    }
+
+    return transferredWords;
+}
+
+static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t transferredWords)
+{
+    uint32_t i;
+    uint32_t totalWords;
+    uint32_t wordsCanBeWrite; /* The words can be read at this time. */
+    uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT);
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */
+    if (writeWatermark >= totalWords)
+    {
+        wordsCanBeWrite = totalWords;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is equal or bigger than writeWatermark,
+    transfers watermark level words. */
+    else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark))
+    {
+        wordsCanBeWrite = writeWatermark;
+    }
+    /* If watermark level is less than totalWords and left words to be sent is less than writeWatermark, transfers left
+    words. */
+    else
+    {
+        wordsCanBeWrite = (totalWords - transferredWords);
+    }
+
+    i = 0U;
+    while (i < wordsCanBeWrite)
+    {
+        base->FIFO[i] = data->txData[transferredWords++];
+        i++;
+    }
+
+    return transferredWords;
+}
+
+static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data)
+{
+    uint32_t totalWords;
+    uint32_t transferredWords = 0U;
+    status_t error = kStatus_Success;
+    uint32_t status;
+    bool transferOver = false;
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    while ((transferredWords < totalWords) && (error == kStatus_Success))
+    {
+        /* wait data transfer complete or reach RX watermark */
+        do
+        {
+            status = SDIF_GetInterruptStatus(base);
+            if (status & kSDIF_DataTransferError)
+            {
+                if (!(data->enableIgnoreError))
+                {
+                    error = kStatus_Fail;
+                }
+            }
+        } while (((status & (kSDIF_DataTransferOver | kSDIF_ReadFIFORequest)) == 0U) && (!transferOver));
+
+        if ((status & kSDIF_DataTransferOver) == kSDIF_DataTransferOver)
+        {
+            transferOver = true;
+        }
+
+        if (error == kStatus_Success)
+        {
+            transferredWords = SDIF_ReadDataPort(base, data, transferredWords);
+        }
+
+        /* clear interrupt status */
+        SDIF_ClearInterruptStatus(base, status);
+    }
+
+    return error;
+}
+
+static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data)
+{
+    uint32_t totalWords;
+    uint32_t transferredWords = 0U;
+    status_t error = kStatus_Success;
+    uint32_t status;
+
+    if (data->blockSize % sizeof(uint32_t) != 0U)
+    {
+        data->blockSize +=
+            sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */
+    }
+
+    totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t));
+
+    while ((transferredWords < totalWords) && (error == kStatus_Success))
+    {
+        /* wait data transfer complete or reach RX watermark */
+        do
+        {
+            status = SDIF_GetInterruptStatus(base);
+            if (status & kSDIF_DataTransferError)
+            {
+                if (!(data->enableIgnoreError))
+                {
+                    error = kStatus_Fail;
+                }
+            }
+        } while ((status & kSDIF_WriteFIFORequest) == 0U);
+
+        if (error == kStatus_Success)
+        {
+            transferredWords = SDIF_WriteDataPort(base, data, transferredWords);
+        }
+
+        /* clear interrupt status */
+        SDIF_ClearInterruptStatus(base, status);
+    }
+
+    while ((SDIF_GetInterruptStatus(base) & kSDIF_DataTransferOver) != kSDIF_DataTransferOver)
+    {
+    }
+
+    if (SDIF_GetInterruptStatus(base) & kSDIF_DataTransferError)
+    {
+        if (!(data->enableIgnoreError))
+        {
+            error = kStatus_Fail;
+        }
+    }
+    SDIF_ClearInterruptStatus(base, (kSDIF_DataTransferOver | kSDIF_DataTransferError));
+
+    return error;
+}
+
+bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout)
+{
+    base->CTRL |= mask;
+
+    /* check software DMA reset here for DMA reset also need to check this bit */
+    while ((base->CTRL & mask) != 0U)
+    {
+        if (!timeout)
+        {
+            break;
+        }
+        timeout--;
+    }
+
+    return timeout ? true : false;
+}
+
+static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA)
+{
+    assert(NULL != data);
+
+    uint32_t dmaStatus = 0U;
+    status_t error = kStatus_Success;
+
+    /* in DMA mode, only need to wait the complete flag and check error */
+    if (isDMA)
+    {
+        do
+        {
+            dmaStatus = SDIF_GetInternalDMAStatus(base);
+            if ((dmaStatus & kSDIF_DMAFatalBusError) == kSDIF_DMAFatalBusError)
+            {
+                SDIF_ClearInternalDMAStatus(base, kSDIF_DMAFatalBusError | kSDIF_AbnormalInterruptSummary);
+                error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */
+            }
+            /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */
+            if ((dmaStatus & kSDIF_DMACardErrorSummary) == kSDIF_DMACardErrorSummary)
+            {
+                SDIF_ClearInternalDMAStatus(base, kSDIF_DMACardErrorSummary | kSDIF_AbnormalInterruptSummary);
+                if (!(data->enableIgnoreError))
+                {
+                    error = kStatus_SDIF_DataTransferFail;
+                }
+
+                /* if error occur, then return */
+                break;
+            }
+        } while ((dmaStatus & (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor)) == 0U);
+
+        /* clear the corresponding status bit */
+        SDIF_ClearInternalDMAStatus(base, (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor |
+                                           kSDIF_NormalInterruptSummary));
+
+        SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base));
+    }
+    else
+    {
+        if (data->rxData != NULL)
+        {
+            error = SDIF_ReadDataPortBlocking(base, data);
+        }
+        else
+        {
+            error = SDIF_WriteDataPortBlocking(base, data);
+        }
+    }
+
+    return error;
+}
+
+status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout)
+{
+    assert(NULL != cmd);
+
+    base->CMDARG = cmd->argument;
+    base->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK));
+
+    /* wait start_cmd bit auto clear within timeout */
+    while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK)
+    {
+        if (!timeout)
+        {
+            break;
+        }
+
+        --timeout;
+    }
+
+    return timeout ? kStatus_Success : kStatus_Fail;
+}
+
+bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout)
+{
+    bool enINT = false;
+    sdif_command_t command;
+
+    memset(&command, 0U, sizeof(sdif_command_t));
+
+    /* add for confict with interrupt mode,close the interrupt temporary */
+    if ((base->CTRL & SDIF_CTRL_INT_ENABLE_MASK) == SDIF_CTRL_INT_ENABLE_MASK)
+    {
+        enINT = true;
+        base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK;
+    }
+
+    command.flags = SDIF_CMD_SEND_INITIALIZATION_MASK;
+
+    if (SDIF_SendCommand(base, &command, timeout) == kStatus_Fail)
+    {
+        return false;
+    }
+
+    /* wait command done */
+    while ((SDIF_GetInterruptStatus(base) & kSDIF_CommandDone) != kSDIF_CommandDone)
+    {
+    }
+
+    /* clear status */
+    SDIF_ClearInterruptStatus(base, kSDIF_CommandDone);
+
+    /* add for confict with interrupt mode */
+    if (enINT)
+    {
+        base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK;
+    }
+
+    return true;
+}
+
+void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider)
+{
+    /*config the clock delay and pharse shift
+     *should config the clk_in_drv,
+     *clk_in_sample to meet the min hold and
+     *setup time
+     */
+    if (target_HZ <= kSDIF_Freq400KHZ)
+    {
+        /*min hold time:5ns
+        * min setup time: 5ns
+        * delay = (x+1)*250ps
+        */
+        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY) |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_INDENTIFICATION_MODE_DRV_DELAY);
+    }
+    else if (target_HZ >= kSDIF_Freq50MHZ)
+    {
+        /*
+        * user need to pay attention to this parameter
+        * can be change the setting for you card and board
+        * min hold time:2ns
+        * min setup time: 6ns
+        * delay = (x+1)*250ps
+        */
+        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY) |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_50MHZ_DRV_DELAY);
+        /* means the input clock = 2 * card clock,
+        * can use clock pharse shift tech
+        */
+        if (divider == 1U)
+        {
+            SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
+                                   SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
+                                   SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift180);
+        }
+    }
+    else
+    {
+        /*
+        * user need to pay attention to this parameter
+        * can be change the setting for you card and board
+        * min hold time:5ns
+        * min setup time: 5ns
+        * delay = (x+1)*250ps
+        */
+        SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY) |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
+                              SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_25MHZ_DRV_DELAY);
+        /* means the input clock = 2 * card clock,
+        * can use clock pharse shift tech
+        */
+        if (divider == 1U)
+        {
+            SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
+                                   SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
+                                   SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift90);
+        }
+    }
+}
+
+uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ)
+{
+    assert(srcClock_Hz <= FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK);
+
+    sdif_command_t cmd = {0U};
+    uint32_t divider = 0U, targetFreq = target_HZ;
+
+    /* if target freq bigger than the source clk, set the target_HZ to
+     src clk, this interface can run up to 52MHZ with card */
+    if (srcClock_Hz < targetFreq)
+    {
+        targetFreq = srcClock_Hz;
+    }
+
+    /* disable the clock first,need sync to CIU*/
+    SDIF_EnableCardClock(base, false);
+
+    /* update the clock register and wait the pre-transfer complete */
+    cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete;
+    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
+
+    /*calucate the divider*/
+    if (targetFreq != srcClock_Hz)
+    {
+        divider = (srcClock_Hz / targetFreq + 1U) / 2U;
+    }
+    /* load the clock divider */
+    base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider);
+
+    /* update the divider to CIU */
+    cmd.flags = kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete;
+    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
+
+    /* enable the card clock and sync to CIU */
+    SDIF_EnableCardClock(base, true);
+    SDIF_SendCommand(base, &cmd, SDIF_TIMEOUT_VALUE);
+
+    /* config the clock delay to meet the hold time and setup time */
+    SDIF_ConfigClockDelay(target_HZ, divider);
+
+    /* return the actual card clock freq */
+
+    return (divider != 0U) ? (srcClock_Hz / (divider * 2U)) : srcClock_Hz;
+}
+
+bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout)
+{
+    /* assert this bit to reset the data machine to abort the read data */
+    base->CTRL |= SDIF_CTRL_ABORT_READ_DATA_MASK;
+    /* polling the bit self clear */
+    while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK)
+    {
+        if (!timeout)
+        {
+            break;
+        }
+        timeout--;
+    }
+
+    return base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK ? false : true;
+}
+
+status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize)
+{
+    assert(NULL != config);
+    assert(NULL != data);
+
+    uint32_t dmaEntry = 0U, i, dmaBufferSize = 0U, dmaBuffer1Size = 0U;
+    uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr;
+    const uint32_t *dataBuffer = data;
+    sdif_dma_descriptor_t *descriptorPoniter = NULL;
+    uint32_t maxDMABuffer = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * (config->mode);
+
+    /* check the dma descriptor buffer length , it is user's responsibility to make sure the DMA descriptor table
+    size is bigger enough to hold the transfer descriptor */
+    if (config->dmaDesBufferLen * sizeof(uint32_t) < sizeof(sdif_dma_descriptor_t))
+    {
+        return kStatus_SDIF_DescriptorBufferLenError;
+    }
+
+    /* check the read/write data size,must be a multiple of 4 */
+    if (dataSize % sizeof(uint32_t) != 0U)
+    {
+        dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t));
+    }
+
+    /*config the bus mode*/
+    if (config->enableFixBurstLen)
+    {
+        base->BMOD |= SDIF_BMOD_FB_MASK;
+    }
+
+    /* calucate the dma descriptor entry due to DMA buffer size limit */
+    /* if datasize smaller than one descriptor buffer size */
+    if (dataSize > maxDMABuffer)
+    {
+        dmaEntry = dataSize / maxDMABuffer + (dataSize % maxDMABuffer ? 1U : 0U);
+    }
+    else /* need one dma descriptor */
+    {
+        dmaEntry = 1U;
+    }
+
+    /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor
+    table
+    size is bigger enough to hold the transfer descriptor */
+    if (config->dmaDesBufferLen * sizeof(uint32_t) < (dmaEntry * sizeof(sdif_dma_descriptor_t) + config->dmaDesSkipLen))
+    {
+        return kStatus_SDIF_DescriptorBufferLenError;
+    }
+
+    switch (config->mode)
+    {
+        case kSDIF_DualDMAMode:
+            base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */
+            for (i = 0U; i < dmaEntry; i++)
+            {
+                if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE)
+                {
+                    dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
+                    dataSize -= dmaBufferSize;
+                    dmaBuffer1Size = dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ?
+                                         FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE :
+                                         dataSize;
+                    dataSize -= dmaBuffer1Size;
+                }
+                else
+                {
+                    dmaBufferSize = dataSize;
+                    dmaBuffer1Size = 0U;
+                }
+
+                descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+                if (i == 0U)
+                {
+                    descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart;
+                }
+                descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorOwnByDMA | kSDIF_DisableCompleteInterrupt;
+                descriptorPoniter->dmaDataBufferSize =
+                    SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size);
+
+                descriptorPoniter->dmaDataBufferAddr0 = dataBuffer;
+                descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t);
+                dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t);
+
+                /* descriptor skip length */
+                tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t);
+            }
+            /* enable the completion interrupt when reach the last descriptor */
+            descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt;
+            descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd | kSDIF_DMADescriptorEnd;
+            break;
+
+        case kSDIF_ChainDMAMode:
+            for (i = 0U; i < dmaEntry; i++)
+            {
+                if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE)
+                {
+                    dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
+                    dataSize -= FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE;
+                }
+                else
+                {
+                    dmaBufferSize = dataSize;
+                }
+
+                descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer;
+                if (i == 0U)
+                {
+                    descriptorPoniter->dmaDesAttribute = kSDIF_DMADescriptorDataBufferStart;
+                }
+                descriptorPoniter->dmaDesAttribute |=
+                    kSDIF_DMADescriptorOwnByDMA | kSDIF_DMASecondAddrChained | kSDIF_DisableCompleteInterrupt;
+                descriptorPoniter->dmaDataBufferSize =
+                    SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/
+                descriptorPoniter->dmaDataBufferAddr0 = dataBuffer;
+                dataBuffer += dmaBufferSize / sizeof(uint32_t);
+                tempDMADesBuffer +=
+                    sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calucate the next descriptor address */
+                /* this descriptor buffer2 pointer to the next descriptor address */
+                descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer;
+            }
+            /* enable the completion interrupt when reach the last descriptor */
+            descriptorPoniter->dmaDesAttribute &= ~kSDIF_DisableCompleteInterrupt;
+            descriptorPoniter->dmaDesAttribute |= kSDIF_DMADescriptorDataBufferEnd;
+            break;
+
+        default:
+            break;
+    }
+
+    /* use internal DMA interface */
+    base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK;
+    /* enable the internal SD/MMC DMA */
+    base->BMOD |= SDIF_BMOD_DE_MASK;
+    /* enable DMA status check */
+    base->IDINTEN |= kSDIF_DMAAllStatus;
+    /* clear write/read FIFO request interrupt in DMA mode, DMA will handle the data transfer*/
+    SDIF_DisableInterrupt(base, kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | kSDIF_DataTransferOver);
+    /* load DMA descriptor buffer address */
+    base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr;
+
+    return kStatus_Success;
+}
+
+void SDIF_Init(SDIF_Type *base, sdif_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t timeout;
+
+    /* enable SDIF clock */
+    CLOCK_EnableClock(kCLOCK_Sdio);
+
+    /* do software reset */
+    base->BMOD |= SDIF_BMOD_SWR_MASK;
+
+    /* reset all */
+    SDIF_Reset(base, kSDIF_ResetAll, SDIF_TIMEOUT_VALUE);
+
+    /*config timeout register */
+    timeout = base->TMOUT;
+    timeout &= ~(SDIF_TMOUT_RESPONSE_TIMEOUT_MASK | SDIF_TMOUT_DATA_TIMEOUT_MASK);
+    timeout |= SDIF_TMOUT_RESPONSE_TIMEOUT(config->responseTimeout) | SDIF_TMOUT_DATA_TIMEOUT(config->dataTimeout);
+
+    base->TMOUT = timeout;
+
+    /* config the card detect debounce clock count */
+    base->DEBNCE = SDIF_DEBNCE_DEBOUNCE_COUNT(config->cardDetDebounce_Clock);
+
+    /*config the watermark/burst transfer value */
+    base->FIFOTH =
+        SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U);
+
+    /* enable the interrupt status  */
+    SDIF_EnableInterrupt(base, kSDIF_AllInterruptStatus);
+
+    /* clear all interrupt/DMA status */
+    SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus);
+    SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus);
+}
+
+status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer)
+{
+    assert(NULL != transfer);
+
+    bool isDMA = false;
+    sdif_data_t *data = transfer->data;
+
+    /* config the transfer parameter */
+    if (SDIF_TransferConfig(base, transfer) != kStatus_Success)
+    {
+        return kStatue_SDIF_InvalidArgument;
+    }
+
+    /* if need transfer data in dma mode, config the DMA descriptor first */
+    if ((data != NULL) && (dmaConfig != NULL))
+    {
+        /* use internal DMA mode to transfer between the card and host*/
+        isDMA = true;
+
+        if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData,
+                                   data->blockSize * data->blockCount) != kStatus_Success)
+        {
+            return kStatus_SDIF_DescriptorBufferLenError;
+        }
+    }
+
+    /* send command first */
+    if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success)
+    {
+        return kStatus_SDIF_SyncCmdTimeout;
+    }
+
+    /* wait the command transfer done and check if error occurs */
+    if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success)
+    {
+        return kStatus_SDIF_SendCmdFail;
+    }
+
+    /* if use DMA transfer mode ,check the corresponding status bit */
+    if (data != NULL)
+    {
+        /* check the if has DMA descriptor featch error */
+        if (isDMA &&
+            ((SDIF_GetInternalDMAStatus(base) & kSDIF_DMADescriptorUnavailable) == kSDIF_DMADescriptorUnavailable))
+        {
+            SDIF_ClearInternalDMAStatus(base, kSDIF_DMADescriptorUnavailable | kSDIF_AbnormalInterruptSummary);
+
+            /* release the DMA descriptor to DMA */
+            SDIF_ReleaseDMADescriptor(base, dmaConfig);
+        }
+        /* handle data transfer */
+        if (SDIF_TransferDataBlocking(base, data, isDMA) != kStatus_Success)
+        {
+            return kStatus_SDIF_DataTransferFail;
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t SDIF_TransferNonBlocking(SDIF_Type *base,
+                                  sdif_handle_t *handle,
+                                  sdif_dma_config_t *dmaConfig,
+                                  sdif_transfer_t *transfer)
+{
+    assert(NULL != transfer);
+
+    sdif_data_t *data = transfer->data;
+
+    /* save the data and command before transfer */
+    handle->data = transfer->data;
+    handle->command = transfer->command;
+    handle->transferredWords = 0U;
+    handle->interruptFlags = 0U;
+    handle->dmaInterruptFlags = 0U;
+
+    /* config the transfer parameter */
+    if (SDIF_TransferConfig(base, transfer) != kStatus_Success)
+    {
+        return kStatue_SDIF_InvalidArgument;
+    }
+
+    if ((data != NULL) && (dmaConfig != NULL))
+    {
+        /* use internal DMA mode to transfer between the card and host*/
+        if (SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData,
+                                   data->blockSize * data->blockCount) != kStatus_Success)
+        {
+            return kStatus_SDIF_DescriptorBufferLenError;
+        }
+    }
+
+    /* send command first */
+    if (SDIF_SendCommand(base, transfer->command, SDIF_TIMEOUT_VALUE) != kStatus_Success)
+    {
+        return kStatus_SDIF_SyncCmdTimeout;
+    }
+
+    return kStatus_Success;
+}
+
+void SDIF_TransferCreateHandle(SDIF_Type *base,
+                               sdif_handle_t *handle,
+                               sdif_transfer_callback_t *callback,
+                               void *userData)
+{
+    assert(handle);
+    assert(callback);
+
+    /* reset the handle. */
+    memset(handle, 0U, sizeof(*handle));
+
+    /* Set the callback. */
+    handle->callback.SDIOInterrupt = callback->SDIOInterrupt;
+    handle->callback.DMADesUnavailable = callback->DMADesUnavailable;
+    handle->callback.CommandReload = callback->CommandReload;
+    handle->callback.TransferComplete = callback->TransferComplete;
+
+    handle->userData = userData;
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_sdifHandle[SDIF_GetInstance(base)] = handle;
+
+    /* save IRQ handler */
+    s_sdifIsr = SDIF_TransferHandleIRQ;
+
+    /* enable the global interrupt */
+    SDIF_EnableGlobalInterrupt(base, true);
+
+    EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]);
+}
+
+void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability)
+{
+    assert(NULL != capability);
+
+    capability->sdVersion = SDIF_SUPPORT_SD_VERSION;
+    capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION;
+    capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK;
+    /* set the max block count = max byte conut / max block size */
+    capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK;
+    capability->flags = kSDIF_SupportHighSpeedFlag | kSDIF_SupportDmaFlag | kSDIF_SupportSuspendResumeFlag |
+                        kSDIF_SupportV330Flag | kSDIF_Support4BitFlag | kSDIF_Support8BitFlag;
+}
+
+static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
+{
+    assert(handle->command);
+
+    /* transfer error */
+    if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout))
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData);
+    }
+    /* cmd buffer full, in this condition user need re-send the command */
+    else if (interruptFlags & kSDIF_HardwareLockError)
+    {
+        if (handle->callback.CommandReload)
+        {
+            handle->callback.CommandReload();
+        }
+    }
+    /* transfer command success */
+    else
+    {
+        SDIF_ReadCommandResponse(base, handle->command);
+        if (((handle->data) == NULL) && (handle->callback.TransferComplete))
+        {
+            handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+        }
+    }
+}
+
+static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
+{
+    assert(handle->data);
+
+    /* data starvation by host time out, software should read/write FIFO*/
+    if (interruptFlags & kSDIF_DataStarvationByHostTimeout)
+    {
+        if (handle->data->rxData != NULL)
+        {
+            handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
+        }
+        else if (handle->data->txData != NULL)
+        {
+            handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords);
+        }
+        else
+        {
+            handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
+        }
+    }
+    /* data transfer fail */
+    else if (interruptFlags & kSDIF_DataTransferError)
+    {
+        if (!handle->data->enableIgnoreError)
+        {
+            handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
+        }
+    }
+    /* need fill data to FIFO */
+    else if (interruptFlags & kSDIF_WriteFIFORequest)
+    {
+        handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords);
+    }
+    /* need read data from FIFO */
+    else if (interruptFlags & kSDIF_ReadFIFORequest)
+    {
+        handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
+    }
+    else
+    {
+    }
+
+    /* data transfer over */
+    if (interruptFlags & kSDIF_DataTransferOver)
+    {
+        while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0U))
+        {
+            handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords);
+        }
+        handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+    }
+}
+
+static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags)
+{
+    if (interruptFlags & kSDIF_DMAFatalBusError)
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_SDIF_DMATransferFailWithFBE, handle->userData);
+    }
+    else if (interruptFlags & kSDIF_DMADescriptorUnavailable)
+    {
+        if (handle->callback.DMADesUnavailable)
+        {
+            handle->callback.DMADesUnavailable();
+        }
+    }
+    else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) &&
+             (!handle->data->enableIgnoreError))
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData);
+    }
+    /* card normal summary */
+    else
+    {
+        handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+    }
+}
+
+static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle)
+{
+    if (handle->callback.SDIOInterrupt != NULL)
+    {
+        handle->callback.SDIOInterrupt();
+    }
+}
+
+static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle)
+{
+    assert(handle);
+
+    uint32_t interruptFlags, dmaInterruptFlags;
+
+    interruptFlags = SDIF_GetInterruptStatus(base);
+    dmaInterruptFlags = SDIF_GetInternalDMAStatus(base);
+
+    handle->interruptFlags = interruptFlags;
+    handle->dmaInterruptFlags = dmaInterruptFlags;
+
+    if ((interruptFlags & kSDIF_CommandTransferStatus) != 0U)
+    {
+        SDIF_TransferHandleCommand(base, handle, (interruptFlags & kSDIF_CommandTransferStatus));
+    }
+    if ((interruptFlags & kSDIF_DataTransferStatus) != 0U)
+    {
+        SDIF_TransferHandleData(base, handle, (interruptFlags & kSDIF_DataTransferStatus));
+    }
+    if (interruptFlags & kSDIF_SDIOInterrupt)
+    {
+        SDIF_TransferHandleSDIOInterrupt(handle);
+    }
+    if (dmaInterruptFlags & kSDIF_DMAAllStatus)
+    {
+        SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags);
+    }
+
+    SDIF_ClearInterruptStatus(base, interruptFlags);
+    SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags);
+}
+
+void SDIF_Deinit(SDIF_Type *base)
+{
+    /* disable clock here*/
+    CLOCK_DisableClock(kCLOCK_Sdio);
+    /* disable the SDIOCLKCTRL */
+    SYSCON->SDIOCLKCTRL &= ~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+                             SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK);
+    RESET_PeripheralReset(kSDIO_RST_SHIFT_RSTn);
+}
+
+#if defined(SDIF)
+void SDIF_DriverIRQHandler(void)
+{
+    assert(s_sdifHandle[0]);
+
+    s_sdifIsr(SDIF, s_sdifHandle[0]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,824 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SDIF_H_
+#define _FSL_SDIF_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sdif
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.1. */
+#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*@}*/
+
+#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler /*!< convert the name here, due to RM use SDIO */
+
+#define SDIF_SUPPORT_SD_VERSION (0x20)  /*!< define the controller support sd/sdio card version 2.0 */
+#define SDIF_SUPPORT_MMC_VERSION (0x44) /*!< define the controller support mmc card version 4.4 */
+
+#define SDIF_TIMEOUT_VALUE (65535U)    /*!< define the timeout counter */
+#define SDIF_POLL_DEMAND_VALUE (0xFFU) /*!< this value can be any value */
+
+#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU)          /*!< DMA descriptor buffer1 size */
+#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U) /*!<DMA descriptor buffer2 size */
+#define SDIF_RX_WATERMARK (15U)                                    /*!<RX water mark value */
+#define SDIF_TX_WATERMARK (16U)                                    /*!<TX water mark value */
+
+/*! @brief  SDIOCLKCTRL setting
+* below clock delay setting should meet you board layout
+* user can change it when you meet timing mismatch issue
+* such as: response error/CRC error and so on
+*/
+#define SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY (0X17U)
+#define SDIF_INDENTIFICATION_MODE_DRV_DELAY (0X17U)
+#define SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY (0x10U)
+#define SDIF_HIGHSPEED_25MHZ_DRV_DELAY (0x10U)
+#define SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY (0x1FU)
+#define SDIF_HIGHSPEED_50MHZ_DRV_DELAY (0x1FU)
+
+/*! @brief SDIF status */
+enum _sdif_status
+{
+    kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */
+    kStatue_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U),          /*!< invalid argument status */
+    kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */
+    kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U),    /* send command to card fail */
+    kStatus_SDIF_SendCmdErrorBufferFull =
+        MAKE_STATUS(kStatusGroup_SDIF, 4U), /* send command to card fail, due to command buffer full
+                                     user need to resend this command */
+    kStatus_SDIF_DMATransferFailWithFBE =
+        MAKE_STATUS(kStatusGroup_SDIF, 5U), /* DMA transfer data fail with fatal bus error ,
+                                     to do with this error :issue a hard reset/controller reset*/
+    kStatus_SDIF_DMATransferDescriptorUnavaliable = MAKE_STATUS(kStatusGroup_SDIF, 6U), /* DMA descriptor unavalible */
+    kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U),                 /* transfer data fail */
+    kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U),
+};
+
+/*! @brief Host controller capabilities flag mask */
+enum _sdif_capability_flag
+{
+    kSDIF_SupportHighSpeedFlag = 0x1U,     /*!< Support high-speed */
+    kSDIF_SupportDmaFlag = 0x2U,           /*!< Support DMA */
+    kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */
+    kSDIF_SupportV330Flag = 0x8U,          /*!< Support voltage 3.3V */
+    kSDIF_Support4BitFlag = 0x10U,         /*!< Support 4 bit mode */
+    kSDIF_Support8BitFlag = 0x20U,         /*!< Support 8 bit mode */
+};
+
+/*! @brief define the reset type */
+enum _sdif_reset_type
+{
+    kSDIF_ResetController =
+        SDIF_CTRL_CONTROLLER_RESET_MASK,                /*!< reset controller,will reset: BIU/CIU interface
+                                                          CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE
+                                                          and READ_WAIT bits of control register,START_CMD bit of the
+                                                          command register*/
+    kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK,        /*!< reset data FIFO*/
+    kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */
+
+    kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/
+                     kSDIF_ResetDMAInterface,
+};
+
+/*! @brief define the card bus width type */
+typedef enum _sdif_bus_width
+{
+    kSDIF_Bus1BitWidth = 0U,                          /*!< 1bit bus width, 1bit mode and 4bit mode
+                                                      share one register bit */
+    kSDIF_Bus4BitWidth = SDIF_CTYPE_CARD_WIDTH0_MASK, /*!< 4bit mode mask */
+    kSDIF_Bus8BitWidth = SDIF_CTYPE_CARD_WIDTH1_MASK, /*!< support 8 bit mode */
+} sdif_bus_width_t;
+
+/*! @brief define the command flags */
+enum _sdif_command_flags
+{
+    kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK,      /*!< command request response*/
+    kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK,  /*!< command response length long */
+    kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/
+    kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK,               /*!< request data transfer,ethier read/write*/
+    kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK,             /*!< data transfer direction */
+    kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK,    /*!< data transfer mode :stream/block transfer command */
+    kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */
+    kSDIF_WaitPreTransferComplete =
+        SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd  */
+    kSDIF_TransferStopAbort =
+        SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer
+                                       ,this bit should set so that cmd/data state-machines of CIU can return
+                                       to idle correctly*/
+    kSDIF_SendInitialization =
+        SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initaliztion  80 clocks for SD card after power on  */
+    kSDIF_CmdUpdateClockRegisterOnly =
+        SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK,                /*!< send cmd update the CIU clock register only */
+    kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */
+    kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK,         /*!< command expect command completion signal signal */
+    kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK,        /*!< this bit should only be set for mandatory boot mode */
+    kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */
+    kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK,      /*!< when software set this bit along with START_CMD, CIU
+                                                                terminates the boot operation*/
+    kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK,       /*!< select boot mode ,alternate or mandatory*/
+    kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK,      /*!< this bit set for CMD11 only */
+    kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK,    /*!< cmd and data send to card through the HOLD register*/
+};
+
+/*! @brief The command type */
+enum _sdif_command_type
+{
+    kCARD_CommandTypeNormal = 0U,  /*!< Normal command */
+    kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
+    kCARD_CommandTypeResume = 2U,  /*!< Resume command */
+    kCARD_CommandTypeAbort = 3U,   /*!< Abort command */
+};
+
+/*!
+ * @brief The command response type.
+ *
+ * Define the command response type from card to host controller.
+ */
+enum _sdif_response_type
+{
+    kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
+    kCARD_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
+    kCARD_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
+    kCARD_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
+    kCARD_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
+    kCARD_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
+    kCARD_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
+    kCARD_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
+    kCARD_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
+    kCARD_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
+};
+
+/*! @brief define the interrupt mask flags */
+enum _sdif_interrupt_mask
+{
+    kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK,                 /*!< mask for card detect */
+    kSDIF_ResponseError = SDIF_INTMASK_RE_MASK,                /*!< command response error */
+    kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK,               /*!< command transfer over*/
+    kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK,            /*!< data transfer over flag*/
+    kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK,           /*!< write FIFO request */
+    kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK,            /*!< read FIFO request */
+    kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK,           /*!< reponse CRC error */
+    kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK,               /*!< data CRC error */
+    kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK,             /*!< response timeout */
+    kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK,            /*!< read data timeout */
+    kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */
+    kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK,                  /*!< indicate the FIFO underrun or overrun error */
+    kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK,           /*!< hardware lock write error */
+    kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK,           /*!< start bit error */
+    kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK,                 /*!< indicate the auto command done */
+    kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK,             /*!< end bit error */
+    kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK,     /*!< interrupt from the SDIO card */
+
+    kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError |
+                                  kSDIF_ResponseTimeout |
+                                  kSDIF_HardwareLockError, /*!< command transfer status collection*/
+    kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest |
+                               kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout |
+                               kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError |
+                               kSDIF_AutoCmdDone, /*!< data transfer status collection */
+    kSDIF_DataTransferError =
+        kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout,
+    kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */
+
+};
+
+/*! @brief define the internal DMA status flags */
+enum _sdif_dma_status
+{
+    kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */
+    kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK,  /*!< DMA revieve finished for one DMA descriptor */
+    kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK,           /*!< DMA fatal bus error */
+    kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK,    /*!< DMA descriptor unavailable */
+    kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK,        /*!< card error summary */
+    kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK,     /*!< normal interrupt summary */
+    kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK,   /*!< abnormal interrupt summary*/
+
+    kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError |
+                         kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary |
+                         kSDIF_AbnormalInterruptSummary,
+
+};
+
+/*! @brief define the internal DMA descriptor flag */
+enum _sdif_dma_descriptor_flag
+{
+    kSDIF_DisableCompleteInterrupt = 0x2U,     /*!< disable the complete interrupt flag for the ends
+                                                in the buffer pointed to by this descriptor*/
+    kSDIF_DMADescriptorDataBufferEnd = 0x4U,   /*!< indicate this descriptor contain the last data buffer of data */
+    kSDIF_DMADescriptorDataBufferStart = 0x8U, /*!< indicate this descriptor contain the first data buffer
+                                                 of data,if first buffer size is 0,next descriptor contain
+                                                 the begaining of the data*/
+    kSDIF_DMASecondAddrChained = 0x10U,        /*!< indicate that the second addr in the descriptor is the
+                                               next descriptor addr not the data buffer */
+    kSDIF_DMADescriptorEnd = 0x20U,            /*!< indicate that the descriptor list reached its final descriptor*/
+    kSDIF_DMADescriptorOwnByDMA = 0x80000000U, /*!< indicate the descriptor is own by SD/MMC DMA */
+};
+
+/*! @brief define the internal DMA mode */
+typedef enum _sdif_dma_mode
+{
+    kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */
+    kSDIF_DualDMAMode = 0x02U,  /* dual mode is one descriptor with two buffer */
+} sdif_dma_mode_t;
+
+/*! @brief define the card work freq mode */
+enum _sdif_card_freq
+{
+    kSDIF_Freq50MHZ = 50000000U, /*!< 50MHZ mode*/
+    kSDIF_Freq400KHZ = 400000U,  /*!< identificatioin mode*/
+};
+
+/*! @brief define the clock pharse shift */
+enum _sdif_clock_pharse_shift
+{
+    kSDIF_ClcokPharseShift0,   /*!< clock pharse shift 0*/
+    kSDIF_ClcokPharseShift90,  /*!< clock pharse shift 90*/
+    kSDIF_ClcokPharseShift180, /*!< clock pharse shift 180*/
+    kSDIF_ClcokPharseShift270, /*!< clock pharse shift 270*/
+};
+
+/*! @brief define the internal DMA descriptor */
+typedef struct _sdif_dma_descriptor
+{
+    uint32_t dmaDesAttribute;           /*!< internal DMA attribute control and status */
+    uint32_t dmaDataBufferSize;         /*!< internal DMA transfer buffer size control */
+    const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */
+    const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */
+
+} sdif_dma_descriptor_t;
+
+/*! @brief Defines the internal DMA config structure. */
+typedef struct _sdif_dma_config
+{
+    bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will
+                             use only SINGLE, INCR4, INCR8 or INCR16 during start of
+                             normal burst transfers. When reset, the AHB will use SINGLE
+                             and INCR burst transfer operations */
+
+    sdif_dma_mode_t mode; /*!< define the DMA mode */
+
+    uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor
+                               this field is special for dual DMA mode */
+
+    uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/
+    uint32_t dmaDesBufferLen;        /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the
+                                        dma descriptor buffer length if it is bigger enough for your transfer */
+
+} sdif_dma_config_t;
+
+/*!
+ * @brief Card data descriptor
+ */
+typedef struct _sdif_data
+{
+    bool streamTransfer;      /*!< indicate this is a stream data transfer command */
+    bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */
+    bool enableIgnoreError;   /*!< indicate if enable ignore error when transfer data */
+
+    size_t blockSize;       /*!< Block size, take care when config this parameter */
+    uint32_t blockCount;    /*!< Block count */
+    uint32_t *rxData;       /*!< data buffer to recieve */
+    const uint32_t *txData; /*!< data buffer to transfer */
+} sdif_data_t;
+
+/*!
+ * @brief Card command descriptor
+ *
+ * Define card command-related attribute.
+ */
+typedef struct _sdif_command
+{
+    uint32_t index;              /*!< Command index */
+    uint32_t argument;           /*!< Command argument */
+    uint32_t response[4U];       /*!< Response for this command */
+    uint32_t type;               /*!< define the command type */
+    uint32_t responseType;       /*!< Command response type */
+    uint32_t flags;              /*!< Cmd flags */
+    uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when
+                                    recieve the cmd response */
+} sdif_command_t;
+
+/*! @brief Transfer state */
+typedef struct _sdif_transfer
+{
+    sdif_data_t *data;       /*!< Data to transfer */
+    sdif_command_t *command; /*!< Command to send */
+} sdif_transfer_t;
+
+/*! @brief Data structure to initialize the sdif */
+typedef struct _sdif_config
+{
+    uint8_t responseTimeout;        /*!< command reponse timeout value */
+    uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in
+                                        card detect logic,typical value is 5-25ms */
+    uint32_t endianMode;            /*!< define endian mode ,this field is not used in this
+                                    module actually, keep for compatible with middleware*/
+    uint32_t dataTimeout;           /*!< data timeout value  */
+} sdif_config_t;
+
+/*!
+ * @brief SDIF capability information.
+ * Defines a structure to get the capability information of SDIF.
+ */
+typedef struct _sdif_capability
+{
+    uint32_t sdVersion;      /*!< support SD card/sdio version */
+    uint32_t mmcVersion;     /*!< support emmc card version */
+    uint32_t maxBlockLength; /*!< Maximum block length united as byte */
+    uint32_t maxBlockCount;  /*!< Maximum byte count can be transfered */
+    uint32_t flags;          /*!< Capability flags to indicate the support information */
+} sdif_capability_t;
+
+/*! @brief sdif callback functions. */
+typedef struct _sdif_transfer_callback
+{
+    void (*SDIOInterrupt)(void);     /*!< SDIO card interrupt occurs */
+    void (*DMADesUnavailable)(void); /*!< DMA descriptor unavailable */
+    void (*CommandReload)(void);     /*!< command buffer full,need re-load */
+    void (*TransferComplete)(SDIF_Type *base,
+                             void *handle,
+                             status_t status,
+                             void *userData); /*!< Transfer complete callback */
+} sdif_transfer_callback_t;
+
+/*!
+ * @brief sdif handle
+ *
+ * Defines the structure to save the sdif state information and callback function. The detail interrupt status when
+ * send command or transfer data can be obtained from interruptFlags field by using mask defined in
+ * sdif_interrupt_flag_t;
+ * @note All the fields except interruptFlags and transferredWords must be allocated by the user.
+ */
+typedef struct _sdif_handle
+{
+    /* Transfer parameter */
+    sdif_data_t *volatile data;       /*!< Data to transfer */
+    sdif_command_t *volatile command; /*!< Command to send */
+
+    /* Transfer status */
+    volatile uint32_t interruptFlags;    /*!< Interrupt flags of last transaction */
+    volatile uint32_t dmaInterruptFlags; /*!< DMA interrupt flags of last transaction*/
+    volatile uint32_t transferredWords;  /*!< Words transferred by polling way */
+
+    /* Callback functions */
+    sdif_transfer_callback_t callback; /*!< Callback function */
+    void *userData;                    /*!< Parameter for transfer complete callback */
+} sdif_handle_t;
+
+/*! @brief sdif transfer function. */
+typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content);
+
+/*! @brief sdif host descriptor */
+typedef struct _sdif_host
+{
+    SDIF_Type *base;                   /*!< sdif peripheral base address */
+    uint32_t sourceClock_Hz;           /*!< sdif source clock frequency united in Hz */
+    sdif_config_t config;              /*!< sdif configuration */
+    sdif_transfer_function_t transfer; /*!< sdif transfer function */
+    sdif_capability_t capability;      /*!< sdif capability information */
+} sdif_host_t;
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief SDIF module initialization function.
+ *
+ * Configures the SDIF according to the user configuration.
+ * @param base SDIF peripheral base address.
+ * @param config SDIF configuration information.
+ */
+void SDIF_Init(SDIF_Type *base, sdif_config_t *config);
+
+/*!
+ * @brief SDIF module deinit function.
+ * user should call this function follow with IP reset
+ * @param base SDIF peripheral base address.
+ */
+void SDIF_Deinit(SDIF_Type *base);
+
+/*!
+ * @brief SDIF send initialize 80 clocks for SD card after initilize
+ * @param base SDIF peripheral base address.
+ * @param timeout value
+ */
+bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout);
+
+/*!
+ * @brief SDIF module detect card insert status function.
+ * @param base SDIF peripheral base address.
+ * @param data3 indicate use data3 as card insert detect pin
+ * will return the data3 PIN status in this condition
+ */
+static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3)
+{
+    if (data3)
+    {
+        return base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK;
+    }
+    else
+    {
+        return base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF module enable/disable card clock.
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK;
+    }
+    else
+    {
+        base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF module enable/disable module disable the card clock
+ * to enter low power mode when card is idle,for SDIF cards, if
+ * interrupts must be detected, clock should not be stopped
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK;
+    }
+    else
+    {
+        base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK;
+    }
+}
+
+/*!
+ * @brief Sets the card bus clock frequency.
+ *
+ * @param base SDIF peripheral base address.
+ * @param srcClock_Hz SDIF source clock frequency united in Hz.
+ * @param target_HZ card bus clock frequency united in Hz.
+ * @return The nearest frequency of busClock_Hz configured to SD bus.
+ */
+uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ);
+
+/*!
+ * @brief reset the different block of the interface.
+ * @param base SDIF peripheral base address.
+ * @param mask indicate which block to reset.
+ * @param timeout value,set to wait the bit self clear
+ * @return reset result.
+ */
+bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout);
+
+/*!
+ * @brief enable/disable the card power.
+ * once turn power on, software should wait for regulator/switch
+ * ramp-up time before trying to initialize card.
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag.
+ */
+static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK;
+    }
+    else
+    {
+        base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK;
+    }
+}
+
+/*!
+ * @brief get the card write protect status
+ * @param base SDIF peripheral base address.
+ */
+static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base)
+{
+    return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK;
+}
+
+/*!
+ * @brief set card data bus width
+ * @param base SDIF peripheral base address.
+ * @param data bus width type
+ */
+static inline void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type)
+{
+    base->CTYPE = type;
+}
+
+/*!
+ * @brief toggle state on hardware reset PIN
+ * This is used which card has a reset PIN typically.
+ * @param base SDIF peripheral base address.
+ */
+static inline void SDIF_AssertHardwareReset(SDIF_Type *base)
+{
+    base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK;
+}
+
+/*!
+ * @brief send command to the card
+ * @param base SDIF peripheral base address.
+ * @param command configuration collection
+ * @param timeout value
+ * @return command excute status
+ */
+status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout);
+
+/*!
+ * @brief SDIF enable/disable global interrupt
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF enable interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask
+ */
+static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->INTMASK |= mask;
+}
+
+/*!
+ * @brief SDIF disable interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask
+ */
+static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->INTMASK &= ~mask;
+}
+
+/*!
+ * @brief SDIF get interrupt status
+ * @param base SDIF peripheral base address.
+ */
+static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base)
+{
+    return base->MINTSTS;
+}
+
+/*!
+ * @brief SDIF clear interrupt status
+ * @param base SDIF peripheral base address.
+ * @param status mask to clear
+ */
+static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask)
+{
+    base->RINTSTS &= mask;
+}
+
+/*!
+ * @brief Creates the SDIF handle.
+ * register call back function for interrupt and enable the interrupt
+ * @param base SDIF peripheral base address.
+ * @param handle SDIF handle pointer.
+ * @param callback Structure pointer to contain all callback functions.
+ * @param userData Callback function parameter.
+ */
+void SDIF_TransferCreateHandle(SDIF_Type *base,
+                               sdif_handle_t *handle,
+                               sdif_transfer_callback_t *callback,
+                               void *userData);
+
+/*!
+ * @brief SDIF enable DMA interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask to set
+ */
+static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->IDINTEN |= mask;
+}
+
+/*!
+ * @brief SDIF disable DMA interrupt
+ * @param base SDIF peripheral base address.
+ * @param interrupt mask to clear
+ */
+static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask)
+{
+    base->IDINTEN &= ~mask;
+}
+
+/*!
+ * @brief SDIF get internal DMA status
+ * @param base SDIF peripheral base address.
+ * @return the internal DMA status register
+ */
+static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base)
+{
+    return base->IDSTS;
+}
+
+/*!
+ * @brief SDIF clear internal DMA status
+ * @param base SDIF peripheral base address.
+ * @param status mask to clear
+ */
+static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask)
+{
+    base->IDSTS &= mask;
+}
+
+/*!
+ * @brief SDIF internal DMA config function
+ * @param base SDIF peripheral base address.
+ * @param internal DMA configuration collection
+ * @param data buffer pointer
+ * @param data buffer size
+ */
+status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize);
+
+/*!
+ * @brief SDIF send read wait to SDIF card function
+ * @param base SDIF peripheral base address.
+ */
+static inline void SDIF_SendReadWait(SDIF_Type *base)
+{
+    base->CTRL |= SDIF_CTRL_READ_WAIT_MASK;
+}
+
+/*!
+ * @brief SDIF abort the read data when SDIF card is in suspend state
+ * Once assert this bit,data state machine will be reset which is waiting for the
+ * next blocking data,used in SDIO card suspend sequence,should call after suspend
+ * cmd send
+ * @param base SDIF peripheral base address.
+ * @param timeout value to wait this bit self clear which indicate the data machine
+ * reset to idle
+ */
+bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout);
+
+/*!
+ * @brief SDIF enable/disable CE-ATA card interrupt
+ * this bit should set together with the card register
+ * @param base SDIF peripheral base address.
+ * @param enable/disable flag
+ */
+static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF transfer function data/cmd in a non-blocking way
+ * this API should be use in interrupt mode, when use this API user
+ * must call SDIF_TransferCreateHandle first, all status check through
+ * interrupt
+ * @param base SDIF peripheral base address.
+ * @param sdif handle
+ * @param DMA config structure
+ *  This parameter can be config as:
+ *      1. NULL
+            In this condition, polling transfer mode is selected
+        2. avaliable DMA config
+            In this condition, DMA transfer mode is selected
+ * @param sdif transfer configuration collection
+ */
+status_t SDIF_TransferNonBlocking(SDIF_Type *base,
+                                  sdif_handle_t *handle,
+                                  sdif_dma_config_t *dmaConfig,
+                                  sdif_transfer_t *transfer);
+
+/*!
+ * @brief SDIF transfer function data/cmd in a blocking way
+ * @param base SDIF peripheral base address.
+ * @param DMA config structure
+ *       1. NULL
+ *           In this condition, polling transfer mode is selected
+ *       2. avaliable DMA config
+ *           In this condition, DMA transfer mode is selected
+ * @param sdif transfer configuration collection
+ */
+status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer);
+
+/*!
+ * @brief SDIF release the DMA descriptor to DMA engine
+ * this function should be called when DMA descriptor unavailable status occurs
+ * @param base SDIF peripheral base address.
+ * @param sdif DMA config pointer
+ */
+status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig);
+
+/*!
+ * @brief SDIF return the controller capability
+ * @param base SDIF peripheral base address.
+ * @param sdif capability pointer
+ */
+void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability);
+
+/*!
+ * @brief SDIF return the controller status
+ * @param base SDIF peripheral base address.
+ */
+static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base)
+{
+    return base->STATUS;
+}
+
+/*!
+ * @brief SDIF send command  complete signal disable to CE-ATA card
+ * @param base SDIF peripheral base address.
+ * @param send auto stop flag
+ */
+static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop)
+{
+    if (withAutoStop)
+    {
+        base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK;
+    }
+    else
+    {
+        base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK;
+    }
+}
+
+/*!
+ * @brief SDIF config the clock delay
+ * This function is used to config the cclk_in delay to
+ * sample and drvive the data ,should meet the min setup
+ * time and hold time, and user need to config this paramter
+ * according to your board setting
+ * @param target freq work mode
+ * @param clock divider which is used to decide if use pharse shift for delay
+ */
+void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+
+#endif /* _FSL_sdif_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,712 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spi.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+/* Note:  FIFOCFG[SIZE] has always value 1 = 8 items depth */
+#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3)
+
+/* Convert transfer count to transfer bytes. dataWidth is a
+ * range <0,15>. Range <8,15> represents 2B transfer */
+#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U))
+#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U))
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief internal SPI config array */
+static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0};
+
+/*! @brief Array to map SPI instance number to base address. */
+static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS;
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_spiIRQ[] = SPI_IRQS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the FLEXCOMM */
+uint32_t SPI_GetInstance(SPI_Type *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++)
+    {
+        if ((uint32_t)base == s_spiBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+void *SPI_GetConfig(SPI_Type *base)
+{
+    int32_t instance;
+    instance = SPI_GetInstance(base);
+    if (instance < 0)
+    {
+        return NULL;
+    }
+    return &g_configs[instance];
+}
+
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableLoopback = false;
+    config->enableMaster = true;
+    config->polarity = kSPI_ClockPolarityActiveHigh;
+    config->phase = kSPI_ClockPhaseFirstEdge;
+    config->direction = kSPI_MsbFirst;
+    config->baudRate_Bps = 500000U;
+    config->dataWidth = kSPI_Data8Bits;
+    config->sselNum = kSPI_Ssel0;
+    config->txWatermark = kSPI_TxFifo0;
+    config->rxWatermark = kSPI_RxFifo1;
+}
+
+status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz)
+{
+    int32_t result = 0, instance = 0;
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to SPI mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
+    assert(kStatus_Success == result);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    /* set divider */
+    result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+    /* get instance number */
+    instance = SPI_GetInstance(base);
+    assert(instance >= 0);
+
+    /* configure SPI mode */
+    tmp = base->CFG;
+    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | SPI_CFG_ENABLE_MASK);
+    /* phase */
+    tmp |= SPI_CFG_CPHA(config->phase);
+    /* polarity */
+    tmp |= SPI_CFG_CPOL(config->polarity);
+    /* direction */
+    tmp |= SPI_CFG_LSBF(config->direction);
+    /* master mode */
+    tmp |= SPI_CFG_MASTER(1);
+    /* loopback */
+    tmp |= SPI_CFG_LOOP(config->enableLoopback);
+    base->CFG = tmp;
+
+    /* store configuration */
+    g_configs[instance].dataWidth = config->dataWidth;
+    g_configs[instance].sselNum = config->sselNum;
+    /* enable FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
+    /* trigger level - empty txFIFO, one item in rxFIFO */
+    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
+    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
+    /* enable generating interrupts for FIFOTRIG levels */
+    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
+    /* set FIFOTRIG */
+    base->FIFOTRIG = tmp;
+
+    SPI_Enable(base, config->enableMaster);
+    return kStatus_Success;
+}
+
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config)
+{
+    assert(NULL != config);
+
+    config->enableSlave = true;
+    config->polarity = kSPI_ClockPolarityActiveHigh;
+    config->phase = kSPI_ClockPhaseFirstEdge;
+    config->direction = kSPI_MsbFirst;
+    config->dataWidth = kSPI_Data8Bits;
+    config->txWatermark = kSPI_TxFifo0;
+    config->rxWatermark = kSPI_RxFifo1;
+}
+
+status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config)
+{
+    int32_t result = 0, instance;
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (NULL == config)));
+    if ((NULL == base) || (NULL == config))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* configure flexcomm to SPI, enable clock gate */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI);
+    assert(kStatus_Success == result);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    instance = SPI_GetInstance(base);
+
+    /* configure SPI mode */
+    tmp = base->CFG;
+    tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK);
+    /* phase */
+    tmp |= SPI_CFG_CPHA(config->phase);
+    /* polarity */
+    tmp |= SPI_CFG_CPOL(config->polarity);
+    /* direction */
+    tmp |= SPI_CFG_LSBF(config->direction);
+    base->CFG = tmp;
+
+    /* store configuration */
+    g_configs[instance].dataWidth = config->dataWidth;
+    /* empty and enable FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK;
+    /* trigger level - empty txFIFO, one item in rxFIFO */
+    tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK));
+    tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark);
+    /* enable generating interrupts for FIFOTRIG levels */
+    tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK;
+    /* set FIFOTRIG */
+    base->FIFOTRIG = tmp;
+
+    SPI_Enable(base, config->enableSlave);
+    return kStatus_Success;
+}
+
+void SPI_Deinit(SPI_Type *base)
+{
+    /* Assert arguments */
+    assert(NULL != base);
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK |
+                         SPI_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(SPI_CFG_ENABLE_MASK);
+}
+
+void SPI_EnableTxDMA(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK;
+    }
+}
+
+void SPI_EnableRxDMA(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK;
+    }
+}
+
+status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t tmp;
+
+    /* assert params */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* calculate baudrate */
+    tmp = (srcClock_Hz / baudrate_Bps) - 1;
+    if (tmp > 0xFFFF)
+    {
+        return kStatus_SPI_BaudrateNotSupport;
+    }
+    base->DIV &= ~SPI_DIV_DIVVAL_MASK;
+    base->DIV |= SPI_DIV_DIVVAL(tmp);
+    return kStatus_Success;
+}
+
+void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags)
+{
+    uint32_t control = 0;
+    int32_t instance;
+
+    /* check params */
+    assert(NULL != base);
+    /* get and check instance */
+    instance = SPI_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return;
+    }
+
+    /* set data width */
+    control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth);
+    /* set sssel */
+    control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
+    /* mask configFlags */
+    control |= (configFlags & SPI_FIFOWR_FLAGS_MASK);
+    /* control should not affect lower 16 bits */
+    assert(!(control & 0xFFFF));
+    base->FIFOWR = data | control;
+}
+
+status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                        spi_master_handle_t *handle,
+                                        spi_master_callback_t callback,
+                                        void *userData)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* get flexcomm instance by 'base' param */
+    instance = SPI_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    /* Initialize the handle */
+    if (base->CFG & SPI_CFG_MASTER_MASK)
+    {
+        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_MasterTransferHandleIRQ, handle);
+    }
+    else
+    {
+        FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_SlaveTransferHandleIRQ, handle);
+    }
+
+    handle->dataWidth = g_configs[instance].dataWidth;
+    /* in slave mode, the sselNum is not important */
+    handle->sselNum = g_configs[instance].sselNum;
+    handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base);
+    handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base);
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Enable SPI NVIC */
+    EnableIRQ(s_spiIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer)
+{
+    int32_t instance;
+    uint32_t tx_ctrl = 0, last_ctrl = 0;
+    uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth;
+    uint32_t toReceiveCount = 0;
+    uint8_t *txData, *rxData;
+    uint32_t fifoDepth;
+
+    /* check params */
+    assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
+    if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    fifoDepth = SPI_FIFO_DEPTH(base);
+    txData = xfer->txData;
+    rxData = xfer->rxData;
+    txRemainingBytes = txData ? xfer->dataSize : 0;
+    rxRemainingBytes = rxData ? xfer->dataSize : 0;
+
+    instance = SPI_GetInstance(base);
+    assert(instance >= 0);
+    dataWidth = g_configs[instance].dataWidth;
+
+    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
+    assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
+    if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* clear tx/rx errors and empty FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
+    /* select slave to talk with */
+    tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
+    /* set width of data - range asserted at entry */
+    tx_ctrl |= SPI_FIFOWR_LEN(dataWidth);
+    /* end of transfer */
+    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
+    /* delay end of transfer */
+    last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
+    /* last index of loop */
+    while (txRemainingBytes || rxRemainingBytes || toReceiveCount)
+    {
+        /* if rxFIFO is not empty */
+        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+        {
+            tmp32 = base->FIFORD;
+            /* rxBuffer is not empty */
+            if (rxRemainingBytes)
+            {
+                *(rxData++) = tmp32;
+                rxRemainingBytes--;
+                /* read 16 bits at once */
+                if (dataWidth > 8)
+                {
+                    *(rxData++) = tmp32 >> 8;
+                    rxRemainingBytes--;
+                }
+            }
+            /* decrease number of data expected to receive */
+            toReceiveCount -= 1;
+        }
+        /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */
+        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) &&
+            ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))))
+        {
+            /* txBuffer is not empty */
+            if (txRemainingBytes)
+            {
+                tmp32 = *(txData++);
+                txRemainingBytes--;
+                /* write 16 bit at once */
+                if (dataWidth > 8)
+                {
+                    tmp32 |= ((uint32_t)(*(txData++))) << 8U;
+                    txRemainingBytes--;
+                }
+                if (!txRemainingBytes)
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            else
+            {
+                tmp32 = SPI_DUMMYDATA;
+                /* last transfer */
+                if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            /* send data */
+            tmp32 = tx_ctrl | tmp32;
+            base->FIFOWR = tmp32;
+            toReceiveCount += 1;
+        }
+    }
+    /* wait if TX FIFO of previous transfer is not empty */
+    while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK))
+    {
+    }
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer)
+{
+    /* check params */
+    assert(
+        !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */
+    assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)));
+    if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check if SPI is busy */
+    if (handle->state == kStatus_SPI_Busy)
+    {
+        return kStatus_SPI_Busy;
+    }
+
+    /* Set the handle information */
+    handle->txData = xfer->txData;
+    handle->rxData = xfer->rxData;
+    /* set count */
+    handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0;
+    handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0;
+    handle->totalByteCount = xfer->dataSize;
+    /* other options */
+    handle->toReceiveCount = 0;
+    handle->configFlags = xfer->configFlags;
+    /* Set the SPI state to busy */
+    handle->state = kStatus_SPI_Busy;
+    /* clear FIFOs when transfer starts */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+    base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
+    /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */
+    base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK;
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count)
+{
+    assert(NULL != handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kStatus_SPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->totalByteCount - handle->rxRemainingBytes;
+    return kStatus_Success;
+}
+
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupt requests*/
+    base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK);
+    /* Empty FIFOs */
+    base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
+
+    handle->state = kStatus_SPI_Idle;
+    handle->txRemainingBytes = 0;
+    handle->rxRemainingBytes = 0;
+}
+
+static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle)
+{
+    uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32;
+    bool loopContinue;
+    uint32_t fifoDepth;
+
+    /* check params */
+    assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData)));
+
+    fifoDepth = SPI_FIFO_DEPTH(base);
+    /* select slave to talk with */
+    tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum));
+    /* set width of data */
+    tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth);
+    /* end of transfer */
+    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
+    /* delay end of transfer */
+    last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
+    do
+    {
+        loopContinue = false;
+
+        /* rxFIFO is not empty */
+        if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+        {
+            tmp32 = base->FIFORD;
+            /* rxBuffer is not empty */
+            if (handle->rxRemainingBytes)
+            {
+                /* low byte must go first */
+                *(handle->rxData++) = tmp32;
+                handle->rxRemainingBytes--;
+                /* read 16 bits at once */
+                if (handle->dataWidth > kSPI_Data8Bits)
+                {
+                    *(handle->rxData++) = tmp32 >> 8;
+                    handle->rxRemainingBytes--;
+                }
+            }
+            /* decrease number of data expected to receive */
+            handle->toReceiveCount -= 1;
+            loopContinue = true;
+        }
+
+        /* - txFIFO is not full
+         * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO
+         * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer
+         */
+        if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) &&
+            ((handle->txRemainingBytes) ||
+             (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))))
+        {
+            /* txBuffer is not empty */
+            if (handle->txRemainingBytes)
+            {
+                /* low byte must go first */
+                tmp32 = *(handle->txData++);
+                handle->txRemainingBytes--;
+                /* write 16 bit at once */
+                if (handle->dataWidth > kSPI_Data8Bits)
+                {
+                    tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U;
+                    handle->txRemainingBytes--;
+                }
+                /* last transfer */
+                if (!handle->txRemainingBytes)
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            else
+            {
+                tmp32 = SPI_DUMMYDATA;
+                /* last transfer */
+                if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))
+                {
+                    tx_ctrl |= last_ctrl;
+                }
+            }
+            /* send data */
+            tmp32 = tx_ctrl | tmp32;
+            base->FIFOWR = tmp32;
+            /* increase number of expected data to receive */
+            handle->toReceiveCount += 1;
+            loopContinue = true;
+        }
+    } while (loopContinue);
+}
+
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle)
+{
+    assert((NULL != base) && (NULL != handle));
+
+    /* IRQ behaviour:
+     * - first interrupt is triggered by empty txFIFO. The transfer function
+     *   then tries empty rxFIFO and fill txFIFO interleaved that results to
+     *   strategy to process as many items as possible.
+     * - the next IRQs can be:
+     *      rxIRQ from nonempty rxFIFO which requires to empty rxFIFO.
+     *      txIRQ from empty txFIFO which requires to refill txFIFO.
+     * - last interrupt is triggered by empty txFIFO. The last state is
+     *   known by empty rxBuffer and txBuffer. If there is nothing to receive
+     *   or send - both operations have been finished and interrupts can be
+     *   disabled.
+     */
+
+    /* Data to send or read or expected to receive */
+    if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount))
+    {
+        /* Transmit or receive data */
+        SPI_TransferHandleIRQInternal(base, handle);
+        /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and
+         * enable txIRQ to confirm when txFIFO becomes empty */
+        if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount))
+        {
+            base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK);
+            base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK;
+        }
+        else
+        {
+            uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes);
+            /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data,
+             * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */
+            if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount))
+            {
+                base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK;
+            }
+            /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel.
+             * Cannot clear rxFIFO, txFIFO might be still active */
+            if (rxRemainingCount == 0)
+            {
+                if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) &&
+                    (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1))
+                {
+                    base->FIFOTRIG =
+                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1);
+                }
+            }
+            /* Expected to receive less data than rxLevel value, we have to update rxLevel */
+            else
+            {
+                if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1))
+                {
+                    base->FIFOTRIG =
+                        (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1);
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */
+        base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK;
+        base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) |
+                         SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark);
+        /* set idle state and call user callback */
+        handle->state = kStatus_SPI_Idle;
+        if (handle->callback)
+        {
+            (handle->callback)(base, handle, handle->state, handle->userData);
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,629 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPI_H_
+#define _FSL_SPI_H_
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*!
+ * @addtogroup spi_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.0.0. */
+#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define SPI_DUMMYDATA (0xFFFF)
+#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF)
+#define SPI_CTRLMASK (0xFFFF0000)
+
+#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000)
+#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16))
+#define SPI_DEASSERT_ALL (0xF0000)
+
+#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK))
+
+#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT)
+#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief SPI transfer option.*/
+typedef enum _spi_xfer_option {
+    kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK),  /*!< Delay chip select */
+    kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */
+} spi_xfer_option_t;
+
+/*! @brief SPI data shifter direction options.*/
+typedef enum _spi_shift_direction {
+    kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
+    kSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit. */
+} spi_shift_direction_t;
+
+/*! @brief SPI clock polarity configuration.*/
+typedef enum _spi_clock_polarity {
+    kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
+    kSPI_ClockPolarityActiveLow          /*!< Active-low SPI clock (idles high). */
+} spi_clock_polarity_t;
+
+/*! @brief SPI clock phase configuration.*/
+typedef enum _spi_clock_phase {
+    kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
+                                         *   cycle of a data transfer. */
+    kSPI_ClockPhaseSecondEdge        /*!< First edge on SCK occurs at the start of the
+                                         *   first cycle of a data transfer. */
+} spi_clock_phase_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _spi_txfifo_watermark {
+    kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */
+    kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */
+    kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */
+    kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */
+    kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */
+    kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */
+    kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */
+    kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */
+} spi_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _spi_rxfifo_watermark {
+    kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */
+    kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */
+    kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */
+    kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */
+    kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */
+    kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */
+    kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */
+    kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */
+} spi_rxfifo_watermark_t;
+
+/*! @brief Transfer data width */
+typedef enum _spi_data_width {
+    kSPI_Data4Bits = 3,   /*!< 4 bits data width */
+    kSPI_Data5Bits = 4,   /*!< 5 bits data width */
+    kSPI_Data6Bits = 5,   /*!< 6 bits data width */
+    kSPI_Data7Bits = 6,   /*!< 7 bits data width */
+    kSPI_Data8Bits = 7,   /*!< 8 bits data width */
+    kSPI_Data9Bits = 8,   /*!< 9 bits data width */
+    kSPI_Data10Bits = 9,  /*!< 10 bits data width */
+    kSPI_Data11Bits = 10, /*!< 11 bits data width */
+    kSPI_Data12Bits = 11, /*!< 12 bits data width */
+    kSPI_Data13Bits = 12, /*!< 13 bits data width */
+    kSPI_Data14Bits = 13, /*!< 14 bits data width */
+    kSPI_Data15Bits = 14, /*!< 15 bits data width */
+    kSPI_Data16Bits = 15, /*!< 16 bits data width */
+} spi_data_width_t;
+
+/*! @brief Slave select */
+typedef enum _spi_ssel {
+    kSPI_Ssel0 = 0, /*!< Slave select 0 */
+    kSPI_Ssel1 = 1, /*!< Slave select 1 */
+    kSPI_Ssel2 = 2, /*!< Slave select 2 */
+    kSPI_Ssel3 = 3, /*!< Slave select 3 */
+} spi_ssel_t;
+
+/*! @brief SPI master user configure structure.*/
+typedef struct _spi_master_config
+{
+    bool enableLoopback;                /*!< Enable loopback for test purpose */
+    bool enableMaster;                  /*!< Enable SPI at initialization time */
+    spi_clock_polarity_t polarity;      /*!< Clock polarity */
+    spi_clock_phase_t phase;            /*!< Clock phase */
+    spi_shift_direction_t direction;    /*!< MSB or LSB */
+    uint32_t baudRate_Bps;              /*!< Baud Rate for SPI in Hz */
+    spi_data_width_t dataWidth;         /*!< Width of the data */
+    spi_ssel_t sselNum;                 /*!< Slave select number */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} spi_master_config_t;
+
+/*! @brief SPI slave user configure structure.*/
+typedef struct _spi_slave_config
+{
+    bool enableSlave;                   /*!< Enable SPI at initialization time */
+    spi_clock_polarity_t polarity;      /*!< Clock polarity */
+    spi_clock_phase_t phase;            /*!< Clock phase */
+    spi_shift_direction_t direction;    /*!< MSB or LSB */
+    spi_data_width_t dataWidth;         /*!< Width of the data */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} spi_slave_config_t;
+
+/*! @brief SPI transfer status.*/
+enum _spi_status
+{
+    kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0),  /*!< SPI bus is busy */
+    kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1),  /*!< SPI is idle */
+    kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI  error */
+    kStatus_SPI_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief SPI interrupt sources.*/
+enum _spi_interrupt_enable
+{
+    kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */
+    kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */
+};
+
+/*! @brief SPI status flags.*/
+enum _spi_statusflags
+{
+    kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK,       /*!< txFifo is empty */
+    kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK,   /*!< txFifo is not full */
+    kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */
+    kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK,         /*!< rxFIFO is full */
+};
+
+/*! @brief SPI transfer structure */
+typedef struct _spi_transfer
+{
+    uint8_t *txData;      /*!< Send buffer */
+    uint8_t *rxData;      /*!< Receive buffer */
+    uint32_t configFlags; /*!< Additional option to control transfer */
+    size_t dataSize;      /*!< Transfer bytes */
+} spi_transfer_t;
+
+/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
+typedef struct _spi_config
+{
+    spi_data_width_t dataWidth;
+    spi_ssel_t sselNum;
+} spi_config_t;
+
+/*! @brief  Master handle type */
+typedef struct _spi_master_handle spi_master_handle_t;
+
+/*! @brief  Slave handle type */
+typedef spi_master_handle_t spi_slave_handle_t;
+
+/*! @brief SPI master callback for finished transmit */
+typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI slave callback for finished transmit */
+typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI transfer handle structure */
+struct _spi_master_handle
+{
+    uint8_t *volatile txData;         /*!< Transfer buffer */
+    uint8_t *volatile rxData;         /*!< Receive buffer */
+    volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
+    volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
+    volatile size_t toReceiveCount;   /*!< Receive data remaining in bytes */
+    size_t totalByteCount;            /*!< A number of transfer bytes */
+    volatile uint32_t state;          /*!< SPI internal state */
+    spi_master_callback_t callback;   /*!< SPI callback */
+    void *userData;                   /*!< Callback parameter */
+    uint8_t dataWidth;                /*!< Width of the data [Valid values: 1 to 16] */
+    uint8_t sselNum;      /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */
+    uint32_t configFlags; /*!< Additional option to control transfer */
+    spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*! @brief Returns instance number for SPI peripheral base address. */
+uint32_t SPI_GetInstance(SPI_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief  Sets the SPI master configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
+ * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
+ * some fields of the structure before calling SPI_MasterInit(). After calling this API,
+ * the master is ready to transfer.
+ * Example:
+   @code
+   spi_master_config_t config;
+   SPI_MasterGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to master config structure
+ */
+void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with master configuration.
+ *
+ * The configuration structure can be filled by user from scratch, or be set with default
+ * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+   spi_master_config_t config = {
+   .baudRate_Bps = 400000,
+   ...
+   };
+   SPI_MasterInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to master configuration structure
+ * @param srcClock_Hz Source clock frequency.
+ */
+status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief  Sets the SPI slave configuration structure to default values.
+ *
+ * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
+ * Modify some fields of the structure before calling SPI_SlaveInit().
+ * Example:
+   @code
+   spi_slave_config_t config;
+   SPI_SlaveGetDefaultConfig(&config);
+   @endcode
+ *
+ * @param config pointer to slave configuration structure
+ */
+void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
+
+/*!
+ * @brief Initializes the SPI with slave configuration.
+ *
+ * The configuration structure can be filled by user from scratch or be set with
+ * default values by SPI_SlaveGetDefaultConfig().
+ * After calling this API, the slave is ready to transfer.
+ * Example
+   @code
+    spi_slave_config_t config = {
+    .polarity = flexSPIClockPolarity_ActiveHigh;
+    .phase = flexSPIClockPhase_FirstEdge;
+    .direction = flexSPIMsbFirst;
+    ...
+    };
+    SPI_SlaveInit(SPI0, &config);
+   @endcode
+ *
+ * @param base SPI base pointer
+ * @param config pointer to slave configuration structure
+ */
+status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
+
+/*!
+ * @brief De-initializes the SPI.
+ *
+ * Calling this API resets the SPI module, gates the SPI clock.
+ * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
+ *
+ * @param base SPI base pointer
+ */
+void SPI_Deinit(SPI_Type *base);
+
+/*!
+ * @brief Enable or disable the SPI Master or Slave
+ * @param base SPI base pointer
+ * @param enable or disable ( true = enable, false = disable)
+ */
+static inline void SPI_Enable(SPI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= SPI_CFG_ENABLE_MASK;
+    }
+    else
+    {
+        base->CFG &= ~SPI_CFG_ENABLE_MASK;
+    }
+}
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the status flag.
+ *
+ * @param base SPI base pointer
+ * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status.
+ */
+static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
+{
+    assert(NULL != base);
+    return base->FIFOSTAT;
+}
+
+/*! @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxLvlIrq
+ *        @arg kSPI_TxLvlIrq
+ */
+static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
+{
+    assert(NULL != base);
+    base->FIFOINTENSET = irqs;
+}
+
+/*!
+ * @brief Disables the interrupt for the SPI.
+ *
+ * @param base SPI base pointer
+ * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
+ *        @arg kSPI_RxLvlIrq
+ *        @arg kSPI_TxLvlIrq
+ */
+static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
+{
+    assert(NULL != base);
+    base->FIFOINTENCLR = irqs;
+}
+
+/*! @} */
+
+/*!
+ * @name DMA Control
+ * @{
+ */
+
+/*!
+ * @brief Enables the DMA request from SPI txFIFO.
+ *
+ * @param base SPI base pointer
+ * @param enable True means enable DMA, false means disable DMA
+ */
+void SPI_EnableTxDMA(SPI_Type *base, bool enable);
+
+/*!
+ * @brief Enables the DMA request from SPI rxFIFO.
+ *
+ * @param base SPI base pointer
+ * @param enable True means enable DMA, false means disable DMA
+ */
+void SPI_EnableRxDMA(SPI_Type *base, bool enable);
+
+/*! @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the baud rate for SPI transfer. This is only used in master.
+ *
+ * @param base SPI base pointer
+ * @param baudrate_Bps baud rate needed in Hz.
+ * @param srcClock_Hz SPI source clock frequency in Hz.
+ */
+status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Writes a data into the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @param data needs to be write.
+ * @param configFlags transfer configuration options @ref spi_xfer_option_t
+ */
+void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags);
+
+/*!
+ * @brief Gets a data from the SPI data register.
+ *
+ * @param base SPI base pointer
+ * @return Data in the register.
+ */
+static inline uint32_t SPI_ReadData(SPI_Type *base)
+{
+    assert(NULL != base);
+    return base->FIFORD;
+}
+
+/*! @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPI master handle.
+ *
+ * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
+                                        spi_master_handle_t *handle,
+                                        spi_master_callback_t callback,
+                                        void *userData);
+
+/*!
+ * @brief Transfers a block of data using a polling method.
+ *
+ * @param base SPI base pointer
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ */
+status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking SPI interrupt transfer.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Gets the master transfer count.
+ *
+ * This function gets the master transfer count.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief SPI master aborts a transfer using an interrupt.
+ *
+ * This function aborts a transfer using an interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Interrupts the handler for the SPI.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
+ */
+void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
+
+/*!
+ * @brief Initializes the SPI slave handle.
+ *
+ * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
+ * for a specified SPI instance, call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
+                                                     spi_slave_handle_t *handle,
+                                                     spi_slave_callback_t callback,
+                                                     void *userData)
+{
+    return SPI_MasterTransferCreateHandle(base, handle, callback, userData);
+}
+
+/*!
+ * @brief Performs a non-blocking SPI slave interrupt transfer.
+ *
+ * @note The API returns immediately after the transfer initialization is finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_xfer_config_t structure
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
+{
+    return SPI_MasterTransferNonBlocking(base, handle, xfer);
+}
+
+/*!
+ * @brief Gets the slave transfer count.
+ *
+ * This function gets the slave transfer count.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
+ * @return status of status_t.
+ */
+static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count);
+}
+
+/*!
+ * @brief SPI slave aborts a transfer using an interrupt.
+ *
+ * This function aborts a transfer using an interrupt.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
+ */
+static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle);
+}
+
+/*!
+ * @brief Interrupts a handler for the SPI slave.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
+ */
+static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle)
+{
+    SPI_MasterTransferHandleIRQ(base, handle);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_SPI_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spi_dma.h"
+
+/*******************************************************************************
+ * Definitons
+ ******************************************************************************/
+/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
+typedef struct _spi_dma_private_handle
+{
+    SPI_Type *base;
+    spi_dma_handle_t *handle;
+} spi_dma_private_handle_t;
+
+/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
+enum _spi_dma_states_t
+{
+    kSPI_Idle = 0x0, /*!< SPI is idle state */
+    kSPI_Busy        /*!< SPI is busy tranferring data. */
+};
+
+typedef struct _spi_dma_txdummy
+{
+    uint32_t lastWord;
+    uint32_t word;
+} spi_dma_txdummy_t;
+
+/*<! Private handle only used for internally. */
+static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+* @brief SPI private function to return SPI configuration
+*
+* @param base SPI base address.
+*/
+void *SPI_GetConfig(SPI_Type *base);
+
+/*!
+ * @brief DMA callback function for SPI send transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*!
+ * @brief DMA callback function for SPI receive transfer.
+ *
+ * @param handle DMA handle pointer.
+ * @param userData User data for DMA callback function.
+ */
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#endif
+
+#if defined(__ICCARM__)
+#pragma data_alignment = 4
+static uint16_t s_rxDummy;
+#elif defined(__CC_ARM)
+__attribute__((aligned(4))) static uint16_t s_rxDummy;
+#elif defined(__GNUC__)
+__attribute__((aligned(4))) static uint16_t s_rxDummy;
+#endif
+
+#if defined(__ICCARM__)
+#pragma data_alignment = 16
+static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__CC_ARM)
+__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#elif defined(__GNUC__)
+__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
+#endif
+
+/*******************************************************************************
+* Code
+******************************************************************************/
+
+static void XferToFifoWR(spi_transfer_t *xfer, uint32_t *fifowr)
+{
+    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0;
+    *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0;
+}
+
+static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr)
+{
+    *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum)));
+    /* set width of data - range asserted at entry */
+    *fifowr |= SPI_FIFOWR_LEN(config->dataWidth);
+}
+
+static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl)
+{
+    assert(!(fifo == NULL));
+    if (fifo == NULL)
+    {
+        return;
+    }
+    /* CS deassert and CS delay are relevant only for last word */
+    uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK));
+    uint32_t i = 0;
+    for (; i + 1 < count; i++)
+    {
+        fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U);
+    }
+    if (i < count)
+    {
+        fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U);
+    }
+}
+
+static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
+{
+    *dummy = SPI_DUMMYDATA;
+    XferToFifoWR(xfer, dummy);
+    SpiConfigToFifoWR(spi_config_p, dummy);
+}
+
+status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                           spi_dma_handle_t *handle,
+                                           spi_dma_callback_t callback,
+                                           void *userData,
+                                           dma_handle_t *txHandle,
+                                           dma_handle_t *rxHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = SPI_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* Set spi base to handle */
+    handle->txHandle = txHandle;
+    handle->rxHandle = rxHandle;
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Set SPI state to idle */
+    handle->state = kSPI_Idle;
+
+    /* Set handle to global state */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    /* Install callback for Tx dma channel */
+    DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
+    DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
+
+    return kStatus_Success;
+}
+
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    int32_t instance;
+    status_t result = kStatus_Success;
+    spi_config_t *spi_config_p;
+
+    assert(!((NULL == handle) || (NULL == xfer)));
+    if ((NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* txData set and not aligned to sizeof(uint32_t) */
+    assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))));
+    if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* rxData set and not aligned to sizeof(uint32_t) */
+    assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))));
+    if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* byte size is zero or not aligned to sizeof(uint32_t) */
+    assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))));
+    if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* cannot get instance from base address */
+    instance = SPI_GetInstance(base);
+    assert(!(instance < 0));
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check if the device is busy */
+    if (handle->state == kSPI_Busy)
+    {
+        return kStatus_SPI_Busy;
+    }
+    else
+    {
+        uint32_t tmp;
+        dma_transfer_config_t xferConfig = {0};
+        spi_config_p = (spi_config_t *)SPI_GetConfig(base);
+
+        handle->state = kStatus_SPI_Busy;
+        handle->transferSize = xfer->dataSize;
+
+        /* receive */
+        SPI_EnableRxDMA(base, true);
+        if (xfer->rxData)
+        {
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_PeripheralToMemory, NULL);
+        }
+        else
+        {
+            DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_StaticToStatic, NULL);
+        }
+        DMA_SubmitTransfer(handle->rxHandle, &xferConfig);
+        handle->rxInProgress = true;
+        DMA_StartTransfer(handle->rxHandle);
+
+        /* transmit */
+        SPI_EnableTxDMA(base, true);
+        if (xfer->txData)
+        {
+            tmp = 0;
+            XferToFifoWR(xfer, &tmp);
+            SpiConfigToFifoWR(spi_config_p, &tmp);
+            PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp);
+            DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize,
+                                kDMA_MemoryToPeripheral, NULL);
+            DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+        }
+        else
+        {
+            if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t)))
+            {
+                dma_xfercfg_t tmp_xfercfg = { 0 };
+                tmp_xfercfg.valid = true;
+                tmp_xfercfg.swtrig = true;
+                tmp_xfercfg.intA = true;
+                tmp_xfercfg.byteWidth = sizeof(uint32_t);
+                tmp_xfercfg.srcInc = 0;
+                tmp_xfercfg.dstInc = 0;
+                tmp_xfercfg.transferCount = 1;
+                /* create chained descriptor to transmit last word */
+                SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p);
+                DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
+                                     (uint32_t *)&base->FIFOWR, NULL);
+                /* use common API to setup first descriptor */
+                SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p);
+                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
+                                    xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic,
+                                    &s_spi_descriptor_table[instance]);
+                /* disable interrupts for first descriptor
+                 * to avoid calling callback twice */
+                xferConfig.xfercfg.intA = false;
+                xferConfig.xfercfg.intB = false;
+                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+            }
+            else
+            {
+                SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p);
+                DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
+                                    xfer->dataSize, kDMA_StaticToStatic, NULL);
+                result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+                if (result != kStatus_Success)
+                {
+                    return result;
+                }
+            }
+        }
+        handle->txInProgress = true;
+        DMA_StartTransfer(handle->txHandle);
+    }
+
+    return result;
+}
+
+static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle = privHandle->handle;
+    SPI_Type *base = privHandle->base;
+
+    /* change the state */
+    spiHandle->rxInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = kSPI_Idle;
+        if (spiHandle->callback)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
+{
+    spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
+    spi_dma_handle_t *spiHandle = privHandle->handle;
+    SPI_Type *base = privHandle->base;
+
+    /* change the state */
+    spiHandle->txInProgress = false;
+
+    /* All finished, call the callback */
+    if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
+    {
+        spiHandle->state = kSPI_Idle;
+        if (spiHandle->callback)
+        {
+            (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
+        }
+    }
+}
+
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Stop tx transfer first */
+    DMA_AbortTransfer(handle->txHandle);
+    /* Then rx transfer */
+    DMA_AbortTransfer(handle->rxHandle);
+
+    /* Set the handle state */
+    handle->txInProgress = false;
+    handle->rxInProgress = false;
+    handle->state = kSPI_Idle;
+}
+
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    if (!count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state != kSPI_Busy)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    size_t bytes;
+
+    bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
+
+    *count = handle->transferSize - bytes;
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPI_DMA_H_
+#define _FSL_SPI_DMA_H_
+
+#include "fsl_dma.h"
+#include "fsl_spi.h"
+
+/*!
+ * @addtogroup spi_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef struct _spi_dma_handle spi_dma_handle_t;
+
+/*! @brief SPI DMA callback called at the end of transfer. */
+typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/
+struct _spi_dma_handle
+{
+    volatile bool txInProgress;  /*!< Send transfer finished */
+    volatile bool rxInProgress;  /*!< Receive transfer finished */
+    dma_handle_t *txHandle;      /*!< DMA handler for SPI send */
+    dma_handle_t *rxHandle;      /*!< DMA handler for SPI receive */
+    uint8_t bytesPerFrame;       /*!< Bytes in a frame for SPI tranfer */
+    spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */
+    void *userData;              /*!< User Data for SPI DMA callback */
+    uint32_t state;              /*!< Internal state of SPI DMA transfer */
+    size_t transferSize;         /*!< Bytes need to be transfer */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initialize the SPI master DMA handle.
+ *
+ * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
+                                           spi_dma_handle_t *handle,
+                                           spi_dma_callback_t callback,
+                                           void *userData,
+                                           dma_handle_t *txHandle,
+                                           dma_handle_t *rxHandle);
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer);
+
+/*!
+ * @brief Initialize the SPI slave DMA handle.
+ *
+ * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs.
+ * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI handle pointer.
+ * @param callback User callback function called at the end of a transfer.
+ * @param userData User data for callback.
+ * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
+ * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
+ */
+static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base,
+                                                        spi_dma_handle_t *handle,
+                                                        spi_dma_callback_t callback,
+                                                        void *userData,
+                                                        dma_handle_t *txHandle,
+                                                        dma_handle_t *rxHandle)
+{
+    return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle);
+}
+
+/*!
+ * @brief Perform a non-blocking SPI transfer using DMA.
+ *
+ * @note This interface returned immediately after transfer initiates, users should call
+ * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ * @param xfer Pointer to dma transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
+ */
+static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
+{
+    return SPI_MasterTransferDMA(base, handle, xfer);
+}
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the master DMA transfer remaining bytes.
+ *
+ * This function gets the master DMA transfer remaining bytes.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
+ * @return status of status_t.
+ */
+status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Abort a SPI transfer using DMA.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle SPI DMA handle pointer.
+ */
+static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
+{
+    SPI_MasterTransferAbortDMA(base, handle);
+}
+
+/*!
+ * @brief Gets the slave DMA transfer remaining bytes.
+ *
+ * This function gets the slave DMA transfer remaining bytes.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
+ * @return status of status_t.
+ */
+static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
+{
+    return SPI_MasterTransferGetCountDMA(base, handle, count);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_SPI_DMA_H_*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spifi.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the SPIFI instance from peripheral base address.
+ *
+ * @param base SPIFI peripheral base address.
+ * @return SPIFI instance.
+ */
+uint32_t SPIFI_GetInstance(SPIFI_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of SPIFI peripheral base address. */
+static SPIFI_Type *const s_spifiBases[] = SPIFI_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of SPIFI clock name. */
+static const clock_ip_name_t s_spifiClock[] = SPIFI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+uint32_t SPIFI_GetInstance(SPIFI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_spifiBases); instance++)
+    {
+        if (s_spifiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_spifiBases));
+
+    return instance;
+}
+
+void SPIFI_GetDefaultConfig(spifi_config_t *config)
+{
+    config->timeout = 0xFFFFU;
+    config->csHighTime = 0xFU;
+    config->disablePrefetch = false;
+    config->disableCachePrefech = false;
+    config->isFeedbackClock = true;
+    config->spiMode = kSPIFI_SPISckLow;
+    config->isReadFullClockCycle = false;
+    config->dualMode = kSPIFI_QuadMode;
+}
+
+void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config)
+{
+    assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_EnableClock(s_spifiClock[SPIFI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the Command register */
+    SPIFI_ResetCommand(base);
+
+    /* Set time delay parameter */
+    base->CTRL = SPIFI_CTRL_TIMEOUT(config->timeout) | SPIFI_CTRL_CSHIGH(config->csHighTime) |
+                 SPIFI_CTRL_D_PRFTCH_DIS(config->disablePrefetch) | SPIFI_CTRL_MODE3(config->spiMode) |
+                 SPIFI_CTRL_PRFTCH_DIS(config->disableCachePrefech) | SPIFI_CTRL_DUAL(config->dualMode) |
+                 SPIFI_CTRL_RFCLK(config->isReadFullClockCycle) | SPIFI_CTRL_FBCLK(config->isFeedbackClock);
+}
+
+void SPIFI_Deinit(SPIFI_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the SAI clock */
+    CLOCK_DisableClock(s_spifiClock[SPIFI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd)
+{
+    /* Wait for the CMD and MCINT flag all be 0 */
+    while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK))
+    {
+    }
+    base->CMD = SPIFI_CMD_DATALEN(cmd->dataLen) | SPIFI_CMD_POLL(cmd->isPollMode) | SPIFI_CMD_DOUT(cmd->direction) |
+                SPIFI_CMD_INTLEN(cmd->intermediateBytes) | SPIFI_CMD_FIELDFORM(cmd->format) |
+                SPIFI_CMD_FRAMEFORM(cmd->type) | SPIFI_CMD_OPCODE(cmd->opcode);
+
+    /* Wait for the command written */
+    while ((base->STAT & SPIFI_STAT_CMD_MASK) == 0U)
+    {
+    }
+}
+
+void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd)
+{
+    /* Wait for the CMD and MCINT flag all be 0 */
+    while (SPIFI_GetStatusFlag(base) & (SPIFI_STAT_MCINIT_MASK | SPIFI_STAT_CMD_MASK))
+    {
+    }
+
+    base->MCMD = SPIFI_MCMD_POLL(0U) | SPIFI_MCMD_DOUT(0U) | SPIFI_MCMD_INTLEN(cmd->intermediateBytes) |
+                 SPIFI_MCMD_FIELDFORM(cmd->format) | SPIFI_MCMD_FRAMEFORM(cmd->type) | SPIFI_MCMD_OPCODE(cmd->opcode);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPIFI_H_
+#define _FSL_SPIFI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup spifi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief SPIFI driver version 2.0.0. */
+#define FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Status structure of SPIFI.*/
+enum _status_t
+{
+    kStatus_SPIFI_Idle = MAKE_STATUS(kStatusGroup_SPIFI, 0),  /*!< SPIFI is in idle state  */
+    kStatus_SPIFI_Busy = MAKE_STATUS(kStatusGroup_SPIFI, 1),  /*!< SPIFI is busy */
+    kStatus_SPIFI_Error = MAKE_STATUS(kStatusGroup_SPIFI, 2), /*!< Error occurred during SPIFI transfer */
+};
+
+/*! @brief SPIFI interrupt source */
+typedef enum _spifi_interrupt_enable
+{
+    kSPIFI_CommandFinishInterruptEnable = SPIFI_CTRL_INTEN_MASK, /*!< Interrupt while command finished */
+} spifi_interrupt_enable_t;
+
+/*! @brief SPIFI SPI mode select */
+typedef enum _spifi_spi_mode
+{
+    kSPIFI_SPISckLow = 0x0U, /*!< SCK low after last bit of command, keeps low while CS high */
+    kSPIFI_SPISckHigh = 0x1U /*!< SCK high after last bit of command and while CS high */
+} spifi_spi_mode_t;
+
+/*! @brief SPIFI dual mode select */
+typedef enum _spifi_dual_mode
+{
+    kSPIFI_QuadMode = 0x0U, /*!< SPIFI uses IO3:0 */
+    kSPIFI_DualMode = 0x1U  /*!< SPIFI uses IO1:0 */
+} spifi_dual_mode_t;
+
+/*! @brief SPIFI data direction */
+typedef enum _spifi_data_direction
+{
+    kSPIFI_DataInput = 0x0U, /*!< Data input from serial flash. */
+    kSPIFI_DataOutput = 0x1U /*!< Data output to serial flash. */
+} spifi_data_direction_t;
+
+/*! @brief SPIFI command opcode format */
+typedef enum _spifi_command_format
+{
+    kSPIFI_CommandAllSerial = 0x0,     /*!< All fields of command are serial. */
+    kSPIFI_CommandDataQuad = 0x1U,     /*!< Only data field is dual/quad, others are serial. */
+    kSPIFI_CommandOpcodeSerial = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */
+    kSPIFI_CommandAllQuad = 0x3U       /*!< All fields of command are dual/quad mode. */
+} spifi_command_format_t;
+
+/*! @brief SPIFI command type */
+typedef enum _spifi_command_type
+{
+    kSPIFI_CommandOpcodeOnly = 0x1U,             /*!< Command only have opcode, no address field */
+    kSPIFI_CommandOpcodeAddrOneByte = 0x2U,      /*!< Command have opcode and also one byte address field */
+    kSPIFI_CommandOpcodeAddrTwoBytes = 0x3U,     /*!< Command have opcode and also two bytes address field */
+    kSPIFI_CommandOpcodeAddrThreeBytes = 0x4U,   /*!< Command have opcode and also three bytes address field. */
+    kSPIFI_CommandOpcodeAddrFourBytes = 0x5U,    /*!< Command have opcode and also four bytes address field */
+    kSPIFI_CommandNoOpcodeAddrThreeBytes = 0x6U, /*!< Command have no opcode and three bytes address field */
+    kSPIFI_CommandNoOpcodeAddrFourBytes = 0x7U   /*!< Command have no opcode and four bytes address field */
+} spifi_command_type_t;
+
+/*! @brief SPIFI status flags */
+enum _spifi_status_flags
+{
+    kSPIFI_MemoryCommandWriteFinished = SPIFI_STAT_MCINIT_MASK, /*!< Memory command write finished */
+    kSPIFI_CommandWriteFinished = SPIFI_STAT_CMD_MASK,          /*!< Command write finished */
+    kSPIFI_InterruptRequest = SPIFI_STAT_INTRQ_MASK /*!< CMD flag from 1 to 0, means command execute finished */
+};
+
+/*! @brief SPIFI command structure */
+typedef struct _spifi_command
+{
+    uint16_t dataLen;                 /*!< How many data bytes are needed in this command. */
+    bool isPollMode;                  /*!< For command need to read data from serial flash */
+    spifi_data_direction_t direction; /*!< Data direction of this command. */
+    uint8_t intermediateBytes;        /*!< How many intermediate bytes needed */
+    spifi_command_format_t format;    /*!< Command format */
+    spifi_command_type_t type;        /*!< Command type */
+    uint8_t opcode;                   /*!< Command opcode value */
+} spifi_command_t;
+
+/*!
+ * @brief SPIFI region configuration structure.
+ */
+typedef struct _spifi_config
+{
+    uint16_t timeout;           /*!< SPI transfer timeout, the unit is SCK cycles */
+    uint8_t csHighTime;         /*!< CS high time cycles */
+    bool disablePrefetch;       /*!< True means SPIFI will not attempt a speculative prefetch. */
+    bool disableCachePrefech;   /*!< Disable prefetch of cache line */
+    bool isFeedbackClock;       /*!< Is data sample uses feedback clock. */
+    spifi_spi_mode_t spiMode;   /*!< SPIFI spi mode select */
+    bool isReadFullClockCycle;  /*!< If enable read full clock cycle. */
+    spifi_dual_mode_t dualMode; /*!< SPIFI dual mode, dual or quad. */
+} spifi_config_t;
+
+/*! @brief Transfer structure for SPIFI */
+typedef struct _spifi_transfer
+{
+    uint8_t *data;   /*!< Pointer to data to transmit */
+    size_t dataSize; /*!< Bytes to be transmit */
+} spifi_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPIFI with the user configuration structure.
+ *
+ * This function configures the SPIFI module with the user-defined configuration.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param config   The pointer to the configuration structure.
+ */
+void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config);
+
+/*!
+ * @brief Get SPIFI default configure settings.
+ *
+ * @param config  SPIFI config structure pointer.
+ */
+void SPIFI_GetDefaultConfig(spifi_config_t *config);
+
+/*!
+ * @brief Deinitializes the SPIFI regions.
+ *
+ * @param base     SPIFI peripheral base address.
+ */
+void SPIFI_Deinit(SPIFI_Type *base);
+
+/* @}*/
+
+/*!
+ * @name Basic Control Operations
+ * @{
+ */
+
+/*!
+ * @brief Set SPIFI flash command.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param cmd      SPIFI command structure pointer.
+ */
+void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd);
+
+/*!
+ * @brief Set SPIFI command address.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param addr     Address value for the command.
+ */
+static inline void SPIFI_SetCommandAddress(SPIFI_Type *base, uint32_t addr)
+{
+    base->ADDR = addr;
+}
+
+/*!
+ * @brief Set SPIFI intermediate data.
+ *
+ * Before writing a command wihch needs specific intermediate value, users shall call this function to write it.
+ * The main use of this function for current serial flash is to select no-opcode mode and cancelling this mode. As
+ * dummy cycle do not care about the value, no need to call this function.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param val      Intermediate data.
+ */
+static inline void SPIFI_SetIntermediateData(SPIFI_Type *base, uint32_t val)
+{
+    base->IDATA = val;
+}
+
+/*!
+ * @brief Set SPIFI Cache limit value.
+ *
+ * SPIFI includes caching of prevously-accessed data to improve performance. Software can write an address to this
+ * function, to prevent such caching at and above the address.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param val     Zero-based upper limit of cacheable memory.
+ */
+static inline void SPIFI_SetCacheLimit(SPIFI_Type *base, uint32_t val)
+{
+    base->CLIMIT = val;
+}
+
+/*!
+ * @brief Reset the command field of SPIFI.
+ *
+ * This function is used to abort the current command or memory mode.
+ *
+ * @param base     SPIFI peripheral base address.
+ */
+static inline void SPIFI_ResetCommand(SPIFI_Type *base)
+{
+    base->STAT = SPIFI_STAT_RESET_MASK;
+    /* Wait for the RESET flag cleared by HW */
+    while (base->STAT & SPIFI_STAT_RESET_MASK)
+    {
+    }
+}
+
+/*!
+ * @brief Set SPIFI flash AHB read command.
+ *
+ * Call this function means SPIFI enters to memory mode, while users need to use command, a SPIFI_ResetCommand shall
+ * be called.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param cmd      SPIFI command structure pointer.
+ */
+void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd);
+
+/*!
+ * @brief Enable SPIFI interrupt.
+ *
+ * The interrupt is triggered only in command mode, and it means the command now is finished.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param mask     SPIFI interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: spifi_interrupt_enable_t
+ */
+static inline void SPIFI_EnableInterrupt(SPIFI_Type *base, uint32_t mask)
+{
+    base->CTRL |= mask;
+}
+
+/*!
+ * @brief Disable SPIFI interrupt.
+ *
+ * The interrupt is triggered only in command mode, and it means the command now is finished.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param mask     SPIFI interrupt enable mask. It is a logic OR of members the
+ *                 enumeration :: spifi_interrupt_enable_t
+ */
+static inline void SPIFI_DisableInterrupt(SPIFI_Type *base, uint32_t mask)
+{
+    base->CTRL &= ~mask;
+}
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get the status of all interrupt flags for SPIFI.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @return SPIFI flag status
+ */
+static inline uint32_t SPIFI_GetStatusFlag(SPIFI_Type *base)
+{
+    return base->STAT;
+}
+
+/* @}*/
+
+/*!
+ * @brief Enable or disable DMA request for SPIFI.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param enable   True means enable DMA and false means disable DMA.
+ */
+static inline void SPIFI_EnableDMA(SPIFI_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= SPIFI_CTRL_DMAEN_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~SPIFI_CTRL_DMAEN_MASK;
+    }
+}
+
+/*!
+ * @brief  Gets the SPIFI data register address.
+ *
+ * This API is used to provide a transfer address for the SPIFI DMA transfer configuration.
+ *
+ * @param base SPIFI base pointer
+ * @return data register address
+ */
+static inline uint32_t SPIFI_GetDataRegisterAddress(SPIFI_Type *base)
+{
+    return (uint32_t)(&(base->DATA));
+}
+
+/*!
+ * @brief Write a word data in address of SPIFI.
+ *
+ * Users can write a page or at least a word data into SPIFI address.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @param data     Data need be write.
+ */
+static inline void SPIFI_WriteData(SPIFI_Type *base, uint32_t data)
+{
+    base->DATA = data;
+}
+
+/*!
+ * @brief Read data from serial flash.
+ *
+ * Users should notice before call this function, the data length field in command register shall larger
+ * than 4, otherwise a hardfault will happen.
+ *
+ * @param base     SPIFI peripheral base address.
+ * @return Data input from flash.
+ */
+static inline uint32_t SPIFI_ReadData(SPIFI_Type *base)
+{
+    return base->DATA;
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SPIFI_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_spifi_dma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Structure definition for spifi_dma_private_handle_t. The structure is private. */
+typedef struct _spifi_dma_private_handle
+{
+    SPIFI_Type *base;
+    spifi_dma_handle_t *handle;
+} spifi_dma_private_handle_t;
+
+/* SPIFI DMA transfer handle. */
+enum _spifi_dma_tansfer_states
+{
+    kSPIFI_Idle,   /* TX idle. */
+    kSPIFI_BusBusy /* RX busy. */
+};
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*<! Private handle only used for internally. */
+static spifi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPIFI_COUNT][2];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief SPIFI DMA send finished callback function.
+ *
+ * This function is called when SPIFI DMA send finished. It disables the SPIFI
+ * TX DMA request and sends @ref kStatus_SPIFI_TxIdle to SPIFI callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void SPIFI_SendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode);
+
+/*!
+ * @brief SPIFI DMA receive finished callback function.
+ *
+ * This function is called when SPIFI DMA receive finished. It disables the SPIFI
+ * RX DMA request and sends @ref kStatus_SPIFI_RxIdle to SPIFI callback.
+ *
+ * @param handle The DMA handle.
+ * @param param Callback function parameter.
+ */
+static void SPIFI_ReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode);
+
+/*!
+ * @brief Get the SPIFI instance from peripheral base address.
+ *
+ * @param base SPIFI peripheral base address.
+ * @return SPIFI instance.
+ */
+extern uint32_t SPIFI_GetInstance(SPIFI_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void SPIFI_SendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    spifi_dma_private_handle_t *spifiPrivateHandle = (spifi_dma_private_handle_t *)param;
+
+    /* Avoid the warning for unused variables. */
+    handle = handle;
+    intmode = intmode;
+
+    if (transferDone)
+    {
+        SPIFI_TransferAbortSendDMA(spifiPrivateHandle->base, spifiPrivateHandle->handle);
+
+        if (spifiPrivateHandle->handle->callback)
+        {
+            spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle,
+                                                 kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+static void SPIFI_ReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    spifi_dma_private_handle_t *spifiPrivateHandle = (spifi_dma_private_handle_t *)param;
+
+    /* Avoid warning for unused parameters. */
+    handle = handle;
+    intmode = intmode;
+
+    if (transferDone)
+    {
+        /* Disable transfer. */
+        SPIFI_TransferAbortReceiveDMA(spifiPrivateHandle->base, spifiPrivateHandle->handle);
+
+        if (spifiPrivateHandle->handle->callback)
+        {
+            spifiPrivateHandle->handle->callback(spifiPrivateHandle->base, spifiPrivateHandle->handle,
+                                                 kStatus_SPIFI_Idle, spifiPrivateHandle->handle->userData);
+        }
+    }
+}
+
+void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle)
+{
+    assert(handle);
+
+    uint32_t instance = SPIFI_GetInstance(base);
+
+    s_dmaPrivateHandle[instance][0].base = base;
+    s_dmaPrivateHandle[instance][0].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->state = kSPIFI_Idle;
+    handle->dmaHandle = dmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure TX dma callback */
+    DMA_SetCallback(handle->dmaHandle, SPIFI_SendDMACallback, &s_dmaPrivateHandle[instance][0]);
+}
+
+void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle)
+{
+    assert(handle);
+
+    uint32_t instance = SPIFI_GetInstance(base);
+
+    s_dmaPrivateHandle[instance][1].base = base;
+    s_dmaPrivateHandle[instance][1].handle = handle;
+
+    memset(handle, 0, sizeof(*handle));
+
+    handle->state = kSPIFI_Idle;
+    handle->dmaHandle = dmaHandle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure RX dma callback */
+    DMA_SetCallback(handle->dmaHandle, SPIFI_ReceiveDMACallback, &s_dmaPrivateHandle[instance][1]);
+}
+
+status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer)
+{
+    assert(handle && (handle->dmaHandle));
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kSPIFI_BusBusy == handle->state)
+    {
+        status = kStatus_SPIFI_Busy;
+    }
+    else
+    {
+        handle->state = kSPIFI_BusBusy;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)SPIFI_GetDataRegisterAddress(base), sizeof(uint32_t),
+                            xfer->dataSize, kDMA_MemoryToPeripheral, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->dmaHandle);
+
+        /* Enable SPIFI TX DMA. */
+        SPIFI_EnableDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer)
+{
+    assert(handle && (handle->dmaHandle));
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kSPIFI_BusBusy == handle->state)
+    {
+        status = kStatus_SPIFI_Busy;
+    }
+    else
+    {
+        handle->state = kSPIFI_BusBusy;
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)SPIFI_GetDataRegisterAddress(base), xfer->data, sizeof(uint32_t),
+                            xfer->dataSize, kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->dmaHandle);
+
+        /* Enable SPIFI TX DMA. */
+        SPIFI_EnableDMA(base, true);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle)
+{
+    assert(handle && (handle->dmaHandle));
+
+    /* Disable SPIFI TX DMA. */
+    SPIFI_EnableDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    handle->state = kSPIFI_Idle;
+}
+
+void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle)
+{
+    assert(handle && (handle->dmaHandle));
+
+    /* Disable SPIFI RX DMA. */
+    SPIFI_EnableDMA(base, false);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->dmaHandle);
+
+    handle->state = kSPIFI_Idle;
+}
+
+status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kSPIFI_BusBusy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}
+
+status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count)
+{
+    assert(handle);
+
+    status_t status = kStatus_Success;
+
+    if (handle->state != kSPIFI_BusBusy)
+    {
+        status = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->transferSize - DMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel);
+    }
+
+    return status;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SPIFI_DMA_H_
+#define _FSL_SPIFI_DMA_H_
+
+#include "fsl_dma.h"
+#include "fsl_spifi.h"
+
+/*!
+ * @addtogroup spifi
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+typedef struct _spifi_dma_handle spifi_dma_handle_t;
+
+/*! @brief SPIFI DMA transfer callback function for finish and error */
+typedef void (*spifi_dma_callback_t)(SPIFI_Type *base, spifi_dma_handle_t *handle, status_t status, void *userData);
+
+/*! @brief SPIFI DMA transfer handle, users should not touch the content of the handle.*/
+struct _spifi_dma_handle
+{
+    dma_handle_t *dmaHandle;       /*!< DMA handler for SPIFI send */
+    size_t transferSize;           /*!< Bytes need to transfer. */
+    uint32_t state;                /*!< Internal state for SPIFI DMA transfer */
+    spifi_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */
+    void *userData;                /*!< User callback parameter */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SPIFI handle for send which is used in transactional functions and set the callback.
+ *
+ * @param base SPIFI peripheral base address
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param callback SPIFI callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested DMA handle for DMA transfer
+ */
+void SPIFI_TransferTxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Initializes the SPIFI handle for receive which is used in transactional functions and set the callback.
+ *
+ * @param base SPIFI peripheral base address
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param callback SPIFI callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested DMA handle for DMA transfer
+ */
+void SPIFI_TransferRxCreateHandleDMA(SPIFI_Type *base,
+                                     spifi_dma_handle_t *handle,
+                                     spifi_dma_callback_t callback,
+                                     void *userData,
+                                     dma_handle_t *dmaHandle);
+
+/*!
+ * @brief Transfers SPIFI data using an DMA non-blocking method.
+ *
+ * This function writes data to the SPIFI transmit FIFO. This function is non-blocking.
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param xfer SPIFI transfer structure.
+ */
+status_t SPIFI_TransferSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using an DMA non-blocking method.
+ *
+ * This function receive data from the SPIFI receive buffer/FIFO. This function is non-blocking.
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param xfer SPIFI transfer structure.
+ */
+status_t SPIFI_TransferReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, spifi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using DMA.
+ *
+ * This function aborts the sent data using DMA.
+ *
+ * @param base SPIFI peripheral base address.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ */
+void SPIFI_TransferAbortSendDMA(SPIFI_Type *base, spifi_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the receive data using DMA.
+ *
+ * This function abort receive data which using DMA.
+ *
+ * @param base SPIFI peripheral base address.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ */
+void SPIFI_TransferAbortReceiveDMA(SPIFI_Type *base, spifi_dma_handle_t *handle);
+
+/*!
+ * @brief Gets the transferred counts of send.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure.
+ * @param count Bytes sent.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPIFI_TransferGetSendCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the status of the receive transfer.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param handle Pointer to spifi_dma_handle_t structure
+ * @param count Bytes received.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t SPIFI_TransferGetReceiveCountDMA(SPIFI_Type *base, spifi_dma_handle_t *handle, size_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* _FSL_SPIFI_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,708 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+    int i;
+
+    for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++)
+    {
+        if ((uint32_t)base == s_usartBaseAddrs[i])
+        {
+            return i;
+        }
+    }
+
+    assert(false);
+    return 0;
+}
+
+static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+    size_t size;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (handle->rxRingBufferTail > handle->rxRingBufferHead)
+    {
+        size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
+    }
+    else
+    {
+        size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
+    }
+    return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+    bool full;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+    /* ring buffer is ready we can start receiving data */
+    base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+
+    if (handle->rxState == kUSART_RxIdle)
+    {
+        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+    }
+    handle->rxRingBuffer = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+    int result;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to USART mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    /* setup baudrate */
+    result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (config->enableTx)
+    {
+        /* empty and enable txFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+    }
+
+    /* empty and enable rxFIFO */
+    if (config->enableRx)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+    }
+    /* setup configuration and enable USART */
+    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK;
+    return kStatus_Success;
+}
+
+void USART_Deinit(USART_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+                         USART_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+    /* Check arguments */
+    assert(NULL != config);
+
+    /* Set always all members ! */
+    config->baudRate_Bps = 115200U;
+    config->parityMode = kUSART_ParityDisabled;
+    config->stopBitCount = kUSART_OneStopBit;
+    config->bitCountPerChar = kUSART_8BitsPerChar;
+    config->loopback = false;
+    config->enableRx = false;
+    config->enableTx = false;
+    config->txWatermark = kUSART_TxFifo0;
+    config->rxWatermark = kUSART_RxFifo1;
+}
+
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+    uint32_t osrval, brgval, diff, baudrate;
+
+    /* check arguments */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /*
+     * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+     * potentially cause more noise errors or incorrect data.
+     */
+    for (osrval = best_osrval; osrval >= 8; osrval--)
+    {
+        brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1;
+        if (brgval > 0xFFFF)
+        {
+            continue;
+        }
+        baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1));
+        diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
+        if (diff < best_diff)
+        {
+            best_diff = diff;
+            best_osrval = osrval;
+            best_brgval = brgval;
+        }
+    }
+
+    /* value over range */
+    if (best_brgval > 0xFFFF)
+    {
+        return kStatus_USART_BaudrateNotSupport;
+    }
+
+    base->OSR = best_osrval;
+    base->BRG = best_brgval;
+    return kStatus_Success;
+}
+
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return;
+    }
+    /* Check whether txFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+    {
+        return;
+    }
+    for (; length > 0; length--)
+    {
+        /* Loop until txFIFO get some space for new data */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+        }
+        base->FIFOWR = *data;
+        data++;
+    }
+    /* Wait to finish transfer */
+    while (!(base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+}
+
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+    uint32_t status;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check whether rxFIFO is enabled */
+    if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK))
+    {
+        return kStatus_Fail;
+    }
+    for (; length > 0; length--)
+    {
+        /* loop until rxFIFO have some data to read */
+        while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+        }
+        /* check receive status */
+        status = base->STAT;
+        if (status & USART_STAT_FRAMERRINT_MASK)
+        {
+            base->STAT |= USART_STAT_FRAMERRINT_MASK;
+            return kStatus_USART_FramingError;
+        }
+        if (status & USART_STAT_PARITYERRINT_MASK)
+        {
+            base->STAT |= USART_STAT_PARITYERRINT_MASK;
+            return kStatus_USART_ParityError;
+        }
+        if (status & USART_STAT_RXNOISEINT_MASK)
+        {
+            base->STAT |= USART_STAT_RXNOISEINT_MASK;
+            return kStatus_USART_NoiseError;
+        }
+        /* check rxFIFO status */
+        if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+        {
+            base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+            base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+            return kStatus_USART_RxError;
+        }
+
+        *data = base->FIFORD;
+        data++;
+    }
+    return kStatus_Success;
+}
+
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData)
+{
+    int32_t instance = 0;
+
+    /* Check 'base' */
+    assert(!((NULL == base) || (NULL == handle)));
+    if ((NULL == base) || (NULL == handle))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* Set the TX/RX state. */
+    handle->rxState = kUSART_RxIdle;
+    handle->txState = kUSART_TxIdle;
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+    handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base);
+    handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+    FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)USART_TransferHandleIRQ, handle);
+
+    /* Enable interrupt in NVIC. */
+    EnableIRQ(s_usartIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if (kUSART_TxBusy == handle->txState)
+    {
+        return kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txData = xfer->data;
+        handle->txDataSize = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState = kUSART_TxBusy;
+        /* Enable transmiter interrupt. */
+        base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
+    }
+    return kStatus_Success;
+}
+
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupts */
+    base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK;
+    /* Empty txFIFO */
+    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+    handle->txDataSize = 0;
+    handle->txState = kUSART_TxIdle;
+}
+
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes)
+{
+    uint32_t i;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t regPrimask = 0U;
+
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0 == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+    if (kUSART_RxBusy == handle->rxState)
+    {
+        return kStatus_USART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            regPrimask = DisableGlobalIRQ();
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+            if (bytesToCopy)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+                bytesToReceive -= bytesToCopy;
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize = bytesToReceive;
+                handle->rxDataSizeAll = bytesToReceive;
+                handle->rxState = kUSART_RxBusy;
+            }
+            /* Enable IRQ if previously enabled. */
+            EnableGlobalIRQ(regPrimask);
+            /* Call user callback since all data are received. */
+            if (0 == bytesToReceive)
+            {
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState = kUSART_RxBusy;
+
+            /* Enable RX interrupt. */
+            base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
+        }
+        /* Return the how many bytes have read. */
+        if (receivedBytes)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+    }
+    return kStatus_Success;
+}
+
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (!handle->rxRingBuffer)
+    {
+        /* Disable interrupts */
+        base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK;
+        /* Empty rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState = kUSART_RxIdle;
+}
+
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if (kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert((NULL != base) && (NULL != handle));
+
+    bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer);
+    bool sendEnabled = handle->txDataSize;
+
+    /* If RX overrun. */
+    if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)
+    {
+        /* Clear rx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+        }
+    }
+    while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||
+           (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))
+    {
+        /* Receive data */
+        if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))
+        {
+            /* Receive to app bufffer if app buffer is present */
+            if (handle->rxDataSize)
+            {
+                *handle->rxData = base->FIFORD;
+                handle->rxDataSize--;
+                handle->rxData++;
+                receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer));
+                if (!handle->rxDataSize)
+                {
+                    if (!handle->rxRingBuffer)
+                    {
+                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+                    }
+                    handle->rxState = kUSART_RxIdle;
+                    if (handle->callback)
+                    {
+                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                    }
+                }
+            }
+            /* Otherwise receive to ring buffer if ring buffer is present */
+            else
+            {
+                if (handle->rxRingBuffer)
+                {
+                    /* If RX ring buffer is full, trigger callback to notify over run. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        if (handle->callback)
+                        {
+                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+                        }
+                    }
+                    /* If ring buffer is still full after callback function, the oldest data is overrided. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        /* Increase handle->rxRingBufferTail to make room for new data. */
+                        if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                        {
+                            handle->rxRingBufferTail = 0U;
+                        }
+                        else
+                        {
+                            handle->rxRingBufferTail++;
+                        }
+                    }
+                    /* Read data. */
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD;
+                    /* Increase handle->rxRingBufferHead. */
+                    if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferHead = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferHead++;
+                    }
+                }
+            }
+        }
+        /* Send data */
+        if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+            base->FIFOWR = *handle->txData;
+            handle->txDataSize--;
+            handle->txData++;
+            sendEnabled = handle->txDataSize != 0;
+            if (!sendEnabled)
+            {
+                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+                handle->txState = kUSART_TxIdle;
+                if (handle->callback)
+                {
+                    handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+                }
+            }
+        }
+    }
+
+    /* ring buffer is not used */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* restore if rx transfer ends and rxLevel is different from default value */
+        if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+        }
+        /* decrease level if rx transfer is bellow */
+        if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1)))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1));
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,643 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_USART_H_
+#define _FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.0.0. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Error codes for the USART driver. */
+enum _usart_status
+{
+    kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0),              /*!< Transmitter is busy. */
+    kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1),              /*!< Receiver is busy. */
+    kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2),              /*!< USART transmitter is idle. */
+    kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3),              /*!< USART receiver is idle. */
+    kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7),             /*!< Error happens on txFIFO. */
+    kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9),             /*!< Error happens on rxFIFO. */
+    kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */
+    kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10),         /*!< USART noise error. */
+    kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11),       /*!< USART framing error. */
+    kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12),        /*!< USART parity error. */
+    kStatus_USART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode
+{
+    kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kUSART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kUSART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count
+{
+    kUSART_OneStopBit = 0U, /*!< One stop bit */
+    kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len
+{
+    kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+    kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark
+{
+    kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+    kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+    kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+    kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+    kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+    kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+    kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+    kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark
+{
+    kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+    kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+    kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+    kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+    kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+    kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+    kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+    kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+    kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+    kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+    kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+    kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+    kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK),                 /*!< TEERR bit, sets if TX buffer is error */
+    kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK),                 /*!< RXERR bit, sets if RX buffer is error */
+    kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK),       /*!< TXEMPTY bit, sets if TX buffer is empty */
+    kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK),   /*!< TXNOTFULL bit, sets if TX buffer is not full */
+    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
+    kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK),         /*!< RXFULL bit, sets if RX buffer is full */
+};
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+    uint32_t baudRate_Bps;                /*!< USART baud rate  */
+    usart_parity_mode_t parityMode;       /*!< Parity mode, disabled (default), even, odd */
+    usart_stop_bit_count_t stopBitCount;  /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    usart_data_len_t bitCountPerChar;     /*!< Data length - 7 bit, 8 bit  */
+    bool loopback;                        /*!< Enable peripheral loopback */
+    bool enableRx;                        /*!< Enable RX */
+    bool enableTx;                        /*!< Enable TX */
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    usart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                     /*!< USART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*! @brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source freqency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+    return base->FIFOSTAT;
+}
+
+/*!
+ * @brief Clear USART status flags.
+ *
+ * This function clear supported USART status flags
+ * Flags that can be cleared or set are:
+ *      kUSART_TxError
+ *      kUSART_RxError
+ * For example:
+ * @code
+ *     USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask status flags to be cleared.
+ */
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
+{
+    /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
+    base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = mask & 0xF;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = ~(mask & 0xF);
+}
+
+/*!
+* @brief Enable DMA for Tx
+*/
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+    }
+}
+
+/*!
+* @brief Enable DMA for Rx
+*/
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+    }
+}
+
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+    base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+    return base->FIFORD;
+}
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See  #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+                                   usart_handle_t *handle,
+                                   uint8_t *ringBuffer,
+                                   size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_dma.h"
+#include "fsl_flexcomm.h"
+#include "fsl_usart_dma.h"
+
+/*<! Structure definition for uart_dma_handle_t. The structure is private. */
+typedef struct _usart_dma_private_handle
+{
+    USART_Type *base;
+    usart_dma_handle_t *handle;
+} usart_dma_private_handle_t;
+
+enum _usart_transfer_states
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*<! Private handle only used for internally. */
+static usart_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_USART_COUNT];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static void USART_TransferSendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
+
+    /* Disable UART TX DMA. */
+    USART_EnableTxDMA(usartPrivateHandle->base, false);
+
+    usartPrivateHandle->handle->txState = kUSART_TxIdle;
+
+    if (usartPrivateHandle->handle->callback)
+    {
+        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle,
+                                             usartPrivateHandle->handle->userData);
+    }
+}
+
+static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
+{
+    assert(handle);
+    assert(param);
+
+    usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
+
+    /* Disable UART RX DMA. */
+    USART_EnableRxDMA(usartPrivateHandle->base, false);
+
+    usartPrivateHandle->handle->rxState = kUSART_RxIdle;
+
+    if (usartPrivateHandle->handle->callback)
+    {
+        usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle,
+                                             usartPrivateHandle->handle->userData);
+    }
+}
+
+status_t USART_TransferCreateHandleDMA(USART_Type *base,
+                                       usart_dma_handle_t *handle,
+                                       usart_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txDmaHandle,
+                                       dma_handle_t *rxDmaHandle)
+{
+    int32_t instance = 0;
+
+    /* check 'base' */
+    assert(!(NULL == base));
+    if (NULL == base)
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* check 'handle' */
+    assert(!(NULL == handle));
+    if (NULL == handle)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    memset(handle, 0, sizeof(*handle));
+    /* assign 'base' and 'handle' */
+    s_dmaPrivateHandle[instance].base = base;
+    s_dmaPrivateHandle[instance].handle = handle;
+
+    /* set tx/rx 'idle' state */
+    handle->rxState = kUSART_RxIdle;
+    handle->txState = kUSART_TxIdle;
+
+    handle->callback = callback;
+    handle->userData = userData;
+
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->txDmaHandle = txDmaHandle;
+
+    /* Configure TX. */
+    if (txDmaHandle)
+    {
+        DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    /* Configure RX. */
+    if (rxDmaHandle)
+    {
+        DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
+    }
+
+    return kStatus_Success;
+}
+
+status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->txDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous TX not finished. */
+    if (kUSART_TxBusy == handle->txState)
+    {
+        status = kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txState = kUSART_TxBusy;
+        handle->txDataSizeAll = xfer->dataSize;
+
+        /* Enable DMA request from txFIFO */
+        USART_EnableTxDMA(base, true);
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)&base->FIFOWR, sizeof(uint8_t), xfer->dataSize,
+                            kDMA_MemoryToPeripheral, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->txDmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
+    dma_transfer_config_t xferConfig;
+    status_t status;
+
+    /* If previous RX not finished. */
+    if (kUSART_RxBusy == handle->rxState)
+    {
+        status = kStatus_USART_RxBusy;
+    }
+    else
+    {
+        handle->rxState = kUSART_RxBusy;
+        handle->rxDataSizeAll = xfer->dataSize;
+
+        /* Enable DMA request from rxFIFO */
+        USART_EnableRxDMA(base, true);
+
+        /* Prepare transfer. */
+        DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->data, sizeof(uint8_t), xfer->dataSize,
+                            kDMA_PeripheralToMemory, NULL);
+
+        /* Submit transfer. */
+        DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+        DMA_StartTransfer(handle->rxDmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->txDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->txDmaHandle);
+    handle->txState = kUSART_TxIdle;
+}
+
+void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle)
+{
+    assert(NULL != handle);
+    assert(NULL != handle->rxDmaHandle);
+
+    /* Stop transfer. */
+    DMA_AbortTransfer(handle->rxDmaHandle);
+    handle->rxState = kUSART_RxIdle;
+}
+
+status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count)
+{
+    assert(handle);
+    assert(handle->rxDmaHandle);
+    assert(count);
+
+    if (kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+
+    return kStatus_Success;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_USART_DMA_H_
+#define _FSL_USART_DMA_H_
+
+#include "fsl_common.h"
+#include "fsl_dma.h"
+#include "fsl_usart.h"
+
+/*!
+ * @addtogroup usart_dma_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_dma_handle usart_dma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*usart_dma_transfer_callback_t)(USART_Type *base,
+                                              usart_dma_handle_t *handle,
+                                              status_t status,
+                                              void *userData);
+
+/*!
+* @brief UART DMA handle
+*/
+struct _usart_dma_handle
+{
+    USART_Type *base; /*!< UART peripheral base address. */
+
+    usart_dma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                         /*!< UART callback function parameter.*/
+    size_t rxDataSizeAll;                   /*!< Size of the data to receive. */
+    size_t txDataSizeAll;                   /*!< Size of the data to send out. */
+
+    dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
+    dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name DMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle which is used in transactional functions.
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param callback Callback function.
+ * @param userData User data.
+ * @param txDmaHandle User-requested DMA handle for TX DMA transfer.
+ * @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
+ */
+status_t USART_TransferCreateHandleDMA(USART_Type *base,
+                                       usart_dma_handle_t *handle,
+                                       usart_dma_transfer_callback_t callback,
+                                       void *userData,
+                                       dma_handle_t *txDmaHandle,
+                                       dma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Sends data using DMA.
+ *
+ * This function sends data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART DMA transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_USART_TxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base USART peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer USART DMA transfer structure. See #usart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_USART_RxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data using DMA.
+ *
+ * This function aborts send data using DMA.
+ *
+ * @param base USART peripheral base address
+ * @param handle Pointer to usart_dma_handle_t structure
+ */
+void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle);
+
+/*!
+ * @brief Aborts the received data using DMA.
+ *
+ * This function aborts the received data using DMA.
+ *
+ * @param base USART peripheral base address
+ * @param handle Pointer to usart_dma_handle_t structure
+ */
+void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_DMA_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_utick.h"
+#include "fsl_power.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Typedef for interrupt handler. */
+typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base UTICK peripheral base address
+ *
+ * @return The UTICK instance
+ */
+static uint32_t UTICK_GetInstance(UTICK_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of UTICK handle. */
+static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT];
+/* Array of UTICK peripheral base address. */
+static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS;
+/* Array of UTICK IRQ number. */
+static const IRQn_Type s_utickIRQ[] = UTICK_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of UTICK clock name. */
+static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+/* UTICK ISR for transactional APIs. */
+static utick_isr_t s_utickIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t UTICK_GetInstance(UTICK_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++)
+    {
+        if (s_utickBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_utickBases));
+
+    return instance;
+}
+
+void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb)
+{
+    uint32_t instance;
+
+    /* Get instance from peripheral base address. */
+    instance = UTICK_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_utickHandle[instance] = cb;
+    EnableDeepSleepIRQ(s_utickIRQ[instance]);
+    base->CTRL = count | UTICK_CTRL_REPEAT(mode);
+}
+
+void UTICK_Init(UTICK_Type *base)
+{
+    /* Enable utick clock */
+    CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]);
+    /* Power up Watchdog oscillator*/
+    POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC);
+    s_utickIsr = UTICK_HandleIRQ;
+}
+
+void UTICK_Deinit(UTICK_Type *base)
+{
+    /* Turn off utick */
+    base->CTRL = 0;
+    /* Disable utick clock */
+    CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]);
+}
+
+uint32_t UTICK_GetStatusFlags(UTICK_Type *base)
+{
+    return (base->STAT);
+}
+
+void UTICK_ClearStatusFlags(UTICK_Type *base)
+{
+    base->STAT = UTICK_STAT_INTR_MASK;
+}
+
+void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb)
+{
+    UTICK_ClearStatusFlags(base);
+    if (cb)
+    {
+        cb();
+    }
+}
+
+#if defined(UTICK0)
+void UTICK0_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK0, s_utickHandle[0]);
+}
+#endif
+#if defined(UTICK1)
+void UTICK1_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK1, s_utickHandle[1]);
+}
+#endif
+#if defined(UTICK2)
+void UTICK2_DriverIRQHandler(void)
+{
+    s_utickIsr(UTICK2, s_utickHandle[2]);
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_UTICK_H_
+#define _FSL_UTICK_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup utick
+ * @{
+ */
+
+/*! @file*/
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UTICK driver version 2.0.0. */
+#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief UTICK timer operational mode. */
+typedef enum _utick_mode
+{
+    kUTICK_Onetime = 0x0U, /*!< Trigger once*/
+    kUTICK_Repeat = 0x1U,  /*!< Trigger repeatedly */
+} utick_mode_t;
+
+/*! @brief UTICK callback function. */
+typedef void (*utick_callback_t)(void);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+* @brief Initializes an UTICK by turning its bus clock on
+*
+*/
+void UTICK_Init(UTICK_Type *base);
+
+/*!
+ * @brief Deinitializes a UTICK instance.
+ *
+ * This function shuts down Utick bus clock
+ *
+ * @param base UTICK peripheral base address.
+ */
+void UTICK_Deinit(UTICK_Type *base);
+/*!
+ * @brief Get Status Flags.
+ *
+ * This returns the status flag
+ *
+ * @param base UTICK peripheral base address.
+ * @return status register value
+ */
+uint32_t UTICK_GetStatusFlags(UTICK_Type *base);
+/*!
+ * @brief Clear Status Interrupt Flags.
+ *
+ * This clears intr status flag
+ *
+ * @param base UTICK peripheral base address.
+ * @return none
+ */
+void UTICK_ClearStatusFlags(UTICK_Type *base);
+
+/*!
+ * @brief Starts UTICK.
+ *
+ * This function starts a repeat/onetime countdown with an optional callback
+ *
+ * @param base   UTICK peripheral base address.
+ * @param mode  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
+ * @param count  UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
+ * @param cb  UTICK callback (can be left as NULL if none, otherwise should be a void func(void))
+ * @return none
+ */
+void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb);
+/*!
+ * @brief UTICK Interrupt Service Handler.
+ *
+ * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request
+ * in UTICK_SetTick()).
+ * if no user callback is scheduled, the interrupt will simply be cleared.
+ *
+ * @param base   UTICK peripheral base address.
+ * @param cb  callback scheduled for this instance of UTICK
+ * @return none
+ */
+void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UTICK_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_wwdt.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base WWDT peripheral base address
+ *
+ * @return The WWDT instance
+ */
+static uint32_t WWDT_GetInstance(WWDT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to WWDT bases for each instance. */
+static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to WWDT clocks for each instance. */
+static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to WWDT resets for each instance. */
+static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t WWDT_GetInstance(WWDT_Type *base)
+{
+    uint32_t instance;
+    uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0]));
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < wwdtArrayCount; instance++)
+    {
+        if (s_wwdtBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < wwdtArrayCount);
+
+    return instance;
+}
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void WWDT_GetDefaultConfig(wwdt_config_t *config)
+{
+    assert(config);
+
+    /* Enable the watch dog */
+    config->enableWwdt = true;
+    /* Disable the watchdog timeout reset */
+    config->enableWatchdogReset = false;
+    /* Disable the watchdog protection for updating the timeout value */
+    config->enableWatchdogProtect = false;
+    /* Do not lock the watchdog oscillator */
+    config->enableLockOscillator = false;
+    /* Windowing is not in effect */
+    config->windowValue = 0xFFFFFFU;
+    /* Set the timeout value to the max */
+    config->timeoutValue = 0xFFFFFFU;
+    /* No warning is provided */
+    config->warningValue = 0;
+}
+
+void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)
+{
+    assert(config);
+
+    uint32_t value = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the WWDT clock */
+    CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the WWDT module */
+    RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]);
+
+    value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) |
+            WWDT_MOD_WDPROTECT(config->enableWatchdogProtect) | WWDT_MOD_LOCK(config->enableLockOscillator);
+    /* Set configruation */
+    base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue);
+    base->TC = WWDT_TC_COUNT(config->timeoutValue);
+    base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue);
+    base->MOD = value;
+}
+
+void WWDT_Deinit(WWDT_Type *base)
+{
+    WWDT_Disable(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the WWDT clock */
+    CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void WWDT_Refresh(WWDT_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupt to protect refresh sequence */
+    primaskValue = DisableGlobalIRQ();
+    base->FEED = WWDT_FIRST_WORD_OF_REFRESH;
+    base->FEED = WWDT_SECOND_WORD_OF_REFRESH;
+    EnableGlobalIRQ(primaskValue);
+}
+
+void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask)
+{
+    /* Clear the WDINT bit so that we don't accidentally clear it */
+    uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK));
+
+    /* Clear timeout by writing a zero */
+    if (mask & kWWDT_TimeoutFlag)
+    {
+        reg &= ~WWDT_MOD_WDTOF_MASK;
+    }
+
+    /* Clear warning interrupt flag by writing a one */
+    if (mask & kWWDT_WarningFlag)
+    {
+        reg |= WWDT_MOD_WDINT_MASK;
+    }
+
+    base->MOD = reg;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_WWDT_H_
+#define _FSL_WWDT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup wwdt
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines WWDT driver version 2.0.0. */
+#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @name Refresh sequence */
+/*@{*/
+#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU)  /*!< First word of refresh sequence */
+#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */
+/*@}*/
+
+/*! @brief Describes WWDT configuration structure. */
+typedef struct _wwdt_config
+{
+    bool enableWwdt;            /*!< Enables or disables WWDT */
+    bool enableWatchdogReset;   /*!< true: Watchdog timeout will cause a chip reset
+                                     false: Watchdog timeout will not cause a chip reset */
+    bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be
+                                           changed after counter is below warning & window values
+                                     false: Disable watchdog protect; timeout value can be changed
+                                            at any time */
+    bool enableLockOscillator;  /*!< true: Disabling or powering down the watchdog oscillator is prevented
+                                           Once set, this bit can only be cleared by a reset
+                                     false: Do not lock oscillator */
+    uint32_t windowValue;       /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */
+    uint32_t timeoutValue;      /*!< Timeout value */
+    uint32_t warningValue;      /*!< Watchdog time counter value that will generate a
+                                     warning interrupt. Set this to 0 for no warning */
+
+} wwdt_config_t;
+
+/*!
+ * @brief WWDT status flags.
+ *
+ * This structure contains the WWDT status flags for use in the WWDT functions.
+ */
+enum _wwdt_status_flags_t
+{
+    kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */
+    kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK  /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */
+};
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name WWDT Initialization and De-initialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes WWDT configure sturcture.
+ *
+ * This function initializes the WWDT configure structure to default value. The default
+ * value are:
+ * @code
+ *  config->enableWwdt = true;
+ *  config->enableWatchdogReset = false;
+ *  config->enableWatchdogProtect = false;
+ *  config->enableLockOscillator = false;
+ *  config->windowValue = 0xFFFFFFU;
+ *  config->timeoutValue = 0xFFFFFFU;
+ *  config->warningValue = 0;
+ * @endcode
+ *
+ * @param config Pointer to WWDT config structure.
+ * @see wwdt_config_t
+ */
+void WWDT_GetDefaultConfig(wwdt_config_t *config);
+
+/*!
+ * @brief Initializes the WWDT.
+ *
+ * This function initializes the WWDT. When called, the WWDT runs according to the configuration.
+ *
+ * Example:
+ * @code
+ *   wwdt_config_t config;
+ *   WWDT_GetDefaultConfig(&config);
+ *   config.timeoutValue = 0x7ffU;
+ *   WWDT_Init(wwdt_base,&config);
+ * @endcode
+ *
+ * @param base   WWDT peripheral base address
+ * @param config The configuration of WWDT
+ */
+void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config);
+
+/*!
+ * @brief Shuts down the WWDT.
+ *
+ * This function shuts down the WWDT.
+ *
+ * @param base WWDT peripheral base address
+ */
+void WWDT_Deinit(WWDT_Type *base);
+
+/* @} */
+
+/*!
+ * @name WWDT Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables the WWDT module.
+ *
+ * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit;
+ * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run
+ * permanently.
+ *
+ * @param base WWDT peripheral base address
+ */
+static inline void WWDT_Enable(WWDT_Type *base)
+{
+    base->MOD |= WWDT_MOD_WDEN_MASK;
+}
+
+/*!
+ * @brief Disables the WWDT module.
+ *
+ * This function write value into WWDT_MOD register to disable the WWDT.
+ *
+ * @param base WWDT peripheral base address
+ */
+static inline void WWDT_Disable(WWDT_Type *base)
+{
+    base->MOD &= ~WWDT_MOD_WDEN_MASK;
+}
+
+/*!
+ * @brief Gets all WWDT status flags.
+ *
+ * This function gets all status flags.
+ *
+ * Example for getting Timeout Flag:
+ * @code
+ *   uint32_t status;
+ *   status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag;
+ * @endcode
+ * @param base        WWDT peripheral base address
+ * @return The status flags. This is the logical OR of members of the
+ *         enumeration ::_wwdt_status_flags_t
+ */
+static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base)
+{
+    return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK));
+}
+
+/*!
+ * @brief Clear WWDT flag.
+ *
+ * This function clears WWDT status flag.
+ *
+ * Example for clearing warning flag:
+ * @code
+ *   WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag);
+ * @endcode
+ * @param base WWDT peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::_wwdt_status_flags_t
+ */
+void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask);
+
+/*!
+ * @brief Set the WWDT warning value.
+ *
+ * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog
+ * interrupt. When the watchdog timer counter is no longer greater than the value defined by
+ * WARNINT, an interrupt will be generated after the subsequent WDCLK.
+ *
+ * @param base         WWDT peripheral base address
+ * @param warningValue WWDT warning value.
+ */
+static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue)
+{
+    base->WARNINT = WWDT_WARNINT_WARNINT(warningValue);
+}
+
+/*!
+ * @brief Set the WWDT timeout value.
+ *
+ * This function sets the timeout value. Every time a feed sequence occurs the value in the TC
+ * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be
+ * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4.
+ * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change
+ * the timeout value before the watchdog counter is below the warning and window values
+ * will cause a watchdog reset and set the WDTOF flag.
+ *
+ * @param base WWDT peripheral base address
+ * @param timeoutCount WWDT timeout value, count of WWDT clock tick.
+ */
+static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount)
+{
+    base->TC = WWDT_TC_COUNT(timeoutCount);
+}
+
+/*!
+ * @brief Sets the WWDT window value.
+ *
+ * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed.
+ * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog
+ * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer
+ * value) so windowing is not in effect.
+ *
+ * @param base        WWDT peripheral base address
+ * @param windowValue WWDT window value.
+ */
+static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)
+{
+    base->WINDOW = WWDT_WINDOW_WINDOW(windowValue);
+}
+
+/*!
+ * @brief Refreshes the WWDT timer.
+ *
+ * This function feeds the WWDT.
+ * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted.
+ *
+ * @param base WWDT peripheral base address
+ */
+void WWDT_Refresh(WWDT_Type *base);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_WWDT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/PeripheralPins.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+/************RTC***************/
+extern const PinMap PinMap_RTC[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+#if defined(FSL_FEATURE_SOC_LPC_CAN_COUNT) && (FSL_FEATURE_SOC_LPC_CAN_COUNT > 0)
+/************CAN***************/
+extern const PinMap PinMap_CAN_TD[];
+extern const PinMap PinMap_CAN_RD[];
+#endif
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_CTS[];
+extern const PinMap PinMap_UART_RTS[];
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+/************PWM***************/
+extern const PinMap PinMap_PWM[];
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/PortNames.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1
+} PortName;
+
+typedef enum {
+    Flexcomm0 = 0,
+    Flexcomm1 = 1,
+    Flexcomm2 = 2,
+    Flexcomm3 = 3,
+    Flexcomm4 = 4,
+    Flexcomm5 = 5,
+    Flexcomm6 = 6,
+    Flexcomm7 = 7,
+    Flexcomm8 = 8,
+    Flexcomm9 = 9
+} FlexcommName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralNames.h"
+#include "fsl_adc.h"
+#include "fsl_power.h"
+#include "PeripheralPins.h"
+
+/* Array of ADC peripheral base address. */
+static ADC_Type *const adc_addrs[] = ADC_BASE_PTRS;
+extern void ADC_ClockPower_Configuration(void);
+
+#define MAX_FADC 6000000
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+    adc_config_t adc_config;
+
+    ADC_ClockPower_Configuration();
+
+    /* Calibration after power up. */
+    if (!(ADC_DoSelfCalibration(adc_addrs[instance]))) {
+        /* Calibration failed */
+        return;
+    }
+
+    ADC_GetDefaultConfig(&adc_config);
+    adc_config.clockDividerNumber = 1;
+
+    ADC_Init(adc_addrs[instance], &adc_config);
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+    uint32_t channel = obj->adc & 0xF;
+    adc_conv_seq_config_t adcConvSeqConfigStruct;
+    adc_result_info_t adcResultInfoStruct;
+
+    adcConvSeqConfigStruct.channelMask = (1U << channel);
+    adcConvSeqConfigStruct.triggerMask = 0U;
+    adcConvSeqConfigStruct.triggerPolarity = kADC_TriggerPolarityNegativeEdge;
+    adcConvSeqConfigStruct.enableSingleStep = false;
+    adcConvSeqConfigStruct.enableSyncBypass = false;
+    adcConvSeqConfigStruct.interruptMode = kADC_InterruptForEachSequence;
+
+    ADC_SetConvSeqAConfig(adc_addrs[instance], &adcConvSeqConfigStruct);
+    ADC_DoSoftwareTriggerConvSeqA(adc_addrs[instance]);
+
+    /* Wait for the converter to be done. */
+    while (!ADC_GetChannelConversionResult(adc_addrs[instance], channel, &adcResultInfoStruct)) {
+    }
+
+    return adcResultInfoStruct.result;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float)value * (1.0f / (float)0xFFFF);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/gpio_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "fsl_gpio.h"
+
+uint32_t gpio_set(PinName pin)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    pin_function(pin, 0);
+
+    return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+    if (pin == (PinName)NC)
+        return;
+
+    pin_function(pin, 0);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t pin_number = obj->pin & 0x1F;
+    uint8_t port_number = obj->pin / 32;
+
+    switch (direction) {
+        case PIN_INPUT:
+            GPIO->DIR[port_number] &= ~(1U << pin_number);
+            break;
+        case PIN_OUTPUT:
+            GPIO->DIR[port_number] |= (1U << pin_number);
+            break;
+    }
+}
+
+void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t pin_number = obj->pin & 0x1F;
+    uint8_t port_number = obj->pin / 32;
+
+    GPIO_WritePinOutput(GPIO, port_number, pin_number, value);
+}
+
+int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t pin_number = obj->pin & 0x1F;
+    uint8_t port_number = obj->pin / 32;
+
+    return (int)GPIO_ReadPinInput(GPIO, port_number, pin_number);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/gpio_irq_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,150 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+
+#include "gpio_irq_api.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "fsl_inputmux.h"
+#include "fsl_pint.h"
+#include "mbed_error.h"
+
+static uint32_t channel_ids[NUMBER_OF_GPIO_INTS] = {0};
+static gpio_irq_handler irq_handler;
+/* Array of PORT IRQ number. */
+static const IRQn_Type pint_irqs[] = PINT_IRQS;
+
+void pint_intr_callback(pint_pin_int_t pintr, uint32_t pmatch_status)
+{
+    uint32_t ch_bit = (1 << pintr);
+
+    // Return immediately if:
+    //   * The interrupt was already served
+    //   * There is no user handler
+    //   * It is a level interrupt, not an edge interrupt
+    if (((PINT->IST & ch_bit) == 0) ||
+        (channel_ids[pintr] == 0) ||
+        (PINT->ISEL & ch_bit)) {
+        return;
+    }
+
+    if ((PINT->IENR & ch_bit) && (PINT->RISE & ch_bit)){
+        irq_handler(channel_ids[pintr], IRQ_RISE);
+        PINT->RISE = ch_bit;
+    }
+
+    if ((PINT->IENF & ch_bit) && (PINT->FALL & ch_bit)) {
+        irq_handler(channel_ids[pintr], IRQ_FALL);
+        PINT->FALL = ch_bit;
+    }
+    PINT_PinInterruptClrStatus(PINT, pintr);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    int found_free_channel = 0;
+    int i = 0;
+
+    if (pin == NC) {
+        return -1;
+    }
+
+    irq_handler = handler;
+
+    for (i = 0; i < NUMBER_OF_GPIO_INTS; i++) {
+        if (channel_ids[i] == 0) {
+            channel_ids[i] = id;
+            obj->ch = i;
+            found_free_channel = 1;
+            break;
+        }
+    }
+
+    if (!found_free_channel) {
+        return -1;
+    }
+
+    obj->pin = pin & 0x1F;
+    obj->port = pin / 32;
+
+    /* Connect trigger sources to PINT */
+    INPUTMUX_Init(INPUTMUX);
+
+    INPUTMUX->PINTSEL[obj->ch] = pin;
+
+    /* Turnoff clock to inputmux to save power. Clock is only needed to make changes */
+    INPUTMUX_Deinit(INPUTMUX);
+
+    /* Initialize PINT */
+    PINT_Init(PINT);
+
+    NVIC_EnableIRQ(pint_irqs[obj->ch]);
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    channel_ids[obj->ch] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    unsigned int ch_bit = (1 << obj->ch);
+
+    // Clear interrupt
+    if (!(PINT->ISEL & ch_bit))
+        PINT->IST = ch_bit;
+
+    // Edge trigger
+    PINT->ISEL &= ~ch_bit;
+
+    /* Setup Pin Interrupt for rising or falling edge */
+    if (enable) {
+        if (event == IRQ_RISE) {
+            /* Checking if falling edge interrupt is already enabled on this pin */
+            if (PINT->IENF & (1U << obj->ch)) {
+                PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableBothEdges, pint_intr_callback);
+            } else {
+                PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableRiseEdge, pint_intr_callback);
+            }
+        } else {
+            /* Checking if rising edge interrupt is already enabled on this pin */
+            if (PINT->IENR & (1U << obj->ch)) {
+                PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableBothEdges, pint_intr_callback);
+            } else {
+                PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableFallEdge, pint_intr_callback);
+            }
+        }
+    } else {
+        PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableNone, NULL);
+    }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    NVIC_EnableIRQ(pint_irqs[obj->ch]);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    NVIC_DisableIRQ(pint_irqs[obj->ch]);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/gpio_object.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+} gpio_t;
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/i2c_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,299 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "fsl_i2c.h"
+#include "PeripheralPins.h"
+
+/* 7 bit IIC addr - R/W flag not included */
+static int i2c_address = 0;
+
+/* Array of I2C peripheral base address. */
+static I2C_Type *const i2c_addrs[] = I2C_BASE_PTRS;
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
+    uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->instance = pinmap_merge(i2c_sda, i2c_scl);
+    obj->next_repeated_start = 0;
+    MBED_ASSERT((int)obj->instance != NC);
+
+    i2c_master_config_t master_config;
+
+    switch (obj->instance) {
+        case 0:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+            RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+            break;
+        case 1:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
+            RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn);
+            break;
+        case 2:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
+            RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
+            break;
+        case 3:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
+            RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn);
+            break;
+        case 4:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+            RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+            break;
+        case 5:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
+            RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
+            break;
+        case 6:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6);
+            RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn);
+            break;
+        case 7:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
+            RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
+            break;
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+        case 8:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8);
+            RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn);
+            break;
+#endif
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+        case 9:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM9);
+            RESET_PeripheralReset(kFC9_RST_SHIFT_RSTn);
+            break;
+#endif
+    }
+
+    I2C_MasterGetDefaultConfig(&master_config);
+    I2C_MasterInit(i2c_addrs[obj->instance], &master_config, 12000000);
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+int i2c_start(i2c_t *obj)
+{
+    I2C_Type *base = i2c_addrs[obj->instance];
+    uint32_t status;
+
+    do
+    {
+        status = I2C_GetStatusFlags(base);
+    } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+    /* Clear controller state. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    /* Start the transfer */
+    base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
+
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    I2C_Type *base = i2c_addrs[obj->instance];
+    uint32_t status;
+
+    do
+    {
+        status = I2C_GetStatusFlags(base);
+    } while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+
+    /* Clear controller state. */
+    I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
+
+    base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
+
+    return 0;
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    I2C_MasterSetBaudRate(i2c_addrs[obj->instance], hz, 12000000);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    I2C_Type *base = i2c_addrs[obj->instance];
+    i2c_master_transfer_t master_xfer;
+
+    i2c_address = address >> 1;
+    memset(&master_xfer, 0, sizeof(master_xfer));
+    master_xfer.slaveAddress = address >> 1;
+    master_xfer.direction = kI2C_Read;
+    master_xfer.data = (uint8_t *)data;
+    master_xfer.dataSize = length;
+    if (obj->next_repeated_start) {
+        master_xfer.flags |= kI2C_TransferRepeatedStartFlag;
+    }
+    if (!stop) {
+        master_xfer.flags |= kI2C_TransferNoStopFlag;
+    }
+    obj->next_repeated_start = master_xfer.flags & kI2C_TransferNoStopFlag ? 1 : 0;
+
+    /* The below function will issue a STOP signal at the end of the transfer.
+     * This is required by the hardware in order to receive the last byte
+     */
+    if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) {
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    I2C_Type *base = i2c_addrs[obj->instance];
+    i2c_master_transfer_t master_xfer;
+
+    if (length == 0) {
+        if (I2C_MasterStart(base, address >> 1, kI2C_Write) != kStatus_Success) {
+            return I2C_ERROR_NO_SLAVE;
+        }
+
+        if (((I2C_GetStatusFlags(base) & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) {
+            i2c_stop(obj);
+            return I2C_ERROR_NO_SLAVE;
+        } else {
+            i2c_stop(obj);
+            return length;
+        }
+    }
+
+    memset(&master_xfer, 0, sizeof(master_xfer));
+    master_xfer.slaveAddress = address >> 1;
+    master_xfer.direction = kI2C_Write;
+    master_xfer.data = (uint8_t *)data;
+    master_xfer.dataSize = length;
+    if (obj->next_repeated_start) {
+        master_xfer.flags |= kI2C_TransferRepeatedStartFlag;
+    }
+    if (!stop) {
+        master_xfer.flags |= kI2C_TransferNoStopFlag;
+    }
+    obj->next_repeated_start = master_xfer.flags & kI2C_TransferNoStopFlag ? 1 : 0;
+
+    if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) {
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    return length;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    uint8_t data;
+    I2C_Type *base = i2c_addrs[obj->instance];
+    i2c_master_transfer_t master_xfer;
+
+    memset(&master_xfer, 0, sizeof(master_xfer));
+    master_xfer.slaveAddress = i2c_address;
+    master_xfer.direction = kI2C_Read;
+    master_xfer.data = &data;
+    master_xfer.dataSize = 1;
+
+    if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) {
+        return I2C_ERROR_NO_SLAVE;
+    }
+    return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    status_t ret_value;
+
+    ret_value = I2C_MasterWriteBlocking(i2c_addrs[obj->instance], (uint8_t *)(&data), 1, kI2C_TransferNoStopFlag);
+
+    if (ret_value == kStatus_Success) {
+        return 1;
+    } else if (ret_value == kStatus_I2C_Nak) {
+        return 0;
+    } else {
+        return 2;
+    }
+}
+
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+    i2c_slave_config_t slave_config;
+    I2C_SlaveGetDefaultConfig(&slave_config);
+    slave_config.enableSlave = (bool)enable_slave;
+
+    I2C_SlaveInit(i2c_addrs[obj->instance], &slave_config, 12000000);
+}
+
+int i2c_slave_receive(i2c_t *obj)
+{
+    uint32_t status_flags = I2C_GetStatusFlags(i2c_addrs[obj->instance]);
+
+    if (status_flags & kI2C_SlaveSelected) {
+        if (((status_flags >> I2C_STAT_SLVSTATE_SHIFT) & I2C_STAT_SLVSTATE_MASK) == 0x1) {
+            // read addressed
+            return 1;
+        } else {
+            // write addressed
+            return 3;
+        }
+    } else {
+        // slave not addressed
+        return 0;
+    }
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+    I2C_Type *base = i2c_addrs[obj->instance];
+
+    I2C_SlaveReadBlocking(base, (uint8_t *)data, length);
+
+    return length;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+    I2C_Type *base = i2c_addrs[obj->instance];
+
+    I2C_SlaveWriteBlocking(base, (uint8_t *)data, length);
+
+    return length;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
+{
+    if ((idx >= 0) && (idx <= 3)) {
+        I2C_SlaveSetAddress(i2c_addrs[obj->instance], (i2c_slave_address_register_t)idx, address, false);
+    }
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/objects.h	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t port;
+    uint32_t pin;
+    uint32_t ch;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    PWMName pwm_name;
+};
+
+struct serial_s {
+    int index;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+struct i2c_s {
+    uint32_t instance;
+    uint8_t next_repeated_start;
+};
+
+struct spi_s {
+    uint32_t instance;
+    uint8_t bits;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/pinmap.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "fsl_common.h"
+
+void pin_function(PinName pin, int function)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    clock_ip_name_t gpio_clocks[] = GPIO_CLOCKS;
+    uint32_t pin_number = pin & 0x1F;
+    uint8_t port_number = pin / 32;
+    uint32_t reg;
+
+    CLOCK_EnableClock(gpio_clocks[port_number]);
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    reg = IOCON->PIO[port_number][pin_number];
+    reg = (reg & ~0x7) | (function & 0x7);
+    IOCON->PIO[port_number][pin_number] = reg;
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t pin_number = pin & 0x1F;
+    uint8_t port_number = pin / 32;
+    uint32_t reg = IOCON->PIO[port_number][pin_number] & ~IOCON_PIO_MODE_MASK;
+
+    switch (mode) {
+        case PullNone:
+            break;
+        case PullDown:
+            reg |= (1 << IOCON_PIO_MODE_SHIFT);
+            break;
+        case PullUp:
+            reg |= (2 << IOCON_PIO_MODE_SHIFT);
+            break;
+        default:
+            break;
+    }
+
+    IOCON->PIO[port_number][pin_number] = reg;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/port_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "fsl_gpio.h"
+
+PinName port_pin(PortName port, int pin_n)
+{
+    return (PinName)((port << PORT_SHIFT) | pin_n);;
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    uint32_t i;
+
+    obj->port = port;
+    obj->mask = mask;
+
+    GPIO->MASK[port] = ~mask;
+
+    // The function is set per pin: reuse gpio logic
+    for (i = 0; i < 32; i++) {
+        if (obj->mask & (1 << i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+
+    // The mode is set per pin: reuse pinmap logic
+    for (i = 0; i < 32; i++) {
+        if (obj->mask & (1 << i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    switch (dir) {
+        case PIN_INPUT:
+            GPIO->DIR[obj->port] &= ~obj->mask;
+            break;
+        case PIN_OUTPUT:
+            GPIO->DIR[obj->port] |=  obj->mask;
+            break;
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    GPIO_WriteMPort(GPIO, obj->port, value);
+}
+
+int port_read(port_t *obj)
+{
+    return (int)(GPIO_ReadMPort(GPIO, obj->port));
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/rtc_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "pinmap.h"
+#include "fsl_rtc.h"
+#include "PeripheralPins.h"
+
+extern void rtc_setup_oscillator(void);
+
+void rtc_init(void)
+{
+    rtc_setup_oscillator();
+
+    RTC_Init(RTC);
+
+    RTC_StartTimer(RTC);
+}
+
+void rtc_free(void)
+{
+    RTC_Deinit(RTC);
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ * 0 = Disabled, 1 = Enabled
+ */
+int rtc_isenabled(void)
+{
+    CLOCK_EnableClock(kCLOCK_Rtc);
+    return (int)((RTC->CTRL & RTC_CTRL_RTC_EN_MASK) >> RTC_CTRL_RTC_EN_SHIFT);
+}
+
+time_t rtc_read(void)
+{
+    return (time_t)RTC->COUNT;
+}
+
+void rtc_write(time_t t)
+{
+    if (t == 0) {
+        t = 1;
+    }
+    RTC_StopTimer(RTC);
+    RTC->COUNT = t;
+    RTC_StartTimer(RTC);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/serial_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,384 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include "mbed_assert.h"
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "fsl_usart.h"
+#include "PeripheralPins.h"
+#include "clock_config.h"
+
+static uint32_t serial_irq_ids[FSL_FEATURE_SOC_USART_COUNT] = {0};
+static uart_irq_handler irq_handler;
+/* Array of UART peripheral base address. */
+static USART_Type *const uart_addrs[] = USART_BASE_PTRS;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+    obj->index = pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)obj->index != NC);
+
+    usart_config_t config;
+
+    switch (obj->index) {
+        case 0:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+            RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+            break;
+        case 1:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
+            RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn);
+            break;
+        case 2:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
+            RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
+            break;
+        case 3:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
+            RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn);
+            break;
+        case 4:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+            RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+            break;
+        case 5:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
+            RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
+            break;
+        case 6:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6);
+            RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn);
+            break;
+        case 7:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
+            RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
+            break;
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+        case 8:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8);
+            RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn);
+            break;
+#endif
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+        case 9:
+            CLOCK_AttachClk(kFRO12M_to_FLEXCOMM9);
+            RESET_PeripheralReset(kFC9_RST_SHIFT_RSTn);
+            break;
+#endif
+    }
+
+    USART_GetDefaultConfig(&config);
+    config.baudRate_Bps = 9600;
+    config.enableTx = true;
+    config.enableRx = true;
+
+    USART_Init(uart_addrs[obj->index], &config, 12000000);
+
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    if (tx != NC) {
+        pin_mode(tx, PullUp);
+    }
+    if (rx != NC) {
+        pin_mode(rx, PullUp);
+    }
+
+    if (obj->index == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    USART_Deinit(uart_addrs[obj->index]);
+    serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    USART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, 12000000);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    USART_Type *base = uart_addrs[obj->index];
+    uint8_t temp;
+
+    /* Set bit count and parity mode. */
+    temp = base->CFG & ~(USART_CFG_PARITYSEL_MASK | USART_CFG_DATALEN_MASK | USART_CFG_STOPLEN_MASK);
+
+    if (parity != ParityNone)
+    {
+        /* Enable Parity */
+        if (parity == ParityOdd) {
+            temp |= USART_CFG_PARITYSEL(3U);
+        } else if (parity == ParityEven) {
+            temp |= USART_CFG_PARITYSEL(2U);
+        } else {
+            // Hardware does not support forced parity
+            MBED_ASSERT(0);
+        }
+    }
+
+    /* Set stop bits */
+    if (stop_bits == 2) {
+        temp |= USART_CFG_STOPLEN(1U);
+    }
+
+    /* Set Data size */
+    if (data_bits == 8) {
+        temp |= USART_CFG_DATALEN(1U);
+    } else {
+        temp |= USART_CFG_DATALEN(2U);
+    }
+
+    base->CFG = temp;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index)
+{
+    if (serial_irq_ids[index] != 0) {
+        if (transmit_empty)
+            irq_handler(serial_irq_ids[index], TxIrq);
+
+        if (receive_full)
+            irq_handler(serial_irq_ids[index], RxIrq);
+    }
+}
+
+void uart0_irq()
+{
+    uint32_t status_flags = USART0->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 0);
+}
+
+void uart1_irq()
+{
+    uint32_t status_flags = USART1->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 1);
+}
+
+void uart2_irq()
+{
+    uint32_t status_flags = USART2->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 2);
+}
+
+void uart3_irq()
+{
+    uint32_t status_flags = USART3->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 3);
+}
+
+void uart4_irq()
+{
+    uint32_t status_flags = USART4->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 4);
+}
+
+void uart5_irq()
+{
+    uint32_t status_flags = USART5->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 5);
+}
+
+void uart6_irq()
+{
+    uint32_t status_flags = USART6->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 6);
+}
+
+void uart7_irq()
+{
+    uint32_t status_flags = USART7->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 7);
+}
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+void uart8_irq()
+{
+    uint32_t status_flags = USART8->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 8);
+}
+#endif
+
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+void uart9_irq()
+{
+    uint32_t status_flags = USART9->FIFOSTAT;
+    uart_irq((status_flags & kUSART_TxFifoEmptyFlag), (status_flags & kUSART_RxFifoFullFlag), 9);
+}
+#endif
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    IRQn_Type uart_irqs[] = USART_IRQS;
+    uint32_t vector = 0;
+
+    switch (obj->index) {
+        case 0:
+            vector = (uint32_t)&uart0_irq;
+            break;
+        case 1:
+            vector = (uint32_t)&uart1_irq;
+            break;
+        case 2:
+            vector = (uint32_t)&uart2_irq;
+            break;
+        case 3:
+            vector = (uint32_t)&uart3_irq;
+            break;
+        case 4:
+            vector = (uint32_t)&uart4_irq;
+            break;
+        case 5:
+            vector = (uint32_t)&uart5_irq;
+            break;
+        case 6:
+            vector = (uint32_t)&uart6_irq;
+            break;
+        case 7:
+            vector = (uint32_t)&uart7_irq;
+            break;
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+        case 8:
+            vector = (uint32_t)&uart8_irq;
+            break;
+#endif
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+        case 9:
+            vector = (uint32_t)&uart9_irq;
+            break;
+#endif
+        default:
+            break;
+    }
+
+    if (enable) {
+        switch (irq) {
+            case RxIrq:
+                USART_EnableInterrupts(uart_addrs[obj->index], kUSART_RxLevelInterruptEnable);
+                break;
+            case TxIrq:
+                USART_EnableInterrupts(uart_addrs[obj->index], kUSART_TxLevelInterruptEnable);
+                break;
+            default:
+                break;
+        }
+        NVIC_SetVector(uart_irqs[obj->index], vector);
+        NVIC_EnableIRQ(uart_irqs[obj->index]);
+
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+        switch (irq) {
+            case RxIrq:
+                USART_DisableInterrupts(uart_addrs[obj->index], kUSART_RxLevelInterruptEnable);
+                break;
+            case TxIrq:
+                USART_DisableInterrupts(uart_addrs[obj->index], kUSART_TxLevelInterruptEnable);
+                break;
+            default:
+                break;
+        }
+        switch (other_irq) {
+            case RxIrq:
+                all_disabled = (((uart_addrs[obj->index]->FIFOINTENSET) & kUSART_RxLevelInterruptEnable) == 0);
+                break;
+            case TxIrq:
+                all_disabled = (((uart_addrs[obj->index]->FIFOINTENSET) & kUSART_TxLevelInterruptEnable)== 0);
+                break;
+            default:
+                break;
+        }
+        if (all_disabled)
+            NVIC_DisableIRQ(uart_irqs[obj->index]);
+    }
+}
+
+int serial_getc(serial_t *obj)
+{
+    while (!serial_readable(obj));
+    uint8_t data;
+    data = USART_ReadByte(uart_addrs[obj->index]);
+
+    return data;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    while (!serial_writable(obj));
+    USART_WriteByte(uart_addrs[obj->index], (uint8_t)c);
+}
+
+int serial_readable(serial_t *obj)
+{
+    uint32_t status_flags = USART_GetStatusFlags(uart_addrs[obj->index]);
+
+    return (status_flags & kUSART_RxFifoNotEmptyFlag);
+}
+
+int serial_writable(serial_t *obj)
+{
+    uint32_t status_flags = USART_GetStatusFlags(uart_addrs[obj->index]);
+
+    return (status_flags & kUSART_TxFifoNotFullFlag);
+}
+
+void serial_clear(serial_t *obj)
+{
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+    uart_addrs[obj->index]->CTL |= USART_CTL_TXBRKEN_MASK;
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    uart_addrs[obj->index]->CTL &= ~USART_CTL_TXBRKEN_MASK;
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/sleep.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "fsl_power.h"
+#include "clock_config.h"
+
+void hal_sleep(void)
+{
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __WFI();
+}
+
+void hal_deepsleep(void)
+{
+    LPC_CLOCK_INTERNAL_IRC();
+    /* Enter Deep Sleep mode */
+    POWER_EnterDeepSleep(APP_EXCLUDE_FROM_DEEPSLEEP);
+    LPC_CLOCK_RUN();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,191 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+#include "mbed_assert.h"
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "fsl_spi.h"
+#include "PeripheralPins.h"
+
+/* Array of SPI peripheral base address. */
+static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    // determine the SPI to use
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+
+    obj->instance = pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->instance != NC);
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj)
+{
+    SPI_Deinit(spi_address[obj->instance]);
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    spi_master_config_t master_config;
+    spi_slave_config_t slave_config;
+
+    /* Bits: values between 4 and 16 are valid */
+    MBED_ASSERT(bits >= 4 && bits <= 16);
+    obj->bits = bits;
+
+    if (slave) {
+        /* Slave config */
+        SPI_SlaveGetDefaultConfig(&slave_config);
+        slave_config.dataWidth = (uint32_t)bits - 1;
+        slave_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
+        slave_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
+
+        SPI_SlaveInit(spi_address[obj->instance], &slave_config);
+    } else {
+        /* Master config */
+        SPI_MasterGetDefaultConfig(&master_config);
+        master_config.dataWidth = (uint32_t)bits - 1;
+        master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
+        master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
+        master_config.direction = kSPI_MsbFirst;
+
+        switch (obj->instance) {
+            case 0:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+                RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
+                break;
+            case 1:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
+                RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn);
+                break;
+            case 2:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
+                RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
+                break;
+            case 3:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
+                RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn);
+                break;
+            case 4:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+                RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+                break;
+            case 5:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
+                RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
+                break;
+            case 6:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6);
+                RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn);
+                break;
+            case 7:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
+                RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
+                break;
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
+            case 8:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8);
+                RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn);
+                break;
+#endif
+#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
+            case 9:
+                CLOCK_AttachClk(kFRO12M_to_FLEXCOMM9);
+                RESET_PeripheralReset(kFC9_RST_SHIFT_RSTn);
+                break;
+#endif
+
+        }
+
+        SPI_MasterInit(spi_address[obj->instance], &master_config, 12000000);
+    }
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+    SPI_MasterSetBaud(spi_address[obj->instance], (uint32_t)hz, 12000000);
+}
+
+static inline int spi_readable(spi_t * obj)
+{
+    return (SPI_GetStatusFlags(spi_address[obj->instance]) & kSPI_RxNotEmptyFlag);
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+    uint32_t rx_data;
+
+    SPI_WriteData(spi_address[obj->instance], (uint16_t)value, kSPI_FrameAssert);
+    // wait rx buffer full
+    while (!spi_readable(obj));
+    rx_data = SPI_ReadData(spi_address[obj->instance]);
+    return rx_data & 0xffff;
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, 
+                           char *rx_buffer, int rx_length, char write_fill) {
+    int total = (tx_length > rx_length) ? tx_length : rx_length;
+
+    for (int i = 0; i < total; i++) {
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+        char in = spi_master_write(obj, out);
+        if (i < rx_length) {
+            rx_buffer[i] = in;
+        }
+    }
+
+    return total;
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+    return spi_readable(obj);
+}
+
+int spi_slave_read(spi_t *obj)
+{
+    uint32_t rx_data;
+
+    while (!spi_readable(obj));
+    rx_data = SPI_ReadData(spi_address[obj->instance]);
+    return rx_data & 0xffff;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    SPI_WriteData(spi_address[obj->instance], (uint16_t)value, 0);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/us_ticker.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "fsl_ctimer.h"
+#include "PeripheralNames.h"
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    ctimer_config_t config;
+
+    if (us_ticker_inited) {
+        return;
+    }
+
+    us_ticker_inited = 1;
+
+    uint32_t pclk = CLOCK_GetFreq(kCLOCK_BusClk);
+    uint32_t prescale = pclk / 1000000; // default to 1MHz (1 us ticks)
+
+    CTIMER_GetDefaultConfig(&config);
+    config.prescale = prescale - 1;
+    CTIMER_Init(CTIMER1, &config);
+    CTIMER_Reset(CTIMER1);
+    CTIMER_StartTimer(CTIMER1);
+
+    NVIC_SetVector(CTIMER1_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(CTIMER1_IRQn);
+}
+
+uint32_t us_ticker_read(void) {
+    if (!us_ticker_inited)
+        us_ticker_init();
+
+    return CTIMER1->TC;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp) {
+    ctimer_match_config_t matchConfig;
+
+    matchConfig.enableCounterReset = false;
+    matchConfig.enableCounterStop = false;
+    matchConfig.matchValue = (uint32_t)timestamp;
+    matchConfig.outControl = kCTIMER_Output_NoAction;
+    matchConfig.outPinInitState = true;
+    matchConfig.enableInterrupt = true;
+
+    CTIMER_SetupMatch(CTIMER1, kCTIMER_Match_0, &matchConfig);
+}
+
+void us_ticker_disable_interrupt(void) {
+    CTIMER1->MCR &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+    CTIMER1->IR = 1;
+}
+
+void us_ticker_fire_interrupt(void)
+{
+    NVIC_SetPendingIRQ(CTIMER1_IRQn);
+}

--- a/targets/TARGET_NXP/mbed_rtx.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_NXP/mbed_rtx.h	Thu Aug 03 13:13:39 2017 +0100
@@ -80,6 +80,18 @@
 #define INITIAL_SP              (0x10002000UL)
 #endif
 
+#elif defined(TARGET_LPC54114_M4)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (0x20010000UL)
+#endif
+
+#elif defined(TARGET_LPC54608)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (0x20028000UL)
+#endif
+
 #endif
 
 #endif  // MBED_MBED_RTX_H

--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -83,11 +83,12 @@
     return(fSpiWriteB(obj, value));
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -260,11 +260,12 @@
     return spi_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -311,11 +311,12 @@
     return spi_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar has changed

Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar has changed

Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a has changed

Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a has changed

Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a has changed

Binary file targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a has changed

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h	Thu Aug 03 13:13:39 2017 +0100
@@ -32,7 +32,7 @@
 #include "hal_efuse.h"
 #include "hal_soc_ps_monitor.h"
 #include "diag.h"
-
+#include "system_8195a.h"
 
 // from RDC team
 #ifdef CONFIG_MBED_ENABLED

--- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -15,10 +15,6 @@
  */
 #include "flash_ext.h"
 
-#define FLASH_START       (SPI_FLASH_BASE + FLASH_OFS_START)
-#define FLASH_END         (SPI_FLASH_BASE + FLASH_OFS_END)
-#define FLASH_OFS(addr)   ((addr) - SPI_FLASH_BASE)
-
 int32_t flash_init(flash_t *obj)
 {
     __flash_ext_turnon();
@@ -35,20 +31,25 @@
 
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
-    __flash_ext_erase_sector(obj, FLASH_OFS(address));
+    flash_ext_erase_sector(obj, address);
 
     return 0;
 }
 
+int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
+{
+    return flash_ext_stream_read(obj, address, size, data);;
+}
+
 int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
 {
-    return __flash_ext_stream_write(obj, FLASH_OFS(address), size, data);
+    return flash_ext_stream_write(obj, address, size, data);
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
 {
-    if (address < FLASH_START || address >= FLASH_END)
-        return 0;
+    if (address >= FLASH_OFS_END)
+        return MBED_FLASH_INVALID_SIZE;
 
     return FLASH_SECTOR_SIZE;
 }
@@ -60,7 +61,7 @@
 
 uint32_t flash_get_start_address(const flash_t *obj)
 {
-    return FLASH_START;
+    return FLASH_OFS_START;
 }
 
 uint32_t flash_get_size(const flash_t *obj)

--- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.c	Thu Aug 03 13:13:39 2017 +0100
@@ -128,7 +128,7 @@
     __flash_ext_turnon();
 
     SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
-    
+
     offset = addr & 0x03;
     addr = addr & ~0x03;
     pbuf = data;
@@ -189,13 +189,13 @@
     uint32_t i, offset, word;
     const uint8_t*pbuf;
     uint8_t *ptr;
-    u8 flashtype = 0; 
+    u8 flashtype = 0;
 
     offset = addr & 0x03;
     addr = addr & ~0x03;
     pbuf = data;
     flashtype = flashobj.SpicInitPara.flashtype;
-    
+
     if (offset != 0) {
         word = HAL_READ32(SPI_FLASH_BASE, addr);
         ptr = (uint8_t *)&word + offset;
@@ -207,7 +207,7 @@
         }
         HAL_WRITE32(SPI_FLASH_BASE, addr, word);
         SpicWaitBusyDoneRtl8195A();
-        
+
         if(flashtype == FLASH_MICRON){
             SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
         } else {
@@ -222,7 +222,7 @@
                 ((uint32_t)(*(pbuf+2)) << 16) | ((uint32_t)(*(pbuf+3)) << 24);
             HAL_WRITE32(SPI_FLASH_BASE, addr, word);
             SpicWaitBusyDoneRtl8195A();
-            
+
             if(flashtype == FLASH_MICRON){
                 SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
             } else {
@@ -237,7 +237,7 @@
         while (len >= 4) {
             HAL_WRITE32(SPI_FLASH_BASE, addr, (uint32_t)*((uint32_t *)pbuf));
             SpicWaitBusyDoneRtl8195A();
-            
+
             if(flashtype == FLASH_MICRON){
                 SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
             } else {
@@ -260,7 +260,7 @@
 
         HAL_WRITE32(SPI_FLASH_BASE, addr, word);
         SpicWaitBusyDoneRtl8195A();
-        
+
         if(flashtype == FLASH_MICRON){
             SpicWaitOperationDoneRtl8195A(flashobj.SpicInitPara);
         } else {
@@ -271,7 +271,7 @@
     return 0;
 }
 
-int flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data)
+int flash_ext_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data)
 {
     int32_t status;
 
@@ -287,7 +287,7 @@
     return flash_ext_stream_read(obj, addr, len, data);
 }
 
-int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data)
+int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data)
 {
     return flash_ext_stream_write(obj, addr, len, data);
 }
@@ -308,7 +308,7 @@
 */
 
 int flash_ext_burst_write(flash_t *obj, uint32_t address ,uint32_t length, uint8_t *data)
-{    
+{
     u32 OccuSize;
     u32 ProgramSize;
     u32 PageSize;
@@ -340,7 +340,7 @@
             }
 
             address += ProgramSize;
-            data += ProgramSize;   
+            data += ProgramSize;
             length -= ProgramSize;
             OccuSize = 0;
         } else{
@@ -435,7 +435,7 @@
 void flash_ext_reset_status(flash_t *obj)
 {
     __flash_ext_turnon();
-    SpicSetFlashStatusRefinedRtl8195A(0, flashobj.SpicInitPara);    
+    SpicSetFlashStatusRefinedRtl8195A(0, flashobj.SpicInitPara);
     SpicWaitWipDoneRefinedRtl8195A(flashobj.SpicInitPara);
     __flash_ext_turnoff();
 }

--- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h	Thu Aug 03 13:13:39 2017 +0100
@@ -25,17 +25,17 @@
 
 #define FLASH_PAGE_SIZE 256
 #define FLASH_SIZE        0x100000
-#define FLASH_OFS_START   0xc0000
+#define FLASH_OFS_START   0x0
 #define FLASH_OFS_END     (FLASH_OFS_START + FLASH_SIZE)
 
 extern void flash_ext_erase_sector(flash_t *obj, uint32_t address);
 extern void flash_ext_erase_block(flash_t * obj, uint32_t address);
-extern int flash_ext_read_word(flash_t *obj, uint32_t address, uint32_t * data);
+extern int flash_ext_read_word(flash_t *obj, uint32_t address, uint32_t *data);
 extern int flash_ext_write_word(flash_t *obj, uint32_t address, uint32_t data);
-extern int flash_ext_stream_read(flash_t *obj, uint32_t address, uint32_t len, uint8_t * data);
-extern int flash_ext_stream_write(flash_t *obj, uint32_t address, uint32_t len, uint8_t * data);
+extern int flash_ext_stream_read(flash_t *obj, uint32_t address, uint32_t len, uint8_t *data);
+extern int flash_ext_stream_write(flash_t *obj, uint32_t address, uint32_t len, const uint8_t *data);
 extern int flash_stream_read(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data);
-extern int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, uint8_t *data);
+extern int flash_stream_write(flash_t *obj, uint32_t addr, uint32_t len, const uint8_t *data);
 extern void flash_ext_write_protect(flash_t *obj, uint32_t protect);
 extern int flash_ext_get_status(flash_t *obj);
 extern int flash_ext_set_status(flash_t *obj, uint32_t data);

--- a/targets/TARGET_Realtek/TARGET_AMEBA/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -241,12 +241,13 @@
     return ssi_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length)
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill)
 {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,238 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * USB capable         | NO
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32f0xx.h"
+#include "mbed_assert.h"
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+    /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO pin(PA8) for debugging purpose
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    //Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select HSE oscillator as PLL source
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+    }
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,477 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 48 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
-                                                 This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 48000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
-  /* Reset PREDIV[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  
-#else
- #warning "No target selected"
-#endif
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-  /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
-      }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
-      {
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
-      }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
-      else
-      {
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
-          STM32F091xC || STM32F098xx || STM32F030xC */
-      }
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  //Select HSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  
-  // Select HSE oscillator as PLL source
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0) {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  } else {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
-  }
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-  
-//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
- 
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
-  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
-  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
-  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
-  
-  return 1; // OK
-}
-
-/* Used for the different timeouts in the HAL */
-void SysTick_Handler(void)
-{
-  HAL_IncTick();
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
     {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
-    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - Connected to STDIO_UART_RX
     {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
     {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
     {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
@@ -109,14 +109,14 @@
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
     {NC,    NC,     0}
 };
 
 const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * USB capable         | NO
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32f0xx.h"
+#include "mbed_assert.h"
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+    /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO pin(PA8) for debugging purpose
+    // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    //Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+
+    // Select HSE oscillator as PLL source
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+    }
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,471 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 48 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
-                                                 This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 48000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
-  /* Reset PREDIV[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  
-#else
- #warning "No target selected"
-#endif
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-  /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
-      }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
-      {
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
-      }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
-      else
-      {
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
-          STM32F091xC || STM32F098xx || STM32F030xC */
-      }
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  //Select HSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  
-  // Select HSE oscillator as PLL source
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0) {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  } else {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
-  }
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-  
-//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
- 
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
-  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
-  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
-  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -41,7 +41,7 @@
 const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
     {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
     {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
     {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
     {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
@@ -74,7 +74,7 @@
 // TIM2 cannot be used because already used by the us_ticker
 const PinMap PinMap_PWM[] = {
 //  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  3, 0)},  // TIM2_CH3
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  3, 0)},  // TIM2_CH3 - Connected to STDIO_UART_TX
 //  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  4, 0)},  // TIM2_CH4
     {PA_4,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
     {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  1, 0)},  // TIM3_CH1
@@ -104,7 +104,7 @@
 
 const PinMap PinMap_UART_TX[] = {
     {PA_1,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
-    {PA_2,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // STDIO TX
+    {PA_2,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // Connected to STDIO_UART_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
 //  {PA_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // SWCLK
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
@@ -114,7 +114,7 @@
 const PinMap PinMap_UART_RX[] = {
     {PA_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
-    {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // STDIO RX
+    {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // Connected to STDIO_UART_RX
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
     {NC,    NC,     0}
 };
@@ -153,6 +153,6 @@
 
 const PinMap PinMap_SPI_SSEL[] = {
     {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX
     {NC,    NC,    0}
 };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * USB capable         | NO
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32f0xx.h"
+#include "mbed_assert.h"
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO - not connected by default)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+    /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO pin(PA8) for debugging purpose */
+// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    //Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+
+    // Select HSE oscillator as PLL source
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+    }
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/system_stm32f0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,471 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 48 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
-                                                 This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 48000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
-  /* Reset PREDIV[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  
-#else
- #warning "No target selected"
-#endif
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-  /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
-      }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
-      {
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
-      }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
-      else
-      {
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
-          STM32F091xC || STM32F098xx || STM32F030xC */
-      }
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  //Select HSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  
-  // Select HSE oscillator as PLL source
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0) {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  } else {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
-  }
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-  
-//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
- 
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
-  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
-  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
-  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -41,7 +41,7 @@
 const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
     {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
     {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
     {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
     {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
@@ -79,7 +79,7 @@
 // TIM2 cannot be used because already used by the us_ticker
 const PinMap PinMap_PWM[] = {
 //  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  3, 0)},  // TIM2_CH3
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  3, 0)},  // TIM2_CH3 - Connected to STDIO_UART_TX
 //  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  4, 0)},  // TIM2_CH4
     {PA_4,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
     {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  1, 0)},  // TIM3_CH1
@@ -109,7 +109,7 @@
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // STDIO TX
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
 //  {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // SWCLK
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
@@ -119,7 +119,7 @@
 const PinMap PinMap_UART_RX[] = {
     {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
-    {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // STDIO RX
+    {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
     {NC,    NC,     0}
 };
@@ -158,7 +158,7 @@
 
 const PinMap PinMap_SPI_SSEL[] = {
     {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX
     {NC,    NC,    0}
 };
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32f0xx.h"
+#include "mbed_assert.h"
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO - not connected by default)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+    /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO pin(PA8) for debugging purpose */
+// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    //Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+
+    // Select HSE oscillator as PLL source
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+    }
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL6;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL6;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,471 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 48 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
-                                                 This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 48000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
-  /* Reset PREDIV[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  
-#else
- #warning "No target selected"
-#endif
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-  /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
-      }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
-      {
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
-      }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
-      else
-      {
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
-          STM32F091xC || STM32F098xx || STM32F030xC */
-      }
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  //Select HSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  
-  // Select HSE oscillator as PLL source
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0) {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  } else {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
-  }
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-  
-//  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
- 
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
-  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
-  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
-  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL6;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
     {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
-    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - Connected to STDIO_UART_RX
     {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
     {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
     {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
@@ -84,8 +84,8 @@
 // TIM1 cannot be used because already used by the us_ticker
 const PinMap PinMap_PWM[] = {
     {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N
-    {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 1, 0)}, // TIM15_CH1
-    {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 2, 0)}, // TIM15_CH2
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 2, 0)}, // TIM15_CH2 - Connected to STDIO_UART_RX
     {PA_4,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
 //  {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3,  1, 0)},  // TIM3_CH1
     {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1
@@ -128,7 +128,7 @@
 
 const PinMap PinMap_UART_TX[] = {
     {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Warning: SWCLK is also on this pin
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
@@ -141,7 +141,7 @@
 
 const PinMap PinMap_UART_RX[] = {
     {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32f0xx.h"
+#include "mbed_assert.h"
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+    /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO pin(PA8) for debugging purpose
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    //Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select HSE oscillator as PLL source
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+    }
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO pin(PA8) for debugging purpose
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2; // HSI div 2
+    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/system_stm32f0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,476 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 48 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
-                                                 This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 48000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
-  /* Reset PREDIV[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  
-#else
- #warning "No target selected"
-#endif
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-  /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
-      }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
-      {
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
-      }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
-      else
-      {
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
-          STM32F091xC || STM32F098xx || STM32F030xC */
-      }
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  //Select HSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  
-  // Select HSE oscillator as PLL source
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0) {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  } else {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
-  }
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
- 
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
-  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
-  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
-  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2; // HSI div 2
-  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
     {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
+//  {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - Connected to STDIO_UART_RX
     {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
     {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
     {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
@@ -93,9 +93,9 @@
 const PinMap PinMap_PWM[] = {
 //  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
     {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N
-    {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 1, 0)}, // TIM15_CH1
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX
 //  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  3, 0)},  // TIM2_CH3
-    {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 2, 0)}, // TIM15_CH2
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 2, 0)}, // TIM15_CH2 - Connected to STDIO_UART_RX
 //  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  4, 0)},  // TIM2_CH4
     {PA_4,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
 //  {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3,  1, 0)},  // TIM3_CH1
@@ -142,7 +142,7 @@
 
 const PinMap PinMap_UART_TX[] = {
     {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Warning: SWCLK is also on this pin
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
@@ -155,7 +155,7 @@
 
 const PinMap PinMap_UART_RX[] = {
     {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32f0xx.h"
+#include "mbed_assert.h"
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+    /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO pin(PA8) for debugging purpose
+    // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    //Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select HSE oscillator as PLL source
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+    }
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO pin(PA8) for debugging purpose
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/system_stm32f0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,475 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 48 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
-                                                 This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 48000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
-  /* Reset PREDIV[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  
-#else
- #warning "No target selected"
-#endif
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-  /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
-      }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
-      {
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
-      }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
-      else
-      {
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
-          STM32F091xC || STM32F098xx || STM32F030xC */
-      }
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  //Select HSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  
-  // Select HSE oscillator as PLL source
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0) {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  } else {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
-  }
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-  
-  // Output clock on MCO pin(PA8) for debugging purpose
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
- 
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
-  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
-  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
-  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
     {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
+//  {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - Connected to STDIO_UART_RX
     {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
     {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
     {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
@@ -55,6 +55,10 @@
     {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC_IN13
     {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC_IN14
     {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC_IN15
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18
@@ -99,10 +103,10 @@
 const PinMap PinMap_PWM[] = {
 //  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
     {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N
-    {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 1, 0)}, // TIM15_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH3
-    {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 2, 0)}, // TIM15_CH2
-//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  4, 0)},  // TIM2_CH4
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH3 - Connected to STDIO_UART_TX
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM15, 2, 0)}, // TIM15_CH2 - Connected to STDIO_UART_RX
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  4, 0)},  // TIM2_CH4 - Connected to STDIO_UART_RX
     {PA_4,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
 //  {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3,  1, 0)},  // TIM3_CH1
     {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1
@@ -148,7 +152,7 @@
 
 const PinMap PinMap_UART_TX[] = {
     {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX
     {PA_4,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART6)},
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Warning: SWCLK is also on this pin
@@ -169,7 +173,7 @@
 
 const PinMap PinMap_UART_RX[] = {
     {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)},
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX
     {PA_5,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART6)},
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * USB capable         | NO
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32f0xx.h"
+#include "mbed_assert.h"
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+    /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output system clock on MCO pin(PA8) for debugging purpose
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV8); // 48MHz/8=6MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    //Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select HSE oscillator as PLL source
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+    }
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output HSE clock on MCO pin(PA8) for debugging purpose
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8MHz/2=4MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 8MHz/4=2MHz with ST-Link MCO
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+    RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output HSI clock on MCO1 pin(PA8) for debugging purpose
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV2); // 8MHz/2=4MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/system_stm32f0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,474 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    04-November-2016
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 48 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 48
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
-                                                 This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 48000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
-  /* Reset PREDIV[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  
-#else
- #warning "No target selected"
-#endif
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-  /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
-  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
-      }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
-      {
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
-      }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
-      else
-      {
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
-          STM32F091xC || STM32F098xx || STM32F030xC */
-      }
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // HSI did not start !!!
-        }
-      }
-    }
-  }
-  
-  // Output system clock on MCO pin(PA8) for debugging purpose
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV8); // 48MHz/8=6MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  //Select HSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Select HSE oscillator as PLL source
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0) {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  } else {
-      RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
-  }
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-  
-  // Output HSE clock on MCO pin(PA8) for debugging purpose
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8MHz/2=4MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 8MHz/4=2MHz with ST-Link MCO
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
- 
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
-  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
-  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
-  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-      return 0; // FAIL
-  }
- 
-  // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-      return 0; // FAIL
-  }
-
-  // Output HSI clock on MCO1 pin(PA8) for debugging purpose
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV2); // 8MHz/2=4MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/system_stm32f0xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,324 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f0xx.c
+  * @author  MCD Application Team
+  * @version V2.3.1
+  * @date    04-November-2016
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+  *
+  * This file provides two functions and one global variable to be called from
+  *    user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx_system
+  * @{
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f0xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
+                                                 This value can be provided and adapted by the user application. */
+#endif /* HSI48_VALUE */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock there is no need to
+               call the 2 first functions listed above, since SystemCoreClock variable is 
+               updated automatically.
+  */
+uint32_t SystemCoreClock = 8000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+  RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+  /* Reset PREDIV[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+  /* Set default USB clock to PLLCLK, since there is no HSI48 */
+  RCC->CFGR3 |= (uint32_t)0x00000080U;  
+#else
+ #warning "No target selected"
+#endif
+
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000U;
+
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+      {
+        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+      }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+      {
+        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+      }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+      else
+      {
+#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
+        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
+          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+          STM32F091xC || STM32F098xx || STM32F030xC */
+      }
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -264,17 +264,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
                 irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
                 irq_handler(serial_irq_ids[id], RxIrq);
-                volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
-                UNUSED(tmpval);
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -419,7 +417,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
@@ -433,7 +431,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,232 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | NO                     | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  */
+
+#include "stm32f1xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+    RCC->CFGR &= 0xF8FF0000U;
+#else
+    RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+    /* Reset PLL2ON and PLL3ON bits */
+    RCC->CR &= 0xEBFFFFFFU;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x00FF0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#else
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+    /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+        /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0) {
+                while(1) {
+                    // [TODO] Put something here to tell the user that a problem occured...
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,596 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f1xx.c
-  * @author  MCD Application Team
-  * @version V4.2.0
-  * @date    31-March-2017
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f1xx_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
-  *    the product used), refer to "HSE_VALUE". 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f1xx.h"
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Defines
-  * @{
-  */
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM  */ 
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#if defined(STM32F100xB) ||defined(STM32F100xE)
-  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#if !defined(STM32F105xC) && !defined(STM32F107xC)
-  RCC->CFGR &= 0xF8FF0000U;
-#else
-  RCC->CFGR &= 0xF0FF0000U;
-#endif /* STM32F105xC */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= 0xEBFFFFFFU;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;
-#elif defined(STM32F100xB) || defined(STM32F100xE)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-#endif /* STM32F105xC */
-    
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
-#endif /* STM32F105xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-  uint32_t prediv1factor = 0U;
-#endif /* STM32F100xB or STM32F100xE */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08U:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#if !defined(STM32F105xC) && !defined(STM32F107xC)      
-      pllmull = ( pllmull >> 18U) + 2U;
-      
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {
- #if defined(STM32F100xB) || defined(STM32F100xE)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18U;
-      
-      if (pllmull != 0x0DU)
-      {
-         pllmull += 2U;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13U / 2U; 
-      }
-            
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-        
-        if (prediv1source == 0U)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F105xC */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
-  *         This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-  __IO uint32_t tmpreg;
-  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-    required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114U;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
-  RCC->APB2ENR = 0x000001E0U;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
-
-  (void)(tmpreg);
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BBU;  
-  GPIOD->CRH = 0xBBBBBBBBU;
-
-  GPIOE->CRL = 0xB44444BBU;  
-  GPIOE->CRH = 0xBBBBBBBBU;
-
-  GPIOF->CRL = 0x44BBBBBBU;  
-  GPIOF->CRH = 0xBBBB4444U;
-
-  GPIOG->CRL = 0x44BBBBBBU;  
-  GPIOG->CRH = 0x444B4B44U;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4U] = 0x00001091U;
-  FSMC_Bank1->BTCR[5U] = 0x00110212U;
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h	Thu Aug 03 13:13:39 2017 +0100
@@ -64,7 +64,10 @@
     PWM_1 = (int)TIM1_BASE,
     PWM_2 = (int)TIM2_BASE,
     PWM_3 = (int)TIM3_BASE,
-    PWM_4 = (int)TIM4_BASE
+    PWM_4 = (int)TIM4_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
 } PWMName;
 
 #ifdef __cplusplus

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,231 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 24                     | 24
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 24                     | 24
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 24                     | 24
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 24                     | 24
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  */
+
+#include "stm32f1xx.h"
+
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+    RCC->CFGR &= 0xF8FF0000U;
+#else
+    RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+    /* Reset PLL2ON and PLL3ON bits */
+    RCC->CR &= 0xEBFFFFFFU;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x00FF0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#else
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+    /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+        /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0) {
+                while(1) {
+                    // [TODO] Put something here to tell the user that a problem occured...
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV2;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,594 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f1xx.c
-  * @author  MCD Application Team
-  * @version V4.2.0
-  * @date    31-March-2017
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f1xx_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
-  *    the product used), refer to "HSE_VALUE". 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 24                     | 24
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 24                     | 24
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 24                     | 24
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 24                     | 24
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f1xx.h"
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Defines
-  * @{
-  */
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM  */ 
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#if defined(STM32F100xB) ||defined(STM32F100xE)
-  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#if !defined(STM32F105xC) && !defined(STM32F107xC)
-  RCC->CFGR &= 0xF8FF0000U;
-#else
-  RCC->CFGR &= 0xF0FF0000U;
-#endif /* STM32F105xC */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= 0xEBFFFFFFU;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;
-#elif defined(STM32F100xB) || defined(STM32F100xE)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-#endif /* STM32F105xC */
-    
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
-#endif /* STM32F105xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-  uint32_t prediv1factor = 0U;
-#endif /* STM32F100xB or STM32F100xE */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08U:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#if !defined(STM32F105xC) && !defined(STM32F107xC)      
-      pllmull = ( pllmull >> 18U) + 2U;
-      
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {
- #if defined(STM32F100xB) || defined(STM32F100xE)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18U;
-      
-      if (pllmull != 0x0DU)
-      {
-         pllmull += 2U;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13U / 2U; 
-      }
-            
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-        
-        if (prediv1source == 0U)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F105xC */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
-  *         This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-  __IO uint32_t tmpreg;
-  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-    required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114U;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
-  RCC->APB2ENR = 0x000001E0U;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
-
-  (void)(tmpreg);
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BBU;  
-  GPIOD->CRH = 0xBBBBBBBBU;
-
-  GPIOE->CRL = 0xB44444BBU;  
-  GPIOE->CRH = 0xBBBBBBBBU;
-
-  GPIOF->CRL = 0x44BBBBBBU;  
-  GPIOF->CRH = 0xBBBB4444U;
-
-  GPIOG->CRL = 0x44BBBBBBU;  
-  GPIOG->CRH = 0x444B4B44U;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4U] = 0x00001091U;
-  FSMC_Bank1->BTCR[5U] = 0x00110212U;
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz 
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,260 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-------------------------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC  / CLOCK_SOURCE_USB=1 | 3- PLL_HSI / CLOCK_SOURCE_USB=1
+  *                                    | (external 8 MHz clock)                | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL / CLOCK_SOURCE_USB=1  |
+  *                                    | (external 8 MHz xtal)                 |
+  *-------------------------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72 / 72                               | 64 / 48
+  *-------------------------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72 / 72                               | 64 / 48
+  *-------------------------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36 / 36                               | 32 / 24
+  *-------------------------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72 / 72                               | 64 / 48
+  *-------------------------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | NO / YES                              | NO / YES
+  *-------------------------------------------------------------------------------------------
+  */
+
+#include "stm32f1xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+    RCC->CFGR &= 0xF8FF0000U;
+#else
+    RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+    /* Reset PLL2ON and PLL3ON bits */
+    RCC->CR &= 0xEBFFFFFFU;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x00FF0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+
+    /* Reset CFGR2 register */
+    RCC->CFGR2 = 0x00000000U;
+#else
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+#endif
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+#if (CLOCK_SOURCE_USB)
+    RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;
+#endif /* CLOCK_SOURCE_USB */
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+#if (CLOCK_SOURCE_USB)
+    /* USB clock selection */
+    RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);
+#endif /* CLOCK_SOURCE_USB */
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+#if (CLOCK_SOURCE_USB)
+    RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;
+#endif /* CLOCK_SOURCE_USB */
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
+#if (CLOCK_SOURCE_USB)
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12; // 48 MHz (8 MHz/2 * 12)
+#else /* CLOCK_SOURCE_USB */
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+#endif /* CLOCK_SOURCE_USB */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+#if (CLOCK_SOURCE_USB)
+    /* USB clock selection */
+    RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);
+#endif /* CLOCK_SOURCE_USB */
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,596 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f1xx.c
-  * @author  MCD Application Team
-  * @version V4.2.0
-  * @date    31-March-2017
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f1xx_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
-  *    the product used), refer to "HSE_VALUE". 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f1xx.h"
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Defines
-  * @{
-  */
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM  */ 
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#if defined(STM32F100xB) ||defined(STM32F100xE)
-  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#if !defined(STM32F105xC) && !defined(STM32F107xC)
-  RCC->CFGR &= 0xF8FF0000U;
-#else
-  RCC->CFGR &= 0xF0FF0000U;
-#endif /* STM32F105xC */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= 0xEBFFFFFFU;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;
-#elif defined(STM32F100xB) || defined(STM32F100xE)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-#endif /* STM32F105xC */
-    
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
-#endif /* STM32F105xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-  uint32_t prediv1factor = 0U;
-#endif /* STM32F100xB or STM32F100xE */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08U:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#if !defined(STM32F105xC) && !defined(STM32F107xC)      
-      pllmull = ( pllmull >> 18U) + 2U;
-      
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {
- #if defined(STM32F100xB) || defined(STM32F100xE)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18U;
-      
-      if (pllmull != 0x0DU)
-      {
-         pllmull += 2U;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13U / 2U; 
-      }
-            
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-        
-        if (prediv1source == 0U)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F105xC */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
-  *         This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-  __IO uint32_t tmpreg;
-  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-    required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114U;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
-  RCC->APB2ENR = 0x000001E0U;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
-
-  (void)(tmpreg);
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BBU;  
-  GPIOD->CRH = 0xBBBBBBBBU;
-
-  GPIOE->CRL = 0xB44444BBU;  
-  GPIOE->CRH = 0xBBBBBBBBU;
-
-  GPIOF->CRL = 0x44BBBBBBU;  
-  GPIOF->CRH = 0xBBBB4444U;
-
-  GPIOG->CRL = 0x44BBBBBBU;  
-  GPIOG->CRH = 0x444B4B44U;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4U] = 0x00001091U;
-  FSMC_Bank1->BTCR[5U] = 0x00110212U;
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c	Thu Aug 03 13:13:39 2017 +0100
@@ -1462,7 +1462,7 @@
         /* Generate Start */
         hi2c->Instance->CR1 |= I2C_CR1_START;
       }
-      else
+      else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED
       {
         /* Generate ReStart */
         hi2c->Instance->CR1 |= I2C_CR1_START;
@@ -1564,7 +1564,7 @@
         /* Generate Start */
         hi2c->Instance->CR1 |= I2C_CR1_START;
       }
-      else
+      else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) // MBED
       {
         /* Enable Acknowledge */
         hi2c->Instance->CR1 |= I2C_CR1_ACK;
@@ -4008,7 +4008,7 @@
 
       /* Enable Pos */
       hi2c->Instance->CR1 |= I2C_CR1_POS;
-      
+
       /* Disable BUF interrupt */
       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
     }
@@ -4078,6 +4078,12 @@
     {
       /* Disable Acknowledge */
       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
     else
     {

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/system_stm32f1xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,458 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f1xx.c
+  * @author  MCD Application Team
+  * @version V4.2.0
+  * @date    31-March-2017
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f1xx_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+  *    the product used), refer to "HSE_VALUE". 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f1xx.h"
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM  */ 
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#if defined(STM32F100xB) ||defined(STM32F100xE)
+  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+  RCC->CFGR &= 0xF8FF0000U;
+#else
+  RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEBFFFFFFU;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+    
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+  uint32_t prediv1factor = 0U;
+#endif /* STM32F100xB or STM32F100xE */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00U:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08U:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#if !defined(STM32F105xC) && !defined(STM32F107xC)      
+      pllmull = ( pllmull >> 18U) + 2U;
+      
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18U;
+      
+      if (pllmull != 0x0DU)
+      {
+         pllmull += 2U;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13U / 2U; 
+      }
+            
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+        
+        if (prediv1source == 0U)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F105xC */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
+  *         This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+  __IO uint32_t tmpreg;
+  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+    required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114U;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+  RCC->APB2ENR = 0x000001E0U;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+  (void)(tmpreg);
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BBU;  
+  GPIOD->CRH = 0xBBBBBBBBU;
+
+  GPIOE->CRL = 0xB44444BBU;  
+  GPIOE->CRH = 0xBBBBBBBBU;
+
+  GPIOF->CRL = 0x44BBBBBBU;  
+  GPIOF->CRH = 0xBBBB4444U;
+
+  GPIOG->CRL = 0x44BBBBBBU;  
+  GPIOG->CRH = 0x444B4B44U;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4U] = 0x00001091U;
+  FSMC_Bank1->BTCR[5U] = 0x00110212U;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -159,16 +159,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
                 irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
                 irq_handler(serial_irq_ids[id], RxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -228,7 +227,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
@@ -242,7 +241,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,222 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 120
+  * AHBCLK (MHz)        | 120
+  * APB1CLK (MHz)       |  30
+  * APB2CLK (MHz)       |  60
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f2xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+#if 0 // SYSCLK can be map to PC_9
+    HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_2);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+    }
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLM            = 8;
+    RCC_OscInitStruct.PLL.PLLN            = 240;
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2;
+    RCC_OscInitStruct.PLL.PLLQ            = 5;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM = 16;
+    RCC_OscInitStruct.PLL.PLLN = 240;
+    RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+    RCC_OscInitStruct.PLL.PLLQ = 5;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                  | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_stm32f2xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,504 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f2xx.c
-  * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    17-March-2017
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f2xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
-  *                           | (external 25MHz xtal) | (internal 16MHz clock)
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)               | 120                   | 96
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)              | 120                   | 96
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)             |  30                   |  12
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)             | 60                   | 24
-  *-----------------------------------------------------------------------------
-  * USB capable               | YES                   |  NO
-  * with 48 MHz precise clock |                       |
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f2xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F2xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f2xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F2xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM322xG_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F2xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F2xx_System_Private_Variables
-  * @{
-  */
-  
-  /* This variable can be updated in Three ways :
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 16000000;
-  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F2xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemFrequency variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
-  *              depends on the application requirements), user has to ensure that HSE_VALUE
-  *              is same as the real frequency of the crystal used. Otherwise, this function
-  *              may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *     
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f2xx.s before jump to main.
-  *         This function configures the external SRAM mounted on STM322xG_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0x00;
-
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
-  (void)(tmp);
-
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00085AAA;
-  /* Configure PGx pins speed to 100 MHz */ 
-  GPIOG->OSPEEDR = 0x000CAFFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*--FSMC Configuration -------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-
-  /* Configure and enable Bank1_SRAM2 */
-  FSMC_Bank1->BTCR[2]  = 0x00001011;
-  FSMC_Bank1->BTCR[3]  = 0x00000201;
-  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-    /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-    if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-    {
-        /* 2- If fail try to start with HSE and external xtal */
-#if USE_PLL_HSE_XTAL != 0
-        if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-        {
-            /* 3- If fail start with HSI clock */
-            if (SetSysClock_PLL_HSI() == 0) {
-                while (1) {
-                    // [TODO] Put something here to tell the user that a problem occured...
-                }
-            }
-        }
-    }
-
-#if 0 // SYSCLK can be map to PC_9
-    HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_2);
-#endif
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-
-    /* The voltage scaling allows optimizing the power consumption when the device is
-       clocked below the maximum system frequency, to update the voltage scaling value
-       regarding system frequency refer to product datasheet. */
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    // Enable HSE oscillator and activate PLL with HSE as source
-    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-    if (bypass == 0) {
-        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
-    } else {
-        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
-    }
-    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-    RCC_OscInitStruct.PLL.PLLM            = 8;
-    RCC_OscInitStruct.PLL.PLLN            = 240;
-    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2;
-    RCC_OscInitStruct.PLL.PLLQ            = 5;
-
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-
-    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
-    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-
-    /* The voltage scaling allows optimizing the power consumption when the device is
-       clocked below the maximum system frequency, to update the voltage scaling value
-       regarding system frequency refer to product datasheet. */
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-    RCC_OscInitStruct.HSICalibrationValue = 16;
-    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
-    RCC_OscInitStruct.PLL.PLLM = 8;
-    RCC_OscInitStruct.PLL.PLLN = 192;
-    RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
-    RCC_OscInitStruct.PLL.PLLQ = 8;
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
-                                  | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
-        return 0; // FAIL
-    }
-
-
-    return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_i2c.c	Thu Aug 03 13:13:39 2017 +0100
@@ -1414,8 +1414,17 @@
     /* Generate Start */    
     if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
     {
-       /* Generate Start or ReStart */
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate Start */
         hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
+      else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED
+      {
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
 
     /* Process Unlocked */
@@ -1504,11 +1513,23 @@
     
     if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
     {
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)  || (XferOptions == I2C_NO_OPTION_FRAME))
+      {
         /* Enable Acknowledge */
         hi2c->Instance->CR1 |= I2C_CR1_ACK;
-        
-        /* Generate Start or ReStart */
+
+        /* Generate Start */
         hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
+      else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+      {
+        /* Enable Acknowledge */
+        hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
 
     /* Process Unlocked */
@@ -3996,6 +4017,12 @@
     {
       /* Disable Acknowledge */
       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
     else
     {

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/device/system_stm32f2xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,372 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V2.2.0
+  * @date    17-March-2017
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *             
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+  
+  /* This variable can be updated in Three ways :
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 16000000;
+  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+  (void)(tmp);
+
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*--FSMC Configuration -------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -246,16 +246,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
                 irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
                 irq_handler(serial_irq_ids[id], RxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -385,7 +384,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
             NVIC_SetVector(irq_n, vector);
             NVIC_EnableIRQ(irq_n);
@@ -399,7 +398,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,231 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- USE_PLL_HSE_EXTC    | 3- USE_PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- USE_PLL_HSE_XTAL    |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable                        | YES                    | NO
+  *-----------------------------------------------------------------------------
+  */
+
+
+#include "stm32f3xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset CFGR register */
+    RCC->CFGR &= 0xF87FC00CU;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+    /* Reset PREDIV1[3:0] bits */
+    RCC->CFGR2 &= 0xFFFFFFF0U;
+
+    /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+    RCC->CFGR3 &= 0xFF00FCCCU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_stm32f3xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,447 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f3xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f3xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f3xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f3xx.h"
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 72000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset CFGR register */
-  RCC->CFGR &= 0xF87FC00CU;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= 0xFFFFFFF0U;
-
-  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
-  RCC->CFGR3 &= 0xFF00FCCCU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-      else
-      {
-        /* HSI oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
-      }
-#else      
-      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- USE_PLL_HSE_EXTC    | 3- USE_PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- USE_PLL_HSE_XTAL    |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable                        | NO                     | NO
+  *-----------------------------------------------------------------------------
+  */
+
+
+#include "stm32f3xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset CFGR register */
+    RCC->CFGR &= 0xF87FC00CU;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+    /* Reset PREDIV1[3:0] bits */
+    RCC->CFGR2 &= 0xFFFFFFF0U;
+
+    /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+    RCC->CFGR3 &= 0xFF00FCCCU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/system_stm32f3xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,446 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f3xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f3xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f3xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f3xx.h"
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 72000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset CFGR register */
-  RCC->CFGR &= 0xF87FC00CU;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= 0xFFFFFFF0U;
-
-  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
-  RCC->CFGR3 &= 0xFF00FCCCU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-      else
-      {
-        /* HSI oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
-      }
-#else      
-      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,215 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | NO                     | NO
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f3xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset CFGR register */
+    RCC->CFGR &= 0xF87FC00CU;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+    /* Reset PREDIV1[3:0] bits */
+    RCC->CFGR2 &= 0xFFFFFFF0U;
+
+    /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+    RCC->CFGR3 &= 0xFF00FCCCU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+    /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+        /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0) {
+                while(1) {
+                    // [TODO] Put something here to tell the user that a problem occured...
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+    return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+    return 1; // OK
+}
+

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_stm32f3xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,446 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f3xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f3xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f3xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f3xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 72000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset CFGR register */
-  RCC->CFGR &= 0xF87FC00CU;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= 0xFFFFFFF0U;
-
-  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
-  RCC->CFGR3 &= 0xFF00FCCCU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-      else
-      {
-        /* HSI oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
-      }
-#else      
-      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,234 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 72
+  * AHBCLK (MHz)        | 72
+  * APB1CLK (MHz)       | 36
+  * APB2CLK (MHz)       | 72
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+  */
+
+
+#include "stm32f3xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset CFGR register */
+    RCC->CFGR &= 0xF87FC00CU;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+    /* Reset PREDIV1[3:0] bits */
+    RCC->CFGR2 &= 0xFFFFFFF0U;
+
+    /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+    RCC->CFGR3 &= 0xFF00FCCCU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO2 pin(PC9) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,234 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 8 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 72
+  * AHBCLK (MHz)        | 72
+  * APB1CLK (MHz)       | 36
+  * APB2CLK (MHz)       | 72
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+  */
+
+
+#include "stm32f3xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset CFGR register */
+    RCC->CFGR &= 0xF87FC00CU;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+    /* Reset PREDIV1[3:0] bits */
+    RCC->CFGR2 &= 0xFFFFFFF0U;
+
+    /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+    RCC->CFGR3 &= 0xFF00FCCCU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO2 pin(PC9) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/system_stm32f3xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,447 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f3xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f3xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f3xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f3xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 72000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset CFGR register */
-  RCC->CFGR &= 0xF87FC00CU;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= 0xFFFFFFF0U;
-
-  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
-  RCC->CFGR3 &= 0xFF00FCCCU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-      else
-      {
-        /* HSI oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
-      }
-#else      
-      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PREDIV          = RCC_PREDIV_DIV2;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- USE_PLL_HSE_EXTC    | 3- USE_PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- USE_PLL_HSE_XTAL    |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable                        | NO                     | NO
+  *-----------------------------------------------------------------------------
+  */
+
+
+#include "stm32f3xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset CFGR register */
+    RCC->CFGR &= 0xF87FC00CU;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+    /* Reset PREDIV1[3:0] bits */
+    RCC->CFGR2 &= 0xFFFFFFF0U;
+
+    /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+    RCC->CFGR3 &= 0xFF00FCCCU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_stm32f3xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,446 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f3xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f3xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f3xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f3xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 72000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset CFGR register */
-  RCC->CFGR &= 0xF87FC00CU;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= 0xFFFFFFF0U;
-
-  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
-  RCC->CFGR3 &= 0xFF00FCCCU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-      else
-      {
-        /* HSI oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
-      }
-#else      
-      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- USE_PLL_HSE_EXTC    | 3- USE_PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 8 MHz)
+  *                                    | 2- USE_PLL_HSE_XTAL    |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72                     | 64
+  *-----------------------------------------------------------------------------
+  * USB capable                        | NO                     | NO
+  *-----------------------------------------------------------------------------
+  */
+
+
+#include "stm32f3xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= 0x00000001U;
+
+    /* Reset CFGR register */
+    RCC->CFGR &= 0xF87FC00CU;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= 0xFEF6FFFFU;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= 0xFFFBFFFFU;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+    RCC->CFGR &= 0xFF80FFFFU;
+
+    /* Reset PREDIV1[3:0] bits */
+    RCC->CFGR2 &= 0xFFFFFFF0U;
+
+    /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+    RCC->CFGR3 &= 0xFF00FCCCU;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_stm32f3xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,446 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f3xx.c
-  * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
-  *
-  * 1. This file provides two functions and one global variable to be called from
-  *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f3xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f3xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f3xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
-               updated automatically.
-  */
-uint32_t SystemCoreClock = 72000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset CFGR register */
-  RCC->CFGR &= 0xF87FC00CU;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= 0xFFFFFFF0U;
-
-  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
-  RCC->CFGR3 &= 0xFF00FCCCU;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
-      {
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-      else
-      {
-        /* HSI oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
-      }
-#else      
-      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
-      }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/system_stm32f3xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,324 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f3xx.c
+  * @author  MCD Application Team
+  * @version V2.3.1
+  * @date    16-December-2016
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  * 1. This file provides two functions and one global variable to be called from
+  *    user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f3xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. This file configures the system clock as follows:
+  *=============================================================================
+  *                         Supported STM32F3xx device
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | HSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 8000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 8000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | DISABLE
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f3xx_system
+  * @{
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f3xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock there is no need to
+               call the 2 first functions listed above, since SystemCoreClock variable is 
+               updated automatically.
+  */
+uint32_t SystemCoreClock = 8000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F3xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset CFGR register */
+  RCC->CFGR &= 0xF87FC00CU;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= 0xFF80FFFFU;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= 0xFFFFFFF0U;
+
+  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+  RCC->CFGR3 &= 0xFF00FCCCU;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000U;
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
+        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+      {
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+      }
+      else
+      {
+        /* HSI oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
+      }
+#else      
+      if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+      }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -210,17 +210,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
             irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
         }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
-            irq_handler(serial_irq_ids[id], RxIrq);
-                volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
-                UNUSED(tmpval);
+                irq_handler(serial_irq_ids[id], RxIrq);
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -312,7 +310,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
@@ -326,7 +324,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -88,7 +88,7 @@
 const PinMap PinMap_UART_TX[] = {
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PD_5,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PD_9,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_8,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {NC,    NC,     0}
 };
@@ -96,7 +96,7 @@
 const PinMap PinMap_UART_RX[] = {
     {PA_10,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PD_8,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_9,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
     {NC,    NC,     0}
 };
@@ -104,12 +104,14 @@
 const PinMap PinMap_UART_RTS[] = {
     {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {NC,    NC,     0}
 };
 
 const PinMap PinMap_UART_CTS[] = {
     {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {NC,    NC,     0}
 };
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/device/flash_data.h	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_FLASH_DATA_H
-#define MBED_FLASH_DATA_H
-
-#include "device.h"
-#include <stdint.h>
-
-#if DEVICE_FLASH
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Base address of the Flash sectors Bank 1 */
-#define ADDR_FLASH_SECTOR_0     ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_1     ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_2     ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_3     ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_4     ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
-#define ADDR_FLASH_SECTOR_5     ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_6     ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_7     ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_8     ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_9     ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_10    ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_11    ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
-
-/* Base address of the Flash sectors Bank 2 */
-#define ADDR_FLASH_SECTOR_12     ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_13     ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_14     ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_15     ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */
-#define ADDR_FLASH_SECTOR_16     ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */
-#define ADDR_FLASH_SECTOR_17     ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_18     ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_19     ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_20     ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes  */
-#define ADDR_FLASH_SECTOR_21     ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes  */
-#define ADDR_FLASH_SECTOR_22     ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_23     ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */
-      
-
-#endif
-#endif

--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c	Thu Aug 03 13:13:39 2017 +0100
@@ -1413,8 +1413,17 @@
     /* Generate Start */    
     if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
     {
-        /* Generate Start or ReStart */
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate Start */
         hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
+      else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED
+      {
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
 
     /* Process Unlocked */
@@ -1503,10 +1512,23 @@
     
     if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
     {
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)  || (XferOptions == I2C_NO_OPTION_FRAME))
+      {
         /* Enable Acknowledge */
         hi2c->Instance->CR1 |= I2C_CR1_ACK;
-        /* Generate Start or ReStart */
+
+        /* Generate Start */
         hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
+      else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+      {
+        /* Enable Acknowledge */
+        hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
 
     /* Process Unlocked */
@@ -3993,6 +4015,12 @@
     {
       /* Disable Acknowledge */
       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
     else
     {

--- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -273,16 +273,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
                 irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
                 irq_handler(serial_irq_ids[id], RxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -438,7 +437,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
             NVIC_SetVector(irq_n, vector);
             NVIC_EnableIRQ(irq_n);
@@ -452,7 +451,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,250 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *--------------------------------------------------------------------
+  * System clock source   | 1- USE_PLL_HSE_EXTC (external 25 MHz clock)
+  *                       | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal)
+  *                       | 3- USE_PLL_HSI (internal 16 MHz clock)
+  *--------------------------------------------------------------------
+  * SYSCLK(MHz)           |            216
+  * AHBCLK (MHz)          |            216
+  * APB1CLK (MHz)         |             54
+  * APB2CLK (MHz)         |            108
+  * USB capable (48 MHz)  |            YES
+  *--------------------------------------------------------------------
+**/
+
+#include "stm32f7xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO2 pin(PC9) for debugging purpose
+    // Can be visualized on uSD card CN3 connector pin 8
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+    }
+    // Warning: this configuration is for a 25 MHz xtal clock only
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLM            = 25;            // VCO input clock = 1 MHz (25 MHz / 25)
+    RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM            = 8;            // VCO input clock = 2 MHz (16 MHz / 8)
+    RCC_OscInitStruct.PLL.PLLN            = 216;           // VCO output clock = 432 MHz (2 MHz * 216)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_stm32f7xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,834 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f7xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
-  *                           | (external 25MHz xtal) | (internal 16MHz clock)
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)               | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)              | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)             |  54                   |  54
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)             | 108                   | 108
-  *-----------------------------------------------------------------------------
-  * USB capable               | YES                   |  NO
-  * with 48 MHz precise clock |                       |
-  *-----------------------------------------------------------------------------  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F7xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f7xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
-     on STMicroelectronics EVAL/Discovery boards as data memory  */
-/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
-     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
-     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
-/* #define DATA_IN_ExtSRAM */ 
-/* #define DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */ 
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Variables
-  * @{
-  */
-
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = HSI_VALUE;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
-  * @{
-  */
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemFrequency variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *     
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f7xx.s before jump to main.
-  *         This function configures the external memories (SRAM/SDRAM)
-  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0;
-#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;  
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;  
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xFF800FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC00000CC;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80220AAA;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80320FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40110555;
-
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;   
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
-  
-#elif defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */  
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x50150005;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554005;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC000000C;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80020A0A;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80020A0A;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40010505;
-  
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-  
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-  
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;      
-  
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-  
-#elif defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  
-    /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55000555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 100 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00100555;
-  
-/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
-
-#endif /* DATA_IN_ExtSRAM */
-
-  (void)(tmp);
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO2 pin(PC9) for debugging purpose
-  // Can be visualized on uSD card CN3 connector pin 8
-  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
-  
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
-  }
-  // Warning: this configuration is for a 25 MHz xtal clock only
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM            = 25;            // VCO input clock = 1 MHz (25 MHz / 25)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-  
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable CPU L1-Cache
-  SCB_EnableICache();
-  SCB_EnableDCache();
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
- 
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
-  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,250 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *--------------------------------------------------------------------
+  * System clock source   | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                       | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                       | 3- USE_PLL_HSI (internal 16 MHz clock)
+  *--------------------------------------------------------------------
+  * SYSCLK(MHz)           |            216
+  * AHBCLK (MHz)          |            216
+  * APB1CLK (MHz)         |             54
+  * APB2CLK (MHz)         |            108
+  * USB capable (48 MHz)  |            YES
+  *--------------------------------------------------------------------
+**/
+
+#include "stm32f7xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO2 pin(PC9) for debugging purpose
+    // Can be visualized on CN8 connector pin 4
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+    }
+    // Warning: this configuration is for a 8 MHz xtal clock only
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLM            = 4;             // VCO input clock = 2 MHz (8 MHz / 4)
+    RCC_OscInitStruct.PLL.PLLN            = 216;           // VCO output clock = 432 MHz (2 MHz * 216)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM            = 8;            // VCO input clock = 2 MHz (16 MHz / 8)
+    RCC_OscInitStruct.PLL.PLLN            = 216;           // VCO output clock = 432 MHz (2 MHz * 216)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,834 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f7xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
-  *                           | (external 25MHz xtal) | (internal 16MHz clock)
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)               | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)              | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)             |  54                   |  54
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)             | 108                   | 108
-  *-----------------------------------------------------------------------------
-  * USB capable               | YES                   |  NO
-  * with 48 MHz precise clock |                       |
-  *-----------------------------------------------------------------------------  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F7xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f7xx.h"
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
-     on STMicroelectronics EVAL/Discovery boards as data memory  */
-/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
-     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
-     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
-/* #define DATA_IN_ExtSRAM */ 
-/* #define DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */ 
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Variables
-  * @{
-  */
-
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = HSI_VALUE;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
-  * @{
-  */
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemFrequency variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *     
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f7xx.s before jump to main.
-  *         This function configures the external memories (SRAM/SDRAM)
-  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0;
-#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;  
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;  
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xFF800FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC00000CC;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80220AAA;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80320FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40110555;
-
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;   
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
-  
-#elif defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */  
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x50150005;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554005;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC000000C;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80020A0A;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80020A0A;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40010505;
-  
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-  
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-  
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;      
-  
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-  
-#elif defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  
-    /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55000555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 100 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00100555;
-  
-/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
-
-#endif /* DATA_IN_ExtSRAM */
-
-  (void)(tmp);
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO2 pin(PC9) for debugging purpose
-  // Can be visualized on CN8 connector pin 4
-  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
-  
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
-  }
-  // Warning: this configuration is for a 8 MHz xtal clock only
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-  
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable CPU L1-Cache
-  SCB_EnableICache();
-  SCB_EnableDCache();
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
- 
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
-  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,250 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *--------------------------------------------------------------------
+  * System clock source   | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                       | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                       | 3- USE_PLL_HSI (internal 16 MHz clock)
+  *--------------------------------------------------------------------
+  * SYSCLK(MHz)           |            216
+  * AHBCLK (MHz)          |            216
+  * APB1CLK (MHz)         |             54
+  * APB2CLK (MHz)         |            108
+  * USB capable (48 MHz)  |            YES
+  *--------------------------------------------------------------------
+**/
+
+#include "stm32f7xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO2 pin(PC9) for debugging purpose
+    // Can be visualized on CN8 connector pin 4
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+    }
+    // Warning: this configuration is for a 8 MHz xtal clock only
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLM            = 4;             // VCO input clock = 2 MHz (8 MHz / 4)
+    RCC_OscInitStruct.PLL.PLLN            = 216;           // VCO output clock = 432 MHz (2 MHz * 216)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM            = 8;            // VCO input clock = 1 MHz (16 MHz / 16)
+    RCC_OscInitStruct.PLL.PLLN            = 216;           // VCO output clock = 432 MHz (1 MHz * 432)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_stm32f7xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,834 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f7xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
-  *                           | (external 25MHz xtal) | (internal 16MHz clock)
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)               | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)              | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)             |  54                   |  54
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)             | 108                   | 108
-  *-----------------------------------------------------------------------------
-  * USB capable               | YES                   |  NO
-  * with 48 MHz precise clock |                       |
-  *-----------------------------------------------------------------------------  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F7xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f7xx.h"
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
-     on STMicroelectronics EVAL/Discovery boards as data memory  */
-/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
-     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
-     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
-/* #define DATA_IN_ExtSRAM */ 
-/* #define DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */ 
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Variables
-  * @{
-  */
-
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = HSI_VALUE;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
-  * @{
-  */
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemFrequency variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *     
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f7xx.s before jump to main.
-  *         This function configures the external memories (SRAM/SDRAM)
-  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0;
-#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;  
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;  
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xFF800FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC00000CC;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80220AAA;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80320FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40110555;
-
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;   
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
-  
-#elif defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */  
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x50150005;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554005;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC000000C;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80020A0A;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80020A0A;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40010505;
-  
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-  
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-  
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;      
-  
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-  
-#elif defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  
-    /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55000555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 100 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00100555;
-  
-/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
-
-#endif /* DATA_IN_ExtSRAM */
-
-  (void)(tmp);
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO2 pin(PC9) for debugging purpose
-  // Can be visualized on CN8 connector pin 4
-  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
-  
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
-  }
-  // Warning: this configuration is for a 8 MHz xtal clock only
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-  
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable CPU L1-Cache
-  SCB_EnableICache();
-  SCB_EnableDCache();
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
- 
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
-  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,252 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *--------------------------------------------------------------------
+  * System clock source   | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                       | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                       | 3- USE_PLL_HSI (internal 16 MHz clock)
+  *--------------------------------------------------------------------
+  * SYSCLK(MHz)           |            216
+  * AHBCLK (MHz)          |            216
+  * APB1CLK (MHz)         |             54
+  * APB2CLK (MHz)         |            108
+  * USB capable (48 MHz)  |            YES
+  *--------------------------------------------------------------------
+**/
+
+#include "stm32f7xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO2 pin(PC9) for debugging purpose
+    // Can be visualized on CN8 connector pin 4
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+    }
+    // Warning: this configuration is for a 8 MHz xtal clock only
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLM            = 4;             // VCO input clock = 2 MHz (8 MHz / 4)
+    RCC_OscInitStruct.PLL.PLLN            = 216;           // VCO output clock = 432 MHz (2 MHz * 216)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+    RCC_OscInitStruct.PLL.PLLR            = 2;             // I2S clock
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM            = 8;            // VCO input clock = 2 MHz (16 MHz / 8)
+    RCC_OscInitStruct.PLL.PLLN            = 216;           // VCO output clock = 432 MHz (2 MHz * 216)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;
+    RCC_OscInitStruct.PLL.PLLR            = 2;             // I2S clock
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_stm32f7xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,836 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f7xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
-  *                           | (external 25MHz xtal) | (internal 16MHz clock)
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)               | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)              | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)             |  54                   |  54
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)             | 108                   | 108
-  *-----------------------------------------------------------------------------
-  * USB capable               | YES                   |  NO
-  * with 48 MHz precise clock |                       |
-  *-----------------------------------------------------------------------------  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F7xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f7xx.h"
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
-     on STMicroelectronics EVAL/Discovery boards as data memory  */
-/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
-     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
-     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
-/* #define DATA_IN_ExtSRAM */ 
-/* #define DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */ 
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Variables
-  * @{
-  */
-
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = HSI_VALUE;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
-  * @{
-  */
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemFrequency variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *     
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f7xx.s before jump to main.
-  *         This function configures the external memories (SRAM/SDRAM)
-  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0;
-#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;  
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;  
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xFF800FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC00000CC;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80220AAA;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80320FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40110555;
-
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;   
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
-  
-#elif defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */  
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x50150005;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554005;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC000000C;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80020A0A;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80020A0A;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40010505;
-  
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-  
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-  
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;      
-  
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-  
-#elif defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  
-    /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55000555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 100 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00100555;
-  
-/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
-
-#endif /* DATA_IN_ExtSRAM */
-
-  (void)(tmp);
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO2 pin(PC9) for debugging purpose
-  // Can be visualized on CN8 connector pin 4
-  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
-  
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
-  }
-  // Warning: this configuration is for a 8 MHz xtal clock only
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM            = 8;             // VCO input clock = 1 MHz (8 MHz / 8)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR            = 2;             // I2S clock
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-  
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable CPU L1-Cache
-  SCB_EnableICache();
-  SCB_EnableDCache();
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
- 
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
-  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR            = 2;             // I2S clock
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f767xx.S	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f767xx.S	Thu Aug 03 13:13:39 2017 +0100
@@ -58,10 +58,6 @@
 .word  _sdata
 /* end address for the .data section. defined in linker script */
 .word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
 
 /**
@@ -95,24 +91,18 @@
   adds  r2, r0, r1
   cmp  r2, r3
   bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-    
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
 
 /* Call the clock system initialization function.*/
   bl  SystemInit   
 /* Call static constructors */
-    bl __libc_init_array
+  //bl __libc_init_array
 /* Call the application's entry point.*/
-  bl  main
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before
+  // starting main(). software_init_hook() is available and has to be called due
+  // to initializsation when using rtos.
+  bl _start
   bx  lr    
 .size  Reset_Handler, .-Reset_Handler
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,250 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *--------------------------------------------------------------------
+  * System clock source   | 1- USE_PLL_HSE_EXTC (external 25 MHz clock)
+  *                       | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal)
+  *                       | 3- USE_PLL_HSI (internal 16 MHz clock)
+  *--------------------------------------------------------------------
+  * SYSCLK(MHz)           |            216
+  * AHBCLK (MHz)          |            216
+  * APB1CLK (MHz)         |             54
+  * APB2CLK (MHz)         |            108
+  * USB capable (48 MHz)  |            YES
+  *--------------------------------------------------------------------
+**/
+
+#include "stm32f7xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x24003010;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO2 pin(PC9) for debugging purpose
+    // Can be visualized on CN8 connector pin 4
+    //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
+    }
+    // Warning: this configuration is for a 25 MHz xtal clock only
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLM            = 25;            // VCO input clock = 1 MHz (25 MHz / 25)
+    RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+    RCC_OscInitStruct.PLL.PLLR            = 2;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLLSAI output as USB clock source */
+    RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+    RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
+    RCC_PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
+    RCC_PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7;
+    RCC_PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+    if(HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct)  != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    // Enable power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
+    RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
+    RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+    RCC_OscInitStruct.PLL.PLLR            = 2;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Activate the OverDrive to reach the 216 MHz Frequency
+    if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    return 1; // OK
+
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_stm32f7xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,848 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f7xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    30-December-2016
-  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f7xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source       | [1] PLL_HSE_XTAL      | [2] PLL_HSI if [1] fails
-  *                           | (external 25MHz xtal) | (internal 16MHz clock)
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)               | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)              | 216                   | 216
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)             |  54                   |  54
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)             | 108                   | 108
-  *-----------------------------------------------------------------------------
-  * USB capable               | YES                   |  NO
-  * with 48 MHz precise clock |                       |
-  *-----------------------------------------------------------------------------  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f7xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F7xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f7xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
-     on STMicroelectronics EVAL/Discovery boards as data memory  */
-/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
-     need to be added  in the project preprocessor to avoid SDRAM multiple configuration
-     (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
-/* #define DATA_IN_ExtSRAM */ 
-/* #define DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */ 
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Variables
-  * @{
-  */
-
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = HSI_VALUE;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
-  * @{
-  */
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F7xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemFrequency variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *     
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f7xx.s before jump to main.
-  *         This function configures the external memories (SRAM/SDRAM)
-  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0;
-#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;  
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;  
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xFF800FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC00000CC;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80220AAA;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80320FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40110555;
-
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;   
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);  
-  
-#elif defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-  /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */  
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x50150005;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */ 
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554005;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCC000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */ 
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55400555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CC00CC;
-  GPIOG->AFR[1]  = 0xC000000C;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x80020A0A;
-  /* Configure PGx pins speed to 50 MHz */ 
-  GPIOG->OSPEEDR = 0x80020A0A;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x40010505;
-  
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */ 
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */ 
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */  
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */ 
-  GPIOH->PUPDR   = 0x55550450;
-  
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */ 
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */ 
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */  
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */ 
-  GPIOI->PUPDR   = 0x00145555;
-  
-/*-- FMC Configuration ------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-  FMC_Bank5_6->SDCR[0] = 0x000019E5;
-  FMC_Bank5_6->SDTR[0] = 0x01116361;      
-  
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-  
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  /* Auto refresh command */
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  /* MRD register program */
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
-  
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-  
-#elif defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  
-    /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
-  
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x55550545;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x55554145;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x55000555;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 100 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00100555;
-  
-/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[4]  = 0x00001091;
-  FMC_Bank1->BTCR[5]  = 0x00110212;
-  FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;  
-
-#endif /* DATA_IN_ExtSRAM */
-
-  (void)(tmp);
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO2 pin(PC9) for debugging purpose
-  // Can be visualized on CN8 connector pin 4
-  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
-  
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External clock on OSC_IN */
-  }
-  // Warning: this configuration is for a 25 MHz xtal clock only
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM            = 25;            // VCO input clock = 1 MHz (25 MHz / 25)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR            = 2;
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLLSAI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
-  PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
-  PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
-  PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7;
-  PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
-  if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct)  != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-  
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  // Enable CPU L1-Cache
-  SCB_EnableICache();
-  SCB_EnableDCache();
-
-  // Enable power clock  
-  __PWR_CLK_ENABLE();
- 
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSICalibrationValue = 16;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;   
-  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
-  RCC_OscInitStruct.PLL.PLLN            = 432;           // VCO output clock = 432 MHz (1 MHz * 432)
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLQ            = 9;             // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR            = 2;
-
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  // Activate the OverDrive to reach the 216 MHz Frequency
-  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 216 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;           //  54 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           // 108 MHz
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h	Thu Aug 03 13:13:39 2017 +0100
@@ -105,11 +105,13 @@
   *        This value is used by the RCC HAL module to compute the system frequency
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
+#if !defined  (HSE_VALUE)
 #if defined(TARGET_DISCO_F746NG) || defined(TARGET_DISCO_F769NI)
   #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
 #else
   #define HSE_VALUE    8000000U /*!< Default value of the External oscillator in Hz */
 #endif
+#endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT    200U   /*!< Time out for HSE start up, in ms */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/system_stm32f7xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,288 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.c
+  * @author  MCD Application Team
+  * @version V1.2.0
+  * @date    30-December-2016
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f7xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Variables
+  * @{
+  */
+
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 16000000;
+  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -238,16 +238,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
                 irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_IT(huart, UART_CLEAR_TCF);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
                 irq_handler(serial_irq_ids[id], RxIrq);
-                volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -373,7 +372,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
@@ -387,7 +386,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -62,7 +62,7 @@
 //*** DAC ***
 
 const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // DAC_OUT
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT
     {NC,   NC,    0}
 };
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select HSI48 as USB clock source */
+    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,468 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x100. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100U;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000U;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *             value as defined by the MSI range.
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00U:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-    case 0x04U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0CU:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18U)];
-      plldiv = (plldiv >> 22U) + 1U;
-
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select HSI48 as USB clock source */
-  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,260 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+    RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __HAL_RCC_PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+    __HAL_RCC_PWR_CLK_DISABLE();
+
+    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    // PLLCLK = (16 MHz * 6)/3 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_6;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_3;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select HSI48 as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Configure the clock recovery system (CRS) ********************************/
+    /* Enable CRS Clock */
+    __HAL_RCC_CRS_CLK_ENABLE();
+    /* Default Synchro Signal division factor (not divided) */
+    RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+    /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+    RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+    /* HSI48 is synchronized with USB SOF at 1KHz rate */
+    RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+    RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+    /* Set the TRIM[5:0] to the default value */
+    RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
+    /* Start automatic synchronization */
+    HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,485 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x100. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100U;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000U;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *             value as defined by the MSI range.
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00U:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-    case 0x04U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0CU:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18U)];
-      plldiv = (plldiv >> 22U) + 1U;
-
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  __HAL_RCC_PWR_CLK_DISABLE();
-
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  // PLLCLK = (16 MHz * 6)/3 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_6;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_3;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select HSI48 as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Configure the clock recovery system (CRS) ********************************/
-  /* Enable CRS Clock */
-  __HAL_RCC_CRS_CLK_ENABLE();
-  /* Default Synchro Signal division factor (not divided) */
-  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
-  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
-  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
-  /* HSI48 is synchronized with USB SOF at 1KHz rate */
-  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
-  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
-  /* Set the TRIM[5:0] to the default value */
-  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
-  /* Start automatic synchronization */
-  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,227 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | NO
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,465 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x100. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100U;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000U;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *             value as defined by the MSI range.
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00U:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-    case 0x04U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0CU:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18U)];
-      plldiv = (plldiv >> 22U) + 1U;
-
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,227 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | NO
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,523 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x100. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
-#define USE_MSI_OSC      (0) /* Use multi-speed internal RC oscillator */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-uint8_t SetSysClock_MSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100U;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000U;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *             value as defined by the MSI range.
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00U:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-    case 0x04U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0CU:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18U)];
-      plldiv = (plldiv >> 22U) + 1U;
-
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail try to start with MSI */
-      #if USE_MSI_OSC != 0
-      if (SetSysClock_MSI() == 0)
-      #endif
-      {
-      /* 4- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-  return 1; // OK
-}
-
-/******************************************************************************/
-/*            MSI (4Mhz) used as System clock source                          */
-/******************************************************************************/
-uint8_t SetSysClock_MSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable MSI Oscillator */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct)!= HAL_OK)
-  {
-    /* Initialization Error */
-    return 0;
-  }
-
-  /* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;  // 4 MHz
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;      // 4 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;       // 4 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;       // 4 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0)!= HAL_OK)
-  {
-    /* Initialization Error */
-    return 0;
-  }
-
-  /* Enable Power Control clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet.  */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
-
-  /* Disable Power Control clock */
-  __HAL_RCC_PWR_CLK_DISABLE();
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -68,7 +68,7 @@
 //*** DAC ***
 
 const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // DAC_OUT
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT
     {NC,   NC,    0}
 };
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,244 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/system_stm32l0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,464 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x100. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100U;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000U;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *             value as defined by the MSI range.
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00U:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-    case 0x04U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0CU:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18U)];
-      plldiv = (plldiv >> 22U) + 1U;
-
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,244 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l0xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100U;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+    /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+    /*!< Reset HSI48ON  bit */
+    RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+    /*!< Disable all interrupts */
+    RCC->CIER = 0x00000000U;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (8 MHz * 8)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = 16;
+    RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
+    // PLLCLK = (16 MHz * 4)/2 = 32 MHz
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,464 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.7.0
-  * @date    31-May-2016
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x100. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
-  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
-  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100U;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400CU;
-
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6U;
-
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000U;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
-  *             value as defined by the MSI range.
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00U:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-    case 0x04U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0CU:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18U)];
-      plldiv = (plldiv >> 22U) + 1U;
-
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
-      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is
-     clocked below the maximum system frequency, to update the voltage scaling value
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) && \
-  !defined (STM32L011xx) && !defined (STM32L021xx)
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-#endif
-  // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/device/system_stm32l0xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,295 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l0xx.c
+  * @author  MCD Application Team
+  * @version V1.7.0
+  * @date    31-May-2016
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l0xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+   
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Defines
+  * @{
+  */
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x100. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 2000000U;
+  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{    
+/*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100U;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t) 0x88FF400CU;
+ 
+  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFF6U;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+  
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+  /*!< Disable all interrupts */
+  RCC->CIER = 0x00000000U;
+  
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00U:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+    case 0x04U:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0CU:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18U)];
+      plldiv = (plldiv >> 22U) + 1U;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -201,16 +201,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
                 irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
                 irq_handler(serial_irq_ids[id], RxIrq);
-                volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -302,7 +301,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
@@ -316,7 +315,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,236 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  */
+
+#include "stm32l1xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t)0x88FFC00C;
+
+    /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+    /*!< Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+    /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+        /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0) {
+                while(1) {
+                    // [TODO] Put something here to tell the user that a problem occured...
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
+        return 1;   // already on HSE PLL, could occur from deepsleep waking
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
+    // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
+    // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
+    while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_stm32l1xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,623 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
-const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t)0x88FFC00C;
-  
-  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xEEFEFFFE;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Flash 1 wait state */
-  FLASH->ACR |= FLASH_ACR_LATENCY;
-  
-  /* Power enable */
-  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
-
-  /* Select the Voltage Range 1 (1.8 V) */
-  PWR->CR = PWR_CR_VOS_0;
-  
-  /* Wait Until the Voltage Regulator is ready */
-  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
-  {
-  }
-  
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  (void)(tmpreg);
-  
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
-    return 1;   // already on HSE PLL, could occur from deepsleep waking
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
-  // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
-  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,234 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *-----------------------------------------------------------------
+  * SYSCLK(MHz)         | 32
+  * AHBCLK (MHz)        | 32
+  * APB1CLK (MHz)       | 32
+  * USB capable         | YES
+  *-----------------------------------------------------------------
+  */
+
+#include "stm32l1xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+#define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI          0x2  // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t)0x88FFC00C;
+
+    /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+    /*!< Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0)
+#endif
+            {
+                while(1) {
+                    MBED_ASSERT(1);
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE oscillator and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    // SYSCLK = 32 MHz (8 MHz *12 /3)
+    // USBCLK = 48 MHz (8 MHz *12 /2)
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    // SYSCLK = 32 MHz (16 MHz *6 /3)
+    // USBCLK = 48 MHz (16 MHz *6 /2)
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
+    while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/system_stm32l1xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,621 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
-const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t)0x88FFC00C;
-  
-  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xEEFEFFFE;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Flash 1 wait state */
-  FLASH->ACR |= FLASH_ACR_LATENCY;
-  
-  /* Power enable */
-  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
-
-  /* Select the Voltage Range 1 (1.8 V) */
-  PWR->CR = PWR_CR_VOS_0;
-  
-  /* Wait Until the Voltage Regulator is ready */
-  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
-  {
-  }
-  
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  (void)(tmpreg);
-  
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
-  // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
-  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,234 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC         | 3- PLL_HSI
+  *                                    | (external 16 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL         |
+  *                                    | (external 16 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  */
+
+#include "stm32l1xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t)0x88FFC00C;
+
+    /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+    /*!< Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+    /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+        /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0) {
+                while(1) {
+                    // [TODO] Put something here to tell the user that a problem occured...
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 16 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 16 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    // SYSCLK = 32 MHz ((16 MHz * 6) / 3)
+    // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> USB OK
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
+    // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
+    while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_stm32l1xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,618 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC         | 3- PLL_HSI
-  *                                    | (external 16 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL         |
-  *                                    | (external 16 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#define HSE_VALUE    ((uint32_t)16000000) /*!< NZ32-SC151 has a 16MHz External crystal */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
-const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t)0x88FFC00C;
-  
-  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xEEFEFFFE;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Flash 1 wait state */
-  FLASH->ACR |= FLASH_ACR_LATENCY;
-  
-  /* Power enable */
-  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
-
-  /* Select the Voltage Range 1 (1.8 V) */
-  PWR->CR = PWR_CR_VOS_0;
-  
-  /* Wait Until the Voltage Regulator is ready */
-  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
-  {
-  }
-  
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  (void)(tmpreg);
-  
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 16 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 16 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 32 MHz ((16 MHz * 6) / 3)
-  // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> USB OK
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
-
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
-  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct	Thu Aug 03 13:13:39 2017 +0100
@@ -1,3 +1,4 @@
+#! armcc -E
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Copyright (c) 2015, STMicroelectronics
@@ -27,10 +28,19 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x40000
+#endif
+
+
 ; STM32L151RC: 256KB FLASH + 32KB SRAM
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
 
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_STD/stm32l151rc.sct	Thu Aug 03 13:13:39 2017 +0100
@@ -1,3 +1,4 @@
+#! armcc -E
 ; Scatter-Loading Description File
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Copyright (c) 2015, STMicroelectronics
@@ -27,10 +28,19 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x40000
+#endif
+
+
 ; STM32L151RC: 256KB FLASH + 32KB SRAM
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
 
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_GCC_ARM/STM32L151XC.ld	Thu Aug 03 13:13:39 2017 +0100
@@ -1,11 +1,17 @@
 /* Linker script to configure memory regions. */
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
 
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 256k
+#endif
 MEMORY
 {
   /* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
    * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
    */
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
+  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
   RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
 }
 

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_IAR/stm32l152xc.icf	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_IAR/stm32l152xc.icf	Thu Aug 03 13:13:39 2017 +0100
@@ -1,7 +1,9 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; }
 /* [ROM = 256kb = 0x40000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0803FFFF;
+define symbol __intvec_start__     = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
 
 /* [RAM = 32kb = 0x8000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */
 define symbol __NVIC_start__          = 0x20000000;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,259 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC         | 3- PLL_HSI
+  *                                    | (external 24 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL         |
+  *                                    | (external 24 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  */
+
+#include "stm32l1xx.h"
+#include "stdio.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t)0x88FFC00C;
+
+    /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+    /*!< Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+
+#if defined(__ICCARM__)
+#pragma section=".intvec"
+#define FLASH_VTOR_BASE   ((uint32_t)__section_begin(".intvec"))
+#elif defined(__CC_ARM)
+    extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+#define FLASH_VTOR_BASE   ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__GNUC__)
+    extern uint32_t g_pfnVectors[];
+#define FLASH_VTOR_BASE   ((uint32_t)g_pfnVectors)
+#else
+#error "Flash vector address not set for this toolchain"
+#endif
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_VTOR_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+    /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+        /* 2- If fail try to start with HSE and external xtal */
+#if USE_PLL_HSE_XTAL != 0
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI() == 0) {
+                while(1) {
+                    // [TODO] Put something here to tell the user that a problem occured...
+                }
+            }
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* Used to gain time after DeepSleep in case HSI is used */
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
+    } else {
+        RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 24 MHz clock on OSC_IN */
+    }
+    RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
+    // SYSCLK = 32 MHz ((24 MHz * 4) / 3)
+    // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //if (bypass == 0)
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    //else
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+
+    return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
+    // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
+    while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}
+
+/******************************************************************************/
+/*            Hard Fault Handler                                              */
+/******************************************************************************/
+void HardFault_Handler(void)
+{
+    printf("Hard Fault\n");
+    NVIC_SystemReset();
+}
+

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_stm32l1xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,628 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC         | 3- PLL_HSI
-  *                                    | (external 24 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL         |
-  *                                    | (external 24 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-#include "stdio.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#define HSE_VALUE    ((uint32_t)24000000) /*!< XDOT-L151CC has a 24MHz External crystal */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
-const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t)0x88FFC00C;
-  
-  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xEEFEFFFE;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Flash 1 wait state */
-  FLASH->ACR |= FLASH_ACR_LATENCY;
-  
-  /* Power enable */
-  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
-
-  /* Select the Voltage Range 1 (1.8 V) */
-  PWR->CR = PWR_CR_VOS_0;
-  
-  /* Wait Until the Voltage Regulator is ready */
-  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
-  {
-  }
-  
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  (void)(tmpreg);
-  
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 24 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 32 MHz ((24 MHz * 4) / 3)
-  // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
-
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
-  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/******************************************************************************/
-/*            Hard Fault Handler                                              */
-/******************************************************************************/
-void HardFault_Handler(void)
-{
-  printf("Hard Fault\n");
-  NVIC_SystemReset();
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L1/common_objects.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/common_objects.h	Thu Aug 03 13:13:39 2017 +0100
@@ -110,6 +110,11 @@
 #endif
 };
 
+struct flash_s {
+    /*  nothing to be stored for now */
+    uint32_t dummy;
+};
+
 struct dac_s {
     DACName dac;
     PinName pin;

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c	Thu Aug 03 13:13:39 2017 +0100
@@ -1337,7 +1337,7 @@
 
     /* Enable Acknowledge */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    
+
     /* Generate Start */
     SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
@@ -1428,8 +1428,17 @@
     /* Generate Start */
     if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) || (hi2c->PreviousState == I2C_STATE_NONE))
     {
-        /* Generate Start or ReStart */
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate Start */
         SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
+      else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+      {
+        /* Generate ReStart */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
     }
 
     /* Process Unlocked */
@@ -1518,10 +1527,23 @@
 
     if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
     {
+      /* Generate Start condition if first transfer */
+      if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)  || (XferOptions == I2C_NO_OPTION_FRAME))
+      {
         /* Enable Acknowledge */
         SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-        /* Generate Start or ReStart */
+
+        /* Generate Start */
         SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
+      else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Generate ReStart */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
     }
 
     /* Process Unlocked */
@@ -3866,11 +3888,15 @@
     {
       /* Disable Acknowledge */
       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+      if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
+      {
+        /* Generate ReStart */
+        hi2c->Instance->CR1 |= I2C_CR1_START;
+      }
     }
     else
     {
-      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
-
       /* Generate Stop */
       hi2c->Instance->CR1 |= I2C_CR1_STOP;
     }

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/system_stm32l1xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,452 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V2.2.0
+  * @date    01-July-2016
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *             
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock        = 2097000;
+const uint8_t PLLMulTable[9]    = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Flash 1 wait state */
+  FLASH->ACR |= FLASH_ACR_LATENCY;
+  
+  /* Power enable */
+  RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
+
+  /* Select the Voltage Range 1 (1.8 V) */
+  PWR->CR = PWR_CR_VOS_0;
+  
+  /* Wait Until the Voltage Regulator is ready */
+  while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+  {
+  }
+  
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+  
+  (void)(tmpreg);
+  
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,143 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+#include "mbed_assert.h"
+#include "cmsis.h"
+
+/*  L1 targets embed 16 pages sectors */
+#define NUM_PAGES_IN_SECTOR 16
+
+int32_t flash_init(flash_t *obj)
+{
+    /* Unlock the Flash to enable the flash control register access *************/
+    HAL_FLASH_Unlock();
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    /* Lock the Flash to disable the flash control register access (recommended
+     * to protect the FLASH memory against possible unwanted operation) *********/
+    HAL_FLASH_Lock();
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    uint32_t FirstPage = 0;
+    uint32_t PAGEError = 0;
+    FLASH_EraseInitTypeDef EraseInitStruct;
+
+    if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+
+        return -1;
+    }
+
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR | FLASH_FLAG_EOP | FLASH_FLAG_PGAERR | FLASH_FLAG_WRPERR);
+    /* MBED HAL erases 1 sector at a time */
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.PageAddress = address;
+    EraseInitStruct.NbPages     = NUM_PAGES_IN_SECTOR;
+
+    /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
+     you have to make sure that these data are rewritten before they are accessed during code
+     execution. If this cannot be done safely, it is recommended to flush the caches by setting the
+     DCRST and ICRST bits in the FLASH_CR register. */
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address,
+        const uint8_t *data, uint32_t size)
+{
+    uint32_t StartAddress = 0;
+
+    if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+        return -1;
+    }
+
+    if ((size % 4) != 0) {
+        /* L1 flash devices can only be programmed 32bits/4 bytes at a time */
+        return -1;
+    }
+
+    /* Program the user Flash area word by word */
+    StartAddress = address;
+
+    /*  HW needs an aligned address to program flash, which data
+     *  parameters doesn't ensure  */
+    if ((uint32_t) data % 4 != 0) {
+        volatile uint32_t data32;
+        while (address < (StartAddress + size)) {
+            for (uint8_t i =0; i < 4; i++) {
+                *(((uint8_t *) &data32) + i) = *(data + i);
+            }
+
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data32) == HAL_OK) {
+                address = address + 4;
+                data = data + 4;
+            } else {
+                return -1;
+            }
+        }
+    } else { /*  case where data is aligned, so let's avoid any copy */
+        while (address < (StartAddress + size)) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
+                address = address + 4;
+                data = data + 4;
+            } else {
+                return -1;
+            }
+        }
+    }
+
+    return 0;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) 
+{
+    if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+        return MBED_FLASH_INVALID_SIZE;
+    } else {
+        return (NUM_PAGES_IN_SECTOR * FLASH_PAGE_SIZE);
+    }
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return FLASH_PAGE_SIZE;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj) 
+{
+    return FLASH_BASE;
+}
+
+uint32_t flash_get_size(const flash_t *obj) 
+{
+    return FLASH_SIZE;
+}
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -190,16 +190,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
                 irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
                 irq_handler(serial_irq_ids[id], RxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -284,7 +283,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
@@ -298,7 +297,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,374 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.c
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        | or PLL_MSI
+  *                                    | (external 8 MHz xtal)  | (internal 4 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 48                     | 80
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_stm32l4xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,580 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l4xx.c
-  * @author  MCD Application Team
-  * @version V1.3.1
-  * @date    21-April-2017
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l4xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *   After each device reset the MSI (4 MHz) is used as system clock source.
-  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
-  *   configure the system clock before to branch to main program.
-  *
-  *   This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        | or PLL_MSI
-  *                                    | (external 8 MHz xtal)  | (internal 4 MHz)
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                     | 80
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                     | 80
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                     | 80
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 48                     | 80
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l4xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l4xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Macros
-  * @{
-  */
-
-// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
-#define USE_PLL_HSE_EXTC (0) // Use external clock
-#define USE_PLL_HSE_XTAL (0) // Use external xtal
-#define USE_PLL_HSI      (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
-#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 4000000;
-
-  const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
-  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
-                                      4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-#if (USE_PLL_HSI != 0)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif
-
-uint8_t SetSysClock_PLL_MSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set MSION bit */
-  RCC->CR |= RCC_CR_MSION;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON , HSION, and PLLON bits */
-  RCC->CR &= (uint32_t)0xEAF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x00001000;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
-  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *             4 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              16 MHz) but the real value may vary depending on the variations
-  *              in voltage and temperature.
-  *
-  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
-
-  /* Get MSI Range frequency--------------------------------------------------*/
-  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
-  { /* MSISRANGE from RCC_CSR applies */
-    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
-  }
-  else
-  { /* MSIRANGE from RCC_CR applies */
-    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
-  }
-  /*MSI frequency range in HZ*/
-  msirange = MSIRangeTable[msirange];
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case 0x00:  /* MSI used as system clock source */
-      SystemCoreClock = msirange;
-      break;
-
-    case 0x04:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-
-    case 0x08:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-
-    case 0x0C:  /* PLL used as system clock  source */
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
-         SYSCLK = PLL_VCO / PLLR
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
-
-      switch (pllsource)
-      {
-        case 0x02:  /* HSI used as PLL clock source */
-          pllvco = (HSI_VALUE / pllm);
-          break;
-
-        case 0x03:  /* HSE used as PLL clock source */
-          pllvco = (HSE_VALUE / pllm);
-          break;
-
-        default:    /* MSI used as PLL clock source */
-          pllvco = (msirange / pllm);
-          break;
-      }
-      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
-      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
-      SystemCoreClock = pllvco/pllr;
-      break;
-
-    default:
-      SystemCoreClock = msirange;
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-#if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-    {
-      /* 3- If fail start with HSI or MSI clock */
-#if (USE_PLL_HSI != 0)
-      if (SetSysClock_PLL_HSI() == 0)
-#else
-      if (SetSysClock_PLL_MSI() == 0)
-#endif
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 1
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-#endif
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-
-  // Used to gain time after DeepSleep in case HSI is used
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-    
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
-  }
-  RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
-  RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
-  RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
-  
-  // Non-USB configuration : sysclock = 80MHz
-  //RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  //RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  //RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  //RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  //RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
-
-  // USB configuration : sysclock = 48 MHz
-  RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  RCC_OscInitStruct.PLL.PLLN              = 24; // VCO output clock = 192 MHz (8 MHz * 24)
-  RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR              = 4; // PLL clock = 48 MHz (192 MHz / 4)
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 2
-  if (bypass == 0)
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  else
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-#if (USE_PLL_HSI != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-  
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
-  RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ             = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 3
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by MSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_MSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  
-  // Enable LSE Oscillator to automatically calibrate the MSI clock
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-    RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
-  }
-  
-  // Enable MSI oscillator and activate PLL with MSI as source
-  RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
-  RCC_OscInitStruct.MSIClockRange        = RCC_MSIRANGE_6;
-  RCC_OscInitStruct.MSICalibrationValue  = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_MSI; // 4 MHz
-  RCC_OscInitStruct.PLL.PLLM             = 1; // VCO input clock = 4 MHz (4 MHz / 1)
-  RCC_OscInitStruct.PLL.PLLN             = 40; // VCO output clock = 160 MHz (4 MHz * 40)
-  RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ             = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 4
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
-#endif
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -105,7 +105,7 @@
 //*** I2C ***
 
 const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Pin not available on any connector
+//    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Pin not available on any connector
     {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14
     {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Pin not available on any connector
     {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED2
@@ -114,7 +114,7 @@
 };
 
 const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Pin not available on any connector
+//    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Pin not available on any connector
     {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D15
     {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Pin not available on any connector
     {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Pin not available on any connector
@@ -159,10 +159,10 @@
     {PB_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 Pin not available on any connector
     {PB_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 ARDUINO D5
     {PB_5,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 Pin not available on any connector
-    {PB_6,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 Pin not available on any connector
-    {PB_6_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N Pin not available on any connector
-    {PB_7,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 Pin not available on any connector
-    {PB_7_ALT0,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N Pin not available on any connector
+//    {PB_6,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 Pin not available on any connector
+//    {PB_6_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N Pin not available on any connector
+//    {PB_7,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 Pin not available on any connector
+//    {PB_7_ALT0,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N Pin not available on any connector
     {PB_8,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 ARDUINO D15
     {PB_8_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 ARDUINO D15
     {PB_9,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 ARDUINO D14
@@ -262,7 +262,7 @@
     {PA_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Pin not available on any connector
     {PB_4,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO D5
     {PB_5,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Pin not available on any connector
-    {PB_7,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Pin not available on any connector
+//    {PB_7,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Pin not available on any connector
     {PB_13,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Pin not available on any connector
     {PB_13_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Pin not available on any connector
     {PD_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // PMOD 3

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_stm32l4xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,587 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l4xx.c
-  * @author  MCD Application Team
-  * @version V1.3.1
-  * @date    21-April-2017
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l4xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *   After each device reset the MSI (4 MHz) is used as system clock source.
-  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
-  *   configure the system clock before to branch to main program.
-  *
-  *   This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | PLL_HSE                     | PLL_HSI           | PLL_MSI
-  *                                    | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
-  *---------------------------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                         | NO                | YES
-  *---------------------------------------------------------------------------------------------
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l4xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l4xx.h"
-#include "nvic_addr.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Macros
-  * @{
-  */
-
-// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
-#define USE_PLL_HSE_EXTC (0) // Use external clock
-#define USE_PLL_HSE_XTAL (0) // Use external xtal
-#define USE_PLL_HSI      (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
-#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 4000000;
-
-  const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
-  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
-                                      4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-#if (USE_PLL_HSI != 0)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif
-
-uint8_t SetSysClock_PLL_MSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set MSION bit */
-  RCC->CR |= RCC_CR_MSION;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON , HSION, and PLLON bits */
-  RCC->CR &= (uint32_t)0xEAF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x00001000;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
-  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *             4 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              16 MHz) but the real value may vary depending on the variations
-  *              in voltage and temperature.
-  *
-  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
-
-  /* Get MSI Range frequency--------------------------------------------------*/
-  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
-  { /* MSISRANGE from RCC_CSR applies */
-    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
-  }
-  else
-  { /* MSIRANGE from RCC_CR applies */
-    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
-  }
-  /*MSI frequency range in HZ*/
-  msirange = MSIRangeTable[msirange];
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case 0x00:  /* MSI used as system clock source */
-      SystemCoreClock = msirange;
-      break;
-
-    case 0x04:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-
-    case 0x08:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-
-    case 0x0C:  /* PLL used as system clock  source */
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
-         SYSCLK = PLL_VCO / PLLR
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
-
-      switch (pllsource)
-      {
-        case 0x02:  /* HSI used as PLL clock source */
-          pllvco = (HSI_VALUE / pllm);
-          break;
-
-        case 0x03:  /* HSE used as PLL clock source */
-          pllvco = (HSE_VALUE / pllm);
-          break;
-
-        default:    /* MSI used as PLL clock source */
-          pllvco = (msirange / pllm);
-          break;
-      }
-      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
-      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
-      SystemCoreClock = pllvco/pllr;
-      break;
-
-    default:
-      SystemCoreClock = msirange;
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-#if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-    {
-      /* 3- If fail start with HSI or MSI clock */
-#if (USE_PLL_HSI != 0)
-      if (SetSysClock_PLL_HSI() == 0)
-#else
-      if (SetSysClock_PLL_MSI() == 0)
-#endif
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 1
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-#endif
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-
-  // Used to gain time after DeepSleep in case HSI is used
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-    
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
-  }
-  RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
-  RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
-  RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
-  
-  // Non-USB configuration : sysclock = 80MHz
-  //RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  //RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  //RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  //RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  //RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
-
-  // USB configuration : sysclock = 48 MHz
-  RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  RCC_OscInitStruct.PLL.PLLN              = 24; // VCO output clock = 192 MHz (8 MHz * 24)
-  RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR              = 4; // PLL clock = 48 MHz (192 MHz / 4)
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 2
-  if (bypass == 0)
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  else
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-#if (USE_PLL_HSI != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-  
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
-  RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ             = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 3
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by MSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_MSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  // Enable LSE Oscillator to automatically calibrate the MSI clock
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-    RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
-  }
-
-  HAL_RCCEx_DisableLSECSS();
-   /* Enable MSI Oscillator and activate PLL with MSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
-
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
-  RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
-  RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
-  RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
-  RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-   /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 4
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
-#endif
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/nvic_addr.h	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef NVIC_ADDR_H
-#define NVIC_ADDR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__ICCARM__)
-    #pragma section=".intvec"
-    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)__section_begin(".intvec"))
-#elif defined(__CC_ARM)
-    extern uint32_t Load$$LR$$LR_IROM1$$Base[];
-    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)Load$$LR$$LR_IROM1$$Base)
-#elif defined(__GNUC__)
-    extern uint32_t g_pfnVectors[];
-    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)g_pfnVectors)
-#else
-    #error "Flash vector address not set for this toolchain"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_stm32l4xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,587 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l4xx.c
-  * @author  MCD Application Team
-  * @version V1.3.1
-  * @date    21-April-2017
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l4xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *   After each device reset the MSI (4 MHz) is used as system clock source.
-  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
-  *   configure the system clock before to branch to main program.
-  *
-  *   This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | PLL_HSE                     | PLL_HSI           | PLL_MSI
-  *                                    | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
-  *---------------------------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                         | NO                | YES
-  *---------------------------------------------------------------------------------------------
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l4xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l4xx.h"
-#include "nvic_addr.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Macros
-  * @{
-  */
-
-// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
-#define USE_PLL_HSE_EXTC (0) // Use external clock
-#define USE_PLL_HSE_XTAL (0) // Use external xtal
-#define USE_PLL_HSI      (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
-#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 4000000;
-
-  const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
-  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
-                                      4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-#if (USE_PLL_HSI != 0)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif
-
-uint8_t SetSysClock_PLL_MSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set MSION bit */
-  RCC->CR |= RCC_CR_MSION;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON , HSION, and PLLON bits */
-  RCC->CR &= (uint32_t)0xEAF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x00001000;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
-  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *             4 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              16 MHz) but the real value may vary depending on the variations
-  *              in voltage and temperature.
-  *
-  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
-
-  /* Get MSI Range frequency--------------------------------------------------*/
-  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
-  { /* MSISRANGE from RCC_CSR applies */
-    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
-  }
-  else
-  { /* MSIRANGE from RCC_CR applies */
-    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
-  }
-  /*MSI frequency range in HZ*/
-  msirange = MSIRangeTable[msirange];
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case 0x00:  /* MSI used as system clock source */
-      SystemCoreClock = msirange;
-      break;
-
-    case 0x04:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-
-    case 0x08:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-
-    case 0x0C:  /* PLL used as system clock  source */
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
-         SYSCLK = PLL_VCO / PLLR
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
-
-      switch (pllsource)
-      {
-        case 0x02:  /* HSI used as PLL clock source */
-          pllvco = (HSI_VALUE / pllm);
-          break;
-
-        case 0x03:  /* HSE used as PLL clock source */
-          pllvco = (HSE_VALUE / pllm);
-          break;
-
-        default:    /* MSI used as PLL clock source */
-          pllvco = (msirange / pllm);
-          break;
-      }
-      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
-      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
-      SystemCoreClock = pllvco/pllr;
-      break;
-
-    default:
-      SystemCoreClock = msirange;
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-#if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-    {
-      /* 3- If fail start with HSI or MSI clock */
-#if (USE_PLL_HSI != 0)
-      if (SetSysClock_PLL_HSI() == 0)
-#else
-      if (SetSysClock_PLL_MSI() == 0)
-#endif
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 1
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-#endif
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-
-  // Used to gain time after DeepSleep in case HSI is used
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-    
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
-  }
-  RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
-  RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
-  RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
-  
-  // Non-USB configuration : sysclock = 80MHz
-  //RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  //RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  //RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  //RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  //RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
-
-  // USB configuration : sysclock = 48 MHz
-  RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  RCC_OscInitStruct.PLL.PLLN              = 24; // VCO output clock = 192 MHz (8 MHz * 24)
-  RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR              = 4; // PLL clock = 48 MHz (192 MHz / 4)
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 2
-  if (bypass == 0)
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  else
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-#if (USE_PLL_HSI != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-  
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
-  RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ             = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 3
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by MSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_MSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  // Enable LSE Oscillator to automatically calibrate the MSI clock
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-    RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
-  }
-
-  HAL_RCCEx_DisableLSECSS();
-   /* Enable MSI Oscillator and activate PLL with MSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
-
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
-  RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
-  RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
-  RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
-  RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-   /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 4
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
-#endif
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_stm32l4xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,587 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l4xx.c
-  * @author  MCD Application Team
-  * @version V1.3.1
-  * @date    21-April-2017
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l4xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *   After each device reset the MSI (4 MHz) is used as system clock source.
-  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
-  *   configure the system clock before to branch to main program.
-  *
-  *   This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | PLL_HSE                     | PLL_HSI           | PLL_MSI
-  *                                    | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
-  *---------------------------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                         | NO                | YES
-  *---------------------------------------------------------------------------------------------
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l4xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l4xx.h"
-#include "nvic_addr.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Macros
-  * @{
-  */
-
-// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
-#define USE_PLL_HSE_EXTC (0) // Use external clock
-#define USE_PLL_HSE_XTAL (0) // Use external xtal
-#define USE_PLL_HSI      (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
-#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 4000000;
-
-  const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
-  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
-                                      4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-#if (USE_PLL_HSI != 0)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif
-
-uint8_t SetSysClock_PLL_MSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set MSION bit */
-  RCC->CR |= RCC_CR_MSION;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON , HSION, and PLLON bits */
-  RCC->CR &= (uint32_t)0xEAF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x00001000;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS;; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
-  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *             4 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              16 MHz) but the real value may vary depending on the variations
-  *              in voltage and temperature.
-  *
-  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
-
-  /* Get MSI Range frequency--------------------------------------------------*/
-  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
-  { /* MSISRANGE from RCC_CSR applies */
-    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
-  }
-  else
-  { /* MSIRANGE from RCC_CR applies */
-    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
-  }
-  /*MSI frequency range in HZ*/
-  msirange = MSIRangeTable[msirange];
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case 0x00:  /* MSI used as system clock source */
-      SystemCoreClock = msirange;
-      break;
-
-    case 0x04:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-
-    case 0x08:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-
-    case 0x0C:  /* PLL used as system clock  source */
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
-         SYSCLK = PLL_VCO / PLLR
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
-
-      switch (pllsource)
-      {
-        case 0x02:  /* HSI used as PLL clock source */
-          pllvco = (HSI_VALUE / pllm);
-          break;
-
-        case 0x03:  /* HSE used as PLL clock source */
-          pllvco = (HSE_VALUE / pllm);
-          break;
-
-        default:    /* MSI used as PLL clock source */
-          pllvco = (msirange / pllm);
-          break;
-      }
-      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
-      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
-      SystemCoreClock = pllvco/pllr;
-      break;
-
-    default:
-      SystemCoreClock = msirange;
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-#if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-    {
-      /* 3- If fail start with HSI or MSI clock */
-#if (USE_PLL_HSI != 0)
-      if (SetSysClock_PLL_HSI() == 0)
-#else
-      if (SetSysClock_PLL_MSI() == 0)
-#endif
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 1
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-#endif
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-
-  // Used to gain time after DeepSleep in case HSI is used
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-    
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
-  }
-  RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
-  RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
-  RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
-  
-  // Non-USB configuration : sysclock = 80MHz
-  //RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  //RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  //RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  //RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  //RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
-
-  // USB configuration : sysclock = 48 MHz
-  RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  RCC_OscInitStruct.PLL.PLLN              = 24; // VCO output clock = 192 MHz (8 MHz * 24)
-  RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR              = 4; // PLL clock = 48 MHz (192 MHz / 4)
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 2
-  if (bypass == 0)
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  else
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-#if (USE_PLL_HSI != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-  
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
-  RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ             = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 3
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by MSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_MSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  // Enable LSE Oscillator to automatically calibrate the MSI clock
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-    RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
-  }
-
-  HAL_RCCEx_DisableLSECSS();
-   /* Enable MSI Oscillator and activate PLL with MSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
-
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
-  RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
-  RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
-  RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
-  RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-   /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 4
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
-#endif
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/nvic_addr.h	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef NVIC_ADDR_H
-#define NVIC_ADDR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__ICCARM__)
-    #pragma section=".intvec"
-    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)__section_begin(".intvec"))
-#elif defined(__CC_ARM)
-    extern uint32_t Load$$LR$$LR_IROM1$$Base[];
-    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)Load$$LR$$LR_IROM1$$Base)
-#elif defined(__GNUC__)
-    extern uint32_t g_pfnVectors[];
-    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)g_pfnVectors)
-#else
-    #error "Flash vector address not set for this toolchain"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_stm32l4xx.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,586 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l4xx.c
-  * @author  MCD Application Team
-  * @version V1.3.1
-  * @date    21-April-2017
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l4xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *   After each device reset the MSI (4 MHz) is used as system clock source.
-  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
-  *   configure the system clock before to branch to main program.
-  *
-  *   This file configures the system clock as follows:
-  *=============================================================================
-  * System clock source                | PLL_HSE                     | PLL_HSI           | PLL_MSI
-  *                                    | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
-  *---------------------------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 48                          | 80                | 80
-  *---------------------------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                         | NO                | YES
-  *---------------------------------------------------------------------------------------------
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l4xx_system
-  * @{
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l4xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Macros
-  * @{
-  */
-
-// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
-#define USE_PLL_HSE_EXTC (0) // Use external clock
-#define USE_PLL_HSE_XTAL (0) // Use external xtal
-#define USE_PLL_HSI      (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
-#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 4000000;
-
-  const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
-  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
-                                      4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-#if (USE_PLL_HSI != 0)
-uint8_t SetSysClock_PLL_HSI(void);
-#endif
-
-uint8_t SetSysClock_PLL_MSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L4xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set MSION bit */
-  RCC->CR |= RCC_CR_MSION;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON , HSION, and PLLON bits */
-  RCC->CR &= (uint32_t)0xEAF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x00001000;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
-  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *             4 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              16 MHz) but the real value may vary depending on the variations
-  *              in voltage and temperature.
-  *
-  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
-
-  /* Get MSI Range frequency--------------------------------------------------*/
-  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
-  { /* MSISRANGE from RCC_CSR applies */
-    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
-  }
-  else
-  { /* MSIRANGE from RCC_CR applies */
-    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
-  }
-  /*MSI frequency range in HZ*/
-  msirange = MSIRangeTable[msirange];
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case 0x00:  /* MSI used as system clock source */
-      SystemCoreClock = msirange;
-      break;
-
-    case 0x04:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-
-    case 0x08:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-
-    case 0x0C:  /* PLL used as system clock  source */
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
-         SYSCLK = PLL_VCO / PLLR
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
-
-      switch (pllsource)
-      {
-        case 0x02:  /* HSI used as PLL clock source */
-          pllvco = (HSI_VALUE / pllm);
-          break;
-
-        case 0x03:  /* HSE used as PLL clock source */
-          pllvco = (HSE_VALUE / pllm);
-          break;
-
-        default:    /* MSI used as PLL clock source */
-          pllvco = (msirange / pllm);
-          break;
-      }
-      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
-      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
-      SystemCoreClock = pllvco/pllr;
-      break;
-
-    default:
-      SystemCoreClock = msirange;
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-#if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-#endif
-    {
-      /* 3- If fail start with HSI or MSI clock */
-#if (USE_PLL_HSI != 0)
-      if (SetSysClock_PLL_HSI() == 0)
-#else
-      if (SetSysClock_PLL_MSI() == 0)
-#endif
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 1
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-#endif
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-
-  // Used to gain time after DeepSleep in case HSI is used
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-    
-  // Enable HSE oscillator and activate PLL with HSE as source
-  RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
-  }
-  RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
-  RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
-  RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
-  
-  // Non-USB configuration : sysclock = 80MHz
-  //RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  //RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  //RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  //RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  //RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
-
-  // USB configuration : sysclock = 48 MHz
-  RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
-  RCC_OscInitStruct.PLL.PLLN              = 24; // VCO output clock = 192 MHz (8 MHz * 24)
-  RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ              = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
-  RCC_OscInitStruct.PLL.PLLR              = 4; // PLL clock = 48 MHz (192 MHz / 4)
-  
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 2
-  if (bypass == 0)
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  else
-    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-#if (USE_PLL_HSI != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 
-  // Select MSI as system clock source to allow modification of the PLL configuration
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-  
-  // Enable HSI oscillator and activate PLL with HSI as source
-  RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
-  RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
-  RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
-  RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
-  RCC_OscInitStruct.PLL.PLLQ             = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
-  RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  // Disable MSI Oscillator
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 3
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-#endif
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by MSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_MSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  // Enable LSE Oscillator to automatically calibrate the MSI clock
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
-  RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-    RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
-  }
-
-  HAL_RCCEx_DisableLSECSS();
-   /* Enable MSI Oscillator and activate PLL with MSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
-  RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
-
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
-  RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
-  RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
-  RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
-  RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-   /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;           /* 40 MHz */
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  // Output clock on MCO1 pin(PA8) for debugging purpose
-#if DEBUG_MCO == 4
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
-#endif
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -47,8 +47,8 @@
 
     // ADC Internal Channels "pins"  (Temperature, Vref, Vbat, ...)
     //   are described in PinNames.h and PeripheralPins.c
-    //   Pin value must be >= 0xF0
-    if (pin < 0xF0) {
+    //   Pin value must be between 0xF0 and 0xFF
+    if ((pin < 0xF0) || (pin >= 0x100)) {
         // Normal channels
         // Get the peripheral name from the pin and assign it to the object
         obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/system_stm32l4xx.c	Thu Aug 03 13:13:39 2017 +0100
@@ -0,0 +1,362 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.c
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l4xx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 4000000;
+
+  const uint8_t  AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t  APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
+  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
+                                      4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Private_Functions
+  * @{
+  */
+
+/*+ MBED */
+#if 0
+/*- MBED */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= RCC_CR_MSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON , HSION, and PLLON bits */
+  RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00001000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/*+ MBED */
+#endif
+/*- MBED */
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
+  { /* MSISRANGE from RCC_CSR applies */
+    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
+  }
+  else
+  { /* MSIRANGE from RCC_CR applies */
+    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
+  }
+  /*MSI frequency range in HZ*/
+  msirange = MSIRangeTable[msirange];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:  /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C:  /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
+
+      switch (pllsource)
+      {
+        case 0x02:  /* HSI used as PLL clock source */
+          pllvco = (HSI_VALUE / pllm);
+          break;
+
+        case 0x03:  /* HSE used as PLL clock source */
+          pllvco = (HSE_VALUE / pllm);
+          break;
+
+        default:    /* MSI used as PLL clock source */
+          pllvco = (msirange / pllm);
+          break;
+      }
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c	Thu Aug 03 13:13:39 2017 +0100
@@ -217,16 +217,15 @@
     UART_HandleTypeDef * huart = &uart_handlers[id];
     
     if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
-            if (__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) {
-            irq_handler(serial_irq_ids[id], TxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
+            if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
+                irq_handler(serial_irq_ids[id], TxIrq);
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
             if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
-            irq_handler(serial_irq_ids[id], RxIrq);
-                __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
+                irq_handler(serial_irq_ids[id], RxIrq);
+                /*  Flag has been cleared when reading the content */
             }
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
@@ -330,7 +329,7 @@
         if (irq == RxIrq) {
             __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
         } else { // TxIrq
-            __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
         }
         NVIC_SetVector(irq_n, vector);
         NVIC_EnableIRQ(irq_n);
@@ -344,7 +343,7 @@
                 all_disabled = 1;
             }
         } else { // TxIrq
-            __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+            __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
             // Check if RxIrq is disabled too
             if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
                 all_disabled = 1;

--- a/targets/TARGET_STM/can_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/can_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -85,8 +85,8 @@
         error("Cannot initialize CAN");
     }
 
-    // Set initial CAN frequency to 100 kb/s
-    if (can_frequency(obj, 100000) != 1) {
+    // Set initial CAN frequency to specified frequency
+    if (can_frequency(obj, hz) != 1) {
         error("Can frequency could not be set\n");
     }
 

--- a/targets/TARGET_STM/gpio_irq_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/gpio_irq_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -90,8 +90,9 @@
             if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
                 __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
 
-                if (gpio_channel->channel_ids[gpio_idx] == 0)
+                if (gpio_channel->channel_ids[gpio_idx] == 0) {
                     continue;
+                }
 
                 // Check which edge has generated the irq
                 if ((gpio->IDR & pin) == 0) {
@@ -99,9 +100,11 @@
                 } else {
                     irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
                 }
+                return;
             }
         }
     }
+    error("Unexpected Spurious interrupt, index %d\r\n", irq_index);
 }
 
 
@@ -254,18 +257,23 @@
 
 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
 {
+    /*  Enable / Disable Edge triggered interrupt and store event */
     if (event == IRQ_RISE) {
         if (enable) {
             LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event |= IRQ_RISE;
         } else {
             LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event &= ~IRQ_RISE;
         }
     }
     if (event == IRQ_FALL) {
         if (enable) {
             LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event |= IRQ_FALL;
         } else {
             LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+            obj->event &= ~IRQ_FALL;
         }
     }
 }
@@ -284,14 +292,23 @@
 
     LL_EXTI_EnableIT_0_31(1 << pin_index);
 
+    /* Restore previous edge interrupt configuration if applicable */
+    if (obj->event & IRQ_RISE) {
+        LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+    }
+    if (obj->event & IRQ_FALL) {
+        LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
+    }
+
     NVIC_EnableIRQ(obj->irq_n);
 }
 
 void gpio_irq_disable(gpio_irq_t *obj)
 {
     /* Clear EXTI line configuration */
+    LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
+    LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
     LL_EXTI_DisableIT_0_31(1 << STM_PIN(obj->pin));
     NVIC_DisableIRQ(obj->irq_n);
     NVIC_ClearPendingIRQ(obj->irq_n);
-    obj->event = EDGE_NONE;
 }

--- a/targets/TARGET_STM/i2c_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/i2c_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -743,13 +743,6 @@
     int count = I2C_ERROR_BUS_BUSY, ret = 0;
     uint32_t timeout = 0;
 
-    if((length == 0) || (data == 0)) {
-        if(HAL_I2C_IsDeviceReady(handle, address, 1, 10) == HAL_OK)
-            return 0;
-        else
-            return I2C_ERROR_BUS_BUSY;
-    }
-
     if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
         (obj_s->XferOperation == I2C_LAST_FRAME)) {
         if (stop)
@@ -802,13 +795,6 @@
     int count = I2C_ERROR_BUS_BUSY, ret = 0;
     uint32_t timeout = 0;
 
-    if((length == 0) || (data == 0)) {
-        if(HAL_I2C_IsDeviceReady(handle, address, 1, 10) == HAL_OK)
-            return 0;
-        else
-            return I2C_ERROR_BUS_BUSY;
-    }
-
     if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
         (obj_s->XferOperation == I2C_LAST_FRAME)) {
         if (stop)

--- a/targets/TARGET_STM/mbed_rtx.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/mbed_rtx.h	Thu Aug 03 13:13:39 2017 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2017 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -17,298 +17,90 @@
 #ifndef MBED_MBED_RTX_H
 #define MBED_MBED_RTX_H
 
-#if defined(TARGET_STM32F051R8)
-
 #ifndef INITIAL_SP
-#define INITIAL_SP              (0x20002000UL)
-#endif
-
-#elif defined(TARGET_STM32L031K6)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20002000UL)
-#endif
 
-#elif defined(TARGET_STM32F070RB)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20004000UL)
-#endif
+#if (defined(TARGET_STM32F051R8) ||\
+     defined(TARGET_STM32F100RB) ||\
+     defined(TARGET_STM32L031K6) ||\
+     defined(TARGET_STM32L053C8) ||\
+     defined(TARGET_STM32L053R8))
+#define INITIAL_SP              (0x20002000UL)
 
-#elif defined(TARGET_STM32F072RB)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20004000UL)
-#endif
+#elif (defined(TARGET_STM32F303K8) ||\
+       defined(TARGET_STM32F334C8) ||\
+       defined(TARGET_STM32F334R8))
+#define INITIAL_SP              (0x20003000UL)
 
-#elif defined(TARGET_STM32F091RC)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20008000UL)
-#endif
-
-#elif defined(TARGET_STM32F100RB)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20002000UL)
-#endif
+#elif (defined(TARGET_STM32F070RB) ||\
+       defined(TARGET_STM32F072RB) ||\
+       defined(TARGET_STM32F302R8))
+#define INITIAL_SP              (0x20004000UL)
 
-#elif defined(TARGET_STM32F103RB)
-
-#ifndef INITIAL_SP
+#elif (defined(TARGET_STM32F103RB) ||\
+       defined(TARGET_STM32L072CZ) ||\
+       defined(TARGET_STM32L073RZ))
 #define INITIAL_SP              (0x20005000UL)
-#endif
 
-#elif defined(TARGET_STM32F207ZG)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
+#elif (defined(TARGET_STM32F091RC) ||\
+       defined(TARGET_STM32F410RB) ||\
+       defined(TARGET_STM32L151CC) ||\
+       defined(TARGET_STM32L151RC) ||\
+       defined(TARGET_STM32L152RC))
+#define INITIAL_SP              (0x20008000UL)
 
 #elif defined(TARGET_STM32F303VC)
-
-#ifndef INITIAL_SP
 #define INITIAL_SP              (0x2000A000UL)
-#endif
 
-#elif defined(TARGET_STM32F334C8)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20003000UL)
-#endif
+#elif defined(TARGET_STM32L432KC)
+#define INITIAL_SP              (0x2000C000UL)
 
-#elif defined(TARGET_STM32F302R8)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20004000UL)
-#endif
-
-#elif defined(TARGET_STM32F303K8)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20003000UL)
-#endif
+#elif (defined(TARGET_STM32F303RE) ||\
+       defined(TARGET_STM32F303ZE) ||\
+       defined(TARGET_STM32F401VC))
+#define INITIAL_SP              (0x20010000UL)
 
-#elif defined(TARGET_STM32F303RE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20010000UL)
-#endif
-
-#elif defined(TARGET_STM32F303ZE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20010000UL)
-#endif
+#elif defined(TARGET_STM32L152RE)
+#define INITIAL_SP              (0x20014000UL)
 
-#elif defined(TARGET_STM32F334R8)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20003000UL)
-#endif
-
-#elif defined(TARGET_STM32F446VE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
+#elif (defined(TARGET_STM32F401RE) ||\
+       defined(TARGET_STM32L475VG) ||\
+       defined(TARGET_STM32L476RG) ||\
+       defined(TARGET_STM32L476VG) ||\
+       defined(TARGET_STM32L486RG))
+#define INITIAL_SP              (0x20018000UL)
 
-#elif defined(TARGET_STM32F401VC)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20010000UL)
-#endif
-
-#elif (defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F439ZI))
+#elif (defined(TARGET_STM32F207ZG) ||\
+       defined(TARGET_STM32F405RG) ||\
+       defined(TARGET_STM32F407VG) ||\
+       defined(TARGET_STM32F411RE) ||\
+       defined(TARGET_STM32F446RE) ||\
+       defined(TARGET_STM32F446VE) ||\
+       defined(TARGET_STM32F446ZE))
+#define INITIAL_SP              (0x20020000UL)
 
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20030000UL)
-#endif
-
-#elif defined(TARGET_UBLOX_EVK_ODIN_W2)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20030000UL)
-#endif
-
-#elif defined(TARGET_UBLOX_C030)
-
-#ifndef INITIAL_SP
+#elif (defined(TARGET_STM32F429ZI) ||\
+       defined(TARGET_STM32F437VG) ||\
+       defined(TARGET_STM32F439ZI))
 #define INITIAL_SP              (0x20030000UL)
-#endif
 
-#elif defined(TARGET_STM32F469NI)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20050000UL)
-#endif
-
-#elif defined(TARGET_STM32F405RG)
+#elif defined(TARGET_STM32F412ZG)
+#define INITIAL_SP              (0x20040000UL)
 
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
-
-#elif defined(TARGET_STM32F401RE)
+#elif (defined(TARGET_STM32F413ZH) ||\
+       defined(TARGET_STM32F469NI) ||\
+       defined(TARGET_STM32F746NG) ||\
+       defined(TARGET_STM32F746ZG) ||\
+       defined(TARGET_STM32F756ZG))
+#define INITIAL_SP              (0x20050000UL)
 
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20018000UL)
-#endif
+#elif (defined(TARGET_STM32F767ZI) ||\
+       defined(TARGET_STM32F769NI))
+#define INITIAL_SP              (0x20080000UL)
 
-#elif defined(TARGET_STM32F410RB)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20008000UL)
+#else
+#error "INITIAL_SP is not defined for this target in the mbed_rtx.h file"
 #endif
 
-#elif defined(TARGET_MTS_MDOT_F411RE) || defined (TARGET_MTS_DRAGONFLY_F411RE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
-
-#elif defined(TARGET_STM32F411RE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
-
-#elif defined(TARGET_STM32F412ZG)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20040000UL)
-#endif
-
-#elif defined(TARGET_STM32F413ZH)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20050000UL)
-#endif
-#ifndef OS_TASKCNT
-#define OS_TASKCNT              14
-#endif
-#ifndef OS_MAINSTKSIZE
-#define OS_MAINSTKSIZE          256
-#endif
-#ifndef OS_CLOCK
-#define OS_CLOCK                100000000
-#endif
-
-
-#elif defined(TARGET_STM32F446RE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
-
-#elif defined(TARGET_STM32F446ZE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
-
-#elif defined(TARGET_STM32F407VG)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20020000UL)
-#endif
-
-#elif defined(TARGET_STM32F746NG)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20050000UL)
-#endif
-
-#elif (defined(TARGET_STM32F746ZG) || defined(TARGET_STM32F756ZG))
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20050000UL)
-#endif
-
-#elif defined(TARGET_STM32F767ZI)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20080000UL)
-#endif
-
-#elif defined(TARGET_STM32F769NI)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20080000UL)
-#endif
-
-#elif defined(TARGET_STM32L053C8)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20002000UL)
-#endif
-
-#elif defined(TARGET_STM32L031K6)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20002000UL)
-#endif
-
-#elif defined(TARGET_STM32L053R8)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20002000UL)
-#endif
-
-#elif defined(TARGET_STM32L072CZ)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20005000UL)
-#endif
-
-#elif defined(TARGET_STM32L073RZ)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20005000UL)
-#endif
-
-#elif defined(TARGET_STM32L152RC)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20008000UL)
-#endif
-
-#elif defined(TARGET_STM32L152RE)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20014000UL)
-#endif
-
-#elif defined(TARGET_NZ32_SC151)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20008000UL)
-#endif
-
-#elif defined(TARGET_XDOT_L151CC)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20008000UL)
-#endif
-
-#elif defined(TARGET_STM32L476VG) || defined(TARGET_STM32L475VG)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20018000UL)
-#endif
-
-#elif defined(TARGET_STM32L432KC)
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x2000C000UL)
-#endif
-
-#elif (defined(TARGET_STM32L476RG) || defined(TARGET_STM32L486RG))
-
-#ifndef INITIAL_SP
-#define INITIAL_SP              (0x20018000UL)
-#endif
-
-#endif
+#endif // INITIAL_SP
 
 #endif  // MBED_MBED_RTX_H

--- a/targets/TARGET_STM/stm_spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_STM/stm_spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -387,12 +387,13 @@
     }
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length)
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill)
 {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -391,11 +391,12 @@
     return spi_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -115,16 +115,19 @@
     {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+    {PA_6 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+    {PC_3 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
     {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+    {PC_11, PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {NC   , NC   , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}
 };
 

--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c	Thu Aug 03 13:13:39 2017 +0100
@@ -117,16 +117,19 @@
     {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+    {PA_6 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
     {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+    {PC_3 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
     {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+    {PC_11, PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
     {NC   , NC   , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}
 };
 

--- a/targets/TARGET_WIZNET/TARGET_W7500x/rtc_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-#include "cmsis.h"
-#include "W7500x_pwm.h"
-
-time_t wiz_rtc_time;
-char rtc_enabled = 0;
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-void PWM3_Handler(void)
-{
-
-    wiz_rtc_time++;
-    PWM_CH3_ClearOverflowInt();
-
-}
-#ifdef __cplusplus
-}
-#endif
-
-
-
-void rtc_init(void) {
-    PWM_TimerModeInitTypeDef TimerModeStructure;
-    *(volatile uint32_t *)(0x410010e0) = 0x03;
-
-    /* Timer mode configuration */    
-    TimerModeStructure.PWM_CHn_PR = 7;
-    TimerModeStructure.PWM_CHn_MR = 1;
-    TimerModeStructure.PWM_CHn_LR = 0xF4240;
-    TimerModeStructure.PWM_CHn_UDMR = PWM_CHn_UDMR_UpCount;
-    TimerModeStructure.PWM_CHn_PDMR = PWM_CHn_PDMR_Periodic;
-    
-    PWM_TimerModeInit(PWM_CH3, &TimerModeStructure); 
-    
-    /* PWM interrupt configuration */
-    PWM_IntConfig(PWM_CH3, ENABLE);
-    PWM_CHn_IntConfig(PWM_CH3, PWM_CHn_IER_OIE, ENABLE);
-    
-    /* PWM channel 0 start */
-    PWM_CHn_Start(PWM_CH3);
-    NVIC_SetVector(PWM3_IRQn, (uint32_t)PWM3_Handler);
-    NVIC_EnableIRQ(PWM3_IRQn);		
-    rtc_enabled = 1;
-}
-
-void rtc_free(void) {
-    // [TODO]
-}
-
-
-int rtc_isenabled(void) {
-	return rtc_enabled;
-}
-
-
-time_t rtc_read(void) {
-    return wiz_rtc_time;
-}
-
-void rtc_write(time_t t) {
-    //*(volatile uint32_t *)(0x41001008) = 0x42; // timer disable, interrupt disable
-    wiz_rtc_time = t; 
-    //*(volatile uint32_t *)(0x41001008) = 0x72; // timer enable interrupt enable  
-}

--- a/targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c	Thu Aug 03 13:13:39 2017 +0100
@@ -183,11 +183,12 @@
     return ssp_read(obj);
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
     for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : 0xff;
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
         char in = spi_master_write(obj, out);
         if (i < rx_length) {
             rx_buffer[i] = in;

--- a/targets/TARGET_ublox/TARGET_HI2110/device/hi2110.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_ublox/TARGET_HI2110/device/hi2110.h	Thu Aug 03 13:13:39 2017 +0100
@@ -21,6 +21,8 @@
  extern "C" {
 #endif
 
+#include "system_hi2110.h"
+
 /******************************************************************************/
 /*                Processor and Core Peripherals                              */
 /******************************************************************************/

--- a/targets/TARGET_ublox/TARGET_HI2110/device/system_hi2110.h	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/TARGET_ublox/TARGET_HI2110/device/system_hi2110.h	Thu Aug 03 13:13:39 2017 +0100
@@ -22,6 +22,7 @@
 #endif
 
 #include <stdint.h>
+#include <stdbool.h>
 
 
 extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */

--- a/targets/targets.json	Wed Jul 19 17:31:21 2017 +0100
+++ b/targets/targets.json	Thu Aug 03 13:13:39 2017 +0100
@@ -264,12 +264,12 @@
             "modem_is_on_board": {
                 "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
                 "value": 1,
-                "macro_name": "MODEM_ON_BOARD" 
+                "macro_name": "MODEM_ON_BOARD"
             },
             "modem_data_connection_type": {
                 "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
                 "value": 1,
-                "macro_name": "MODEM_ON_BOARD_UART" 
+                "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
         "macros": ["TARGET_LPC1768"],
@@ -676,11 +676,44 @@
         "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
     },
+    "LPC54114": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54114_M4", "LPCXpresso"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["1054"],
+        "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name" : "LPC54114J256BD64"
+    },
+    "LPC54608": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54608", "LPCXpresso"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_LPC54608J512ET180", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "detect_code": ["1056"],
+        "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name" : "LPC54608J512ET180"
+    },
     "NUCLEO_F030R8": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0",
         "extra_labels_add": ["STM32F0", "STM32F030R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0725"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["SERIAL_FC"],
@@ -694,6 +727,13 @@
         "core": "Cortex-M0",
         "default_toolchain": "uARM",
         "extra_labels_add": ["STM32F0", "STM32F031K6"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0791"],
         "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["SERIAL_FC"],
@@ -707,6 +747,13 @@
         "core": "Cortex-M0",
         "default_toolchain": "uARM",
         "extra_labels_add": ["STM32F0", "STM32F042K6"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0785"],
         "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["CAN", "SERIAL_FC"],
@@ -719,6 +766,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0",
         "extra_labels_add": ["STM32F0", "STM32F070RB"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0755"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
@@ -730,6 +784,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0",
         "extra_labels_add": ["STM32F0", "STM32F072RB"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0730"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
@@ -741,6 +802,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0",
         "extra_labels_add": ["STM32F0", "STM32F091RC"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0750"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
@@ -752,6 +820,18 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M3",
         "extra_labels_add": ["STM32F1", "STM32F103RB"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "clock_source_usb": {
+                "help": "In case of HSI clock source, to get 48 Mhz USB, SYSCLK has to be reduced from 64 to 48 MHz (set 0 for the max SYSCLK value)",
+                "value": "0",
+                "macro_name": "CLOCK_SOURCE_USB"
+            }
+        },
         "detect_code": ["0700"],
         "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH"],
         "release_versions": ["2", "5"],
@@ -767,6 +847,11 @@
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
                 "value": "PA_7",
                 "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
             }
         },
         "detect_code": ["0835"],
@@ -781,6 +866,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F302x8", "STM32F302R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0705"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
         "default_lib": "small",
@@ -793,6 +885,13 @@
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"],
         "macros_add": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0775"],
         "default_lib": "small",
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
@@ -804,6 +903,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303RE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0745"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
         "release_versions": ["2", "5"],
@@ -814,6 +920,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303ZE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0747"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER"],
         "release_versions": ["2", "5"],
@@ -824,6 +937,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F334x8", "STM32F334R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0735"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
         "default_lib": "small",
@@ -1052,6 +1172,11 @@
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
                 "value": "PA_7",
                 "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
             }
         },
         "macros_add": ["USBHOST_OTHER"],
@@ -1071,8 +1196,14 @@
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
                 "value": "PA_7",
                 "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
             }
         },
+        "macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0819"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
@@ -1089,6 +1220,11 @@
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
                 "value": "PA_7",
                 "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
+            },
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
             }
         },
         "supported_form_factors": ["ARDUINO"],
@@ -1106,6 +1242,13 @@
         "supported_toolchains": ["uARM"],
         "default_toolchain": "uARM",
         "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0780"],
         "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
         "default_lib": "small",
@@ -1118,6 +1261,13 @@
         "extra_labels_add": ["STM32L0", "STM32L031K6"],
         "default_toolchain": "uARM",
         "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0790"],
         "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
         "default_lib": "small",
@@ -1129,6 +1279,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0+",
         "extra_labels_add": ["STM32L0", "STM32L053R8"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0715"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "default_lib": "small",
@@ -1140,6 +1297,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M0+",
         "extra_labels_add": ["STM32L0", "STM32L073RZ", "STM32L073xx"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0760"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
@@ -1150,6 +1314,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M3",
         "extra_labels_add": ["STM32L1", "STM32L152RE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0710"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
         "release_versions": ["2", "5"],
@@ -1160,6 +1331,13 @@
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32L4", "STM32L432xC", "STM32L432KC"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0770"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "CAN", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
@@ -1172,7 +1350,7 @@
         "extra_labels_add": ["STM32L4", "STM32L476RG", "STM32L476xG"],
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI (L4)",
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
                 "value": "USE_PLL_MSI",
                 "macro_name": "CLOCK_SOURCE"
             }
@@ -1189,6 +1367,13 @@
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0827"],
         "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
@@ -1211,6 +1396,13 @@
         "core": "Cortex-M0",
         "extra_labels_add": ["STM32F0", "STM32F051", "STM32F051R8"],
         "supported_toolchains": ["GCC_ARM"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has_add": ["SERIAL_FC"],
         "device_name": "STM32F051R8"
@@ -1237,6 +1429,13 @@
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F334x8","STM32F334C8"],
         "macros_add": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0810"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
         "default_lib": "small",
@@ -1295,6 +1494,13 @@
         "core": "Cortex-M0+",
         "extra_labels_add": ["STM32L0", "STM32L053C8"],
         "macros": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -1306,6 +1512,13 @@
         "extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xx"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "macros": ["RTC_LSI=1"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0833"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG"],
         "release_versions": ["2", "5"],
@@ -1316,6 +1529,13 @@
         "core": "Cortex-M7F",
         "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746NG"],
         "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0815"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
         "features": ["LWIP"],
@@ -1327,6 +1547,13 @@
         "core": "Cortex-M7FD",
         "extra_labels_add": ["STM32F7", "STM32F769", "STM32F769xI", "STM32F769NI"],
         "supported_form_factors": ["ARDUINO"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0817"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG"],
         "features": ["LWIP"],
@@ -1337,6 +1564,13 @@
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0764"],
         "macros_add": ["USBHOST_OTHER"],
@@ -1348,6 +1582,13 @@
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "detect_code": ["0820"],
         "macros_add": ["USBHOST_OTHER"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
@@ -1385,12 +1626,12 @@
             "modem_is_on_board": {
                 "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
                 "value": 1,
-                "macro_name": "MODEM_ON_BOARD" 
+                "macro_name": "MODEM_ON_BOARD"
             },
             "modem_data_connection_type": {
                 "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
                 "value": 1,
-                "macro_name": "MODEM_ON_BOARD_UART" 
+                "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
         "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000", "RTC_LSI=1"],
@@ -1408,9 +1649,10 @@
         "default_toolchain": "ARM",
         "extra_labels_add": ["STM32L1", "STM32L151CC"],
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "device_has_add": ["ANALOGOUT"],
+        "device_has_add": ["ANALOGOUT", "FLASH"],
         "release_versions": ["5"],
-        "device_name": "STM32L151CC"
+        "device_name": "STM32L151CC",
+        "bootloader_supported": true
     },
     "MOTE_L152RC": {
         "inherits": ["FAMILY_STM32"],
@@ -1456,12 +1698,12 @@
             "modem_is_on_board": {
                 "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
                 "value": 1,
-                "macro_name": "MODEM_ON_BOARD" 
+                "macro_name": "MODEM_ON_BOARD"
             },
             "modem_data_connection_type": {
                 "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
                 "value": 1,
-                "macro_name": "MODEM_ON_BOARD_UART" 
+                "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
         "macros_add": ["RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
@@ -1975,7 +2217,9 @@
         "extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
         "macros": ["CMSDK_CM3DS"],
         "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC"],
-        "release_versions": ["2", "5"]
+        "release_versions": ["2", "5"],
+        "copy_method": "mps2",
+        "reset_method": "reboot.txt"
     },
     "ARM_BEETLE_SOC": {
         "inherits": ["ARM_IOTSS_Target"],
@@ -2601,7 +2845,7 @@
         "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
     "WIZWIKI_W7500P": {
@@ -2611,7 +2855,7 @@
         "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
     "WIZWIKI_W7500ECO": {
@@ -2620,7 +2864,7 @@
         "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
         "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
     "SAMR21G18A": {
@@ -3003,5 +3247,13 @@
         "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2"],
         "device_name": "nRF51822_xxAC"
+    },
+    "VBLUNO52": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "macros_add": ["BOARD_PCA10040", "BOARD_VBLUNO52", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2"],
+        "device_name": "nRF52832_xxAA"
     }
 }