Diego Ostuni
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ST25R3911
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st25r3911_com.h
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00001 00002 /****************************************************************************** 00003 * @attention 00004 * 00005 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00006 * 00007 * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); 00008 * You may not use this file except in compliance with the License. 00009 * You may obtain a copy of the License at: 00010 * 00011 * http://www.st.com/myliberty 00012 * 00013 * Unless required by applicable law or agreed to in writing, software 00014 * distributed under the License is distributed on an "AS IS" BASIS, 00015 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, 00016 * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, 00017 * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. 00018 * See the License for the specific language governing permissions and 00019 * limitations under the License. 00020 * 00021 ******************************************************************************/ 00022 00023 00024 /* 00025 * PROJECT: ST25R3911 firmware 00026 * $Revision: $ 00027 * LANGUAGE: ISO C99 00028 */ 00029 00030 /*! \file 00031 * 00032 * \author Ulrich Herrmann 00033 * 00034 * \brief ST25R3911 communication declaration file 00035 * 00036 */ 00037 /*! 00038 * This driver provides basic abstraction for communication with the ST25R3911. 00039 * It uses the SPI driver for interfacing with the ST25R3911. 00040 * 00041 * API: 00042 * - Read Register: #st25r3911ReadRegister 00043 * - Modify Register: #st25r3911ModifyRegister 00044 * - Write Register: #mST25 -> writeRegister 00045 * - Write Multiple Registers: #mST25 -> writeMultipleRegisters 00046 * - Load ST25R3911 FIFO with data: #mST25 -> writeFifo 00047 * - Read from ST25R3911 FIFO: #mST25 -> readFifo 00048 * - Execute direct command: #mST25 -> executeCommand 00049 * 00050 * 00051 * @addtogroup RFAL 00052 * @{ 00053 * 00054 * @addtogroup RFAL-HAL 00055 * @brief RFAL Hardware Abstraction Layer 00056 * @{ 00057 * 00058 * @addtogroup ST25R3911 00059 * @brief RFAL ST25R3911 Driver 00060 * @{ 00061 * 00062 * @addtogroup ST25R3911_Com 00063 * @brief RFAL ST25R3911 Communication 00064 * @{ 00065 * 00066 */ 00067 00068 #ifndef ST25R3911_COM_H 00069 #define ST25R3911_COM_H 00070 00071 /* 00072 ****************************************************************************** 00073 * INCLUDES 00074 ****************************************************************************** 00075 */ 00076 #include <stdint.h> 00077 #include <stdbool.h> 00078 #include "st_errno.h" 00079 #include "platform1.h" 00080 #include "ST25R3911.h" 00081 #include "utils.h" 00082 00083 00084 00085 /* 00086 ****************************************************************************** 00087 * GLOBAL DEFINES 00088 ****************************************************************************** 00089 */ 00090 00091 #define ST25R3911_FIFO_STATUS_LEN 2 /*!< Number of FIFO Status Register */ 00092 00093 00094 00095 00096 #define ST25R3911_REG_IO_CONF1 0x00 /*!< RW IO Configuration Register 1 */ 00097 #define ST25R3911_REG_IO_CONF2 0x01 /*!< RW IO Configuration Register 2 */ 00098 00099 #define ST25R3911_REG_OP_CONTROL 0x02 /*!< RW Operation Control Register */ 00100 #define ST25R3911_REG_MODE 0x03 /*!< RW Mode Definition Register */ 00101 #define ST25R3911_REG_BIT_RATE 0x04 /*!< RW Bit Rate Definition Register */ 00102 00103 #define ST25R3911_REG_ISO14443A_NFC 0x05 /*!< RW ISO14443A and NFC 106 kBit/s Settings Register */ 00104 #define ST25R3911_REG_ISO14443B_1 0x06 /*!< RW ISO14443B Settings Register 1 */ 00105 #define ST25R3911_REG_ISO14443B_2 0x07 /*!< RW ISO14443B Settings Register 2 */ 00106 #define ST25R3911_REG_STREAM_MODE 0x08 /*!< RW Stream Mode Definition Register */ 00107 #define ST25R3911_REG_AUX 0x09 /*!< RW Auxiliary Definition Register */ 00108 #define ST25R3911_REG_RX_CONF1 0x0A /*!< RW Receiver Configuration Register 1 */ 00109 #define ST25R3911_REG_RX_CONF2 0x0B /*!< RW Receiver Configuration Register 2 */ 00110 #define ST25R3911_REG_RX_CONF3 0x0C /*!< RW Receiver Configuration Register 3 */ 00111 #define ST25R3911_REG_RX_CONF4 0x0D /*!< RW Receiver Configuration Register 4 */ 00112 00113 #define ST25R3911_REG_MASK_RX_TIMER 0x0E /*!< RW Mask Receive Timer Register */ 00114 #define ST25R3911_REG_NO_RESPONSE_TIMER1 0x0F /*!< RW No-response Timer Register 1 */ 00115 #define ST25R3911_REG_NO_RESPONSE_TIMER2 0x10 /*!< RW No-response Timer Register 2 */ 00116 #define ST25R3911_REG_GPT_CONTROL 0x11 /*!< RW General Purpose Timer Control Register */ 00117 #define ST25R3911_REG_GPT1 0x12 /*!< RW General Purpose Timer Register 1 */ 00118 #define ST25R3911_REG_GPT2 0x13 /*!< RW General Purpose Timer Register 2 */ 00119 00120 #define ST25R3911_REG_IRQ_MASK_MAIN 0x14 /*!< RW Mask Main Interrupt Register */ 00121 #define ST25R3911_REG_IRQ_MASK_TIMER_NFC 0x15 /*!< RW Mask Timer and NFC Interrupt Register */ 00122 #define ST25R3911_REG_IRQ_MASK_ERROR_WUP 0x16 /*!< RW Mask Error and Wake-up Interrupt Register */ 00123 #define ST25R3911_REG_IRQ_MAIN 0x17 /*!< R Main Interrupt Register */ 00124 #define ST25R3911_REG_IRQ_TIMER_NFC 0x18 /*!< R Timer and NFC Interrupt Register */ 00125 #define ST25R3911_REG_IRQ_ERROR_WUP 0x19 /*!< R Error and Wake-up Interrupt Register */ 00126 #define ST25R3911_REG_FIFO_RX_STATUS1 0x1A /*!< R FIFO RX Status Register 1 */ 00127 #define ST25R3911_REG_FIFO_RX_STATUS2 0x1B /*!< R FIFO RX Status Register 2 */ 00128 #define ST25R3911_REG_COLLISION_STATUS 0x1C /*!< R Collision Display Register */ 00129 00130 #define ST25R3911_REG_NUM_TX_BYTES1 0x1D /*!< RW Number of Transmitted Bytes Register 1 */ 00131 #define ST25R3911_REG_NUM_TX_BYTES2 0x1E /*!< RW Number of Transmitted Bytes Register 2 */ 00132 00133 #define ST25R3911_REG_NFCIP1_BIT_RATE 0x1F /*!< R NFCIP Bit Rate Detection Display Register */ 00134 00135 #define ST25R3911_REG_AD_RESULT 0x20 /*!< R A/D Converter Output Register */ 00136 00137 #define ST25R3911_REG_ANT_CAL_CONTROL 0x21 /*!< RW Antenna Calibration Control Register */ 00138 #define ST25R3911_REG_ANT_CAL_TARGET 0x22 /*!< RW Antenna Calibration Target Register */ 00139 #define ST25R3911_REG_ANT_CAL_RESULT 0x23 /*!< R Antenna Calibration Display Register */ 00140 00141 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL 0x24 /*!< RW AM Modulation Depth Control Register */ 00142 #define ST25R3911_REG_AM_MOD_DEPTH_RESULT 0x25 /*!< R AM Modulation Depth Display Register */ 00143 #define ST25R3911_REG_RFO_AM_ON_LEVEL 0x26 /*!< RW RFO AM Modulation (On) Level Definition Register */ 00144 #define ST25R3911_REG_RFO_AM_OFF_LEVEL 0x27 /*!< RW RFO Normal (AM Off) Level Definition Register */ 00145 00146 #define ST25R3911_REG_FIELD_THRESHOLD 0x29 /*!< RW External Field Detector Threshold Register */ 00147 00148 #define ST25R3911_REG_REGULATOR_CONTROL 0x2A /*!< RW Regulated Voltage Control Register */ 00149 #define ST25R3911_REG_REGULATOR_RESULT 0x2B /*!< R Regulator Display Register */ 00150 00151 #define ST25R3911_REG_RSSI_RESULT 0x2C /*!< R RSSI Display Register*/ 00152 #define ST25R3911_REG_GAIN_RED_STATE 0x2D /*!< R Gain Reduction State Register*/ 00153 00154 #define ST25R3911_REG_CAP_SENSOR_CONTROL 0x2E /*!< RW Capacitive Sensor Control Register */ 00155 #define ST25R3911_REG_CAP_SENSOR_RESULT 0x2F /*!< R Capacitive Sensor Display Register */ 00156 00157 #define ST25R3911_REG_AUX_DISPLAY 0x30 /*!< R Auxiliary Display Register */ 00158 00159 #define ST25R3911_REG_WUP_TIMER_CONTROL 0x31 /*!< RW Wake-up Timer Control Register */ 00160 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF 0x32 /*!< RW Amplitude Measurement Configuration Register */ 00161 #define ST25R3911_REG_AMPLITUDE_MEASURE_REF 0x33 /*!< RW Amplitude Measurement Reference Register */ 00162 #define ST25R3911_REG_AMPLITUDE_MEASURE_AA_RESULT 0x34 /*!< R Amplitude Measurement Auto Averaging Display Register */ 00163 #define ST25R3911_REG_AMPLITUDE_MEASURE_RESULT 0x35 /*!< R Amplitude Measurement Display Register */ 00164 #define ST25R3911_REG_PHASE_MEASURE_CONF 0x36 /*!< RW Phase Measurement Configuration Register */ 00165 #define ST25R3911_REG_PHASE_MEASURE_REF 0x37 /*!< RW Phase Measurement Reference Register */ 00166 #define ST25R3911_REG_PHASE_MEASURE_AA_RESULT 0x38 /*!< R Phase Measurement Auto Averaging Display Register */ 00167 #define ST25R3911_REG_PHASE_MEASURE_RESULT 0x39 /*!< R Phase Measurement Display Register */ 00168 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF 0x3A /*!< RW Capacitance Measurement Configuration Register */ 00169 #define ST25R3911_REG_CAPACITANCE_MEASURE_REF 0x3B /*!< RW Capacitance Measurement Reference Register */ 00170 #define ST25R3911_REG_CAPACITANCE_MEASURE_AA_RESULT 0x3C /*!< R Capacitance Measurement Auto Averaging Display Register */ 00171 #define ST25R3911_REG_CAPACITANCE_MEASURE_RESULT 0x3D /*!< R Capacitance Measurement Display Register */ 00172 #define ST25R3911_REG_IC_IDENTITY 0x3F /*!< R Chip Id: 0 for old silicon, v2 silicon: 0x09 */ 00173 00174 00175 /*! Register bit definitions \cond DOXYGEN_SUPRESS */ 00176 00177 #define ST25R3911_REG_IO_CONF1_lf_clk_off (1<<0) 00178 #define ST25R3911_REG_IO_CONF1_out_cl0 (1<<1) 00179 #define ST25R3911_REG_IO_CONF1_out_cl1 (1<<2) 00180 #define ST25R3911_REG_IO_CONF1_osc (1<<3) 00181 #define ST25R3911_REG_IO_CONF1_fifo_lt (1<<4) 00182 #define ST25R3911_REG_IO_CONF1_fifo_lt_32bytes (0<<4) 00183 #define ST25R3911_REG_IO_CONF1_fifo_lt_16bytes (1<<4) 00184 #define ST25R3911_REG_IO_CONF1_fifo_lr (1<<5) 00185 #define ST25R3911_REG_IO_CONF1_fifo_lr_64bytes (0<<5) 00186 #define ST25R3911_REG_IO_CONF1_fifo_lr_80bytes (1<<5) 00187 #define ST25R3911_REG_IO_CONF1_rfo2 (1<<6) 00188 #define ST25R3911_REG_IO_CONF1_single (1<<7) 00189 #define ST25R3911_REG_IO_CONF2_slow_up (1<<0) 00190 #define ST25R3911_REG_IO_CONF2_io_18 (1<<2) 00191 #define ST25R3911_REG_IO_CONF2_miso_pd1 (1<<3) 00192 #define ST25R3911_REG_IO_CONF2_miso_pd2 (1<<4) 00193 #define ST25R3911_REG_IO_CONF2_vspd_off (1<<6) 00194 #define ST25R3911_REG_IO_CONF2_sup3V (1<<7) 00195 #define ST25R3911_REG_OP_CONTROL_wu (1<<2) 00196 #define ST25R3911_REG_OP_CONTROL_tx_en (1<<3) 00197 #define ST25R3911_REG_OP_CONTROL_rx_man (1<<4) 00198 #define ST25R3911_REG_OP_CONTROL_rx_chn (1<<5) 00199 #define ST25R3911_REG_OP_CONTROL_rx_en (1<<6) 00200 #define ST25R3911_REG_OP_CONTROL_en (1<<7) 00201 #define ST25R3911_REG_MODE_nfc_ar (1<<0) 00202 #define ST25R3911_REG_MODE_nfc_ar_on (1<<0) 00203 #define ST25R3911_REG_MODE_nfc_ar_off (0<<0) 00204 #define ST25R3911_REG_MODE_mask_om (0xf<<3) 00205 #define ST25R3911_REG_MODE_om_nfc (0x0<<3) 00206 #define ST25R3911_REG_MODE_om_iso14443a (0x1<<3) 00207 #define ST25R3911_REG_MODE_om_iso14443b (0x2<<3) 00208 #define ST25R3911_REG_MODE_om_felica (0x3<<3) 00209 #define ST25R3911_REG_MODE_om_topaz (0x4<<3) 00210 #define ST25R3911_REG_MODE_om_subcarrier_stream (0xe<<3) 00211 #define ST25R3911_REG_MODE_om_bpsk_stream (0xf<<3) 00212 #define ST25R3911_REG_MODE_om_bit_rate_detection (0x0<<3) 00213 #define ST25R3911_REG_MODE_om_nfcip1_normal_mode (0x1<<3) 00214 #define ST25R3911_REG_MODE_targ (1<<7) 00215 #define ST25R3911_REG_MODE_targ_targ (1<<7) 00216 #define ST25R3911_REG_MODE_targ_init (0<<7) 00217 #define ST25R3911_REG_BIT_RATE_mask_txrate (0xf<<4) 00218 #define ST25R3911_REG_BIT_RATE_shift_txrate (4) 00219 #define ST25R3911_REG_BIT_RATE_txrate_106 (0x0<<4) 00220 #define ST25R3911_REG_BIT_RATE_txrate_212 (0x1<<4) 00221 #define ST25R3911_REG_BIT_RATE_txrate_424 (0x2<<4) 00222 #define ST25R3911_REG_BIT_RATE_txrate_848 (0x3<<4) 00223 #define ST25R3911_REG_BIT_RATE_txrate_1695 (0x4<<4) 00224 #define ST25R3911_REG_BIT_RATE_txrate_3390 (0x5<<4) 00225 #define ST25R3911_REG_BIT_RATE_txrate_6780 (0x6<<4) 00226 #define ST25R3911_REG_BIT_RATE_mask_rxrate (0xf<<0) 00227 #define ST25R3911_REG_BIT_RATE_shift_rxrate (0) 00228 #define ST25R3911_REG_BIT_RATE_rxrate_106 (0x0<<0) 00229 #define ST25R3911_REG_BIT_RATE_rxrate_212 (0x1<<0) 00230 #define ST25R3911_REG_BIT_RATE_rxrate_424 (0x2<<0) 00231 #define ST25R3911_REG_BIT_RATE_rxrate_848 (0x3<<0) 00232 #define ST25R3911_REG_BIT_RATE_rxrate_1695 (0x4<<0) 00233 #define ST25R3911_REG_BIT_RATE_rxrate_3390 (0x5<<0) 00234 #define ST25R3911_REG_BIT_RATE_rxrate_6780 (0x6<<0) 00235 #define ST25R3911_REG_ISO14443A_NFC_antcl (1<<0) 00236 #define ST25R3911_REG_ISO14443A_NFC_mask_p_len (0xf<<1) 00237 #define ST25R3911_REG_ISO14443A_NFC_shift_p_len (1) 00238 #define ST25R3911_REG_ISO14443A_NFC_nfc_f0 (1<<5) 00239 #define ST25R3911_REG_ISO14443A_NFC_nfc_f0_off (0<<5) 00240 #define ST25R3911_REG_ISO14443A_NFC_no_rx_par (1<<6) 00241 #define ST25R3911_REG_ISO14443A_NFC_no_rx_par_off (0<<6) 00242 #define ST25R3911_REG_ISO14443A_NFC_no_tx_par (1<<7) 00243 #define ST25R3911_REG_ISO14443A_NFC_no_tx_par_off (0<<7) 00244 #define ST25R3911_REG_ISO14443B_1_mask_eof (1<<2) 00245 #define ST25R3911_REG_ISO14443B_1_eof_10etu (0<<2) 00246 #define ST25R3911_REG_ISO14443B_1_eof_11etu (1<<2) 00247 #define ST25R3911_REG_ISO14443B_1_mask_sof (3<<3) 00248 #define ST25R3911_REG_ISO14443B_1_mask_sof_0 (1<<4) 00249 #define ST25R3911_REG_ISO14443B_1_sof_0_10etu (0<<4) 00250 #define ST25R3911_REG_ISO14443B_1_sof_0_11etu (1<<4) 00251 #define ST25R3911_REG_ISO14443B_1_mask_sof_1 (1<<3) 00252 #define ST25R3911_REG_ISO14443B_1_sof_1_2etu (0<<3) 00253 #define ST25R3911_REG_ISO14443B_1_sof_2_3etu (1<<3) 00254 #define ST25R3911_REG_ISO14443B_1_mask_egt (7<<5) 00255 #define ST25R3911_REG_ISO14443B_1_shift_egt (5) 00256 #define ST25R3911_REG_ISO14443B_2_eof_12 (1<<3) 00257 #define ST25R3911_REG_ISO14443B_2_eof_12_10to11etu (0<<3) 00258 #define ST25R3911_REG_ISO14443B_2_eof_12_10to12etu (1<<3) 00259 #define ST25R3911_REG_ISO14443B_2_no_eof (1<<4) 00260 #define ST25R3911_REG_ISO14443B_2_no_sof (1<<5) 00261 #define ST25R3911_REG_ISO14443B_2_mask_tr1 (3<<6) 00262 #define ST25R3911_REG_ISO14443B_2_shift_tr1 (6) 00263 #define ST25R3911_REG_ISO14443B_2_tr1_0 (1<<6) 00264 #define ST25R3911_REG_ISO14443B_2_tr1_1 (1<<7) 00265 #define ST25R3911_REG_ISO14443B_2_tr1_80fs80fs (0<<6) 00266 #define ST25R3911_REG_ISO14443B_2_tr1_64fs32fs (1<<6) 00267 #define ST25R3911_REG_STREAM_MODE_mask_stx (7<<0) 00268 #define ST25R3911_REG_STREAM_MODE_shift_stx (0) 00269 #define ST25R3911_REG_STREAM_MODE_stx_106 (0<<0) 00270 #define ST25R3911_REG_STREAM_MODE_stx_212 (1<<0) 00271 #define ST25R3911_REG_STREAM_MODE_stx_424 (2<<0) 00272 #define ST25R3911_REG_STREAM_MODE_stx_848 (3<<0) 00273 #define ST25R3911_REG_STREAM_MODE_stx_1695 (4<<0) 00274 #define ST25R3911_REG_STREAM_MODE_stx_3390 (5<<0) 00275 #define ST25R3911_REG_STREAM_MODE_stx_6780 (6<<0) 00276 #define ST25R3911_REG_STREAM_MODE_mask_scp (3<<3) 00277 #define ST25R3911_REG_STREAM_MODE_shift_scp (3) 00278 #define ST25R3911_REG_STREAM_MODE_scp_1pulse (0<<3) 00279 #define ST25R3911_REG_STREAM_MODE_scp_2pulses (1<<3) 00280 #define ST25R3911_REG_STREAM_MODE_scp_4pulses (2<<3) 00281 #define ST25R3911_REG_STREAM_MODE_scp_8pulses (3<<3) 00282 #define ST25R3911_REG_STREAM_MODE_mask_scf (3<<5) 00283 #define ST25R3911_REG_STREAM_MODE_shift_scf (5) 00284 #define ST25R3911_REG_STREAM_MODE_scf_bpsk848 (0<<5) 00285 #define ST25R3911_REG_STREAM_MODE_scf_bpsk1695 (1<<5) 00286 #define ST25R3911_REG_STREAM_MODE_scf_bpsk3390 (2<<5) 00287 #define ST25R3911_REG_STREAM_MODE_scf_bpsk106 (3<<5) 00288 #define ST25R3911_REG_STREAM_MODE_scf_sc212 (0<<5) 00289 #define ST25R3911_REG_STREAM_MODE_scf_sc424 (1<<5) 00290 #define ST25R3911_REG_STREAM_MODE_scf_sc848 (2<<5) 00291 #define ST25R3911_REG_STREAM_MODE_scf_sc1695 (3<<5) 00292 #define ST25R3911_REG_AUX_mask_nfc_n (3<<0) 00293 #define ST25R3911_REG_AUX_nfc_n0 (1<<0) 00294 #define ST25R3911_REG_AUX_nfc_n1 (1<<1) 00295 #define ST25R3911_REG_AUX_rx_tol (1<<2) 00296 #define ST25R3911_REG_AUX_ook_hr (1<<3) 00297 #define ST25R3911_REG_AUX_en_fd (1<<4) 00298 #define ST25R3911_REG_AUX_tr_am (1<<5) 00299 #define ST25R3911_REG_AUX_crc_2_fifo (1<<6) 00300 #define ST25R3911_REG_AUX_no_crc_rx (1<<7) 00301 #define ST25R3911_REG_RX_CONF1_z12k (1<<0) 00302 #define ST25R3911_REG_RX_CONF1_h80 (1<<1) 00303 #define ST25R3911_REG_RX_CONF1_h200 (1<<2) 00304 #define ST25R3911_REG_RX_CONF1_mask_lp (7<<3) 00305 #define ST25R3911_REG_RX_CONF1_lp_1200khz (0<<3) 00306 #define ST25R3911_REG_RX_CONF1_lp_600khz (1<<3) 00307 #define ST25R3911_REG_RX_CONF1_lp_300khz (2<<3) 00308 #define ST25R3911_REG_RX_CONF1_lp_2000khz (4<<3) 00309 #define ST25R3911_REG_RX_CONF1_lp_7000khz (5<<3) 00310 #define ST25R3911_REG_RX_CONF1_amd_sel (1<<6) 00311 #define ST25R3911_REG_RX_CONF1_ch_sel (1<<7) 00312 #define ST25R3911_REG_RX_CONF2_sqm_dyn (1<<1) 00313 #define ST25R3911_REG_RX_CONF2_agc_alg (1<<2) 00314 #define ST25R3911_REG_RX_CONF2_agc_m (1<<3) 00315 #define ST25R3911_REG_RX_CONF2_agc_en (1<<4) 00316 #define ST25R3911_REG_RX_CONF2_lf_en (1<<5) 00317 #define ST25R3911_REG_RX_CONF2_lf_op (1<<6) 00318 #define ST25R3911_REG_RX_CONF2_rx_lp (1<<7) 00319 #define ST25R3911_REG_RX_CONF3_rg_nfc (1<<0) 00320 #define ST25R3911_REG_RX_CONF3_lim (1<<1) 00321 #define ST25R3911_REG_RX_CONF3_shift_rg1_pm (2) 00322 #define ST25R3911_REG_RX_CONF3_mask_rg1_pm (0x7<<2) 00323 #define ST25R3911_REG_RX_CONF3_rg1_pm0 (1<<2) 00324 #define ST25R3911_REG_RX_CONF3_rg1_pm1 (1<<3) 00325 #define ST25R3911_REG_RX_CONF3_rg1_pm2 (1<<4) 00326 #define ST25R3911_REG_RX_CONF3_shift_rg1_am (5) 00327 #define ST25R3911_REG_RX_CONF3_mask_rg1_am (0x7<<5) 00328 #define ST25R3911_REG_RX_CONF3_rg1_am0 (1<<5) 00329 #define ST25R3911_REG_RX_CONF3_rg1_am1 (1<<6) 00330 #define ST25R3911_REG_RX_CONF3_rg1_am2 (1<<7) 00331 #define ST25R3911_REG_RX_CONF4_shift_rg2_pm (0) 00332 #define ST25R3911_REG_RX_CONF4_mask_rg2_pm (0xf<<0) 00333 #define ST25R3911_REG_RX_CONF4_rg2_pm0 (1<<0) 00334 #define ST25R3911_REG_RX_CONF4_rg2_pm1 (1<<1) 00335 #define ST25R3911_REG_RX_CONF4_rg2_pm2 (1<<2) 00336 #define ST25R3911_REG_RX_CONF4_rg2_pm3 (1<<3) 00337 #define ST25R3911_REG_RX_CONF4_shift_rg2_am (4) 00338 #define ST25R3911_REG_RX_CONF4_mask_rg2_am (0xf<<4) 00339 #define ST25R3911_REG_RX_CONF4_rg2_am0 (1<<4) 00340 #define ST25R3911_REG_RX_CONF4_rg2_am1 (1<<5) 00341 #define ST25R3911_REG_RX_CONF4_rg2_am2 (1<<6) 00342 #define ST25R3911_REG_RX_CONF4_rg2_am3 (1<<7) 00343 #define ST25R3911_REG_GPT_CONTROL_nrt_step (1<<0) 00344 #define ST25R3911_REG_GPT_CONTROL_nrt_emv (1<<1) 00345 #define ST25R3911_REG_GPT_CONTROL_gptc0 (1<<5) 00346 #define ST25R3911_REG_GPT_CONTROL_gptc1 (1<<6) 00347 #define ST25R3911_REG_GPT_CONTROL_gptc2 (1<<7) 00348 #define ST25R3911_REG_GPT_CONTROL_gptc_mask (0x7<<5) 00349 #define ST25R3911_REG_GPT_CONTROL_gptc_no_trigger (0x0<<5) 00350 #define ST25R3911_REG_GPT_CONTROL_gptc_erx (0x1<<5) 00351 #define ST25R3911_REG_GPT_CONTROL_gptc_srx (0x2<<5) 00352 #define ST25R3911_REG_GPT_CONTROL_gptc_etx_nfc (0x3<<5) 00353 #define ST25R3911_REG_FIFO_RX_STATUS2_np_lb (1<<0) 00354 #define ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb (7<<1) 00355 #define ST25R3911_REG_FIFO_RX_STATUS2_shift_fifo_lb (1) 00356 #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb0 (1<<1) 00357 #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb1 (1<<2) 00358 #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb2 (1<<3) 00359 #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_ncp (1<<4) 00360 #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_ovr (1<<5) 00361 #define ST25R3911_REG_FIFO_RX_STATUS2_fifo_unf (1<<6) 00362 #define ST25R3911_REG_COLLISION_STATUS_c_pb (1<<0) 00363 #define ST25R3911_REG_COLLISION_STATUS_mask_c_bit (3<<1) 00364 #define ST25R3911_REG_COLLISION_STATUS_shift_c_bit (1) 00365 #define ST25R3911_REG_COLLISION_STATUS_mask_c_byte (0xf<<4) 00366 #define ST25R3911_REG_COLLISION_STATUS_shift_c_byte (4) 00367 #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate0 (1<<4) 00368 #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate1 (1<<5) 00369 #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate2 (1<<6) 00370 #define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate3 (1<<7) 00371 #define ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_mask (0xf<<4) 00372 #define ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_shift (4) 00373 #define ST25R3911_REG_ANT_CAL_CONTROL_mask_tre (0xf<<3) 00374 #define ST25R3911_REG_ANT_CAL_CONTROL_shift_tre (3) 00375 #define ST25R3911_REG_ANT_CAL_CONTROL_tre_0 (1<<3) 00376 #define ST25R3911_REG_ANT_CAL_CONTROL_tre_1 (1<<4) 00377 #define ST25R3911_REG_ANT_CAL_CONTROL_tre_2 (1<<5) 00378 #define ST25R3911_REG_ANT_CAL_CONTROL_tre_3 (1<<6) 00379 #define ST25R3911_REG_ANT_CAL_CONTROL_trim_s (1<<7) 00380 #define ST25R3911_REG_ANT_CAL_RESULT_tri_err (1<<3) 00381 #define ST25R3911_REG_ANT_CAL_RESULT_tri_0 (1<<4) 00382 #define ST25R3911_REG_ANT_CAL_RESULT_tri_1 (1<<5) 00383 #define ST25R3911_REG_ANT_CAL_RESULT_tri_2 (1<<6) 00384 #define ST25R3911_REG_ANT_CAL_RESULT_tri_3 (1<<7) 00385 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mask_mod (0x3f<<1) 00386 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_shift_mod (1) 00387 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_8percent (0xb<<1) 00388 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_10percent (0xe<<1) 00389 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_14percent (0x14<<1) 00390 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_20percent (0x20<<1) 00391 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_25percent (0x2a<<1) 00392 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_30percent (0x37<<1) 00393 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_33percent (0x3f<<1) 00394 #define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_am_s (1<<7) 00395 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram0 (1<<0) 00396 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram1 (1<<1) 00397 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram2 (1<<2) 00398 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram3 (1<<3) 00399 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram4 (1<<4) 00400 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram5 (1<<5) 00401 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram6 (1<<6) 00402 #define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram7 (1<<7) 00403 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t0 (1<<0) 00404 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t1 (1<<1) 00405 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t2 (1<<2) 00406 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_t3 (1<<3) 00407 #define ST25R3911_REG_FIELD_THRESHOLD_trg_l0 (1<<4) 00408 #define ST25R3911_REG_FIELD_THRESHOLD_trg_l1 (1<<5) 00409 #define ST25R3911_REG_FIELD_THRESHOLD_trg_l2 (1<<6) 00410 #define ST25R3911_REG_FIELD_THRESHOLD_mask_trg (0x07<<4) 00411 #define ST25R3911_REG_FIELD_THRESHOLD_trg_75mV (0x00<<4) 00412 #define ST25R3911_REG_FIELD_THRESHOLD_trg_105mV (0x01<<4) 00413 #define ST25R3911_REG_FIELD_THRESHOLD_trg_150mV (0x02<<4) 00414 #define ST25R3911_REG_FIELD_THRESHOLD_trg_205mV (0x03<<4) 00415 #define ST25R3911_REG_FIELD_THRESHOLD_trg_290mV (0x04<<4) 00416 #define ST25R3911_REG_FIELD_THRESHOLD_trg_400mV (0x05<<4) 00417 #define ST25R3911_REG_FIELD_THRESHOLD_trg_560mV (0x06<<4) 00418 #define ST25R3911_REG_FIELD_THRESHOLD_trg_800mV (0x07<<4) 00419 #define ST25R3911_REG_FIELD_THRESHOLD_mask_rfe (0x0F<<0) 00420 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_75mV (0x00<<0) 00421 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_105mV (0x01<<0) 00422 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_150mV (0x02<<0) 00423 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_205mV (0x03<<0) 00424 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_290mV (0x04<<0) 00425 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_400mV (0x05<<0) 00426 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_560mV (0x06<<0) 00427 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_800mV (0x07<<0) 00428 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_25mV (0x08<<0) 00429 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_33mV (0x09<<0) 00430 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_47mV (0x0A<<0) 00431 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_64mV (0x0B<<0) 00432 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_90mV (0x0C<<0) 00433 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_125mV (0x0D<<0) 00434 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_175mV (0x0E<<0) 00435 #define ST25R3911_REG_FIELD_THRESHOLD_rfe_250mV (0x0F<<0) 00436 #define ST25R3911_REG_REGULATOR_CONTROL_shift_mpsv (1) 00437 #define ST25R3911_REG_REGULATOR_CONTROL_mask_mpsv (3<<1) 00438 #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vdd (0<<1) 00439 #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_a (1<<1) 00440 #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_d (2<<1) 00441 #define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_rf (3<<1) 00442 #define ST25R3911_REG_REGULATOR_CONTROL_mask_rege (0xf<<3) 00443 #define ST25R3911_REG_REGULATOR_CONTROL_shift_rege (3) 00444 #define ST25R3911_REG_REGULATOR_CONTROL_reg_s (1<<7) 00445 #define ST25R3911_REG_REGULATOR_RESULT_mrt_on (1<<0) 00446 #define ST25R3911_REG_REGULATOR_RESULT_nrt_on (1<<1) 00447 #define ST25R3911_REG_REGULATOR_RESULT_gpt_on (1<<2) 00448 #define ST25R3911_REG_REGULATOR_RESULT_mask_reg (0xf<<4) 00449 #define ST25R3911_REG_REGULATOR_RESULT_shift_reg (4) 00450 #define ST25R3911_REG_REGULATOR_RESULT_reg_0 (1<<4) 00451 #define ST25R3911_REG_REGULATOR_RESULT_reg_1 (1<<5) 00452 #define ST25R3911_REG_REGULATOR_RESULT_reg_2 (1<<6) 00453 #define ST25R3911_REG_REGULATOR_RESULT_reg_3 (1<<7) 00454 #define ST25R3911_REG_RSSI_RESULT_rssi_pm0 (1<<0) 00455 #define ST25R3911_REG_RSSI_RESULT_rssi_pm1 (1<<1) 00456 #define ST25R3911_REG_RSSI_RESULT_rssi_pm2 (1<<2) 00457 #define ST25R3911_REG_RSSI_RESULT_rssi_pm3 (1<<3) 00458 #define ST25R3911_REG_RSSI_RESULT_rssi_am_0 (1<<4) 00459 #define ST25R3911_REG_RSSI_RESULT_rssi_am_1 (1<<5) 00460 #define ST25R3911_REG_RSSI_RESULT_rssi_am_2 (1<<6) 00461 #define ST25R3911_REG_RSSI_RESULT_rssi_am_3 (1<<7) 00462 #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_0 (1<<0) 00463 #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_1 (1<<1) 00464 #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_2 (1<<2) 00465 #define ST25R3911_REG_GAIN_RED_STATE_gs_pm_3 (1<<3) 00466 #define ST25R3911_REG_GAIN_RED_STATE_gs_am_0 (1<<4) 00467 #define ST25R3911_REG_GAIN_RED_STATE_gs_am_1 (1<<5) 00468 #define ST25R3911_REG_GAIN_RED_STATE_gs_am_2 (1<<6) 00469 #define ST25R3911_REG_GAIN_RED_STATE_gs_am_3 (1<<7) 00470 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g0 (1<<0) 00471 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g1 (1<<1) 00472 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g2 (1<<2) 00473 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal0 (1<<3) 00474 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal1 (1<<4) 00475 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal2 (1<<5) 00476 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal3 (1<<6) 00477 #define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal4 (1<<7) 00478 #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_err (1<<1) 00479 #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_end (1<<2) 00480 #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal0 (1<<3) 00481 #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal1 (1<<4) 00482 #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal2 (1<<5) 00483 #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal3 (1<<6) 00484 #define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal4 (1<<7) 00485 #define ST25R3911_REG_AUX_DISPLAY_mrt_on (1<<0) 00486 #define ST25R3911_REG_AUX_DISPLAY_nrt_on (1<<1) 00487 #define ST25R3911_REG_AUX_DISPLAY_gpt_on (1<<2) 00488 #define ST25R3911_REG_AUX_DISPLAY_rx_on (1<<3) 00489 #define ST25R3911_REG_AUX_DISPLAY_osc_ok (1<<4) 00490 #define ST25R3911_REG_AUX_DISPLAY_tx_on (1<<5) 00491 #define ST25R3911_REG_AUX_DISPLAY_efd_o (1<<6) 00492 #define ST25R3911_REG_AUX_DISPLAY_a_cha (1<<7) 00493 #define ST25R3911_REG_WUP_TIMER_CONTROL_wcap (1<<0) 00494 #define ST25R3911_REG_WUP_TIMER_CONTROL_wph (1<<1) 00495 #define ST25R3911_REG_WUP_TIMER_CONTROL_wam (1<<2) 00496 #define ST25R3911_REG_WUP_TIMER_CONTROL_wto (1<<3) 00497 #define ST25R3911_REG_WUP_TIMER_CONTROL_wut0 (1<<4) 00498 #define ST25R3911_REG_WUP_TIMER_CONTROL_wut1 (1<<5) 00499 #define ST25R3911_REG_WUP_TIMER_CONTROL_wut2 (1<<6) 00500 #define ST25R3911_REG_WUP_TIMER_CONTROL_shift_wut (4) 00501 #define ST25R3911_REG_WUP_TIMER_CONTROL_wur (1<<7) 00502 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_ae (1<<0) 00503 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aew0 (1<<1) 00504 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aew1 (1<<2) 00505 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_aew (1) 00506 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_mask_am_aew (3<<1) 00507 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aam (1<<3) 00508 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d0 (1<<4) 00509 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d1 (1<<5) 00510 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d2 (1<<6) 00511 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d3 (1<<7) 00512 #define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_d (4) 00513 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_ae (1<<0) 00514 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aew0 (1<<1) 00515 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aew1 (1<<2) 00516 #define ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_aew (1) 00517 #define ST25R3911_REG_PHASE_MEASURE_CONF_mask_pm_aew (3<<1) 00518 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aam (1<<3) 00519 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d0 (1<<4) 00520 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d1 (1<<5) 00521 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d2 (1<<6) 00522 #define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d3 (1<<7) 00523 #define ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_d (4) 00524 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_ae (1<<0) 00525 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aew0 (1<<1) 00526 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aew1 (1<<2) 00527 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aam (1<<3) 00528 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d0 (1<<4) 00529 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d1 (1<<5) 00530 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d2 (1<<6) 00531 #define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d3 (1<<7) 00532 #define ST25R3911_REG_IC_IDENTITY_v2 (0x09) 00533 #define ST25R3911_REG_IC_IDENTITY_ic_type (1<<3) 00534 #define ST25R3911_REG_IC_IDENTITY_mask_ic_type (0x1F<<3) 00535 #define ST25R3911_REG_IC_IDENTITY_shift_ic_type (3) 00536 #define ST25R3911_REG_IC_IDENTITY_mask_ic_rev (7) 00537 00538 /*! \endcond DOXYGEN_SUPRESS */ 00539 00540 /* 00541 ****************************************************************************** 00542 * GLOBAL FUNCTION PROTOTYPES 00543 ****************************************************************************** 00544 */ 00545 /*! 00546 ***************************************************************************** 00547 * \brief Returns the content of a register within the ST25R3911 00548 * 00549 * This function is used to read out the content of ST25R3911 registers. 00550 * 00551 * \param[in] reg: Address of register to read. 00552 * \param[out] val: Returned value. 00553 * 00554 ***************************************************************************** 00555 */ 00556 //extern void st25r3911ReadRegister(uint8_t reg, uint8_t* val); 00557 00558 /*! 00559 ***************************************************************************** 00560 * \brief Writes a given value to a register within the ST25R3911 00561 * 00562 * This function is used to write \a val to address \a reg within the ST25R3911. 00563 * 00564 * \param[in] reg: Address of the register to write. 00565 * \param[in] val: Value to be written. 00566 * 00567 ***************************************************************************** 00568 */ 00569 //extern void st25r3911WriteRegister(uint8_t reg, uint8_t val); 00570 00571 /*! 00572 ***************************************************************************** 00573 * \brief Cleart bits on Register 00574 * 00575 * This function clears the given bitmask on the register 00576 * 00577 * \warning This method does not guarantee consistency of register content 00578 * when called from multiple contexts (task, ISR, thread) 00579 * 00580 * \param[in] reg: Address of the register clear 00581 * \param[in] clr_mask: Bitmask of bit to be cleared 00582 * 00583 ***************************************************************************** 00584 */ 00585 extern void st25r3911ClrRegisterBits( uint8_t reg, uint8_t clr_mask, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); 00586 00587 00588 /*! 00589 ***************************************************************************** 00590 * \brief Set bits on Register 00591 * 00592 * This function sets the given bitmask on the register 00593 * 00594 * \warning This method does not guarantee consistency of register content 00595 * when called from multiple contexts (task, ISR, thread) 00596 * 00597 * \param[in] reg: Address of the register clear 00598 * \param[in] set_mask: Bitmask of bit to be cleared 00599 * 00600 ***************************************************************************** 00601 */ 00602 extern void st25r3911SetRegisterBits( uint8_t reg, uint8_t set_mask, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); 00603 00604 00605 /*! 00606 ***************************************************************************** 00607 * \brief Changes the given bits on a ST25R3911 register 00608 * 00609 * This function is used if only a particular bits should be changed within 00610 * an ST25R3911 register. 00611 * 00612 * \warning This method does not guarantee consistency of register content 00613 * when called from multiple contexts (task, ISR, thread) 00614 * 00615 * \param[in] reg: Address of the register to write. 00616 * \param[in] valueMask: bitmask of bits to be changed 00617 * \param[in] value: the bits to be written on the enabled valueMask bits 00618 * 00619 ***************************************************************************** 00620 */ 00621 extern void st25r3911ChangeRegisterBits(uint8_t reg, uint8_t valueMask, uint8_t value, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); 00622 00623 /*! 00624 ***************************************************************************** 00625 * \brief Read a test register within the ST25R3911 00626 * 00627 * This function is used to read the content of test address \a reg within the ST25R3911. 00628 * 00629 * \param[in] reg: Address of the register to read. 00630 * \param[out] val: Returned read. 00631 * 00632 ***************************************************************************** 00633 */ 00634 extern void st25r3911ReadTestRegister(uint8_t reg, uint8_t* val, ST25R3911* mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); 00635 00636 /*! 00637 ***************************************************************************** 00638 * \brief Writes a given value to a test register within the ST25R3911 00639 * 00640 * This function is used to write \a val to test address \a reg within the ST25R3911. 00641 * 00642 * \param[in] reg: Address of the register to write. 00643 * \param[in] val: Value to be written. 00644 * 00645 ***************************************************************************** 00646 */ 00647 extern void st25r3911WriteTestRegister(uint8_t reg, uint8_t val, ST25R3911* mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); 00648 00649 /*! 00650 ***************************************************************************** 00651 * \brief Modifies a value within a ST25R3911 register 00652 * 00653 * This function is used if only a particular bits should be changed within 00654 * an ST25R3911 register. 00655 * 00656 * \warning This method does not guarantee consistency of register content 00657 * when called from multiple contexts (task, ISR, thread) 00658 * 00659 * \param[in] reg: Address of the register to write. 00660 * \param[in] clr_mask: bitmask of bits to be cleared to 0. 00661 * \param[in] set_mask: bitmask of bits to be set to 1. 00662 * 00663 ***************************************************************************** 00664 */ 00665 extern void st25r3911ModifyRegister(uint8_t reg, uint8_t clr_mask, uint8_t set_mask, SPI* mspiChannel, ST25R3911* mST25, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); 00666 00667 00668 /*! 00669 ***************************************************************************** 00670 * \brief Changes the given bits on a ST25R3911 Test register 00671 * 00672 * This function is used if only a particular bits should be changed within 00673 * an ST25R3916 register. 00674 * 00675 * \param[in] reg: Address of the Test register to change. 00676 * \param[in] valueMask: bitmask of bits to be changed 00677 * \param[in] value: the bits to be written on the enabled valueMask bits 00678 * 00679 * \warning This method does not guarantee consistency of register content 00680 * when called from multiple contexts (task, ISR, thread) 00681 00682 * \return ERR_NONE : Operation successful 00683 * \return ERR_PARAM : Invalid parameter 00684 * \return ERR_SEND : Transmission error or acknowledge not received 00685 ***************************************************************************** 00686 */ 00687 extern void st25r3911ChangeTestRegisterBits( uint8_t reg, uint8_t valueMask, uint8_t value, ST25R3911* mST25, SPI* mspiChannel, DigitalOut* gpio_cs, InterruptIn* IRQ, DigitalOut* fieldLED_01, DigitalOut* fieldLED_02, DigitalOut* fieldLED_03, DigitalOut* fieldLED_04, DigitalOut* fieldLED_05, DigitalOut* fieldLED_06 ); 00688 00689 00690 /*! 00691 ***************************************************************************** 00692 * \brief Check if register ID is valid 00693 * 00694 * Checks if the given register ID a valid ST25R3911 register 00695 * 00696 * \param[in] reg: Address of register to check 00697 * 00698 * \return true if is a valid register ID 00699 * \return false otherwise 00700 * 00701 ***************************************************************************** 00702 */ 00703 extern bool st25r3911IsRegValid( uint8_t reg ); 00704 00705 #endif /* ST25R3911_COM_H */ 00706 00707 /** 00708 * @} 00709 * 00710 * @} 00711 * 00712 * @} 00713 * 00714 * @} 00715 */ 00716
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