uvis3.h

00001 /**
00002   ******************************************************************************
00003   * @file    uvis3.h
00004   * @author  AST Robotics Team
00005   * @version V0.0.1
00006   * @date    18-February-2014
00007   * @brief   This file contains definitions uvis3.c 
00008   *          firmware driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038   
00039 
00040 /* Define to prevent recursive inclusion -------------------------------------*/
00041 #ifndef __UVIS3_H
00042 #define __UVIS3_H
00043 
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047 
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "../Common/uv.h"
00050 
00051 /** @addtogroup BSP
00052   * @{
00053   */
00054 
00055 /** @addtogroup UVIS3
00056   * @{
00057   */
00058   
00059 /** @defgroup UVIS3_Exported_Constants
00060   * @{
00061   */
00062 
00063 /******************************************************************************/
00064 /*************************** START REGISTER MAPPING  **************************/
00065 /******************************************************************************/
00066 /**
00067  * @brief Device Address
00068  */
00069 #define UVIS3_ADDRESS                                      0x8E
00070 
00071 
00072 /**
00073  * @brief Device identifier register.
00074  * \code
00075  * Read
00076  * Default value: 0xBD
00077  * 7:0 This read-only register contains the device identifier that, 
00078        for UVIS3, is set to 0xCA.
00079  * \endcode
00080  */
00081 #define UVIS3_WHO_AM_I_ADDR                             0x0F
00082   
00083 
00084  /**
00085  * @brief UVIS3 control register 1
00086  * \code
00087  * Read/write
00088  * Default value: 0x80.
00089  * 7 PD: power down control. 1 - disable; 0 - enable.
00090  * 6:2 reserved.
00091  * 1 BDU: Block Data Update. 0 - continuous update; 1 -output registers not 
00092           updated until MSB and LSB reading. //CHECK
00093  * 0 ODR: Output Data Rate. 0 - ODR disabled (one shot mode); 1 ODR at 1 Hz.
00094  * \endcode
00095  */
00096 #define UVIS3_CTRL_REG1_ADDR                            0x20
00097 
00098 
00099  /**
00100  * @brief UVIS3 control register 2
00101  * \code
00102  * Read/write
00103  * Default value: 0x00.
00104  * 7 BOOT: reboot memory content. 1 - reload flash content; 0 - normal mode.
00105  * 6:5 reserved.
00106  * 4: I2C_DIS: Disable I2C interface. 0: enable; 1: disable.
00107  * 3 SIM: SPI Serial Interface Mode Selection. 0: 4 wires interface; 
00108           1: 3 wires interface.
00109  * 2:1 Reserved
00110  * 0: One shot enable. 0: waiting for start of conversion; 
00111       1: start for a new dataset.
00112  * \endcode
00113  */
00114 #define UVIS3_CTRL_REG2_ADDR                            0x21
00115 
00116 
00117  /**
00118  * @brief UVIS3 control register 3
00119  * \code
00120  * Read/write
00121  * Default value: 0x00.
00122  * 7 INT_H_L: Interrupt active high, low. 0: active high; 1: active low.
00123  * 6 PP_OD: Push-pull/open drain selection on interrupt pads. 0: push-pull; 
00124             1: open drain.
00125  * 5:2 Reserved
00126  * 1:0 INT1_S2, INT1_S1: data signal on INT1 pad control bits. 
00127                          Default value: 00.
00128  *   |  INT1_S2  | INT1_S1  | INT1 pin               |
00129  *   -------------------------------------------------
00130  *   |     0     |  0       |  Data ready            |        
00131  *   |     0     |  1       |  UV index High         |                           
00132  *   |     1     |  0       |  UV index Low          |                            
00133  *   |     1     |  1       |  UV index High or Low  |                 
00134  * \endcode
00135  */
00136 #define UVIS3_CTRL_REG3_ADDR                            0x22
00137 
00138 
00139  /**
00140  * @brief INT1 interrupt configuration
00141  * \code
00142  * Read/write
00143  * Default value: 0x00.
00144  * 7:4 Reserved.
00145  * 3: DIFF_EN: interrupt logical block enable. 0: interrupt logick block 
00146                disable; 1: enable.
00147  * 2: LIR: Latch interrupt request into INT_SOURCE register with (24h), with 
00148            the INT_SOURCE register cleared by reading INT_SOURCE reg (24h). 
00149            0: interrupt request not latched;1: latched.
00150  * 1: UVLE: Enable interrupt generation on differential UV low event. 0: disable 
00151             interrupt request;1: enable interrupt request
00152  * 0: UVHE: Enable interrupt generation on differential UV high event SIM; 
00153             0: disable interrupt request;1: enable interrupt request
00154  * \endcode
00155  */
00156 #define UVIS3_INT_CFG_ADDR                              0x23
00157 
00158 
00159 
00160  /**
00161  * @brief Interrupt source configuration register
00162  * \code
00163  * Read/write
00164  * Default value: 0x00.
00165  * 7:3 Reserved.
00166  * 2: IA: Interrupt Active. 0: no interrupt has been generated; 
00167           1: one or more interrupt events have been generated. 
00168  * 1: UVL: Differential UV low. 0: no interrupt; 1: UVL event has occurred.
00169  * 0: UVH: Differential UV high. 0: no interrupt; 1: UVH event has occurred.
00170  * \endcode
00171  */
00172 #define UVIS3_INT_SRC_ADDR                              0x24
00173 
00174 
00175 
00176  /**
00177  * @brief Differential UV interrupt threshold
00178  * \code
00179  * Read/write
00180  * Default value: 0x00.
00181  * 7:0 Differential UV Interrupt Threshold values.
00182  * \endcode
00183  */
00184 #define UVIS3_DIFF_UV_TSH_ADDR                          0x25
00185 
00186 
00187  /**
00188  * @brief Status register
00189  * \code
00190  * Read/write
00191  * Default value: 0x00.
00192  * 7:1 Reserved.
00193  * 0: UV_DA: UV data available. 0: UV data index not available; 1: UV data 
00194              index available.
00195  * \endcode
00196  */
00197 #define UVIS3_STATUS_REG_ADDR                           0x27
00198 
00199 
00200  /**
00201  * @brief UV index data
00202  * \code
00203  * Read/write
00204  * Default value: 0x00.
00205  * 7:0 UV index data output values.
00206  * \endcode
00207  */
00208 #define UVIS3_UVDATA_OUT_ADDR                           0x28
00209 
00210 
00211 /******************************************************************************/
00212 /**************************** END REGISTER MAPPING  ***************************/
00213 /******************************************************************************/
00214 
00215 /**
00216  * @brief Device Identifier. Default value of the WHO_AM_I register.
00217  */
00218 #define I_AM_UVIS3                 ((uint8_t)0xCA)
00219 
00220 /** @defgroup Power_Mode_selection CTRL_REG1
00221   * @{
00222   */
00223 #define UVIS3_MODE_ACTIVE               ((uint8_t)0x00)
00224 #define UVIS3_MODE_POWERDOWN            ((uint8_t)0x80)
00225 
00226 #define UVIS3_MODE_MASK                 ((uint8_t)0x80)
00227 
00228 /**
00229   * @}
00230   */ 
00231 
00232 /** @defgroup OutPut_DataRate_Selection CTRL_REG1
00233   * @{
00234   */
00235 #define UVIS3_ODR_ONE_SHOT              ((uint8_t)0x00)
00236 #define UVIS3_ODR_1HZ                   ((uint8_t)0x01)
00237 
00238 #define UVIS3_ODR_MASK                  ((uint8_t)0x01)
00239 
00240 /**
00241   * @}
00242   */
00243 
00244 /** @defgroup Boot_Mode_selection CTRL_REG2
00245   * @{
00246   */
00247 #define UVIS3_BOOT_NORMALMODE           ((uint8_t)0x00)
00248 #define UVIS3_BOOT_REBOOTMEMORY         ((uint8_t)0x80)
00249 
00250 #define UVIS3_BOOT_MASK                 ((uint8_t)0x80)
00251 
00252 /**
00253   * @}
00254   */
00255 
00256 
00257 /** @defgroup UVIS3_Exported_Functions
00258   * @{
00259   */
00260 /* Sensor Configuration Functions */ 
00261 void      UVIS3_Init(UV_InitTypeDef *UVIS3_Init);
00262 uint8_t   UVIS3_ReadID(void);
00263 void      UVIS3_RebootCmd(void);
00264 void      UVIS3_GetIndex(float* pfData);
00265 
00266 /* Interrupt Configuration Functions */
00267 void      UVIS3_INT1InterruptConfig(uint16_t Int1Config);
00268 void      UVIS3_EnableIT(void);
00269 void      UVIS3_DisableIT(void);
00270 
00271 /* Uv sensor driver structure */
00272 extern UV_DrvTypeDef Uvis3Drv;
00273 
00274 /* Uv sensor IO functions */
00275 void      UV_IO_Init(void);
00276 void      UV_IO_DeInit(void);
00277 void      UV_IO_Write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t WriteAddr, uint16_t NumByteToWrite);
00278 void      UV_IO_Read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr, uint16_t NumByteToRead);
00279 
00280 /**
00281   * @}
00282   */
00283 
00284 /**
00285   * @}
00286   */ 
00287   
00288 /**
00289   * @}
00290   */ 
00291   
00292 #ifdef __cplusplus
00293   }
00294 #endif
00295   
00296 #endif /* __UVIS3_H */
00297 
00298 
00299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 
00300