Egor Syomin / Mbed 2 deprecated LG

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Dependencies:   mbed

Fork of LG by igor Apu

InputOutput.h@20:e56d63c1ca05, 2016-02-03 (annotated)

Committer:
DarkPatrick
Date:
Wed Feb 03 09:33:19 2016 +0400
Revision:
20:e56d63c1ca05
Parent:
1:f2adcae3d304 
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 1:f2adcae3d304 1 #ifndef InputOutput_H
igor_v 1:f2adcae3d304 2 #define InputOutput_H
igor_v 0:8ad47e2b6f00 3
igor_v 0:8ad47e2b6f00 4
igor_v 0:8ad47e2b6f00 5 #include "stdint.h"
igor_v 0:8ad47e2b6f00 6
igor_v 1:f2adcae3d304 7
igor_v 0:8ad47e2b6f00 8 //******************************I2C*************************************************
igor_v 0:8ad47e2b6f00 9 #define I2C0
igor_v 0:8ad47e2b6f00 10
igor_v 0:8ad47e2b6f00 11 #define I2C_IDLE 1
igor_v 0:8ad47e2b6f00 12 #define I2C_BUSY 0
igor_v 0:8ad47e2b6f00 13
igor_v 0:8ad47e2b6f00 14 #define I2CONSET_I2EN 0x0000040 /* I2C Control Set Register */
igor_v 0:8ad47e2b6f00 15 #define I2CONSET_AA 0x0000004
igor_v 0:8ad47e2b6f00 16 #define I2CONSET_SI 0x0000008
igor_v 0:8ad47e2b6f00 17 #define I2CONSET_STO 0x0000010
igor_v 0:8ad47e2b6f00 18 #define I2CONSET_STA 0x0000020
igor_v 0:8ad47e2b6f00 19
igor_v 0:8ad47e2b6f00 20 #define I2CONCLR_AAC 0x0000004 /* I2C Control clear Register */
igor_v 0:8ad47e2b6f00 21 #define I2CONCLR_SIC 0x0000008
igor_v 0:8ad47e2b6f00 22 #define I2CONCLR_STAC 0x0000020
igor_v 0:8ad47e2b6f00 23 #define I2CONCLR_I2ENC 0x0000040
igor_v 0:8ad47e2b6f00 24
igor_v 0:8ad47e2b6f00 25 #define I2SCLH_SCLH 0x00000080 /* I2C SCL Duty Cycle High Reg */
igor_v 0:8ad47e2b6f00 26 #define I2SCLL_SCLL 0x00000080 /* I2C SCL Duty Cycle Low Reg */
igor_v 0:8ad47e2b6f00 27
igor_v 0:8ad47e2b6f00 28 #define I2C_WRITELENGTH 0x00000006 /*Buffer length*/
igor_v 0:8ad47e2b6f00 29 #define A_ADDRESS 0x0000005E /*address of slave potentiometer (table 6-2 of pot's manual)*/
igor_v 0:8ad47e2b6f00 30 #define B_ADDRESS 0x0000005C /*address of slave potentiometer (table 6-2 of pot's manual)*/
igor_v 0:8ad47e2b6f00 31 #define WRITE_CMD 0x00000000 /*address of wiper0 register in memory map*/
igor_v 0:8ad47e2b6f00 32
igor_v 0:8ad47e2b6f00 33 //********************************SPI************************************************
igor_v 0:8ad47e2b6f00 34 #define HALFWORDS_FOR_ADCs 3
igor_v 0:8ad47e2b6f00 35
igor_v 0:8ad47e2b6f00 36 #define WRITE_DAC0 0x00000030 //write data to DAC 0
igor_v 0:8ad47e2b6f00 37 #define WRITE_DAC1 0x00000031 //write data to DAC 1
igor_v 0:8ad47e2b6f00 38
igor_v 0:8ad47e2b6f00 39 #define DAC (1<<23) //DAC identifer
igor_v 0:8ad47e2b6f00 40 #define ADC (1<<16) //ADC identifer
igor_v 0:8ad47e2b6f00 41
igor_v 0:8ad47e2b6f00 42 #define SetCS(a) LPC_GPIO0->FIOSET = a //set CS signal for ADC or DAC
igor_v 0:8ad47e2b6f00 43 #define ResetCS(a) LPC_GPIO0->FIOCLR = a //reset CS signal for ADC or DAC
igor_v 0:8ad47e2b6f00 44 #define SetDAC(a) LPC_GPIO0->FIOSET = a //set CS signal for ADC or DAC
igor_v 0:8ad47e2b6f00 45 #define ResetDAC(a) LPC_GPIO0->FIOCLR = a //reset CS signal for ADC or DAC
igor_v 0:8ad47e2b6f00 46
igor_v 0:8ad47e2b6f00 47
igor_v 0:8ad47e2b6f00 48
igor_v 0:8ad47e2b6f00 49 #define SSPCR1_SSE 0x00000002
igor_v 0:8ad47e2b6f00 50
igor_v 0:8ad47e2b6f00 51 #define TX_SSP_EMPT 0x00000001
igor_v 0:8ad47e2b6f00 52 #define RX_SSP_notEMPT 0x00000004
igor_v 0:8ad47e2b6f00 53 #define TX_SSP_notFULL 0x00000002
igor_v 0:8ad47e2b6f00 54 #define RX_SSP_FULL 0x00000008
igor_v 0:8ad47e2b6f00 55 #define SSP_BUSY 0x00000010
igor_v 0:8ad47e2b6f00 56
igor_v 0:8ad47e2b6f00 57 #define ADC_ERR_MSK 0x00000001
igor_v 0:8ad47e2b6f00 58 #define DAC_ERR_MSK 0x00000002
igor_v 0:8ad47e2b6f00 59
igor_v 0:8ad47e2b6f00 60 #define TIMEOUT 1000
igor_v 0:8ad47e2b6f00 61
igor_v 0:8ad47e2b6f00 62 typedef union {
igor_v 0:8ad47e2b6f00 63 int ArrayOut[31];
igor_v 0:8ad47e2b6f00 64 struct {
igor_v 0:8ad47e2b6f00 65 int WP_reg; //e. PLC output voltage
igor_v 0:8ad47e2b6f00 66 int WP_sin; //r. ������ ������ ��� - ����� 250 ��
igor_v 0:8ad47e2b6f00 67 int WP_pll; //r. ����� XOR �� ������� ���
igor_v 0:8ad47e2b6f00 68 int HF_reg; //e. HFO output voltage
igor_v 0:8ad47e2b6f00 69
igor_v 0:8ad47e2b6f00 70 int HF_dif;
igor_v 0:8ad47e2b6f00 71
igor_v 0:8ad47e2b6f00 72 int WP_Phase_Det_Array[8]; //e. arrays for "worms" output //r. ������� ��� ������ "���������"
igor_v 0:8ad47e2b6f00 73 int WP_sin_Array[8];
igor_v 0:8ad47e2b6f00 74 int WP_scope1, WP_scope2; //e. temporary variables for Rate3 monitoring //r. ��������� ���������� ��� ���������� � Rate3
igor_v 0:8ad47e2b6f00 75
igor_v 0:8ad47e2b6f00 76 uint32_t F_ras; //e. really output frequency, divided by 16 (for transmission)
igor_v 0:8ad47e2b6f00 77 uint32_t L_Vibro; //e. period of oscillation of the dither drive //r. ������ ��������� ������������
igor_v 0:8ad47e2b6f00 78 uint32_t T_Vibro; //e. pulse width of the dither drive //r. ������������ �������� ������������
igor_v 0:8ad47e2b6f00 79 uint32_t T_VB_pll; //e. PD output of the frequency regulator of the dither drive //r. ����� �� ���������� ������� ������������
igor_v 0:8ad47e2b6f00 80
igor_v 0:8ad47e2b6f00 81 int PS_dif;
igor_v 0:8ad47e2b6f00 82 int BINS_dif;
igor_v 0:8ad47e2b6f00 83 int Cnt_Dif;
igor_v 0:8ad47e2b6f00 84 int Cnt_Pls;
igor_v 0:8ad47e2b6f00 85 int Cnt_Mns;
igor_v 0:8ad47e2b6f00 86 int Tmp_Out[6];
igor_v 0:8ad47e2b6f00 87
igor_v 0:8ad47e2b6f00 88 __int64 SF_dif;
igor_v 0:8ad47e2b6f00 89
igor_v 0:8ad47e2b6f00 90 } Str;
igor_v 0:8ad47e2b6f00 91 } OUTPUT;
igor_v 0:8ad47e2b6f00 92
igor_v 0:8ad47e2b6f00 93
igor_v 1:f2adcae3d304 94
igor_v 1:f2adcae3d304 95
igor_v 1:f2adcae3d304 96
igor_v 0:8ad47e2b6f00 97 typedef union {
igor_v 0:8ad47e2b6f00 98 int ArrayIn[3];
igor_v 0:8ad47e2b6f00 99 struct {
igor_v 0:8ad47e2b6f00 100 int Tmp_in[2];
igor_v 0:8ad47e2b6f00 101 int HF_out;
igor_v 0:8ad47e2b6f00 102 int WP_sel;
igor_v 0:8ad47e2b6f00 103 } StrIn;
igor_v 0:8ad47e2b6f00 104 } INPUT;
igor_v 0:8ad47e2b6f00 105
igor_v 0:8ad47e2b6f00 106
igor_v 0:8ad47e2b6f00 107
igor_v 0:8ad47e2b6f00 108 extern INPUT Input;
igor_v 0:8ad47e2b6f00 109 extern OUTPUT Output;
igor_v 0:8ad47e2b6f00 110
igor_v 0:8ad47e2b6f00 111 void DAC_ADC_Exchange_Init(void);
igor_v 0:8ad47e2b6f00 112 void DAC_ADC_Exchange(void);
igor_v 0:8ad47e2b6f00 113 void ADC_Input(void);
igor_v 0:8ad47e2b6f00 114
igor_v 0:8ad47e2b6f00 115 void clc_HFO(void);
igor_v 0:8ad47e2b6f00 116
igor_v 0:8ad47e2b6f00 117 int clc_WP_sin(void);
igor_v 0:8ad47e2b6f00 118 void clc_PLC(void);
igor_v 0:8ad47e2b6f00 119 void init_PLC(void);
igor_v 0:8ad47e2b6f00 120
igor_v 0:8ad47e2b6f00 121 void clc_Pulses(void);
igor_v 0:8ad47e2b6f00 122 void SOI_Init(void);
igor_v 0:8ad47e2b6f00 123
igor_v 0:8ad47e2b6f00 124 void VibroDither_SwitchOn(void);
igor_v 0:8ad47e2b6f00 125 void VibroDither_SwitchOff(void);
igor_v 0:8ad47e2b6f00 126 void VibroDither_Set(void);
igor_v 0:8ad47e2b6f00 127 void DACInit(void);
igor_v 0:8ad47e2b6f00 128 void DAC_Output(int);
igor_v 0:8ad47e2b6f00 129 void clc_ThermoSensors(void);
igor_v 0:8ad47e2b6f00 130
igor_v 0:8ad47e2b6f00 131 void Out_G_photo(unsigned, unsigned);
igor_v 0:8ad47e2b6f00 132 void G_Photo_Init( void );
igor_v 0:8ad47e2b6f00 133 void G_Photo_Exchange(void);
igor_v 0:8ad47e2b6f00 134
igor_v 1:f2adcae3d304 135 #endif // InputOutput_H
igor_v 0:8ad47e2b6f00 136