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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_adc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32wg_adc.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32WG_ADC register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32WG_ADC
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32WG_ADC Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t CMD; /**< Command Register */
<> 144:ef7eb2e8f9f7 45 __I uint32_t STATUS; /**< Status Register */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t SINGLECTRL; /**< Single Sample Control Register */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t SCANCTRL; /**< Scan Control Register */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 49 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 52 __I uint32_t SINGLEDATA; /**< Single Conversion Result Data */
<> 144:ef7eb2e8f9f7 53 __I uint32_t SCANDATA; /**< Scan Conversion Result Data */
<> 144:ef7eb2e8f9f7 54 __I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
<> 144:ef7eb2e8f9f7 55 __I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t CAL; /**< Calibration Register */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 144:ef7eb2e8f9f7 59 __IO uint32_t BIASPROG; /**< Bias Programming Register */
<> 144:ef7eb2e8f9f7 60 } ADC_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 63 * @defgroup EFM32WG_ADC_BitFields
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 *****************************************************************************/
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /* Bit fields for ADC CTRL */
<> 144:ef7eb2e8f9f7 68 #define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
<> 144:ef7eb2e8f9f7 69 #define _ADC_CTRL_MASK 0x0F7F7F3BUL /**< Mask for ADC_CTRL */
<> 144:ef7eb2e8f9f7 70 #define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
<> 144:ef7eb2e8f9f7 71 #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
<> 144:ef7eb2e8f9f7 72 #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 73 #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
<> 144:ef7eb2e8f9f7 74 #define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */
<> 144:ef7eb2e8f9f7 75 #define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */
<> 144:ef7eb2e8f9f7 76 #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
<> 144:ef7eb2e8f9f7 77 #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 78 #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
<> 144:ef7eb2e8f9f7 79 #define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /**< Shifted mode FASTBG for ADC_CTRL */
<> 144:ef7eb2e8f9f7 80 #define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */
<> 144:ef7eb2e8f9f7 81 #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
<> 144:ef7eb2e8f9f7 82 #define ADC_CTRL_TAILGATE (0x1UL << 3) /**< Conversion Tailgating */
<> 144:ef7eb2e8f9f7 83 #define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */
<> 144:ef7eb2e8f9f7 84 #define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */
<> 144:ef7eb2e8f9f7 85 #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 86 #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 87 #define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */
<> 144:ef7eb2e8f9f7 88 #define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */
<> 144:ef7eb2e8f9f7 89 #define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 90 #define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */
<> 144:ef7eb2e8f9f7 91 #define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /**< Mode DECAP for ADC_CTRL */
<> 144:ef7eb2e8f9f7 92 #define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /**< Mode RCFILT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 93 #define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 94 #define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /**< Shifted mode BYPASS for ADC_CTRL */
<> 144:ef7eb2e8f9f7 95 #define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /**< Shifted mode DECAP for ADC_CTRL */
<> 144:ef7eb2e8f9f7 96 #define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /**< Shifted mode RCFILT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 97 #define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
<> 144:ef7eb2e8f9f7 98 #define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
<> 144:ef7eb2e8f9f7 99 #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 100 #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
<> 144:ef7eb2e8f9f7 101 #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 102 #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
<> 144:ef7eb2e8f9f7 103 #define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
<> 144:ef7eb2e8f9f7 104 #define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */
<> 144:ef7eb2e8f9f7 105 #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 106 #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 107 #define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
<> 144:ef7eb2e8f9f7 108 #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
<> 144:ef7eb2e8f9f7 109 #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 110 #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 111 #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 112 #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 113 #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 114 #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 115 #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 116 #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 117 #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 118 #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 119 #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 120 #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 121 #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 122 #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
<> 144:ef7eb2e8f9f7 123 #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 124 #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 125 #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 126 #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 127 #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 128 #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 129 #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 130 #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 131 #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 132 #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 133 #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 134 #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Bit fields for ADC CMD */
<> 144:ef7eb2e8f9f7 137 #define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
<> 144:ef7eb2e8f9f7 138 #define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
<> 144:ef7eb2e8f9f7 139 #define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */
<> 144:ef7eb2e8f9f7 140 #define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
<> 144:ef7eb2e8f9f7 141 #define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
<> 144:ef7eb2e8f9f7 142 #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 143 #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 144 #define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */
<> 144:ef7eb2e8f9f7 145 #define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
<> 144:ef7eb2e8f9f7 146 #define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
<> 144:ef7eb2e8f9f7 147 #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 148 #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 149 #define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
<> 144:ef7eb2e8f9f7 150 #define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
<> 144:ef7eb2e8f9f7 151 #define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
<> 144:ef7eb2e8f9f7 152 #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 153 #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 154 #define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
<> 144:ef7eb2e8f9f7 155 #define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
<> 144:ef7eb2e8f9f7 156 #define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
<> 144:ef7eb2e8f9f7 157 #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 158 #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Bit fields for ADC STATUS */
<> 144:ef7eb2e8f9f7 161 #define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
<> 144:ef7eb2e8f9f7 162 #define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */
<> 144:ef7eb2e8f9f7 163 #define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */
<> 144:ef7eb2e8f9f7 164 #define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
<> 144:ef7eb2e8f9f7 165 #define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
<> 144:ef7eb2e8f9f7 166 #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 167 #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 168 #define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
<> 144:ef7eb2e8f9f7 169 #define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
<> 144:ef7eb2e8f9f7 170 #define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
<> 144:ef7eb2e8f9f7 171 #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 172 #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 173 #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */
<> 144:ef7eb2e8f9f7 174 #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
<> 144:ef7eb2e8f9f7 175 #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
<> 144:ef7eb2e8f9f7 176 #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 177 #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 178 #define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
<> 144:ef7eb2e8f9f7 179 #define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
<> 144:ef7eb2e8f9f7 180 #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
<> 144:ef7eb2e8f9f7 181 #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 182 #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 183 #define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
<> 144:ef7eb2e8f9f7 184 #define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
<> 144:ef7eb2e8f9f7 185 #define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
<> 144:ef7eb2e8f9f7 186 #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 187 #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 188 #define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Sample Data Valid */
<> 144:ef7eb2e8f9f7 189 #define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
<> 144:ef7eb2e8f9f7 190 #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
<> 144:ef7eb2e8f9f7 191 #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 192 #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 193 #define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
<> 144:ef7eb2e8f9f7 194 #define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
<> 144:ef7eb2e8f9f7 195 #define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
<> 144:ef7eb2e8f9f7 196 #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 197 #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 198 #define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */
<> 144:ef7eb2e8f9f7 199 #define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */
<> 144:ef7eb2e8f9f7 200 #define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 201 #define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /**< Mode CH0 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 202 #define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /**< Mode CH1 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 203 #define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /**< Mode CH2 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 204 #define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /**< Mode CH3 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 205 #define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /**< Mode CH4 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 206 #define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /**< Mode CH5 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 207 #define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /**< Mode CH6 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 208 #define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /**< Mode CH7 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 209 #define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_STATUS */
<> 144:ef7eb2e8f9f7 210 #define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /**< Shifted mode CH0 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 211 #define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /**< Shifted mode CH1 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 212 #define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /**< Shifted mode CH2 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 213 #define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /**< Shifted mode CH3 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 214 #define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /**< Shifted mode CH4 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 215 #define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /**< Shifted mode CH5 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 216 #define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /**< Shifted mode CH6 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 217 #define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /**< Shifted mode CH7 for ADC_STATUS */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Bit fields for ADC SINGLECTRL */
<> 144:ef7eb2e8f9f7 220 #define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 221 #define _ADC_SINGLECTRL_MASK 0xF1F70F37UL /**< Mask for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 222 #define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Sample Repetitive Mode */
<> 144:ef7eb2e8f9f7 223 #define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
<> 144:ef7eb2e8f9f7 224 #define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
<> 144:ef7eb2e8f9f7 225 #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 226 #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 227 #define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Sample Differential Mode */
<> 144:ef7eb2e8f9f7 228 #define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
<> 144:ef7eb2e8f9f7 229 #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
<> 144:ef7eb2e8f9f7 230 #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 231 #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 232 #define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Sample Result Adjustment */
<> 144:ef7eb2e8f9f7 233 #define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
<> 144:ef7eb2e8f9f7 234 #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
<> 144:ef7eb2e8f9f7 235 #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 236 #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 237 #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 238 #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 239 #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 240 #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 241 #define _ADC_SINGLECTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
<> 144:ef7eb2e8f9f7 242 #define _ADC_SINGLECTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
<> 144:ef7eb2e8f9f7 243 #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 244 #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 245 #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 246 #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 247 #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 248 #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 249 #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 250 #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 251 #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 252 #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 253 #define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
<> 144:ef7eb2e8f9f7 254 #define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
<> 144:ef7eb2e8f9f7 255 #define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 256 #define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 257 #define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 258 #define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 259 #define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 260 #define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 261 #define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 262 #define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 263 #define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 264 #define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 265 #define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 266 #define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 267 #define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 268 #define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 269 #define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /**< Mode TEMP for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 270 #define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /**< Mode VDDDIV3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 271 #define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /**< Mode VDD for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 272 #define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /**< Mode VSS for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 273 #define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /**< Mode VREFDIV2 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 274 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 275 #define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 276 #define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 277 #define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 278 #define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 279 #define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 280 #define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 281 #define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 282 #define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 283 #define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 284 #define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 285 #define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 286 #define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 287 #define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 288 #define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 289 #define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 290 #define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 291 #define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 292 #define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /**< Shifted mode VDD for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 293 #define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 294 #define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 295 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 296 #define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 297 #define _ADC_SINGLECTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
<> 144:ef7eb2e8f9f7 298 #define _ADC_SINGLECTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
<> 144:ef7eb2e8f9f7 299 #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 300 #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 301 #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 302 #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 303 #define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 304 #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 305 #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 306 #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 307 #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 308 #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 309 #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 310 #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 311 #define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 312 #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 313 #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 314 #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 315 #define _ADC_SINGLECTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
<> 144:ef7eb2e8f9f7 316 #define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
<> 144:ef7eb2e8f9f7 317 #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 318 #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 319 #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 320 #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 321 #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 322 #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 323 #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 324 #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 325 #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 326 #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 327 #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 328 #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 329 #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 330 #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 331 #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 332 #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 333 #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 334 #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 335 #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 336 #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 337 #define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /**< Single Sample PRS Trigger Enable */
<> 144:ef7eb2e8f9f7 338 #define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
<> 144:ef7eb2e8f9f7 339 #define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
<> 144:ef7eb2e8f9f7 340 #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 341 #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 342 #define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
<> 144:ef7eb2e8f9f7 343 #define _ADC_SINGLECTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
<> 144:ef7eb2e8f9f7 344 #define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 345 #define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 346 #define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 347 #define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 348 #define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 349 #define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 350 #define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 351 #define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 352 #define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 353 #define _ADC_SINGLECTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 354 #define _ADC_SINGLECTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 355 #define _ADC_SINGLECTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 356 #define _ADC_SINGLECTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 357 #define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 358 #define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 359 #define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 360 #define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 361 #define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 362 #define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 363 #define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 364 #define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 365 #define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 366 #define ADC_SINGLECTRL_PRSSEL_PRSCH8 (_ADC_SINGLECTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 367 #define ADC_SINGLECTRL_PRSSEL_PRSCH9 (_ADC_SINGLECTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 368 #define ADC_SINGLECTRL_PRSSEL_PRSCH10 (_ADC_SINGLECTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 369 #define ADC_SINGLECTRL_PRSSEL_PRSCH11 (_ADC_SINGLECTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SINGLECTRL */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Bit fields for ADC SCANCTRL */
<> 144:ef7eb2e8f9f7 372 #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 373 #define _ADC_SCANCTRL_MASK 0xF1F7FF37UL /**< Mask for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 374 #define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
<> 144:ef7eb2e8f9f7 375 #define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
<> 144:ef7eb2e8f9f7 376 #define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
<> 144:ef7eb2e8f9f7 377 #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 378 #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 379 #define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
<> 144:ef7eb2e8f9f7 380 #define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
<> 144:ef7eb2e8f9f7 381 #define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
<> 144:ef7eb2e8f9f7 382 #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 383 #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 384 #define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
<> 144:ef7eb2e8f9f7 385 #define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
<> 144:ef7eb2e8f9f7 386 #define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
<> 144:ef7eb2e8f9f7 387 #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 388 #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 389 #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 390 #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 391 #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 392 #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 393 #define _ADC_SCANCTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
<> 144:ef7eb2e8f9f7 394 #define _ADC_SCANCTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
<> 144:ef7eb2e8f9f7 395 #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 396 #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 397 #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 398 #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 399 #define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 400 #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 401 #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 402 #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 403 #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 404 #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 405 #define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
<> 144:ef7eb2e8f9f7 406 #define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
<> 144:ef7eb2e8f9f7 407 #define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 408 #define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 409 #define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 410 #define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 411 #define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 412 #define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 413 #define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 414 #define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 415 #define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 416 #define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 417 #define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /**< Mode CH5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 418 #define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 419 #define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 420 #define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 421 #define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 422 #define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 423 #define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 424 #define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 425 #define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 426 #define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 427 #define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 428 #define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 429 #define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 430 #define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /**< Shifted mode CH5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 431 #define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /**< Shifted mode CH6 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 432 #define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /**< Shifted mode CH7 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 433 #define _ADC_SCANCTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
<> 144:ef7eb2e8f9f7 434 #define _ADC_SCANCTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
<> 144:ef7eb2e8f9f7 435 #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 436 #define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 437 #define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 438 #define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 439 #define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 440 #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 441 #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 442 #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 443 #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 444 #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 445 #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 446 #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 447 #define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 448 #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 449 #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 450 #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 451 #define _ADC_SCANCTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
<> 144:ef7eb2e8f9f7 452 #define _ADC_SCANCTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
<> 144:ef7eb2e8f9f7 453 #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 454 #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 455 #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 456 #define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 457 #define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 458 #define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 459 #define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 460 #define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 461 #define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 462 #define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 463 #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 464 #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 465 #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 466 #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 467 #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 468 #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 469 #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 470 #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 471 #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 472 #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 473 #define ADC_SCANCTRL_PRSEN (0x1UL << 24) /**< Scan Sequence PRS Trigger Enable */
<> 144:ef7eb2e8f9f7 474 #define _ADC_SCANCTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
<> 144:ef7eb2e8f9f7 475 #define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
<> 144:ef7eb2e8f9f7 476 #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 477 #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 478 #define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
<> 144:ef7eb2e8f9f7 479 #define _ADC_SCANCTRL_PRSSEL_MASK 0xF0000000UL /**< Bit mask for ADC_PRSSEL */
<> 144:ef7eb2e8f9f7 480 #define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 481 #define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 482 #define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 483 #define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 484 #define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 485 #define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 486 #define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 487 #define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 488 #define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 489 #define _ADC_SCANCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 490 #define _ADC_SCANCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 491 #define _ADC_SCANCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 492 #define _ADC_SCANCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 493 #define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 494 #define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 495 #define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 496 #define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 497 #define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 498 #define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 499 #define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 500 #define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 501 #define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 502 #define ADC_SCANCTRL_PRSSEL_PRSCH8 (_ADC_SCANCTRL_PRSSEL_PRSCH8 << 28) /**< Shifted mode PRSCH8 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 503 #define ADC_SCANCTRL_PRSSEL_PRSCH9 (_ADC_SCANCTRL_PRSSEL_PRSCH9 << 28) /**< Shifted mode PRSCH9 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 504 #define ADC_SCANCTRL_PRSSEL_PRSCH10 (_ADC_SCANCTRL_PRSSEL_PRSCH10 << 28) /**< Shifted mode PRSCH10 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 505 #define ADC_SCANCTRL_PRSSEL_PRSCH11 (_ADC_SCANCTRL_PRSSEL_PRSCH11 << 28) /**< Shifted mode PRSCH11 for ADC_SCANCTRL */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Bit fields for ADC IEN */
<> 144:ef7eb2e8f9f7 508 #define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
<> 144:ef7eb2e8f9f7 509 #define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */
<> 144:ef7eb2e8f9f7 510 #define ADC_IEN_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 511 #define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 512 #define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 513 #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 514 #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 515 #define ADC_IEN_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 516 #define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
<> 144:ef7eb2e8f9f7 517 #define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
<> 144:ef7eb2e8f9f7 518 #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 519 #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 520 #define ADC_IEN_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 521 #define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 522 #define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 523 #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 524 #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 525 #define ADC_IEN_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 526 #define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 527 #define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 528 #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 529 #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Bit fields for ADC IF */
<> 144:ef7eb2e8f9f7 532 #define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
<> 144:ef7eb2e8f9f7 533 #define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */
<> 144:ef7eb2e8f9f7 534 #define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 535 #define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 536 #define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 537 #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 538 #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 539 #define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 540 #define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
<> 144:ef7eb2e8f9f7 541 #define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
<> 144:ef7eb2e8f9f7 542 #define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 543 #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 544 #define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 545 #define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 546 #define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 547 #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 548 #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 549 #define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 550 #define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 551 #define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 552 #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 553 #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Bit fields for ADC IFS */
<> 144:ef7eb2e8f9f7 556 #define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
<> 144:ef7eb2e8f9f7 557 #define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */
<> 144:ef7eb2e8f9f7 558 #define ADC_IFS_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 559 #define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 560 #define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 561 #define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 562 #define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 563 #define ADC_IFS_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 564 #define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
<> 144:ef7eb2e8f9f7 565 #define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
<> 144:ef7eb2e8f9f7 566 #define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 567 #define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 568 #define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 569 #define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 570 #define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 571 #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 572 #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 573 #define ADC_IFS_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 574 #define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 575 #define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 576 #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 577 #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Bit fields for ADC IFC */
<> 144:ef7eb2e8f9f7 580 #define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
<> 144:ef7eb2e8f9f7 581 #define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */
<> 144:ef7eb2e8f9f7 582 #define ADC_IFC_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 583 #define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 584 #define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
<> 144:ef7eb2e8f9f7 585 #define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 586 #define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 587 #define ADC_IFC_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 588 #define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
<> 144:ef7eb2e8f9f7 589 #define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
<> 144:ef7eb2e8f9f7 590 #define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 591 #define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 592 #define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 593 #define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 594 #define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
<> 144:ef7eb2e8f9f7 595 #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 596 #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 597 #define ADC_IFC_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 598 #define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 599 #define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
<> 144:ef7eb2e8f9f7 600 #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 601 #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Bit fields for ADC SINGLEDATA */
<> 144:ef7eb2e8f9f7 604 #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
<> 144:ef7eb2e8f9f7 605 #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
<> 144:ef7eb2e8f9f7 606 #define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
<> 144:ef7eb2e8f9f7 607 #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
<> 144:ef7eb2e8f9f7 608 #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
<> 144:ef7eb2e8f9f7 609 #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Bit fields for ADC SCANDATA */
<> 144:ef7eb2e8f9f7 612 #define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
<> 144:ef7eb2e8f9f7 613 #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
<> 144:ef7eb2e8f9f7 614 #define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
<> 144:ef7eb2e8f9f7 615 #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
<> 144:ef7eb2e8f9f7 616 #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
<> 144:ef7eb2e8f9f7 617 #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Bit fields for ADC SINGLEDATAP */
<> 144:ef7eb2e8f9f7 620 #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
<> 144:ef7eb2e8f9f7 621 #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
<> 144:ef7eb2e8f9f7 622 #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
<> 144:ef7eb2e8f9f7 623 #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
<> 144:ef7eb2e8f9f7 624 #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
<> 144:ef7eb2e8f9f7 625 #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Bit fields for ADC SCANDATAP */
<> 144:ef7eb2e8f9f7 628 #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
<> 144:ef7eb2e8f9f7 629 #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
<> 144:ef7eb2e8f9f7 630 #define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
<> 144:ef7eb2e8f9f7 631 #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
<> 144:ef7eb2e8f9f7 632 #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
<> 144:ef7eb2e8f9f7 633 #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Bit fields for ADC CAL */
<> 144:ef7eb2e8f9f7 636 #define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */
<> 144:ef7eb2e8f9f7 637 #define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */
<> 144:ef7eb2e8f9f7 638 #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
<> 144:ef7eb2e8f9f7 639 #define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */
<> 144:ef7eb2e8f9f7 640 #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 641 #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 642 #define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
<> 144:ef7eb2e8f9f7 643 #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
<> 144:ef7eb2e8f9f7 644 #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 645 #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 646 #define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
<> 144:ef7eb2e8f9f7 647 #define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */
<> 144:ef7eb2e8f9f7 648 #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 649 #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 650 #define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
<> 144:ef7eb2e8f9f7 651 #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
<> 144:ef7eb2e8f9f7 652 #define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 653 #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Bit fields for ADC BIASPROG */
<> 144:ef7eb2e8f9f7 656 #define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 657 #define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 658 #define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 659 #define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 660 #define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 661 #define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 662 #define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
<> 144:ef7eb2e8f9f7 663 #define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */
<> 144:ef7eb2e8f9f7 664 #define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */
<> 144:ef7eb2e8f9f7 665 #define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 666 #define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 667 #define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */
<> 144:ef7eb2e8f9f7 668 #define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */
<> 144:ef7eb2e8f9f7 669 #define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 670 #define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /** @} End of group EFM32WG_ADC */
<> 144:ef7eb2e8f9f7 673 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 674