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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_devinfo.h@50:a417edff4437, 2016-01-15 (annotated)

Committer:
mbed_official
Date:
Fri Jan 15 07:45:16 2016 +0000
Revision:
50:a417edff4437
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9



Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/



Remove doubling of buffer size in realiseEndpoint()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32zg_devinfo.h
bogdanm 0:9b334a45a8ff 3 * @brief EFM32ZG_DEVINFO register and bit field definitions
mbed_official 50:a417edff4437 4 * @version 4.2.0
bogdanm 0:9b334a45a8ff 5 ******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
mbed_official 50:a417edff4437 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 22 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 23 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 24 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 25 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 28 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 29 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 *****************************************************************************/
bogdanm 0:9b334a45a8ff 32 /**************************************************************************//**
mbed_official 50:a417edff4437 33 * @addtogroup Parts
mbed_official 50:a417edff4437 34 * @{
mbed_official 50:a417edff4437 35 ******************************************************************************/
mbed_official 50:a417edff4437 36 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 37 * @defgroup EFM32ZG_DEVINFO
bogdanm 0:9b334a45a8ff 38 * @{
bogdanm 0:9b334a45a8ff 39 *****************************************************************************/
bogdanm 0:9b334a45a8ff 40 typedef struct
bogdanm 0:9b334a45a8ff 41 {
bogdanm 0:9b334a45a8ff 42 __I uint32_t CAL; /**< Calibration temperature and checksum */
bogdanm 0:9b334a45a8ff 43 __I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
bogdanm 0:9b334a45a8ff 44 __I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
bogdanm 0:9b334a45a8ff 45 __I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
bogdanm 0:9b334a45a8ff 46 uint32_t RESERVED0[2]; /**< Reserved */
bogdanm 0:9b334a45a8ff 47 __I uint32_t IDAC0CAL0; /**< IDAC0 calibration register */
bogdanm 0:9b334a45a8ff 48 uint32_t RESERVED1[2]; /**< Reserved */
bogdanm 0:9b334a45a8ff 49 __I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
bogdanm 0:9b334a45a8ff 50 __I uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
bogdanm 0:9b334a45a8ff 51 __I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
bogdanm 0:9b334a45a8ff 52 __I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
bogdanm 0:9b334a45a8ff 53 __I uint32_t MEMINFO; /**< Memory information */
bogdanm 0:9b334a45a8ff 54 uint32_t RESERVED2[2]; /**< Reserved */
bogdanm 0:9b334a45a8ff 55 __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
bogdanm 0:9b334a45a8ff 56 __I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
bogdanm 0:9b334a45a8ff 57 __I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
bogdanm 0:9b334a45a8ff 58 __I uint32_t PART; /**< Part description */
bogdanm 0:9b334a45a8ff 59 } DEVINFO_TypeDef; /** @} */
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 62 * @defgroup EFM32ZG_DEVINFO_BitFields
bogdanm 0:9b334a45a8ff 63 * @{
bogdanm 0:9b334a45a8ff 64 *****************************************************************************/
bogdanm 0:9b334a45a8ff 65 /* Bit fields for EFM32ZG_DEVINFO */
bogdanm 0:9b334a45a8ff 66 #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
bogdanm 0:9b334a45a8ff 67 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
bogdanm 0:9b334a45a8ff 68 #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
bogdanm 0:9b334a45a8ff 69 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
bogdanm 0:9b334a45a8ff 70 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
bogdanm 0:9b334a45a8ff 71 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
bogdanm 0:9b334a45a8ff 72 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
bogdanm 0:9b334a45a8ff 73 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
bogdanm 0:9b334a45a8ff 74 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
bogdanm 0:9b334a45a8ff 75 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
bogdanm 0:9b334a45a8ff 76 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
bogdanm 0:9b334a45a8ff 77 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
bogdanm 0:9b334a45a8ff 78 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
bogdanm 0:9b334a45a8ff 79 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
bogdanm 0:9b334a45a8ff 80 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
bogdanm 0:9b334a45a8ff 81 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
bogdanm 0:9b334a45a8ff 82 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
bogdanm 0:9b334a45a8ff 83 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
bogdanm 0:9b334a45a8ff 84 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
bogdanm 0:9b334a45a8ff 85 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
bogdanm 0:9b334a45a8ff 86 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
bogdanm 0:9b334a45a8ff 87 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
bogdanm 0:9b334a45a8ff 88 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
bogdanm 0:9b334a45a8ff 89 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
bogdanm 0:9b334a45a8ff 90 #define _DEVINFO_IDAC0CAL0_RANGE0_MASK 0x000000FFUL /**< Current range 0 tuning value for IDAC0 mask */
bogdanm 0:9b334a45a8ff 91 #define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT 0 /**< Current range 0 tuning value for IDAC0 shift */
bogdanm 0:9b334a45a8ff 92 #define _DEVINFO_IDAC0CAL0_RANGE1_MASK 0x0000FF00UL /**< Current range 1 tuning value for IDAC0 mask */
bogdanm 0:9b334a45a8ff 93 #define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT 8 /**< Current range 1 tuning value for IDAC0 shift */
bogdanm 0:9b334a45a8ff 94 #define _DEVINFO_IDAC0CAL0_RANGE2_MASK 0x00FF0000UL /**< Current range 2 tuning value for IDAC0 mask */
bogdanm 0:9b334a45a8ff 95 #define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT 16 /**< Current range 2 tuning value for IDAC0 shift */
bogdanm 0:9b334a45a8ff 96 #define _DEVINFO_IDAC0CAL0_RANGE3_MASK 0xFF000000UL /**< Current range 3 tuning value for IDAC0 mask */
bogdanm 0:9b334a45a8ff 97 #define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT 24 /**< Current range 3 tuning value for IDAC0 shift */
bogdanm 0:9b334a45a8ff 98 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
bogdanm 0:9b334a45a8ff 99 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
bogdanm 0:9b334a45a8ff 100 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
bogdanm 0:9b334a45a8ff 101 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
bogdanm 0:9b334a45a8ff 102 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
bogdanm 0:9b334a45a8ff 103 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
bogdanm 0:9b334a45a8ff 104 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
bogdanm 0:9b334a45a8ff 105 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
bogdanm 0:9b334a45a8ff 106 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
bogdanm 0:9b334a45a8ff 107 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
bogdanm 0:9b334a45a8ff 108 #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
bogdanm 0:9b334a45a8ff 109 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
bogdanm 0:9b334a45a8ff 110 #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
bogdanm 0:9b334a45a8ff 111 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
bogdanm 0:9b334a45a8ff 112 #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
bogdanm 0:9b334a45a8ff 113 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
bogdanm 0:9b334a45a8ff 114 #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
bogdanm 0:9b334a45a8ff 115 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
bogdanm 0:9b334a45a8ff 116 #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
bogdanm 0:9b334a45a8ff 117 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
bogdanm 0:9b334a45a8ff 118 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
bogdanm 0:9b334a45a8ff 119 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
bogdanm 0:9b334a45a8ff 120 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
bogdanm 0:9b334a45a8ff 121 #define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
bogdanm 0:9b334a45a8ff 122 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
bogdanm 0:9b334a45a8ff 123 #define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
bogdanm 0:9b334a45a8ff 124 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
bogdanm 0:9b334a45a8ff 125 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
bogdanm 0:9b334a45a8ff 126 #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
bogdanm 0:9b334a45a8ff 127 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
bogdanm 0:9b334a45a8ff 128 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
bogdanm 0:9b334a45a8ff 129 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
bogdanm 0:9b334a45a8ff 130 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
bogdanm 0:9b334a45a8ff 131 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
mbed_official 50:a417edff4437 132 /* Legacy family #defines */
bogdanm 0:9b334a45a8ff 133 #define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
bogdanm 0:9b334a45a8ff 134 #define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
bogdanm 0:9b334a45a8ff 135 #define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
bogdanm 0:9b334a45a8ff 136 #define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
bogdanm 0:9b334a45a8ff 137 #define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
bogdanm 0:9b334a45a8ff 138 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
mbed_official 50:a417edff4437 139 #define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
mbed_official 50:a417edff4437 140 /* New style family #defines */
mbed_official 50:a417edff4437 141 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
mbed_official 50:a417edff4437 142 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
mbed_official 50:a417edff4437 143 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
mbed_official 50:a417edff4437 144 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
mbed_official 50:a417edff4437 145 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
mbed_official 50:a417edff4437 146 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
mbed_official 50:a417edff4437 147 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
mbed_official 50:a417edff4437 148 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
mbed_official 50:a417edff4437 149 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
mbed_official 50:a417edff4437 150 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
bogdanm 0:9b334a45a8ff 151 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
bogdanm 0:9b334a45a8ff 152 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /** @} End of group EFM32ZG_DEVINFO */
mbed_official 50:a417edff4437 155 /** @} End of group Parts */
bogdanm 0:9b334a45a8ff 156