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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h@151:91825d030f9b, 2016-11-14 (annotated)

Committer:
DangerousElectrician
Date:
Mon Nov 14 04:39:23 2016 +0000
Revision:
151:91825d030f9b
Parent:
149:156823d33999 
stuff changed?

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 8 * module driver.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @attention
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 15 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 20 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 22 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 23 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 ******************************************************************************
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #ifndef __STM32L0xx_HAL_H
<> 144:ef7eb2e8f9f7 41 #define __STM32L0xx_HAL_H
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32l0xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @defgroup HAL HAL
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** @defgroup SYSCFG_BootMode Boot Mode
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 65 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0)
<> 144:ef7eb2e8f9f7 66 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE)
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /**
<> 144:ef7eb2e8f9f7 69 * @}
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP
<> 144:ef7eb2e8f9f7 76 #define DBGMCU_STOP DBGMCU_CR_DBG_STOP
<> 144:ef7eb2e8f9f7 77 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
<> 144:ef7eb2e8f9f7 78 #define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00) && ((__PERIPH__) != 0x00))
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /**
<> 144:ef7eb2e8f9f7 82 * @}
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #if defined (LCD_BASE) /* STM32L0x3xx only */
<> 144:ef7eb2e8f9f7 86 /** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors
<> 144:ef7eb2e8f9f7 87 * @{
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89 #define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */
<> 144:ef7eb2e8f9f7 90 #define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */
<> 144:ef7eb2e8f9f7 91 #define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */
<> 144:ef7eb2e8f9f7 92 #define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */
<> 144:ef7eb2e8f9f7 93 #if defined (SYSCFG_CFGR2_CAPA_3)
<> 144:ef7eb2e8f9f7 94 #define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */
<> 144:ef7eb2e8f9f7 95 #endif
<> 144:ef7eb2e8f9f7 96 #if defined (SYSCFG_CFGR2_CAPA_4)
<> 144:ef7eb2e8f9f7 97 #define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */
<> 144:ef7eb2e8f9f7 98 #endif
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @}
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 #endif
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 #define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000) /* no pad connected */
<> 144:ef7eb2e8f9f7 109 #define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */
<> 144:ef7eb2e8f9f7 110 #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */
<> 144:ef7eb2e8f9f7 111 #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \
<> 144:ef7eb2e8f9f7 114 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \
<> 144:ef7eb2e8f9f7 115 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \
<> 144:ef7eb2e8f9f7 116 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1))
<> 144:ef7eb2e8f9f7 117 /**
<> 144:ef7eb2e8f9f7 118 * @}
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124 #define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY))
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /**
<> 144:ef7eb2e8f9f7 129 * @}
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO
<> 144:ef7eb2e8f9f7 133 * @{
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135 /** @brief Fast mode Plus driving capability on a specific GPIO
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 #if defined (SYSCFG_CFGR2_I2C_PB6_FMP)
<> 144:ef7eb2e8f9f7 138 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */
<> 144:ef7eb2e8f9f7 139 #endif
<> 144:ef7eb2e8f9f7 140 #if defined (SYSCFG_CFGR2_I2C_PB7_FMP)
<> 144:ef7eb2e8f9f7 141 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */
<> 144:ef7eb2e8f9f7 142 #endif
<> 144:ef7eb2e8f9f7 143 #if defined (SYSCFG_CFGR2_I2C_PB8_FMP)
<> 144:ef7eb2e8f9f7 144 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146 #if defined (SYSCFG_CFGR2_I2C_PB9_FMP)
<> 144:ef7eb2e8f9f7 147 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */
<> 144:ef7eb2e8f9f7 148 #endif
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \
<> 144:ef7eb2e8f9f7 151 (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \
<> 144:ef7eb2e8f9f7 152 (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \
<> 144:ef7eb2e8f9f7 153 (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) )
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @brief Freeze/Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief TIM2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 172 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 173 #endif
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @brief TIM3 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 180 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 181 #endif
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @brief TIM6 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 188 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 189 #endif
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @brief TIM7 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 196 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 197 #endif
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @brief RTC Peripherals Debug mode
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 204 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 205 #endif
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief WWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 212 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 213 #endif
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @brief IWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 220 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 221 #endif
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP)
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief I2C1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
<> 144:ef7eb2e8f9f7 228 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
<> 144:ef7eb2e8f9f7 229 #endif
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP)
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @brief I2C2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
<> 144:ef7eb2e8f9f7 236 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
<> 144:ef7eb2e8f9f7 237 #endif
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 #if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP)
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief I2C3 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
<> 144:ef7eb2e8f9f7 244 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
<> 144:ef7eb2e8f9f7 245 #endif
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 #if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief LPTIMER Peripherals Debug mode
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
<> 144:ef7eb2e8f9f7 252 #define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
<> 144:ef7eb2e8f9f7 253 #endif
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 #if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP)
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @brief TIM22 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 #define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
<> 144:ef7eb2e8f9f7 260 #define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
<> 144:ef7eb2e8f9f7 261 #endif
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP)
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief TIM21 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 #define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
<> 144:ef7eb2e8f9f7 268 #define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
<> 144:ef7eb2e8f9f7 269 #endif
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /** @brief Main Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /** @brief System Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @brief Embedded SRAM mapped at 0x00000000
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1)
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @brief Configuration of the DBG Low Power mode.
<> 144:ef7eb2e8f9f7 285 * @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active.
<> 144:ef7eb2e8f9f7 286 * This parameter can be a value of
<> 144:ef7eb2e8f9f7 287 * - DBGMCU_SLEEP
<> 144:ef7eb2e8f9f7 288 * - DBGMCU_STOP
<> 144:ef7eb2e8f9f7 289 * - DBGMCU_STANDBY
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 #define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \
<> 144:ef7eb2e8f9f7 292 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
<> 144:ef7eb2e8f9f7 293 } while (0)
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Returns the boot mode as configured by user.
<> 144:ef7eb2e8f9f7 296 * @retval The boot mode as configured by user. The returned can be a value of :
<> 144:ef7eb2e8f9f7 297 * - SYSCFG_BOOT_MAINFLASH
<> 144:ef7eb2e8f9f7 298 * - SYSCFG_BOOT_SYSTEMFLASH
<> 144:ef7eb2e8f9f7 299 * - SYSCFG_BOOT_SRAM
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @brief Check whether the specified SYSCFG flag is set or not.
<> 144:ef7eb2e8f9f7 305 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 306 * The only parameter supported is SYSCFG_FLAG_VREFINT_READY
<> 144:ef7eb2e8f9f7 307 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /** @brief Fast mode Plus driving capability enable macro
<> 144:ef7eb2e8f9f7 312 * @param __FASTMODEPLUS__: This parameter can be a value of :
<> 144:ef7eb2e8f9f7 313 * @arg SYSCFG_FASTMODEPLUS_PB6
<> 144:ef7eb2e8f9f7 314 * @arg SYSCFG_FASTMODEPLUS_PB7
<> 144:ef7eb2e8f9f7 315 * @arg SYSCFG_FASTMODEPLUS_PB8
<> 144:ef7eb2e8f9f7 316 * @arg SYSCFG_FASTMODEPLUS_PB9
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
<> 144:ef7eb2e8f9f7 319 SET_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
<> 144:ef7eb2e8f9f7 320 }while(0)
<> 144:ef7eb2e8f9f7 321 /** @brief Fast mode Plus driving capability disable macro
<> 144:ef7eb2e8f9f7 322 * @param __FASTMODEPLUS__: This parameter can be a value of :
<> 144:ef7eb2e8f9f7 323 * @arg SYSCFG_FASTMODEPLUS_PB6
<> 144:ef7eb2e8f9f7 324 * @arg SYSCFG_FASTMODEPLUS_PB7
<> 144:ef7eb2e8f9f7 325 * @arg SYSCFG_FASTMODEPLUS_PB8
<> 144:ef7eb2e8f9f7 326 * @arg SYSCFG_FASTMODEPLUS_PB9
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
<> 144:ef7eb2e8f9f7 329 CLEAR_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
<> 144:ef7eb2e8f9f7 330 }while(0)
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @}
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /** @defgroup HAL_Exported_Functions HAL Exported Functions
<> 144:ef7eb2e8f9f7 338 * @{
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 341 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 342 * @{
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 345 HAL_StatusTypeDef HAL_DeInit(void);
<> 144:ef7eb2e8f9f7 346 void HAL_MspInit(void);
<> 144:ef7eb2e8f9f7 347 void HAL_MspDeInit(void);
<> 144:ef7eb2e8f9f7 348 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 355 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 void HAL_IncTick(void);
<> 144:ef7eb2e8f9f7 359 void HAL_Delay(__IO uint32_t Delay);
<> 144:ef7eb2e8f9f7 360 uint32_t HAL_GetTick(void);
<> 144:ef7eb2e8f9f7 361 void HAL_SuspendTick(void);
<> 144:ef7eb2e8f9f7 362 void HAL_ResumeTick(void);
<> 144:ef7eb2e8f9f7 363 uint32_t HAL_GetHalVersion(void);
<> 144:ef7eb2e8f9f7 364 uint32_t HAL_GetREVID(void);
<> 144:ef7eb2e8f9f7 365 uint32_t HAL_GetDEVID(void);
<> 144:ef7eb2e8f9f7 366 void HAL_DBGMCU_EnableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 367 void HAL_DBGMCU_DisableDBGSleepMode(void);
<> 144:ef7eb2e8f9f7 368 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 369 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 370 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 371 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 372 void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph);
<> 144:ef7eb2e8f9f7 373 void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph);
<> 144:ef7eb2e8f9f7 374 uint32_t HAL_SYSCFG_GetBootMode(void);
<> 144:ef7eb2e8f9f7 375 void HAL_SYSCFG_EnableVREFINT(void);
<> 144:ef7eb2e8f9f7 376 void HAL_SYSCFG_DisableVREFINT(void);
<> 144:ef7eb2e8f9f7 377 void HAL_SYSCFG_Enable_Lock_VREFINT(void);
<> 144:ef7eb2e8f9f7 378 void HAL_SYSCFG_Disable_Lock_VREFINT(void);
<> 144:ef7eb2e8f9f7 379 void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @}
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 389 /**************************************************************/
<> 144:ef7eb2e8f9f7 390 /** @defgroup HAL_Private HAL Private
<> 144:ef7eb2e8f9f7 391 * @{
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 /**************************************************************/
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @}
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @}
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409 #endif
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 #endif /* __STM32L0xx_HAL_H */
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 414