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targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h@144:ef7eb2e8f9f7
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_usart.h
<> 144:ef7eb2e8f9f7 3 * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
<> 144:ef7eb2e8f9f7 4 * peripheral API
<> 144:ef7eb2e8f9f7 5 * @version 4.2.1
<> 144:ef7eb2e8f9f7 6 *******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @section License
<> 144:ef7eb2e8f9f7 8 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 9 *******************************************************************************
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 12 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 13 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 16 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 18 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 19 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 22 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 23 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 24 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 25 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 26 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 29 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 30 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 ******************************************************************************/
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #ifndef __SILICON_LABS_EM_USART_H__
<> 144:ef7eb2e8f9f7 36 #define __SILICON_LABS_EM_USART_H__
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #include "em_device.h"
<> 144:ef7eb2e8f9f7 39 #if defined(USART_COUNT) && (USART_COUNT > 0)
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdbool.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 48 * @addtogroup EM_Library
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 ******************************************************************************/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 53 * @addtogroup USART
<> 144:ef7eb2e8f9f7 54 * @brief Universal Synchronous/Asynchronous Receiver/Transmitter (USART) peripheral API
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 ******************************************************************************/
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /*******************************************************************************
<> 144:ef7eb2e8f9f7 59 ******************************** ENUMS ************************************
<> 144:ef7eb2e8f9f7 60 ******************************************************************************/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** Databit selection. */
<> 144:ef7eb2e8f9f7 63 typedef enum
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 66 usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 67 usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 68 usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 69 usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 databits. */
<> 144:ef7eb2e8f9f7 70 usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 databits. */
<> 144:ef7eb2e8f9f7 71 usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 72 usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 73 usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 74 usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 75 usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 76 usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 77 usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 databits (not available for UART). */
<> 144:ef7eb2e8f9f7 78 } USART_Databits_TypeDef;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** Enable selection. */
<> 144:ef7eb2e8f9f7 82 typedef enum
<> 144:ef7eb2e8f9f7 83 {
<> 144:ef7eb2e8f9f7 84 /** Disable both receiver and transmitter. */
<> 144:ef7eb2e8f9f7 85 usartDisable = 0x0,
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** Enable receiver only, transmitter disabled. */
<> 144:ef7eb2e8f9f7 88 usartEnableRx = USART_CMD_RXEN,
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** Enable transmitter only, receiver disabled. */
<> 144:ef7eb2e8f9f7 91 usartEnableTx = USART_CMD_TXEN,
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /** Enable both receiver and transmitter. */
<> 144:ef7eb2e8f9f7 94 usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
<> 144:ef7eb2e8f9f7 95 } USART_Enable_TypeDef;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** Oversampling selection, used for asynchronous operation. */
<> 144:ef7eb2e8f9f7 99 typedef enum
<> 144:ef7eb2e8f9f7 100 {
<> 144:ef7eb2e8f9f7 101 usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
<> 144:ef7eb2e8f9f7 102 usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
<> 144:ef7eb2e8f9f7 103 usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
<> 144:ef7eb2e8f9f7 104 usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
<> 144:ef7eb2e8f9f7 105 } USART_OVS_TypeDef;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** Parity selection, mainly used for asynchronous operation. */
<> 144:ef7eb2e8f9f7 109 typedef enum
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
<> 144:ef7eb2e8f9f7 112 usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
<> 144:ef7eb2e8f9f7 113 usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
<> 144:ef7eb2e8f9f7 114 } USART_Parity_TypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /** Stopbits selection, used for asynchronous operation. */
<> 144:ef7eb2e8f9f7 118 typedef enum
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stopbits. */
<> 144:ef7eb2e8f9f7 121 usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stopbits. */
<> 144:ef7eb2e8f9f7 122 usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stopbits. */
<> 144:ef7eb2e8f9f7 123 usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stopbits. */
<> 144:ef7eb2e8f9f7 124 } USART_Stopbits_TypeDef;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** Clock polarity/phase mode. */
<> 144:ef7eb2e8f9f7 128 typedef enum
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 /** Clock idle low, sample on rising edge. */
<> 144:ef7eb2e8f9f7 131 usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** Clock idle low, sample on falling edge. */
<> 144:ef7eb2e8f9f7 134 usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING,
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /** Clock idle high, sample on falling edge. */
<> 144:ef7eb2e8f9f7 137 usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING,
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** Clock idle high, sample on rising edge. */
<> 144:ef7eb2e8f9f7 140 usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
<> 144:ef7eb2e8f9f7 141 } USART_ClockMode_TypeDef;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /** Pulse width selection for IrDA mode. */
<> 144:ef7eb2e8f9f7 145 typedef enum
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
<> 144:ef7eb2e8f9f7 148 usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */
<> 144:ef7eb2e8f9f7 151 usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO,
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */
<> 144:ef7eb2e8f9f7 154 usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE,
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */
<> 144:ef7eb2e8f9f7 157 usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
<> 144:ef7eb2e8f9f7 158 } USART_IrDAPw_Typedef;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** PRS channel selection for IrDA mode. */
<> 144:ef7eb2e8f9f7 162 typedef enum
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, /**< PRS channel 0 */
<> 144:ef7eb2e8f9f7 165 usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
<> 144:ef7eb2e8f9f7 166 usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
<> 144:ef7eb2e8f9f7 167 usartIrDAPrsCh3 = USART_IRCTRL_IRPRSSEL_PRSCH3, /**< PRS channel 3 */
<> 144:ef7eb2e8f9f7 168 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH4)
<> 144:ef7eb2e8f9f7 169 usartIrDAPrsCh4 = USART_IRCTRL_IRPRSSEL_PRSCH4, /**< PRS channel 4 */
<> 144:ef7eb2e8f9f7 170 #endif
<> 144:ef7eb2e8f9f7 171 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH5)
<> 144:ef7eb2e8f9f7 172 usartIrDAPrsCh5 = USART_IRCTRL_IRPRSSEL_PRSCH5, /**< PRS channel 5 */
<> 144:ef7eb2e8f9f7 173 #endif
<> 144:ef7eb2e8f9f7 174 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH6)
<> 144:ef7eb2e8f9f7 175 usartIrDAPrsCh6 = USART_IRCTRL_IRPRSSEL_PRSCH6, /**< PRS channel 6 */
<> 144:ef7eb2e8f9f7 176 #endif
<> 144:ef7eb2e8f9f7 177 #if defined(USART_IRCTRL_IRPRSSEL_PRSCH7)
<> 144:ef7eb2e8f9f7 178 usartIrDAPrsCh7 = USART_IRCTRL_IRPRSSEL_PRSCH7, /**< PRS channel 7 */
<> 144:ef7eb2e8f9f7 179 #endif
<> 144:ef7eb2e8f9f7 180 } USART_IrDAPrsSel_Typedef;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 #if defined(_USART_I2SCTRL_MASK)
<> 144:ef7eb2e8f9f7 183 /** I2S format selection. */
<> 144:ef7eb2e8f9f7 184 typedef enum
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data */
<> 144:ef7eb2e8f9f7 187 usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
<> 144:ef7eb2e8f9f7 188 usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data */
<> 144:ef7eb2e8f9f7 189 usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data */
<> 144:ef7eb2e8f9f7 190 usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data */
<> 144:ef7eb2e8f9f7 191 usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data */
<> 144:ef7eb2e8f9f7 192 usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data */
<> 144:ef7eb2e8f9f7 193 usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data */
<> 144:ef7eb2e8f9f7 194 } USART_I2sFormat_TypeDef;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /** I2S frame data justify. */
<> 144:ef7eb2e8f9f7 197 typedef enum
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame */
<> 144:ef7eb2e8f9f7 200 usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame */
<> 144:ef7eb2e8f9f7 201 } USART_I2sJustify_TypeDef;
<> 144:ef7eb2e8f9f7 202 #endif
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 #if defined(_USART_INPUT_MASK)
<> 144:ef7eb2e8f9f7 205 /** USART Rx input PRS selection. */
<> 144:ef7eb2e8f9f7 206 typedef enum
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 usartPrsRxCh0 = USART_INPUT_RXPRSSEL_PRSCH0, /**< PRSCH0 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 209 usartPrsRxCh1 = USART_INPUT_RXPRSSEL_PRSCH1, /**< PRSCH1 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 210 usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 211 usartPrsRxCh3 = USART_INPUT_RXPRSSEL_PRSCH3, /**< PRSCH3 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 #if defined(USART_INPUT_RXPRSSEL_PRSCH7)
<> 144:ef7eb2e8f9f7 214 usartPrsRxCh4 = USART_INPUT_RXPRSSEL_PRSCH4, /**< PRSCH4 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 215 usartPrsRxCh5 = USART_INPUT_RXPRSSEL_PRSCH5, /**< PRSCH5 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 216 usartPrsRxCh6 = USART_INPUT_RXPRSSEL_PRSCH6, /**< PRSCH6 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 217 usartPrsRxCh7 = USART_INPUT_RXPRSSEL_PRSCH7, /**< PRSCH7 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 218 #endif
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #if defined(USART_INPUT_RXPRSSEL_PRSCH11)
<> 144:ef7eb2e8f9f7 221 usartPrsRxCh8 = USART_INPUT_RXPRSSEL_PRSCH8, /**< PRSCH8 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 222 usartPrsRxCh9 = USART_INPUT_RXPRSSEL_PRSCH9, /**< PRSCH9 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 223 usartPrsRxCh10 = USART_INPUT_RXPRSSEL_PRSCH10, /**< PRSCH10 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 224 usartPrsRxCh11 = USART_INPUT_RXPRSSEL_PRSCH11 /**< PRSCH11 selected as USART_INPUT */
<> 144:ef7eb2e8f9f7 225 #endif
<> 144:ef7eb2e8f9f7 226 } USART_PrsRxCh_TypeDef;
<> 144:ef7eb2e8f9f7 227 #endif
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /** USART PRS Transmit Trigger Channels */
<> 144:ef7eb2e8f9f7 230 typedef enum
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 233 usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 234 usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 235 usartPrsTriggerCh3 = USART_TRIGCTRL_TSEL_PRSCH3, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #if defined(USART_TRIGCTRL_TSEL_PRSCH7)
<> 144:ef7eb2e8f9f7 238 usartPrsTriggerCh4 = USART_TRIGCTRL_TSEL_PRSCH4, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 239 usartPrsTriggerCh5 = USART_TRIGCTRL_TSEL_PRSCH5, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 240 usartPrsTriggerCh6 = USART_TRIGCTRL_TSEL_PRSCH6, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 241 usartPrsTriggerCh7 = USART_TRIGCTRL_TSEL_PRSCH7, /**< PRSCH0 selected as USART Trigger */
<> 144:ef7eb2e8f9f7 242 #endif
<> 144:ef7eb2e8f9f7 243 } USART_PrsTriggerCh_TypeDef;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /*******************************************************************************
<> 144:ef7eb2e8f9f7 246 ******************************* STRUCTS ***********************************
<> 144:ef7eb2e8f9f7 247 ******************************************************************************/
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /** Asynchronous mode init structure. */
<> 144:ef7eb2e8f9f7 250 typedef struct
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 /** Specifies whether TX and/or RX shall be enabled when init completed. */
<> 144:ef7eb2e8f9f7 253 USART_Enable_TypeDef enable;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * USART/UART reference clock assumed when configuring baudrate setup. Set
<> 144:ef7eb2e8f9f7 257 * it to 0 if currently configurated reference clock shall be used.
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 uint32_t refFreq;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /** Desired baudrate. */
<> 144:ef7eb2e8f9f7 262 uint32_t baudrate;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /** Oversampling used. */
<> 144:ef7eb2e8f9f7 265 USART_OVS_TypeDef oversampling;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** Number of databits in frame. Notice that UART modules only support 8 or
<> 144:ef7eb2e8f9f7 268 * 9 databits. */
<> 144:ef7eb2e8f9f7 269 USART_Databits_TypeDef databits;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /** Parity mode to use. */
<> 144:ef7eb2e8f9f7 272 USART_Parity_TypeDef parity;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /** Number of stopbits to use. */
<> 144:ef7eb2e8f9f7 275 USART_Stopbits_TypeDef stopbits;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 #if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
<> 144:ef7eb2e8f9f7 278 /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */
<> 144:ef7eb2e8f9f7 279 bool mvdis;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /** Enable USART Rx via PRS. */
<> 144:ef7eb2e8f9f7 282 bool prsRxEnable;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
<> 144:ef7eb2e8f9f7 285 USART_PrsRxCh_TypeDef prsRxCh;
<> 144:ef7eb2e8f9f7 286 #endif
<> 144:ef7eb2e8f9f7 287 #if defined(_USART_TIMING_CSHOLD_MASK)
<> 144:ef7eb2e8f9f7 288 /** Auto CS enabling */
<> 144:ef7eb2e8f9f7 289 bool autoCsEnable;
<> 144:ef7eb2e8f9f7 290 /** Auto CS hold time in baud cycles */
<> 144:ef7eb2e8f9f7 291 uint8_t autoCsHold;
<> 144:ef7eb2e8f9f7 292 /** Auto CS setup time in baud cycles */
<> 144:ef7eb2e8f9f7 293 uint8_t autoCsSetup;
<> 144:ef7eb2e8f9f7 294 #endif
<> 144:ef7eb2e8f9f7 295 } USART_InitAsync_TypeDef;
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /** USART PRS trigger enable */
<> 144:ef7eb2e8f9f7 298 typedef struct
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 #if defined(USART_TRIGCTRL_AUTOTXTEN)
<> 144:ef7eb2e8f9f7 301 /** Enable AUTOTX */
<> 144:ef7eb2e8f9f7 302 bool autoTxTriggerEnable;
<> 144:ef7eb2e8f9f7 303 #endif
<> 144:ef7eb2e8f9f7 304 /** Trigger receive via PRS channel */
<> 144:ef7eb2e8f9f7 305 bool rxTriggerEnable;
<> 144:ef7eb2e8f9f7 306 /** Trigger transmit via PRS channel */
<> 144:ef7eb2e8f9f7 307 bool txTriggerEnable;
<> 144:ef7eb2e8f9f7 308 /** PRS channel to be used to trigger auto transmission */
<> 144:ef7eb2e8f9f7 309 USART_PrsTriggerCh_TypeDef prsTriggerChannel;
<> 144:ef7eb2e8f9f7 310 } USART_PrsTriggerInit_TypeDef;
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /** Default config for USART async init structure. */
<> 144:ef7eb2e8f9f7 313 #if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
<> 144:ef7eb2e8f9f7 314 #define USART_INITASYNC_DEFAULT \
<> 144:ef7eb2e8f9f7 315 { \
<> 144:ef7eb2e8f9f7 316 usartEnable, /* Enable RX/TX when init completed. */ \
<> 144:ef7eb2e8f9f7 317 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 318 115200, /* 115200 bits/s. */ \
<> 144:ef7eb2e8f9f7 319 usartOVS16, /* 16x oversampling. */ \
<> 144:ef7eb2e8f9f7 320 usartDatabits8, /* 8 databits. */ \
<> 144:ef7eb2e8f9f7 321 usartNoParity, /* No parity. */ \
<> 144:ef7eb2e8f9f7 322 usartStopbits1, /* 1 stopbit. */ \
<> 144:ef7eb2e8f9f7 323 false, /* Do not disable majority vote. */ \
<> 144:ef7eb2e8f9f7 324 false, /* Not USART PRS input mode. */ \
<> 144:ef7eb2e8f9f7 325 usartPrsRxCh0, /* PRS channel 0. */ \
<> 144:ef7eb2e8f9f7 326 false, /* Auto CS functionality enable/disable switch */ \
<> 144:ef7eb2e8f9f7 327 0, /* Auto CS Hold cycles */ \
<> 144:ef7eb2e8f9f7 328 0 /* Auto CS Setup cycles */ \
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330 #elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
<> 144:ef7eb2e8f9f7 331 #define USART_INITASYNC_DEFAULT \
<> 144:ef7eb2e8f9f7 332 { \
<> 144:ef7eb2e8f9f7 333 usartEnable, /* Enable RX/TX when init completed. */ \
<> 144:ef7eb2e8f9f7 334 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 335 115200, /* 115200 bits/s. */ \
<> 144:ef7eb2e8f9f7 336 usartOVS16, /* 16x oversampling. */ \
<> 144:ef7eb2e8f9f7 337 usartDatabits8, /* 8 databits. */ \
<> 144:ef7eb2e8f9f7 338 usartNoParity, /* No parity. */ \
<> 144:ef7eb2e8f9f7 339 usartStopbits1, /* 1 stopbit. */ \
<> 144:ef7eb2e8f9f7 340 false, /* Do not disable majority vote. */ \
<> 144:ef7eb2e8f9f7 341 false, /* Not USART PRS input mode. */ \
<> 144:ef7eb2e8f9f7 342 usartPrsRxCh0 /* PRS channel 0. */ \
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 #else
<> 144:ef7eb2e8f9f7 345 #define USART_INITASYNC_DEFAULT \
<> 144:ef7eb2e8f9f7 346 { \
<> 144:ef7eb2e8f9f7 347 usartEnable, /* Enable RX/TX when init completed. */ \
<> 144:ef7eb2e8f9f7 348 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 349 115200, /* 115200 bits/s. */ \
<> 144:ef7eb2e8f9f7 350 usartOVS16, /* 16x oversampling. */ \
<> 144:ef7eb2e8f9f7 351 usartDatabits8, /* 8 databits. */ \
<> 144:ef7eb2e8f9f7 352 usartNoParity, /* No parity. */ \
<> 144:ef7eb2e8f9f7 353 usartStopbits1 /* 1 stopbit. */ \
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355 #endif
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** Default config for USART PRS triggering structure. */
<> 144:ef7eb2e8f9f7 358 #if defined(USART_TRIGCTRL_AUTOTXTEN)
<> 144:ef7eb2e8f9f7 359 #define USART_INITPRSTRIGGER_DEFAULT \
<> 144:ef7eb2e8f9f7 360 { \
<> 144:ef7eb2e8f9f7 361 false, /* Do not enable autoTX triggering. */ \
<> 144:ef7eb2e8f9f7 362 false, /* Do not enable receive triggering. */ \
<> 144:ef7eb2e8f9f7 363 false, /* Do not enable transmit triggering. */ \
<> 144:ef7eb2e8f9f7 364 usartPrsTriggerCh0 /* Set default channel to zero. */ \
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366 #else
<> 144:ef7eb2e8f9f7 367 #define USART_INITPRSTRIGGER_DEFAULT \
<> 144:ef7eb2e8f9f7 368 { \
<> 144:ef7eb2e8f9f7 369 false, /* Do not enable receive triggering. */ \
<> 144:ef7eb2e8f9f7 370 false, /* Do not enable transmit triggering. */ \
<> 144:ef7eb2e8f9f7 371 usartPrsTriggerCh0 /* Set default channel to zero. */ \
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373 #endif
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** Synchronous mode init structure. */
<> 144:ef7eb2e8f9f7 376 typedef struct
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 /** Specifies whether TX and/or RX shall be enabled when init completed. */
<> 144:ef7eb2e8f9f7 379 USART_Enable_TypeDef enable;
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * USART/UART reference clock assumed when configuring baudrate setup. Set
<> 144:ef7eb2e8f9f7 383 * it to 0 if currently configurated reference clock shall be used.
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385 uint32_t refFreq;
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /** Desired baudrate. */
<> 144:ef7eb2e8f9f7 388 uint32_t baudrate;
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /** Number of databits in frame. */
<> 144:ef7eb2e8f9f7 391 USART_Databits_TypeDef databits;
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /** Select if to operate in master or slave mode. */
<> 144:ef7eb2e8f9f7 394 bool master;
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /** Select if to send most or least significant bit first. */
<> 144:ef7eb2e8f9f7 397 bool msbf;
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /** Clock polarity/phase mode. */
<> 144:ef7eb2e8f9f7 400 USART_ClockMode_TypeDef clockMode;
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 #if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
<> 144:ef7eb2e8f9f7 403 /** Enable USART Rx via PRS. */
<> 144:ef7eb2e8f9f7 404 bool prsRxEnable;
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
<> 144:ef7eb2e8f9f7 407 USART_PrsRxCh_TypeDef prsRxCh;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /** Enable AUTOTX mode. Transmits as long as RX is not full.
<> 144:ef7eb2e8f9f7 410 * If TX is empty, underflows are generated. */
<> 144:ef7eb2e8f9f7 411 bool autoTx;
<> 144:ef7eb2e8f9f7 412 #endif
<> 144:ef7eb2e8f9f7 413 #if defined(_USART_TIMING_CSHOLD_MASK)
<> 144:ef7eb2e8f9f7 414 /** Auto CS enabling */
<> 144:ef7eb2e8f9f7 415 bool autoCsEnable;
<> 144:ef7eb2e8f9f7 416 /** Auto CS hold time in baud cycles */
<> 144:ef7eb2e8f9f7 417 uint8_t autoCsHold;
<> 144:ef7eb2e8f9f7 418 /** Auto CS setup time in baud cycles */
<> 144:ef7eb2e8f9f7 419 uint8_t autoCsSetup;
<> 144:ef7eb2e8f9f7 420 #endif
<> 144:ef7eb2e8f9f7 421 } USART_InitSync_TypeDef;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /** Default config for USART sync init structure. */
<> 144:ef7eb2e8f9f7 424 #if defined(_USART_TIMING_CSHOLD_MASK)
<> 144:ef7eb2e8f9f7 425 #define USART_INITSYNC_DEFAULT \
<> 144:ef7eb2e8f9f7 426 { \
<> 144:ef7eb2e8f9f7 427 usartEnable, /* Enable RX/TX when init completed. */ \
<> 144:ef7eb2e8f9f7 428 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 429 1000000, /* 1 Mbits/s. */ \
<> 144:ef7eb2e8f9f7 430 usartDatabits8, /* 8 databits. */ \
<> 144:ef7eb2e8f9f7 431 true, /* Master mode. */ \
<> 144:ef7eb2e8f9f7 432 false, /* Send least significant bit first. */ \
<> 144:ef7eb2e8f9f7 433 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
<> 144:ef7eb2e8f9f7 434 false, /* Not USART PRS input mode. */ \
<> 144:ef7eb2e8f9f7 435 usartPrsRxCh0, /* PRS channel 0. */ \
<> 144:ef7eb2e8f9f7 436 false, /* No AUTOTX mode. */ \
<> 144:ef7eb2e8f9f7 437 false, /* No AUTOCS mode */ \
<> 144:ef7eb2e8f9f7 438 0, /* Auto CS Hold cycles */ \
<> 144:ef7eb2e8f9f7 439 0 /* Auto CS Setup cycles */ \
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441 #elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
<> 144:ef7eb2e8f9f7 442 #define USART_INITSYNC_DEFAULT \
<> 144:ef7eb2e8f9f7 443 { \
<> 144:ef7eb2e8f9f7 444 usartEnable, /* Enable RX/TX when init completed. */ \
<> 144:ef7eb2e8f9f7 445 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 446 1000000, /* 1 Mbits/s. */ \
<> 144:ef7eb2e8f9f7 447 usartDatabits8, /* 8 databits. */ \
<> 144:ef7eb2e8f9f7 448 true, /* Master mode. */ \
<> 144:ef7eb2e8f9f7 449 false, /* Send least significant bit first. */ \
<> 144:ef7eb2e8f9f7 450 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
<> 144:ef7eb2e8f9f7 451 false, /* Not USART PRS input mode. */ \
<> 144:ef7eb2e8f9f7 452 usartPrsRxCh0, /* PRS channel 0. */ \
<> 144:ef7eb2e8f9f7 453 false /* No AUTOTX mode. */ \
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455 #else
<> 144:ef7eb2e8f9f7 456 #define USART_INITSYNC_DEFAULT \
<> 144:ef7eb2e8f9f7 457 { \
<> 144:ef7eb2e8f9f7 458 usartEnable, /* Enable RX/TX when init completed. */ \
<> 144:ef7eb2e8f9f7 459 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 460 1000000, /* 1 Mbits/s. */ \
<> 144:ef7eb2e8f9f7 461 usartDatabits8, /* 8 databits. */ \
<> 144:ef7eb2e8f9f7 462 true, /* Master mode. */ \
<> 144:ef7eb2e8f9f7 463 false, /* Send least significant bit first. */ \
<> 144:ef7eb2e8f9f7 464 usartClockMode0 /* Clock idle low, sample on rising edge. */ \
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 #endif
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** IrDA mode init structure. Inherited from asynchronous mode init structure */
<> 144:ef7eb2e8f9f7 470 typedef struct
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 /** General Async initialization structure. */
<> 144:ef7eb2e8f9f7 473 USART_InitAsync_TypeDef async;
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /** Set to invert Rx signal before IrDA demodulator. */
<> 144:ef7eb2e8f9f7 476 bool irRxInv;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /** Set to enable filter on IrDA demodulator. */
<> 144:ef7eb2e8f9f7 479 bool irFilt;
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /** Configure the pulse width generated by the IrDA modulator as a fraction
<> 144:ef7eb2e8f9f7 482 * of the configured USART bit period. */
<> 144:ef7eb2e8f9f7 483 USART_IrDAPw_Typedef irPw;
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /** Enable the PRS channel selected by irPrsSel as input to IrDA module
<> 144:ef7eb2e8f9f7 486 * instead of TX. */
<> 144:ef7eb2e8f9f7 487 bool irPrsEn;
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /** A PRS can be used as input to the pulse modulator instead of TX.
<> 144:ef7eb2e8f9f7 490 * This value selects the channel to use. */
<> 144:ef7eb2e8f9f7 491 USART_IrDAPrsSel_Typedef irPrsSel;
<> 144:ef7eb2e8f9f7 492 } USART_InitIrDA_TypeDef;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /** Default config for IrDA mode init structure. */
<> 144:ef7eb2e8f9f7 496 #define USART_INITIRDA_DEFAULT \
<> 144:ef7eb2e8f9f7 497 { \
<> 144:ef7eb2e8f9f7 498 { \
<> 144:ef7eb2e8f9f7 499 usartEnable, /* Enable RX/TX when init completed. */ \
<> 144:ef7eb2e8f9f7 500 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 501 115200, /* 115200 bits/s. */ \
<> 144:ef7eb2e8f9f7 502 usartOVS16, /* 16x oversampling. */ \
<> 144:ef7eb2e8f9f7 503 usartDatabits8, /* 8 databits. */ \
<> 144:ef7eb2e8f9f7 504 usartEvenParity, /* Even parity. */ \
<> 144:ef7eb2e8f9f7 505 usartStopbits1 /* 1 stopbit. */ \
<> 144:ef7eb2e8f9f7 506 }, \
<> 144:ef7eb2e8f9f7 507 false, /* Rx invert disabled. */ \
<> 144:ef7eb2e8f9f7 508 false, /* Filtering disabled. */ \
<> 144:ef7eb2e8f9f7 509 usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
<> 144:ef7eb2e8f9f7 510 false, /* Routing to PRS is disabled. */ \
<> 144:ef7eb2e8f9f7 511 usartIrDAPrsCh0 /* PRS channel 0. */ \
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 #if defined(_USART_I2SCTRL_MASK)
<> 144:ef7eb2e8f9f7 516 /** I2S mode init structure. Inherited from synchronous mode init structure */
<> 144:ef7eb2e8f9f7 517 typedef struct
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 /** General Sync initialization structure. */
<> 144:ef7eb2e8f9f7 520 USART_InitSync_TypeDef sync;
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /** I2S mode. */
<> 144:ef7eb2e8f9f7 523 USART_I2sFormat_TypeDef format;
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /** Delay on I2S data. Set to add a one-cycle delay between a transition
<> 144:ef7eb2e8f9f7 526 * on the word-clock and the start of the I2S word.
<> 144:ef7eb2e8f9f7 527 * Should be set for standard I2S format. */
<> 144:ef7eb2e8f9f7 528 bool delay;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /** Separate DMA Request For Left/Right Data. */
<> 144:ef7eb2e8f9f7 531 bool dmaSplit;
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /** Justification of I2S data within the frame */
<> 144:ef7eb2e8f9f7 534 USART_I2sJustify_TypeDef justify;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /** Stero or Mono, set to true for mono. */
<> 144:ef7eb2e8f9f7 537 bool mono;
<> 144:ef7eb2e8f9f7 538 } USART_InitI2s_TypeDef;
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /** Default config for I2S mode init structure. */
<> 144:ef7eb2e8f9f7 542 #define USART_INITI2S_DEFAULT \
<> 144:ef7eb2e8f9f7 543 { \
<> 144:ef7eb2e8f9f7 544 { \
<> 144:ef7eb2e8f9f7 545 usartEnableTx, /* Enable TX when init completed. */ \
<> 144:ef7eb2e8f9f7 546 0, /* Use current configured reference clock for configuring baudrate. */ \
<> 144:ef7eb2e8f9f7 547 1000000, /* Baudrate 1M bits/s. */ \
<> 144:ef7eb2e8f9f7 548 usartDatabits16, /* 16 databits. */ \
<> 144:ef7eb2e8f9f7 549 true, /* Operate as I2S master. */ \
<> 144:ef7eb2e8f9f7 550 true, /* Most significant bit first. */ \
<> 144:ef7eb2e8f9f7 551 usartClockMode0, /* Clock idle low, sample on rising edge. */ \
<> 144:ef7eb2e8f9f7 552 false, /* Don't enable USARTRx via PRS. */ \
<> 144:ef7eb2e8f9f7 553 usartPrsRxCh0, /* PRS channel selection (dummy). */ \
<> 144:ef7eb2e8f9f7 554 false /* Disable AUTOTX mode. */ \
<> 144:ef7eb2e8f9f7 555 }, \
<> 144:ef7eb2e8f9f7 556 usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
<> 144:ef7eb2e8f9f7 557 true, /* Delay on I2S data. */ \
<> 144:ef7eb2e8f9f7 558 false, /* No DMA split. */ \
<> 144:ef7eb2e8f9f7 559 usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
<> 144:ef7eb2e8f9f7 560 false /* Stereo mode. */ \
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562 #endif
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /*******************************************************************************
<> 144:ef7eb2e8f9f7 565 ***************************** PROTOTYPES **********************************
<> 144:ef7eb2e8f9f7 566 ******************************************************************************/
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 void USART_BaudrateAsyncSet(USART_TypeDef *usart,
<> 144:ef7eb2e8f9f7 569 uint32_t refFreq,
<> 144:ef7eb2e8f9f7 570 uint32_t baudrate,
<> 144:ef7eb2e8f9f7 571 USART_OVS_TypeDef ovs);
<> 144:ef7eb2e8f9f7 572 uint32_t USART_BaudrateCalc(uint32_t refFreq,
<> 144:ef7eb2e8f9f7 573 uint32_t clkdiv,
<> 144:ef7eb2e8f9f7 574 bool syncmode,
<> 144:ef7eb2e8f9f7 575 USART_OVS_TypeDef ovs);
<> 144:ef7eb2e8f9f7 576 uint32_t USART_BaudrateGet(USART_TypeDef *usart);
<> 144:ef7eb2e8f9f7 577 void USART_BaudrateSyncSet(USART_TypeDef *usart,
<> 144:ef7eb2e8f9f7 578 uint32_t refFreq,
<> 144:ef7eb2e8f9f7 579 uint32_t baudrate);
<> 144:ef7eb2e8f9f7 580 void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);
<> 144:ef7eb2e8f9f7 583 void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);
<> 144:ef7eb2e8f9f7 584 #if defined(USART0) || ((USART_COUNT == 1) && defined(USART1))
<> 144:ef7eb2e8f9f7 585 void USART_InitIrDA(const USART_InitIrDA_TypeDef *init);
<> 144:ef7eb2e8f9f7 586 #endif
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #if defined(_USART_I2SCTRL_MASK)
<> 144:ef7eb2e8f9f7 589 void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);
<> 144:ef7eb2e8f9f7 590 #endif
<> 144:ef7eb2e8f9f7 591 void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 595 * @brief
<> 144:ef7eb2e8f9f7 596 * Clear one or more pending USART interrupts.
<> 144:ef7eb2e8f9f7 597 *
<> 144:ef7eb2e8f9f7 598 * @param[in] usart
<> 144:ef7eb2e8f9f7 599 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 600 *
<> 144:ef7eb2e8f9f7 601 * @param[in] flags
<> 144:ef7eb2e8f9f7 602 * Pending USART/UART interrupt source(s) to clear. Use one or more valid
<> 144:ef7eb2e8f9f7 603 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
<> 144:ef7eb2e8f9f7 604 ******************************************************************************/
<> 144:ef7eb2e8f9f7 605 __STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags)
<> 144:ef7eb2e8f9f7 606 {
<> 144:ef7eb2e8f9f7 607 usart->IFC = flags;
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 612 * @brief
<> 144:ef7eb2e8f9f7 613 * Disable one or more USART interrupts.
<> 144:ef7eb2e8f9f7 614 *
<> 144:ef7eb2e8f9f7 615 * @param[in] usart
<> 144:ef7eb2e8f9f7 616 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 617 *
<> 144:ef7eb2e8f9f7 618 * @param[in] flags
<> 144:ef7eb2e8f9f7 619 * USART/UART interrupt source(s) to disable. Use one or more valid
<> 144:ef7eb2e8f9f7 620 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
<> 144:ef7eb2e8f9f7 621 ******************************************************************************/
<> 144:ef7eb2e8f9f7 622 __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 usart->IEN &= ~flags;
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 629 * @brief
<> 144:ef7eb2e8f9f7 630 * Enable one or more USART interrupts.
<> 144:ef7eb2e8f9f7 631 *
<> 144:ef7eb2e8f9f7 632 * @note
<> 144:ef7eb2e8f9f7 633 * Depending on the use, a pending interrupt may already be set prior to
<> 144:ef7eb2e8f9f7 634 * enabling the interrupt. Consider using USART_IntClear() prior to enabling
<> 144:ef7eb2e8f9f7 635 * if such a pending interrupt should be ignored.
<> 144:ef7eb2e8f9f7 636 *
<> 144:ef7eb2e8f9f7 637 * @param[in] usart
<> 144:ef7eb2e8f9f7 638 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 639 *
<> 144:ef7eb2e8f9f7 640 * @param[in] flags
<> 144:ef7eb2e8f9f7 641 * USART/UART interrupt source(s) to enable. Use one or more valid
<> 144:ef7eb2e8f9f7 642 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
<> 144:ef7eb2e8f9f7 643 ******************************************************************************/
<> 144:ef7eb2e8f9f7 644 __STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 usart->IEN |= flags;
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 651 * @brief
<> 144:ef7eb2e8f9f7 652 * Get pending USART interrupt flags.
<> 144:ef7eb2e8f9f7 653 *
<> 144:ef7eb2e8f9f7 654 * @note
<> 144:ef7eb2e8f9f7 655 * The event bits are not cleared by the use of this function.
<> 144:ef7eb2e8f9f7 656 *
<> 144:ef7eb2e8f9f7 657 * @param[in] usart
<> 144:ef7eb2e8f9f7 658 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 659 *
<> 144:ef7eb2e8f9f7 660 * @return
<> 144:ef7eb2e8f9f7 661 * USART/UART interrupt source(s) pending. Returns one or more valid
<> 144:ef7eb2e8f9f7 662 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
<> 144:ef7eb2e8f9f7 663 ******************************************************************************/
<> 144:ef7eb2e8f9f7 664 __STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 return usart->IF;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 671 * @brief
<> 144:ef7eb2e8f9f7 672 * Get enabled and pending USART interrupt flags.
<> 144:ef7eb2e8f9f7 673 * Useful for handling more interrupt sources in the same interrupt handler.
<> 144:ef7eb2e8f9f7 674 *
<> 144:ef7eb2e8f9f7 675 * @param[in] usart
<> 144:ef7eb2e8f9f7 676 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 677 *
<> 144:ef7eb2e8f9f7 678 * @note
<> 144:ef7eb2e8f9f7 679 * Interrupt flags are not cleared by the use of this function.
<> 144:ef7eb2e8f9f7 680 *
<> 144:ef7eb2e8f9f7 681 * @return
<> 144:ef7eb2e8f9f7 682 * Pending and enabled USART interrupt sources.
<> 144:ef7eb2e8f9f7 683 * The return value is the bitwise AND combination of
<> 144:ef7eb2e8f9f7 684 * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn
<> 144:ef7eb2e8f9f7 685 * register (USARTx_IEN_nnn) and
<> 144:ef7eb2e8f9f7 686 * - the OR combination of valid interrupt flags of the USART module
<> 144:ef7eb2e8f9f7 687 * (USARTx_IF_nnn).
<> 144:ef7eb2e8f9f7 688 ******************************************************************************/
<> 144:ef7eb2e8f9f7 689 __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
<> 144:ef7eb2e8f9f7 690 {
<> 144:ef7eb2e8f9f7 691 uint32_t ien;
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Store USARTx->IEN in temporary variable in order to define explicit order
<> 144:ef7eb2e8f9f7 694 * of volatile accesses. */
<> 144:ef7eb2e8f9f7 695 ien = usart->IEN;
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Bitwise AND of pending and enabled interrupts */
<> 144:ef7eb2e8f9f7 698 return usart->IF & ien;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 703 * @brief
<> 144:ef7eb2e8f9f7 704 * Set one or more pending USART interrupts from SW.
<> 144:ef7eb2e8f9f7 705 *
<> 144:ef7eb2e8f9f7 706 * @param[in] usart
<> 144:ef7eb2e8f9f7 707 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 708 *
<> 144:ef7eb2e8f9f7 709 * @param[in] flags
<> 144:ef7eb2e8f9f7 710 * USART/UART interrupt source(s) to set to pending. Use one or more valid
<> 144:ef7eb2e8f9f7 711 * interrupt flags for the USART module (USART_IF_nnn) OR'ed together.
<> 144:ef7eb2e8f9f7 712 ******************************************************************************/
<> 144:ef7eb2e8f9f7 713 __STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 usart->IFS = flags;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 720 * @brief
<> 144:ef7eb2e8f9f7 721 * Get USART STATUS register.
<> 144:ef7eb2e8f9f7 722 *
<> 144:ef7eb2e8f9f7 723 * @param[in] usart
<> 144:ef7eb2e8f9f7 724 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 725 *
<> 144:ef7eb2e8f9f7 726 * @return
<> 144:ef7eb2e8f9f7 727 * STATUS register value.
<> 144:ef7eb2e8f9f7 728 *
<> 144:ef7eb2e8f9f7 729 ******************************************************************************/
<> 144:ef7eb2e8f9f7 730 __STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 return usart->STATUS;
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 void USART_Reset(USART_TypeDef *usart);
<> 144:ef7eb2e8f9f7 736 uint8_t USART_Rx(USART_TypeDef *usart);
<> 144:ef7eb2e8f9f7 737 uint16_t USART_RxDouble(USART_TypeDef *usart);
<> 144:ef7eb2e8f9f7 738 uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
<> 144:ef7eb2e8f9f7 739 uint16_t USART_RxExt(USART_TypeDef *usart);
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 743 * @brief
<> 144:ef7eb2e8f9f7 744 * Receive one 4-8 bit frame, (or part of 10-16 bit frame).
<> 144:ef7eb2e8f9f7 745 *
<> 144:ef7eb2e8f9f7 746 * @details
<> 144:ef7eb2e8f9f7 747 * This function is used to quickly receive one 4-8 bits frame by reading the
<> 144:ef7eb2e8f9f7 748 * RXDATA register directly, without checking the STATUS register for the
<> 144:ef7eb2e8f9f7 749 * RXDATAV flag. This can be useful from the RXDATAV interrupt handler,
<> 144:ef7eb2e8f9f7 750 * i.e. waiting is superfluous, in order to quickly read the received data.
<> 144:ef7eb2e8f9f7 751 * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames.
<> 144:ef7eb2e8f9f7 752 *
<> 144:ef7eb2e8f9f7 753 * @note
<> 144:ef7eb2e8f9f7 754 * Since this function does not check whether the RXDATA register actually
<> 144:ef7eb2e8f9f7 755 * holds valid data, it should only be used in situations when it is certain
<> 144:ef7eb2e8f9f7 756 * that there is valid data, ensured by some external program routine, e.g.
<> 144:ef7eb2e8f9f7 757 * like when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a
<> 144:ef7eb2e8f9f7 758 * better choice if the validity of the RXDATA register is not certain.
<> 144:ef7eb2e8f9f7 759 *
<> 144:ef7eb2e8f9f7 760 * @note
<> 144:ef7eb2e8f9f7 761 * Notice that possible parity/stop bits in asynchronous mode are not
<> 144:ef7eb2e8f9f7 762 * considered part of specified frame bit length.
<> 144:ef7eb2e8f9f7 763 *
<> 144:ef7eb2e8f9f7 764 * @param[in] usart
<> 144:ef7eb2e8f9f7 765 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 766 *
<> 144:ef7eb2e8f9f7 767 * @return
<> 144:ef7eb2e8f9f7 768 * Data received.
<> 144:ef7eb2e8f9f7 769 ******************************************************************************/
<> 144:ef7eb2e8f9f7 770 __STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 return (uint8_t)usart->RXDATA;
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 777 * @brief
<> 144:ef7eb2e8f9f7 778 * Receive two 4-8 bit frames, or one 10-16 bit frame.
<> 144:ef7eb2e8f9f7 779 *
<> 144:ef7eb2e8f9f7 780 * @details
<> 144:ef7eb2e8f9f7 781 * This function is used to quickly receive one 10-16 bits frame or two 4-8
<> 144:ef7eb2e8f9f7 782 * bit frames by reading the RXDOUBLE register directly, without checking
<> 144:ef7eb2e8f9f7 783 * the STATUS register for the RXDATAV flag. This can be useful from the
<> 144:ef7eb2e8f9f7 784 * RXDATAV interrupt handler, i.e. waiting is superfluous, in order to
<> 144:ef7eb2e8f9f7 785 * quickly read the received data.
<> 144:ef7eb2e8f9f7 786 * This function is normally used to receive one frame when operating with
<> 144:ef7eb2e8f9f7 787 * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet()
<> 144:ef7eb2e8f9f7 788 * for reception of two 9 bit frames.
<> 144:ef7eb2e8f9f7 789 *
<> 144:ef7eb2e8f9f7 790 * @note
<> 144:ef7eb2e8f9f7 791 * Since this function does not check whether the RXDOUBLE register actually
<> 144:ef7eb2e8f9f7 792 * holds valid data, it should only be used in situations when it is certain
<> 144:ef7eb2e8f9f7 793 * that there is valid data, ensured by some external program routine, e.g.
<> 144:ef7eb2e8f9f7 794 * like when handling an RXDATAV interrupt. The @ref USART_RxDouble() is
<> 144:ef7eb2e8f9f7 795 * normally a better choice if the validity of the RXDOUBLE register is not
<> 144:ef7eb2e8f9f7 796 * certain.
<> 144:ef7eb2e8f9f7 797 *
<> 144:ef7eb2e8f9f7 798 * @note
<> 144:ef7eb2e8f9f7 799 * Notice that possible parity/stop bits in asynchronous mode are not
<> 144:ef7eb2e8f9f7 800 * considered part of specified frame bit length.
<> 144:ef7eb2e8f9f7 801 *
<> 144:ef7eb2e8f9f7 802 * @param[in] usart
<> 144:ef7eb2e8f9f7 803 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 804 *
<> 144:ef7eb2e8f9f7 805 * @return
<> 144:ef7eb2e8f9f7 806 * Data received.
<> 144:ef7eb2e8f9f7 807 ******************************************************************************/
<> 144:ef7eb2e8f9f7 808 __STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 return (uint16_t)usart->RXDOUBLE;
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 815 * @brief
<> 144:ef7eb2e8f9f7 816 * Receive two 4-9 bit frames, or one 10-16 bit frame with extended
<> 144:ef7eb2e8f9f7 817 * information.
<> 144:ef7eb2e8f9f7 818 *
<> 144:ef7eb2e8f9f7 819 * @details
<> 144:ef7eb2e8f9f7 820 * This function is used to quickly receive one 10-16 bits frame or two 4-9
<> 144:ef7eb2e8f9f7 821 * bit frames by reading the RXDOUBLEX register directly, without checking
<> 144:ef7eb2e8f9f7 822 * the STATUS register for the RXDATAV flag. This can be useful from the
<> 144:ef7eb2e8f9f7 823 * RXDATAV interrupt handler, i.e. waiting is superfluous, in order to
<> 144:ef7eb2e8f9f7 824 * quickly read the received data.
<> 144:ef7eb2e8f9f7 825 *
<> 144:ef7eb2e8f9f7 826 * @note
<> 144:ef7eb2e8f9f7 827 * Since this function does not check whether the RXDOUBLEX register actually
<> 144:ef7eb2e8f9f7 828 * holds valid data, it should only be used in situations when it is certain
<> 144:ef7eb2e8f9f7 829 * that there is valid data, ensured by some external program routine, e.g.
<> 144:ef7eb2e8f9f7 830 * like when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is
<> 144:ef7eb2e8f9f7 831 * normally a better choice if the validity of the RXDOUBLEX register is not
<> 144:ef7eb2e8f9f7 832 * certain.
<> 144:ef7eb2e8f9f7 833 *
<> 144:ef7eb2e8f9f7 834 * @note
<> 144:ef7eb2e8f9f7 835 * Notice that possible parity/stop bits in asynchronous mode are not
<> 144:ef7eb2e8f9f7 836 * considered part of specified frame bit length.
<> 144:ef7eb2e8f9f7 837 *
<> 144:ef7eb2e8f9f7 838 * @param[in] usart
<> 144:ef7eb2e8f9f7 839 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 840 *
<> 144:ef7eb2e8f9f7 841 * @return
<> 144:ef7eb2e8f9f7 842 * Data received.
<> 144:ef7eb2e8f9f7 843 ******************************************************************************/
<> 144:ef7eb2e8f9f7 844 __STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 return usart->RXDOUBLEX;
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 851 * @brief
<> 144:ef7eb2e8f9f7 852 * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
<> 144:ef7eb2e8f9f7 853 * information.
<> 144:ef7eb2e8f9f7 854 *
<> 144:ef7eb2e8f9f7 855 * @details
<> 144:ef7eb2e8f9f7 856 * This function is used to quickly receive one 4-9 bit frame, (or part of
<> 144:ef7eb2e8f9f7 857 * 10-16 bit frame) with extended information by reading the RXDATAX register
<> 144:ef7eb2e8f9f7 858 * directly, without checking the STATUS register for the RXDATAV flag. This
<> 144:ef7eb2e8f9f7 859 * can be useful from the RXDATAV interrupt handler, i.e. waiting is
<> 144:ef7eb2e8f9f7 860 * superfluous, in order to quickly read the received data.
<> 144:ef7eb2e8f9f7 861 *
<> 144:ef7eb2e8f9f7 862 * @note
<> 144:ef7eb2e8f9f7 863 * Since this function does not check whether the RXDATAX register actually
<> 144:ef7eb2e8f9f7 864 * holds valid data, it should only be used in situations when it is certain
<> 144:ef7eb2e8f9f7 865 * that there is valid data, ensured by some external program routine, e.g.
<> 144:ef7eb2e8f9f7 866 * like when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally
<> 144:ef7eb2e8f9f7 867 * a better choice if the validity of the RXDATAX register is not certain.
<> 144:ef7eb2e8f9f7 868 *
<> 144:ef7eb2e8f9f7 869 * @note
<> 144:ef7eb2e8f9f7 870 * Notice that possible parity/stop bits in asynchronous mode are not
<> 144:ef7eb2e8f9f7 871 * considered part of specified frame bit length.
<> 144:ef7eb2e8f9f7 872 *
<> 144:ef7eb2e8f9f7 873 * @param[in] usart
<> 144:ef7eb2e8f9f7 874 * Pointer to USART/UART peripheral register block.
<> 144:ef7eb2e8f9f7 875 *
<> 144:ef7eb2e8f9f7 876 * @return
<> 144:ef7eb2e8f9f7 877 * Data received.
<> 144:ef7eb2e8f9f7 878 ******************************************************************************/
<> 144:ef7eb2e8f9f7 879 __STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 return (uint16_t)usart->RXDATAX;
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data);
<> 144:ef7eb2e8f9f7 885 void USART_Tx(USART_TypeDef *usart, uint8_t data);
<> 144:ef7eb2e8f9f7 886 void USART_TxDouble(USART_TypeDef *usart, uint16_t data);
<> 144:ef7eb2e8f9f7 887 void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
<> 144:ef7eb2e8f9f7 888 void USART_TxExt(USART_TypeDef *usart, uint16_t data);
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /** @} (end addtogroup USART) */
<> 144:ef7eb2e8f9f7 892 /** @} (end addtogroup EM_Library) */
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896 #endif
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 #endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
<> 144:ef7eb2e8f9f7 899 #endif /* __SILICON_LABS_EM_USART_H__ */