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targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_mpu.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_mpu.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Definitions
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Defines the register numbers of the region descriptor configure. */
<> 144:ef7eb2e8f9f7 38 #define MPU_REGIONDESCRIPTOR_WROD_REGNUM (4U)
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*******************************************************************************
<> 144:ef7eb2e8f9f7 41 * Variables
<> 144:ef7eb2e8f9f7 42 ******************************************************************************/
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 const clock_ip_name_t g_mpuClock[FSL_FEATURE_SOC_MPU_COUNT] = MPU_CLOCKS;
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*******************************************************************************
<> 144:ef7eb2e8f9f7 47 * Codes
<> 144:ef7eb2e8f9f7 48 ******************************************************************************/
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 void MPU_Init(MPU_Type *base, const mpu_config_t *config)
<> 144:ef7eb2e8f9f7 51 {
<> 144:ef7eb2e8f9f7 52 assert(config);
<> 144:ef7eb2e8f9f7 53 uint8_t count;
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Un-gate MPU clock */
<> 144:ef7eb2e8f9f7 56 CLOCK_EnableClock(g_mpuClock[0]);
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Initializes the regions. */
<> 144:ef7eb2e8f9f7 59 for (count = 1; count < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; count++)
<> 144:ef7eb2e8f9f7 60 {
<> 144:ef7eb2e8f9f7 61 base->WORD[count][3] = 0; /* VLD/VID+PID. */
<> 144:ef7eb2e8f9f7 62 base->WORD[count][0] = 0; /* Start address. */
<> 144:ef7eb2e8f9f7 63 base->WORD[count][1] = 0; /* End address. */
<> 144:ef7eb2e8f9f7 64 base->WORD[count][2] = 0; /* Access rights. */
<> 144:ef7eb2e8f9f7 65 base->RGDAAC[count] = 0; /* Alternate access rights. */
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /* MPU configure. */
<> 144:ef7eb2e8f9f7 69 while (config)
<> 144:ef7eb2e8f9f7 70 {
<> 144:ef7eb2e8f9f7 71 MPU_SetRegionConfig(base, &(config->regionConfig));
<> 144:ef7eb2e8f9f7 72 config = config->next;
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74 /* Enable MPU. */
<> 144:ef7eb2e8f9f7 75 MPU_Enable(base, true);
<> 144:ef7eb2e8f9f7 76 }
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 void MPU_Deinit(MPU_Type *base)
<> 144:ef7eb2e8f9f7 79 {
<> 144:ef7eb2e8f9f7 80 /* Disable MPU. */
<> 144:ef7eb2e8f9f7 81 MPU_Enable(base, false);
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* Gate the clock. */
<> 144:ef7eb2e8f9f7 84 CLOCK_DisableClock(g_mpuClock[0]);
<> 144:ef7eb2e8f9f7 85 }
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform)
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 assert(hardwareInform);
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 uint32_t cesReg = base->CESR;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 hardwareInform->hardwareRevisionLevel = (cesReg & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT;
<> 144:ef7eb2e8f9f7 94 hardwareInform->slavePortsNumbers = (cesReg & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT;
<> 144:ef7eb2e8f9f7 95 hardwareInform->regionsNumbers = (mpu_region_total_num_t)((cesReg & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT);
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig)
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 assert(regionConfig);
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 uint32_t wordReg = 0;
<> 144:ef7eb2e8f9f7 103 uint8_t count;
<> 144:ef7eb2e8f9f7 104 uint8_t number = regionConfig->regionNum;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* The start and end address of the region descriptor. */
<> 144:ef7eb2e8f9f7 107 base->WORD[number][0] = regionConfig->startAddress;
<> 144:ef7eb2e8f9f7 108 base->WORD[number][1] = regionConfig->endAddress;
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* The region descriptor access rights control. */
<> 144:ef7eb2e8f9f7 111 for (count = 0; count < MPU_REGIONDESCRIPTOR_WROD_REGNUM; count++)
<> 144:ef7eb2e8f9f7 112 {
<> 144:ef7eb2e8f9f7 113 wordReg |= MPU_WORD_LOW_MASTER(count, (((uint32_t)regionConfig->accessRights1[count].superAccessRights << 3U) |
<> 144:ef7eb2e8f9f7 114 (uint8_t)regionConfig->accessRights1[count].userAccessRights)) |
<> 144:ef7eb2e8f9f7 115 MPU_WORD_HIGH_MASTER(count, ((uint32_t)regionConfig->accessRights2[count].readEnable << 1U |
<> 144:ef7eb2e8f9f7 116 (uint8_t)regionConfig->accessRights2[count].writeEnable));
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 119 wordReg |= MPU_WORD_MASTER_PE(count, regionConfig->accessRights1[count].processIdentifierEnable);
<> 144:ef7eb2e8f9f7 120 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Set region descriptor access rights. */
<> 144:ef7eb2e8f9f7 124 base->WORD[number][2] = wordReg;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 wordReg = MPU_WORD_VLD(1);
<> 144:ef7eb2e8f9f7 127 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 128 wordReg |= MPU_WORD_PID(regionConfig->processIdentifier) | MPU_WORD_PIDMASK(regionConfig->processIdMask);
<> 144:ef7eb2e8f9f7 129 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 base->WORD[number][3] = wordReg;
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr)
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 base->WORD[regionNum][0] = startAddr;
<> 144:ef7eb2e8f9f7 137 base->WORD[regionNum][1] = endAddr;
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 void MPU_SetRegionLowMasterAccessRights(MPU_Type *base,
<> 144:ef7eb2e8f9f7 141 mpu_region_num_t regionNum,
<> 144:ef7eb2e8f9f7 142 mpu_master_t masterNum,
<> 144:ef7eb2e8f9f7 143 const mpu_low_masters_access_rights_t *accessRights)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 assert(accessRights);
<> 144:ef7eb2e8f9f7 146 #if FSL_FEATURE_MPU_HAS_MASTER4
<> 144:ef7eb2e8f9f7 147 assert(masterNum < kMPU_Master4);
<> 144:ef7eb2e8f9f7 148 #endif
<> 144:ef7eb2e8f9f7 149 uint32_t mask = MPU_WORD_LOW_MASTER_MASK(masterNum);
<> 144:ef7eb2e8f9f7 150 uint32_t right = base->RGDAAC[regionNum];
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 153 mask |= MPU_LOW_MASTER_PE_MASK(masterNum);
<> 144:ef7eb2e8f9f7 154 #endif
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Build rights control value. */
<> 144:ef7eb2e8f9f7 157 right &= ~mask;
<> 144:ef7eb2e8f9f7 158 right |= MPU_WORD_LOW_MASTER(masterNum,
<> 144:ef7eb2e8f9f7 159 ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
<> 144:ef7eb2e8f9f7 160 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 161 right |= MPU_WORD_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
<> 144:ef7eb2e8f9f7 162 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Set low master region access rights. */
<> 144:ef7eb2e8f9f7 165 base->RGDAAC[regionNum] = right;
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 void MPU_SetRegionHighMasterAccessRights(MPU_Type *base,
<> 144:ef7eb2e8f9f7 169 mpu_region_num_t regionNum,
<> 144:ef7eb2e8f9f7 170 mpu_master_t masterNum,
<> 144:ef7eb2e8f9f7 171 const mpu_high_masters_access_rights_t *accessRights)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 assert(accessRights);
<> 144:ef7eb2e8f9f7 174 #if FSL_FEATURE_MPU_HAS_MASTER3
<> 144:ef7eb2e8f9f7 175 assert(masterNum > kMPU_Master3);
<> 144:ef7eb2e8f9f7 176 #endif
<> 144:ef7eb2e8f9f7 177 uint32_t mask = MPU_WORD_HIGH_MASTER_MASK(masterNum);
<> 144:ef7eb2e8f9f7 178 uint32_t right = base->RGDAAC[regionNum];
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Build rights control value. */
<> 144:ef7eb2e8f9f7 181 right &= ~mask;
<> 144:ef7eb2e8f9f7 182 right |= MPU_WORD_HIGH_MASTER((masterNum - (uint8_t)kMPU_RegionNum04),
<> 144:ef7eb2e8f9f7 183 (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
<> 144:ef7eb2e8f9f7 184 /* Set low master region access rights. */
<> 144:ef7eb2e8f9f7 185 base->RGDAAC[regionNum] = right;
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 uint8_t sperr;
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 sperr = ((base->CESR & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT) & (0x1U << slaveNum);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 return (sperr != 0) ? true : false;
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 assert(errInform);
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 uint16_t value;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Error address. */
<> 144:ef7eb2e8f9f7 204 errInform->address = base->SP[slaveNum].EAR;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Error detail information. */
<> 144:ef7eb2e8f9f7 207 value = (base->SP[slaveNum].EDR & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT;
<> 144:ef7eb2e8f9f7 208 if (!value)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 errInform->accessControl = kMPU_NoRegionHit;
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212 else if (!(value & (uint16_t)(value - 1)))
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 errInform->accessControl = kMPU_NoneOverlappRegion;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216 else
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 errInform->accessControl = kMPU_OverlappRegion;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 value = base->SP[slaveNum].EDR;
<> 144:ef7eb2e8f9f7 222 errInform->master = (mpu_master_t)((value & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT);
<> 144:ef7eb2e8f9f7 223 errInform->attributes = (mpu_err_attributes_t)((value & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT);
<> 144:ef7eb2e8f9f7 224 errInform->accessType = (mpu_err_access_type_t)((value & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT);
<> 144:ef7eb2e8f9f7 225 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
<> 144:ef7eb2e8f9f7 226 errInform->processorIdentification = (uint8_t)((value & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT);
<> 144:ef7eb2e8f9f7 227 #endif
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /*!< Clears error slave port bit. */
<> 144:ef7eb2e8f9f7 230 value = (base->CESR & ~MPU_CESR_SPERR_MASK) | (0x1U << slaveNum);
<> 144:ef7eb2e8f9f7 231 base->CESR = value;
<> 144:ef7eb2e8f9f7 232 }