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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f0xx_hal_pwr.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief PWR HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of the Power Controller (PWR) peripheral:
bogdanm 0:9b334a45a8ff 10 * + Initialization/de-initialization function
bogdanm 0:9b334a45a8ff 11 * + Peripheral Control function
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 @verbatim
bogdanm 0:9b334a45a8ff 14 ******************************************************************************
bogdanm 0:9b334a45a8ff 15 * @attention
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 20 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 22 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 25 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 27 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 28 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 29 *
bogdanm 0:9b334a45a8ff 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 40 *
bogdanm 0:9b334a45a8ff 41 ******************************************************************************
bogdanm 0:9b334a45a8ff 42 */
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 45 #include "stm32f0xx_hal.h"
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 48 * @{
bogdanm 0:9b334a45a8ff 49 */
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /** @defgroup PWR PWR
bogdanm 0:9b334a45a8ff 52 * @brief PWR HAL module driver
bogdanm 0:9b334a45a8ff 53 * @{
bogdanm 0:9b334a45a8ff 54 */
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 #ifdef HAL_PWR_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 60 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 61 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 62 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 63 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /** @defgroup PWR_Exported_Functions PWR Exported Functions
bogdanm 0:9b334a45a8ff 66 * @{
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 70 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 71 *
bogdanm 0:9b334a45a8ff 72 @verbatim
bogdanm 0:9b334a45a8ff 73 ===============================================================================
bogdanm 0:9b334a45a8ff 74 ##### Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 75 ===============================================================================
bogdanm 0:9b334a45a8ff 76 [..]
bogdanm 0:9b334a45a8ff 77 After reset, the backup domain (RTC registers, RTC backup data
bogdanm 0:9b334a45a8ff 78 registers) is protected against possible unwanted
bogdanm 0:9b334a45a8ff 79 write accesses.
bogdanm 0:9b334a45a8ff 80 To enable access to the RTC Domain and RTC registers, proceed as follows:
bogdanm 0:9b334a45a8ff 81 (+) Enable the Power Controller (PWR) APB1 interface clock using the
bogdanm 0:9b334a45a8ff 82 __HAL_RCC_PWR_CLK_ENABLE() macro.
bogdanm 0:9b334a45a8ff 83 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 @endverbatim
bogdanm 0:9b334a45a8ff 86 * @{
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /**
bogdanm 0:9b334a45a8ff 90 * @brief Deinitializes the PWR peripheral registers to their default reset values.
bogdanm 0:9b334a45a8ff 91 * @retval None
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93 void HAL_PWR_DeInit(void)
bogdanm 0:9b334a45a8ff 94 {
bogdanm 0:9b334a45a8ff 95 __HAL_RCC_PWR_FORCE_RESET();
bogdanm 0:9b334a45a8ff 96 __HAL_RCC_PWR_RELEASE_RESET();
bogdanm 0:9b334a45a8ff 97 }
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /**
bogdanm 0:9b334a45a8ff 100 * @brief Enables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 101 * backup data registers when present).
bogdanm 0:9b334a45a8ff 102 * @note If the HSE divided by 32 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 103 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 104 * @retval None
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106 void HAL_PWR_EnableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 107 {
bogdanm 0:9b334a45a8ff 108 PWR->CR |= (uint32_t)PWR_CR_DBP;
bogdanm 0:9b334a45a8ff 109 }
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /**
bogdanm 0:9b334a45a8ff 112 * @brief Disables access to the backup domain (RTC registers, RTC
bogdanm 0:9b334a45a8ff 113 * backup data registers when present).
bogdanm 0:9b334a45a8ff 114 * @note If the HSE divided by 32 is used as the RTC clock, the
bogdanm 0:9b334a45a8ff 115 * Backup Domain Access should be kept enabled.
bogdanm 0:9b334a45a8ff 116 * @retval None
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118 void HAL_PWR_DisableBkUpAccess(void)
bogdanm 0:9b334a45a8ff 119 {
bogdanm 0:9b334a45a8ff 120 PWR->CR &= ~((uint32_t)PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 121 }
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /**
bogdanm 0:9b334a45a8ff 124 * @}
bogdanm 0:9b334a45a8ff 125 */
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 128 * @brief Low Power modes configuration functions
bogdanm 0:9b334a45a8ff 129 *
bogdanm 0:9b334a45a8ff 130 @verbatim
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 ===============================================================================
bogdanm 0:9b334a45a8ff 133 ##### Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 134 ===============================================================================
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 *** WakeUp pin configuration ***
bogdanm 0:9b334a45a8ff 137 ================================
bogdanm 0:9b334a45a8ff 138 [..]
bogdanm 0:9b334a45a8ff 139 (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
bogdanm 0:9b334a45a8ff 140 forced in input pull down configuration and is active on rising edges.
bogdanm 0:9b334a45a8ff 141 (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
bogdanm 0:9b334a45a8ff 142 (++)WakeUp Pin 1 on PA.00.
bogdanm 0:9b334a45a8ff 143 (++)WakeUp Pin 2 on PC.13.
bogdanm 0:9b334a45a8ff 144 (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
bogdanm 0:9b334a45a8ff 145 (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
bogdanm 0:9b334a45a8ff 146 (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
bogdanm 0:9b334a45a8ff 147 (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
bogdanm 0:9b334a45a8ff 148 (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
bogdanm 0:9b334a45a8ff 149 (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 *** Low Power modes configuration ***
bogdanm 0:9b334a45a8ff 152 =====================================
bogdanm 0:9b334a45a8ff 153 [..]
bogdanm 0:9b334a45a8ff 154 The devices feature 3 low-power modes:
bogdanm 0:9b334a45a8ff 155 (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
bogdanm 0:9b334a45a8ff 156 (+) Stop mode: all clocks are stopped, regulator running, regulator
bogdanm 0:9b334a45a8ff 157 in low power mode
bogdanm 0:9b334a45a8ff 158 (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 *** Sleep mode ***
bogdanm 0:9b334a45a8ff 161 ==================
bogdanm 0:9b334a45a8ff 162 [..]
bogdanm 0:9b334a45a8ff 163 (+) Entry:
bogdanm 0:9b334a45a8ff 164 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
bogdanm 0:9b334a45a8ff 165 functions with
bogdanm 0:9b334a45a8ff 166 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 167 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 (+) Exit:
bogdanm 0:9b334a45a8ff 170 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
bogdanm 0:9b334a45a8ff 171 controller (NVIC) can wake up the device from Sleep mode.
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 *** Stop mode ***
bogdanm 0:9b334a45a8ff 174 =================
bogdanm 0:9b334a45a8ff 175 [..]
bogdanm 0:9b334a45a8ff 176 In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
bogdanm 0:9b334a45a8ff 177 and the HSE RC oscillators are disabled. Internal SRAM and register contents
bogdanm 0:9b334a45a8ff 178 are preserved.
bogdanm 0:9b334a45a8ff 179 The voltage regulator can be configured either in normal or low-power mode.
bogdanm 0:9b334a45a8ff 180 To minimize the consumption.
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 (+) Entry:
bogdanm 0:9b334a45a8ff 183 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
bogdanm 0:9b334a45a8ff 184 function with:
bogdanm 0:9b334a45a8ff 185 (++) Main regulator ON.
bogdanm 0:9b334a45a8ff 186 (++) Low Power regulator ON.
bogdanm 0:9b334a45a8ff 187 (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
bogdanm 0:9b334a45a8ff 188 (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
bogdanm 0:9b334a45a8ff 189 (+) Exit:
bogdanm 0:9b334a45a8ff 190 (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
bogdanm 0:9b334a45a8ff 191 (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
bogdanm 0:9b334a45a8ff 192 when programmed in wakeup mode (the peripheral must be
bogdanm 0:9b334a45a8ff 193 programmed in wakeup mode and the corresponding interrupt vector
bogdanm 0:9b334a45a8ff 194 must be enabled in the NVIC)
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 *** Standby mode ***
bogdanm 0:9b334a45a8ff 197 ====================
bogdanm 0:9b334a45a8ff 198 [..]
bogdanm 0:9b334a45a8ff 199 The Standby mode allows to achieve the lowest power consumption. It is based
bogdanm 0:9b334a45a8ff 200 on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
bogdanm 0:9b334a45a8ff 201 The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
bogdanm 0:9b334a45a8ff 202 the HSE oscillator are also switched off. SRAM and register contents are lost
bogdanm 0:9b334a45a8ff 203 except for the RTC registers, RTC backup registers and Standby circuitry.
bogdanm 0:9b334a45a8ff 204 The voltage regulator is OFF.
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 (+) Entry:
bogdanm 0:9b334a45a8ff 207 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
bogdanm 0:9b334a45a8ff 208 (+) Exit:
bogdanm 0:9b334a45a8ff 209 (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
bogdanm 0:9b334a45a8ff 210 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 *** Auto-wakeup (AWU) from low-power mode ***
bogdanm 0:9b334a45a8ff 213 =============================================
bogdanm 0:9b334a45a8ff 214 [..]
bogdanm 0:9b334a45a8ff 215 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
bogdanm 0:9b334a45a8ff 216 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
bogdanm 0:9b334a45a8ff 217 without depending on an external interrupt (Auto-wakeup mode).
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
bogdanm 0:9b334a45a8ff 222 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
bogdanm 0:9b334a45a8ff 225 is necessary to configure the RTC to detect the tamper or time stamp event using the
bogdanm 0:9b334a45a8ff 226 HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
bogdanm 0:9b334a45a8ff 229 configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 (+) Comparator auto-wakeup (AWU) from the Stop mode
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
bogdanm 0:9b334a45a8ff 234 (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
bogdanm 0:9b334a45a8ff 235 to be sensitive to to the selected edges (falling, rising or falling
bogdanm 0:9b334a45a8ff 236 and rising) (Interrupt or Event modes) using the EXTI_Init() function.
bogdanm 0:9b334a45a8ff 237 (+++) Configure the comparator to generate the event.
bogdanm 0:9b334a45a8ff 238 @endverbatim
bogdanm 0:9b334a45a8ff 239 * @{
bogdanm 0:9b334a45a8ff 240 */
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /**
bogdanm 0:9b334a45a8ff 243 * @brief Enables the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 244 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
bogdanm 0:9b334a45a8ff 245 * This parameter can be value of :
bogdanm 0:9b334a45a8ff 246 * @ref PWREx_WakeUp_Pins
bogdanm 0:9b334a45a8ff 247 * @retval None
bogdanm 0:9b334a45a8ff 248 */
bogdanm 0:9b334a45a8ff 249 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 250 {
bogdanm 0:9b334a45a8ff 251 /* Check the parameters */
bogdanm 0:9b334a45a8ff 252 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 253 PWR->CSR |= (PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx);
bogdanm 0:9b334a45a8ff 254 }
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /**
bogdanm 0:9b334a45a8ff 257 * @brief Disables the WakeUp PINx functionality.
bogdanm 0:9b334a45a8ff 258 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
bogdanm 0:9b334a45a8ff 259 * This parameter can be values of :
bogdanm 0:9b334a45a8ff 260 * @ref PWREx_WakeUp_Pins
bogdanm 0:9b334a45a8ff 261 * @retval None
bogdanm 0:9b334a45a8ff 262 */
bogdanm 0:9b334a45a8ff 263 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
bogdanm 0:9b334a45a8ff 264 {
bogdanm 0:9b334a45a8ff 265 /* Check the parameters */
bogdanm 0:9b334a45a8ff 266 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
bogdanm 0:9b334a45a8ff 267 PWR->CSR &= ~(PWR_CSR_EWUP1 << (uint8_t)WakeUpPinx);
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /**
bogdanm 0:9b334a45a8ff 271 * @brief Enters Sleep mode.
bogdanm 0:9b334a45a8ff 272 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 273 * @param Regulator: Specifies the regulator state in SLEEP mode.
bogdanm 0:9b334a45a8ff 274 * On STM32F0 devices, this parameter is a dummy value and it is ignored
bogdanm 0:9b334a45a8ff 275 * as regulator can't be modified in this mode. Parameter is kept for platform
bogdanm 0:9b334a45a8ff 276 * compatibility.
bogdanm 0:9b334a45a8ff 277 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 278 * When WFI entry is used, tick interrupt have to be disabled if not desired as
bogdanm 0:9b334a45a8ff 279 * the interrupt wake up source.
bogdanm 0:9b334a45a8ff 280 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 281 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
bogdanm 0:9b334a45a8ff 282 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
bogdanm 0:9b334a45a8ff 283 * @retval None
bogdanm 0:9b334a45a8ff 284 */
bogdanm 0:9b334a45a8ff 285 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
bogdanm 0:9b334a45a8ff 286 {
bogdanm 0:9b334a45a8ff 287 /* Check the parameters */
bogdanm 0:9b334a45a8ff 288 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 289 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Clear SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 292 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /* Select SLEEP mode entry -------------------------------------------------*/
bogdanm 0:9b334a45a8ff 295 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 298 __WFI();
bogdanm 0:9b334a45a8ff 299 }
bogdanm 0:9b334a45a8ff 300 else
bogdanm 0:9b334a45a8ff 301 {
bogdanm 0:9b334a45a8ff 302 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 303 __SEV();
bogdanm 0:9b334a45a8ff 304 __WFE();
bogdanm 0:9b334a45a8ff 305 __WFE();
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 }
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /**
bogdanm 0:9b334a45a8ff 310 * @brief Enters STOP mode.
bogdanm 0:9b334a45a8ff 311 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
bogdanm 0:9b334a45a8ff 312 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
bogdanm 0:9b334a45a8ff 313 * the HSI RC oscillator is selected as system clock.
bogdanm 0:9b334a45a8ff 314 * @note When the voltage regulator operates in low power mode, an additional
bogdanm 0:9b334a45a8ff 315 * startup delay is incurred when waking up from Stop mode.
bogdanm 0:9b334a45a8ff 316 * By keeping the internal regulator ON during Stop mode, the consumption
bogdanm 0:9b334a45a8ff 317 * is higher although the startup time is reduced.
bogdanm 0:9b334a45a8ff 318 * @param Regulator: Specifies the regulator state in STOP mode.
bogdanm 0:9b334a45a8ff 319 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 320 * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
bogdanm 0:9b334a45a8ff 321 * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
bogdanm 0:9b334a45a8ff 322 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
bogdanm 0:9b334a45a8ff 323 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 324 * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
bogdanm 0:9b334a45a8ff 325 * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
bogdanm 0:9b334a45a8ff 326 * @retval None
bogdanm 0:9b334a45a8ff 327 */
bogdanm 0:9b334a45a8ff 328 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
bogdanm 0:9b334a45a8ff 329 {
bogdanm 0:9b334a45a8ff 330 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /* Check the parameters */
bogdanm 0:9b334a45a8ff 333 assert_param(IS_PWR_REGULATOR(Regulator));
bogdanm 0:9b334a45a8ff 334 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /* Select the regulator state in STOP mode ---------------------------------*/
bogdanm 0:9b334a45a8ff 337 tmpreg = PWR->CR;
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /* Clear PDDS and LPDS bits */
bogdanm 0:9b334a45a8ff 340 tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /* Set LPDS bit according to Regulator value */
bogdanm 0:9b334a45a8ff 343 tmpreg |= Regulator;
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /* Store the new value */
bogdanm 0:9b334a45a8ff 346 PWR->CR = tmpreg;
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 349 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /* Select STOP mode entry --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 352 if(STOPEntry == PWR_STOPENTRY_WFI)
bogdanm 0:9b334a45a8ff 353 {
bogdanm 0:9b334a45a8ff 354 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 355 __WFI();
bogdanm 0:9b334a45a8ff 356 }
bogdanm 0:9b334a45a8ff 357 else
bogdanm 0:9b334a45a8ff 358 {
bogdanm 0:9b334a45a8ff 359 /* Request Wait For Event */
bogdanm 0:9b334a45a8ff 360 __SEV();
bogdanm 0:9b334a45a8ff 361 __WFE();
bogdanm 0:9b334a45a8ff 362 __WFE();
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* Reset SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 366 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /**
bogdanm 0:9b334a45a8ff 370 * @brief Enters STANDBY mode.
bogdanm 0:9b334a45a8ff 371 * @note In Standby mode, all I/O pins are high impedance except for:
bogdanm 0:9b334a45a8ff 372 * - Reset pad (still available)
bogdanm 0:9b334a45a8ff 373 * - RTC alternate function pins if configured for tamper, time-stamp, RTC
bogdanm 0:9b334a45a8ff 374 * Alarm out, or RTC clock calibration out.
bogdanm 0:9b334a45a8ff 375 * - WKUP pins if enabled.
bogdanm 0:9b334a45a8ff 376 * STM32F0x8 devices, the Stop mode is available, but it is
bogdanm 0:9b334a45a8ff 377 * aningless to distinguish between voltage regulator in Low power
bogdanm 0:9b334a45a8ff 378 * mode and voltage regulator in Run mode because the regulator
bogdanm 0:9b334a45a8ff 379 * not used and the core is supplied directly from an external source.
bogdanm 0:9b334a45a8ff 380 * Consequently, the Standby mode is not available on those devices.
bogdanm 0:9b334a45a8ff 381 * @retval None
bogdanm 0:9b334a45a8ff 382 */
bogdanm 0:9b334a45a8ff 383 void HAL_PWR_EnterSTANDBYMode(void)
bogdanm 0:9b334a45a8ff 384 {
bogdanm 0:9b334a45a8ff 385 /* Select STANDBY mode */
bogdanm 0:9b334a45a8ff 386 PWR->CR |= (uint32_t)PWR_CR_PDDS;
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /* Set SLEEPDEEP bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 389 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /* This option is used to ensure that store operations are completed */
bogdanm 0:9b334a45a8ff 392 #if defined ( __CC_ARM)
bogdanm 0:9b334a45a8ff 393 __force_stores();
bogdanm 0:9b334a45a8ff 394 #endif
bogdanm 0:9b334a45a8ff 395 /* Request Wait For Interrupt */
bogdanm 0:9b334a45a8ff 396 __WFI();
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 /**
bogdanm 0:9b334a45a8ff 400 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 401 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 402 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 403 * Setting this bit is useful when the processor is expected to run only on
bogdanm 0:9b334a45a8ff 404 * interruptions handling.
bogdanm 0:9b334a45a8ff 405 * @retval None
bogdanm 0:9b334a45a8ff 406 */
bogdanm 0:9b334a45a8ff 407 void HAL_PWR_EnableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 408 {
bogdanm 0:9b334a45a8ff 409 /* Set SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 410 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /**
bogdanm 0:9b334a45a8ff 415 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
bogdanm 0:9b334a45a8ff 416 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
bogdanm 0:9b334a45a8ff 417 * re-enters SLEEP mode when an interruption handling is over.
bogdanm 0:9b334a45a8ff 418 * @retval None
bogdanm 0:9b334a45a8ff 419 */
bogdanm 0:9b334a45a8ff 420 void HAL_PWR_DisableSleepOnExit(void)
bogdanm 0:9b334a45a8ff 421 {
bogdanm 0:9b334a45a8ff 422 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 423 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
bogdanm 0:9b334a45a8ff 424 }
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @brief Enables CORTEX M4 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 430 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 431 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 432 * @retval None
bogdanm 0:9b334a45a8ff 433 */
bogdanm 0:9b334a45a8ff 434 void HAL_PWR_EnableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 /* Set SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 437 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 438 }
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 /**
bogdanm 0:9b334a45a8ff 442 * @brief Disables CORTEX M4 SEVONPEND bit.
bogdanm 0:9b334a45a8ff 443 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
bogdanm 0:9b334a45a8ff 444 * WFE to wake up when an interrupt moves from inactive to pended.
bogdanm 0:9b334a45a8ff 445 * @retval None
bogdanm 0:9b334a45a8ff 446 */
bogdanm 0:9b334a45a8ff 447 void HAL_PWR_DisableSEVOnPend(void)
bogdanm 0:9b334a45a8ff 448 {
bogdanm 0:9b334a45a8ff 449 /* Clear SEVONPEND bit of Cortex System Control Register */
bogdanm 0:9b334a45a8ff 450 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /**
bogdanm 0:9b334a45a8ff 454 * @}
bogdanm 0:9b334a45a8ff 455 */
bogdanm 0:9b334a45a8ff 456
bogdanm 0:9b334a45a8ff 457 /**
bogdanm 0:9b334a45a8ff 458 * @}
bogdanm 0:9b334a45a8ff 459 */
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 #endif /* HAL_PWR_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 462 /**
bogdanm 0:9b334a45a8ff 463 * @}
bogdanm 0:9b334a45a8ff 464 */
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @}
bogdanm 0:9b334a45a8ff 468 */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/