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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device/efm32hg_devinfo.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_devinfo.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32hg_devinfo.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32HG_DEVINFO register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32HG_DEVINFO
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 *****************************************************************************/
<> 144:ef7eb2e8f9f7 40 typedef struct
<> 144:ef7eb2e8f9f7 41 {
<> 144:ef7eb2e8f9f7 42 __I uint32_t CAL; /**< Calibration temperature and checksum */
<> 144:ef7eb2e8f9f7 43 __I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
<> 144:ef7eb2e8f9f7 44 __I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
<> 144:ef7eb2e8f9f7 45 __I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
<> 144:ef7eb2e8f9f7 46 uint32_t RESERVED0[2]; /**< Reserved */
<> 144:ef7eb2e8f9f7 47 __I uint32_t IDAC0CAL0; /**< IDAC0 calibration register */
<> 144:ef7eb2e8f9f7 48 __I uint32_t USHFRCOCAL0; /**< USHFRCO calibration register */
<> 144:ef7eb2e8f9f7 49 uint32_t RESERVED1[1]; /**< Reserved */
<> 144:ef7eb2e8f9f7 50 __I uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
<> 144:ef7eb2e8f9f7 51 __I uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
<> 144:ef7eb2e8f9f7 52 __I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
<> 144:ef7eb2e8f9f7 53 __I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
<> 144:ef7eb2e8f9f7 54 __I uint32_t MEMINFO; /**< Memory information */
<> 144:ef7eb2e8f9f7 55 uint32_t RESERVED2[2]; /**< Reserved */
<> 144:ef7eb2e8f9f7 56 __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
<> 144:ef7eb2e8f9f7 57 __I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
<> 144:ef7eb2e8f9f7 58 __I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
<> 144:ef7eb2e8f9f7 59 __I uint32_t PART; /**< Part description */
<> 144:ef7eb2e8f9f7 60 } DEVINFO_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 63 * @defgroup EFM32HG_DEVINFO_BitFields
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 *****************************************************************************/
<> 144:ef7eb2e8f9f7 66 /* Bit fields for EFM32HG_DEVINFO */
<> 144:ef7eb2e8f9f7 67 #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
<> 144:ef7eb2e8f9f7 68 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
<> 144:ef7eb2e8f9f7 69 #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
<> 144:ef7eb2e8f9f7 70 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
<> 144:ef7eb2e8f9f7 71 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
<> 144:ef7eb2e8f9f7 72 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
<> 144:ef7eb2e8f9f7 73 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
<> 144:ef7eb2e8f9f7 74 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
<> 144:ef7eb2e8f9f7 75 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
<> 144:ef7eb2e8f9f7 76 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
<> 144:ef7eb2e8f9f7 77 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
<> 144:ef7eb2e8f9f7 78 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
<> 144:ef7eb2e8f9f7 79 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
<> 144:ef7eb2e8f9f7 80 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
<> 144:ef7eb2e8f9f7 81 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
<> 144:ef7eb2e8f9f7 82 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
<> 144:ef7eb2e8f9f7 83 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
<> 144:ef7eb2e8f9f7 84 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
<> 144:ef7eb2e8f9f7 85 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
<> 144:ef7eb2e8f9f7 86 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
<> 144:ef7eb2e8f9f7 87 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
<> 144:ef7eb2e8f9f7 88 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
<> 144:ef7eb2e8f9f7 89 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
<> 144:ef7eb2e8f9f7 90 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
<> 144:ef7eb2e8f9f7 91 #define _DEVINFO_IDAC0CAL0_RANGE0_MASK 0x000000FFUL /**< Current range 0 tuning value for IDAC0 mask */
<> 144:ef7eb2e8f9f7 92 #define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT 0 /**< Current range 0 tuning value for IDAC0 shift */
<> 144:ef7eb2e8f9f7 93 #define _DEVINFO_IDAC0CAL0_RANGE1_MASK 0x0000FF00UL /**< Current range 1 tuning value for IDAC0 mask */
<> 144:ef7eb2e8f9f7 94 #define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT 8 /**< Current range 1 tuning value for IDAC0 shift */
<> 144:ef7eb2e8f9f7 95 #define _DEVINFO_IDAC0CAL0_RANGE2_MASK 0x00FF0000UL /**< Current range 2 tuning value for IDAC0 mask */
<> 144:ef7eb2e8f9f7 96 #define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT 16 /**< Current range 2 tuning value for IDAC0 shift */
<> 144:ef7eb2e8f9f7 97 #define _DEVINFO_IDAC0CAL0_RANGE3_MASK 0xFF000000UL /**< Current range 3 tuning value for IDAC0 mask */
<> 144:ef7eb2e8f9f7 98 #define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT 24 /**< Current range 3 tuning value for IDAC0 shift */
<> 144:ef7eb2e8f9f7 99 #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK 0x0000007FUL /**< 24 MHz TUNING value for USFRCO mask */
<> 144:ef7eb2e8f9f7 100 #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT 0 /**< 24 MHz TUNING value for USFRCO shift */
<> 144:ef7eb2e8f9f7 101 #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK 0x00003F00UL /**< 24 MHz FINETUNING value for USFRCO mask */
<> 144:ef7eb2e8f9f7 102 #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT 8 /**< 24 MHz FINETUNING value for USFRCO shift */
<> 144:ef7eb2e8f9f7 103 #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK 0x007F0000UL /**< 24 MHz TUNING value for USFRCO mask */
<> 144:ef7eb2e8f9f7 104 #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT 16 /**< 24 MHz TUNING value for USFRCO shift */
<> 144:ef7eb2e8f9f7 105 #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK 0x3F000000UL /**< 24 MHz FINETUNING value for USFRCO mask */
<> 144:ef7eb2e8f9f7 106 #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT 24 /**< 24 MHz FINETUNING value for USFRCO shift */
<> 144:ef7eb2e8f9f7 107 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
<> 144:ef7eb2e8f9f7 108 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
<> 144:ef7eb2e8f9f7 109 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
<> 144:ef7eb2e8f9f7 110 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
<> 144:ef7eb2e8f9f7 111 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
<> 144:ef7eb2e8f9f7 112 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
<> 144:ef7eb2e8f9f7 113 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
<> 144:ef7eb2e8f9f7 114 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
<> 144:ef7eb2e8f9f7 115 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
<> 144:ef7eb2e8f9f7 116 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
<> 144:ef7eb2e8f9f7 117 #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
<> 144:ef7eb2e8f9f7 118 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
<> 144:ef7eb2e8f9f7 119 #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
<> 144:ef7eb2e8f9f7 120 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
<> 144:ef7eb2e8f9f7 121 #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
<> 144:ef7eb2e8f9f7 122 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
<> 144:ef7eb2e8f9f7 123 #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
<> 144:ef7eb2e8f9f7 124 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
<> 144:ef7eb2e8f9f7 125 #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
<> 144:ef7eb2e8f9f7 126 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
<> 144:ef7eb2e8f9f7 127 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
<> 144:ef7eb2e8f9f7 128 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
<> 144:ef7eb2e8f9f7 129 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
<> 144:ef7eb2e8f9f7 130 #define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
<> 144:ef7eb2e8f9f7 131 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
<> 144:ef7eb2e8f9f7 132 #define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
<> 144:ef7eb2e8f9f7 133 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
<> 144:ef7eb2e8f9f7 134 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
<> 144:ef7eb2e8f9f7 135 #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
<> 144:ef7eb2e8f9f7 136 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
<> 144:ef7eb2e8f9f7 137 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
<> 144:ef7eb2e8f9f7 138 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
<> 144:ef7eb2e8f9f7 139 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
<> 144:ef7eb2e8f9f7 140 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
<> 144:ef7eb2e8f9f7 141 /* Legacy family #defines */
<> 144:ef7eb2e8f9f7 142 #define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
<> 144:ef7eb2e8f9f7 143 #define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
<> 144:ef7eb2e8f9f7 144 #define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
<> 144:ef7eb2e8f9f7 145 #define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
<> 144:ef7eb2e8f9f7 146 #define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
<> 144:ef7eb2e8f9f7 147 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
<> 144:ef7eb2e8f9f7 148 #define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
<> 144:ef7eb2e8f9f7 149 /* New style family #defines */
<> 144:ef7eb2e8f9f7 150 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
<> 144:ef7eb2e8f9f7 151 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
<> 144:ef7eb2e8f9f7 152 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
<> 144:ef7eb2e8f9f7 153 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
<> 144:ef7eb2e8f9f7 154 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
<> 144:ef7eb2e8f9f7 155 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
<> 144:ef7eb2e8f9f7 156 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
<> 144:ef7eb2e8f9f7 157 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
<> 144:ef7eb2e8f9f7 158 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
<> 144:ef7eb2e8f9f7 159 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
<> 144:ef7eb2e8f9f7 160 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
<> 144:ef7eb2e8f9f7 161 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @} End of group EFM32HG_DEVINFO */
<> 144:ef7eb2e8f9f7 164 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 165