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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device/efm32gg_timer.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32gg_timer.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32GG_TIMER register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32GG_TIMER
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32GG_TIMER Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t CMD; /**< Command Register */
<> 144:ef7eb2e8f9f7 45 __I uint32_t STATUS; /**< Status Register */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 47 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t TOP; /**< Counter Top Value Register */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t TOPB; /**< Counter Top Value Buffer Register */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t CNT; /**< Counter Value Register */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t ROUTE; /**< I/O Routing Register */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 uint32_t RESERVED0[1]; /**< Reserved registers */
<> 144:ef7eb2e8f9f7 56 TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 uint32_t RESERVED1[4]; /**< Reserved for future use **/
<> 144:ef7eb2e8f9f7 59 __IO uint32_t DTCTRL; /**< DTI Control Register */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t DTTIME; /**< DTI Time Control Register */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t DTFC; /**< DTI Fault Configuration Register */
<> 144:ef7eb2e8f9f7 62 __IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
<> 144:ef7eb2e8f9f7 63 __I uint32_t DTFAULT; /**< DTI Fault Register */
<> 144:ef7eb2e8f9f7 64 __O uint32_t DTFAULTC; /**< DTI Fault Clear Register */
<> 144:ef7eb2e8f9f7 65 __IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */
<> 144:ef7eb2e8f9f7 66 } TIMER_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 69 * @defgroup EFM32GG_TIMER_BitFields
<> 144:ef7eb2e8f9f7 70 * @{
<> 144:ef7eb2e8f9f7 71 *****************************************************************************/
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /* Bit fields for TIMER CTRL */
<> 144:ef7eb2e8f9f7 74 #define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 75 #define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 76 #define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
<> 144:ef7eb2e8f9f7 77 #define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
<> 144:ef7eb2e8f9f7 78 #define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 79 #define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 80 #define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 81 #define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 82 #define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 83 #define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 84 #define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 85 #define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 86 #define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 87 #define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 88 #define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
<> 144:ef7eb2e8f9f7 89 #define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
<> 144:ef7eb2e8f9f7 90 #define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
<> 144:ef7eb2e8f9f7 91 #define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 92 #define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 93 #define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
<> 144:ef7eb2e8f9f7 94 #define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
<> 144:ef7eb2e8f9f7 95 #define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
<> 144:ef7eb2e8f9f7 96 #define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 97 #define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 98 #define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
<> 144:ef7eb2e8f9f7 99 #define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
<> 144:ef7eb2e8f9f7 100 #define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
<> 144:ef7eb2e8f9f7 101 #define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 102 #define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 103 #define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 104 #define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 105 #define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 106 #define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 107 #define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
<> 144:ef7eb2e8f9f7 108 #define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
<> 144:ef7eb2e8f9f7 109 #define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
<> 144:ef7eb2e8f9f7 110 #define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 111 #define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 112 #define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
<> 144:ef7eb2e8f9f7 113 #define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
<> 144:ef7eb2e8f9f7 114 #define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
<> 144:ef7eb2e8f9f7 115 #define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 116 #define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 117 #define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
<> 144:ef7eb2e8f9f7 118 #define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
<> 144:ef7eb2e8f9f7 119 #define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 120 #define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 121 #define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 122 #define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 123 #define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 124 #define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 125 #define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 126 #define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 127 #define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 128 #define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 129 #define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
<> 144:ef7eb2e8f9f7 130 #define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
<> 144:ef7eb2e8f9f7 131 #define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 132 #define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 133 #define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 134 #define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 135 #define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 136 #define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 137 #define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 138 #define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 139 #define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 140 #define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 141 #define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
<> 144:ef7eb2e8f9f7 142 #define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
<> 144:ef7eb2e8f9f7 143 #define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
<> 144:ef7eb2e8f9f7 144 #define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 145 #define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 146 #define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
<> 144:ef7eb2e8f9f7 147 #define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
<> 144:ef7eb2e8f9f7 148 #define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 149 #define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 150 #define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 151 #define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 152 #define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 153 #define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 154 #define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 155 #define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 156 #define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
<> 144:ef7eb2e8f9f7 157 #define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
<> 144:ef7eb2e8f9f7 158 #define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 159 #define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 160 #define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 161 #define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 162 #define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 163 #define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 164 #define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 165 #define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 166 #define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 167 #define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 168 #define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 169 #define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 170 #define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 171 #define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 172 #define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 173 #define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 174 #define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 175 #define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 176 #define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 177 #define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 178 #define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 179 #define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 180 #define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 181 #define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 182 #define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
<> 144:ef7eb2e8f9f7 183 #define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
<> 144:ef7eb2e8f9f7 184 #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
<> 144:ef7eb2e8f9f7 185 #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 186 #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 187 #define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
<> 144:ef7eb2e8f9f7 188 #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
<> 144:ef7eb2e8f9f7 189 #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
<> 144:ef7eb2e8f9f7 190 #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 191 #define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Bit fields for TIMER CMD */
<> 144:ef7eb2e8f9f7 194 #define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
<> 144:ef7eb2e8f9f7 195 #define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
<> 144:ef7eb2e8f9f7 196 #define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */
<> 144:ef7eb2e8f9f7 197 #define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
<> 144:ef7eb2e8f9f7 198 #define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
<> 144:ef7eb2e8f9f7 199 #define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
<> 144:ef7eb2e8f9f7 200 #define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
<> 144:ef7eb2e8f9f7 201 #define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
<> 144:ef7eb2e8f9f7 202 #define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
<> 144:ef7eb2e8f9f7 203 #define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
<> 144:ef7eb2e8f9f7 204 #define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
<> 144:ef7eb2e8f9f7 205 #define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Bit fields for TIMER STATUS */
<> 144:ef7eb2e8f9f7 208 #define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 209 #define _TIMER_STATUS_MASK 0x07070707UL /**< Mask for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 210 #define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
<> 144:ef7eb2e8f9f7 211 #define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
<> 144:ef7eb2e8f9f7 212 #define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
<> 144:ef7eb2e8f9f7 213 #define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 214 #define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 215 #define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
<> 144:ef7eb2e8f9f7 216 #define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
<> 144:ef7eb2e8f9f7 217 #define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
<> 144:ef7eb2e8f9f7 218 #define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 219 #define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 220 #define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 221 #define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 222 #define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 223 #define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 224 #define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
<> 144:ef7eb2e8f9f7 225 #define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
<> 144:ef7eb2e8f9f7 226 #define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
<> 144:ef7eb2e8f9f7 227 #define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 228 #define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 229 #define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
<> 144:ef7eb2e8f9f7 230 #define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
<> 144:ef7eb2e8f9f7 231 #define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
<> 144:ef7eb2e8f9f7 232 #define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 233 #define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 234 #define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
<> 144:ef7eb2e8f9f7 235 #define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
<> 144:ef7eb2e8f9f7 236 #define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
<> 144:ef7eb2e8f9f7 237 #define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 238 #define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 239 #define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
<> 144:ef7eb2e8f9f7 240 #define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
<> 144:ef7eb2e8f9f7 241 #define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
<> 144:ef7eb2e8f9f7 242 #define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 243 #define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 244 #define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
<> 144:ef7eb2e8f9f7 245 #define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
<> 144:ef7eb2e8f9f7 246 #define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
<> 144:ef7eb2e8f9f7 247 #define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 248 #define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 249 #define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
<> 144:ef7eb2e8f9f7 250 #define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
<> 144:ef7eb2e8f9f7 251 #define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
<> 144:ef7eb2e8f9f7 252 #define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 253 #define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 254 #define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
<> 144:ef7eb2e8f9f7 255 #define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
<> 144:ef7eb2e8f9f7 256 #define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
<> 144:ef7eb2e8f9f7 257 #define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 258 #define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 259 #define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
<> 144:ef7eb2e8f9f7 260 #define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
<> 144:ef7eb2e8f9f7 261 #define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
<> 144:ef7eb2e8f9f7 262 #define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 263 #define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 264 #define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 265 #define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 266 #define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 267 #define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 268 #define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
<> 144:ef7eb2e8f9f7 269 #define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
<> 144:ef7eb2e8f9f7 270 #define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
<> 144:ef7eb2e8f9f7 271 #define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 272 #define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 273 #define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 274 #define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 275 #define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 276 #define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 277 #define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
<> 144:ef7eb2e8f9f7 278 #define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
<> 144:ef7eb2e8f9f7 279 #define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
<> 144:ef7eb2e8f9f7 280 #define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 281 #define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 282 #define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 283 #define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 284 #define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 285 #define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Bit fields for TIMER IEN */
<> 144:ef7eb2e8f9f7 288 #define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
<> 144:ef7eb2e8f9f7 289 #define _TIMER_IEN_MASK 0x00000773UL /**< Mask for TIMER_IEN */
<> 144:ef7eb2e8f9f7 290 #define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 291 #define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 144:ef7eb2e8f9f7 292 #define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 144:ef7eb2e8f9f7 293 #define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 294 #define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 295 #define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 296 #define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 144:ef7eb2e8f9f7 297 #define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 144:ef7eb2e8f9f7 298 #define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 299 #define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 300 #define TIMER_IEN_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Enable */
<> 144:ef7eb2e8f9f7 301 #define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 302 #define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 303 #define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 304 #define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 305 #define TIMER_IEN_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Enable */
<> 144:ef7eb2e8f9f7 306 #define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 307 #define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 308 #define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 309 #define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 310 #define TIMER_IEN_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Enable */
<> 144:ef7eb2e8f9f7 311 #define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 312 #define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 313 #define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 314 #define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 315 #define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 316 #define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 317 #define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 318 #define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 319 #define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 320 #define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 321 #define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 322 #define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 323 #define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 324 #define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 325 #define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 326 #define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 327 #define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 328 #define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 329 #define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Bit fields for TIMER IF */
<> 144:ef7eb2e8f9f7 332 #define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
<> 144:ef7eb2e8f9f7 333 #define _TIMER_IF_MASK 0x00000773UL /**< Mask for TIMER_IF */
<> 144:ef7eb2e8f9f7 334 #define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 335 #define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 144:ef7eb2e8f9f7 336 #define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 144:ef7eb2e8f9f7 337 #define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 338 #define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 339 #define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 340 #define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 144:ef7eb2e8f9f7 341 #define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 144:ef7eb2e8f9f7 342 #define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 343 #define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 344 #define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
<> 144:ef7eb2e8f9f7 345 #define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 346 #define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 347 #define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 348 #define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 349 #define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
<> 144:ef7eb2e8f9f7 350 #define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 351 #define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 352 #define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 353 #define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 354 #define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
<> 144:ef7eb2e8f9f7 355 #define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 356 #define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 357 #define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 358 #define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 359 #define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 360 #define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 361 #define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 362 #define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 363 #define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 364 #define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 365 #define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 366 #define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 367 #define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 368 #define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 369 #define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 370 #define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 371 #define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 372 #define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 373 #define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Bit fields for TIMER IFS */
<> 144:ef7eb2e8f9f7 376 #define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */
<> 144:ef7eb2e8f9f7 377 #define _TIMER_IFS_MASK 0x00000773UL /**< Mask for TIMER_IFS */
<> 144:ef7eb2e8f9f7 378 #define TIMER_IFS_OF (0x1UL << 0) /**< Overflow Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 379 #define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 144:ef7eb2e8f9f7 380 #define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 144:ef7eb2e8f9f7 381 #define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 382 #define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 383 #define TIMER_IFS_UF (0x1UL << 1) /**< Underflow Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 384 #define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 144:ef7eb2e8f9f7 385 #define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 144:ef7eb2e8f9f7 386 #define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 387 #define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 388 #define TIMER_IFS_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 389 #define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 390 #define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 391 #define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 392 #define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 393 #define TIMER_IFS_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 394 #define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 395 #define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 396 #define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 397 #define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 398 #define TIMER_IFS_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 399 #define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 400 #define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 401 #define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 402 #define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 403 #define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 404 #define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 405 #define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 406 #define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 407 #define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 408 #define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 409 #define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 410 #define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 411 #define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 412 #define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 413 #define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 414 #define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 415 #define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 416 #define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 417 #define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Bit fields for TIMER IFC */
<> 144:ef7eb2e8f9f7 420 #define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */
<> 144:ef7eb2e8f9f7 421 #define _TIMER_IFC_MASK 0x00000773UL /**< Mask for TIMER_IFC */
<> 144:ef7eb2e8f9f7 422 #define TIMER_IFC_OF (0x1UL << 0) /**< Overflow Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 423 #define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
<> 144:ef7eb2e8f9f7 424 #define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
<> 144:ef7eb2e8f9f7 425 #define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 426 #define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 427 #define TIMER_IFC_UF (0x1UL << 1) /**< Underflow Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 428 #define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
<> 144:ef7eb2e8f9f7 429 #define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
<> 144:ef7eb2e8f9f7 430 #define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 431 #define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 432 #define TIMER_IFC_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 433 #define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 434 #define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
<> 144:ef7eb2e8f9f7 435 #define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 436 #define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 437 #define TIMER_IFC_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 438 #define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 439 #define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
<> 144:ef7eb2e8f9f7 440 #define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 441 #define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 442 #define TIMER_IFC_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 443 #define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 444 #define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
<> 144:ef7eb2e8f9f7 445 #define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 446 #define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 447 #define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 448 #define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 449 #define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
<> 144:ef7eb2e8f9f7 450 #define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 451 #define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 452 #define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 453 #define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 454 #define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
<> 144:ef7eb2e8f9f7 455 #define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 456 #define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 457 #define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 458 #define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 459 #define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
<> 144:ef7eb2e8f9f7 460 #define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 461 #define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Bit fields for TIMER TOP */
<> 144:ef7eb2e8f9f7 464 #define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
<> 144:ef7eb2e8f9f7 465 #define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */
<> 144:ef7eb2e8f9f7 466 #define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
<> 144:ef7eb2e8f9f7 467 #define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */
<> 144:ef7eb2e8f9f7 468 #define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
<> 144:ef7eb2e8f9f7 469 #define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Bit fields for TIMER TOPB */
<> 144:ef7eb2e8f9f7 472 #define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
<> 144:ef7eb2e8f9f7 473 #define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */
<> 144:ef7eb2e8f9f7 474 #define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
<> 144:ef7eb2e8f9f7 475 #define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */
<> 144:ef7eb2e8f9f7 476 #define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
<> 144:ef7eb2e8f9f7 477 #define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Bit fields for TIMER CNT */
<> 144:ef7eb2e8f9f7 480 #define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
<> 144:ef7eb2e8f9f7 481 #define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */
<> 144:ef7eb2e8f9f7 482 #define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
<> 144:ef7eb2e8f9f7 483 #define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */
<> 144:ef7eb2e8f9f7 484 #define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
<> 144:ef7eb2e8f9f7 485 #define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Bit fields for TIMER ROUTE */
<> 144:ef7eb2e8f9f7 488 #define _TIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 489 #define _TIMER_ROUTE_MASK 0x00070707UL /**< Mask for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 490 #define TIMER_ROUTE_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
<> 144:ef7eb2e8f9f7 491 #define _TIMER_ROUTE_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
<> 144:ef7eb2e8f9f7 492 #define _TIMER_ROUTE_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
<> 144:ef7eb2e8f9f7 493 #define _TIMER_ROUTE_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 494 #define TIMER_ROUTE_CC0PEN_DEFAULT (_TIMER_ROUTE_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 495 #define TIMER_ROUTE_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
<> 144:ef7eb2e8f9f7 496 #define _TIMER_ROUTE_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
<> 144:ef7eb2e8f9f7 497 #define _TIMER_ROUTE_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
<> 144:ef7eb2e8f9f7 498 #define _TIMER_ROUTE_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 499 #define TIMER_ROUTE_CC1PEN_DEFAULT (_TIMER_ROUTE_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 500 #define TIMER_ROUTE_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
<> 144:ef7eb2e8f9f7 501 #define _TIMER_ROUTE_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
<> 144:ef7eb2e8f9f7 502 #define _TIMER_ROUTE_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
<> 144:ef7eb2e8f9f7 503 #define _TIMER_ROUTE_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 504 #define TIMER_ROUTE_CC2PEN_DEFAULT (_TIMER_ROUTE_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 505 #define TIMER_ROUTE_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
<> 144:ef7eb2e8f9f7 506 #define _TIMER_ROUTE_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
<> 144:ef7eb2e8f9f7 507 #define _TIMER_ROUTE_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
<> 144:ef7eb2e8f9f7 508 #define _TIMER_ROUTE_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 509 #define TIMER_ROUTE_CDTI0PEN_DEFAULT (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 510 #define TIMER_ROUTE_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
<> 144:ef7eb2e8f9f7 511 #define _TIMER_ROUTE_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
<> 144:ef7eb2e8f9f7 512 #define _TIMER_ROUTE_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
<> 144:ef7eb2e8f9f7 513 #define _TIMER_ROUTE_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 514 #define TIMER_ROUTE_CDTI1PEN_DEFAULT (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 515 #define TIMER_ROUTE_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
<> 144:ef7eb2e8f9f7 516 #define _TIMER_ROUTE_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
<> 144:ef7eb2e8f9f7 517 #define _TIMER_ROUTE_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
<> 144:ef7eb2e8f9f7 518 #define _TIMER_ROUTE_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 519 #define TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 520 #define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */
<> 144:ef7eb2e8f9f7 521 #define _TIMER_ROUTE_LOCATION_MASK 0x70000UL /**< Bit mask for TIMER_LOCATION */
<> 144:ef7eb2e8f9f7 522 #define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 523 #define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 524 #define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 525 #define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 526 #define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 527 #define _TIMER_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 528 #define _TIMER_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 529 #define TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 530 #define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 531 #define TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 532 #define TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 533 #define TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 534 #define TIMER_ROUTE_LOCATION_LOC4 (_TIMER_ROUTE_LOCATION_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 535 #define TIMER_ROUTE_LOCATION_LOC5 (_TIMER_ROUTE_LOCATION_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTE */
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Bit fields for TIMER CC_CTRL */
<> 144:ef7eb2e8f9f7 538 #define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 539 #define _TIMER_CC_CTRL_MASK 0x0F3F3F17UL /**< Mask for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 540 #define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
<> 144:ef7eb2e8f9f7 541 #define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
<> 144:ef7eb2e8f9f7 542 #define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 543 #define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 544 #define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 545 #define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 546 #define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 547 #define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 548 #define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 549 #define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 550 #define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 551 #define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 552 #define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
<> 144:ef7eb2e8f9f7 553 #define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
<> 144:ef7eb2e8f9f7 554 #define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
<> 144:ef7eb2e8f9f7 555 #define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 556 #define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 557 #define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
<> 144:ef7eb2e8f9f7 558 #define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
<> 144:ef7eb2e8f9f7 559 #define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
<> 144:ef7eb2e8f9f7 560 #define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 561 #define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 562 #define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
<> 144:ef7eb2e8f9f7 563 #define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
<> 144:ef7eb2e8f9f7 564 #define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 565 #define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 566 #define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 567 #define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 568 #define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 569 #define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 570 #define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 571 #define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 572 #define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 573 #define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 574 #define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
<> 144:ef7eb2e8f9f7 575 #define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
<> 144:ef7eb2e8f9f7 576 #define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 577 #define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 578 #define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 579 #define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 580 #define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 581 #define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 582 #define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 583 #define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 584 #define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 585 #define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 586 #define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
<> 144:ef7eb2e8f9f7 587 #define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
<> 144:ef7eb2e8f9f7 588 #define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 589 #define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 590 #define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 591 #define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 592 #define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 593 #define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 594 #define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 595 #define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 596 #define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 597 #define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 598 #define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
<> 144:ef7eb2e8f9f7 599 #define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
<> 144:ef7eb2e8f9f7 600 #define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 601 #define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 602 #define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 603 #define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 604 #define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 605 #define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 606 #define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 607 #define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 608 #define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 609 #define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 610 #define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 611 #define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 612 #define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 613 #define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 614 #define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 615 #define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 616 #define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 617 #define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 618 #define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 619 #define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 620 #define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 621 #define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 622 #define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 623 #define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 624 #define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 625 #define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 626 #define TIMER_CC_CTRL_INSEL (0x1UL << 20) /**< Input Selection */
<> 144:ef7eb2e8f9f7 627 #define _TIMER_CC_CTRL_INSEL_SHIFT 20 /**< Shift value for TIMER_INSEL */
<> 144:ef7eb2e8f9f7 628 #define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /**< Bit mask for TIMER_INSEL */
<> 144:ef7eb2e8f9f7 629 #define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 630 #define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 631 #define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 632 #define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 633 #define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 20) /**< Shifted mode PIN for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 634 #define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 20) /**< Shifted mode PRS for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 635 #define TIMER_CC_CTRL_FILT (0x1UL << 21) /**< Digital Filter */
<> 144:ef7eb2e8f9f7 636 #define _TIMER_CC_CTRL_FILT_SHIFT 21 /**< Shift value for TIMER_FILT */
<> 144:ef7eb2e8f9f7 637 #define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /**< Bit mask for TIMER_FILT */
<> 144:ef7eb2e8f9f7 638 #define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 639 #define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 640 #define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 641 #define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 642 #define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 21) /**< Shifted mode DISABLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 643 #define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 21) /**< Shifted mode ENABLE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 644 #define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
<> 144:ef7eb2e8f9f7 645 #define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
<> 144:ef7eb2e8f9f7 646 #define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 647 #define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 648 #define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 649 #define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 650 #define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 651 #define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 652 #define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 653 #define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 654 #define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 655 #define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 656 #define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
<> 144:ef7eb2e8f9f7 657 #define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
<> 144:ef7eb2e8f9f7 658 #define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 659 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 660 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 661 #define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 662 #define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 663 #define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 664 #define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 665 #define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 666 #define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 667 #define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Bit fields for TIMER CC_CCV */
<> 144:ef7eb2e8f9f7 670 #define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */
<> 144:ef7eb2e8f9f7 671 #define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */
<> 144:ef7eb2e8f9f7 672 #define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
<> 144:ef7eb2e8f9f7 673 #define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */
<> 144:ef7eb2e8f9f7 674 #define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */
<> 144:ef7eb2e8f9f7 675 #define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Bit fields for TIMER CC_CCVP */
<> 144:ef7eb2e8f9f7 678 #define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */
<> 144:ef7eb2e8f9f7 679 #define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */
<> 144:ef7eb2e8f9f7 680 #define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
<> 144:ef7eb2e8f9f7 681 #define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */
<> 144:ef7eb2e8f9f7 682 #define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */
<> 144:ef7eb2e8f9f7 683 #define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /* Bit fields for TIMER CC_CCVB */
<> 144:ef7eb2e8f9f7 686 #define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */
<> 144:ef7eb2e8f9f7 687 #define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */
<> 144:ef7eb2e8f9f7 688 #define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
<> 144:ef7eb2e8f9f7 689 #define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */
<> 144:ef7eb2e8f9f7 690 #define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */
<> 144:ef7eb2e8f9f7 691 #define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Bit fields for TIMER DTCTRL */
<> 144:ef7eb2e8f9f7 694 #define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 695 #define _TIMER_DTCTRL_MASK 0x010000FFUL /**< Mask for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 696 #define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
<> 144:ef7eb2e8f9f7 697 #define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
<> 144:ef7eb2e8f9f7 698 #define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
<> 144:ef7eb2e8f9f7 699 #define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 700 #define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 701 #define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
<> 144:ef7eb2e8f9f7 702 #define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
<> 144:ef7eb2e8f9f7 703 #define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
<> 144:ef7eb2e8f9f7 704 #define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 705 #define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 706 #define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 707 #define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 708 #define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 709 #define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 710 #define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
<> 144:ef7eb2e8f9f7 711 #define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
<> 144:ef7eb2e8f9f7 712 #define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
<> 144:ef7eb2e8f9f7 713 #define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 714 #define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 715 #define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
<> 144:ef7eb2e8f9f7 716 #define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
<> 144:ef7eb2e8f9f7 717 #define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
<> 144:ef7eb2e8f9f7 718 #define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 719 #define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 720 #define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
<> 144:ef7eb2e8f9f7 721 #define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
<> 144:ef7eb2e8f9f7 722 #define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 723 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 724 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 725 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 726 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 727 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 728 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 729 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 730 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 731 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 732 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 733 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 734 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 735 #define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 736 #define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 737 #define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 738 #define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 739 #define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 740 #define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 741 #define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 742 #define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 743 #define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 744 #define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 745 #define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 746 #define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 747 #define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 748 #define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
<> 144:ef7eb2e8f9f7 749 #define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
<> 144:ef7eb2e8f9f7 750 #define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
<> 144:ef7eb2e8f9f7 751 #define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 752 #define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Bit fields for TIMER DTTIME */
<> 144:ef7eb2e8f9f7 755 #define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 756 #define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 757 #define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
<> 144:ef7eb2e8f9f7 758 #define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
<> 144:ef7eb2e8f9f7 759 #define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 760 #define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 761 #define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 762 #define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 763 #define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 764 #define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 765 #define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 766 #define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 767 #define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 768 #define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 769 #define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 770 #define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 771 #define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 772 #define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 773 #define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 774 #define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 775 #define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 776 #define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 777 #define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 778 #define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 779 #define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 780 #define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 781 #define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 782 #define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 783 #define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
<> 144:ef7eb2e8f9f7 784 #define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
<> 144:ef7eb2e8f9f7 785 #define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 786 #define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 787 #define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
<> 144:ef7eb2e8f9f7 788 #define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
<> 144:ef7eb2e8f9f7 789 #define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 790 #define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Bit fields for TIMER DTFC */
<> 144:ef7eb2e8f9f7 793 #define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 794 #define _TIMER_DTFC_MASK 0x0F030707UL /**< Mask for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 795 #define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
<> 144:ef7eb2e8f9f7 796 #define _TIMER_DTFC_DTPRS0FSEL_MASK 0x7UL /**< Bit mask for TIMER_DTPRS0FSEL */
<> 144:ef7eb2e8f9f7 797 #define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 798 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 799 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 800 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 801 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 802 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 803 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 804 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 805 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 806 #define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 807 #define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 808 #define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 809 #define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 810 #define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 811 #define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 812 #define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 813 #define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 814 #define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 815 #define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
<> 144:ef7eb2e8f9f7 816 #define _TIMER_DTFC_DTPRS1FSEL_MASK 0x700UL /**< Bit mask for TIMER_DTPRS1FSEL */
<> 144:ef7eb2e8f9f7 817 #define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 818 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 819 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 820 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 821 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 822 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 823 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 824 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 825 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 826 #define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 827 #define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 828 #define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 829 #define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 830 #define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 831 #define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 832 #define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 833 #define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 834 #define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 835 #define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
<> 144:ef7eb2e8f9f7 836 #define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
<> 144:ef7eb2e8f9f7 837 #define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 838 #define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 839 #define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 840 #define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 841 #define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 842 #define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 843 #define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 844 #define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 845 #define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 846 #define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 847 #define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
<> 144:ef7eb2e8f9f7 848 #define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
<> 144:ef7eb2e8f9f7 849 #define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
<> 144:ef7eb2e8f9f7 850 #define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 851 #define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 852 #define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
<> 144:ef7eb2e8f9f7 853 #define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
<> 144:ef7eb2e8f9f7 854 #define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
<> 144:ef7eb2e8f9f7 855 #define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 856 #define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 857 #define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
<> 144:ef7eb2e8f9f7 858 #define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
<> 144:ef7eb2e8f9f7 859 #define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
<> 144:ef7eb2e8f9f7 860 #define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 861 #define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 862 #define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
<> 144:ef7eb2e8f9f7 863 #define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
<> 144:ef7eb2e8f9f7 864 #define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
<> 144:ef7eb2e8f9f7 865 #define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 866 #define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Bit fields for TIMER DTOGEN */
<> 144:ef7eb2e8f9f7 869 #define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 870 #define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 871 #define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
<> 144:ef7eb2e8f9f7 872 #define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
<> 144:ef7eb2e8f9f7 873 #define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
<> 144:ef7eb2e8f9f7 874 #define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 875 #define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 876 #define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
<> 144:ef7eb2e8f9f7 877 #define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
<> 144:ef7eb2e8f9f7 878 #define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
<> 144:ef7eb2e8f9f7 879 #define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 880 #define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 881 #define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
<> 144:ef7eb2e8f9f7 882 #define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
<> 144:ef7eb2e8f9f7 883 #define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
<> 144:ef7eb2e8f9f7 884 #define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 885 #define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 886 #define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
<> 144:ef7eb2e8f9f7 887 #define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
<> 144:ef7eb2e8f9f7 888 #define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
<> 144:ef7eb2e8f9f7 889 #define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 890 #define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 891 #define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
<> 144:ef7eb2e8f9f7 892 #define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
<> 144:ef7eb2e8f9f7 893 #define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
<> 144:ef7eb2e8f9f7 894 #define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 895 #define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 896 #define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
<> 144:ef7eb2e8f9f7 897 #define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
<> 144:ef7eb2e8f9f7 898 #define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
<> 144:ef7eb2e8f9f7 899 #define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 900 #define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* Bit fields for TIMER DTFAULT */
<> 144:ef7eb2e8f9f7 903 #define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 904 #define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 905 #define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
<> 144:ef7eb2e8f9f7 906 #define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
<> 144:ef7eb2e8f9f7 907 #define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
<> 144:ef7eb2e8f9f7 908 #define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 909 #define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 910 #define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
<> 144:ef7eb2e8f9f7 911 #define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
<> 144:ef7eb2e8f9f7 912 #define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
<> 144:ef7eb2e8f9f7 913 #define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 914 #define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 915 #define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
<> 144:ef7eb2e8f9f7 916 #define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
<> 144:ef7eb2e8f9f7 917 #define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
<> 144:ef7eb2e8f9f7 918 #define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 919 #define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 920 #define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
<> 144:ef7eb2e8f9f7 921 #define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
<> 144:ef7eb2e8f9f7 922 #define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
<> 144:ef7eb2e8f9f7 923 #define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 924 #define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /* Bit fields for TIMER DTFAULTC */
<> 144:ef7eb2e8f9f7 927 #define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 928 #define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 929 #define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
<> 144:ef7eb2e8f9f7 930 #define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
<> 144:ef7eb2e8f9f7 931 #define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
<> 144:ef7eb2e8f9f7 932 #define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 933 #define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 934 #define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
<> 144:ef7eb2e8f9f7 935 #define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
<> 144:ef7eb2e8f9f7 936 #define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
<> 144:ef7eb2e8f9f7 937 #define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 938 #define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 939 #define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
<> 144:ef7eb2e8f9f7 940 #define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
<> 144:ef7eb2e8f9f7 941 #define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
<> 144:ef7eb2e8f9f7 942 #define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 943 #define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 944 #define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
<> 144:ef7eb2e8f9f7 945 #define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
<> 144:ef7eb2e8f9f7 946 #define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
<> 144:ef7eb2e8f9f7 947 #define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 948 #define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Bit fields for TIMER DTLOCK */
<> 144:ef7eb2e8f9f7 951 #define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 952 #define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 953 #define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
<> 144:ef7eb2e8f9f7 954 #define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
<> 144:ef7eb2e8f9f7 955 #define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 956 #define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 957 #define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 958 #define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 959 #define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 960 #define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 961 #define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 962 #define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 963 #define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 964 #define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 /** @} End of group EFM32GG_TIMER */
<> 144:ef7eb2e8f9f7 967 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 968