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targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /******************************************************************************
<> 149:156823d33999 2 * @file spi.h
<> 149:156823d33999 3 * @version V0.10
<> 149:156823d33999 4 * $Revision: 17 $
<> 149:156823d33999 5 * $Date: 15/08/11 10:26a $
<> 149:156823d33999 6 * @brief M451 series SPI driver header file
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 *****************************************************************************/
<> 149:156823d33999 11 #ifndef __SPI_H__
<> 149:156823d33999 12 #define __SPI_H__
<> 149:156823d33999 13
<> 149:156823d33999 14 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 15 /* Include related headers */
<> 149:156823d33999 16 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 17 #include "M451Series.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #ifdef __cplusplus
<> 149:156823d33999 20 extern "C"
<> 149:156823d33999 21 {
<> 149:156823d33999 22 #endif
<> 149:156823d33999 23
<> 149:156823d33999 24
<> 149:156823d33999 25 /** @addtogroup Standard_Driver Standard Driver
<> 149:156823d33999 26 @{
<> 149:156823d33999 27 */
<> 149:156823d33999 28
<> 149:156823d33999 29 /** @addtogroup SPI_Driver SPI Driver
<> 149:156823d33999 30 @{
<> 149:156823d33999 31 */
<> 149:156823d33999 32
<> 149:156823d33999 33 /** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
<> 149:156823d33999 34 @{
<> 149:156823d33999 35 */
<> 149:156823d33999 36
<> 149:156823d33999 37 #define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
<> 149:156823d33999 38 #define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
<> 149:156823d33999 39 #define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
<> 149:156823d33999 40 #define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
<> 149:156823d33999 41
<> 149:156823d33999 42 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
<> 149:156823d33999 43 #define SPI_MASTER (0x0) /*!< Set as master */
<> 149:156823d33999 44
<> 149:156823d33999 45 #define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */
<> 149:156823d33999 46 #define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
<> 149:156823d33999 47 #define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
<> 149:156823d33999 48
<> 149:156823d33999 49 /* SPI Interrupt Mask */
<> 149:156823d33999 50 #define SPI_UNIT_INT_MASK (0x001) /*!< Unit transfer interrupt mask */
<> 149:156823d33999 51 #define SPI_SSACT_INT_MASK (0x002) /*!< Slave selection signal active interrupt mask */
<> 149:156823d33999 52 #define SPI_SSINACT_INT_MASK (0x004) /*!< Slave selection signal inactive interrupt mask */
<> 149:156823d33999 53 #define SPI_SLVUR_INT_MASK (0x008) /*!< Slave under run interrupt mask */
<> 149:156823d33999 54 #define SPI_SLVBE_INT_MASK (0x010) /*!< Slave bit count error interrupt mask */
<> 149:156823d33999 55 #define SPI_SLVTO_INT_MASK (0x020) /*!< Slave time-out interrupt mask */
<> 149:156823d33999 56 #define SPI_TXUF_INT_MASK (0x040) /*!< Slave TX underflow interrupt mask */
<> 149:156823d33999 57 #define SPI_FIFO_TXTH_INT_MASK (0x080) /*!< FIFO TX threshold interrupt mask */
<> 149:156823d33999 58 #define SPI_FIFO_RXTH_INT_MASK (0x100) /*!< FIFO RX threshold interrupt mask */
<> 149:156823d33999 59 #define SPI_FIFO_RXOV_INT_MASK (0x200) /*!< FIFO RX overrun interrupt mask */
<> 149:156823d33999 60 #define SPI_FIFO_RXTO_INT_MASK (0x400) /*!< FIFO RX time-out interrupt mask */
<> 149:156823d33999 61
<> 149:156823d33999 62 /* SPI Status Mask */
<> 149:156823d33999 63 #define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
<> 149:156823d33999 64 #define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
<> 149:156823d33999 65 #define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
<> 149:156823d33999 66 #define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
<> 149:156823d33999 67 #define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
<> 149:156823d33999 68 #define SPI_TXRX_RESET_MASK (0x20) /*!< TX or RX reset status mask */
<> 149:156823d33999 69 #define SPI_SPIEN_STS_MASK (0x40) /*!< SPIEN status mask */
<> 149:156823d33999 70 #define SPI_SSLINE_STS_MASK (0x80) /*!< SPIn_SS line status mask */
<> 149:156823d33999 71
<> 149:156823d33999 72
<> 149:156823d33999 73 /* I2S Data Width */
<> 149:156823d33999 74 #define I2S_DATABIT_8 (0 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */
<> 149:156823d33999 75 #define I2S_DATABIT_16 (1 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */
<> 149:156823d33999 76 #define I2S_DATABIT_24 (2 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */
<> 149:156823d33999 77 #define I2S_DATABIT_32 (3 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */
<> 149:156823d33999 78
<> 149:156823d33999 79 /* I2S Audio Format */
<> 149:156823d33999 80 #define I2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */
<> 149:156823d33999 81 #define I2S_STEREO 0 /*!< Stereo channel */
<> 149:156823d33999 82
<> 149:156823d33999 83 /* I2S Data Format */
<> 149:156823d33999 84 #define I2S_FORMAT_I2S (0<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */
<> 149:156823d33999 85 #define I2S_FORMAT_MSB (1<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */
<> 149:156823d33999 86 #define I2S_FORMAT_PCMA (2<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */
<> 149:156823d33999 87 #define I2S_FORMAT_PCMB (3<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */
<> 149:156823d33999 88
<> 149:156823d33999 89 /* I2S Operation mode */
<> 149:156823d33999 90 #define I2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */
<> 149:156823d33999 91 #define I2S_MODE_MASTER 0 /*!< As master mode */
<> 149:156823d33999 92
<> 149:156823d33999 93 /* I2S TX FIFO Threshold */
<> 149:156823d33999 94 #define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */
<> 149:156823d33999 95 #define I2S_FIFO_TX_LEVEL_WORD_1 (1 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */
<> 149:156823d33999 96 #define I2S_FIFO_TX_LEVEL_WORD_2 (2 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */
<> 149:156823d33999 97 #define I2S_FIFO_TX_LEVEL_WORD_3 (3 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */
<> 149:156823d33999 98 /* I2S RX FIFO Threshold */
<> 149:156823d33999 99 #define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */
<> 149:156823d33999 100 #define I2S_FIFO_RX_LEVEL_WORD_2 (1 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */
<> 149:156823d33999 101 #define I2S_FIFO_RX_LEVEL_WORD_3 (2 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */
<> 149:156823d33999 102 #define I2S_FIFO_RX_LEVEL_WORD_4 (3 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */
<> 149:156823d33999 103
<> 149:156823d33999 104 /* I2S Record Channel */
<> 149:156823d33999 105 #define I2S_MONO_RIGHT 0 /*!< Record mono right channel */
<> 149:156823d33999 106 #define I2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */
<> 149:156823d33999 107
<> 149:156823d33999 108 /* I2S Channel */
<> 149:156823d33999 109 #define I2S_RIGHT 0 /*!< Select right channel */
<> 149:156823d33999 110 #define I2S_LEFT 1 /*!< Select left channel */
<> 149:156823d33999 111
<> 149:156823d33999 112 /* I2S Interrupt Mask */
<> 149:156823d33999 113 #define I2S_FIFO_TXTH_INT_MASK (0x01) /*!< TX FIFO threshold interrupt mask */
<> 149:156823d33999 114 #define I2S_FIFO_RXTH_INT_MASK (0x02) /*!< RX FIFO threshold interrupt mask */
<> 149:156823d33999 115 #define I2S_FIFO_RXOV_INT_MASK (0x04) /*!< RX FIFO overrun interrupt mask */
<> 149:156823d33999 116 #define I2S_FIFO_RXTO_INT_MASK (0x08) /*!< RX FIFO time-out interrupt mask */
<> 149:156823d33999 117 #define I2S_TXUF_INT_MASK (0x10) /*!< TX FIFO underflow interrupt mask */
<> 149:156823d33999 118 #define I2S_RIGHT_ZC_INT_MASK (0x20) /*!< Right channel zero cross interrupt mask */
<> 149:156823d33999 119 #define I2S_LEFT_ZC_INT_MASK (0x40) /*!< Left channel zero cross interrupt mask */
<> 149:156823d33999 120
<> 149:156823d33999 121 /*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
<> 149:156823d33999 122
<> 149:156823d33999 123
<> 149:156823d33999 124 /** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
<> 149:156823d33999 125 @{
<> 149:156823d33999 126 */
<> 149:156823d33999 127
<> 149:156823d33999 128 /**
<> 149:156823d33999 129 * @brief Clear the unit transfer interrupt flag.
<> 149:156823d33999 130 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 131 * @return None.
<> 149:156823d33999 132 * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
<> 149:156823d33999 133 */
<> 149:156823d33999 134 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
<> 149:156823d33999 135
<> 149:156823d33999 136 /**
<> 149:156823d33999 137 * @brief Disable 2-bit Transfer mode.
<> 149:156823d33999 138 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 139 * @return None.
<> 149:156823d33999 140 * @details Clear TWOBIT bit of SPI_CTL register to disable 2-bit Transfer mode.
<> 149:156823d33999 141 */
<> 149:156823d33999 142 #define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CTL &= ~SPI_CTL_TWOBIT_Msk)
<> 149:156823d33999 143
<> 149:156823d33999 144 /**
<> 149:156823d33999 145 * @brief Disable Slave 3-wire mode.
<> 149:156823d33999 146 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 147 * @return None.
<> 149:156823d33999 148 * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
<> 149:156823d33999 149 */
<> 149:156823d33999 150 #define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
<> 149:156823d33999 151
<> 149:156823d33999 152 /**
<> 149:156823d33999 153 * @brief Disable Dual I/O mode.
<> 149:156823d33999 154 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 155 * @return None.
<> 149:156823d33999 156 * @details Clear DUALIOEN bit of SPI_CTL register to disable Dual I/O mode.
<> 149:156823d33999 157 */
<> 149:156823d33999 158 #define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk)
<> 149:156823d33999 159
<> 149:156823d33999 160 /**
<> 149:156823d33999 161 * @brief Disable Quad I/O mode.
<> 149:156823d33999 162 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 163 * @return None.
<> 149:156823d33999 164 * @details Clear QUADIOEN bit of SPI_CTL register to disable Quad I/O mode.
<> 149:156823d33999 165 */
<> 149:156823d33999 166 #define SPI_DISABLE_QUAD_MODE(spi) ((spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk)
<> 149:156823d33999 167
<> 149:156823d33999 168 /**
<> 149:156823d33999 169 * @brief Enable 2-bit Transfer mode.
<> 149:156823d33999 170 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 171 * @return None.
<> 149:156823d33999 172 * @details Set TWOBIT bit of SPI_CTL register to enable 2-bit Transfer mode.
<> 149:156823d33999 173 */
<> 149:156823d33999 174 #define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CTL |= SPI_CTL_TWOBIT_Msk)
<> 149:156823d33999 175
<> 149:156823d33999 176 /**
<> 149:156823d33999 177 * @brief Enable Slave 3-wire mode.
<> 149:156823d33999 178 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 179 * @return None.
<> 149:156823d33999 180 * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
<> 149:156823d33999 181 */
<> 149:156823d33999 182 #define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
<> 149:156823d33999 183
<> 149:156823d33999 184 /**
<> 149:156823d33999 185 * @brief Enable Dual input mode.
<> 149:156823d33999 186 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 187 * @return None.
<> 149:156823d33999 188 * @details Clear QDIODIR bit and set DUALIOEN bit of SPI_CTL register to enable Dual input mode.
<> 149:156823d33999 189 */
<> 149:156823d33999 190 #define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_DUALIOEN_Msk)
<> 149:156823d33999 191
<> 149:156823d33999 192 /**
<> 149:156823d33999 193 * @brief Enable Dual output mode.
<> 149:156823d33999 194 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 195 * @return None.
<> 149:156823d33999 196 * @details Set QDIODIR bit and DUALIOEN bit of SPI_CTL register to enable Dual output mode.
<> 149:156823d33999 197 */
<> 149:156823d33999 198 #define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk))
<> 149:156823d33999 199
<> 149:156823d33999 200 /**
<> 149:156823d33999 201 * @brief Enable Quad input mode.
<> 149:156823d33999 202 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 203 * @return None.
<> 149:156823d33999 204 * @details Clear QDIODIR bit and set QUADIOEN bit of SPI_CTL register to enable Quad input mode.
<> 149:156823d33999 205 */
<> 149:156823d33999 206 #define SPI_ENABLE_QUAD_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_QUADIOEN_Msk)
<> 149:156823d33999 207
<> 149:156823d33999 208 /**
<> 149:156823d33999 209 * @brief Enable Quad output mode.
<> 149:156823d33999 210 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 211 * @return None.
<> 149:156823d33999 212 * @details Set QDIODIR bit and QUADIOEN bit of SPI_CTL register to enable Quad output mode.
<> 149:156823d33999 213 */
<> 149:156823d33999 214 #define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk))
<> 149:156823d33999 215
<> 149:156823d33999 216 /**
<> 149:156823d33999 217 * @brief Trigger RX PDMA function.
<> 149:156823d33999 218 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 219 * @return None.
<> 149:156823d33999 220 * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
<> 149:156823d33999 221 */
<> 149:156823d33999 222 #define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
<> 149:156823d33999 223
<> 149:156823d33999 224 /**
<> 149:156823d33999 225 * @brief Trigger TX PDMA function.
<> 149:156823d33999 226 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 227 * @return None.
<> 149:156823d33999 228 * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
<> 149:156823d33999 229 */
<> 149:156823d33999 230 #define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
<> 149:156823d33999 231
<> 149:156823d33999 232 /**
<> 149:156823d33999 233 * @brief Disable RX PDMA transfer.
<> 149:156823d33999 234 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 235 * @return None.
<> 149:156823d33999 236 * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
<> 149:156823d33999 237 */
<> 149:156823d33999 238 #define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
<> 149:156823d33999 239
<> 149:156823d33999 240 /**
<> 149:156823d33999 241 * @brief Disable TX PDMA transfer.
<> 149:156823d33999 242 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 243 * @return None.
<> 149:156823d33999 244 * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
<> 149:156823d33999 245 */
<> 149:156823d33999 246 #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
<> 149:156823d33999 247
<> 149:156823d33999 248 /**
<> 149:156823d33999 249 * @brief Get the count of available data in RX FIFO.
<> 149:156823d33999 250 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 251 * @return The count of available data in RX FIFO.
<> 149:156823d33999 252 * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
<> 149:156823d33999 253 */
<> 149:156823d33999 254 #define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
<> 149:156823d33999 255
<> 149:156823d33999 256 /**
<> 149:156823d33999 257 * @brief Get the RX FIFO empty flag.
<> 149:156823d33999 258 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 259 * @retval 0 RX FIFO is not empty.
<> 149:156823d33999 260 * @retval 1 RX FIFO is empty.
<> 149:156823d33999 261 * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
<> 149:156823d33999 262 */
<> 149:156823d33999 263 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
<> 149:156823d33999 264
<> 149:156823d33999 265 /**
<> 149:156823d33999 266 * @brief Get the TX FIFO empty flag.
<> 149:156823d33999 267 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 268 * @retval 0 TX FIFO is not empty.
<> 149:156823d33999 269 * @retval 1 TX FIFO is empty.
<> 149:156823d33999 270 * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
<> 149:156823d33999 271 */
<> 149:156823d33999 272 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
<> 149:156823d33999 273
<> 149:156823d33999 274 /**
<> 149:156823d33999 275 * @brief Get the TX FIFO full flag.
<> 149:156823d33999 276 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 277 * @retval 0 TX FIFO is not full.
<> 149:156823d33999 278 * @retval 1 TX FIFO is full.
<> 149:156823d33999 279 * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
<> 149:156823d33999 280 */
<> 149:156823d33999 281 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
<> 149:156823d33999 282
<> 149:156823d33999 283 /**
<> 149:156823d33999 284 * @brief Get the datum read from RX register.
<> 149:156823d33999 285 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 286 * @return Data in RX register.
<> 149:156823d33999 287 * @details Read SPI_RX register to get the received datum.
<> 149:156823d33999 288 */
<> 149:156823d33999 289 #define SPI_READ_RX(spi) ((spi)->RX)
<> 149:156823d33999 290
<> 149:156823d33999 291 /**
<> 149:156823d33999 292 * @brief Write datum to TX register.
<> 149:156823d33999 293 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 294 * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
<> 149:156823d33999 295 * @return None.
<> 149:156823d33999 296 * @details Write u32TxData to SPI_TX register.
<> 149:156823d33999 297 */
<> 149:156823d33999 298 #define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
<> 149:156823d33999 299
<> 149:156823d33999 300 /**
<> 149:156823d33999 301 * @brief Set SPIn_SS pin to high state.
<> 149:156823d33999 302 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 303 * @return None.
<> 149:156823d33999 304 * @details Disable automatic slave selection function and set SPIn_SS pin to high state.
<> 149:156823d33999 305 */
<> 149:156823d33999 306 #define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
<> 149:156823d33999 307
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @brief Set SPIn_SS pin to low state.
<> 149:156823d33999 310 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 311 * @return None.
<> 149:156823d33999 312 * @details Disable automatic slave selection function and set SPIn_SS pin to low state.
<> 149:156823d33999 313 */
<> 149:156823d33999 314 #define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
<> 149:156823d33999 315
<> 149:156823d33999 316 /**
<> 149:156823d33999 317 * @brief Enable Byte Reorder function.
<> 149:156823d33999 318 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 319 * @return None.
<> 149:156823d33999 320 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
<> 149:156823d33999 321 */
<> 149:156823d33999 322 #define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
<> 149:156823d33999 323
<> 149:156823d33999 324 /**
<> 149:156823d33999 325 * @brief Disable Byte Reorder function.
<> 149:156823d33999 326 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 327 * @return None.
<> 149:156823d33999 328 * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
<> 149:156823d33999 329 */
<> 149:156823d33999 330 #define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
<> 149:156823d33999 331
<> 149:156823d33999 332 /**
<> 149:156823d33999 333 * @brief Set the length of suspend interval.
<> 149:156823d33999 334 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 335 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
<> 149:156823d33999 336 * @return None.
<> 149:156823d33999 337 * @details Set the length of suspend interval according to u32SuspCycle.
<> 149:156823d33999 338 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
<> 149:156823d33999 339 */
<> 149:156823d33999 340 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
<> 149:156823d33999 341
<> 149:156823d33999 342 /**
<> 149:156823d33999 343 * @brief Set the SPI transfer sequence with LSB first.
<> 149:156823d33999 344 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 345 * @return None.
<> 149:156823d33999 346 * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
<> 149:156823d33999 347 */
<> 149:156823d33999 348 #define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
<> 149:156823d33999 349
<> 149:156823d33999 350 /**
<> 149:156823d33999 351 * @brief Set the SPI transfer sequence with MSB first.
<> 149:156823d33999 352 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 353 * @return None.
<> 149:156823d33999 354 * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
<> 149:156823d33999 355 */
<> 149:156823d33999 356 #define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
<> 149:156823d33999 357
<> 149:156823d33999 358 /**
<> 149:156823d33999 359 * @brief Set the data width of a SPI transaction.
<> 149:156823d33999 360 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 361 * @param[in] u32Width The bit width of one transaction.
<> 149:156823d33999 362 * @return None.
<> 149:156823d33999 363 * @details The data width can be 8 ~ 32 bits.
<> 149:156823d33999 364 */
<> 149:156823d33999 365 #define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
<> 149:156823d33999 366
<> 149:156823d33999 367 /**
<> 149:156823d33999 368 * @brief Get the SPI busy state.
<> 149:156823d33999 369 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 370 * @retval 0 SPI controller is not busy.
<> 149:156823d33999 371 * @retval 1 SPI controller is busy.
<> 149:156823d33999 372 * @details This macro will return the busy state of SPI controller.
<> 149:156823d33999 373 */
<> 149:156823d33999 374 #define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
<> 149:156823d33999 375
<> 149:156823d33999 376 /**
<> 149:156823d33999 377 * @brief Enable SPI controller.
<> 149:156823d33999 378 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 379 * @return None.
<> 149:156823d33999 380 * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
<> 149:156823d33999 381 */
<> 149:156823d33999 382 #define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
<> 149:156823d33999 383
<> 149:156823d33999 384 /**
<> 149:156823d33999 385 * @brief Disable SPI controller.
<> 149:156823d33999 386 * @param[in] spi The pointer of the specified SPI module.
<> 149:156823d33999 387 * @return None.
<> 149:156823d33999 388 * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
<> 149:156823d33999 389 */
<> 149:156823d33999 390 #define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
<> 149:156823d33999 391
<> 149:156823d33999 392
<> 149:156823d33999 393 /**
<> 149:156823d33999 394 * @brief Enable zero cross detection function.
<> 149:156823d33999 395 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 396 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
<> 149:156823d33999 397 * - \ref I2S_RIGHT
<> 149:156823d33999 398 * - \ref I2S_LEFT
<> 149:156823d33999 399 * @return None
<> 149:156823d33999 400 * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
<> 149:156823d33999 401 */
<> 149:156823d33999 402 static __INLINE void I2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
<> 149:156823d33999 403 {
<> 149:156823d33999 404 if(u32ChMask == I2S_RIGHT)
<> 149:156823d33999 405 i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
<> 149:156823d33999 406 else
<> 149:156823d33999 407 i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
<> 149:156823d33999 408 }
<> 149:156823d33999 409
<> 149:156823d33999 410 /**
<> 149:156823d33999 411 * @brief Disable zero cross detection function.
<> 149:156823d33999 412 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 413 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
<> 149:156823d33999 414 * - \ref I2S_RIGHT
<> 149:156823d33999 415 * - \ref I2S_LEFT
<> 149:156823d33999 416 * @return None
<> 149:156823d33999 417 * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
<> 149:156823d33999 418 */
<> 149:156823d33999 419 static __INLINE void I2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
<> 149:156823d33999 420 {
<> 149:156823d33999 421 if(u32ChMask == I2S_RIGHT)
<> 149:156823d33999 422 i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
<> 149:156823d33999 423 else
<> 149:156823d33999 424 i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
<> 149:156823d33999 425 }
<> 149:156823d33999 426
<> 149:156823d33999 427 /**
<> 149:156823d33999 428 * @brief Enable I2S TX DMA function.
<> 149:156823d33999 429 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 430 * @return None
<> 149:156823d33999 431 * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
<> 149:156823d33999 432 */
<> 149:156823d33999 433 #define I2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
<> 149:156823d33999 434
<> 149:156823d33999 435 /**
<> 149:156823d33999 436 * @brief Disable I2S TX DMA function.
<> 149:156823d33999 437 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 438 * @return None
<> 149:156823d33999 439 * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
<> 149:156823d33999 440 */
<> 149:156823d33999 441 #define I2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
<> 149:156823d33999 442
<> 149:156823d33999 443 /**
<> 149:156823d33999 444 * @brief Enable I2S RX DMA function.
<> 149:156823d33999 445 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 446 * @return None
<> 149:156823d33999 447 * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
<> 149:156823d33999 448 */
<> 149:156823d33999 449 #define I2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
<> 149:156823d33999 450
<> 149:156823d33999 451 /**
<> 149:156823d33999 452 * @brief Disable I2S RX DMA function.
<> 149:156823d33999 453 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 454 * @return None
<> 149:156823d33999 455 * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
<> 149:156823d33999 456 */
<> 149:156823d33999 457 #define I2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
<> 149:156823d33999 458
<> 149:156823d33999 459 /**
<> 149:156823d33999 460 * @brief Enable I2S TX function.
<> 149:156823d33999 461 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 462 * @return None
<> 149:156823d33999 463 * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
<> 149:156823d33999 464 */
<> 149:156823d33999 465 #define I2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
<> 149:156823d33999 466
<> 149:156823d33999 467 /**
<> 149:156823d33999 468 * @brief Disable I2S TX function.
<> 149:156823d33999 469 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 470 * @return None
<> 149:156823d33999 471 * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
<> 149:156823d33999 472 */
<> 149:156823d33999 473 #define I2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
<> 149:156823d33999 474
<> 149:156823d33999 475 /**
<> 149:156823d33999 476 * @brief Enable I2S RX function.
<> 149:156823d33999 477 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 478 * @return None
<> 149:156823d33999 479 * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
<> 149:156823d33999 480 */
<> 149:156823d33999 481 #define I2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
<> 149:156823d33999 482
<> 149:156823d33999 483 /**
<> 149:156823d33999 484 * @brief Disable I2S RX function.
<> 149:156823d33999 485 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 486 * @return None
<> 149:156823d33999 487 * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
<> 149:156823d33999 488 */
<> 149:156823d33999 489 #define I2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
<> 149:156823d33999 490
<> 149:156823d33999 491 /**
<> 149:156823d33999 492 * @brief Enable TX Mute function.
<> 149:156823d33999 493 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 494 * @return None
<> 149:156823d33999 495 * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
<> 149:156823d33999 496 */
<> 149:156823d33999 497 #define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
<> 149:156823d33999 498
<> 149:156823d33999 499 /**
<> 149:156823d33999 500 * @brief Disable TX Mute function.
<> 149:156823d33999 501 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 502 * @return None
<> 149:156823d33999 503 * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
<> 149:156823d33999 504 */
<> 149:156823d33999 505 #define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
<> 149:156823d33999 506
<> 149:156823d33999 507 /**
<> 149:156823d33999 508 * @brief Clear TX FIFO.
<> 149:156823d33999 509 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 510 * @return None
<> 149:156823d33999 511 * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
<> 149:156823d33999 512 */
<> 149:156823d33999 513 #define I2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
<> 149:156823d33999 514
<> 149:156823d33999 515 /**
<> 149:156823d33999 516 * @brief Clear RX FIFO.
<> 149:156823d33999 517 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 518 * @return None
<> 149:156823d33999 519 * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
<> 149:156823d33999 520 */
<> 149:156823d33999 521 #define I2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
<> 149:156823d33999 522
<> 149:156823d33999 523 /**
<> 149:156823d33999 524 * @brief This function sets the recording source channel when mono mode is used.
<> 149:156823d33999 525 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 526 * @param[in] u32Ch left or right channel. Valid values are:
<> 149:156823d33999 527 * - \ref I2S_MONO_LEFT
<> 149:156823d33999 528 * - \ref I2S_MONO_RIGHT
<> 149:156823d33999 529 * @return None
<> 149:156823d33999 530 * @details This function selects the recording source channel of monaural mode.
<> 149:156823d33999 531 */
<> 149:156823d33999 532 static __INLINE void I2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
<> 149:156823d33999 533 {
<> 149:156823d33999 534 u32Ch == I2S_MONO_LEFT ?
<> 149:156823d33999 535 (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
<> 149:156823d33999 536 (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
<> 149:156823d33999 537 }
<> 149:156823d33999 538
<> 149:156823d33999 539 /**
<> 149:156823d33999 540 * @brief Write data to I2S TX FIFO.
<> 149:156823d33999 541 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 542 * @param[in] u32Data The value written to TX FIFO.
<> 149:156823d33999 543 * @return None
<> 149:156823d33999 544 * @details This macro will write a value to TX FIFO.
<> 149:156823d33999 545 */
<> 149:156823d33999 546 #define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
<> 149:156823d33999 547
<> 149:156823d33999 548 /**
<> 149:156823d33999 549 * @brief Read RX FIFO.
<> 149:156823d33999 550 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 551 * @return The value read from RX FIFO.
<> 149:156823d33999 552 * @details This function will return a value read from RX FIFO.
<> 149:156823d33999 553 */
<> 149:156823d33999 554 #define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
<> 149:156823d33999 555
<> 149:156823d33999 556 /**
<> 149:156823d33999 557 * @brief Get the interrupt flag.
<> 149:156823d33999 558 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 559 * @param[in] u32Mask The mask value for all interrupt flags.
<> 149:156823d33999 560 * @return The interrupt flags specified by the u32mask parameter.
<> 149:156823d33999 561 * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
<> 149:156823d33999 562 */
<> 149:156823d33999 563 #define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
<> 149:156823d33999 564
<> 149:156823d33999 565 /**
<> 149:156823d33999 566 * @brief Clear the interrupt flag.
<> 149:156823d33999 567 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 568 * @param[in] u32Mask The mask value for all interrupt flags.
<> 149:156823d33999 569 * @return None
<> 149:156823d33999 570 * @details This macro will clear the interrupt flags specified by the u32mask parameter.
<> 149:156823d33999 571 * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
<> 149:156823d33999 572 */
<> 149:156823d33999 573 #define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
<> 149:156823d33999 574
<> 149:156823d33999 575 /**
<> 149:156823d33999 576 * @brief Get transmit FIFO level
<> 149:156823d33999 577 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 578 * @return TX FIFO level
<> 149:156823d33999 579 * @details This macro will return the number of available words in TX FIFO.
<> 149:156823d33999 580 */
<> 149:156823d33999 581 #define I2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
<> 149:156823d33999 582
<> 149:156823d33999 583 /**
<> 149:156823d33999 584 * @brief Get receive FIFO level
<> 149:156823d33999 585 * @param[in] i2s The pointer of the specified I2S module.
<> 149:156823d33999 586 * @return RX FIFO level
<> 149:156823d33999 587 * @details This macro will return the number of available words in RX FIFO.
<> 149:156823d33999 588 */
<> 149:156823d33999 589 #define I2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
<> 149:156823d33999 590
<> 149:156823d33999 591
<> 149:156823d33999 592
<> 149:156823d33999 593 /* Function prototype declaration */
<> 149:156823d33999 594 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
<> 149:156823d33999 595 void SPI_Close(SPI_T *spi);
<> 149:156823d33999 596 void SPI_ClearRxFIFO(SPI_T *spi);
<> 149:156823d33999 597 void SPI_ClearTxFIFO(SPI_T *spi);
<> 149:156823d33999 598 void SPI_DisableAutoSS(SPI_T *spi);
<> 149:156823d33999 599 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
<> 149:156823d33999 600 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
<> 149:156823d33999 601 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
<> 149:156823d33999 602 uint32_t SPI_GetBusClock(SPI_T *spi);
<> 149:156823d33999 603 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
<> 149:156823d33999 604 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
<> 149:156823d33999 605 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
<> 149:156823d33999 606 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
<> 149:156823d33999 607 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
<> 149:156823d33999 608
<> 149:156823d33999 609 uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
<> 149:156823d33999 610 void I2S_Close(SPI_T *i2s);
<> 149:156823d33999 611 void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
<> 149:156823d33999 612 void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
<> 149:156823d33999 613 uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
<> 149:156823d33999 614 void I2S_DisableMCLK(SPI_T *i2s);
<> 149:156823d33999 615 void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
<> 149:156823d33999 616
<> 149:156823d33999 617
<> 149:156823d33999 618 /*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
<> 149:156823d33999 619
<> 149:156823d33999 620 /*@}*/ /* end of group SPI_Driver */
<> 149:156823d33999 621
<> 149:156823d33999 622 /*@}*/ /* end of group Standard_Driver */
<> 149:156823d33999 623
<> 149:156823d33999 624 #ifdef __cplusplus
<> 149:156823d33999 625 }
<> 149:156823d33999 626 #endif
<> 149:156823d33999 627
<> 149:156823d33999 628 #endif //__SPI_H__
<> 149:156823d33999 629
<> 149:156823d33999 630 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/