Brandon Modon / Encoder_Nucleo_16_bits

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Nucleo_Encoder_16_bits.cpp@7:cd502aeab71a, 2017-02-21 (annotated)

Committer:
Brand101
Date:
Tue Feb 21 15:33:10 2017 +0000
Revision:
7:cd502aeab71a
Parent:
3:f0450e2b0d47 
45465446

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kkoichy 0:ebd170807e11 1 #include "Nucleo_Encoder_16_bits.h"
kkoichy 0:ebd170807e11 2
kkoichy 3:f0450e2b0d47 3 int32_t Soft_32_Counter_TIM1, Soft_32_Counter_TIM2, Soft_32_Counter_TIM3, Soft_32_Counter_TIM4, Soft_32_Counter_TIM5;
kkoichy 3:f0450e2b0d47 4
kkoichy 3:f0450e2b0d47 5 void Overflow_Routine_TIM1()
kkoichy 3:f0450e2b0d47 6 {
kkoichy 3:f0450e2b0d47 7 if(TIM1->SR & 0x0001)
kkoichy 3:f0450e2b0d47 8 {
kkoichy 3:f0450e2b0d47 9 printf("Overflow Routine TIM2");
kkoichy 3:f0450e2b0d47 10 TIM1->SR &= 0xfffe;
kkoichy 3:f0450e2b0d47 11 if(!(TIM1->CR1&TIM_CR1_DIR))
kkoichy 3:f0450e2b0d47 12 Soft_32_Counter_TIM1 += 0xffff;
kkoichy 3:f0450e2b0d47 13 else
kkoichy 3:f0450e2b0d47 14 Soft_32_Counter_TIM1 -= 0xffff;
kkoichy 3:f0450e2b0d47 15 }
kkoichy 3:f0450e2b0d47 16 }
kkoichy 0:ebd170807e11 17
kkoichy 0:ebd170807e11 18 void Overflow_Routine_TIM2()
kkoichy 0:ebd170807e11 19 {
kkoichy 0:ebd170807e11 20 if(TIM2->SR & 0x0001)
kkoichy 0:ebd170807e11 21 {
kkoichy 3:f0450e2b0d47 22 printf("Overflow Routine TIM2");
kkoichy 0:ebd170807e11 23 TIM2->SR &= 0xfffe;
kkoichy 0:ebd170807e11 24 if(!(TIM2->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 25 Soft_32_Counter_TIM2 += 0xffff;
kkoichy 0:ebd170807e11 26 else
kkoichy 0:ebd170807e11 27 Soft_32_Counter_TIM2 -= 0xffff;
kkoichy 0:ebd170807e11 28 }
kkoichy 0:ebd170807e11 29 }
kkoichy 0:ebd170807e11 30
kkoichy 0:ebd170807e11 31 void Overflow_Routine_TIM3()
kkoichy 0:ebd170807e11 32 {
kkoichy 0:ebd170807e11 33 if(TIM3->SR & 0x0001)
kkoichy 0:ebd170807e11 34 {
kkoichy 3:f0450e2b0d47 35 printf("Overflow Routine TIM3");
kkoichy 0:ebd170807e11 36 TIM3->SR &= 0xfffe;
kkoichy 0:ebd170807e11 37 if(!(TIM3->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 38 Soft_32_Counter_TIM3 += 0xffff;
kkoichy 0:ebd170807e11 39 else
kkoichy 0:ebd170807e11 40 Soft_32_Counter_TIM3 -= 0xffff;
kkoichy 0:ebd170807e11 41 }
kkoichy 0:ebd170807e11 42 }
kkoichy 0:ebd170807e11 43 void Overflow_Routine_TIM4()
kkoichy 0:ebd170807e11 44 {
kkoichy 0:ebd170807e11 45 if(TIM4->SR & 0x0001)
kkoichy 0:ebd170807e11 46 {
kkoichy 3:f0450e2b0d47 47 printf("Overflow Routine TIM4");
kkoichy 0:ebd170807e11 48 TIM4->SR &= 0xfffe;
kkoichy 0:ebd170807e11 49 if(!(TIM4->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 50 Soft_32_Counter_TIM4 += 0xffff;
kkoichy 0:ebd170807e11 51 else
kkoichy 0:ebd170807e11 52 Soft_32_Counter_TIM4 -= 0xffff;
kkoichy 0:ebd170807e11 53 }
kkoichy 0:ebd170807e11 54 }
kkoichy 0:ebd170807e11 55 void Overflow_Routine_TIM5()
kkoichy 0:ebd170807e11 56 {
kkoichy 0:ebd170807e11 57 if(TIM5->SR & 0x0001)
kkoichy 0:ebd170807e11 58 {
kkoichy 3:f0450e2b0d47 59 printf("Overflow Routine TIM5");
kkoichy 0:ebd170807e11 60 TIM5->SR &= 0xfffe;
kkoichy 0:ebd170807e11 61 if(!(TIM5->CR1&TIM_CR1_DIR))
kkoichy 0:ebd170807e11 62 Soft_32_Counter_TIM5 += 0xffff;
kkoichy 0:ebd170807e11 63 else
kkoichy 0:ebd170807e11 64 Soft_32_Counter_TIM5 -= 0xffff;
kkoichy 0:ebd170807e11 65 }
kkoichy 0:ebd170807e11 66 }
kkoichy 0:ebd170807e11 67
kkoichy 0:ebd170807e11 68 namespace mbed
kkoichy 0:ebd170807e11 69 {
kkoichy 1:e82009479b5c 70
kkoichy 1:e82009479b5c 71 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM)
kkoichy 1:e82009479b5c 72 {
kkoichy 1:e82009479b5c 73 TIM = _TIM;
kkoichy 1:e82009479b5c 74 // Initialisation of the TIM module as an encoder counter
kkoichy 1:e82009479b5c 75 EncoderInit(&encoder, &timer, _TIM, 0xffff, TIM_ENCODERMODE_TI12);
kkoichy 1:e82009479b5c 76
kkoichy 1:e82009479b5c 77 // Update (aka over- and underflow) interrupt enabled
kkoichy 1:e82009479b5c 78 TIM->DIER |= 0x0001;
kkoichy 1:e82009479b5c 79 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 1:e82009479b5c 80 TIM->SR &= 0xfffe;
kkoichy 1:e82009479b5c 81
kkoichy 1:e82009479b5c 82 // Setting the ISR for the corresponding interrupt vector
kkoichy 1:e82009479b5c 83 switch((uint32_t)TIM)
kkoichy 1:e82009479b5c 84 {
kkoichy 1:e82009479b5c 85 case TIM2_BASE :
kkoichy 1:e82009479b5c 86 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 1:e82009479b5c 87 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 1:e82009479b5c 88 Soft_32_Counter_TIM2 = 0;
kkoichy 1:e82009479b5c 89 break;
kkoichy 1:e82009479b5c 90
kkoichy 1:e82009479b5c 91 case TIM3_BASE :
kkoichy 1:e82009479b5c 92 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 1:e82009479b5c 93 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 1:e82009479b5c 94 Soft_32_Counter_TIM3 = 0;
kkoichy 1:e82009479b5c 95 break;
kkoichy 1:e82009479b5c 96
kkoichy 1:e82009479b5c 97 case TIM4_BASE :
kkoichy 1:e82009479b5c 98 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 1:e82009479b5c 99 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 1:e82009479b5c 100 Soft_32_Counter_TIM4 = 0;
kkoichy 1:e82009479b5c 101 break;
kkoichy 1:e82009479b5c 102
kkoichy 1:e82009479b5c 103 case TIM5_BASE :
kkoichy 1:e82009479b5c 104 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 1:e82009479b5c 105 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 1:e82009479b5c 106 Soft_32_Counter_TIM5 = 0;
kkoichy 1:e82009479b5c 107 break;
kkoichy 1:e82009479b5c 108
kkoichy 1:e82009479b5c 109 default :
kkoichy 1:e82009479b5c 110
kkoichy 1:e82009479b5c 111 break;
kkoichy 1:e82009479b5c 112 }
kkoichy 1:e82009479b5c 113
kkoichy 1:e82009479b5c 114 }
kkoichy 0:ebd170807e11 115 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 116 {
kkoichy 0:ebd170807e11 117 TIM = _TIM;
kkoichy 0:ebd170807e11 118 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 119 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 120
kkoichy 0:ebd170807e11 121 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 122 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 123 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 124 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 125
kkoichy 0:ebd170807e11 126 // Setting the ISR for the corresponding interrupt vector
kkoichy 0:ebd170807e11 127 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 128 {
kkoichy 0:ebd170807e11 129 case TIM2_BASE :
kkoichy 0:ebd170807e11 130 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 0:ebd170807e11 131 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 0:ebd170807e11 132 Soft_32_Counter_TIM2 = 0;
kkoichy 0:ebd170807e11 133 break;
kkoichy 0:ebd170807e11 134
kkoichy 0:ebd170807e11 135 case TIM3_BASE :
kkoichy 0:ebd170807e11 136 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 0:ebd170807e11 137 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 0:ebd170807e11 138 Soft_32_Counter_TIM3 = 0;
kkoichy 0:ebd170807e11 139 break;
kkoichy 0:ebd170807e11 140
kkoichy 0:ebd170807e11 141 case TIM4_BASE :
kkoichy 0:ebd170807e11 142 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 0:ebd170807e11 143 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 0:ebd170807e11 144 Soft_32_Counter_TIM4 = 0;
kkoichy 0:ebd170807e11 145 break;
kkoichy 0:ebd170807e11 146
kkoichy 0:ebd170807e11 147 case TIM5_BASE :
kkoichy 0:ebd170807e11 148 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 0:ebd170807e11 149 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 0:ebd170807e11 150 Soft_32_Counter_TIM5 = 0;
kkoichy 0:ebd170807e11 151 break;
kkoichy 0:ebd170807e11 152
kkoichy 0:ebd170807e11 153 default :
kkoichy 0:ebd170807e11 154
kkoichy 0:ebd170807e11 155 break;
kkoichy 0:ebd170807e11 156 }
kkoichy 0:ebd170807e11 157
kkoichy 0:ebd170807e11 158 }
kkoichy 0:ebd170807e11 159
kkoichy 0:ebd170807e11 160 Nucleo_Encoder_16_bits::Nucleo_Encoder_16_bits(TIM_Encoder_InitTypeDef * _encoder, TIM_HandleTypeDef * _timer, TIM_TypeDef * _TIM, uint32_t _maxcount, uint32_t _encmode)
kkoichy 0:ebd170807e11 161 {
kkoichy 0:ebd170807e11 162 timer = *_timer;
kkoichy 0:ebd170807e11 163 encoder = *_encoder;
kkoichy 0:ebd170807e11 164 TIM = _TIM;
kkoichy 0:ebd170807e11 165 // Initialisation of the TIM module as an encoder counter
kkoichy 0:ebd170807e11 166 EncoderInit(&encoder, &timer, _TIM, _maxcount, _encmode);
kkoichy 0:ebd170807e11 167
kkoichy 0:ebd170807e11 168 // Update (aka over- and underflow) interrupt enabled
kkoichy 0:ebd170807e11 169 TIM->DIER |= 0x0001;
kkoichy 0:ebd170807e11 170 // The initialisation process generates an update interrupt, so we'll have to clear the update flag before anything else
kkoichy 0:ebd170807e11 171 TIM->SR &= 0xfffe;
kkoichy 0:ebd170807e11 172
kkoichy 0:ebd170807e11 173 // Setting the ISR for the corresponding interrupt vector
kkoichy 0:ebd170807e11 174 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 175 {
kkoichy 0:ebd170807e11 176 case TIM2_BASE :
kkoichy 0:ebd170807e11 177 NVIC_SetVector(TIM2_IRQn, (uint32_t)&Overflow_Routine_TIM2);
kkoichy 0:ebd170807e11 178 NVIC_EnableIRQ(TIM2_IRQn);
kkoichy 0:ebd170807e11 179 Soft_32_Counter_TIM2 = 0;
kkoichy 0:ebd170807e11 180 break;
kkoichy 0:ebd170807e11 181
kkoichy 0:ebd170807e11 182 case TIM3_BASE :
kkoichy 0:ebd170807e11 183 NVIC_SetVector(TIM3_IRQn, (uint32_t)&Overflow_Routine_TIM3);
kkoichy 0:ebd170807e11 184 NVIC_EnableIRQ(TIM3_IRQn);
kkoichy 0:ebd170807e11 185 Soft_32_Counter_TIM3 = 0;
kkoichy 0:ebd170807e11 186 break;
kkoichy 0:ebd170807e11 187
kkoichy 0:ebd170807e11 188 case TIM4_BASE :
kkoichy 0:ebd170807e11 189 NVIC_SetVector(TIM4_IRQn, (uint32_t)&Overflow_Routine_TIM4);
kkoichy 0:ebd170807e11 190 NVIC_EnableIRQ(TIM4_IRQn);
kkoichy 0:ebd170807e11 191 Soft_32_Counter_TIM4 = 0;
kkoichy 0:ebd170807e11 192 break;
kkoichy 0:ebd170807e11 193
kkoichy 0:ebd170807e11 194 case TIM5_BASE :
kkoichy 0:ebd170807e11 195 NVIC_SetVector(TIM5_IRQn, (uint32_t)&Overflow_Routine_TIM5);
kkoichy 0:ebd170807e11 196 NVIC_EnableIRQ(TIM5_IRQn);
kkoichy 0:ebd170807e11 197 Soft_32_Counter_TIM5 = 0;
kkoichy 0:ebd170807e11 198 break;
kkoichy 0:ebd170807e11 199
kkoichy 0:ebd170807e11 200 default :
kkoichy 0:ebd170807e11 201
kkoichy 0:ebd170807e11 202 break;
kkoichy 0:ebd170807e11 203 }
kkoichy 0:ebd170807e11 204
kkoichy 0:ebd170807e11 205 }
kkoichy 0:ebd170807e11 206
kkoichy 0:ebd170807e11 207
kkoichy 0:ebd170807e11 208 int32_t Nucleo_Encoder_16_bits::GetCounter()
kkoichy 0:ebd170807e11 209 {
kkoichy 0:ebd170807e11 210 uint16_t count = TIM->CNT;
kkoichy 0:ebd170807e11 211 switch((uint32_t)TIM)
kkoichy 0:ebd170807e11 212 {
kkoichy 0:ebd170807e11 213 case TIM2_BASE :
kkoichy 0:ebd170807e11 214 return (int32_t)count + Soft_32_Counter_TIM2;
kkoichy 0:ebd170807e11 215 break;
kkoichy 0:ebd170807e11 216
kkoichy 0:ebd170807e11 217 case TIM3_BASE :
kkoichy 0:ebd170807e11 218 return (int32_t)count + Soft_32_Counter_TIM3;
kkoichy 0:ebd170807e11 219 break;
kkoichy 0:ebd170807e11 220
kkoichy 0:ebd170807e11 221 case TIM4_BASE :
kkoichy 0:ebd170807e11 222 return (int32_t)count + Soft_32_Counter_TIM4;
kkoichy 0:ebd170807e11 223 break;
kkoichy 0:ebd170807e11 224
kkoichy 0:ebd170807e11 225 case TIM5_BASE :
kkoichy 0:ebd170807e11 226 return (int32_t)count + Soft_32_Counter_TIM5;
kkoichy 0:ebd170807e11 227 break;
kkoichy 0:ebd170807e11 228 }
kkoichy 0:ebd170807e11 229
kkoichy 0:ebd170807e11 230 return (int32_t)count;
kkoichy 0:ebd170807e11 231 }
kkoichy 0:ebd170807e11 232
kkoichy 0:ebd170807e11 233 TIM_HandleTypeDef* Nucleo_Encoder_16_bits::GetTimer()
kkoichy 0:ebd170807e11 234 {
kkoichy 0:ebd170807e11 235 return &timer;
kkoichy 0:ebd170807e11 236 }
kkoichy 0:ebd170807e11 237
kkoichy 0:ebd170807e11 238
kkoichy 0:ebd170807e11 239
kkoichy 0:ebd170807e11 240
kkoichy 0:ebd170807e11 241
kkoichy 0:ebd170807e11 242
kkoichy 0:ebd170807e11 243 }