Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/src/lpc17xx_emac.c@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 #ifdef __LPC17XX__
Michael J. Spencer 2:1df0b61d3b5a 2
Michael J. Spencer 2:1df0b61d3b5a 3 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 4 * $Id$ lpc17xx_dac.c 2010-05-21
Michael J. Spencer 2:1df0b61d3b5a 5 *//**
Michael J. Spencer 2:1df0b61d3b5a 6 * @file lpc17xx_dac.c
Michael J. Spencer 2:1df0b61d3b5a 7 * @brief Contains all functions support for Ethernet MAC firmware
Michael J. Spencer 2:1df0b61d3b5a 8 * library on LPC17xx
Michael J. Spencer 2:1df0b61d3b5a 9 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 10 * @date 21. May. 2010
Michael J. Spencer 2:1df0b61d3b5a 11 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 12 *
Michael J. Spencer 2:1df0b61d3b5a 13 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 14 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 15 *
Michael J. Spencer 2:1df0b61d3b5a 16 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 17 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 18 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 19 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 20 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 21 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 22 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 23 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 24 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 25 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 26 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 27 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 28
Michael J. Spencer 2:1df0b61d3b5a 29 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 30 /** @addtogroup EMAC
Michael J. Spencer 2:1df0b61d3b5a 31 * @{
Michael J. Spencer 2:1df0b61d3b5a 32 */
Michael J. Spencer 2:1df0b61d3b5a 33
Michael J. Spencer 2:1df0b61d3b5a 34 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 35 #include "lpc17xx_emac.h"
Michael J. Spencer 2:1df0b61d3b5a 36 #include "lpc17xx_clkpwr.h"
Michael J. Spencer 2:1df0b61d3b5a 37
Michael J. Spencer 2:1df0b61d3b5a 38 /* If this source file built with example, the LPC17xx FW library configuration
Michael J. Spencer 2:1df0b61d3b5a 39 * file in each example directory ("lpc17xx_libcfg.h") must be included,
Michael J. Spencer 2:1df0b61d3b5a 40 * otherwise the default FW library configuration file must be included instead
Michael J. Spencer 2:1df0b61d3b5a 41 */
Michael J. Spencer 2:1df0b61d3b5a 42 #ifdef __BUILD_WITH_EXAMPLE__
Michael J. Spencer 2:1df0b61d3b5a 43 #include "lpc17xx_libcfg.h"
Michael J. Spencer 2:1df0b61d3b5a 44 #else
Michael J. Spencer 2:1df0b61d3b5a 45 #include "lpc17xx_libcfg_default.h"
Michael J. Spencer 2:1df0b61d3b5a 46 #endif /* __BUILD_WITH_EXAMPLE__ */
Michael J. Spencer 2:1df0b61d3b5a 47
Michael J. Spencer 2:1df0b61d3b5a 48
Michael J. Spencer 2:1df0b61d3b5a 49 #ifdef _EMAC
Michael J. Spencer 2:1df0b61d3b5a 50
Michael J. Spencer 2:1df0b61d3b5a 51 /* Private Variables ---------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 52 /** @defgroup EMAC_Private_Variables EMAC Private Variables
Michael J. Spencer 2:1df0b61d3b5a 53 * @{
Michael J. Spencer 2:1df0b61d3b5a 54 */
Michael J. Spencer 2:1df0b61d3b5a 55
Michael J. Spencer 2:1df0b61d3b5a 56 /* MII Mgmt Configuration register - Clock divider setting */
Michael J. Spencer 2:1df0b61d3b5a 57 const uint8_t EMAC_clkdiv[] = { 4, 6, 8, 10, 14, 20, 28 };
Michael J. Spencer 2:1df0b61d3b5a 58
Michael J. Spencer 2:1df0b61d3b5a 59 /* EMAC local DMA Descriptors */
Michael J. Spencer 2:1df0b61d3b5a 60
Michael J. Spencer 2:1df0b61d3b5a 61 /** Rx Descriptor data array */
Michael J. Spencer 2:1df0b61d3b5a 62 static RX_Desc Rx_Desc[EMAC_NUM_RX_FRAG];
Michael J. Spencer 2:1df0b61d3b5a 63
Michael J. Spencer 2:1df0b61d3b5a 64 /** Rx Status data array - Must be 8-Byte aligned */
Michael J. Spencer 2:1df0b61d3b5a 65 #if defined ( __CC_ARM )
Michael J. Spencer 2:1df0b61d3b5a 66 static __align(8) RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
Michael J. Spencer 2:1df0b61d3b5a 67 #elif defined ( __ICCARM__ )
Michael J. Spencer 2:1df0b61d3b5a 68 #pragma data_alignment=8
Michael J. Spencer 2:1df0b61d3b5a 69 static RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
Michael J. Spencer 2:1df0b61d3b5a 70 #elif defined ( __GNUC__ )
Michael J. Spencer 2:1df0b61d3b5a 71 static __attribute__ ((aligned (8))) RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
Michael J. Spencer 2:1df0b61d3b5a 72 #endif
Michael J. Spencer 2:1df0b61d3b5a 73
Michael J. Spencer 2:1df0b61d3b5a 74 /** Tx Descriptor data array */
Michael J. Spencer 2:1df0b61d3b5a 75 static TX_Desc Tx_Desc[EMAC_NUM_TX_FRAG];
Michael J. Spencer 2:1df0b61d3b5a 76 /** Tx Status data array */
Michael J. Spencer 2:1df0b61d3b5a 77 static TX_Stat Tx_Stat[EMAC_NUM_TX_FRAG];
Michael J. Spencer 2:1df0b61d3b5a 78
Michael J. Spencer 2:1df0b61d3b5a 79 /* EMAC local DMA buffers */
Michael J. Spencer 2:1df0b61d3b5a 80 /** Rx buffer data */
Michael J. Spencer 2:1df0b61d3b5a 81 static uint32_t rx_buf[EMAC_NUM_RX_FRAG][EMAC_ETH_MAX_FLEN>>2];
Michael J. Spencer 2:1df0b61d3b5a 82 /** Tx buffer data */
Michael J. Spencer 2:1df0b61d3b5a 83 static uint32_t tx_buf[EMAC_NUM_TX_FRAG][EMAC_ETH_MAX_FLEN>>2];
Michael J. Spencer 2:1df0b61d3b5a 84
Michael J. Spencer 2:1df0b61d3b5a 85 /**
Michael J. Spencer 2:1df0b61d3b5a 86 * @}
Michael J. Spencer 2:1df0b61d3b5a 87 */
Michael J. Spencer 2:1df0b61d3b5a 88
Michael J. Spencer 2:1df0b61d3b5a 89 /* Private Functions ---------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 90 static void rx_descr_init (void);
Michael J. Spencer 2:1df0b61d3b5a 91 static void tx_descr_init (void);
Michael J. Spencer 2:1df0b61d3b5a 92 static int32_t write_PHY (uint32_t PhyReg, uint16_t Value);
Michael J. Spencer 2:1df0b61d3b5a 93 static int32_t read_PHY (uint32_t PhyReg);
Michael J. Spencer 2:1df0b61d3b5a 94
Michael J. Spencer 2:1df0b61d3b5a 95 static void setEmacAddr(uint8_t abStationAddr[]);
Michael J. Spencer 2:1df0b61d3b5a 96 static int32_t emac_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len);
Michael J. Spencer 2:1df0b61d3b5a 97
Michael J. Spencer 2:1df0b61d3b5a 98
Michael J. Spencer 2:1df0b61d3b5a 99 /*--------------------------- rx_descr_init ---------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 100 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 101 * @brief Initializes RX Descriptor
Michael J. Spencer 2:1df0b61d3b5a 102 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 103 * @return None
Michael J. Spencer 2:1df0b61d3b5a 104 ***********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 105 static void rx_descr_init (void)
Michael J. Spencer 2:1df0b61d3b5a 106 {
Michael J. Spencer 2:1df0b61d3b5a 107 /* Initialize Receive Descriptor and Status array. */
Michael J. Spencer 2:1df0b61d3b5a 108 uint32_t i;
Michael J. Spencer 2:1df0b61d3b5a 109
Michael J. Spencer 2:1df0b61d3b5a 110 for (i = 0; i < EMAC_NUM_RX_FRAG; i++) {
Michael J. Spencer 2:1df0b61d3b5a 111 Rx_Desc[i].Packet = (uint32_t)&rx_buf[i];
Michael J. Spencer 2:1df0b61d3b5a 112 Rx_Desc[i].Ctrl = EMAC_RCTRL_INT | (EMAC_ETH_MAX_FLEN - 1);
Michael J. Spencer 2:1df0b61d3b5a 113 Rx_Stat[i].Info = 0;
Michael J. Spencer 2:1df0b61d3b5a 114 Rx_Stat[i].HashCRC = 0;
Michael J. Spencer 2:1df0b61d3b5a 115 }
Michael J. Spencer 2:1df0b61d3b5a 116
Michael J. Spencer 2:1df0b61d3b5a 117 /* Set EMAC Receive Descriptor Registers. */
Michael J. Spencer 2:1df0b61d3b5a 118 LPC_EMAC->RxDescriptor = (uint32_t)&Rx_Desc[0];
Michael J. Spencer 2:1df0b61d3b5a 119 LPC_EMAC->RxStatus = (uint32_t)&Rx_Stat[0];
Michael J. Spencer 2:1df0b61d3b5a 120 LPC_EMAC->RxDescriptorNumber = EMAC_NUM_RX_FRAG - 1;
Michael J. Spencer 2:1df0b61d3b5a 121
Michael J. Spencer 2:1df0b61d3b5a 122 /* Rx Descriptors Point to 0 */
Michael J. Spencer 2:1df0b61d3b5a 123 LPC_EMAC->RxConsumeIndex = 0;
Michael J. Spencer 2:1df0b61d3b5a 124 }
Michael J. Spencer 2:1df0b61d3b5a 125
Michael J. Spencer 2:1df0b61d3b5a 126
Michael J. Spencer 2:1df0b61d3b5a 127 /*--------------------------- tx_descr_init ---- ----------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 128 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 129 * @brief Initializes TX Descriptor
Michael J. Spencer 2:1df0b61d3b5a 130 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 131 * @return None
Michael J. Spencer 2:1df0b61d3b5a 132 ***********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 133 static void tx_descr_init (void) {
Michael J. Spencer 2:1df0b61d3b5a 134 /* Initialize Transmit Descriptor and Status array. */
Michael J. Spencer 2:1df0b61d3b5a 135 uint32_t i;
Michael J. Spencer 2:1df0b61d3b5a 136
Michael J. Spencer 2:1df0b61d3b5a 137 for (i = 0; i < EMAC_NUM_TX_FRAG; i++) {
Michael J. Spencer 2:1df0b61d3b5a 138 Tx_Desc[i].Packet = (uint32_t)&tx_buf[i];
Michael J. Spencer 2:1df0b61d3b5a 139 Tx_Desc[i].Ctrl = 0;
Michael J. Spencer 2:1df0b61d3b5a 140 Tx_Stat[i].Info = 0;
Michael J. Spencer 2:1df0b61d3b5a 141 }
Michael J. Spencer 2:1df0b61d3b5a 142
Michael J. Spencer 2:1df0b61d3b5a 143 /* Set EMAC Transmit Descriptor Registers. */
Michael J. Spencer 2:1df0b61d3b5a 144 LPC_EMAC->TxDescriptor = (uint32_t)&Tx_Desc[0];
Michael J. Spencer 2:1df0b61d3b5a 145 LPC_EMAC->TxStatus = (uint32_t)&Tx_Stat[0];
Michael J. Spencer 2:1df0b61d3b5a 146 LPC_EMAC->TxDescriptorNumber = EMAC_NUM_TX_FRAG - 1;
Michael J. Spencer 2:1df0b61d3b5a 147
Michael J. Spencer 2:1df0b61d3b5a 148 /* Tx Descriptors Point to 0 */
Michael J. Spencer 2:1df0b61d3b5a 149 LPC_EMAC->TxProduceIndex = 0;
Michael J. Spencer 2:1df0b61d3b5a 150 }
Michael J. Spencer 2:1df0b61d3b5a 151
Michael J. Spencer 2:1df0b61d3b5a 152
Michael J. Spencer 2:1df0b61d3b5a 153 /*--------------------------- write_PHY -------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 154 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 155 * @brief Write value to PHY device
Michael J. Spencer 2:1df0b61d3b5a 156 * @param[in] PhyReg: PHY Register address
Michael J. Spencer 2:1df0b61d3b5a 157 * @param[in] Value: Value to write
Michael J. Spencer 2:1df0b61d3b5a 158 * @return 0 - if success
Michael J. Spencer 2:1df0b61d3b5a 159 * 1 - if fail
Michael J. Spencer 2:1df0b61d3b5a 160 ***********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 161 static int32_t write_PHY (uint32_t PhyReg, uint16_t Value)
Michael J. Spencer 2:1df0b61d3b5a 162 {
Michael J. Spencer 2:1df0b61d3b5a 163 /* Write a data 'Value' to PHY register 'PhyReg'. */
Michael J. Spencer 2:1df0b61d3b5a 164 uint32_t tout;
Michael J. Spencer 2:1df0b61d3b5a 165
Michael J. Spencer 2:1df0b61d3b5a 166 LPC_EMAC->MADR = EMAC_DEF_ADR | PhyReg;
Michael J. Spencer 2:1df0b61d3b5a 167 LPC_EMAC->MWTD = Value;
Michael J. Spencer 2:1df0b61d3b5a 168
Michael J. Spencer 2:1df0b61d3b5a 169 /* Wait until operation completed */
Michael J. Spencer 2:1df0b61d3b5a 170 tout = 0;
Michael J. Spencer 2:1df0b61d3b5a 171 for (tout = 0; tout < EMAC_MII_WR_TOUT; tout++) {
Michael J. Spencer 2:1df0b61d3b5a 172 if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) {
Michael J. Spencer 2:1df0b61d3b5a 173 return (0);
Michael J. Spencer 2:1df0b61d3b5a 174 }
Michael J. Spencer 2:1df0b61d3b5a 175 }
Michael J. Spencer 2:1df0b61d3b5a 176 // Time out!
Michael J. Spencer 2:1df0b61d3b5a 177 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 178 }
Michael J. Spencer 2:1df0b61d3b5a 179
Michael J. Spencer 2:1df0b61d3b5a 180
Michael J. Spencer 2:1df0b61d3b5a 181 /*--------------------------- read_PHY --------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 182 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 183 * @brief Read value from PHY device
Michael J. Spencer 2:1df0b61d3b5a 184 * @param[in] PhyReg: PHY Register address
Michael J. Spencer 2:1df0b61d3b5a 185 * @return 0 - if success
Michael J. Spencer 2:1df0b61d3b5a 186 * 1 - if fail
Michael J. Spencer 2:1df0b61d3b5a 187 ***********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 188 static int32_t read_PHY (uint32_t PhyReg)
Michael J. Spencer 2:1df0b61d3b5a 189 {
Michael J. Spencer 2:1df0b61d3b5a 190 /* Read a PHY register 'PhyReg'. */
Michael J. Spencer 2:1df0b61d3b5a 191 uint32_t tout;
Michael J. Spencer 2:1df0b61d3b5a 192
Michael J. Spencer 2:1df0b61d3b5a 193 LPC_EMAC->MADR = EMAC_DEF_ADR | PhyReg;
Michael J. Spencer 2:1df0b61d3b5a 194 LPC_EMAC->MCMD = EMAC_MCMD_READ;
Michael J. Spencer 2:1df0b61d3b5a 195
Michael J. Spencer 2:1df0b61d3b5a 196 /* Wait until operation completed */
Michael J. Spencer 2:1df0b61d3b5a 197 tout = 0;
Michael J. Spencer 2:1df0b61d3b5a 198 for (tout = 0; tout < EMAC_MII_RD_TOUT; tout++) {
Michael J. Spencer 2:1df0b61d3b5a 199 if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) {
Michael J. Spencer 2:1df0b61d3b5a 200 LPC_EMAC->MCMD = 0;
Michael J. Spencer 2:1df0b61d3b5a 201 return (LPC_EMAC->MRDD);
Michael J. Spencer 2:1df0b61d3b5a 202 }
Michael J. Spencer 2:1df0b61d3b5a 203 }
Michael J. Spencer 2:1df0b61d3b5a 204 // Time out!
Michael J. Spencer 2:1df0b61d3b5a 205 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 206 }
Michael J. Spencer 2:1df0b61d3b5a 207
Michael J. Spencer 2:1df0b61d3b5a 208 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 209 * @brief Set Station MAC address for EMAC module
Michael J. Spencer 2:1df0b61d3b5a 210 * @param[in] abStationAddr Pointer to Station address that contains 6-bytes
Michael J. Spencer 2:1df0b61d3b5a 211 * of MAC address (should be in order from MAC Address 1 to MAC Address 6)
Michael J. Spencer 2:1df0b61d3b5a 212 * @return None
Michael J. Spencer 2:1df0b61d3b5a 213 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 214 static void setEmacAddr(uint8_t abStationAddr[])
Michael J. Spencer 2:1df0b61d3b5a 215 {
Michael J. Spencer 2:1df0b61d3b5a 216 /* Set the Ethernet MAC Address registers */
Michael J. Spencer 2:1df0b61d3b5a 217 LPC_EMAC->SA0 = ((uint32_t)abStationAddr[5] << 8) | (uint32_t)abStationAddr[4];
Michael J. Spencer 2:1df0b61d3b5a 218 LPC_EMAC->SA1 = ((uint32_t)abStationAddr[3] << 8) | (uint32_t)abStationAddr[2];
Michael J. Spencer 2:1df0b61d3b5a 219 LPC_EMAC->SA2 = ((uint32_t)abStationAddr[1] << 8) | (uint32_t)abStationAddr[0];
Michael J. Spencer 2:1df0b61d3b5a 220 }
Michael J. Spencer 2:1df0b61d3b5a 221
Michael J. Spencer 2:1df0b61d3b5a 222
Michael J. Spencer 2:1df0b61d3b5a 223 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 224 * @brief Calculates CRC code for number of bytes in the frame
Michael J. Spencer 2:1df0b61d3b5a 225 * @param[in] frame_no_fcs Pointer to the first byte of the frame
Michael J. Spencer 2:1df0b61d3b5a 226 * @param[in] frame_len length of the frame without the FCS
Michael J. Spencer 2:1df0b61d3b5a 227 * @return the CRC as a 32 bit integer
Michael J. Spencer 2:1df0b61d3b5a 228 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 229 static int32_t emac_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len)
Michael J. Spencer 2:1df0b61d3b5a 230 {
Michael J. Spencer 2:1df0b61d3b5a 231 int i; // iterator
Michael J. Spencer 2:1df0b61d3b5a 232 int j; // another iterator
Michael J. Spencer 2:1df0b61d3b5a 233 char byte; // current byte
Michael J. Spencer 2:1df0b61d3b5a 234 int crc; // CRC result
Michael J. Spencer 2:1df0b61d3b5a 235 int q0, q1, q2, q3; // temporary variables
Michael J. Spencer 2:1df0b61d3b5a 236 crc = 0xFFFFFFFF;
Michael J. Spencer 2:1df0b61d3b5a 237 for (i = 0; i < frame_len; i++) {
Michael J. Spencer 2:1df0b61d3b5a 238 byte = *frame_no_fcs++;
Michael J. Spencer 2:1df0b61d3b5a 239 for (j = 0; j < 2; j++) {
Michael J. Spencer 2:1df0b61d3b5a 240 if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) {
Michael J. Spencer 2:1df0b61d3b5a 241 q3 = 0x04C11DB7;
Michael J. Spencer 2:1df0b61d3b5a 242 } else {
Michael J. Spencer 2:1df0b61d3b5a 243 q3 = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 244 }
Michael J. Spencer 2:1df0b61d3b5a 245 if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) {
Michael J. Spencer 2:1df0b61d3b5a 246 q2 = 0x09823B6E;
Michael J. Spencer 2:1df0b61d3b5a 247 } else {
Michael J. Spencer 2:1df0b61d3b5a 248 q2 = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 249 }
Michael J. Spencer 2:1df0b61d3b5a 250 if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) {
Michael J. Spencer 2:1df0b61d3b5a 251 q1 = 0x130476DC;
Michael J. Spencer 2:1df0b61d3b5a 252 } else {
Michael J. Spencer 2:1df0b61d3b5a 253 q1 = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 254 }
Michael J. Spencer 2:1df0b61d3b5a 255 if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) {
Michael J. Spencer 2:1df0b61d3b5a 256 q0 = 0x2608EDB8;
Michael J. Spencer 2:1df0b61d3b5a 257 } else {
Michael J. Spencer 2:1df0b61d3b5a 258 q0 = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 259 }
Michael J. Spencer 2:1df0b61d3b5a 260 crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0;
Michael J. Spencer 2:1df0b61d3b5a 261 byte >>= 4;
Michael J. Spencer 2:1df0b61d3b5a 262 }
Michael J. Spencer 2:1df0b61d3b5a 263 }
Michael J. Spencer 2:1df0b61d3b5a 264 return crc;
Michael J. Spencer 2:1df0b61d3b5a 265 }
Michael J. Spencer 2:1df0b61d3b5a 266 /* End of Private Functions --------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 267
Michael J. Spencer 2:1df0b61d3b5a 268
Michael J. Spencer 2:1df0b61d3b5a 269 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 270 /** @addtogroup EMAC_Public_Functions
Michael J. Spencer 2:1df0b61d3b5a 271 * @{
Michael J. Spencer 2:1df0b61d3b5a 272 */
Michael J. Spencer 2:1df0b61d3b5a 273
Michael J. Spencer 2:1df0b61d3b5a 274
Michael J. Spencer 2:1df0b61d3b5a 275 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 276 * @brief Initializes the EMAC peripheral according to the specified
Michael J. Spencer 2:1df0b61d3b5a 277 * parameters in the EMAC_ConfigStruct.
Michael J. Spencer 2:1df0b61d3b5a 278 * @param[in] EMAC_ConfigStruct Pointer to a EMAC_CFG_Type structure
Michael J. Spencer 2:1df0b61d3b5a 279 * that contains the configuration information for the
Michael J. Spencer 2:1df0b61d3b5a 280 * specified EMAC peripheral.
Michael J. Spencer 2:1df0b61d3b5a 281 * @return None
Michael J. Spencer 2:1df0b61d3b5a 282 *
Michael J. Spencer 2:1df0b61d3b5a 283 * Note: This function will initialize EMAC module according to procedure below:
Michael J. Spencer 2:1df0b61d3b5a 284 * - Remove the soft reset condition from the MAC
Michael J. Spencer 2:1df0b61d3b5a 285 * - Configure the PHY via the MIIM interface of the MAC
Michael J. Spencer 2:1df0b61d3b5a 286 * - Select RMII mode
Michael J. Spencer 2:1df0b61d3b5a 287 * - Configure the transmit and receive DMA engines, including the descriptor arrays
Michael J. Spencer 2:1df0b61d3b5a 288 * - Configure the host registers (MAC1,MAC2 etc.) in the MAC
Michael J. Spencer 2:1df0b61d3b5a 289 * - Enable the receive and transmit data paths
Michael J. Spencer 2:1df0b61d3b5a 290 * In default state after initializing, only Rx Done and Tx Done interrupt are enabled,
Michael J. Spencer 2:1df0b61d3b5a 291 * all remain interrupts are disabled
Michael J. Spencer 2:1df0b61d3b5a 292 * (Ref. from LPC17xx UM)
Michael J. Spencer 2:1df0b61d3b5a 293 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 294 Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct)
Michael J. Spencer 2:1df0b61d3b5a 295 {
Michael J. Spencer 2:1df0b61d3b5a 296 /* Initialize the EMAC Ethernet controller. */
Michael J. Spencer 2:1df0b61d3b5a 297 int32_t regv,tout, tmp;
Michael J. Spencer 2:1df0b61d3b5a 298
Michael J. Spencer 2:1df0b61d3b5a 299 /* Set up clock and power for Ethernet module */
Michael J. Spencer 2:1df0b61d3b5a 300 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, ENABLE);
Michael J. Spencer 2:1df0b61d3b5a 301
Michael J. Spencer 2:1df0b61d3b5a 302 /* Reset all EMAC internal modules */
Michael J. Spencer 2:1df0b61d3b5a 303 LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX | EMAC_MAC1_RES_RX |
Michael J. Spencer 2:1df0b61d3b5a 304 EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES | EMAC_MAC1_SOFT_RES;
Michael J. Spencer 2:1df0b61d3b5a 305
Michael J. Spencer 2:1df0b61d3b5a 306 LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES | EMAC_CR_PASS_RUNT_FRM;
Michael J. Spencer 2:1df0b61d3b5a 307
Michael J. Spencer 2:1df0b61d3b5a 308 /* A short delay after reset. */
Michael J. Spencer 2:1df0b61d3b5a 309 for (tout = 100; tout; tout--);
Michael J. Spencer 2:1df0b61d3b5a 310
Michael J. Spencer 2:1df0b61d3b5a 311 /* Initialize MAC control registers. */
Michael J. Spencer 2:1df0b61d3b5a 312 LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
Michael J. Spencer 2:1df0b61d3b5a 313 LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN;
Michael J. Spencer 2:1df0b61d3b5a 314 LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN;
Michael J. Spencer 2:1df0b61d3b5a 315 /*
Michael J. Spencer 2:1df0b61d3b5a 316 * Find the clock that close to desired target clock
Michael J. Spencer 2:1df0b61d3b5a 317 */
Michael J. Spencer 2:1df0b61d3b5a 318 tmp = SystemCoreClock / EMAC_MCFG_MII_MAXCLK;
Michael J. Spencer 2:1df0b61d3b5a 319 for (tout = 0; tout < (int32_t) sizeof (EMAC_clkdiv); tout++){
Michael J. Spencer 2:1df0b61d3b5a 320 if (EMAC_clkdiv[tout] >= tmp) break;
Michael J. Spencer 2:1df0b61d3b5a 321 }
Michael J. Spencer 2:1df0b61d3b5a 322 tout++;
Michael J. Spencer 2:1df0b61d3b5a 323 // Write to MAC configuration register and reset
Michael J. Spencer 2:1df0b61d3b5a 324 LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(tout) | EMAC_MCFG_RES_MII;
Michael J. Spencer 2:1df0b61d3b5a 325 // release reset
Michael J. Spencer 2:1df0b61d3b5a 326 LPC_EMAC->MCFG &= ~(EMAC_MCFG_RES_MII);
Michael J. Spencer 2:1df0b61d3b5a 327 LPC_EMAC->CLRT = EMAC_CLRT_DEF;
Michael J. Spencer 2:1df0b61d3b5a 328 LPC_EMAC->IPGR = EMAC_IPGR_P2_DEF;
Michael J. Spencer 2:1df0b61d3b5a 329
Michael J. Spencer 2:1df0b61d3b5a 330 /* Enable Reduced MII interface. */
Michael J. Spencer 2:1df0b61d3b5a 331 LPC_EMAC->Command = EMAC_CR_RMII | EMAC_CR_PASS_RUNT_FRM;
Michael J. Spencer 2:1df0b61d3b5a 332
Michael J. Spencer 2:1df0b61d3b5a 333 /* Reset Reduced MII Logic. */
Michael J. Spencer 2:1df0b61d3b5a 334 LPC_EMAC->SUPP = EMAC_SUPP_RES_RMII;
Michael J. Spencer 2:1df0b61d3b5a 335
Michael J. Spencer 2:1df0b61d3b5a 336 for (tout = 100; tout; tout--);
Michael J. Spencer 2:1df0b61d3b5a 337 LPC_EMAC->SUPP = 0;
Michael J. Spencer 2:1df0b61d3b5a 338
Michael J. Spencer 2:1df0b61d3b5a 339 /* Put the DP83848C in reset mode */
Michael J. Spencer 2:1df0b61d3b5a 340 write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_BMCR_RESET);
Michael J. Spencer 2:1df0b61d3b5a 341
Michael J. Spencer 2:1df0b61d3b5a 342 /* Wait for hardware reset to end. */
Michael J. Spencer 2:1df0b61d3b5a 343 for (tout = EMAC_PHY_RESP_TOUT; tout; tout--) {
Michael J. Spencer 2:1df0b61d3b5a 344 regv = read_PHY (EMAC_PHY_REG_BMCR);
Michael J. Spencer 2:1df0b61d3b5a 345 if (!(regv & (EMAC_PHY_BMCR_RESET | EMAC_PHY_BMCR_POWERDOWN))) {
Michael J. Spencer 2:1df0b61d3b5a 346 /* Reset complete, device not Power Down. */
Michael J. Spencer 2:1df0b61d3b5a 347 break;
Michael J. Spencer 2:1df0b61d3b5a 348 }
Michael J. Spencer 2:1df0b61d3b5a 349 if (tout == 0){
Michael J. Spencer 2:1df0b61d3b5a 350 // Time out, return ERROR
Michael J. Spencer 2:1df0b61d3b5a 351 return (ERROR);
Michael J. Spencer 2:1df0b61d3b5a 352 }
Michael J. Spencer 2:1df0b61d3b5a 353 }
Michael J. Spencer 2:1df0b61d3b5a 354
Michael J. Spencer 2:1df0b61d3b5a 355 // Set PHY mode
Michael J. Spencer 2:1df0b61d3b5a 356 if (EMAC_SetPHYMode(EMAC_ConfigStruct->Mode) < 0){
Michael J. Spencer 2:1df0b61d3b5a 357 return (ERROR);
Michael J. Spencer 2:1df0b61d3b5a 358 }
Michael J. Spencer 2:1df0b61d3b5a 359
Michael J. Spencer 2:1df0b61d3b5a 360 // Set EMAC address
Michael J. Spencer 2:1df0b61d3b5a 361 setEmacAddr(EMAC_ConfigStruct->pbEMAC_Addr);
Michael J. Spencer 2:1df0b61d3b5a 362
Michael J. Spencer 2:1df0b61d3b5a 363 /* Initialize Tx and Rx DMA Descriptors */
Michael J. Spencer 2:1df0b61d3b5a 364 rx_descr_init ();
Michael J. Spencer 2:1df0b61d3b5a 365 tx_descr_init ();
Michael J. Spencer 2:1df0b61d3b5a 366
Michael J. Spencer 2:1df0b61d3b5a 367 // Set Receive Filter register: enable broadcast and multicast
Michael J. Spencer 2:1df0b61d3b5a 368 LPC_EMAC->RxFilterCtrl = EMAC_RFC_MCAST_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_PERFECT_EN;
Michael J. Spencer 2:1df0b61d3b5a 369
Michael J. Spencer 2:1df0b61d3b5a 370 /* Enable Rx Done and Tx Done interrupt for EMAC */
Michael J. Spencer 2:1df0b61d3b5a 371 LPC_EMAC->IntEnable = EMAC_INT_RX_DONE | EMAC_INT_TX_DONE;
Michael J. Spencer 2:1df0b61d3b5a 372
Michael J. Spencer 2:1df0b61d3b5a 373 /* Reset all interrupts */
Michael J. Spencer 2:1df0b61d3b5a 374 LPC_EMAC->IntClear = 0xFFFF;
Michael J. Spencer 2:1df0b61d3b5a 375
Michael J. Spencer 2:1df0b61d3b5a 376 /* Enable receive and transmit mode of MAC Ethernet core */
Michael J. Spencer 2:1df0b61d3b5a 377 LPC_EMAC->Command |= (EMAC_CR_RX_EN | EMAC_CR_TX_EN);
Michael J. Spencer 2:1df0b61d3b5a 378 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
Michael J. Spencer 2:1df0b61d3b5a 379
Michael J. Spencer 2:1df0b61d3b5a 380 return SUCCESS;
Michael J. Spencer 2:1df0b61d3b5a 381 }
Michael J. Spencer 2:1df0b61d3b5a 382
Michael J. Spencer 2:1df0b61d3b5a 383
Michael J. Spencer 2:1df0b61d3b5a 384 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 385 * @brief De-initializes the EMAC peripheral registers to their
Michael J. Spencer 2:1df0b61d3b5a 386 * default reset values.
Michael J. Spencer 2:1df0b61d3b5a 387 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 388 * @return None
Michael J. Spencer 2:1df0b61d3b5a 389 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 390 void EMAC_DeInit(void)
Michael J. Spencer 2:1df0b61d3b5a 391 {
Michael J. Spencer 2:1df0b61d3b5a 392 // Disable all interrupt
Michael J. Spencer 2:1df0b61d3b5a 393 LPC_EMAC->IntEnable = 0x00;
Michael J. Spencer 2:1df0b61d3b5a 394 // Clear all pending interrupt
Michael J. Spencer 2:1df0b61d3b5a 395 LPC_EMAC->IntClear = (0xFF) | (EMAC_INT_SOFT_INT | EMAC_INT_WAKEUP);
Michael J. Spencer 2:1df0b61d3b5a 396
Michael J. Spencer 2:1df0b61d3b5a 397 /* TurnOff clock and power for Ethernet module */
Michael J. Spencer 2:1df0b61d3b5a 398 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, DISABLE);
Michael J. Spencer 2:1df0b61d3b5a 399 }
Michael J. Spencer 2:1df0b61d3b5a 400
Michael J. Spencer 2:1df0b61d3b5a 401
Michael J. Spencer 2:1df0b61d3b5a 402 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 403 * @brief Check specified PHY status in EMAC peripheral
Michael J. Spencer 2:1df0b61d3b5a 404 * @param[in] ulPHYState Specified PHY Status Type, should be:
Michael J. Spencer 2:1df0b61d3b5a 405 * - EMAC_PHY_STAT_LINK: Link Status
Michael J. Spencer 2:1df0b61d3b5a 406 * - EMAC_PHY_STAT_SPEED: Speed Status
Michael J. Spencer 2:1df0b61d3b5a 407 * - EMAC_PHY_STAT_DUP: Duplex Status
Michael J. Spencer 2:1df0b61d3b5a 408 * @return Status of specified PHY status (0 or 1).
Michael J. Spencer 2:1df0b61d3b5a 409 * (-1) if error.
Michael J. Spencer 2:1df0b61d3b5a 410 *
Michael J. Spencer 2:1df0b61d3b5a 411 * Note:
Michael J. Spencer 2:1df0b61d3b5a 412 * For EMAC_PHY_STAT_LINK, return value:
Michael J. Spencer 2:1df0b61d3b5a 413 * - 0: Link Down
Michael J. Spencer 2:1df0b61d3b5a 414 * - 1: Link Up
Michael J. Spencer 2:1df0b61d3b5a 415 * For EMAC_PHY_STAT_SPEED, return value:
Michael J. Spencer 2:1df0b61d3b5a 416 * - 0: 10Mbps
Michael J. Spencer 2:1df0b61d3b5a 417 * - 1: 100Mbps
Michael J. Spencer 2:1df0b61d3b5a 418 * For EMAC_PHY_STAT_DUP, return value:
Michael J. Spencer 2:1df0b61d3b5a 419 * - 0: Half-Duplex
Michael J. Spencer 2:1df0b61d3b5a 420 * - 1: Full-Duplex
Michael J. Spencer 2:1df0b61d3b5a 421 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 422 int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState)
Michael J. Spencer 2:1df0b61d3b5a 423 {
Michael J. Spencer 2:1df0b61d3b5a 424 int32_t regv, tmp;
Michael J. Spencer 2:1df0b61d3b5a 425 #ifdef MCB_LPC_1768
Michael J. Spencer 2:1df0b61d3b5a 426 regv = read_PHY (EMAC_PHY_REG_STS);
Michael J. Spencer 2:1df0b61d3b5a 427 switch(ulPHYState){
Michael J. Spencer 2:1df0b61d3b5a 428 case EMAC_PHY_STAT_LINK:
Michael J. Spencer 2:1df0b61d3b5a 429 tmp = (regv & EMAC_PHY_SR_LINK) ? 1 : 0;
Michael J. Spencer 2:1df0b61d3b5a 430 break;
Michael J. Spencer 2:1df0b61d3b5a 431 case EMAC_PHY_STAT_SPEED:
Michael J. Spencer 2:1df0b61d3b5a 432 tmp = (regv & EMAC_PHY_SR_SPEED) ? 0 : 1;
Michael J. Spencer 2:1df0b61d3b5a 433 break;
Michael J. Spencer 2:1df0b61d3b5a 434 case EMAC_PHY_STAT_DUP:
Michael J. Spencer 2:1df0b61d3b5a 435 tmp = (regv & EMAC_PHY_SR_FULL_DUP) ? 1 : 0;
Michael J. Spencer 2:1df0b61d3b5a 436 break;
Michael J. Spencer 2:1df0b61d3b5a 437 #elif defined(IAR_LPC_1768)
Michael J. Spencer 2:1df0b61d3b5a 438 /* Use IAR_LPC_1768 board:
Michael J. Spencer 2:1df0b61d3b5a 439 * FSZ8721BL doesn't have Status Register
Michael J. Spencer 2:1df0b61d3b5a 440 * so we read Basic Mode Status Register (0x01h) instead
Michael J. Spencer 2:1df0b61d3b5a 441 */
Michael J. Spencer 2:1df0b61d3b5a 442 regv = read_PHY (EMAC_PHY_REG_BMSR);
Michael J. Spencer 2:1df0b61d3b5a 443 switch(ulPHYState){
Michael J. Spencer 2:1df0b61d3b5a 444 case EMAC_PHY_STAT_LINK:
Michael J. Spencer 2:1df0b61d3b5a 445 tmp = (regv & EMAC_PHY_BMSR_LINK_STATUS) ? 1 : 0;
Michael J. Spencer 2:1df0b61d3b5a 446 break;
Michael J. Spencer 2:1df0b61d3b5a 447 case EMAC_PHY_STAT_SPEED:
Michael J. Spencer 2:1df0b61d3b5a 448 tmp = (regv & EMAC_PHY_SR_100_SPEED) ? 1 : 0;
Michael J. Spencer 2:1df0b61d3b5a 449 break;
Michael J. Spencer 2:1df0b61d3b5a 450 case EMAC_PHY_STAT_DUP:
Michael J. Spencer 2:1df0b61d3b5a 451 tmp = (regv & EMAC_PHY_SR_FULL_DUP) ? 1 : 0;
Michael J. Spencer 2:1df0b61d3b5a 452 break;
Michael J. Spencer 2:1df0b61d3b5a 453 #endif
Michael J. Spencer 2:1df0b61d3b5a 454 default:
Michael J. Spencer 2:1df0b61d3b5a 455 tmp = -1;
Michael J. Spencer 2:1df0b61d3b5a 456 break;
Michael J. Spencer 2:1df0b61d3b5a 457 }
Michael J. Spencer 2:1df0b61d3b5a 458 return (tmp);
Michael J. Spencer 2:1df0b61d3b5a 459 }
Michael J. Spencer 2:1df0b61d3b5a 460
Michael J. Spencer 2:1df0b61d3b5a 461
Michael J. Spencer 2:1df0b61d3b5a 462 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 463 * @brief Set specified PHY mode in EMAC peripheral
Michael J. Spencer 2:1df0b61d3b5a 464 * @param[in] ulPHYMode Specified PHY mode, should be:
Michael J. Spencer 2:1df0b61d3b5a 465 * - EMAC_MODE_AUTO
Michael J. Spencer 2:1df0b61d3b5a 466 * - EMAC_MODE_10M_FULL
Michael J. Spencer 2:1df0b61d3b5a 467 * - EMAC_MODE_10M_HALF
Michael J. Spencer 2:1df0b61d3b5a 468 * - EMAC_MODE_100M_FULL
Michael J. Spencer 2:1df0b61d3b5a 469 * - EMAC_MODE_100M_HALF
Michael J. Spencer 2:1df0b61d3b5a 470 * @return Return (0) if no error, otherwise return (-1)
Michael J. Spencer 2:1df0b61d3b5a 471 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 472 int32_t EMAC_SetPHYMode(uint32_t ulPHYMode)
Michael J. Spencer 2:1df0b61d3b5a 473 {
Michael J. Spencer 2:1df0b61d3b5a 474 int32_t id1, id2, tout, regv;
Michael J. Spencer 2:1df0b61d3b5a 475
Michael J. Spencer 2:1df0b61d3b5a 476 /* Check if this is a DP83848C PHY. */
Michael J. Spencer 2:1df0b61d3b5a 477 id1 = read_PHY (EMAC_PHY_REG_IDR1);
Michael J. Spencer 2:1df0b61d3b5a 478 id2 = read_PHY (EMAC_PHY_REG_IDR2);
Michael J. Spencer 2:1df0b61d3b5a 479
Michael J. Spencer 2:1df0b61d3b5a 480 #ifdef MCB_LPC_1768
Michael J. Spencer 2:1df0b61d3b5a 481 if (((id1 << 16) | (id2 & 0xFFF0)) == EMAC_DP83848C_ID) {
Michael J. Spencer 2:1df0b61d3b5a 482 switch(ulPHYMode){
Michael J. Spencer 2:1df0b61d3b5a 483 case EMAC_MODE_AUTO:
Michael J. Spencer 2:1df0b61d3b5a 484 write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_AUTO_NEG);
Michael J. Spencer 2:1df0b61d3b5a 485 #elif defined(IAR_LPC_1768) /* Use IAR LPC1768 KickStart board */
Michael J. Spencer 2:1df0b61d3b5a 486 if (((id1 << 16) | id2) == EMAC_KSZ8721BL_ID) {
Michael J. Spencer 2:1df0b61d3b5a 487 /* Configure the PHY device */
Michael J. Spencer 2:1df0b61d3b5a 488 switch(ulPHYMode){
Michael J. Spencer 2:1df0b61d3b5a 489 case EMAC_MODE_AUTO:
Michael J. Spencer 2:1df0b61d3b5a 490 /* Use auto-negotiation about the link speed. */
Michael J. Spencer 2:1df0b61d3b5a 491 write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_AUTO_NEG);
Michael J. Spencer 2:1df0b61d3b5a 492 // write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_BMCR_AN);
Michael J. Spencer 2:1df0b61d3b5a 493 #endif
Michael J. Spencer 2:1df0b61d3b5a 494 /* Wait to complete Auto_Negotiation */
Michael J. Spencer 2:1df0b61d3b5a 495 for (tout = EMAC_PHY_RESP_TOUT; tout; tout--) {
Michael J. Spencer 2:1df0b61d3b5a 496 regv = read_PHY (EMAC_PHY_REG_BMSR);
Michael J. Spencer 2:1df0b61d3b5a 497 if (regv & EMAC_PHY_BMSR_AUTO_DONE) {
Michael J. Spencer 2:1df0b61d3b5a 498 /* Auto-negotiation Complete. */
Michael J. Spencer 2:1df0b61d3b5a 499 break;
Michael J. Spencer 2:1df0b61d3b5a 500 }
Michael J. Spencer 2:1df0b61d3b5a 501 if (tout == 0){
Michael J. Spencer 2:1df0b61d3b5a 502 // Time out, return error
Michael J. Spencer 2:1df0b61d3b5a 503 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 504 }
Michael J. Spencer 2:1df0b61d3b5a 505 }
Michael J. Spencer 2:1df0b61d3b5a 506 break;
Michael J. Spencer 2:1df0b61d3b5a 507 case EMAC_MODE_10M_FULL:
Michael J. Spencer 2:1df0b61d3b5a 508 /* Connect at 10MBit full-duplex */
Michael J. Spencer 2:1df0b61d3b5a 509 write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_FULLD_10M);
Michael J. Spencer 2:1df0b61d3b5a 510 break;
Michael J. Spencer 2:1df0b61d3b5a 511 case EMAC_MODE_10M_HALF:
Michael J. Spencer 2:1df0b61d3b5a 512 /* Connect at 10MBit half-duplex */
Michael J. Spencer 2:1df0b61d3b5a 513 write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_HALFD_10M);
Michael J. Spencer 2:1df0b61d3b5a 514 break;
Michael J. Spencer 2:1df0b61d3b5a 515 case EMAC_MODE_100M_FULL:
Michael J. Spencer 2:1df0b61d3b5a 516 /* Connect at 100MBit full-duplex */
Michael J. Spencer 2:1df0b61d3b5a 517 write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_FULLD_100M);
Michael J. Spencer 2:1df0b61d3b5a 518 break;
Michael J. Spencer 2:1df0b61d3b5a 519 case EMAC_MODE_100M_HALF:
Michael J. Spencer 2:1df0b61d3b5a 520 /* Connect at 100MBit half-duplex */
Michael J. Spencer 2:1df0b61d3b5a 521 write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_HALFD_100M);
Michael J. Spencer 2:1df0b61d3b5a 522 break;
Michael J. Spencer 2:1df0b61d3b5a 523 default:
Michael J. Spencer 2:1df0b61d3b5a 524 // un-supported
Michael J. Spencer 2:1df0b61d3b5a 525 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 526 }
Michael J. Spencer 2:1df0b61d3b5a 527 }
Michael J. Spencer 2:1df0b61d3b5a 528 // It's not correct module ID
Michael J. Spencer 2:1df0b61d3b5a 529 else {
Michael J. Spencer 2:1df0b61d3b5a 530 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 531 }
Michael J. Spencer 2:1df0b61d3b5a 532
Michael J. Spencer 2:1df0b61d3b5a 533 // Update EMAC configuration with current PHY status
Michael J. Spencer 2:1df0b61d3b5a 534 if (EMAC_UpdatePHYStatus() < 0){
Michael J. Spencer 2:1df0b61d3b5a 535 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 536 }
Michael J. Spencer 2:1df0b61d3b5a 537
Michael J. Spencer 2:1df0b61d3b5a 538 // Complete
Michael J. Spencer 2:1df0b61d3b5a 539 return (0);
Michael J. Spencer 2:1df0b61d3b5a 540 }
Michael J. Spencer 2:1df0b61d3b5a 541
Michael J. Spencer 2:1df0b61d3b5a 542
Michael J. Spencer 2:1df0b61d3b5a 543 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 544 * @brief Auto-Configures value for the EMAC configuration register to
Michael J. Spencer 2:1df0b61d3b5a 545 * match with current PHY mode
Michael J. Spencer 2:1df0b61d3b5a 546 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 547 * @return Return (0) if no error, otherwise return (-1)
Michael J. Spencer 2:1df0b61d3b5a 548 *
Michael J. Spencer 2:1df0b61d3b5a 549 * Note: The EMAC configuration will be auto-configured:
Michael J. Spencer 2:1df0b61d3b5a 550 * - Speed mode.
Michael J. Spencer 2:1df0b61d3b5a 551 * - Half/Full duplex mode
Michael J. Spencer 2:1df0b61d3b5a 552 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 553 int32_t EMAC_UpdatePHYStatus(void)
Michael J. Spencer 2:1df0b61d3b5a 554 {
Michael J. Spencer 2:1df0b61d3b5a 555 int32_t regv, tout;
Michael J. Spencer 2:1df0b61d3b5a 556
Michael J. Spencer 2:1df0b61d3b5a 557 /* Check the link status. */
Michael J. Spencer 2:1df0b61d3b5a 558 #ifdef MCB_LPC_1768
Michael J. Spencer 2:1df0b61d3b5a 559 for (tout = EMAC_PHY_RESP_TOUT; tout; tout--) {
Michael J. Spencer 2:1df0b61d3b5a 560 regv = read_PHY (EMAC_PHY_REG_STS);
Michael J. Spencer 2:1df0b61d3b5a 561 if (regv & EMAC_PHY_SR_LINK) {
Michael J. Spencer 2:1df0b61d3b5a 562 /* Link is on. */
Michael J. Spencer 2:1df0b61d3b5a 563 break;
Michael J. Spencer 2:1df0b61d3b5a 564 }
Michael J. Spencer 2:1df0b61d3b5a 565 if (tout == 0){
Michael J. Spencer 2:1df0b61d3b5a 566 // time out
Michael J. Spencer 2:1df0b61d3b5a 567 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 568 }
Michael J. Spencer 2:1df0b61d3b5a 569 }
Michael J. Spencer 2:1df0b61d3b5a 570 /* Configure Full/Half Duplex mode. */
Michael J. Spencer 2:1df0b61d3b5a 571 if (regv & EMAC_PHY_SR_DUP) {
Michael J. Spencer 2:1df0b61d3b5a 572 /* Full duplex is enabled. */
Michael J. Spencer 2:1df0b61d3b5a 573 LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
Michael J. Spencer 2:1df0b61d3b5a 574 LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
Michael J. Spencer 2:1df0b61d3b5a 575 LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
Michael J. Spencer 2:1df0b61d3b5a 576 } else {
Michael J. Spencer 2:1df0b61d3b5a 577 /* Half duplex mode. */
Michael J. Spencer 2:1df0b61d3b5a 578 LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
Michael J. Spencer 2:1df0b61d3b5a 579 }
Michael J. Spencer 2:1df0b61d3b5a 580 if (regv & EMAC_PHY_SR_SPEED) {
Michael J. Spencer 2:1df0b61d3b5a 581 /* 10MBit mode. */
Michael J. Spencer 2:1df0b61d3b5a 582 LPC_EMAC->SUPP = 0;
Michael J. Spencer 2:1df0b61d3b5a 583 } else {
Michael J. Spencer 2:1df0b61d3b5a 584 /* 100MBit mode. */
Michael J. Spencer 2:1df0b61d3b5a 585 LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
Michael J. Spencer 2:1df0b61d3b5a 586 }
Michael J. Spencer 2:1df0b61d3b5a 587 #elif defined(IAR_LPC_1768)
Michael J. Spencer 2:1df0b61d3b5a 588 for (tout = EMAC_PHY_RESP_TOUT; tout; tout--) {
Michael J. Spencer 2:1df0b61d3b5a 589 regv = read_PHY (EMAC_PHY_REG_BMSR);
Michael J. Spencer 2:1df0b61d3b5a 590 if (regv & EMAC_PHY_BMSR_LINK_STATUS) {
Michael J. Spencer 2:1df0b61d3b5a 591 /* Link is on. */
Michael J. Spencer 2:1df0b61d3b5a 592 break;
Michael J. Spencer 2:1df0b61d3b5a 593 }
Michael J. Spencer 2:1df0b61d3b5a 594 if (tout == 0){
Michael J. Spencer 2:1df0b61d3b5a 595 // time out
Michael J. Spencer 2:1df0b61d3b5a 596 return (-1);
Michael J. Spencer 2:1df0b61d3b5a 597 }
Michael J. Spencer 2:1df0b61d3b5a 598 }
Michael J. Spencer 2:1df0b61d3b5a 599
Michael J. Spencer 2:1df0b61d3b5a 600 /* Configure Full/Half Duplex mode. */
Michael J. Spencer 2:1df0b61d3b5a 601 if (regv & EMAC_PHY_SR_FULL_DUP) {
Michael J. Spencer 2:1df0b61d3b5a 602 /* Full duplex is enabled. */
Michael J. Spencer 2:1df0b61d3b5a 603 LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
Michael J. Spencer 2:1df0b61d3b5a 604 LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
Michael J. Spencer 2:1df0b61d3b5a 605 LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
Michael J. Spencer 2:1df0b61d3b5a 606 } else {
Michael J. Spencer 2:1df0b61d3b5a 607 /* Half duplex mode. */
Michael J. Spencer 2:1df0b61d3b5a 608 LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
Michael J. Spencer 2:1df0b61d3b5a 609 }
Michael J. Spencer 2:1df0b61d3b5a 610
Michael J. Spencer 2:1df0b61d3b5a 611 /* Configure 100MBit/10MBit mode. */
Michael J. Spencer 2:1df0b61d3b5a 612 if (!(regv & EMAC_PHY_SR_100_SPEED)) {
Michael J. Spencer 2:1df0b61d3b5a 613 /* 10MBit mode. */
Michael J. Spencer 2:1df0b61d3b5a 614 LPC_EMAC->SUPP = 0;
Michael J. Spencer 2:1df0b61d3b5a 615 } else {
Michael J. Spencer 2:1df0b61d3b5a 616 /* 100MBit mode. */
Michael J. Spencer 2:1df0b61d3b5a 617 LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
Michael J. Spencer 2:1df0b61d3b5a 618 }
Michael J. Spencer 2:1df0b61d3b5a 619 #endif
Michael J. Spencer 2:1df0b61d3b5a 620 // Complete
Michael J. Spencer 2:1df0b61d3b5a 621 return (0);
Michael J. Spencer 2:1df0b61d3b5a 622 }
Michael J. Spencer 2:1df0b61d3b5a 623
Michael J. Spencer 2:1df0b61d3b5a 624
Michael J. Spencer 2:1df0b61d3b5a 625 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 626 * @brief Enable/Disable hash filter functionality for specified destination
Michael J. Spencer 2:1df0b61d3b5a 627 * MAC address in EMAC module
Michael J. Spencer 2:1df0b61d3b5a 628 * @param[in] dstMAC_addr Pointer to the first MAC destination address, should
Michael J. Spencer 2:1df0b61d3b5a 629 * be 6-bytes length, in order LSB to the MSB
Michael J. Spencer 2:1df0b61d3b5a 630 * @param[in] NewState New State of this command, should be:
Michael J. Spencer 2:1df0b61d3b5a 631 * - ENABLE.
Michael J. Spencer 2:1df0b61d3b5a 632 * - DISABLE.
Michael J. Spencer 2:1df0b61d3b5a 633 * @return None
Michael J. Spencer 2:1df0b61d3b5a 634 *
Michael J. Spencer 2:1df0b61d3b5a 635 * Note:
Michael J. Spencer 2:1df0b61d3b5a 636 * The standard Ethernet cyclic redundancy check (CRC) function is calculated from
Michael J. Spencer 2:1df0b61d3b5a 637 * the 6 byte destination address in the Ethernet frame (this CRC is calculated
Michael J. Spencer 2:1df0b61d3b5a 638 * anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of
Michael J. Spencer 2:1df0b61d3b5a 639 * the 32 bits CRC result are taken to form the hash. The 6 bit hash is used to access
Michael J. Spencer 2:1df0b61d3b5a 640 * the hash table: it is used as an index in the 64 bit HashFilter register that has been
Michael J. Spencer 2:1df0b61d3b5a 641 * programmed with accept values. If the selected accept value is 1, the frame is
Michael J. Spencer 2:1df0b61d3b5a 642 * accepted.
Michael J. Spencer 2:1df0b61d3b5a 643 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 644 void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState)
Michael J. Spencer 2:1df0b61d3b5a 645 {
Michael J. Spencer 2:1df0b61d3b5a 646 volatile uint32_t *pReg;
Michael J. Spencer 2:1df0b61d3b5a 647 uint32_t tmp;
Michael J. Spencer 2:1df0b61d3b5a 648 int32_t crc;
Michael J. Spencer 2:1df0b61d3b5a 649
Michael J. Spencer 2:1df0b61d3b5a 650 // Calculate the CRC from the destination MAC address
Michael J. Spencer 2:1df0b61d3b5a 651 crc = emac_CRCCalc(dstMAC_addr, 6);
Michael J. Spencer 2:1df0b61d3b5a 652 // Extract the value from CRC to get index value for hash filter table
Michael J. Spencer 2:1df0b61d3b5a 653 crc = (crc >> 23) & 0x3F;
Michael J. Spencer 2:1df0b61d3b5a 654
Michael J. Spencer 2:1df0b61d3b5a 655 pReg = (crc > 31) ? ((volatile uint32_t *)&LPC_EMAC->HashFilterH) \
Michael J. Spencer 2:1df0b61d3b5a 656 : ((volatile uint32_t *)&LPC_EMAC->HashFilterL);
Michael J. Spencer 2:1df0b61d3b5a 657 tmp = (crc > 31) ? (crc - 32) : crc;
Michael J. Spencer 2:1df0b61d3b5a 658 if (NewState == ENABLE) {
Michael J. Spencer 2:1df0b61d3b5a 659 (*pReg) |= (1UL << tmp);
Michael J. Spencer 2:1df0b61d3b5a 660 } else {
Michael J. Spencer 2:1df0b61d3b5a 661 (*pReg) &= ~(1UL << tmp);
Michael J. Spencer 2:1df0b61d3b5a 662 }
Michael J. Spencer 2:1df0b61d3b5a 663 // Enable Rx Filter
Michael J. Spencer 2:1df0b61d3b5a 664 LPC_EMAC->Command &= ~EMAC_CR_PASS_RX_FILT;
Michael J. Spencer 2:1df0b61d3b5a 665 }
Michael J. Spencer 2:1df0b61d3b5a 666
Michael J. Spencer 2:1df0b61d3b5a 667 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 668 * @brief Enable/Disable Filter mode for each specified type EMAC peripheral
Michael J. Spencer 2:1df0b61d3b5a 669 * @param[in] ulFilterMode Filter mode, should be:
Michael J. Spencer 2:1df0b61d3b5a 670 * - EMAC_RFC_UCAST_EN: all frames of unicast types
Michael J. Spencer 2:1df0b61d3b5a 671 * will be accepted
Michael J. Spencer 2:1df0b61d3b5a 672 * - EMAC_RFC_BCAST_EN: broadcast frame will be
Michael J. Spencer 2:1df0b61d3b5a 673 * accepted
Michael J. Spencer 2:1df0b61d3b5a 674 * - EMAC_RFC_MCAST_EN: all frames of multicast
Michael J. Spencer 2:1df0b61d3b5a 675 * types will be accepted
Michael J. Spencer 2:1df0b61d3b5a 676 * - EMAC_RFC_UCAST_HASH_EN: The imperfect hash
Michael J. Spencer 2:1df0b61d3b5a 677 * filter will be applied to unicast addresses
Michael J. Spencer 2:1df0b61d3b5a 678 * - EMAC_RFC_MCAST_HASH_EN: The imperfect hash
Michael J. Spencer 2:1df0b61d3b5a 679 * filter will be applied to multicast addresses
Michael J. Spencer 2:1df0b61d3b5a 680 * - EMAC_RFC_PERFECT_EN: the destination address
Michael J. Spencer 2:1df0b61d3b5a 681 * will be compared with the 6 byte station address
Michael J. Spencer 2:1df0b61d3b5a 682 * programmed in the station address by the filter
Michael J. Spencer 2:1df0b61d3b5a 683 * - EMAC_RFC_MAGP_WOL_EN: the result of the magic
Michael J. Spencer 2:1df0b61d3b5a 684 * packet filter will generate a WoL interrupt when
Michael J. Spencer 2:1df0b61d3b5a 685 * there is a match
Michael J. Spencer 2:1df0b61d3b5a 686 * - EMAC_RFC_PFILT_WOL_EN: the result of the perfect address
Michael J. Spencer 2:1df0b61d3b5a 687 * matching filter and the imperfect hash filter will
Michael J. Spencer 2:1df0b61d3b5a 688 * generate a WoL interrupt when there is a match
Michael J. Spencer 2:1df0b61d3b5a 689 * @param[in] NewState New State of this command, should be:
Michael J. Spencer 2:1df0b61d3b5a 690 * - ENABLE
Michael J. Spencer 2:1df0b61d3b5a 691 * - DISABLE
Michael J. Spencer 2:1df0b61d3b5a 692 * @return None
Michael J. Spencer 2:1df0b61d3b5a 693 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 694 void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState)
Michael J. Spencer 2:1df0b61d3b5a 695 {
Michael J. Spencer 2:1df0b61d3b5a 696 if (NewState == ENABLE){
Michael J. Spencer 2:1df0b61d3b5a 697 LPC_EMAC->RxFilterCtrl |= ulFilterMode;
Michael J. Spencer 2:1df0b61d3b5a 698 } else {
Michael J. Spencer 2:1df0b61d3b5a 699 LPC_EMAC->RxFilterCtrl &= ~ulFilterMode;
Michael J. Spencer 2:1df0b61d3b5a 700 }
Michael J. Spencer 2:1df0b61d3b5a 701 }
Michael J. Spencer 2:1df0b61d3b5a 702
Michael J. Spencer 2:1df0b61d3b5a 703 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 704 * @brief Get status of Wake On LAN Filter for each specified
Michael J. Spencer 2:1df0b61d3b5a 705 * type in EMAC peripheral, clear this status if it is set
Michael J. Spencer 2:1df0b61d3b5a 706 * @param[in] ulWoLMode WoL Filter mode, should be:
Michael J. Spencer 2:1df0b61d3b5a 707 * - EMAC_WOL_UCAST: unicast frames caused WoL
Michael J. Spencer 2:1df0b61d3b5a 708 * - EMAC_WOL_UCAST: broadcast frame caused WoL
Michael J. Spencer 2:1df0b61d3b5a 709 * - EMAC_WOL_MCAST: multicast frame caused WoL
Michael J. Spencer 2:1df0b61d3b5a 710 * - EMAC_WOL_UCAST_HASH: unicast frame that passes the
Michael J. Spencer 2:1df0b61d3b5a 711 * imperfect hash filter caused WoL
Michael J. Spencer 2:1df0b61d3b5a 712 * - EMAC_WOL_MCAST_HASH: multicast frame that passes the
Michael J. Spencer 2:1df0b61d3b5a 713 * imperfect hash filter caused WoL
Michael J. Spencer 2:1df0b61d3b5a 714 * - EMAC_WOL_PERFECT:perfect address matching filter
Michael J. Spencer 2:1df0b61d3b5a 715 * caused WoL
Michael J. Spencer 2:1df0b61d3b5a 716 * - EMAC_WOL_RX_FILTER: the receive filter caused WoL
Michael J. Spencer 2:1df0b61d3b5a 717 * - EMAC_WOL_MAG_PACKET: the magic packet filter caused WoL
Michael J. Spencer 2:1df0b61d3b5a 718 * @return SET/RESET
Michael J. Spencer 2:1df0b61d3b5a 719 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 720 FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode)
Michael J. Spencer 2:1df0b61d3b5a 721 {
Michael J. Spencer 2:1df0b61d3b5a 722 if (LPC_EMAC->RxFilterWoLStatus & ulWoLMode) {
Michael J. Spencer 2:1df0b61d3b5a 723 LPC_EMAC->RxFilterWoLClear = ulWoLMode;
Michael J. Spencer 2:1df0b61d3b5a 724 return SET;
Michael J. Spencer 2:1df0b61d3b5a 725 } else {
Michael J. Spencer 2:1df0b61d3b5a 726 return RESET;
Michael J. Spencer 2:1df0b61d3b5a 727 }
Michael J. Spencer 2:1df0b61d3b5a 728 }
Michael J. Spencer 2:1df0b61d3b5a 729
Michael J. Spencer 2:1df0b61d3b5a 730
Michael J. Spencer 2:1df0b61d3b5a 731 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 732 * @brief Write data to Tx packet data buffer at current index due to
Michael J. Spencer 2:1df0b61d3b5a 733 * TxProduceIndex
Michael J. Spencer 2:1df0b61d3b5a 734 * @param[in] pDataStruct Pointer to a EMAC_PACKETBUF_Type structure
Michael J. Spencer 2:1df0b61d3b5a 735 * data that contain specified information about
Michael J. Spencer 2:1df0b61d3b5a 736 * Packet data buffer.
Michael J. Spencer 2:1df0b61d3b5a 737 * @return None
Michael J. Spencer 2:1df0b61d3b5a 738 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 739 void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct)
Michael J. Spencer 2:1df0b61d3b5a 740 {
Michael J. Spencer 2:1df0b61d3b5a 741 uint32_t idx,len;
Michael J. Spencer 2:1df0b61d3b5a 742 uint32_t *sp,*dp;
Michael J. Spencer 2:1df0b61d3b5a 743
Michael J. Spencer 2:1df0b61d3b5a 744 idx = LPC_EMAC->TxProduceIndex;
Michael J. Spencer 2:1df0b61d3b5a 745 sp = (uint32_t *)pDataStruct->pbDataBuf;
Michael J. Spencer 2:1df0b61d3b5a 746 dp = (uint32_t *)Tx_Desc[idx].Packet;
Michael J. Spencer 2:1df0b61d3b5a 747 /* Copy frame data to EMAC packet buffers. */
Michael J. Spencer 2:1df0b61d3b5a 748 for (len = (pDataStruct->ulDataLen + 3) >> 2; len; len--) {
Michael J. Spencer 2:1df0b61d3b5a 749 *dp++ = *sp++;
Michael J. Spencer 2:1df0b61d3b5a 750 }
Michael J. Spencer 2:1df0b61d3b5a 751 Tx_Desc[idx].Ctrl = (pDataStruct->ulDataLen - 1) | (EMAC_TCTRL_INT | EMAC_TCTRL_LAST);
Michael J. Spencer 2:1df0b61d3b5a 752 }
Michael J. Spencer 2:1df0b61d3b5a 753
Michael J. Spencer 2:1df0b61d3b5a 754 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 755 * @brief Read data from Rx packet data buffer at current index due
Michael J. Spencer 2:1df0b61d3b5a 756 * to RxConsumeIndex
Michael J. Spencer 2:1df0b61d3b5a 757 * @param[in] pDataStruct Pointer to a EMAC_PACKETBUF_Type structure
Michael J. Spencer 2:1df0b61d3b5a 758 * data that contain specified information about
Michael J. Spencer 2:1df0b61d3b5a 759 * Packet data buffer.
Michael J. Spencer 2:1df0b61d3b5a 760 * @return None
Michael J. Spencer 2:1df0b61d3b5a 761 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 762 void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct)
Michael J. Spencer 2:1df0b61d3b5a 763 {
Michael J. Spencer 2:1df0b61d3b5a 764 uint32_t idx, len;
Michael J. Spencer 2:1df0b61d3b5a 765 uint32_t *dp, *sp;
Michael J. Spencer 2:1df0b61d3b5a 766
Michael J. Spencer 2:1df0b61d3b5a 767 idx = LPC_EMAC->RxConsumeIndex;
Michael J. Spencer 2:1df0b61d3b5a 768 dp = (uint32_t *)pDataStruct->pbDataBuf;
Michael J. Spencer 2:1df0b61d3b5a 769 sp = (uint32_t *)Rx_Desc[idx].Packet;
Michael J. Spencer 2:1df0b61d3b5a 770
Michael J. Spencer 2:1df0b61d3b5a 771 if (pDataStruct->pbDataBuf != NULL) {
Michael J. Spencer 2:1df0b61d3b5a 772 for (len = (pDataStruct->ulDataLen + 3) >> 2; len; len--) {
Michael J. Spencer 2:1df0b61d3b5a 773 *dp++ = *sp++;
Michael J. Spencer 2:1df0b61d3b5a 774 }
Michael J. Spencer 2:1df0b61d3b5a 775 }
Michael J. Spencer 2:1df0b61d3b5a 776 }
Michael J. Spencer 2:1df0b61d3b5a 777
Michael J. Spencer 2:1df0b61d3b5a 778 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 779 * @brief Enable/Disable interrupt for each type in EMAC
Michael J. Spencer 2:1df0b61d3b5a 780 * @param[in] ulIntType Interrupt Type, should be:
Michael J. Spencer 2:1df0b61d3b5a 781 * - EMAC_INT_RX_OVERRUN: Receive Overrun
Michael J. Spencer 2:1df0b61d3b5a 782 * - EMAC_INT_RX_ERR: Receive Error
Michael J. Spencer 2:1df0b61d3b5a 783 * - EMAC_INT_RX_FIN: Receive Descriptor Finish
Michael J. Spencer 2:1df0b61d3b5a 784 * - EMAC_INT_RX_DONE: Receive Done
Michael J. Spencer 2:1df0b61d3b5a 785 * - EMAC_INT_TX_UNDERRUN: Transmit Under-run
Michael J. Spencer 2:1df0b61d3b5a 786 * - EMAC_INT_TX_ERR: Transmit Error
Michael J. Spencer 2:1df0b61d3b5a 787 * - EMAC_INT_TX_FIN: Transmit descriptor finish
Michael J. Spencer 2:1df0b61d3b5a 788 * - EMAC_INT_TX_DONE: Transmit Done
Michael J. Spencer 2:1df0b61d3b5a 789 * - EMAC_INT_SOFT_INT: Software interrupt
Michael J. Spencer 2:1df0b61d3b5a 790 * - EMAC_INT_WAKEUP: Wakeup interrupt
Michael J. Spencer 2:1df0b61d3b5a 791 * @param[in] NewState New State of this function, should be:
Michael J. Spencer 2:1df0b61d3b5a 792 * - ENABLE.
Michael J. Spencer 2:1df0b61d3b5a 793 * - DISABLE.
Michael J. Spencer 2:1df0b61d3b5a 794 * @return None
Michael J. Spencer 2:1df0b61d3b5a 795 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 796 void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState)
Michael J. Spencer 2:1df0b61d3b5a 797 {
Michael J. Spencer 2:1df0b61d3b5a 798 if (NewState == ENABLE) {
Michael J. Spencer 2:1df0b61d3b5a 799 LPC_EMAC->IntEnable |= ulIntType;
Michael J. Spencer 2:1df0b61d3b5a 800 } else {
Michael J. Spencer 2:1df0b61d3b5a 801 LPC_EMAC->IntEnable &= ~(ulIntType);
Michael J. Spencer 2:1df0b61d3b5a 802 }
Michael J. Spencer 2:1df0b61d3b5a 803 }
Michael J. Spencer 2:1df0b61d3b5a 804
Michael J. Spencer 2:1df0b61d3b5a 805 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 806 * @brief Check whether if specified interrupt flag is set or not
Michael J. Spencer 2:1df0b61d3b5a 807 * for each interrupt type in EMAC and clear interrupt pending
Michael J. Spencer 2:1df0b61d3b5a 808 * if it is set.
Michael J. Spencer 2:1df0b61d3b5a 809 * @param[in] ulIntType Interrupt Type, should be:
Michael J. Spencer 2:1df0b61d3b5a 810 * - EMAC_INT_RX_OVERRUN: Receive Overrun
Michael J. Spencer 2:1df0b61d3b5a 811 * - EMAC_INT_RX_ERR: Receive Error
Michael J. Spencer 2:1df0b61d3b5a 812 * - EMAC_INT_RX_FIN: Receive Descriptor Finish
Michael J. Spencer 2:1df0b61d3b5a 813 * - EMAC_INT_RX_DONE: Receive Done
Michael J. Spencer 2:1df0b61d3b5a 814 * - EMAC_INT_TX_UNDERRUN: Transmit Under-run
Michael J. Spencer 2:1df0b61d3b5a 815 * - EMAC_INT_TX_ERR: Transmit Error
Michael J. Spencer 2:1df0b61d3b5a 816 * - EMAC_INT_TX_FIN: Transmit descriptor finish
Michael J. Spencer 2:1df0b61d3b5a 817 * - EMAC_INT_TX_DONE: Transmit Done
Michael J. Spencer 2:1df0b61d3b5a 818 * - EMAC_INT_SOFT_INT: Software interrupt
Michael J. Spencer 2:1df0b61d3b5a 819 * - EMAC_INT_WAKEUP: Wakeup interrupt
Michael J. Spencer 2:1df0b61d3b5a 820 * @return New state of specified interrupt (SET or RESET)
Michael J. Spencer 2:1df0b61d3b5a 821 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 822 IntStatus EMAC_IntGetStatus(uint32_t ulIntType)
Michael J. Spencer 2:1df0b61d3b5a 823 {
Michael J. Spencer 2:1df0b61d3b5a 824 if (LPC_EMAC->IntStatus & ulIntType) {
Michael J. Spencer 2:1df0b61d3b5a 825 LPC_EMAC->IntClear = ulIntType;
Michael J. Spencer 2:1df0b61d3b5a 826 return SET;
Michael J. Spencer 2:1df0b61d3b5a 827 } else {
Michael J. Spencer 2:1df0b61d3b5a 828 return RESET;
Michael J. Spencer 2:1df0b61d3b5a 829 }
Michael J. Spencer 2:1df0b61d3b5a 830 }
Michael J. Spencer 2:1df0b61d3b5a 831
Michael J. Spencer 2:1df0b61d3b5a 832
Michael J. Spencer 2:1df0b61d3b5a 833 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 834 * @brief Check whether if the current RxConsumeIndex is not equal to the
Michael J. Spencer 2:1df0b61d3b5a 835 * current RxProduceIndex.
Michael J. Spencer 2:1df0b61d3b5a 836 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 837 * @return TRUE if they're not equal, otherwise return FALSE
Michael J. Spencer 2:1df0b61d3b5a 838 *
Michael J. Spencer 2:1df0b61d3b5a 839 * Note: In case the RxConsumeIndex is not equal to the RxProduceIndex,
Michael J. Spencer 2:1df0b61d3b5a 840 * it means there're available data has been received. They should be read
Michael J. Spencer 2:1df0b61d3b5a 841 * out and released the Receive Data Buffer by updating the RxConsumeIndex value.
Michael J. Spencer 2:1df0b61d3b5a 842 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 843 Bool EMAC_CheckReceiveIndex(void)
Michael J. Spencer 2:1df0b61d3b5a 844 {
Michael J. Spencer 2:1df0b61d3b5a 845 if (LPC_EMAC->RxConsumeIndex != LPC_EMAC->RxProduceIndex) {
Michael J. Spencer 2:1df0b61d3b5a 846 return TRUE;
Michael J. Spencer 2:1df0b61d3b5a 847 } else {
Michael J. Spencer 2:1df0b61d3b5a 848 return FALSE;
Michael J. Spencer 2:1df0b61d3b5a 849 }
Michael J. Spencer 2:1df0b61d3b5a 850 }
Michael J. Spencer 2:1df0b61d3b5a 851
Michael J. Spencer 2:1df0b61d3b5a 852
Michael J. Spencer 2:1df0b61d3b5a 853 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 854 * @brief Check whether if the current TxProduceIndex is not equal to the
Michael J. Spencer 2:1df0b61d3b5a 855 * current RxProduceIndex - 1.
Michael J. Spencer 2:1df0b61d3b5a 856 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 857 * @return TRUE if they're not equal, otherwise return FALSE
Michael J. Spencer 2:1df0b61d3b5a 858 *
Michael J. Spencer 2:1df0b61d3b5a 859 * Note: In case the RxConsumeIndex is equal to the RxProduceIndex - 1,
Michael J. Spencer 2:1df0b61d3b5a 860 * it means the transmit buffer is available and data can be written to transmit
Michael J. Spencer 2:1df0b61d3b5a 861 * buffer to be sent.
Michael J. Spencer 2:1df0b61d3b5a 862 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 863 Bool EMAC_CheckTransmitIndex(void)
Michael J. Spencer 2:1df0b61d3b5a 864 {
Michael J. Spencer 2:1df0b61d3b5a 865 uint32_t tmp = LPC_EMAC->TxConsumeIndex -1;
Michael J. Spencer 2:1df0b61d3b5a 866 if (LPC_EMAC->TxProduceIndex == tmp) {
Michael J. Spencer 2:1df0b61d3b5a 867 return FALSE;
Michael J. Spencer 2:1df0b61d3b5a 868 } else {
Michael J. Spencer 2:1df0b61d3b5a 869 return TRUE;
Michael J. Spencer 2:1df0b61d3b5a 870 }
Michael J. Spencer 2:1df0b61d3b5a 871 }
Michael J. Spencer 2:1df0b61d3b5a 872
Michael J. Spencer 2:1df0b61d3b5a 873
Michael J. Spencer 2:1df0b61d3b5a 874 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 875 * @brief Get current status value of receive data (due to RxConsumeIndex)
Michael J. Spencer 2:1df0b61d3b5a 876 * @param[in] ulRxStatType Received Status type, should be one of following:
Michael J. Spencer 2:1df0b61d3b5a 877 * - EMAC_RINFO_CTRL_FRAME: Control Frame
Michael J. Spencer 2:1df0b61d3b5a 878 * - EMAC_RINFO_VLAN: VLAN Frame
Michael J. Spencer 2:1df0b61d3b5a 879 * - EMAC_RINFO_FAIL_FILT: RX Filter Failed
Michael J. Spencer 2:1df0b61d3b5a 880 * - EMAC_RINFO_MCAST: Multicast Frame
Michael J. Spencer 2:1df0b61d3b5a 881 * - EMAC_RINFO_BCAST: Broadcast Frame
Michael J. Spencer 2:1df0b61d3b5a 882 * - EMAC_RINFO_CRC_ERR: CRC Error in Frame
Michael J. Spencer 2:1df0b61d3b5a 883 * - EMAC_RINFO_SYM_ERR: Symbol Error from PHY
Michael J. Spencer 2:1df0b61d3b5a 884 * - EMAC_RINFO_LEN_ERR: Length Error
Michael J. Spencer 2:1df0b61d3b5a 885 * - EMAC_RINFO_RANGE_ERR: Range error(exceeded max size)
Michael J. Spencer 2:1df0b61d3b5a 886 * - EMAC_RINFO_ALIGN_ERR: Alignment error
Michael J. Spencer 2:1df0b61d3b5a 887 * - EMAC_RINFO_OVERRUN: Receive overrun
Michael J. Spencer 2:1df0b61d3b5a 888 * - EMAC_RINFO_NO_DESCR: No new Descriptor available
Michael J. Spencer 2:1df0b61d3b5a 889 * - EMAC_RINFO_LAST_FLAG: last Fragment in Frame
Michael J. Spencer 2:1df0b61d3b5a 890 * - EMAC_RINFO_ERR: Error Occurred (OR of all error)
Michael J. Spencer 2:1df0b61d3b5a 891 * @return Current value of receive data (due to RxConsumeIndex)
Michael J. Spencer 2:1df0b61d3b5a 892 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 893 FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType)
Michael J. Spencer 2:1df0b61d3b5a 894 {
Michael J. Spencer 2:1df0b61d3b5a 895 uint32_t idx;
Michael J. Spencer 2:1df0b61d3b5a 896 idx = LPC_EMAC->RxConsumeIndex;
Michael J. Spencer 2:1df0b61d3b5a 897 return (((Rx_Stat[idx].Info) & ulRxStatType) ? SET : RESET);
Michael J. Spencer 2:1df0b61d3b5a 898 }
Michael J. Spencer 2:1df0b61d3b5a 899
Michael J. Spencer 2:1df0b61d3b5a 900
Michael J. Spencer 2:1df0b61d3b5a 901 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 902 * @brief Get size of current Received data in received buffer (due to
Michael J. Spencer 2:1df0b61d3b5a 903 * RxConsumeIndex)
Michael J. Spencer 2:1df0b61d3b5a 904 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 905 * @return Size of received data
Michael J. Spencer 2:1df0b61d3b5a 906 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 907 uint32_t EMAC_GetReceiveDataSize(void)
Michael J. Spencer 2:1df0b61d3b5a 908 {
Michael J. Spencer 2:1df0b61d3b5a 909 uint32_t idx;
Michael J. Spencer 2:1df0b61d3b5a 910 idx =LPC_EMAC->RxConsumeIndex;
Michael J. Spencer 2:1df0b61d3b5a 911 return ((Rx_Stat[idx].Info) & EMAC_RINFO_SIZE);
Michael J. Spencer 2:1df0b61d3b5a 912 }
Michael J. Spencer 2:1df0b61d3b5a 913
Michael J. Spencer 2:1df0b61d3b5a 914 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 915 * @brief Increase the RxConsumeIndex (after reading the Receive buffer
Michael J. Spencer 2:1df0b61d3b5a 916 * to release the Receive buffer) and wrap-around the index if
Michael J. Spencer 2:1df0b61d3b5a 917 * it reaches the maximum Receive Number
Michael J. Spencer 2:1df0b61d3b5a 918 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 919 * @return None
Michael J. Spencer 2:1df0b61d3b5a 920 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 921 void EMAC_UpdateRxConsumeIndex(void)
Michael J. Spencer 2:1df0b61d3b5a 922 {
Michael J. Spencer 2:1df0b61d3b5a 923 // Get current Rx consume index
Michael J. Spencer 2:1df0b61d3b5a 924 uint32_t idx = LPC_EMAC->RxConsumeIndex;
Michael J. Spencer 2:1df0b61d3b5a 925
Michael J. Spencer 2:1df0b61d3b5a 926 /* Release frame from EMAC buffer */
Michael J. Spencer 2:1df0b61d3b5a 927 if (++idx == EMAC_NUM_RX_FRAG) idx = 0;
Michael J. Spencer 2:1df0b61d3b5a 928 LPC_EMAC->RxConsumeIndex = idx;
Michael J. Spencer 2:1df0b61d3b5a 929 }
Michael J. Spencer 2:1df0b61d3b5a 930
Michael J. Spencer 2:1df0b61d3b5a 931 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 932 * @brief Increase the TxProduceIndex (after writting to the Transmit buffer
Michael J. Spencer 2:1df0b61d3b5a 933 * to enable the Transmit buffer) and wrap-around the index if
Michael J. Spencer 2:1df0b61d3b5a 934 * it reaches the maximum Transmit Number
Michael J. Spencer 2:1df0b61d3b5a 935 * @param[in] None
Michael J. Spencer 2:1df0b61d3b5a 936 * @return None
Michael J. Spencer 2:1df0b61d3b5a 937 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 938 void EMAC_UpdateTxProduceIndex(void)
Michael J. Spencer 2:1df0b61d3b5a 939 {
Michael J. Spencer 2:1df0b61d3b5a 940 // Get current Tx produce index
Michael J. Spencer 2:1df0b61d3b5a 941 uint32_t idx = LPC_EMAC->TxProduceIndex;
Michael J. Spencer 2:1df0b61d3b5a 942
Michael J. Spencer 2:1df0b61d3b5a 943 /* Start frame transmission */
Michael J. Spencer 2:1df0b61d3b5a 944 if (++idx == EMAC_NUM_TX_FRAG) idx = 0;
Michael J. Spencer 2:1df0b61d3b5a 945 LPC_EMAC->TxProduceIndex = idx;
Michael J. Spencer 2:1df0b61d3b5a 946 }
Michael J. Spencer 2:1df0b61d3b5a 947
Michael J. Spencer 2:1df0b61d3b5a 948
Michael J. Spencer 2:1df0b61d3b5a 949 /**
Michael J. Spencer 2:1df0b61d3b5a 950 * @}
Michael J. Spencer 2:1df0b61d3b5a 951 */
Michael J. Spencer 2:1df0b61d3b5a 952
Michael J. Spencer 2:1df0b61d3b5a 953 #endif /* _EMAC */
Michael J. Spencer 2:1df0b61d3b5a 954
Michael J. Spencer 2:1df0b61d3b5a 955 /**
Michael J. Spencer 2:1df0b61d3b5a 956 * @}
Michael J. Spencer 2:1df0b61d3b5a 957 */
Michael J. Spencer 2:1df0b61d3b5a 958
Michael J. Spencer 2:1df0b61d3b5a 959 /* --------------------------------- End Of File ------------------------------ */
Michael J. Spencer 2:1df0b61d3b5a 960 #endif /* __LPC17XX__ */