Benoît Locher
Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.
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lpc17xx_emac.h
00001 /* @cond */ 00002 /***********************************************************************//** 00003 * @file lpc17xx_emac.h 00004 * @brief Contains all macro definitions and function prototypes 00005 * support for Ethernet MAC firmware library on LPC17xx 00006 * @version 2.0 00007 * @date 21. May. 2010 00008 * @author NXP MCU SW Application Team 00009 ************************************************************************** 00010 * Software that is described herein is for illustrative purposes only 00011 * which provides customers with programming information regarding the 00012 * products. This software is supplied "AS IS" without any warranties. 00013 * NXP Semiconductors assumes no responsibility or liability for the 00014 * use of the software, conveys no license or title under any patent, 00015 * copyright, or mask work right to the product. NXP Semiconductors 00016 * reserves the right to make changes in the software without 00017 * notification. NXP Semiconductors also make no representation or 00018 * warranty that such application will be suitable for the specified 00019 * use without further testing or modification. 00020 **************************************************************************/ 00021 00022 /* Peripheral group ----------------------------------------------------------- */ 00023 /** @defgroup EMAC EMAC 00024 * @ingroup LPC1700CMSIS_FwLib_Drivers 00025 * @{ 00026 */ 00027 00028 #ifndef LPC17XX_EMAC_H_ 00029 #define LPC17XX_EMAC_H_ 00030 00031 /* Includes ------------------------------------------------------------------- */ 00032 #include "LPC17xx.h" 00033 #include "lpc_types.h" 00034 00035 00036 #ifdef __cplusplus 00037 extern "C" 00038 { 00039 #endif 00040 00041 #define MCB_LPC_1768 00042 //#define IAR_LPC_1768 00043 00044 /* Public Macros -------------------------------------------------------------- */ 00045 /** @defgroup EMAC_Public_Macros EMAC Public Macros 00046 * @{ 00047 */ 00048 00049 00050 /* EMAC PHY status type definitions */ 00051 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */ 00052 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */ 00053 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */ 00054 00055 /* EMAC PHY device Speed definitions */ 00056 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */ 00057 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */ 00058 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */ 00059 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */ 00060 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */ 00061 00062 /** 00063 * @} 00064 */ 00065 /* Private Macros ------------------------------------------------------------- */ 00066 /** @defgroup EMAC_Private_Macros EMAC Private Macros 00067 * @{ 00068 */ 00069 00070 00071 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */ 00072 #define EMAC_NUM_RX_FRAG 6 /**< Num.of RX Fragments 6*1536= 9kB */ 00073 #define EMAC_NUM_TX_FRAG 4 /**< Num.of TX Fragments 4*1536= 6kB */ 00074 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */ 00075 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */ 00076 00077 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 00078 /*********************************************************************//** 00079 * Macro defines for MAC Configuration Register 1 00080 **********************************************************************/ 00081 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */ 00082 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */ 00083 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */ 00084 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */ 00085 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */ 00086 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */ 00087 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */ 00088 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */ 00089 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */ 00090 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */ 00091 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */ 00092 00093 /*********************************************************************//** 00094 * Macro defines for MAC Configuration Register 2 00095 **********************************************************************/ 00096 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */ 00097 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */ 00098 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */ 00099 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */ 00100 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */ 00101 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */ 00102 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */ 00103 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */ 00104 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */ 00105 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */ 00106 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */ 00107 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */ 00108 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */ 00109 00110 /*********************************************************************//** 00111 * Macro defines for Back-to-Back Inter-Packet-Gap Register 00112 **********************************************************************/ 00113 /** Programmable field representing the nibble time offset of the minimum possible period 00114 * between the end of any transmitted packet to the beginning of the next */ 00115 #define EMAC_IPGT_BBIPG(n) (n&0x7F) 00116 /** Recommended value for Full Duplex of Programmable field representing the nibble time 00117 * offset of the minimum possible period between the end of any transmitted packet to the 00118 * beginning of the next */ 00119 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) 00120 /** Recommended value for Half Duplex of Programmable field representing the nibble time 00121 * offset of the minimum possible period between the end of any transmitted packet to the 00122 * beginning of the next */ 00123 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) 00124 00125 /*********************************************************************//** 00126 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register 00127 **********************************************************************/ 00128 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */ 00129 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F) 00130 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */ 00131 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) 00132 /** Programmable field representing the optional carrierSense window referenced in 00133 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */ 00134 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8) 00135 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */ 00136 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) 00137 00138 /*********************************************************************//** 00139 * Macro defines for Collision Window/Retry Register 00140 **********************************************************************/ 00141 /** Programmable field specifying the number of retransmission attempts following a collision before 00142 * aborting the packet due to excessive collisions */ 00143 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F) 00144 /** Programmable field representing the slot time or collision window during which collisions occur 00145 * in properly configured networks */ 00146 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8) 00147 /** Default value for Collision Window / Retry register */ 00148 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) 00149 00150 /*********************************************************************//** 00151 * Macro defines for Maximum Frame Register 00152 **********************************************************************/ 00153 /** Represents a maximum receive frame of 1536 octets */ 00154 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF) 00155 00156 /*********************************************************************//** 00157 * Macro defines for PHY Support Register 00158 **********************************************************************/ 00159 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */ 00160 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */ 00161 00162 /*********************************************************************//** 00163 * Macro defines for Test Register 00164 **********************************************************************/ 00165 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */ 00166 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */ 00167 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */ 00168 00169 /*********************************************************************//** 00170 * Macro defines for MII Management Configuration Register 00171 **********************************************************************/ 00172 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */ 00173 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */ 00174 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */ 00175 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */ 00176 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */ 00177 00178 /*********************************************************************//** 00179 * Macro defines for MII Management Command Register 00180 **********************************************************************/ 00181 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */ 00182 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */ 00183 00184 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */ 00185 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */ 00186 00187 /*********************************************************************//** 00188 * Macro defines for MII Management Address Register 00189 **********************************************************************/ 00190 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */ 00191 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */ 00192 00193 /*********************************************************************//** 00194 * Macro defines for MII Management Write Data Register 00195 **********************************************************************/ 00196 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */ 00197 00198 /*********************************************************************//** 00199 * Macro defines for MII Management Read Data Register 00200 **********************************************************************/ 00201 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */ 00202 00203 /*********************************************************************//** 00204 * Macro defines for MII Management Indicators Register 00205 **********************************************************************/ 00206 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */ 00207 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */ 00208 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */ 00209 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */ 00210 00211 /* Station Address 0 Register */ 00212 /* Station Address 1 Register */ 00213 /* Station Address 2 Register */ 00214 00215 00216 /* Control register definitions --------------------------------------------------------------------------- */ 00217 /*********************************************************************//** 00218 * Macro defines for Command Register 00219 **********************************************************************/ 00220 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */ 00221 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */ 00222 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */ 00223 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */ 00224 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */ 00225 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */ 00226 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */ 00227 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */ 00228 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */ 00229 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */ 00230 00231 /*********************************************************************//** 00232 * Macro defines for Status Register 00233 **********************************************************************/ 00234 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */ 00235 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */ 00236 00237 /*********************************************************************//** 00238 * Macro defines for Transmit Status Vector 0 Register 00239 **********************************************************************/ 00240 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */ 00241 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */ 00242 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */ 00243 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */ 00244 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */ 00245 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */ 00246 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ 00247 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ 00248 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ 00249 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */ 00250 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ 00251 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ 00252 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ 00253 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */ 00254 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */ 00255 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */ 00256 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */ 00257 00258 /*********************************************************************//** 00259 * Macro defines for Transmit Status Vector 1 Register 00260 **********************************************************************/ 00261 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */ 00262 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */ 00263 00264 /*********************************************************************//** 00265 * Macro defines for Receive Status Vector Register 00266 **********************************************************************/ 00267 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */ 00268 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */ 00269 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */ 00270 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */ 00271 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */ 00272 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */ 00273 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */ 00274 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */ 00275 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */ 00276 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */ 00277 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */ 00278 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */ 00279 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */ 00280 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */ 00281 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */ 00282 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */ 00283 00284 /*********************************************************************//** 00285 * Macro defines for Flow Control Counter Register 00286 **********************************************************************/ 00287 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */ 00288 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */ 00289 00290 /*********************************************************************//** 00291 * Macro defines for Flow Control Status Register 00292 **********************************************************************/ 00293 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */ 00294 00295 00296 /* Receive filter register definitions -------------------------------------------------------- */ 00297 /*********************************************************************//** 00298 * Macro defines for Receive Filter Control Register 00299 **********************************************************************/ 00300 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */ 00301 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */ 00302 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */ 00303 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */ 00304 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/ 00305 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */ 00306 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */ 00307 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */ 00308 00309 /*********************************************************************//** 00310 * Macro defines for Receive Filter WoL Status/Clear Registers 00311 **********************************************************************/ 00312 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */ 00313 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */ 00314 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */ 00315 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */ 00316 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */ 00317 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */ 00318 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */ 00319 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */ 00320 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */ 00321 00322 00323 /* Module control register definitions ---------------------------------------------------- */ 00324 /*********************************************************************//** 00325 * Macro defines for Interrupt Status/Enable/Clear/Set Registers 00326 **********************************************************************/ 00327 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */ 00328 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */ 00329 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */ 00330 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */ 00331 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */ 00332 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */ 00333 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */ 00334 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */ 00335 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */ 00336 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */ 00337 00338 /*********************************************************************//** 00339 * Macro defines for Power Down Register 00340 **********************************************************************/ 00341 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */ 00342 00343 /* Descriptor and status formats ---------------------------------------------------- */ 00344 /*********************************************************************//** 00345 * Macro defines for RX Descriptor Control Word 00346 **********************************************************************/ 00347 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */ 00348 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */ 00349 00350 /*********************************************************************//** 00351 * Macro defines for RX Status Hash CRC Word 00352 **********************************************************************/ 00353 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */ 00354 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */ 00355 00356 /*********************************************************************//** 00357 * Macro defines for RX Status Information Word 00358 **********************************************************************/ 00359 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */ 00360 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */ 00361 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */ 00362 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */ 00363 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */ 00364 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */ 00365 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */ 00366 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */ 00367 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */ 00368 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */ 00369 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */ 00370 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ 00371 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ 00372 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ 00373 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ 00374 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ 00375 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) 00376 00377 /*********************************************************************//** 00378 * Macro defines for TX Descriptor Control Word 00379 **********************************************************************/ 00380 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */ 00381 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */ 00382 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */ 00383 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */ 00384 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */ 00385 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */ 00386 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */ 00387 00388 /*********************************************************************//** 00389 * Macro defines for TX Status Information Word 00390 **********************************************************************/ 00391 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */ 00392 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ 00393 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ 00394 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ 00395 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */ 00396 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ 00397 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ 00398 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ 00399 00400 #ifdef MCB_LPC_1768 00401 /* DP83848C PHY definition ------------------------------------------------------------ */ 00402 00403 /** PHY device reset time out definition */ 00404 #define EMAC_PHY_RESP_TOUT 0x100000UL 00405 00406 /* ENET Device Revision ID */ 00407 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ 00408 00409 /*********************************************************************//** 00410 * Macro defines for DP83848C PHY Registers 00411 **********************************************************************/ 00412 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ 00413 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ 00414 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ 00415 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ 00416 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ 00417 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ 00418 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ 00419 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ 00420 #define EMAC_PHY_REG_LPNPA 0x08 00421 00422 /*********************************************************************//** 00423 * Macro defines for PHY Extended Registers 00424 **********************************************************************/ 00425 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */ 00426 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */ 00427 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */ 00428 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */ 00429 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */ 00430 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */ 00431 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */ 00432 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */ 00433 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */ 00434 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */ 00435 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */ 00436 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */ 00437 00438 /*********************************************************************//** 00439 * Macro defines for PHY Basic Mode Control Register 00440 **********************************************************************/ 00441 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ 00442 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ 00443 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ 00444 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ 00445 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ 00446 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ 00447 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ 00448 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ 00449 00450 /*********************************************************************//** 00451 * Macro defines for PHY Basic Mode Status Status Register 00452 **********************************************************************/ 00453 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ 00454 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ 00455 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ 00456 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ 00457 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ 00458 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ 00459 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ 00460 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ 00461 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ 00462 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */ 00463 00464 /*********************************************************************//** 00465 * Macro defines for PHY Status Register 00466 **********************************************************************/ 00467 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */ 00468 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */ 00469 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */ 00470 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */ 00471 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */ 00472 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */ 00473 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */ 00474 00475 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ 00476 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ 00477 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ 00478 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ 00479 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ 00480 00481 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */ 00482 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */ 00483 00484 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) 00485 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) 00486 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ 00487 00488 #elif defined(IAR_LPC_1768) 00489 /* KSZ8721BL PHY definition ------------------------------------------------------------ */ 00490 /** PHY device reset time out definition */ 00491 #define EMAC_PHY_RESP_TOUT 0x100000UL 00492 00493 /* ENET Device Revision ID */ 00494 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ 00495 00496 /*********************************************************************//** 00497 * Macro defines for KSZ8721BL PHY Registers 00498 **********************************************************************/ 00499 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ 00500 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ 00501 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ 00502 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ 00503 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ 00504 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ 00505 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ 00506 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ 00507 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */ 00508 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */ 00509 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */ 00510 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */ 00511 00512 /*********************************************************************//** 00513 * Macro defines for PHY Basic Mode Control Register 00514 **********************************************************************/ 00515 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ 00516 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ 00517 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ 00518 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ 00519 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ 00520 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ 00521 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ 00522 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ 00523 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */ 00524 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */ 00525 00526 /*********************************************************************//** 00527 * Macro defines for PHY Basic Mode Status Register 00528 **********************************************************************/ 00529 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ 00530 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ 00531 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ 00532 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ 00533 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ 00534 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ 00535 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ 00536 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ 00537 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ 00538 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ 00539 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */ 00540 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */ 00541 00542 /*********************************************************************//** 00543 * Macro defines for PHY Identifier 00544 **********************************************************************/ 00545 /* PHY Identifier 1 bitmap definitions */ 00546 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */ 00547 00548 /* PHY Identifier 2 bitmap definitions */ 00549 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */ 00550 00551 /*********************************************************************//** 00552 * Macro defines for Auto-Negotiation Advertisement 00553 **********************************************************************/ 00554 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */ 00555 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */ 00556 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */ 00557 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */ 00558 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */ 00559 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */ 00560 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */ 00561 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */ 00562 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */ 00563 00564 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ 00565 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ 00566 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ 00567 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ 00568 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ 00569 00570 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) 00571 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) 00572 00573 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */ 00574 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */ 00575 #endif 00576 00577 /** 00578 * @} 00579 */ 00580 00581 00582 /* Public Types --------------------------------------------------------------- */ 00583 /** @defgroup EMAC_Public_Types EMAC Public Types 00584 * @{ 00585 */ 00586 00587 /* Descriptor and status formats ---------------------------------------------- */ 00588 00589 /** 00590 * @brief RX Descriptor structure type definition 00591 */ 00592 typedef struct { 00593 uint32_t Packet; /**< Receive Packet Descriptor */ 00594 uint32_t Ctrl; /**< Receive Control Descriptor */ 00595 } RX_Desc; 00596 00597 /** 00598 * @brief RX Status structure type definition 00599 */ 00600 typedef struct { 00601 uint32_t Info; /**< Receive Information Status */ 00602 uint32_t HashCRC; /**< Receive Hash CRC Status */ 00603 } RX_Stat; 00604 00605 /** 00606 * @brief TX Descriptor structure type definition 00607 */ 00608 typedef struct { 00609 uint32_t Packet; /**< Transmit Packet Descriptor */ 00610 uint32_t Ctrl; /**< Transmit Control Descriptor */ 00611 } TX_Desc; 00612 00613 /** 00614 * @brief TX Status structure type definition 00615 */ 00616 typedef struct { 00617 uint32_t Info; /**< Transmit Information Status */ 00618 } TX_Stat; 00619 00620 00621 /** 00622 * @brief TX Data Buffer structure definition 00623 */ 00624 typedef struct { 00625 uint32_t ulDataLen; /**< Data length */ 00626 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */ 00627 } EMAC_PACKETBUF_Type; 00628 00629 /** 00630 * @brief EMAC configuration structure definition 00631 */ 00632 typedef struct { 00633 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following: 00634 - EMAC_MODE_AUTO 00635 - EMAC_MODE_10M_FULL 00636 - EMAC_MODE_10M_HALF 00637 - EMAC_MODE_100M_FULL 00638 - EMAC_MODE_100M_HALF 00639 */ 00640 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes 00641 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5]) 00642 */ 00643 } EMAC_CFG_Type; 00644 00645 00646 /** 00647 * @} 00648 */ 00649 00650 00651 /* Public Functions ----------------------------------------------------------- */ 00652 /** @defgroup EMAC_Public_Functions EMAC Public Functions 00653 * @{ 00654 */ 00655 /* Init/DeInit EMAC peripheral */ 00656 Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct); 00657 void EMAC_DeInit(void); 00658 00659 /* PHY functions --------------*/ 00660 int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState); 00661 int32_t EMAC_SetPHYMode(uint32_t ulPHYMode); 00662 int32_t EMAC_UpdatePHYStatus(void); 00663 00664 /* Filter functions ----------*/ 00665 void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState); 00666 void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState); 00667 00668 /* EMAC Packet Buffer functions */ 00669 void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct); 00670 void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct); 00671 00672 /* EMAC Interrupt functions -------*/ 00673 void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState); 00674 IntStatus EMAC_IntGetStatus(uint32_t ulIntType); 00675 00676 /* EMAC Index functions -----------*/ 00677 Bool EMAC_CheckReceiveIndex(void); 00678 Bool EMAC_CheckTransmitIndex(void); 00679 void EMAC_UpdateRxConsumeIndex(void); 00680 void EMAC_UpdateTxProduceIndex(void); 00681 00682 FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType); 00683 uint32_t EMAC_GetReceiveDataSize(void); 00684 FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode); 00685 00686 /** 00687 * @} 00688 */ 00689 00690 #ifdef __cplusplus 00691 } 00692 #endif 00693 00694 #endif /* LPC17XX_EMAC_H_ */ 00695 00696 /** 00697 * @} 00698 */ 00699 00700 /* --------------------------------- End Of File ------------------------------ */ 00701 /* @endcond */
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