Benoît Locher / mbedNet

Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.

lpc17xx.h@0:19f5f51584de, 2011-06-12 (annotated)

Committer:
Benoit
Date:
Sun Jun 12 11:23:03 2011 +0000
Revision:
0:19f5f51584de
Child:
3:e8677c542c5d
Initial release (alpha quality)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Benoit 0:19f5f51584de 1 /**************************************************************************//**
Benoit 0:19f5f51584de 2 * @file LPC17xx.h
Benoit 0:19f5f51584de 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
Benoit 0:19f5f51584de 4 * NXP LPC17xx Device Series
Benoit 0:19f5f51584de 5 * @version: V1.08
Benoit 0:19f5f51584de 6 * @date: 21. December 2009
Benoit 0:19f5f51584de 7 *
Benoit 0:19f5f51584de 8 * @note
Benoit 0:19f5f51584de 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
Benoit 0:19f5f51584de 10 *
Benoit 0:19f5f51584de 11 * @par
Benoit 0:19f5f51584de 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Benoit 0:19f5f51584de 13 * processor based microcontrollers. This file can be freely distributed
Benoit 0:19f5f51584de 14 * within development tools that are supporting such ARM based processors.
Benoit 0:19f5f51584de 15 *
Benoit 0:19f5f51584de 16 * @par
Benoit 0:19f5f51584de 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Benoit 0:19f5f51584de 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Benoit 0:19f5f51584de 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Benoit 0:19f5f51584de 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Benoit 0:19f5f51584de 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Benoit 0:19f5f51584de 22 *
Benoit 0:19f5f51584de 23 ******************************************************************************/
Benoit 0:19f5f51584de 24
Benoit 0:19f5f51584de 25
Benoit 0:19f5f51584de 26 #ifndef __LPC17xx_H__
Benoit 0:19f5f51584de 27 #define __LPC17xx_H__
Benoit 0:19f5f51584de 28
Benoit 0:19f5f51584de 29 /*
Benoit 0:19f5f51584de 30 * ==========================================================================
Benoit 0:19f5f51584de 31 * ---------- Interrupt Number Definition -----------------------------------
Benoit 0:19f5f51584de 32 * ==========================================================================
Benoit 0:19f5f51584de 33 */
Benoit 0:19f5f51584de 34
Benoit 0:19f5f51584de 35 /** @addtogroup LPC17xx_System
Benoit 0:19f5f51584de 36 * @{
Benoit 0:19f5f51584de 37 */
Benoit 0:19f5f51584de 38
Benoit 0:19f5f51584de 39 /** @brief IRQ interrupt source definition */
Benoit 0:19f5f51584de 40 typedef enum IRQn
Benoit 0:19f5f51584de 41 {
Benoit 0:19f5f51584de 42 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
Benoit 0:19f5f51584de 43 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Benoit 0:19f5f51584de 44 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
Benoit 0:19f5f51584de 45 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
Benoit 0:19f5f51584de 46 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
Benoit 0:19f5f51584de 47 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
Benoit 0:19f5f51584de 48 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
Benoit 0:19f5f51584de 49 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
Benoit 0:19f5f51584de 50 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
Benoit 0:19f5f51584de 51
Benoit 0:19f5f51584de 52 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
Benoit 0:19f5f51584de 53 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
Benoit 0:19f5f51584de 54 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
Benoit 0:19f5f51584de 55 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
Benoit 0:19f5f51584de 56 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
Benoit 0:19f5f51584de 57 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
Benoit 0:19f5f51584de 58 UART0_IRQn = 5, /*!< UART0 Interrupt */
Benoit 0:19f5f51584de 59 UART1_IRQn = 6, /*!< UART1 Interrupt */
Benoit 0:19f5f51584de 60 UART2_IRQn = 7, /*!< UART2 Interrupt */
Benoit 0:19f5f51584de 61 UART3_IRQn = 8, /*!< UART3 Interrupt */
Benoit 0:19f5f51584de 62 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
Benoit 0:19f5f51584de 63 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
Benoit 0:19f5f51584de 64 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
Benoit 0:19f5f51584de 65 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
Benoit 0:19f5f51584de 66 SPI_IRQn = 13, /*!< SPI Interrupt */
Benoit 0:19f5f51584de 67 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
Benoit 0:19f5f51584de 68 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
Benoit 0:19f5f51584de 69 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
Benoit 0:19f5f51584de 70 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
Benoit 0:19f5f51584de 71 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
Benoit 0:19f5f51584de 72 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
Benoit 0:19f5f51584de 73 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
Benoit 0:19f5f51584de 74 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
Benoit 0:19f5f51584de 75 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
Benoit 0:19f5f51584de 76 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
Benoit 0:19f5f51584de 77 USB_IRQn = 24, /*!< USB Interrupt */
Benoit 0:19f5f51584de 78 CAN_IRQn = 25, /*!< CAN Interrupt */
Benoit 0:19f5f51584de 79 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
Benoit 0:19f5f51584de 80 I2S_IRQn = 27, /*!< I2S Interrupt */
Benoit 0:19f5f51584de 81 ENET_IRQn = 28, /*!< Ethernet Interrupt */
Benoit 0:19f5f51584de 82 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
Benoit 0:19f5f51584de 83 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
Benoit 0:19f5f51584de 84 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
Benoit 0:19f5f51584de 85 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
Benoit 0:19f5f51584de 86 USBActivity_IRQn = 33, /*!< USB Activity Interrupt */
Benoit 0:19f5f51584de 87 CANActivity_IRQn = 34, /*!< CAN Activity Interrupt */
Benoit 0:19f5f51584de 88 } IRQn_Type;
Benoit 0:19f5f51584de 89
Benoit 0:19f5f51584de 90
Benoit 0:19f5f51584de 91 /*
Benoit 0:19f5f51584de 92 * ==========================================================================
Benoit 0:19f5f51584de 93 * ----------- Processor and Core Peripheral Section ------------------------
Benoit 0:19f5f51584de 94 * ==========================================================================
Benoit 0:19f5f51584de 95 */
Benoit 0:19f5f51584de 96
Benoit 0:19f5f51584de 97 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
Benoit 0:19f5f51584de 98 #define __MPU_PRESENT 1 /*!< MPU present or not */
Benoit 0:19f5f51584de 99 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
Benoit 0:19f5f51584de 100 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Benoit 0:19f5f51584de 101
Benoit 0:19f5f51584de 102
Benoit 0:19f5f51584de 103 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
Benoit 0:19f5f51584de 104 #include "system_LPC17xx.h" /* System Header */
Benoit 0:19f5f51584de 105
Benoit 0:19f5f51584de 106
Benoit 0:19f5f51584de 107 /******************************************************************************/
Benoit 0:19f5f51584de 108 /* Device Specific Peripheral registers structures */
Benoit 0:19f5f51584de 109 /******************************************************************************/
Benoit 0:19f5f51584de 110
Benoit 0:19f5f51584de 111 #if defined ( __CC_ARM )
Benoit 0:19f5f51584de 112 #pragma anon_unions
Benoit 0:19f5f51584de 113 #endif
Benoit 0:19f5f51584de 114
Benoit 0:19f5f51584de 115 /*------------- System Control (SC) ------------------------------------------*/
Benoit 0:19f5f51584de 116 /** @brief System Control (SC) register structure definition */
Benoit 0:19f5f51584de 117 typedef struct
Benoit 0:19f5f51584de 118 {
Benoit 0:19f5f51584de 119 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
Benoit 0:19f5f51584de 120 uint32_t RESERVED0[31];
Benoit 0:19f5f51584de 121 __IO uint32_t PLL0CON; /* Clocking and Power Control */
Benoit 0:19f5f51584de 122 __IO uint32_t PLL0CFG;
Benoit 0:19f5f51584de 123 __I uint32_t PLL0STAT;
Benoit 0:19f5f51584de 124 __O uint32_t PLL0FEED;
Benoit 0:19f5f51584de 125 uint32_t RESERVED1[4];
Benoit 0:19f5f51584de 126 __IO uint32_t PLL1CON;
Benoit 0:19f5f51584de 127 __IO uint32_t PLL1CFG;
Benoit 0:19f5f51584de 128 __I uint32_t PLL1STAT;
Benoit 0:19f5f51584de 129 __O uint32_t PLL1FEED;
Benoit 0:19f5f51584de 130 uint32_t RESERVED2[4];
Benoit 0:19f5f51584de 131 __IO uint32_t PCON;
Benoit 0:19f5f51584de 132 __IO uint32_t PCONP;
Benoit 0:19f5f51584de 133 uint32_t RESERVED3[15];
Benoit 0:19f5f51584de 134 __IO uint32_t CCLKCFG;
Benoit 0:19f5f51584de 135 __IO uint32_t USBCLKCFG;
Benoit 0:19f5f51584de 136 __IO uint32_t CLKSRCSEL;
Benoit 0:19f5f51584de 137 __IO uint32_t CANSLEEPCLR;
Benoit 0:19f5f51584de 138 __IO uint32_t CANWAKEFLAGS;
Benoit 0:19f5f51584de 139 uint32_t RESERVED4[10];
Benoit 0:19f5f51584de 140 __IO uint32_t EXTINT; /* External Interrupts */
Benoit 0:19f5f51584de 141 uint32_t RESERVED5;
Benoit 0:19f5f51584de 142 __IO uint32_t EXTMODE;
Benoit 0:19f5f51584de 143 __IO uint32_t EXTPOLAR;
Benoit 0:19f5f51584de 144 uint32_t RESERVED6[12];
Benoit 0:19f5f51584de 145 __IO uint32_t RSID; /* Reset */
Benoit 0:19f5f51584de 146 uint32_t RESERVED7[7];
Benoit 0:19f5f51584de 147 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
Benoit 0:19f5f51584de 148 __IO uint32_t IRCTRIM; /* Clock Dividers */
Benoit 0:19f5f51584de 149 __IO uint32_t PCLKSEL0;
Benoit 0:19f5f51584de 150 __IO uint32_t PCLKSEL1;
Benoit 0:19f5f51584de 151 uint32_t RESERVED8[4];
Benoit 0:19f5f51584de 152 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
Benoit 0:19f5f51584de 153 __IO uint32_t DMAREQSEL;
Benoit 0:19f5f51584de 154 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
Benoit 0:19f5f51584de 155 } LPC_SC_TypeDef;
Benoit 0:19f5f51584de 156
Benoit 0:19f5f51584de 157 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
Benoit 0:19f5f51584de 158 /** @brief Pin Connect Block (PINCON) register structure definition */
Benoit 0:19f5f51584de 159 typedef struct
Benoit 0:19f5f51584de 160 {
Benoit 0:19f5f51584de 161 __IO uint32_t PINSEL0;
Benoit 0:19f5f51584de 162 __IO uint32_t PINSEL1;
Benoit 0:19f5f51584de 163 __IO uint32_t PINSEL2;
Benoit 0:19f5f51584de 164 __IO uint32_t PINSEL3;
Benoit 0:19f5f51584de 165 __IO uint32_t PINSEL4;
Benoit 0:19f5f51584de 166 __IO uint32_t PINSEL5;
Benoit 0:19f5f51584de 167 __IO uint32_t PINSEL6;
Benoit 0:19f5f51584de 168 __IO uint32_t PINSEL7;
Benoit 0:19f5f51584de 169 __IO uint32_t PINSEL8;
Benoit 0:19f5f51584de 170 __IO uint32_t PINSEL9;
Benoit 0:19f5f51584de 171 __IO uint32_t PINSEL10;
Benoit 0:19f5f51584de 172 uint32_t RESERVED0[5];
Benoit 0:19f5f51584de 173 __IO uint32_t PINMODE0;
Benoit 0:19f5f51584de 174 __IO uint32_t PINMODE1;
Benoit 0:19f5f51584de 175 __IO uint32_t PINMODE2;
Benoit 0:19f5f51584de 176 __IO uint32_t PINMODE3;
Benoit 0:19f5f51584de 177 __IO uint32_t PINMODE4;
Benoit 0:19f5f51584de 178 __IO uint32_t PINMODE5;
Benoit 0:19f5f51584de 179 __IO uint32_t PINMODE6;
Benoit 0:19f5f51584de 180 __IO uint32_t PINMODE7;
Benoit 0:19f5f51584de 181 __IO uint32_t PINMODE8;
Benoit 0:19f5f51584de 182 __IO uint32_t PINMODE9;
Benoit 0:19f5f51584de 183 __IO uint32_t PINMODE_OD0;
Benoit 0:19f5f51584de 184 __IO uint32_t PINMODE_OD1;
Benoit 0:19f5f51584de 185 __IO uint32_t PINMODE_OD2;
Benoit 0:19f5f51584de 186 __IO uint32_t PINMODE_OD3;
Benoit 0:19f5f51584de 187 __IO uint32_t PINMODE_OD4;
Benoit 0:19f5f51584de 188 __IO uint32_t I2CPADCFG;
Benoit 0:19f5f51584de 189 } LPC_PINCON_TypeDef;
Benoit 0:19f5f51584de 190
Benoit 0:19f5f51584de 191 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
Benoit 0:19f5f51584de 192 /** @brief General Purpose Input/Output (GPIO) register structure definition */
Benoit 0:19f5f51584de 193 typedef struct
Benoit 0:19f5f51584de 194 {
Benoit 0:19f5f51584de 195 union {
Benoit 0:19f5f51584de 196 __IO uint32_t FIODIR;
Benoit 0:19f5f51584de 197 struct {
Benoit 0:19f5f51584de 198 __IO uint16_t FIODIRL;
Benoit 0:19f5f51584de 199 __IO uint16_t FIODIRH;
Benoit 0:19f5f51584de 200 };
Benoit 0:19f5f51584de 201 struct {
Benoit 0:19f5f51584de 202 __IO uint8_t FIODIR0;
Benoit 0:19f5f51584de 203 __IO uint8_t FIODIR1;
Benoit 0:19f5f51584de 204 __IO uint8_t FIODIR2;
Benoit 0:19f5f51584de 205 __IO uint8_t FIODIR3;
Benoit 0:19f5f51584de 206 };
Benoit 0:19f5f51584de 207 };
Benoit 0:19f5f51584de 208 uint32_t RESERVED0[3];
Benoit 0:19f5f51584de 209 union {
Benoit 0:19f5f51584de 210 __IO uint32_t FIOMASK;
Benoit 0:19f5f51584de 211 struct {
Benoit 0:19f5f51584de 212 __IO uint16_t FIOMASKL;
Benoit 0:19f5f51584de 213 __IO uint16_t FIOMASKH;
Benoit 0:19f5f51584de 214 };
Benoit 0:19f5f51584de 215 struct {
Benoit 0:19f5f51584de 216 __IO uint8_t FIOMASK0;
Benoit 0:19f5f51584de 217 __IO uint8_t FIOMASK1;
Benoit 0:19f5f51584de 218 __IO uint8_t FIOMASK2;
Benoit 0:19f5f51584de 219 __IO uint8_t FIOMASK3;
Benoit 0:19f5f51584de 220 };
Benoit 0:19f5f51584de 221 };
Benoit 0:19f5f51584de 222 union {
Benoit 0:19f5f51584de 223 __IO uint32_t FIOPIN;
Benoit 0:19f5f51584de 224 struct {
Benoit 0:19f5f51584de 225 __IO uint16_t FIOPINL;
Benoit 0:19f5f51584de 226 __IO uint16_t FIOPINH;
Benoit 0:19f5f51584de 227 };
Benoit 0:19f5f51584de 228 struct {
Benoit 0:19f5f51584de 229 __IO uint8_t FIOPIN0;
Benoit 0:19f5f51584de 230 __IO uint8_t FIOPIN1;
Benoit 0:19f5f51584de 231 __IO uint8_t FIOPIN2;
Benoit 0:19f5f51584de 232 __IO uint8_t FIOPIN3;
Benoit 0:19f5f51584de 233 };
Benoit 0:19f5f51584de 234 };
Benoit 0:19f5f51584de 235 union {
Benoit 0:19f5f51584de 236 __IO uint32_t FIOSET;
Benoit 0:19f5f51584de 237 struct {
Benoit 0:19f5f51584de 238 __IO uint16_t FIOSETL;
Benoit 0:19f5f51584de 239 __IO uint16_t FIOSETH;
Benoit 0:19f5f51584de 240 };
Benoit 0:19f5f51584de 241 struct {
Benoit 0:19f5f51584de 242 __IO uint8_t FIOSET0;
Benoit 0:19f5f51584de 243 __IO uint8_t FIOSET1;
Benoit 0:19f5f51584de 244 __IO uint8_t FIOSET2;
Benoit 0:19f5f51584de 245 __IO uint8_t FIOSET3;
Benoit 0:19f5f51584de 246 };
Benoit 0:19f5f51584de 247 };
Benoit 0:19f5f51584de 248 union {
Benoit 0:19f5f51584de 249 __O uint32_t FIOCLR;
Benoit 0:19f5f51584de 250 struct {
Benoit 0:19f5f51584de 251 __O uint16_t FIOCLRL;
Benoit 0:19f5f51584de 252 __O uint16_t FIOCLRH;
Benoit 0:19f5f51584de 253 };
Benoit 0:19f5f51584de 254 struct {
Benoit 0:19f5f51584de 255 __O uint8_t FIOCLR0;
Benoit 0:19f5f51584de 256 __O uint8_t FIOCLR1;
Benoit 0:19f5f51584de 257 __O uint8_t FIOCLR2;
Benoit 0:19f5f51584de 258 __O uint8_t FIOCLR3;
Benoit 0:19f5f51584de 259 };
Benoit 0:19f5f51584de 260 };
Benoit 0:19f5f51584de 261 } LPC_GPIO_TypeDef;
Benoit 0:19f5f51584de 262
Benoit 0:19f5f51584de 263 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
Benoit 0:19f5f51584de 264 typedef struct
Benoit 0:19f5f51584de 265 {
Benoit 0:19f5f51584de 266 __I uint32_t IntStatus;
Benoit 0:19f5f51584de 267 __I uint32_t IO0IntStatR;
Benoit 0:19f5f51584de 268 __I uint32_t IO0IntStatF;
Benoit 0:19f5f51584de 269 __O uint32_t IO0IntClr;
Benoit 0:19f5f51584de 270 __IO uint32_t IO0IntEnR;
Benoit 0:19f5f51584de 271 __IO uint32_t IO0IntEnF;
Benoit 0:19f5f51584de 272 uint32_t RESERVED0[3];
Benoit 0:19f5f51584de 273 __I uint32_t IO2IntStatR;
Benoit 0:19f5f51584de 274 __I uint32_t IO2IntStatF;
Benoit 0:19f5f51584de 275 __O uint32_t IO2IntClr;
Benoit 0:19f5f51584de 276 __IO uint32_t IO2IntEnR;
Benoit 0:19f5f51584de 277 __IO uint32_t IO2IntEnF;
Benoit 0:19f5f51584de 278 } LPC_GPIOINT_TypeDef;
Benoit 0:19f5f51584de 279
Benoit 0:19f5f51584de 280 /*------------- Timer (TIM) --------------------------------------------------*/
Benoit 0:19f5f51584de 281 /** @brief Timer (TIM) register structure definition */
Benoit 0:19f5f51584de 282 typedef struct
Benoit 0:19f5f51584de 283 {
Benoit 0:19f5f51584de 284 __IO uint32_t IR;
Benoit 0:19f5f51584de 285 __IO uint32_t TCR;
Benoit 0:19f5f51584de 286 __IO uint32_t TC;
Benoit 0:19f5f51584de 287 __IO uint32_t PR;
Benoit 0:19f5f51584de 288 __IO uint32_t PC;
Benoit 0:19f5f51584de 289 __IO uint32_t MCR;
Benoit 0:19f5f51584de 290 __IO uint32_t MR0;
Benoit 0:19f5f51584de 291 __IO uint32_t MR1;
Benoit 0:19f5f51584de 292 __IO uint32_t MR2;
Benoit 0:19f5f51584de 293 __IO uint32_t MR3;
Benoit 0:19f5f51584de 294 __IO uint32_t CCR;
Benoit 0:19f5f51584de 295 __I uint32_t CR0;
Benoit 0:19f5f51584de 296 __I uint32_t CR1;
Benoit 0:19f5f51584de 297 uint32_t RESERVED0[2];
Benoit 0:19f5f51584de 298 __IO uint32_t EMR;
Benoit 0:19f5f51584de 299 uint32_t RESERVED1[12];
Benoit 0:19f5f51584de 300 __IO uint32_t CTCR;
Benoit 0:19f5f51584de 301 } LPC_TIM_TypeDef;
Benoit 0:19f5f51584de 302
Benoit 0:19f5f51584de 303 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
Benoit 0:19f5f51584de 304 /** @brief Pulse-Width Modulation (PWM) register structure definition */
Benoit 0:19f5f51584de 305 typedef struct
Benoit 0:19f5f51584de 306 {
Benoit 0:19f5f51584de 307 __IO uint32_t IR;
Benoit 0:19f5f51584de 308 __IO uint32_t TCR;
Benoit 0:19f5f51584de 309 __IO uint32_t TC;
Benoit 0:19f5f51584de 310 __IO uint32_t PR;
Benoit 0:19f5f51584de 311 __IO uint32_t PC;
Benoit 0:19f5f51584de 312 __IO uint32_t MCR;
Benoit 0:19f5f51584de 313 __IO uint32_t MR0;
Benoit 0:19f5f51584de 314 __IO uint32_t MR1;
Benoit 0:19f5f51584de 315 __IO uint32_t MR2;
Benoit 0:19f5f51584de 316 __IO uint32_t MR3;
Benoit 0:19f5f51584de 317 __IO uint32_t CCR;
Benoit 0:19f5f51584de 318 __I uint32_t CR0;
Benoit 0:19f5f51584de 319 __I uint32_t CR1;
Benoit 0:19f5f51584de 320 __I uint32_t CR2;
Benoit 0:19f5f51584de 321 __I uint32_t CR3;
Benoit 0:19f5f51584de 322 uint32_t RESERVED0;
Benoit 0:19f5f51584de 323 __IO uint32_t MR4;
Benoit 0:19f5f51584de 324 __IO uint32_t MR5;
Benoit 0:19f5f51584de 325 __IO uint32_t MR6;
Benoit 0:19f5f51584de 326 __IO uint32_t PCR;
Benoit 0:19f5f51584de 327 __IO uint32_t LER;
Benoit 0:19f5f51584de 328 uint32_t RESERVED1[7];
Benoit 0:19f5f51584de 329 __IO uint32_t CTCR;
Benoit 0:19f5f51584de 330 } LPC_PWM_TypeDef;
Benoit 0:19f5f51584de 331
Benoit 0:19f5f51584de 332 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
Benoit 0:19f5f51584de 333 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
Benoit 0:19f5f51584de 334 typedef struct
Benoit 0:19f5f51584de 335 {
Benoit 0:19f5f51584de 336 union {
Benoit 0:19f5f51584de 337 __I uint8_t RBR;
Benoit 0:19f5f51584de 338 __O uint8_t THR;
Benoit 0:19f5f51584de 339 __IO uint8_t DLL;
Benoit 0:19f5f51584de 340 uint32_t RESERVED0;
Benoit 0:19f5f51584de 341 };
Benoit 0:19f5f51584de 342 union {
Benoit 0:19f5f51584de 343 __IO uint8_t DLM;
Benoit 0:19f5f51584de 344 __IO uint32_t IER;
Benoit 0:19f5f51584de 345 };
Benoit 0:19f5f51584de 346 union {
Benoit 0:19f5f51584de 347 __I uint32_t IIR;
Benoit 0:19f5f51584de 348 __O uint8_t FCR;
Benoit 0:19f5f51584de 349 };
Benoit 0:19f5f51584de 350 __IO uint8_t LCR;
Benoit 0:19f5f51584de 351 uint8_t RESERVED1[7];
Benoit 0:19f5f51584de 352 __I uint8_t LSR;
Benoit 0:19f5f51584de 353 uint8_t RESERVED2[7];
Benoit 0:19f5f51584de 354 __IO uint8_t SCR;
Benoit 0:19f5f51584de 355 uint8_t RESERVED3[3];
Benoit 0:19f5f51584de 356 __IO uint32_t ACR;
Benoit 0:19f5f51584de 357 __IO uint8_t ICR;
Benoit 0:19f5f51584de 358 uint8_t RESERVED4[3];
Benoit 0:19f5f51584de 359 __IO uint8_t FDR;
Benoit 0:19f5f51584de 360 uint8_t RESERVED5[7];
Benoit 0:19f5f51584de 361 __IO uint8_t TER;
Benoit 0:19f5f51584de 362 uint8_t RESERVED6[39];
Benoit 0:19f5f51584de 363 __I uint8_t FIFOLVL;
Benoit 0:19f5f51584de 364 } LPC_UART_TypeDef;
Benoit 0:19f5f51584de 365
Benoit 0:19f5f51584de 366 /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
Benoit 0:19f5f51584de 367 typedef struct
Benoit 0:19f5f51584de 368 {
Benoit 0:19f5f51584de 369 union {
Benoit 0:19f5f51584de 370 __I uint8_t RBR;
Benoit 0:19f5f51584de 371 __O uint8_t THR;
Benoit 0:19f5f51584de 372 __IO uint8_t DLL;
Benoit 0:19f5f51584de 373 uint32_t RESERVED0;
Benoit 0:19f5f51584de 374 };
Benoit 0:19f5f51584de 375 union {
Benoit 0:19f5f51584de 376 __IO uint8_t DLM;
Benoit 0:19f5f51584de 377 __IO uint32_t IER;
Benoit 0:19f5f51584de 378 };
Benoit 0:19f5f51584de 379 union {
Benoit 0:19f5f51584de 380 __I uint32_t IIR;
Benoit 0:19f5f51584de 381 __O uint8_t FCR;
Benoit 0:19f5f51584de 382 };
Benoit 0:19f5f51584de 383 __IO uint8_t LCR;
Benoit 0:19f5f51584de 384 uint8_t RESERVED1[7];
Benoit 0:19f5f51584de 385 __I uint8_t LSR;
Benoit 0:19f5f51584de 386 uint8_t RESERVED2[7];
Benoit 0:19f5f51584de 387 __IO uint8_t SCR;
Benoit 0:19f5f51584de 388 uint8_t RESERVED3[3];
Benoit 0:19f5f51584de 389 __IO uint32_t ACR;
Benoit 0:19f5f51584de 390 __IO uint8_t ICR;
Benoit 0:19f5f51584de 391 uint8_t RESERVED4[3];
Benoit 0:19f5f51584de 392 __IO uint8_t FDR;
Benoit 0:19f5f51584de 393 uint8_t RESERVED5[7];
Benoit 0:19f5f51584de 394 __IO uint8_t TER;
Benoit 0:19f5f51584de 395 uint8_t RESERVED6[39];
Benoit 0:19f5f51584de 396 __I uint8_t FIFOLVL;
Benoit 0:19f5f51584de 397 } LPC_UART0_TypeDef;
Benoit 0:19f5f51584de 398
Benoit 0:19f5f51584de 399 /** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
Benoit 0:19f5f51584de 400 typedef struct
Benoit 0:19f5f51584de 401 {
Benoit 0:19f5f51584de 402 union {
Benoit 0:19f5f51584de 403 __I uint8_t RBR;
Benoit 0:19f5f51584de 404 __O uint8_t THR;
Benoit 0:19f5f51584de 405 __IO uint8_t DLL;
Benoit 0:19f5f51584de 406 uint32_t RESERVED0;
Benoit 0:19f5f51584de 407 };
Benoit 0:19f5f51584de 408 union {
Benoit 0:19f5f51584de 409 __IO uint8_t DLM;
Benoit 0:19f5f51584de 410 __IO uint32_t IER;
Benoit 0:19f5f51584de 411 };
Benoit 0:19f5f51584de 412 union {
Benoit 0:19f5f51584de 413 __I uint32_t IIR;
Benoit 0:19f5f51584de 414 __O uint8_t FCR;
Benoit 0:19f5f51584de 415 };
Benoit 0:19f5f51584de 416 __IO uint8_t LCR;
Benoit 0:19f5f51584de 417 uint8_t RESERVED1[3];
Benoit 0:19f5f51584de 418 __IO uint8_t MCR;
Benoit 0:19f5f51584de 419 uint8_t RESERVED2[3];
Benoit 0:19f5f51584de 420 __I uint8_t LSR;
Benoit 0:19f5f51584de 421 uint8_t RESERVED3[3];
Benoit 0:19f5f51584de 422 __I uint8_t MSR;
Benoit 0:19f5f51584de 423 uint8_t RESERVED4[3];
Benoit 0:19f5f51584de 424 __IO uint8_t SCR;
Benoit 0:19f5f51584de 425 uint8_t RESERVED5[3];
Benoit 0:19f5f51584de 426 __IO uint32_t ACR;
Benoit 0:19f5f51584de 427 uint32_t RESERVED6;
Benoit 0:19f5f51584de 428 __IO uint32_t FDR;
Benoit 0:19f5f51584de 429 uint32_t RESERVED7;
Benoit 0:19f5f51584de 430 __IO uint8_t TER;
Benoit 0:19f5f51584de 431 uint8_t RESERVED8[27];
Benoit 0:19f5f51584de 432 __IO uint8_t RS485CTRL;
Benoit 0:19f5f51584de 433 uint8_t RESERVED9[3];
Benoit 0:19f5f51584de 434 __IO uint8_t ADRMATCH;
Benoit 0:19f5f51584de 435 uint8_t RESERVED10[3];
Benoit 0:19f5f51584de 436 __IO uint8_t RS485DLY;
Benoit 0:19f5f51584de 437 uint8_t RESERVED11[3];
Benoit 0:19f5f51584de 438 __I uint8_t FIFOLVL;
Benoit 0:19f5f51584de 439 } LPC_UART1_TypeDef;
Benoit 0:19f5f51584de 440
Benoit 0:19f5f51584de 441 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
Benoit 0:19f5f51584de 442 /** @brief Serial Peripheral Interface (SPI) register structure definition */
Benoit 0:19f5f51584de 443 typedef struct
Benoit 0:19f5f51584de 444 {
Benoit 0:19f5f51584de 445 __IO uint32_t SPCR;
Benoit 0:19f5f51584de 446 __I uint32_t SPSR;
Benoit 0:19f5f51584de 447 __IO uint32_t SPDR;
Benoit 0:19f5f51584de 448 __IO uint32_t SPCCR;
Benoit 0:19f5f51584de 449 uint32_t RESERVED0[3];
Benoit 0:19f5f51584de 450 __IO uint32_t SPINT;
Benoit 0:19f5f51584de 451 } LPC_SPI_TypeDef;
Benoit 0:19f5f51584de 452
Benoit 0:19f5f51584de 453 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
Benoit 0:19f5f51584de 454 /** @brief Synchronous Serial Communication (SSP) register structure definition */
Benoit 0:19f5f51584de 455 typedef struct
Benoit 0:19f5f51584de 456 {
Benoit 0:19f5f51584de 457 __IO uint32_t CR0;
Benoit 0:19f5f51584de 458 __IO uint32_t CR1;
Benoit 0:19f5f51584de 459 __IO uint32_t DR;
Benoit 0:19f5f51584de 460 __I uint32_t SR;
Benoit 0:19f5f51584de 461 __IO uint32_t CPSR;
Benoit 0:19f5f51584de 462 __IO uint32_t IMSC;
Benoit 0:19f5f51584de 463 __IO uint32_t RIS;
Benoit 0:19f5f51584de 464 __IO uint32_t MIS;
Benoit 0:19f5f51584de 465 __IO uint32_t ICR;
Benoit 0:19f5f51584de 466 __IO uint32_t DMACR;
Benoit 0:19f5f51584de 467 } LPC_SSP_TypeDef;
Benoit 0:19f5f51584de 468
Benoit 0:19f5f51584de 469 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
Benoit 0:19f5f51584de 470 /** @brief Inter-Integrated Circuit (I2C) register structure definition */
Benoit 0:19f5f51584de 471 typedef struct
Benoit 0:19f5f51584de 472 {
Benoit 0:19f5f51584de 473 __IO uint32_t I2CONSET;
Benoit 0:19f5f51584de 474 __I uint32_t I2STAT;
Benoit 0:19f5f51584de 475 __IO uint32_t I2DAT;
Benoit 0:19f5f51584de 476 __IO uint32_t I2ADR0;
Benoit 0:19f5f51584de 477 __IO uint32_t I2SCLH;
Benoit 0:19f5f51584de 478 __IO uint32_t I2SCLL;
Benoit 0:19f5f51584de 479 __O uint32_t I2CONCLR;
Benoit 0:19f5f51584de 480 __IO uint32_t MMCTRL;
Benoit 0:19f5f51584de 481 __IO uint32_t I2ADR1;
Benoit 0:19f5f51584de 482 __IO uint32_t I2ADR2;
Benoit 0:19f5f51584de 483 __IO uint32_t I2ADR3;
Benoit 0:19f5f51584de 484 __I uint32_t I2DATA_BUFFER;
Benoit 0:19f5f51584de 485 __IO uint32_t I2MASK0;
Benoit 0:19f5f51584de 486 __IO uint32_t I2MASK1;
Benoit 0:19f5f51584de 487 __IO uint32_t I2MASK2;
Benoit 0:19f5f51584de 488 __IO uint32_t I2MASK3;
Benoit 0:19f5f51584de 489 } LPC_I2C_TypeDef;
Benoit 0:19f5f51584de 490
Benoit 0:19f5f51584de 491 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
Benoit 0:19f5f51584de 492 /** @brief Inter IC Sound (I2S) register structure definition */
Benoit 0:19f5f51584de 493 typedef struct
Benoit 0:19f5f51584de 494 {
Benoit 0:19f5f51584de 495 __IO uint32_t I2SDAO;
Benoit 0:19f5f51584de 496 __IO uint32_t I2SDAI;
Benoit 0:19f5f51584de 497 __O uint32_t I2STXFIFO;
Benoit 0:19f5f51584de 498 __I uint32_t I2SRXFIFO;
Benoit 0:19f5f51584de 499 __I uint32_t I2SSTATE;
Benoit 0:19f5f51584de 500 __IO uint32_t I2SDMA1;
Benoit 0:19f5f51584de 501 __IO uint32_t I2SDMA2;
Benoit 0:19f5f51584de 502 __IO uint32_t I2SIRQ;
Benoit 0:19f5f51584de 503 __IO uint32_t I2STXRATE;
Benoit 0:19f5f51584de 504 __IO uint32_t I2SRXRATE;
Benoit 0:19f5f51584de 505 __IO uint32_t I2STXBITRATE;
Benoit 0:19f5f51584de 506 __IO uint32_t I2SRXBITRATE;
Benoit 0:19f5f51584de 507 __IO uint32_t I2STXMODE;
Benoit 0:19f5f51584de 508 __IO uint32_t I2SRXMODE;
Benoit 0:19f5f51584de 509 } LPC_I2S_TypeDef;
Benoit 0:19f5f51584de 510
Benoit 0:19f5f51584de 511 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
Benoit 0:19f5f51584de 512 /** @brief Repetitive Interrupt Timer (RIT) register structure definition */
Benoit 0:19f5f51584de 513 typedef struct
Benoit 0:19f5f51584de 514 {
Benoit 0:19f5f51584de 515 __IO uint32_t RICOMPVAL;
Benoit 0:19f5f51584de 516 __IO uint32_t RIMASK;
Benoit 0:19f5f51584de 517 __IO uint8_t RICTRL;
Benoit 0:19f5f51584de 518 uint8_t RESERVED0[3];
Benoit 0:19f5f51584de 519 __IO uint32_t RICOUNTER;
Benoit 0:19f5f51584de 520 } LPC_RIT_TypeDef;
Benoit 0:19f5f51584de 521
Benoit 0:19f5f51584de 522 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
Benoit 0:19f5f51584de 523 /** @brief Real-Time Clock (RTC) register structure definition */
Benoit 0:19f5f51584de 524 typedef struct
Benoit 0:19f5f51584de 525 {
Benoit 0:19f5f51584de 526 __IO uint8_t ILR;
Benoit 0:19f5f51584de 527 uint8_t RESERVED0[7];
Benoit 0:19f5f51584de 528 __IO uint8_t CCR;
Benoit 0:19f5f51584de 529 uint8_t RESERVED1[3];
Benoit 0:19f5f51584de 530 __IO uint8_t CIIR;
Benoit 0:19f5f51584de 531 uint8_t RESERVED2[3];
Benoit 0:19f5f51584de 532 __IO uint8_t AMR;
Benoit 0:19f5f51584de 533 uint8_t RESERVED3[3];
Benoit 0:19f5f51584de 534 __I uint32_t CTIME0;
Benoit 0:19f5f51584de 535 __I uint32_t CTIME1;
Benoit 0:19f5f51584de 536 __I uint32_t CTIME2;
Benoit 0:19f5f51584de 537 __IO uint8_t SEC;
Benoit 0:19f5f51584de 538 uint8_t RESERVED4[3];
Benoit 0:19f5f51584de 539 __IO uint8_t MIN;
Benoit 0:19f5f51584de 540 uint8_t RESERVED5[3];
Benoit 0:19f5f51584de 541 __IO uint8_t HOUR;
Benoit 0:19f5f51584de 542 uint8_t RESERVED6[3];
Benoit 0:19f5f51584de 543 __IO uint8_t DOM;
Benoit 0:19f5f51584de 544 uint8_t RESERVED7[3];
Benoit 0:19f5f51584de 545 __IO uint8_t DOW;
Benoit 0:19f5f51584de 546 uint8_t RESERVED8[3];
Benoit 0:19f5f51584de 547 __IO uint16_t DOY;
Benoit 0:19f5f51584de 548 uint16_t RESERVED9;
Benoit 0:19f5f51584de 549 __IO uint8_t MONTH;
Benoit 0:19f5f51584de 550 uint8_t RESERVED10[3];
Benoit 0:19f5f51584de 551 __IO uint16_t YEAR;
Benoit 0:19f5f51584de 552 uint16_t RESERVED11;
Benoit 0:19f5f51584de 553 __IO uint32_t CALIBRATION;
Benoit 0:19f5f51584de 554 __IO uint32_t GPREG0;
Benoit 0:19f5f51584de 555 __IO uint32_t GPREG1;
Benoit 0:19f5f51584de 556 __IO uint32_t GPREG2;
Benoit 0:19f5f51584de 557 __IO uint32_t GPREG3;
Benoit 0:19f5f51584de 558 __IO uint32_t GPREG4;
Benoit 0:19f5f51584de 559 __IO uint8_t RTC_AUXEN;
Benoit 0:19f5f51584de 560 uint8_t RESERVED12[3];
Benoit 0:19f5f51584de 561 __IO uint8_t RTC_AUX;
Benoit 0:19f5f51584de 562 uint8_t RESERVED13[3];
Benoit 0:19f5f51584de 563 __IO uint8_t ALSEC;
Benoit 0:19f5f51584de 564 uint8_t RESERVED14[3];
Benoit 0:19f5f51584de 565 __IO uint8_t ALMIN;
Benoit 0:19f5f51584de 566 uint8_t RESERVED15[3];
Benoit 0:19f5f51584de 567 __IO uint8_t ALHOUR;
Benoit 0:19f5f51584de 568 uint8_t RESERVED16[3];
Benoit 0:19f5f51584de 569 __IO uint8_t ALDOM;
Benoit 0:19f5f51584de 570 uint8_t RESERVED17[3];
Benoit 0:19f5f51584de 571 __IO uint8_t ALDOW;
Benoit 0:19f5f51584de 572 uint8_t RESERVED18[3];
Benoit 0:19f5f51584de 573 __IO uint16_t ALDOY;
Benoit 0:19f5f51584de 574 uint16_t RESERVED19;
Benoit 0:19f5f51584de 575 __IO uint8_t ALMON;
Benoit 0:19f5f51584de 576 uint8_t RESERVED20[3];
Benoit 0:19f5f51584de 577 __IO uint16_t ALYEAR;
Benoit 0:19f5f51584de 578 uint16_t RESERVED21;
Benoit 0:19f5f51584de 579 } LPC_RTC_TypeDef;
Benoit 0:19f5f51584de 580
Benoit 0:19f5f51584de 581 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
Benoit 0:19f5f51584de 582 /** @brief Watchdog Timer (WDT) register structure definition */
Benoit 0:19f5f51584de 583 typedef struct
Benoit 0:19f5f51584de 584 {
Benoit 0:19f5f51584de 585 __IO uint8_t WDMOD;
Benoit 0:19f5f51584de 586 uint8_t RESERVED0[3];
Benoit 0:19f5f51584de 587 __IO uint32_t WDTC;
Benoit 0:19f5f51584de 588 __O uint8_t WDFEED;
Benoit 0:19f5f51584de 589 uint8_t RESERVED1[3];
Benoit 0:19f5f51584de 590 __I uint32_t WDTV;
Benoit 0:19f5f51584de 591 __IO uint32_t WDCLKSEL;
Benoit 0:19f5f51584de 592 } LPC_WDT_TypeDef;
Benoit 0:19f5f51584de 593
Benoit 0:19f5f51584de 594 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
Benoit 0:19f5f51584de 595 /** @brief Analog-to-Digital Converter (ADC) register structure definition */
Benoit 0:19f5f51584de 596 typedef struct
Benoit 0:19f5f51584de 597 {
Benoit 0:19f5f51584de 598 __IO uint32_t ADCR;
Benoit 0:19f5f51584de 599 __IO uint32_t ADGDR;
Benoit 0:19f5f51584de 600 uint32_t RESERVED0;
Benoit 0:19f5f51584de 601 __IO uint32_t ADINTEN;
Benoit 0:19f5f51584de 602 __I uint32_t ADDR0;
Benoit 0:19f5f51584de 603 __I uint32_t ADDR1;
Benoit 0:19f5f51584de 604 __I uint32_t ADDR2;
Benoit 0:19f5f51584de 605 __I uint32_t ADDR3;
Benoit 0:19f5f51584de 606 __I uint32_t ADDR4;
Benoit 0:19f5f51584de 607 __I uint32_t ADDR5;
Benoit 0:19f5f51584de 608 __I uint32_t ADDR6;
Benoit 0:19f5f51584de 609 __I uint32_t ADDR7;
Benoit 0:19f5f51584de 610 __I uint32_t ADSTAT;
Benoit 0:19f5f51584de 611 __IO uint32_t ADTRM;
Benoit 0:19f5f51584de 612 } LPC_ADC_TypeDef;
Benoit 0:19f5f51584de 613
Benoit 0:19f5f51584de 614 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
Benoit 0:19f5f51584de 615 /** @brief Digital-to-Analog Converter (DAC) register structure definition */
Benoit 0:19f5f51584de 616 typedef struct
Benoit 0:19f5f51584de 617 {
Benoit 0:19f5f51584de 618 __IO uint32_t DACR;
Benoit 0:19f5f51584de 619 __IO uint32_t DACCTRL;
Benoit 0:19f5f51584de 620 __IO uint16_t DACCNTVAL;
Benoit 0:19f5f51584de 621 } LPC_DAC_TypeDef;
Benoit 0:19f5f51584de 622
Benoit 0:19f5f51584de 623 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
Benoit 0:19f5f51584de 624 /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
Benoit 0:19f5f51584de 625 typedef struct
Benoit 0:19f5f51584de 626 {
Benoit 0:19f5f51584de 627 __I uint32_t MCCON;
Benoit 0:19f5f51584de 628 __O uint32_t MCCON_SET;
Benoit 0:19f5f51584de 629 __O uint32_t MCCON_CLR;
Benoit 0:19f5f51584de 630 __I uint32_t MCCAPCON;
Benoit 0:19f5f51584de 631 __O uint32_t MCCAPCON_SET;
Benoit 0:19f5f51584de 632 __O uint32_t MCCAPCON_CLR;
Benoit 0:19f5f51584de 633 __IO uint32_t MCTIM0;
Benoit 0:19f5f51584de 634 __IO uint32_t MCTIM1;
Benoit 0:19f5f51584de 635 __IO uint32_t MCTIM2;
Benoit 0:19f5f51584de 636 __IO uint32_t MCPER0;
Benoit 0:19f5f51584de 637 __IO uint32_t MCPER1;
Benoit 0:19f5f51584de 638 __IO uint32_t MCPER2;
Benoit 0:19f5f51584de 639 __IO uint32_t MCPW0;
Benoit 0:19f5f51584de 640 __IO uint32_t MCPW1;
Benoit 0:19f5f51584de 641 __IO uint32_t MCPW2;
Benoit 0:19f5f51584de 642 __IO uint32_t MCDEADTIME;
Benoit 0:19f5f51584de 643 __IO uint32_t MCCCP;
Benoit 0:19f5f51584de 644 __IO uint32_t MCCR0;
Benoit 0:19f5f51584de 645 __IO uint32_t MCCR1;
Benoit 0:19f5f51584de 646 __IO uint32_t MCCR2;
Benoit 0:19f5f51584de 647 __I uint32_t MCINTEN;
Benoit 0:19f5f51584de 648 __O uint32_t MCINTEN_SET;
Benoit 0:19f5f51584de 649 __O uint32_t MCINTEN_CLR;
Benoit 0:19f5f51584de 650 __I uint32_t MCCNTCON;
Benoit 0:19f5f51584de 651 __O uint32_t MCCNTCON_SET;
Benoit 0:19f5f51584de 652 __O uint32_t MCCNTCON_CLR;
Benoit 0:19f5f51584de 653 __I uint32_t MCINTFLAG;
Benoit 0:19f5f51584de 654 __O uint32_t MCINTFLAG_SET;
Benoit 0:19f5f51584de 655 __O uint32_t MCINTFLAG_CLR;
Benoit 0:19f5f51584de 656 __O uint32_t MCCAP_CLR;
Benoit 0:19f5f51584de 657 } LPC_MCPWM_TypeDef;
Benoit 0:19f5f51584de 658
Benoit 0:19f5f51584de 659 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
Benoit 0:19f5f51584de 660 /** @brief Quadrature Encoder Interface (QEI) register structure definition */
Benoit 0:19f5f51584de 661 typedef struct
Benoit 0:19f5f51584de 662 {
Benoit 0:19f5f51584de 663 __O uint32_t QEICON;
Benoit 0:19f5f51584de 664 __I uint32_t QEISTAT;
Benoit 0:19f5f51584de 665 __IO uint32_t QEICONF;
Benoit 0:19f5f51584de 666 __I uint32_t QEIPOS;
Benoit 0:19f5f51584de 667 __IO uint32_t QEIMAXPOS;
Benoit 0:19f5f51584de 668 __IO uint32_t CMPOS0;
Benoit 0:19f5f51584de 669 __IO uint32_t CMPOS1;
Benoit 0:19f5f51584de 670 __IO uint32_t CMPOS2;
Benoit 0:19f5f51584de 671 __I uint32_t INXCNT;
Benoit 0:19f5f51584de 672 __IO uint32_t INXCMP;
Benoit 0:19f5f51584de 673 __IO uint32_t QEILOAD;
Benoit 0:19f5f51584de 674 __I uint32_t QEITIME;
Benoit 0:19f5f51584de 675 __I uint32_t QEIVEL;
Benoit 0:19f5f51584de 676 __I uint32_t QEICAP;
Benoit 0:19f5f51584de 677 __IO uint32_t VELCOMP;
Benoit 0:19f5f51584de 678 __IO uint32_t FILTER;
Benoit 0:19f5f51584de 679 uint32_t RESERVED0[998];
Benoit 0:19f5f51584de 680 __O uint32_t QEIIEC;
Benoit 0:19f5f51584de 681 __O uint32_t QEIIES;
Benoit 0:19f5f51584de 682 __I uint32_t QEIINTSTAT;
Benoit 0:19f5f51584de 683 __I uint32_t QEIIE;
Benoit 0:19f5f51584de 684 __O uint32_t QEICLR;
Benoit 0:19f5f51584de 685 __O uint32_t QEISET;
Benoit 0:19f5f51584de 686 } LPC_QEI_TypeDef;
Benoit 0:19f5f51584de 687
Benoit 0:19f5f51584de 688 /*------------- Controller Area Network (CAN) --------------------------------*/
Benoit 0:19f5f51584de 689 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
Benoit 0:19f5f51584de 690 typedef struct
Benoit 0:19f5f51584de 691 {
Benoit 0:19f5f51584de 692 __IO uint32_t mask[512]; /* ID Masks */
Benoit 0:19f5f51584de 693 } LPC_CANAF_RAM_TypeDef;
Benoit 0:19f5f51584de 694
Benoit 0:19f5f51584de 695 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
Benoit 0:19f5f51584de 696 typedef struct /* Acceptance Filter Registers */
Benoit 0:19f5f51584de 697 {
Benoit 0:19f5f51584de 698 __IO uint32_t AFMR;
Benoit 0:19f5f51584de 699 __IO uint32_t SFF_sa;
Benoit 0:19f5f51584de 700 __IO uint32_t SFF_GRP_sa;
Benoit 0:19f5f51584de 701 __IO uint32_t EFF_sa;
Benoit 0:19f5f51584de 702 __IO uint32_t EFF_GRP_sa;
Benoit 0:19f5f51584de 703 __IO uint32_t ENDofTable;
Benoit 0:19f5f51584de 704 __I uint32_t LUTerrAd;
Benoit 0:19f5f51584de 705 __I uint32_t LUTerr;
Benoit 0:19f5f51584de 706 __IO uint32_t FCANIE;
Benoit 0:19f5f51584de 707 __IO uint32_t FCANIC0;
Benoit 0:19f5f51584de 708 __IO uint32_t FCANIC1;
Benoit 0:19f5f51584de 709 } LPC_CANAF_TypeDef;
Benoit 0:19f5f51584de 710
Benoit 0:19f5f51584de 711 /** @brief Controller Area Network Central (CANCR) register structure definition */
Benoit 0:19f5f51584de 712 typedef struct /* Central Registers */
Benoit 0:19f5f51584de 713 {
Benoit 0:19f5f51584de 714 __I uint32_t CANTxSR;
Benoit 0:19f5f51584de 715 __I uint32_t CANRxSR;
Benoit 0:19f5f51584de 716 __I uint32_t CANMSR;
Benoit 0:19f5f51584de 717 } LPC_CANCR_TypeDef;
Benoit 0:19f5f51584de 718
Benoit 0:19f5f51584de 719 /** @brief Controller Area Network Controller (CAN) register structure definition */
Benoit 0:19f5f51584de 720 typedef struct /* Controller Registers */
Benoit 0:19f5f51584de 721 {
Benoit 0:19f5f51584de 722 __IO uint32_t MOD;
Benoit 0:19f5f51584de 723 __O uint32_t CMR;
Benoit 0:19f5f51584de 724 __IO uint32_t GSR;
Benoit 0:19f5f51584de 725 __I uint32_t ICR;
Benoit 0:19f5f51584de 726 __IO uint32_t IER;
Benoit 0:19f5f51584de 727 __IO uint32_t BTR;
Benoit 0:19f5f51584de 728 __IO uint32_t EWL;
Benoit 0:19f5f51584de 729 __I uint32_t SR;
Benoit 0:19f5f51584de 730 __IO uint32_t RFS;
Benoit 0:19f5f51584de 731 __IO uint32_t RID;
Benoit 0:19f5f51584de 732 __IO uint32_t RDA;
Benoit 0:19f5f51584de 733 __IO uint32_t RDB;
Benoit 0:19f5f51584de 734 __IO uint32_t TFI1;
Benoit 0:19f5f51584de 735 __IO uint32_t TID1;
Benoit 0:19f5f51584de 736 __IO uint32_t TDA1;
Benoit 0:19f5f51584de 737 __IO uint32_t TDB1;
Benoit 0:19f5f51584de 738 __IO uint32_t TFI2;
Benoit 0:19f5f51584de 739 __IO uint32_t TID2;
Benoit 0:19f5f51584de 740 __IO uint32_t TDA2;
Benoit 0:19f5f51584de 741 __IO uint32_t TDB2;
Benoit 0:19f5f51584de 742 __IO uint32_t TFI3;
Benoit 0:19f5f51584de 743 __IO uint32_t TID3;
Benoit 0:19f5f51584de 744 __IO uint32_t TDA3;
Benoit 0:19f5f51584de 745 __IO uint32_t TDB3;
Benoit 0:19f5f51584de 746 } LPC_CAN_TypeDef;
Benoit 0:19f5f51584de 747
Benoit 0:19f5f51584de 748 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
Benoit 0:19f5f51584de 749 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
Benoit 0:19f5f51584de 750 typedef struct /* Common Registers */
Benoit 0:19f5f51584de 751 {
Benoit 0:19f5f51584de 752 __I uint32_t DMACIntStat;
Benoit 0:19f5f51584de 753 __I uint32_t DMACIntTCStat;
Benoit 0:19f5f51584de 754 __O uint32_t DMACIntTCClear;
Benoit 0:19f5f51584de 755 __I uint32_t DMACIntErrStat;
Benoit 0:19f5f51584de 756 __O uint32_t DMACIntErrClr;
Benoit 0:19f5f51584de 757 __I uint32_t DMACRawIntTCStat;
Benoit 0:19f5f51584de 758 __I uint32_t DMACRawIntErrStat;
Benoit 0:19f5f51584de 759 __I uint32_t DMACEnbldChns;
Benoit 0:19f5f51584de 760 __IO uint32_t DMACSoftBReq;
Benoit 0:19f5f51584de 761 __IO uint32_t DMACSoftSReq;
Benoit 0:19f5f51584de 762 __IO uint32_t DMACSoftLBReq;
Benoit 0:19f5f51584de 763 __IO uint32_t DMACSoftLSReq;
Benoit 0:19f5f51584de 764 __IO uint32_t DMACConfig;
Benoit 0:19f5f51584de 765 __IO uint32_t DMACSync;
Benoit 0:19f5f51584de 766 } LPC_GPDMA_TypeDef;
Benoit 0:19f5f51584de 767
Benoit 0:19f5f51584de 768 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
Benoit 0:19f5f51584de 769 typedef struct /* Channel Registers */
Benoit 0:19f5f51584de 770 {
Benoit 0:19f5f51584de 771 __IO uint32_t DMACCSrcAddr;
Benoit 0:19f5f51584de 772 __IO uint32_t DMACCDestAddr;
Benoit 0:19f5f51584de 773 __IO uint32_t DMACCLLI;
Benoit 0:19f5f51584de 774 __IO uint32_t DMACCControl;
Benoit 0:19f5f51584de 775 __IO uint32_t DMACCConfig;
Benoit 0:19f5f51584de 776 } LPC_GPDMACH_TypeDef;
Benoit 0:19f5f51584de 777
Benoit 0:19f5f51584de 778 /*------------- Universal Serial Bus (USB) -----------------------------------*/
Benoit 0:19f5f51584de 779 /** @brief Universal Serial Bus (USB) register structure definition */
Benoit 0:19f5f51584de 780 typedef struct
Benoit 0:19f5f51584de 781 {
Benoit 0:19f5f51584de 782 __I uint32_t HcRevision; /* USB Host Registers */
Benoit 0:19f5f51584de 783 __IO uint32_t HcControl;
Benoit 0:19f5f51584de 784 __IO uint32_t HcCommandStatus;
Benoit 0:19f5f51584de 785 __IO uint32_t HcInterruptStatus;
Benoit 0:19f5f51584de 786 __IO uint32_t HcInterruptEnable;
Benoit 0:19f5f51584de 787 __IO uint32_t HcInterruptDisable;
Benoit 0:19f5f51584de 788 __IO uint32_t HcHCCA;
Benoit 0:19f5f51584de 789 __I uint32_t HcPeriodCurrentED;
Benoit 0:19f5f51584de 790 __IO uint32_t HcControlHeadED;
Benoit 0:19f5f51584de 791 __IO uint32_t HcControlCurrentED;
Benoit 0:19f5f51584de 792 __IO uint32_t HcBulkHeadED;
Benoit 0:19f5f51584de 793 __IO uint32_t HcBulkCurrentED;
Benoit 0:19f5f51584de 794 __I uint32_t HcDoneHead;
Benoit 0:19f5f51584de 795 __IO uint32_t HcFmInterval;
Benoit 0:19f5f51584de 796 __I uint32_t HcFmRemaining;
Benoit 0:19f5f51584de 797 __I uint32_t HcFmNumber;
Benoit 0:19f5f51584de 798 __IO uint32_t HcPeriodicStart;
Benoit 0:19f5f51584de 799 __IO uint32_t HcLSTreshold;
Benoit 0:19f5f51584de 800 __IO uint32_t HcRhDescriptorA;
Benoit 0:19f5f51584de 801 __IO uint32_t HcRhDescriptorB;
Benoit 0:19f5f51584de 802 __IO uint32_t HcRhStatus;
Benoit 0:19f5f51584de 803 __IO uint32_t HcRhPortStatus1;
Benoit 0:19f5f51584de 804 __IO uint32_t HcRhPortStatus2;
Benoit 0:19f5f51584de 805 uint32_t RESERVED0[40];
Benoit 0:19f5f51584de 806 __I uint32_t Module_ID;
Benoit 0:19f5f51584de 807
Benoit 0:19f5f51584de 808 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
Benoit 0:19f5f51584de 809 __IO uint32_t OTGIntEn;
Benoit 0:19f5f51584de 810 __O uint32_t OTGIntSet;
Benoit 0:19f5f51584de 811 __O uint32_t OTGIntClr;
Benoit 0:19f5f51584de 812 __IO uint32_t OTGStCtrl;
Benoit 0:19f5f51584de 813 __IO uint32_t OTGTmr;
Benoit 0:19f5f51584de 814 uint32_t RESERVED1[58];
Benoit 0:19f5f51584de 815
Benoit 0:19f5f51584de 816 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
Benoit 0:19f5f51584de 817 __IO uint32_t USBDevIntEn;
Benoit 0:19f5f51584de 818 __O uint32_t USBDevIntClr;
Benoit 0:19f5f51584de 819 __O uint32_t USBDevIntSet;
Benoit 0:19f5f51584de 820
Benoit 0:19f5f51584de 821 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
Benoit 0:19f5f51584de 822 __I uint32_t USBCmdData;
Benoit 0:19f5f51584de 823
Benoit 0:19f5f51584de 824 __I uint32_t USBRxData; /* USB Device Transfer Registers */
Benoit 0:19f5f51584de 825 __O uint32_t USBTxData;
Benoit 0:19f5f51584de 826 __I uint32_t USBRxPLen;
Benoit 0:19f5f51584de 827 __O uint32_t USBTxPLen;
Benoit 0:19f5f51584de 828 __IO uint32_t USBCtrl;
Benoit 0:19f5f51584de 829 __O uint32_t USBDevIntPri;
Benoit 0:19f5f51584de 830
Benoit 0:19f5f51584de 831 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
Benoit 0:19f5f51584de 832 __IO uint32_t USBEpIntEn;
Benoit 0:19f5f51584de 833 __O uint32_t USBEpIntClr;
Benoit 0:19f5f51584de 834 __O uint32_t USBEpIntSet;
Benoit 0:19f5f51584de 835 __O uint32_t USBEpIntPri;
Benoit 0:19f5f51584de 836
Benoit 0:19f5f51584de 837 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
Benoit 0:19f5f51584de 838 __O uint32_t USBEpInd;
Benoit 0:19f5f51584de 839 __IO uint32_t USBMaxPSize;
Benoit 0:19f5f51584de 840
Benoit 0:19f5f51584de 841 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
Benoit 0:19f5f51584de 842 __O uint32_t USBDMARClr;
Benoit 0:19f5f51584de 843 __O uint32_t USBDMARSet;
Benoit 0:19f5f51584de 844 uint32_t RESERVED2[9];
Benoit 0:19f5f51584de 845 __IO uint32_t USBUDCAH;
Benoit 0:19f5f51584de 846 __I uint32_t USBEpDMASt;
Benoit 0:19f5f51584de 847 __O uint32_t USBEpDMAEn;
Benoit 0:19f5f51584de 848 __O uint32_t USBEpDMADis;
Benoit 0:19f5f51584de 849 __I uint32_t USBDMAIntSt;
Benoit 0:19f5f51584de 850 __IO uint32_t USBDMAIntEn;
Benoit 0:19f5f51584de 851 uint32_t RESERVED3[2];
Benoit 0:19f5f51584de 852 __I uint32_t USBEoTIntSt;
Benoit 0:19f5f51584de 853 __O uint32_t USBEoTIntClr;
Benoit 0:19f5f51584de 854 __O uint32_t USBEoTIntSet;
Benoit 0:19f5f51584de 855 __I uint32_t USBNDDRIntSt;
Benoit 0:19f5f51584de 856 __O uint32_t USBNDDRIntClr;
Benoit 0:19f5f51584de 857 __O uint32_t USBNDDRIntSet;
Benoit 0:19f5f51584de 858 __I uint32_t USBSysErrIntSt;
Benoit 0:19f5f51584de 859 __O uint32_t USBSysErrIntClr;
Benoit 0:19f5f51584de 860 __O uint32_t USBSysErrIntSet;
Benoit 0:19f5f51584de 861 uint32_t RESERVED4[15];
Benoit 0:19f5f51584de 862
Benoit 0:19f5f51584de 863 union {
Benoit 0:19f5f51584de 864 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
Benoit 0:19f5f51584de 865 __O uint32_t I2C_TX;
Benoit 0:19f5f51584de 866 };
Benoit 0:19f5f51584de 867 __I uint32_t I2C_STS;
Benoit 0:19f5f51584de 868 __IO uint32_t I2C_CTL;
Benoit 0:19f5f51584de 869 __IO uint32_t I2C_CLKHI;
Benoit 0:19f5f51584de 870 __O uint32_t I2C_CLKLO;
Benoit 0:19f5f51584de 871 uint32_t RESERVED5[824];
Benoit 0:19f5f51584de 872
Benoit 0:19f5f51584de 873 union {
Benoit 0:19f5f51584de 874 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
Benoit 0:19f5f51584de 875 __IO uint32_t OTGClkCtrl;
Benoit 0:19f5f51584de 876 };
Benoit 0:19f5f51584de 877 union {
Benoit 0:19f5f51584de 878 __I uint32_t USBClkSt;
Benoit 0:19f5f51584de 879 __I uint32_t OTGClkSt;
Benoit 0:19f5f51584de 880 };
Benoit 0:19f5f51584de 881 } LPC_USB_TypeDef;
Benoit 0:19f5f51584de 882
Benoit 0:19f5f51584de 883 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
Benoit 0:19f5f51584de 884 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */
Benoit 0:19f5f51584de 885 typedef struct
Benoit 0:19f5f51584de 886 {
Benoit 0:19f5f51584de 887 __IO uint32_t MAC1; /* MAC Registers */
Benoit 0:19f5f51584de 888 __IO uint32_t MAC2;
Benoit 0:19f5f51584de 889 __IO uint32_t IPGT;
Benoit 0:19f5f51584de 890 __IO uint32_t IPGR;
Benoit 0:19f5f51584de 891 __IO uint32_t CLRT;
Benoit 0:19f5f51584de 892 __IO uint32_t MAXF;
Benoit 0:19f5f51584de 893 __IO uint32_t SUPP;
Benoit 0:19f5f51584de 894 __IO uint32_t TEST;
Benoit 0:19f5f51584de 895 __IO uint32_t MCFG;
Benoit 0:19f5f51584de 896 __IO uint32_t MCMD;
Benoit 0:19f5f51584de 897 __IO uint32_t MADR;
Benoit 0:19f5f51584de 898 __O uint32_t MWTD;
Benoit 0:19f5f51584de 899 __I uint32_t MRDD;
Benoit 0:19f5f51584de 900 __I uint32_t MIND;
Benoit 0:19f5f51584de 901 uint32_t RESERVED0[2];
Benoit 0:19f5f51584de 902 __IO uint32_t SA0;
Benoit 0:19f5f51584de 903 __IO uint32_t SA1;
Benoit 0:19f5f51584de 904 __IO uint32_t SA2;
Benoit 0:19f5f51584de 905 uint32_t RESERVED1[45];
Benoit 0:19f5f51584de 906 __IO uint32_t Command; /* Control Registers */
Benoit 0:19f5f51584de 907 __I uint32_t Status;
Benoit 0:19f5f51584de 908 __IO uint32_t RxDescriptor;
Benoit 0:19f5f51584de 909 __IO uint32_t RxStatus;
Benoit 0:19f5f51584de 910 __IO uint32_t RxDescriptorNumber;
Benoit 0:19f5f51584de 911 __I uint32_t RxProduceIndex;
Benoit 0:19f5f51584de 912 __IO uint32_t RxConsumeIndex;
Benoit 0:19f5f51584de 913 __IO uint32_t TxDescriptor;
Benoit 0:19f5f51584de 914 __IO uint32_t TxStatus;
Benoit 0:19f5f51584de 915 __IO uint32_t TxDescriptorNumber;
Benoit 0:19f5f51584de 916 __IO uint32_t TxProduceIndex;
Benoit 0:19f5f51584de 917 __I uint32_t TxConsumeIndex;
Benoit 0:19f5f51584de 918 uint32_t RESERVED2[10];
Benoit 0:19f5f51584de 919 __I uint32_t TSV0;
Benoit 0:19f5f51584de 920 __I uint32_t TSV1;
Benoit 0:19f5f51584de 921 __I uint32_t RSV;
Benoit 0:19f5f51584de 922 uint32_t RESERVED3[3];
Benoit 0:19f5f51584de 923 __IO uint32_t FlowControlCounter;
Benoit 0:19f5f51584de 924 __I uint32_t FlowControlStatus;
Benoit 0:19f5f51584de 925 uint32_t RESERVED4[34];
Benoit 0:19f5f51584de 926 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
Benoit 0:19f5f51584de 927 __IO uint32_t RxFilterWoLStatus;
Benoit 0:19f5f51584de 928 __IO uint32_t RxFilterWoLClear;
Benoit 0:19f5f51584de 929 uint32_t RESERVED5;
Benoit 0:19f5f51584de 930 __IO uint32_t HashFilterL;
Benoit 0:19f5f51584de 931 __IO uint32_t HashFilterH;
Benoit 0:19f5f51584de 932 uint32_t RESERVED6[882];
Benoit 0:19f5f51584de 933 __I uint32_t IntStatus; /* Module Control Registers */
Benoit 0:19f5f51584de 934 __IO uint32_t IntEnable;
Benoit 0:19f5f51584de 935 __O uint32_t IntClear;
Benoit 0:19f5f51584de 936 __O uint32_t IntSet;
Benoit 0:19f5f51584de 937 uint32_t RESERVED7;
Benoit 0:19f5f51584de 938 __IO uint32_t PowerDown;
Benoit 0:19f5f51584de 939 uint32_t RESERVED8;
Benoit 0:19f5f51584de 940 __IO uint32_t Module_ID;
Benoit 0:19f5f51584de 941 } LPC_EMAC_TypeDef;
Benoit 0:19f5f51584de 942
Benoit 0:19f5f51584de 943
Benoit 0:19f5f51584de 944 #if defined ( __CC_ARM )
Benoit 0:19f5f51584de 945 #pragma no_anon_unions
Benoit 0:19f5f51584de 946 #endif
Benoit 0:19f5f51584de 947
Benoit 0:19f5f51584de 948
Benoit 0:19f5f51584de 949 /******************************************************************************/
Benoit 0:19f5f51584de 950 /* Peripheral memory map */
Benoit 0:19f5f51584de 951 /******************************************************************************/
Benoit 0:19f5f51584de 952 /* Base addresses */
Benoit 0:19f5f51584de 953 #define LPC_FLASH_BASE (0x00000000UL)
Benoit 0:19f5f51584de 954 #define LPC_RAM_BASE (0x10000000UL)
Benoit 0:19f5f51584de 955 #ifdef __LPC17XX_REV00
Benoit 0:19f5f51584de 956 #define LPC_AHBRAM0_BASE (0x20000000UL)
Benoit 0:19f5f51584de 957 #define LPC_AHBRAM1_BASE (0x20004000UL)
Benoit 0:19f5f51584de 958 #else
Benoit 0:19f5f51584de 959 #define LPC_AHBRAM0_BASE (0x2007C000UL)
Benoit 0:19f5f51584de 960 #define LPC_AHBRAM1_BASE (0x20080000UL)
Benoit 0:19f5f51584de 961 #endif
Benoit 0:19f5f51584de 962 #define LPC_GPIO_BASE (0x2009C000UL)
Benoit 0:19f5f51584de 963 #define LPC_APB0_BASE (0x40000000UL)
Benoit 0:19f5f51584de 964 #define LPC_APB1_BASE (0x40080000UL)
Benoit 0:19f5f51584de 965 #define LPC_AHB_BASE (0x50000000UL)
Benoit 0:19f5f51584de 966 #define LPC_CM3_BASE (0xE0000000UL)
Benoit 0:19f5f51584de 967
Benoit 0:19f5f51584de 968 /* APB0 peripherals */
Benoit 0:19f5f51584de 969 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
Benoit 0:19f5f51584de 970 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
Benoit 0:19f5f51584de 971 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
Benoit 0:19f5f51584de 972 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
Benoit 0:19f5f51584de 973 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
Benoit 0:19f5f51584de 974 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
Benoit 0:19f5f51584de 975 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
Benoit 0:19f5f51584de 976 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
Benoit 0:19f5f51584de 977 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
Benoit 0:19f5f51584de 978 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
Benoit 0:19f5f51584de 979 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
Benoit 0:19f5f51584de 980 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
Benoit 0:19f5f51584de 981 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
Benoit 0:19f5f51584de 982 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
Benoit 0:19f5f51584de 983 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
Benoit 0:19f5f51584de 984 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
Benoit 0:19f5f51584de 985 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
Benoit 0:19f5f51584de 986 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
Benoit 0:19f5f51584de 987 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
Benoit 0:19f5f51584de 988
Benoit 0:19f5f51584de 989 /* APB1 peripherals */
Benoit 0:19f5f51584de 990 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
Benoit 0:19f5f51584de 991 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
Benoit 0:19f5f51584de 992 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
Benoit 0:19f5f51584de 993 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
Benoit 0:19f5f51584de 994 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
Benoit 0:19f5f51584de 995 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
Benoit 0:19f5f51584de 996 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
Benoit 0:19f5f51584de 997 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
Benoit 0:19f5f51584de 998 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
Benoit 0:19f5f51584de 999 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
Benoit 0:19f5f51584de 1000 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
Benoit 0:19f5f51584de 1001 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
Benoit 0:19f5f51584de 1002
Benoit 0:19f5f51584de 1003 /* AHB peripherals */
Benoit 0:19f5f51584de 1004 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
Benoit 0:19f5f51584de 1005 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
Benoit 0:19f5f51584de 1006 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
Benoit 0:19f5f51584de 1007 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
Benoit 0:19f5f51584de 1008 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
Benoit 0:19f5f51584de 1009 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
Benoit 0:19f5f51584de 1010 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
Benoit 0:19f5f51584de 1011 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
Benoit 0:19f5f51584de 1012 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
Benoit 0:19f5f51584de 1013 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
Benoit 0:19f5f51584de 1014 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
Benoit 0:19f5f51584de 1015
Benoit 0:19f5f51584de 1016 /* GPIOs */
Benoit 0:19f5f51584de 1017 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
Benoit 0:19f5f51584de 1018 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
Benoit 0:19f5f51584de 1019 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
Benoit 0:19f5f51584de 1020 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
Benoit 0:19f5f51584de 1021 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
Benoit 0:19f5f51584de 1022
Benoit 0:19f5f51584de 1023 /******************************************************************************/
Benoit 0:19f5f51584de 1024 /* Peripheral declaration */
Benoit 0:19f5f51584de 1025 /******************************************************************************/
Benoit 0:19f5f51584de 1026 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
Benoit 0:19f5f51584de 1027 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
Benoit 0:19f5f51584de 1028 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
Benoit 0:19f5f51584de 1029 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
Benoit 0:19f5f51584de 1030 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
Benoit 0:19f5f51584de 1031 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
Benoit 0:19f5f51584de 1032 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
Benoit 0:19f5f51584de 1033 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
Benoit 0:19f5f51584de 1034 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
Benoit 0:19f5f51584de 1035 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
Benoit 0:19f5f51584de 1036 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
Benoit 0:19f5f51584de 1037 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
Benoit 0:19f5f51584de 1038 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
Benoit 0:19f5f51584de 1039 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
Benoit 0:19f5f51584de 1040 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
Benoit 0:19f5f51584de 1041 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
Benoit 0:19f5f51584de 1042 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
Benoit 0:19f5f51584de 1043 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
Benoit 0:19f5f51584de 1044 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
Benoit 0:19f5f51584de 1045 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
Benoit 0:19f5f51584de 1046 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
Benoit 0:19f5f51584de 1047 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
Benoit 0:19f5f51584de 1048 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
Benoit 0:19f5f51584de 1049 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
Benoit 0:19f5f51584de 1050 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
Benoit 0:19f5f51584de 1051 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
Benoit 0:19f5f51584de 1052 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
Benoit 0:19f5f51584de 1053 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
Benoit 0:19f5f51584de 1054 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
Benoit 0:19f5f51584de 1055 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
Benoit 0:19f5f51584de 1056 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
Benoit 0:19f5f51584de 1057 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
Benoit 0:19f5f51584de 1058 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
Benoit 0:19f5f51584de 1059 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
Benoit 0:19f5f51584de 1060 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
Benoit 0:19f5f51584de 1061 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
Benoit 0:19f5f51584de 1062 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
Benoit 0:19f5f51584de 1063 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
Benoit 0:19f5f51584de 1064 #define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4))
Benoit 0:19f5f51584de 1065 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
Benoit 0:19f5f51584de 1066 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
Benoit 0:19f5f51584de 1067 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
Benoit 0:19f5f51584de 1068 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
Benoit 0:19f5f51584de 1069 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
Benoit 0:19f5f51584de 1070 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
Benoit 0:19f5f51584de 1071 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
Benoit 0:19f5f51584de 1072 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
Benoit 0:19f5f51584de 1073 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
Benoit 0:19f5f51584de 1074
Benoit 0:19f5f51584de 1075 /**
Benoit 0:19f5f51584de 1076 * @}
Benoit 0:19f5f51584de 1077 */
Benoit 0:19f5f51584de 1078
Benoit 0:19f5f51584de 1079 #endif // __LPC17xx_H__