BEI ZHANG / Mbed 2 deprecated RM3100_SPI_SampleCode

RM3100 SPI sample code

Dependencies:   mbed

RM3100.h@0:71d5c1c75f0b, 2019-03-10 (annotated)

Committer:
BeiZhang
Date:
Sun Mar 10 01:45:12 2019 +0000
Revision:
0:71d5c1c75f0b
RM3100 SPI Sample Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
BeiZhang 0:71d5c1c75f0b 1 /**
BeiZhang 0:71d5c1c75f0b 2 * @file RM3100.h
BeiZhang 0:71d5c1c75f0b 3 *
BeiZhang 0:71d5c1c75f0b 4 * @brief Sample interface for RM3100.
BeiZhang 0:71d5c1c75f0b 5 *
BeiZhang 0:71d5c1c75f0b 6 * @authors Betty Zhang
BeiZhang 0:71d5c1c75f0b 7 * @date 05/21/2018
BeiZhang 0:71d5c1c75f0b 8 * @copyright (C) 2018 PNI Corp, Protonex LLC
BeiZhang 0:71d5c1c75f0b 9 *
BeiZhang 0:71d5c1c75f0b 10 * @copyright Disclosure to third parties or reproduction in any form
BeiZhang 0:71d5c1c75f0b 11 * whatsoever, without prior written consent, is strictly forbidden
BeiZhang 0:71d5c1c75f0b 12 *
BeiZhang 0:71d5c1c75f0b 13 */
BeiZhang 0:71d5c1c75f0b 14 #include "mbed.h"
BeiZhang 0:71d5c1c75f0b 15
BeiZhang 0:71d5c1c75f0b 16
BeiZhang 0:71d5c1c75f0b 17 // Global typedef
BeiZhang 0:71d5c1c75f0b 18 typedef signed char s8;
BeiZhang 0:71d5c1c75f0b 19 typedef char u8;
BeiZhang 0:71d5c1c75f0b 20 typedef short s16;
BeiZhang 0:71d5c1c75f0b 21 typedef unsigned short u16;
BeiZhang 0:71d5c1c75f0b 22 typedef int s32;
BeiZhang 0:71d5c1c75f0b 23 typedef unsigned int u32;
BeiZhang 0:71d5c1c75f0b 24 typedef unsigned long u64;
BeiZhang 0:71d5c1c75f0b 25
BeiZhang 0:71d5c1c75f0b 26 //RM3100 Registers
BeiZhang 0:71d5c1c75f0b 27 #define RM3100_POLL_REG 0x00 /**< RW; Poll for a single measurement*/
BeiZhang 0:71d5c1c75f0b 28 #define RM3100_CMM_REG 0x01 /**< RW; Initiate continuous measurement mode*/
BeiZhang 0:71d5c1c75f0b 29 #define RM3100_CCXLSB_REG 0x04 /**< RW; Cycle count X-axis */
BeiZhang 0:71d5c1c75f0b 30 #define RM3100_CCXMSB_REG 0x05
BeiZhang 0:71d5c1c75f0b 31 #define RM3100_CCYLSB_REG 0x06 /**< RW; Cycle count Y-axis */
BeiZhang 0:71d5c1c75f0b 32 #define RM3100_CCYMSB_REG 0x07
BeiZhang 0:71d5c1c75f0b 33 #define RM3100_CCZLSB_REG 0x08 /**< RW; Cycle count Z-axis */
BeiZhang 0:71d5c1c75f0b 34 #define RM3100_CCZMSB_REG 0x09
BeiZhang 0:71d5c1c75f0b 35 #define RM3100_TMRC_REG 0x0B /**< RW; Set data rate in continuous measurement mode*/
BeiZhang 0:71d5c1c75f0b 36 #define RM3100_MX_REG 0x24 /**< RW; Measurement Result X-axis, Signed 24-bit */
BeiZhang 0:71d5c1c75f0b 37 #define RM3100_BIST_REG 0x33 /**< RW; Built-in self test */
BeiZhang 0:71d5c1c75f0b 38 #define RM3100_STATUS_REG 0x34 /**< R; Status of DRDY */
BeiZhang 0:71d5c1c75f0b 39 #define RM3100_REVID_REG 0x36 /**< R; Revision ID, default 0x22 */
BeiZhang 0:71d5c1c75f0b 40
BeiZhang 0:71d5c1c75f0b 41 //RM3100 Default values
BeiZhang 0:71d5c1c75f0b 42 #define DEFAULTCCOUNT 200 //200
BeiZhang 0:71d5c1c75f0b 43 #define DEFAULTGAIN 75 //200 Cycle Count, Gain 75
BeiZhang 0:71d5c1c75f0b 44
BeiZhang 0:71d5c1c75f0b 45 //Other Settings
BeiZhang 0:71d5c1c75f0b 46 #define UPPERCYCLECOUNT 400
BeiZhang 0:71d5c1c75f0b 47 #define LOWERCYCLECOUNT 30
BeiZhang 0:71d5c1c75f0b 48
BeiZhang 0:71d5c1c75f0b 49
BeiZhang 0:71d5c1c75f0b 50 /**
BeiZhang 0:71d5c1c75f0b 51 * \brief Host interface control
BeiZhang 0:71d5c1c75f0b 52 */
BeiZhang 0:71d5c1c75f0b 53 #pragma pack(push, 1)
BeiZhang 0:71d5c1c75f0b 54 typedef union RegCMM
BeiZhang 0:71d5c1c75f0b 55 {
BeiZhang 0:71d5c1c75f0b 56 /**
BeiZhang 0:71d5c1c75f0b 57 * \brief Direct access to the complete 8bit register
BeiZhang 0:71d5c1c75f0b 58 */
BeiZhang 0:71d5c1c75f0b 59 u8 reg;
BeiZhang 0:71d5c1c75f0b 60 /**
BeiZhang 0:71d5c1c75f0b 61 * \brief Access to individual bits in the register.
BeiZhang 0:71d5c1c75f0b 62 */
BeiZhang 0:71d5c1c75f0b 63 struct
BeiZhang 0:71d5c1c75f0b 64 {
BeiZhang 0:71d5c1c75f0b 65 u8 Start : 1; /**< bit 0: Initiate Continuous Measurement Mode */
BeiZhang 0:71d5c1c75f0b 66 u8 Alarm : 1; /**< bit 1: Go high if measurment outside a prefefined range */
BeiZhang 0:71d5c1c75f0b 67 u8 Drdm : 2; /**< bit 2: DRDM bits establish required condition to trigger DRDY */
BeiZhang 0:71d5c1c75f0b 68 /**< 0 = drdy high when Alarm = 1 and complete of full measurement set by CMX CMY CMZ */
BeiZhang 0:71d5c1c75f0b 69 /**< 1 = drdy high after complete of measurement on any axis */
BeiZhang 0:71d5c1c75f0b 70 /**< 2 = drdy high after complete of full measurement set by CMX CMY CMZ */
BeiZhang 0:71d5c1c75f0b 71 /**< 3 = drdy high when Alarm = 1 */
BeiZhang 0:71d5c1c75f0b 72 u8 CMX : 1; /**< bit 4: 1 means measurement on this Axis */
BeiZhang 0:71d5c1c75f0b 73 u8 CMY : 1; /**< bit 5: 1 means measurement on this Axis */
BeiZhang 0:71d5c1c75f0b 74 u8 CMZ : 1; /**< bit 6: 1 means measurement on this Axis */
BeiZhang 0:71d5c1c75f0b 75 u8 LDM : 1; /**< bit 7: 0 absolute alarm mode, 1 relative alarm mode */
BeiZhang 0:71d5c1c75f0b 76 }
BeiZhang 0:71d5c1c75f0b 77 bits;
BeiZhang 0:71d5c1c75f0b 78 }
BeiZhang 0:71d5c1c75f0b 79 RegCMM; /**< typedef for storing CMM register values */
BeiZhang 0:71d5c1c75f0b 80 #pragma pack(pop)
BeiZhang 0:71d5c1c75f0b 81
BeiZhang 0:71d5c1c75f0b 82 #pragma pack(push, 1)
BeiZhang 0:71d5c1c75f0b 83 typedef union RegTMRC
BeiZhang 0:71d5c1c75f0b 84 {
BeiZhang 0:71d5c1c75f0b 85 /**
BeiZhang 0:71d5c1c75f0b 86 * \brief Direct access to the complete 8bit register
BeiZhang 0:71d5c1c75f0b 87 */
BeiZhang 0:71d5c1c75f0b 88 u8 reg;
BeiZhang 0:71d5c1c75f0b 89 /**
BeiZhang 0:71d5c1c75f0b 90 * \brief Access to individual bits in the register.
BeiZhang 0:71d5c1c75f0b 91 */
BeiZhang 0:71d5c1c75f0b 92 struct
BeiZhang 0:71d5c1c75f0b 93 {
BeiZhang 0:71d5c1c75f0b 94 u8 TMRC : 4; /**< bit 0 - 3: Time between measurement in CCM moden 1-axis */
BeiZhang 0:71d5c1c75f0b 95 /**< value 0b0010 to 0b1111, 0x2 to 0xF, bigger value longer interval */
BeiZhang 0:71d5c1c75f0b 96 u8 Resv : 4; /**< bit 4 - 7: Fixed as 0b1001, 0x9 */
BeiZhang 0:71d5c1c75f0b 97 }
BeiZhang 0:71d5c1c75f0b 98 bits;
BeiZhang 0:71d5c1c75f0b 99 }
BeiZhang 0:71d5c1c75f0b 100 RegTMRC; /**< typedef for storing TMRC register values */
BeiZhang 0:71d5c1c75f0b 101 #pragma pack(pop)
BeiZhang 0:71d5c1c75f0b 102
BeiZhang 0:71d5c1c75f0b 103 #pragma pack(push, 1)
BeiZhang 0:71d5c1c75f0b 104 typedef union RegBIST
BeiZhang 0:71d5c1c75f0b 105 {
BeiZhang 0:71d5c1c75f0b 106 /**
BeiZhang 0:71d5c1c75f0b 107 * \brief Direct access to the complete 8bit register
BeiZhang 0:71d5c1c75f0b 108 */
BeiZhang 0:71d5c1c75f0b 109 u8 reg;
BeiZhang 0:71d5c1c75f0b 110 /**
BeiZhang 0:71d5c1c75f0b 111 * \brief Access to individual bits in the register.
BeiZhang 0:71d5c1c75f0b 112 */
BeiZhang 0:71d5c1c75f0b 113 struct
BeiZhang 0:71d5c1c75f0b 114 {
BeiZhang 0:71d5c1c75f0b 115 u8 BP : 2; /**< bit 0-1: Define number of LR periods for measurement */
BeiZhang 0:71d5c1c75f0b 116 /**< 0 = unused */
BeiZhang 0:71d5c1c75f0b 117 /**< 1 = 1 LR Period */
BeiZhang 0:71d5c1c75f0b 118 /**< 2 = 2 LR Periods */
BeiZhang 0:71d5c1c75f0b 119 /**< 3 = 4 LR Periods */
BeiZhang 0:71d5c1c75f0b 120 u8 BW : 2; /**< bit 2-3: Define timeout period for LR oscillator perriod */
BeiZhang 0:71d5c1c75f0b 121 /**< 0 = unused */
BeiZhang 0:71d5c1c75f0b 122 /**< 1 = 1 sleep oscillation cycle, 30us */
BeiZhang 0:71d5c1c75f0b 123 /**< 2 = 2 sleep oscillation cycles, 60us */
BeiZhang 0:71d5c1c75f0b 124 /**< 3 = 4 sleep oscillation cycles, 120us */
BeiZhang 0:71d5c1c75f0b 125 u8 XYZOK : 3; /**< bit 4-6: Read only */
BeiZhang 0:71d5c1c75f0b 126 /**< bit 4: 1 X ok, 0 not ok */
BeiZhang 0:71d5c1c75f0b 127 /**< bit 5: 1 Y ok, 0 not ok */
BeiZhang 0:71d5c1c75f0b 128 /**< bit 6: 1 Z ok, 0 not ok */
BeiZhang 0:71d5c1c75f0b 129 u8 STE : 1; /**< bit 7: write 1 to enable the self test */
BeiZhang 0:71d5c1c75f0b 130 }
BeiZhang 0:71d5c1c75f0b 131 bits;
BeiZhang 0:71d5c1c75f0b 132 }
BeiZhang 0:71d5c1c75f0b 133 RegBIST; /**< typedef for storing TMRC register values */
BeiZhang 0:71d5c1c75f0b 134 #pragma pack(pop)
BeiZhang 0:71d5c1c75f0b 135
BeiZhang 0:71d5c1c75f0b 136 #pragma pack(push, 1)
BeiZhang 0:71d5c1c75f0b 137 typedef union RegPOLL
BeiZhang 0:71d5c1c75f0b 138 {
BeiZhang 0:71d5c1c75f0b 139 /**
BeiZhang 0:71d5c1c75f0b 140 * \brief Direct access to the complete 8bit register
BeiZhang 0:71d5c1c75f0b 141 */
BeiZhang 0:71d5c1c75f0b 142 u8 reg;
BeiZhang 0:71d5c1c75f0b 143 /**
BeiZhang 0:71d5c1c75f0b 144 * \brief Access to individual bits in the register.
BeiZhang 0:71d5c1c75f0b 145 */
BeiZhang 0:71d5c1c75f0b 146 struct
BeiZhang 0:71d5c1c75f0b 147 {
BeiZhang 0:71d5c1c75f0b 148 u8 LowNibble : 4; /**< bit 0-3: Reserved */
BeiZhang 0:71d5c1c75f0b 149 u8 PMX : 1; /**< bit 4: Measure X axis */
BeiZhang 0:71d5c1c75f0b 150 u8 PMY : 1; /**< bit 5: Measure Y axis */
BeiZhang 0:71d5c1c75f0b 151 u8 PMZ : 1; /**< bit 6: Measure Z axis */
BeiZhang 0:71d5c1c75f0b 152 u8 MSB : 1; /**< bit 7: Reserved */
BeiZhang 0:71d5c1c75f0b 153 }
BeiZhang 0:71d5c1c75f0b 154 bits;
BeiZhang 0:71d5c1c75f0b 155 }
BeiZhang 0:71d5c1c75f0b 156 RegPOLL; /**< typedef for storing TMRC register values */
BeiZhang 0:71d5c1c75f0b 157 #pragma pack(pop)
BeiZhang 0:71d5c1c75f0b 158
BeiZhang 0:71d5c1c75f0b 159
BeiZhang 0:71d5c1c75f0b 160 //RM3100 class
BeiZhang 0:71d5c1c75f0b 161 class RM3100
BeiZhang 0:71d5c1c75f0b 162 {
BeiZhang 0:71d5c1c75f0b 163
BeiZhang 0:71d5c1c75f0b 164 public:
BeiZhang 0:71d5c1c75f0b 165 void ClearDrdyInt(void);
BeiZhang 0:71d5c1c75f0b 166
BeiZhang 0:71d5c1c75f0b 167 void RunCMM(int flag);
BeiZhang 0:71d5c1c75f0b 168
BeiZhang 0:71d5c1c75f0b 169 void ChangeSampleRate(int flag);
BeiZhang 0:71d5c1c75f0b 170
BeiZhang 0:71d5c1c75f0b 171 void SetSampleRateReg(int rate);
BeiZhang 0:71d5c1c75f0b 172
BeiZhang 0:71d5c1c75f0b 173 int GetSampleRate(int * reg_val);
BeiZhang 0:71d5c1c75f0b 174
BeiZhang 0:71d5c1c75f0b 175 void ChangeCycleCount(int flag);
BeiZhang 0:71d5c1c75f0b 176
BeiZhang 0:71d5c1c75f0b 177 void SetCycleCountReg();
BeiZhang 0:71d5c1c75f0b 178
BeiZhang 0:71d5c1c75f0b 179 void ReadRM3100();
BeiZhang 0:71d5c1c75f0b 180
BeiZhang 0:71d5c1c75f0b 181 void SetDrdyIntFlag(u8 flag);
BeiZhang 0:71d5c1c75f0b 182
BeiZhang 0:71d5c1c75f0b 183 u8 GetDrdyIntFlag(void);
BeiZhang 0:71d5c1c75f0b 184
BeiZhang 0:71d5c1c75f0b 185 void DrdyCallBack(void);
BeiZhang 0:71d5c1c75f0b 186
BeiZhang 0:71d5c1c75f0b 187 void ProcessDrdyInt(void);
BeiZhang 0:71d5c1c75f0b 188
BeiZhang 0:71d5c1c75f0b 189 void DisplayCycleCount();
BeiZhang 0:71d5c1c75f0b 190
BeiZhang 0:71d5c1c75f0b 191 void DisplayREVIDReg();
BeiZhang 0:71d5c1c75f0b 192
BeiZhang 0:71d5c1c75f0b 193 void SelfTest();
BeiZhang 0:71d5c1c75f0b 194
BeiZhang 0:71d5c1c75f0b 195 //constructor
BeiZhang 0:71d5c1c75f0b 196 RM3100();
BeiZhang 0:71d5c1c75f0b 197
BeiZhang 0:71d5c1c75f0b 198 private:
BeiZhang 0:71d5c1c75f0b 199 u8 rm3100_service_flag;
BeiZhang 0:71d5c1c75f0b 200 int current_gain[3];
BeiZhang 0:71d5c1c75f0b 201 int current_ccount[3];
BeiZhang 0:71d5c1c75f0b 202 int sample_rate;
BeiZhang 0:71d5c1c75f0b 203 int prev_rate;
BeiZhang 0:71d5c1c75f0b 204
BeiZhang 0:71d5c1c75f0b 205 DigitalOut cs; //ssel
BeiZhang 0:71d5c1c75f0b 206 InterruptIn drdy; //Drdy pin D9
BeiZhang 0:71d5c1c75f0b 207
BeiZhang 0:71d5c1c75f0b 208 SPI spi;
BeiZhang 0:71d5c1c75f0b 209
BeiZhang 0:71d5c1c75f0b 210 };