KL25Z_SystemInit.c

00001 /*
00002 ** ###################################################################
00003 **     Processor:           MKL25Z128VLK4
00004 **     Compilers:           ARM Compiler
00005 **                          Freescale C/C++ for Embedded ARM
00006 **                          GNU C Compiler
00007 **                          IAR ANSI C/C++ Compiler for ARM
00008 **
00009 **     Reference manual:    KL25RM, Rev.1, Jun 2012
00010 **     Version:             rev. 1.1, 2012-06-21
00011 **
00012 **     Abstract:
00013 **         Provides a system configuration function and a global variable that
00014 **         contains the system frequency. It configures the device and initializes
00015 **         the oscillator (PLL) that is part of the microcontroller device.
00016 **
00017 **     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
00018 **
00019 **     http:                 www.freescale.com
00020 **     mail:                 support@freescale.com
00021 **
00022 **     Revisions:
00023 **     - rev. 1.0 (2012-06-13)
00024 **         Initial version.
00025 **     - rev. 1.1 (2012-06-21)
00026 **         Update according to reference manual rev. 1.
00027 **
00028 ** ###################################################################
00029 */
00030 
00031 /**
00032  * @file MKL25Z4
00033  * @version 1.1
00034  * @date 2012-06-21
00035  * @brief Device specific configuration file for MKL25Z4 (implementation file)
00036  *
00037  * Provides a system configuration function and a global variable that contains
00038  * the system frequency. It configures the device and initializes the oscillator
00039  * (PLL) that is part of the microcontroller device.
00040  */
00041 
00042 #include <stdint.h>
00043 #include "MKL25Z4.h"
00044 
00045 //MODIFICATION: We DO want watchdog, uC default after reset is enabled with timeout=1024ms (2^10*LPO=1KHz)
00046 //#define DISABLE_WDOG    1
00047 
00048 #define CLOCK_SETUP     1
00049 /* Predefined clock setups
00050    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
00051          Reference clock source for MCG module is the slow internal clock source 32.768kHz
00052          Core clock = 41.94MHz, BusClock = 13.98MHz
00053    1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
00054          Reference clock source for MCG module is an external crystal 8MHz
00055          Core clock = 48MHz, BusClock = 24MHz
00056    2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
00057          Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
00058          Core clock = 8MHz, BusClock = 8MHz
00059    3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
00060          Reference clock source for MCG module is an external crystal 32.768kHz
00061          Core clock = 47.97MHz, BusClock = 23.98MHz
00062          This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
00063          RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
00064          accuracy durring the reset period. RTC will reset on power down. 
00065 */
00066 
00067 /*----------------------------------------------------------------------------
00068   Define clock source values
00069  *----------------------------------------------------------------------------*/
00070 #if (CLOCK_SETUP == 0)
00071     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00072     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00073     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00074     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
00075 #elif (CLOCK_SETUP == 1)
00076     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00077     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00078     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00079     #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
00080 #elif (CLOCK_SETUP == 2)
00081     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00082     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00083     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00084     #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
00085 #elif (CLOCK_SETUP == 3)    
00086     #define CPU_XTAL_CLK_HZ                 32768u   /* Value of the external crystal or oscillator clock frequency in Hz */
00087     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00088     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00089     #define DEFAULT_SYSTEM_CLOCK            47972352u /* Default System clock value */       
00090 #endif /* (CLOCK_SETUP == 3) */
00091 
00092 /* ----------------------------------------------------------------------------
00093    -- Core clock
00094    ---------------------------------------------------------------------------- */
00095 
00096 //MODIFICATION: That vartiable already exists
00097 // uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
00098 
00099 /* ----------------------------------------------------------------------------
00100    -- SystemInit()
00101    ---------------------------------------------------------------------------- */
00102 
00103 void $Sub$$SystemInit (void) {
00104     
00105     //MODIFICATION:
00106     // That variable already exists, we set it here
00107     SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
00108     // We want visual indication of boot time with red LED on
00109     //TODO
00110 
00111 #if (DISABLE_WDOG)
00112   /* Disable the WDOG module */
00113   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
00114   SIM->COPC = (uint32_t)0x00u;
00115 #endif /* (DISABLE_WDOG) */
00116 #if (CLOCK_SETUP == 0)
00117   /* SIM->CLKDIV1: OUTDIV1=0 */
00118   SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
00119   /* Switch to FEI Mode */
00120   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
00121   MCG->C1 = (uint8_t)0x06U;
00122   /* MCG_C2: LOCRE0=0, =0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
00123   MCG->C2 = (uint8_t)0x00U;
00124   /* MCG->C4: DMX32=0,DRST_DRS=1 */
00125   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
00126   /* OSC0->CR: ERCLKEN=1,=0,EREFSTEN=0,=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00127   OSC0->CR = (uint8_t)0x80U;
00128   /* MCG->C5: =0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
00129   MCG->C5 = (uint8_t)0x00U;
00130   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00131   MCG->C6 = (uint8_t)0x00U;
00132   while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
00133   }
00134   while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
00135   }
00136 #elif (CLOCK_SETUP == 1)
00137   /* SIM->SCGC5: PORTA=1 */
00138   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
00139   /* SIM->CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
00140   SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
00141   /* PORTA->PCR18: ISF=0,MUX=0 */
00142   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
00143   /* PORTA->PCR19: ISF=0,MUX=0 */
00144   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
00145   /* Switch to FBE Mode */
00146   /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
00147   OSC0->CR = (uint8_t)0x89U;
00148   /* MCG->C2: LOCRE0=0, RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
00149   MCG->C2 = (uint8_t)0x24U;
00150   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00151   MCG->C1 = (uint8_t)0x9AU;
00152   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00153   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
00154   /* MCG->C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
00155   MCG->C5 = (uint8_t)0x01U;
00156   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00157   MCG->C6 = (uint8_t)0x00U;
00158   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
00159   }
00160   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00161   }
00162   /* Switch to PBE Mode */
00163   /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
00164   MCG->C6 = (uint8_t)0x40U;
00165   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00166   }
00167   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
00168   }
00169   /* Switch to PEE Mode */
00170   /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00171   MCG->C1 = (uint8_t)0x1AU;
00172   while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
00173   }
00174 #elif (CLOCK_SETUP == 2)
00175   /* SIM->SCGC5: PORTA=1 */
00176   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
00177   /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
00178   SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
00179   /* PORTA->PCR18: ISF=0,MUX=0 */
00180   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
00181   /* PORTA->PCR19: ISF=0,MUX=0 */
00182   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
00183   /* Switch to FBE Mode */
00184   /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
00185   OSC0->CR = (uint8_t)0x89U;
00186   /* MCG->C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
00187   MCG->C2 = (uint8_t)0x24U;
00188   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00189   MCG->C1 = (uint8_t)0x9AU;
00190   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00191   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
00192   /* MCG->C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
00193   MCG->C5 = (uint8_t)0x00U;
00194   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00195   MCG->C6 = (uint8_t)0x00U;
00196   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
00197   }
00198   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00199   }
00200   /* Switch to BLPE Mode */
00201   /* MCG->C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
00202   MCG->C2 = (uint8_t)0x26U;
00203   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00204   }
00205 #elif (CLOCK_SETUP == 3)  
00206 /* SIM->SCGC5: PORTA=1 */
00207   SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
00208   /* SIM->CLKDIV1: OUTDIV1=0, OUTDIV4=1 */
00209   SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
00210   /* PORTA->PCR[3]: ISF=0,MUX=0 */
00211   PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
00212   /* PORTA->PCR[4]: ISF=0,MUX=0 */
00213   PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
00214   /* Switch to FEE Mode */
00215   /* MCG->C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
00216   MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
00217   /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00218   OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
00219   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00220   MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
00221   /* MCG->C4: DMX32=1,DRST_DRS=1 */
00222   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
00223             MCG_C4_DRST_DRS(0x02)
00224            )) | (uint8_t)(
00225             MCG_C4_DMX32_MASK |
00226             MCG_C4_DRST_DRS(0x01)
00227            ));
00228   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
00229   }
00230   while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
00231   }          
00232 #endif /* (CLOCK_SETUP == 3) */
00233 }