Erik van de Coevering / quadV3

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quadv3/mbed/LPC1768/core_cmInstr.h@1:ac68f0368a77, 2013-07-23 (annotated)

Committer:
Anaesthetix
Date:
Tue Jul 23 14:01:42 2013 +0000
Revision:
1:ac68f0368a77
Parent:
0:978110f7f027 
Other accelerometer added

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anaesthetix 0:978110f7f027 1 /**************************************************************************//**
Anaesthetix 0:978110f7f027 2 * @file core_cmInstr.h
Anaesthetix 0:978110f7f027 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
Anaesthetix 0:978110f7f027 4 * @version V3.00
Anaesthetix 0:978110f7f027 5 * @date 09. December 2011
Anaesthetix 0:978110f7f027 6 *
Anaesthetix 0:978110f7f027 7 * @note
Anaesthetix 0:978110f7f027 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
Anaesthetix 0:978110f7f027 9 *
Anaesthetix 0:978110f7f027 10 * @par
Anaesthetix 0:978110f7f027 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Anaesthetix 0:978110f7f027 12 * processor based microcontrollers. This file can be freely distributed
Anaesthetix 0:978110f7f027 13 * within development tools that are supporting such ARM based processors.
Anaesthetix 0:978110f7f027 14 *
Anaesthetix 0:978110f7f027 15 * @par
Anaesthetix 0:978110f7f027 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Anaesthetix 0:978110f7f027 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Anaesthetix 0:978110f7f027 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Anaesthetix 0:978110f7f027 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Anaesthetix 0:978110f7f027 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Anaesthetix 0:978110f7f027 21 *
Anaesthetix 0:978110f7f027 22 ******************************************************************************/
Anaesthetix 0:978110f7f027 23
Anaesthetix 0:978110f7f027 24 #ifndef __CORE_CMINSTR_H
Anaesthetix 0:978110f7f027 25 #define __CORE_CMINSTR_H
Anaesthetix 0:978110f7f027 26
Anaesthetix 0:978110f7f027 27
Anaesthetix 0:978110f7f027 28 /* ########################## Core Instruction Access ######################### */
Anaesthetix 0:978110f7f027 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Anaesthetix 0:978110f7f027 30 Access to dedicated instructions
Anaesthetix 0:978110f7f027 31 @{
Anaesthetix 0:978110f7f027 32 */
Anaesthetix 0:978110f7f027 33
Anaesthetix 0:978110f7f027 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Anaesthetix 0:978110f7f027 35 /* ARM armcc specific functions */
Anaesthetix 0:978110f7f027 36
Anaesthetix 0:978110f7f027 37 #if (__ARMCC_VERSION < 400677)
Anaesthetix 0:978110f7f027 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Anaesthetix 0:978110f7f027 39 #endif
Anaesthetix 0:978110f7f027 40
Anaesthetix 0:978110f7f027 41
Anaesthetix 0:978110f7f027 42 /** \brief No Operation
Anaesthetix 0:978110f7f027 43
Anaesthetix 0:978110f7f027 44 No Operation does nothing. This instruction can be used for code alignment purposes.
Anaesthetix 0:978110f7f027 45 */
Anaesthetix 0:978110f7f027 46 #define __NOP __nop
Anaesthetix 0:978110f7f027 47
Anaesthetix 0:978110f7f027 48
Anaesthetix 0:978110f7f027 49 /** \brief Wait For Interrupt
Anaesthetix 0:978110f7f027 50
Anaesthetix 0:978110f7f027 51 Wait For Interrupt is a hint instruction that suspends execution
Anaesthetix 0:978110f7f027 52 until one of a number of events occurs.
Anaesthetix 0:978110f7f027 53 */
Anaesthetix 0:978110f7f027 54 #define __WFI __wfi
Anaesthetix 0:978110f7f027 55
Anaesthetix 0:978110f7f027 56
Anaesthetix 0:978110f7f027 57 /** \brief Wait For Event
Anaesthetix 0:978110f7f027 58
Anaesthetix 0:978110f7f027 59 Wait For Event is a hint instruction that permits the processor to enter
Anaesthetix 0:978110f7f027 60 a low-power state until one of a number of events occurs.
Anaesthetix 0:978110f7f027 61 */
Anaesthetix 0:978110f7f027 62 #define __WFE __wfe
Anaesthetix 0:978110f7f027 63
Anaesthetix 0:978110f7f027 64
Anaesthetix 0:978110f7f027 65 /** \brief Send Event
Anaesthetix 0:978110f7f027 66
Anaesthetix 0:978110f7f027 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
Anaesthetix 0:978110f7f027 68 */
Anaesthetix 0:978110f7f027 69 #define __SEV __sev
Anaesthetix 0:978110f7f027 70
Anaesthetix 0:978110f7f027 71
Anaesthetix 0:978110f7f027 72 /** \brief Instruction Synchronization Barrier
Anaesthetix 0:978110f7f027 73
Anaesthetix 0:978110f7f027 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
Anaesthetix 0:978110f7f027 75 so that all instructions following the ISB are fetched from cache or
Anaesthetix 0:978110f7f027 76 memory, after the instruction has been completed.
Anaesthetix 0:978110f7f027 77 */
Anaesthetix 0:978110f7f027 78 #define __ISB() __isb(0xF)
Anaesthetix 0:978110f7f027 79
Anaesthetix 0:978110f7f027 80
Anaesthetix 0:978110f7f027 81 /** \brief Data Synchronization Barrier
Anaesthetix 0:978110f7f027 82
Anaesthetix 0:978110f7f027 83 This function acts as a special kind of Data Memory Barrier.
Anaesthetix 0:978110f7f027 84 It completes when all explicit memory accesses before this instruction complete.
Anaesthetix 0:978110f7f027 85 */
Anaesthetix 0:978110f7f027 86 #define __DSB() __dsb(0xF)
Anaesthetix 0:978110f7f027 87
Anaesthetix 0:978110f7f027 88
Anaesthetix 0:978110f7f027 89 /** \brief Data Memory Barrier
Anaesthetix 0:978110f7f027 90
Anaesthetix 0:978110f7f027 91 This function ensures the apparent order of the explicit memory operations before
Anaesthetix 0:978110f7f027 92 and after the instruction, without ensuring their completion.
Anaesthetix 0:978110f7f027 93 */
Anaesthetix 0:978110f7f027 94 #define __DMB() __dmb(0xF)
Anaesthetix 0:978110f7f027 95
Anaesthetix 0:978110f7f027 96
Anaesthetix 0:978110f7f027 97 /** \brief Reverse byte order (32 bit)
Anaesthetix 0:978110f7f027 98
Anaesthetix 0:978110f7f027 99 This function reverses the byte order in integer value.
Anaesthetix 0:978110f7f027 100
Anaesthetix 0:978110f7f027 101 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 102 \return Reversed value
Anaesthetix 0:978110f7f027 103 */
Anaesthetix 0:978110f7f027 104 #define __REV __rev
Anaesthetix 0:978110f7f027 105
Anaesthetix 0:978110f7f027 106
Anaesthetix 0:978110f7f027 107 /** \brief Reverse byte order (16 bit)
Anaesthetix 0:978110f7f027 108
Anaesthetix 0:978110f7f027 109 This function reverses the byte order in two unsigned short values.
Anaesthetix 0:978110f7f027 110
Anaesthetix 0:978110f7f027 111 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 112 \return Reversed value
Anaesthetix 0:978110f7f027 113 */
Anaesthetix 0:978110f7f027 114 static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
Anaesthetix 0:978110f7f027 115 {
Anaesthetix 0:978110f7f027 116 rev16 r0, r0
Anaesthetix 0:978110f7f027 117 bx lr
Anaesthetix 0:978110f7f027 118 }
Anaesthetix 0:978110f7f027 119
Anaesthetix 0:978110f7f027 120
Anaesthetix 0:978110f7f027 121 /** \brief Reverse byte order in signed short value
Anaesthetix 0:978110f7f027 122
Anaesthetix 0:978110f7f027 123 This function reverses the byte order in a signed short value with sign extension to integer.
Anaesthetix 0:978110f7f027 124
Anaesthetix 0:978110f7f027 125 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 126 \return Reversed value
Anaesthetix 0:978110f7f027 127 */
Anaesthetix 0:978110f7f027 128 static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
Anaesthetix 0:978110f7f027 129 {
Anaesthetix 0:978110f7f027 130 revsh r0, r0
Anaesthetix 0:978110f7f027 131 bx lr
Anaesthetix 0:978110f7f027 132 }
Anaesthetix 0:978110f7f027 133
Anaesthetix 0:978110f7f027 134
Anaesthetix 0:978110f7f027 135 #if (__CORTEX_M >= 0x03)
Anaesthetix 0:978110f7f027 136
Anaesthetix 0:978110f7f027 137 /** \brief Reverse bit order of value
Anaesthetix 0:978110f7f027 138
Anaesthetix 0:978110f7f027 139 This function reverses the bit order of the given value.
Anaesthetix 0:978110f7f027 140
Anaesthetix 0:978110f7f027 141 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 142 \return Reversed value
Anaesthetix 0:978110f7f027 143 */
Anaesthetix 0:978110f7f027 144 #define __RBIT __rbit
Anaesthetix 0:978110f7f027 145
Anaesthetix 0:978110f7f027 146
Anaesthetix 0:978110f7f027 147 /** \brief LDR Exclusive (8 bit)
Anaesthetix 0:978110f7f027 148
Anaesthetix 0:978110f7f027 149 This function performs a exclusive LDR command for 8 bit value.
Anaesthetix 0:978110f7f027 150
Anaesthetix 0:978110f7f027 151 \param [in] ptr Pointer to data
Anaesthetix 0:978110f7f027 152 \return value of type uint8_t at (*ptr)
Anaesthetix 0:978110f7f027 153 */
Anaesthetix 0:978110f7f027 154 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
Anaesthetix 0:978110f7f027 155
Anaesthetix 0:978110f7f027 156
Anaesthetix 0:978110f7f027 157 /** \brief LDR Exclusive (16 bit)
Anaesthetix 0:978110f7f027 158
Anaesthetix 0:978110f7f027 159 This function performs a exclusive LDR command for 16 bit values.
Anaesthetix 0:978110f7f027 160
Anaesthetix 0:978110f7f027 161 \param [in] ptr Pointer to data
Anaesthetix 0:978110f7f027 162 \return value of type uint16_t at (*ptr)
Anaesthetix 0:978110f7f027 163 */
Anaesthetix 0:978110f7f027 164 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
Anaesthetix 0:978110f7f027 165
Anaesthetix 0:978110f7f027 166
Anaesthetix 0:978110f7f027 167 /** \brief LDR Exclusive (32 bit)
Anaesthetix 0:978110f7f027 168
Anaesthetix 0:978110f7f027 169 This function performs a exclusive LDR command for 32 bit values.
Anaesthetix 0:978110f7f027 170
Anaesthetix 0:978110f7f027 171 \param [in] ptr Pointer to data
Anaesthetix 0:978110f7f027 172 \return value of type uint32_t at (*ptr)
Anaesthetix 0:978110f7f027 173 */
Anaesthetix 0:978110f7f027 174 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
Anaesthetix 0:978110f7f027 175
Anaesthetix 0:978110f7f027 176
Anaesthetix 0:978110f7f027 177 /** \brief STR Exclusive (8 bit)
Anaesthetix 0:978110f7f027 178
Anaesthetix 0:978110f7f027 179 This function performs a exclusive STR command for 8 bit values.
Anaesthetix 0:978110f7f027 180
Anaesthetix 0:978110f7f027 181 \param [in] value Value to store
Anaesthetix 0:978110f7f027 182 \param [in] ptr Pointer to location
Anaesthetix 0:978110f7f027 183 \return 0 Function succeeded
Anaesthetix 0:978110f7f027 184 \return 1 Function failed
Anaesthetix 0:978110f7f027 185 */
Anaesthetix 0:978110f7f027 186 #define __STREXB(value, ptr) __strex(value, ptr)
Anaesthetix 0:978110f7f027 187
Anaesthetix 0:978110f7f027 188
Anaesthetix 0:978110f7f027 189 /** \brief STR Exclusive (16 bit)
Anaesthetix 0:978110f7f027 190
Anaesthetix 0:978110f7f027 191 This function performs a exclusive STR command for 16 bit values.
Anaesthetix 0:978110f7f027 192
Anaesthetix 0:978110f7f027 193 \param [in] value Value to store
Anaesthetix 0:978110f7f027 194 \param [in] ptr Pointer to location
Anaesthetix 0:978110f7f027 195 \return 0 Function succeeded
Anaesthetix 0:978110f7f027 196 \return 1 Function failed
Anaesthetix 0:978110f7f027 197 */
Anaesthetix 0:978110f7f027 198 #define __STREXH(value, ptr) __strex(value, ptr)
Anaesthetix 0:978110f7f027 199
Anaesthetix 0:978110f7f027 200
Anaesthetix 0:978110f7f027 201 /** \brief STR Exclusive (32 bit)
Anaesthetix 0:978110f7f027 202
Anaesthetix 0:978110f7f027 203 This function performs a exclusive STR command for 32 bit values.
Anaesthetix 0:978110f7f027 204
Anaesthetix 0:978110f7f027 205 \param [in] value Value to store
Anaesthetix 0:978110f7f027 206 \param [in] ptr Pointer to location
Anaesthetix 0:978110f7f027 207 \return 0 Function succeeded
Anaesthetix 0:978110f7f027 208 \return 1 Function failed
Anaesthetix 0:978110f7f027 209 */
Anaesthetix 0:978110f7f027 210 #define __STREXW(value, ptr) __strex(value, ptr)
Anaesthetix 0:978110f7f027 211
Anaesthetix 0:978110f7f027 212
Anaesthetix 0:978110f7f027 213 /** \brief Remove the exclusive lock
Anaesthetix 0:978110f7f027 214
Anaesthetix 0:978110f7f027 215 This function removes the exclusive lock which is created by LDREX.
Anaesthetix 0:978110f7f027 216
Anaesthetix 0:978110f7f027 217 */
Anaesthetix 0:978110f7f027 218 #define __CLREX __clrex
Anaesthetix 0:978110f7f027 219
Anaesthetix 0:978110f7f027 220
Anaesthetix 0:978110f7f027 221 /** \brief Signed Saturate
Anaesthetix 0:978110f7f027 222
Anaesthetix 0:978110f7f027 223 This function saturates a signed value.
Anaesthetix 0:978110f7f027 224
Anaesthetix 0:978110f7f027 225 \param [in] value Value to be saturated
Anaesthetix 0:978110f7f027 226 \param [in] sat Bit position to saturate to (1..32)
Anaesthetix 0:978110f7f027 227 \return Saturated value
Anaesthetix 0:978110f7f027 228 */
Anaesthetix 0:978110f7f027 229 #define __SSAT __ssat
Anaesthetix 0:978110f7f027 230
Anaesthetix 0:978110f7f027 231
Anaesthetix 0:978110f7f027 232 /** \brief Unsigned Saturate
Anaesthetix 0:978110f7f027 233
Anaesthetix 0:978110f7f027 234 This function saturates an unsigned value.
Anaesthetix 0:978110f7f027 235
Anaesthetix 0:978110f7f027 236 \param [in] value Value to be saturated
Anaesthetix 0:978110f7f027 237 \param [in] sat Bit position to saturate to (0..31)
Anaesthetix 0:978110f7f027 238 \return Saturated value
Anaesthetix 0:978110f7f027 239 */
Anaesthetix 0:978110f7f027 240 #define __USAT __usat
Anaesthetix 0:978110f7f027 241
Anaesthetix 0:978110f7f027 242
Anaesthetix 0:978110f7f027 243 /** \brief Count leading zeros
Anaesthetix 0:978110f7f027 244
Anaesthetix 0:978110f7f027 245 This function counts the number of leading zeros of a data value.
Anaesthetix 0:978110f7f027 246
Anaesthetix 0:978110f7f027 247 \param [in] value Value to count the leading zeros
Anaesthetix 0:978110f7f027 248 \return number of leading zeros in value
Anaesthetix 0:978110f7f027 249 */
Anaesthetix 0:978110f7f027 250 #define __CLZ __clz
Anaesthetix 0:978110f7f027 251
Anaesthetix 0:978110f7f027 252 #endif /* (__CORTEX_M >= 0x03) */
Anaesthetix 0:978110f7f027 253
Anaesthetix 0:978110f7f027 254
Anaesthetix 0:978110f7f027 255
Anaesthetix 0:978110f7f027 256 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Anaesthetix 0:978110f7f027 257 /* IAR iccarm specific functions */
Anaesthetix 0:978110f7f027 258
Anaesthetix 0:978110f7f027 259 #include <cmsis_iar.h>
Anaesthetix 0:978110f7f027 260
Anaesthetix 0:978110f7f027 261
Anaesthetix 0:978110f7f027 262 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
Anaesthetix 0:978110f7f027 263 /* GNU gcc specific functions */
Anaesthetix 0:978110f7f027 264
Anaesthetix 0:978110f7f027 265 /** \brief No Operation
Anaesthetix 0:978110f7f027 266
Anaesthetix 0:978110f7f027 267 No Operation does nothing. This instruction can be used for code alignment purposes.
Anaesthetix 0:978110f7f027 268 */
Anaesthetix 0:978110f7f027 269 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
Anaesthetix 0:978110f7f027 270 {
Anaesthetix 0:978110f7f027 271 __ASM volatile ("nop");
Anaesthetix 0:978110f7f027 272 }
Anaesthetix 0:978110f7f027 273
Anaesthetix 0:978110f7f027 274
Anaesthetix 0:978110f7f027 275 /** \brief Wait For Interrupt
Anaesthetix 0:978110f7f027 276
Anaesthetix 0:978110f7f027 277 Wait For Interrupt is a hint instruction that suspends execution
Anaesthetix 0:978110f7f027 278 until one of a number of events occurs.
Anaesthetix 0:978110f7f027 279 */
Anaesthetix 0:978110f7f027 280 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
Anaesthetix 0:978110f7f027 281 {
Anaesthetix 0:978110f7f027 282 __ASM volatile ("wfi");
Anaesthetix 0:978110f7f027 283 }
Anaesthetix 0:978110f7f027 284
Anaesthetix 0:978110f7f027 285
Anaesthetix 0:978110f7f027 286 /** \brief Wait For Event
Anaesthetix 0:978110f7f027 287
Anaesthetix 0:978110f7f027 288 Wait For Event is a hint instruction that permits the processor to enter
Anaesthetix 0:978110f7f027 289 a low-power state until one of a number of events occurs.
Anaesthetix 0:978110f7f027 290 */
Anaesthetix 0:978110f7f027 291 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
Anaesthetix 0:978110f7f027 292 {
Anaesthetix 0:978110f7f027 293 __ASM volatile ("wfe");
Anaesthetix 0:978110f7f027 294 }
Anaesthetix 0:978110f7f027 295
Anaesthetix 0:978110f7f027 296
Anaesthetix 0:978110f7f027 297 /** \brief Send Event
Anaesthetix 0:978110f7f027 298
Anaesthetix 0:978110f7f027 299 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
Anaesthetix 0:978110f7f027 300 */
Anaesthetix 0:978110f7f027 301 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
Anaesthetix 0:978110f7f027 302 {
Anaesthetix 0:978110f7f027 303 __ASM volatile ("sev");
Anaesthetix 0:978110f7f027 304 }
Anaesthetix 0:978110f7f027 305
Anaesthetix 0:978110f7f027 306
Anaesthetix 0:978110f7f027 307 /** \brief Instruction Synchronization Barrier
Anaesthetix 0:978110f7f027 308
Anaesthetix 0:978110f7f027 309 Instruction Synchronization Barrier flushes the pipeline in the processor,
Anaesthetix 0:978110f7f027 310 so that all instructions following the ISB are fetched from cache or
Anaesthetix 0:978110f7f027 311 memory, after the instruction has been completed.
Anaesthetix 0:978110f7f027 312 */
Anaesthetix 0:978110f7f027 313 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
Anaesthetix 0:978110f7f027 314 {
Anaesthetix 0:978110f7f027 315 __ASM volatile ("isb");
Anaesthetix 0:978110f7f027 316 }
Anaesthetix 0:978110f7f027 317
Anaesthetix 0:978110f7f027 318
Anaesthetix 0:978110f7f027 319 /** \brief Data Synchronization Barrier
Anaesthetix 0:978110f7f027 320
Anaesthetix 0:978110f7f027 321 This function acts as a special kind of Data Memory Barrier.
Anaesthetix 0:978110f7f027 322 It completes when all explicit memory accesses before this instruction complete.
Anaesthetix 0:978110f7f027 323 */
Anaesthetix 0:978110f7f027 324 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
Anaesthetix 0:978110f7f027 325 {
Anaesthetix 0:978110f7f027 326 __ASM volatile ("dsb");
Anaesthetix 0:978110f7f027 327 }
Anaesthetix 0:978110f7f027 328
Anaesthetix 0:978110f7f027 329
Anaesthetix 0:978110f7f027 330 /** \brief Data Memory Barrier
Anaesthetix 0:978110f7f027 331
Anaesthetix 0:978110f7f027 332 This function ensures the apparent order of the explicit memory operations before
Anaesthetix 0:978110f7f027 333 and after the instruction, without ensuring their completion.
Anaesthetix 0:978110f7f027 334 */
Anaesthetix 0:978110f7f027 335 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
Anaesthetix 0:978110f7f027 336 {
Anaesthetix 0:978110f7f027 337 __ASM volatile ("dmb");
Anaesthetix 0:978110f7f027 338 }
Anaesthetix 0:978110f7f027 339
Anaesthetix 0:978110f7f027 340
Anaesthetix 0:978110f7f027 341 /** \brief Reverse byte order (32 bit)
Anaesthetix 0:978110f7f027 342
Anaesthetix 0:978110f7f027 343 This function reverses the byte order in integer value.
Anaesthetix 0:978110f7f027 344
Anaesthetix 0:978110f7f027 345 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 346 \return Reversed value
Anaesthetix 0:978110f7f027 347 */
Anaesthetix 0:978110f7f027 348 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
Anaesthetix 0:978110f7f027 349 {
Anaesthetix 0:978110f7f027 350 uint32_t result;
Anaesthetix 0:978110f7f027 351
Anaesthetix 0:978110f7f027 352 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
Anaesthetix 0:978110f7f027 353 return(result);
Anaesthetix 0:978110f7f027 354 }
Anaesthetix 0:978110f7f027 355
Anaesthetix 0:978110f7f027 356
Anaesthetix 0:978110f7f027 357 /** \brief Reverse byte order (16 bit)
Anaesthetix 0:978110f7f027 358
Anaesthetix 0:978110f7f027 359 This function reverses the byte order in two unsigned short values.
Anaesthetix 0:978110f7f027 360
Anaesthetix 0:978110f7f027 361 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 362 \return Reversed value
Anaesthetix 0:978110f7f027 363 */
Anaesthetix 0:978110f7f027 364 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
Anaesthetix 0:978110f7f027 365 {
Anaesthetix 0:978110f7f027 366 uint32_t result;
Anaesthetix 0:978110f7f027 367
Anaesthetix 0:978110f7f027 368 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
Anaesthetix 0:978110f7f027 369 return(result);
Anaesthetix 0:978110f7f027 370 }
Anaesthetix 0:978110f7f027 371
Anaesthetix 0:978110f7f027 372
Anaesthetix 0:978110f7f027 373 /** \brief Reverse byte order in signed short value
Anaesthetix 0:978110f7f027 374
Anaesthetix 0:978110f7f027 375 This function reverses the byte order in a signed short value with sign extension to integer.
Anaesthetix 0:978110f7f027 376
Anaesthetix 0:978110f7f027 377 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 378 \return Reversed value
Anaesthetix 0:978110f7f027 379 */
Anaesthetix 0:978110f7f027 380 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
Anaesthetix 0:978110f7f027 381 {
Anaesthetix 0:978110f7f027 382 uint32_t result;
Anaesthetix 0:978110f7f027 383
Anaesthetix 0:978110f7f027 384 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
Anaesthetix 0:978110f7f027 385 return(result);
Anaesthetix 0:978110f7f027 386 }
Anaesthetix 0:978110f7f027 387
Anaesthetix 0:978110f7f027 388
Anaesthetix 0:978110f7f027 389 #if (__CORTEX_M >= 0x03)
Anaesthetix 0:978110f7f027 390
Anaesthetix 0:978110f7f027 391 /** \brief Reverse bit order of value
Anaesthetix 0:978110f7f027 392
Anaesthetix 0:978110f7f027 393 This function reverses the bit order of the given value.
Anaesthetix 0:978110f7f027 394
Anaesthetix 0:978110f7f027 395 \param [in] value Value to reverse
Anaesthetix 0:978110f7f027 396 \return Reversed value
Anaesthetix 0:978110f7f027 397 */
Anaesthetix 0:978110f7f027 398 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
Anaesthetix 0:978110f7f027 399 {
Anaesthetix 0:978110f7f027 400 uint32_t result;
Anaesthetix 0:978110f7f027 401
Anaesthetix 0:978110f7f027 402 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
Anaesthetix 0:978110f7f027 403 return(result);
Anaesthetix 0:978110f7f027 404 }
Anaesthetix 0:978110f7f027 405
Anaesthetix 0:978110f7f027 406
Anaesthetix 0:978110f7f027 407 /** \brief LDR Exclusive (8 bit)
Anaesthetix 0:978110f7f027 408
Anaesthetix 0:978110f7f027 409 This function performs a exclusive LDR command for 8 bit value.
Anaesthetix 0:978110f7f027 410
Anaesthetix 0:978110f7f027 411 \param [in] ptr Pointer to data
Anaesthetix 0:978110f7f027 412 \return value of type uint8_t at (*ptr)
Anaesthetix 0:978110f7f027 413 */
Anaesthetix 0:978110f7f027 414 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
Anaesthetix 0:978110f7f027 415 {
Anaesthetix 0:978110f7f027 416 uint8_t result;
Anaesthetix 0:978110f7f027 417
Anaesthetix 0:978110f7f027 418 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
Anaesthetix 0:978110f7f027 419 return(result);
Anaesthetix 0:978110f7f027 420 }
Anaesthetix 0:978110f7f027 421
Anaesthetix 0:978110f7f027 422
Anaesthetix 0:978110f7f027 423 /** \brief LDR Exclusive (16 bit)
Anaesthetix 0:978110f7f027 424
Anaesthetix 0:978110f7f027 425 This function performs a exclusive LDR command for 16 bit values.
Anaesthetix 0:978110f7f027 426
Anaesthetix 0:978110f7f027 427 \param [in] ptr Pointer to data
Anaesthetix 0:978110f7f027 428 \return value of type uint16_t at (*ptr)
Anaesthetix 0:978110f7f027 429 */
Anaesthetix 0:978110f7f027 430 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
Anaesthetix 0:978110f7f027 431 {
Anaesthetix 0:978110f7f027 432 uint16_t result;
Anaesthetix 0:978110f7f027 433
Anaesthetix 0:978110f7f027 434 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
Anaesthetix 0:978110f7f027 435 return(result);
Anaesthetix 0:978110f7f027 436 }
Anaesthetix 0:978110f7f027 437
Anaesthetix 0:978110f7f027 438
Anaesthetix 0:978110f7f027 439 /** \brief LDR Exclusive (32 bit)
Anaesthetix 0:978110f7f027 440
Anaesthetix 0:978110f7f027 441 This function performs a exclusive LDR command for 32 bit values.
Anaesthetix 0:978110f7f027 442
Anaesthetix 0:978110f7f027 443 \param [in] ptr Pointer to data
Anaesthetix 0:978110f7f027 444 \return value of type uint32_t at (*ptr)
Anaesthetix 0:978110f7f027 445 */
Anaesthetix 0:978110f7f027 446 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
Anaesthetix 0:978110f7f027 447 {
Anaesthetix 0:978110f7f027 448 uint32_t result;
Anaesthetix 0:978110f7f027 449
Anaesthetix 0:978110f7f027 450 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
Anaesthetix 0:978110f7f027 451 return(result);
Anaesthetix 0:978110f7f027 452 }
Anaesthetix 0:978110f7f027 453
Anaesthetix 0:978110f7f027 454
Anaesthetix 0:978110f7f027 455 /** \brief STR Exclusive (8 bit)
Anaesthetix 0:978110f7f027 456
Anaesthetix 0:978110f7f027 457 This function performs a exclusive STR command for 8 bit values.
Anaesthetix 0:978110f7f027 458
Anaesthetix 0:978110f7f027 459 \param [in] value Value to store
Anaesthetix 0:978110f7f027 460 \param [in] ptr Pointer to location
Anaesthetix 0:978110f7f027 461 \return 0 Function succeeded
Anaesthetix 0:978110f7f027 462 \return 1 Function failed
Anaesthetix 0:978110f7f027 463 */
Anaesthetix 0:978110f7f027 464 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
Anaesthetix 0:978110f7f027 465 {
Anaesthetix 0:978110f7f027 466 uint32_t result;
Anaesthetix 0:978110f7f027 467
Anaesthetix 0:978110f7f027 468 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
Anaesthetix 0:978110f7f027 469 return(result);
Anaesthetix 0:978110f7f027 470 }
Anaesthetix 0:978110f7f027 471
Anaesthetix 0:978110f7f027 472
Anaesthetix 0:978110f7f027 473 /** \brief STR Exclusive (16 bit)
Anaesthetix 0:978110f7f027 474
Anaesthetix 0:978110f7f027 475 This function performs a exclusive STR command for 16 bit values.
Anaesthetix 0:978110f7f027 476
Anaesthetix 0:978110f7f027 477 \param [in] value Value to store
Anaesthetix 0:978110f7f027 478 \param [in] ptr Pointer to location
Anaesthetix 0:978110f7f027 479 \return 0 Function succeeded
Anaesthetix 0:978110f7f027 480 \return 1 Function failed
Anaesthetix 0:978110f7f027 481 */
Anaesthetix 0:978110f7f027 482 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
Anaesthetix 0:978110f7f027 483 {
Anaesthetix 0:978110f7f027 484 uint32_t result;
Anaesthetix 0:978110f7f027 485
Anaesthetix 0:978110f7f027 486 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
Anaesthetix 0:978110f7f027 487 return(result);
Anaesthetix 0:978110f7f027 488 }
Anaesthetix 0:978110f7f027 489
Anaesthetix 0:978110f7f027 490
Anaesthetix 0:978110f7f027 491 /** \brief STR Exclusive (32 bit)
Anaesthetix 0:978110f7f027 492
Anaesthetix 0:978110f7f027 493 This function performs a exclusive STR command for 32 bit values.
Anaesthetix 0:978110f7f027 494
Anaesthetix 0:978110f7f027 495 \param [in] value Value to store
Anaesthetix 0:978110f7f027 496 \param [in] ptr Pointer to location
Anaesthetix 0:978110f7f027 497 \return 0 Function succeeded
Anaesthetix 0:978110f7f027 498 \return 1 Function failed
Anaesthetix 0:978110f7f027 499 */
Anaesthetix 0:978110f7f027 500 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
Anaesthetix 0:978110f7f027 501 {
Anaesthetix 0:978110f7f027 502 uint32_t result;
Anaesthetix 0:978110f7f027 503
Anaesthetix 0:978110f7f027 504 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
Anaesthetix 0:978110f7f027 505 return(result);
Anaesthetix 0:978110f7f027 506 }
Anaesthetix 0:978110f7f027 507
Anaesthetix 0:978110f7f027 508
Anaesthetix 0:978110f7f027 509 /** \brief Remove the exclusive lock
Anaesthetix 0:978110f7f027 510
Anaesthetix 0:978110f7f027 511 This function removes the exclusive lock which is created by LDREX.
Anaesthetix 0:978110f7f027 512
Anaesthetix 0:978110f7f027 513 */
Anaesthetix 0:978110f7f027 514 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
Anaesthetix 0:978110f7f027 515 {
Anaesthetix 0:978110f7f027 516 __ASM volatile ("clrex");
Anaesthetix 0:978110f7f027 517 }
Anaesthetix 0:978110f7f027 518
Anaesthetix 0:978110f7f027 519
Anaesthetix 0:978110f7f027 520 /** \brief Signed Saturate
Anaesthetix 0:978110f7f027 521
Anaesthetix 0:978110f7f027 522 This function saturates a signed value.
Anaesthetix 0:978110f7f027 523
Anaesthetix 0:978110f7f027 524 \param [in] value Value to be saturated
Anaesthetix 0:978110f7f027 525 \param [in] sat Bit position to saturate to (1..32)
Anaesthetix 0:978110f7f027 526 \return Saturated value
Anaesthetix 0:978110f7f027 527 */
Anaesthetix 0:978110f7f027 528 #define __SSAT(ARG1,ARG2) \
Anaesthetix 0:978110f7f027 529 ({ \
Anaesthetix 0:978110f7f027 530 uint32_t __RES, __ARG1 = (ARG1); \
Anaesthetix 0:978110f7f027 531 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Anaesthetix 0:978110f7f027 532 __RES; \
Anaesthetix 0:978110f7f027 533 })
Anaesthetix 0:978110f7f027 534
Anaesthetix 0:978110f7f027 535
Anaesthetix 0:978110f7f027 536 /** \brief Unsigned Saturate
Anaesthetix 0:978110f7f027 537
Anaesthetix 0:978110f7f027 538 This function saturates an unsigned value.
Anaesthetix 0:978110f7f027 539
Anaesthetix 0:978110f7f027 540 \param [in] value Value to be saturated
Anaesthetix 0:978110f7f027 541 \param [in] sat Bit position to saturate to (0..31)
Anaesthetix 0:978110f7f027 542 \return Saturated value
Anaesthetix 0:978110f7f027 543 */
Anaesthetix 0:978110f7f027 544 #define __USAT(ARG1,ARG2) \
Anaesthetix 0:978110f7f027 545 ({ \
Anaesthetix 0:978110f7f027 546 uint32_t __RES, __ARG1 = (ARG1); \
Anaesthetix 0:978110f7f027 547 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Anaesthetix 0:978110f7f027 548 __RES; \
Anaesthetix 0:978110f7f027 549 })
Anaesthetix 0:978110f7f027 550
Anaesthetix 0:978110f7f027 551
Anaesthetix 0:978110f7f027 552 /** \brief Count leading zeros
Anaesthetix 0:978110f7f027 553
Anaesthetix 0:978110f7f027 554 This function counts the number of leading zeros of a data value.
Anaesthetix 0:978110f7f027 555
Anaesthetix 0:978110f7f027 556 \param [in] value Value to count the leading zeros
Anaesthetix 0:978110f7f027 557 \return number of leading zeros in value
Anaesthetix 0:978110f7f027 558 */
Anaesthetix 0:978110f7f027 559 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
Anaesthetix 0:978110f7f027 560 {
Anaesthetix 0:978110f7f027 561 uint8_t result;
Anaesthetix 0:978110f7f027 562
Anaesthetix 0:978110f7f027 563 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
Anaesthetix 0:978110f7f027 564 return(result);
Anaesthetix 0:978110f7f027 565 }
Anaesthetix 0:978110f7f027 566
Anaesthetix 0:978110f7f027 567 #endif /* (__CORTEX_M >= 0x03) */
Anaesthetix 0:978110f7f027 568
Anaesthetix 0:978110f7f027 569
Anaesthetix 0:978110f7f027 570
Anaesthetix 0:978110f7f027 571
Anaesthetix 0:978110f7f027 572 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
Anaesthetix 0:978110f7f027 573 /* TASKING carm specific functions */
Anaesthetix 0:978110f7f027 574
Anaesthetix 0:978110f7f027 575 /*
Anaesthetix 0:978110f7f027 576 * The CMSIS functions have been implemented as intrinsics in the compiler.
Anaesthetix 0:978110f7f027 577 * Please use "carm -?i" to get an up to date list of all intrinsics,
Anaesthetix 0:978110f7f027 578 * Including the CMSIS ones.
Anaesthetix 0:978110f7f027 579 */
Anaesthetix 0:978110f7f027 580
Anaesthetix 0:978110f7f027 581 #endif
Anaesthetix 0:978110f7f027 582
Anaesthetix 0:978110f7f027 583 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
Anaesthetix 0:978110f7f027 584
Anaesthetix 0:978110f7f027 585 #endif /* __CORE_CMINSTR_H */