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Fork of WIZnetInterface by WIZnet

Files at this revision

API Documentation at this revision

Revision 14:2101ab5ee40f, committed 2015-06-17

Comitter:
embeddist
Date:
Wed Jun 17 00:24:45 2015 +0000
Parent:
13:ec1c34e9ec45
Child:
15:24a9f2df2145
Commit message:
- arch/int/W5500.c - fixed reset() for WIZ550io; - tested arch/in/W5500 on LPC824 / NUCLEOF103RB / FRDM-KL25Z

Changed in this revision

arch/ext/W5500.cpp Show annotated file Show diff for this revision Revisions of this file
arch/ext/W5500.h Show annotated file Show diff for this revision Revisions of this file
arch/int/W7500x_toe.cpp Show annotated file Show diff for this revision Revisions of this file
arch/int/W7500x_toe.h Show annotated file Show diff for this revision Revisions of this file 
--- a/arch/ext/W5500.cpp	Tue Jun 16 13:03:28 2015 +0900
+++ b/arch/ext/W5500.cpp	Wed Jun 17 00:24:45 2015 +0000
@@ -155,23 +155,19 @@
 void WIZnet_Chip::reset()
 {
 #if defined(USE_WIZ550IO_MAC)
+    //read the MAC address inside the module	
+    reg_rd_mac(SHAR, mac); 
+#endif
 	// hw reset
     reset_pin = 1;
     reset_pin = 0;
     wait_us(500); // 500us (w5500)
     reset_pin = 1;
     wait_ms(400); // 400ms (w5500)
-
-    reg_rd_mac(SHAR, mac); // read the MAC address inside the modulea
-#else
-	// hw reset
-	reg_wr(MR, 0x80);
-	 wait_us(500); // 500us (w5500) 
-#endif
-
+#if defined(USE_WIZ550IO_MAC)
 	// write MAC address inside the WZTOE MAC address register
     reg_wr_mac(SHAR, mac);
-
+#endif
     // set RX and TX buffer size
 #if 0
     for (int socket = 0; socket < MAX_SOCK_NUM; socket++) {
@@ -378,7 +374,7 @@
     }
     cs = 1;
 
-#if DBG_SPI
+#if DBG_SPI 
     debug("[SPI]W %04x(%02x %d)", addr, cb, len);
     for(int i = 0; i < len; i++) {
         debug(" %02x", buf[i]);
@@ -471,23 +467,54 @@
     debug("\n");
 }
 
-int ethernet_link(void) {
-
-	return ((uint8_t)(WIZnet_Chip::getPHYCFGR())& 0x01);
+int WIZnet_Chip::ethernet_link(void) {
+	int val = getPHYCFGR();
+	return (val&0x01);
 }
 
-void ethernet_set_link(int speed, int duplex) {
+void WIZnet_Chip::ethernet_set_link(int speed, int duplex) {
 	uint32_t val=0;
 	if((speed < 0) || (speed > 1)) {
 		val = (PHYCFGR_OPMDC_ALLA)<<3; 
 	} else {
 		val = (((speed&0x01)<<1)+ (duplex&0x01))<<3; 
 	}
-	WIZnet_Chip::setPHYCFGR((uint8_t)(PHYCFGR_RST&(PHYCFGR_OPMD|val)));
+	setPHYCFGR((uint8_t)(PHYCFGR_RST&(PHYCFGR_OPMD|val)));
 	wait(0.2);
-	WIZnet_Chip::setPHYCFGR((uint8_t)((~PHYCFGR_RST)|(PHYCFGR_OPMD|val)));
+	setPHYCFGR((uint8_t)((~PHYCFGR_RST)|(PHYCFGR_OPMD|val)));
 	wait(0.2);
 }
 
+    void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data) {
+        spi_read(addr, 0x00, data, 6);
+    }
+
+    void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip) {
+        uint8_t buf[4];
+        char* p = (char*)ip;
+        for(int i = 0; i < 4; i++) {
+            buf[i] = atoi(p);
+            p = strchr(p, '.');
+            if (p == NULL) {
+                break;
+            }
+            p++;
+        }
+        spi_write(addr, cb, buf, sizeof(buf));
+    }
+    
+    void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {
+        reg_wr_ip(addr, (0x0C + (socket << 5)), ip);
+    }
+    
+    void WIZnet_Chip::reg_rd_ip_byte(uint16_t addr, uint8_t* data) {
+        spi_read(addr, 0x00, data, 4);
+    }
+    
+    void WIZnet_Chip::reg_wr_ip_byte(uint16_t addr, uint8_t* data) {
+        spi_write(addr, 0x04, data, 4);
+    }
+
+
 #endif
 

--- a/arch/ext/W5500.h	Tue Jun 16 13:03:28 2015 +0900
+++ b/arch/ext/W5500.h	Wed Jun 17 00:24:45 2015 +0000
@@ -151,7 +151,6 @@
 	HalfDuplex100 = 3,
 	FullDuplex100 = 4,
 };
-
 class WIZnet_Chip {
 public:
 enum Protocol {
@@ -350,11 +349,13 @@
         return *reinterpret_cast<T*>(buf);
     }
 
-    void reg_rd_mac(uint16_t addr, uint8_t* data) {
+    void reg_rd_mac(uint16_t addr, uint8_t* data);
+/*     {
         spi_read(addr, 0x00, data, 6);
-    }
+    }*/
 
-    void reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip) {
+    void reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip);
+    /* {
         uint8_t buf[4];
         char* p = (char*)ip;
         for(int i = 0; i < 4; i++) {
@@ -367,18 +368,21 @@
         }
         spi_write(addr, cb, buf, sizeof(buf));
     }
-    
-    void sreg_ip(int socket, uint16_t addr, const char* ip) {
+    */
+    void sreg_ip(int socket, uint16_t addr, const char* ip);
+/*     {
         reg_wr_ip(addr, (0x0C + (socket << 5)), ip);
-    }
+    }*/
     
-    void reg_rd_ip_byte(uint16_t addr, uint8_t* data) {
+    void reg_rd_ip_byte(uint16_t addr, uint8_t* data);
+/*     {
         spi_read(addr, 0x00, data, 4);
-    }
+    }*/
     
-    void reg_wr_ip_byte(uint16_t addr, uint8_t* data) {
+    void reg_wr_ip_byte(uint16_t addr, uint8_t* data);
+/*     {
         spi_write(addr, 0x04, data, 4);
-    }
+    }*/
        
 /////////////////////////////////
 // Common Register I/O function //
@@ -623,7 +627,7 @@
  * @return uint8_t. Value of @ref PHYCFGR register.
  * @sa getPHYCFGR()
  */
-    uint8_t getPHYCFGR() {
+     uint8_t getPHYCFGR() {
         return reg_rd<uint8_t>(PHYCFGR);
     }
 
@@ -978,6 +982,8 @@
     }
 
 
+	int ethernet_link(void);
+	void ethernet_set_link(int speed, int duplex);
 protected:
     uint8_t mac[6];
     uint32_t ip;
@@ -986,22 +992,19 @@
     uint32_t dnsaddr;
     bool dhcp;
     
-    
-
+    void spi_write(uint16_t addr, uint8_t cb, const uint8_t *buf, uint16_t len);
+    void spi_read(uint16_t addr, uint8_t cb, uint8_t *buf, uint16_t len);
+    SPI* spi;
+    DigitalOut cs;
+    DigitalOut reset_pin;
     static WIZnet_Chip* inst;
 
     void reg_wr_mac(uint16_t addr, uint8_t* data) {
         spi_write(addr, 0x04, data, 6);
     }
 
-    void spi_write(uint16_t addr, uint8_t cb, const uint8_t *buf, uint16_t len);
-    void spi_read(uint16_t addr, uint8_t cb, uint8_t *buf, uint16_t len);
-    SPI* spi;
-    DigitalOut cs;
-    DigitalOut reset_pin;
 };
-extern int ethernet_link(void);
-extern void ethernet_set_link(int speed, int duplex);
+
 
 extern uint32_t str_to_ip(const char* str);
 extern void printfBytes(char* str, uint8_t* buf, int len);

--- a/arch/int/W7500x_toe.cpp	Tue Jun 16 13:03:28 2015 +0900
+++ b/arch/int/W7500x_toe.cpp	Wed Jun 17 00:24:45 2015 +0000
@@ -481,11 +481,11 @@
 	idle_MDIO(GPIOx);
 }
 
-int ethernet_link(void) {
+int WIZnet_Chip::ethernet_link(void) {
 	return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01); 
 }
 
-void ethernet_set_link(int speed, int duplex) {
+void WIZnet_Chip::ethernet_set_link(int speed, int duplex) {
 	uint32_t val=0;
 	if((speed < 0) || (speed > 1)) {
 		val = CNTL_AUTONEGO; 
@@ -494,5 +494,37 @@
 	}
 	mdio_write(GPIO_MDC, PHYREG_CONTROL, val);
 }
+
+   void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data) 
+   {
+       	data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));
+       	data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));
+       	data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));
+       	data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));
+       	data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));
+       	data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));
+    }
+
+    void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip)
+    {
+        uint8_t buf[4]={0,};
+		uint32_t wr_ip = 0;
+        char* p = (char*)ip;
+        
+        for(int i = 0; i < 4; i++) {
+            wr_ip = (wr_ip<<8);
+            buf[i] = atoi(p);
+            wr_ip |= buf[i];
+            p = strchr(p, '.');
+            if (p == NULL) break;
+            p++;
+        }
+       	*(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;
+    }
+
+    void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {
+        reg_wr_ip(addr,  (uint8_t)(0x01+(socket<<2)), ip);
+    }
+
 #endif
 

--- a/arch/int/W7500x_toe.h	Tue Jun 16 13:03:28 2015 +0900
+++ b/arch/int/W7500x_toe.h	Wed Jun 17 00:24:45 2015 +0000
@@ -249,7 +249,7 @@
 
     template<typename T>
     T reg_rd(uint16_t addr, uint8_t cb) {
-        uint8_t buf[sizeof(T)];
+        uint8_t buf[sizeof(T)] = {0,};
         for(int i = 0; i < sizeof(buf); i++) { //  Little Endian to Big Endian
         	buf[i] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)+i);
 		}
@@ -263,33 +263,16 @@
         return *reinterpret_cast<T*>(buf);
     }
 
-    void reg_rd_mac(uint16_t addr, uint8_t* data) {
-       	data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));
-       	data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));
-       	data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));
-       	data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));
-       	data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));
-       	data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));
-    }
+    void reg_rd_mac(uint16_t addr, uint8_t* data);
+    
+    void reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip);
 
-    void reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip) {
-        uint8_t buf[4];
-		uint32_t wr_ip = 0;
-        char* p = (char*)ip;
-        for(int i = 0; i < 4; i++) {
-            wr_ip = (wr_ip<<8);
-            buf[i] = atoi(p);
-            wr_ip |= buf[i];
-            p = strchr(p, '.');
-            if (p == NULL) break;
-            p++;
-        }
-       	*(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;
-    }
+    void sreg_ip(int socket, uint16_t addr, const char* ip);
 
-    void sreg_ip(int socket, uint16_t addr, const char* ip) {
-        reg_wr_ip(addr,  (uint8_t)(0x01+(socket<<2)), ip);
-    }
+	int ethernet_link(void);
+	
+	void ethernet_set_link(int speed, int duplex);
+
 
 protected:
     uint8_t mac[6];
@@ -310,8 +293,6 @@
        	*(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6)) = data[5] ;
     }
 };
-extern int ethernet_link(void);
-extern void ethernet_set_link(int speed, int duplex);
 
 extern uint32_t str_to_ip(const char* str);
 extern void printfBytes(char* str, uint8_t* buf, int len);