xLAB - acutators / led-mrf-osc-legacy-code

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependencies:   mbed

led-mrf-osc/mbed-rtos/rtx/HAL_CM.c@0:95aa779116f0, 2015-03-21 (annotated)

Committer:
Jing_Qiu
Date:
Sat Mar 21 02:54:25 2015 +0000
Revision:
0:95aa779116f0
ese519

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jing_Qiu 0:95aa779116f0 1 /*----------------------------------------------------------------------------
Jing_Qiu 0:95aa779116f0 2 * RL-ARM - RTX
Jing_Qiu 0:95aa779116f0 3 *----------------------------------------------------------------------------
Jing_Qiu 0:95aa779116f0 4 * Name: HAL_CM.C
Jing_Qiu 0:95aa779116f0 5 * Purpose: Hardware Abstraction Layer for Cortex-M
Jing_Qiu 0:95aa779116f0 6 * Rev.: V4.60
Jing_Qiu 0:95aa779116f0 7 *----------------------------------------------------------------------------
Jing_Qiu 0:95aa779116f0 8 *
Jing_Qiu 0:95aa779116f0 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
Jing_Qiu 0:95aa779116f0 10 * All rights reserved.
Jing_Qiu 0:95aa779116f0 11 * Redistribution and use in source and binary forms, with or without
Jing_Qiu 0:95aa779116f0 12 * modification, are permitted provided that the following conditions are met:
Jing_Qiu 0:95aa779116f0 13 * - Redistributions of source code must retain the above copyright
Jing_Qiu 0:95aa779116f0 14 * notice, this list of conditions and the following disclaimer.
Jing_Qiu 0:95aa779116f0 15 * - Redistributions in binary form must reproduce the above copyright
Jing_Qiu 0:95aa779116f0 16 * notice, this list of conditions and the following disclaimer in the
Jing_Qiu 0:95aa779116f0 17 * documentation and/or other materials provided with the distribution.
Jing_Qiu 0:95aa779116f0 18 * - Neither the name of ARM nor the names of its contributors may be used
Jing_Qiu 0:95aa779116f0 19 * to endorse or promote products derived from this software without
Jing_Qiu 0:95aa779116f0 20 * specific prior written permission.
Jing_Qiu 0:95aa779116f0 21 *
Jing_Qiu 0:95aa779116f0 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Jing_Qiu 0:95aa779116f0 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Jing_Qiu 0:95aa779116f0 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Jing_Qiu 0:95aa779116f0 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Jing_Qiu 0:95aa779116f0 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Jing_Qiu 0:95aa779116f0 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Jing_Qiu 0:95aa779116f0 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Jing_Qiu 0:95aa779116f0 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Jing_Qiu 0:95aa779116f0 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Jing_Qiu 0:95aa779116f0 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Jing_Qiu 0:95aa779116f0 32 * POSSIBILITY OF SUCH DAMAGE.
Jing_Qiu 0:95aa779116f0 33 *---------------------------------------------------------------------------*/
Jing_Qiu 0:95aa779116f0 34
Jing_Qiu 0:95aa779116f0 35 #include "rt_TypeDef.h"
Jing_Qiu 0:95aa779116f0 36 #include "RTX_Conf.h"
Jing_Qiu 0:95aa779116f0 37 #include "rt_HAL_CM.h"
Jing_Qiu 0:95aa779116f0 38
Jing_Qiu 0:95aa779116f0 39
Jing_Qiu 0:95aa779116f0 40 /*----------------------------------------------------------------------------
Jing_Qiu 0:95aa779116f0 41 * Global Variables
Jing_Qiu 0:95aa779116f0 42 *---------------------------------------------------------------------------*/
Jing_Qiu 0:95aa779116f0 43
Jing_Qiu 0:95aa779116f0 44 #ifdef DBG_MSG
Jing_Qiu 0:95aa779116f0 45 BIT dbg_msg;
Jing_Qiu 0:95aa779116f0 46 #endif
Jing_Qiu 0:95aa779116f0 47
Jing_Qiu 0:95aa779116f0 48 /*----------------------------------------------------------------------------
Jing_Qiu 0:95aa779116f0 49 * Functions
Jing_Qiu 0:95aa779116f0 50 *---------------------------------------------------------------------------*/
Jing_Qiu 0:95aa779116f0 51
Jing_Qiu 0:95aa779116f0 52
Jing_Qiu 0:95aa779116f0 53 /*--------------------------- rt_init_stack ---------------------------------*/
Jing_Qiu 0:95aa779116f0 54
Jing_Qiu 0:95aa779116f0 55 void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
Jing_Qiu 0:95aa779116f0 56 /* Prepare TCB and saved context for a first time start of a task. */
Jing_Qiu 0:95aa779116f0 57 U32 *stk,i,size;
Jing_Qiu 0:95aa779116f0 58
Jing_Qiu 0:95aa779116f0 59 /* Prepare a complete interrupt frame for first task start */
Jing_Qiu 0:95aa779116f0 60 size = p_TCB->priv_stack >> 2;
Jing_Qiu 0:95aa779116f0 61
Jing_Qiu 0:95aa779116f0 62 /* Write to the top of stack. */
Jing_Qiu 0:95aa779116f0 63 stk = &p_TCB->stack[size];
Jing_Qiu 0:95aa779116f0 64
Jing_Qiu 0:95aa779116f0 65 /* Auto correct to 8-byte ARM stack alignment. */
Jing_Qiu 0:95aa779116f0 66 if ((U32)stk & 0x04) {
Jing_Qiu 0:95aa779116f0 67 stk--;
Jing_Qiu 0:95aa779116f0 68 }
Jing_Qiu 0:95aa779116f0 69
Jing_Qiu 0:95aa779116f0 70 stk -= 16;
Jing_Qiu 0:95aa779116f0 71
Jing_Qiu 0:95aa779116f0 72 /* Default xPSR and initial PC */
Jing_Qiu 0:95aa779116f0 73 stk[15] = INITIAL_xPSR;
Jing_Qiu 0:95aa779116f0 74 stk[14] = (U32)task_body;
Jing_Qiu 0:95aa779116f0 75
Jing_Qiu 0:95aa779116f0 76 /* Clear R4-R11,R0-R3,R12,LR registers. */
Jing_Qiu 0:95aa779116f0 77 for (i = 0; i < 14; i++) {
Jing_Qiu 0:95aa779116f0 78 stk[i] = 0;
Jing_Qiu 0:95aa779116f0 79 }
Jing_Qiu 0:95aa779116f0 80
Jing_Qiu 0:95aa779116f0 81 /* Assign a void pointer to R0. */
Jing_Qiu 0:95aa779116f0 82 stk[8] = (U32)p_TCB->msg;
Jing_Qiu 0:95aa779116f0 83
Jing_Qiu 0:95aa779116f0 84 /* Initial Task stack pointer. */
Jing_Qiu 0:95aa779116f0 85 p_TCB->tsk_stack = (U32)stk;
Jing_Qiu 0:95aa779116f0 86
Jing_Qiu 0:95aa779116f0 87 /* Task entry point. */
Jing_Qiu 0:95aa779116f0 88 p_TCB->ptask = task_body;
Jing_Qiu 0:95aa779116f0 89
Jing_Qiu 0:95aa779116f0 90 /* Set a magic word for checking of stack overflow.
Jing_Qiu 0:95aa779116f0 91 For the main thread (ID: 0x01) the stack is in a memory area shared with the
Jing_Qiu 0:95aa779116f0 92 heap, therefore the last word of the stack is a moving target.
Jing_Qiu 0:95aa779116f0 93 We want to do stack/heap collision detection instead.
Jing_Qiu 0:95aa779116f0 94 */
Jing_Qiu 0:95aa779116f0 95 if (p_TCB->task_id != 0x01)
Jing_Qiu 0:95aa779116f0 96 p_TCB->stack[0] = MAGIC_WORD;
Jing_Qiu 0:95aa779116f0 97 }
Jing_Qiu 0:95aa779116f0 98
Jing_Qiu 0:95aa779116f0 99
Jing_Qiu 0:95aa779116f0 100 /*--------------------------- rt_ret_val ----------------------------------*/
Jing_Qiu 0:95aa779116f0 101
Jing_Qiu 0:95aa779116f0 102 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
Jing_Qiu 0:95aa779116f0 103 /* Get pointer to task return value registers (R0..R3) in Stack */
Jing_Qiu 0:95aa779116f0 104 #if (__TARGET_FPU_VFP)
Jing_Qiu 0:95aa779116f0 105 if (p_TCB->stack_frame) {
Jing_Qiu 0:95aa779116f0 106 /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */
Jing_Qiu 0:95aa779116f0 107 return (U32 *)(p_TCB->tsk_stack + 8*4 + 16*4);
Jing_Qiu 0:95aa779116f0 108 } else {
Jing_Qiu 0:95aa779116f0 109 /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
Jing_Qiu 0:95aa779116f0 110 return (U32 *)(p_TCB->tsk_stack + 8*4);
Jing_Qiu 0:95aa779116f0 111 }
Jing_Qiu 0:95aa779116f0 112 #else
Jing_Qiu 0:95aa779116f0 113 /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
Jing_Qiu 0:95aa779116f0 114 return (U32 *)(p_TCB->tsk_stack + 8*4);
Jing_Qiu 0:95aa779116f0 115 #endif
Jing_Qiu 0:95aa779116f0 116 }
Jing_Qiu 0:95aa779116f0 117
Jing_Qiu 0:95aa779116f0 118 void rt_ret_val (P_TCB p_TCB, U32 v0) {
Jing_Qiu 0:95aa779116f0 119 U32 *ret;
Jing_Qiu 0:95aa779116f0 120
Jing_Qiu 0:95aa779116f0 121 ret = rt_ret_regs(p_TCB);
Jing_Qiu 0:95aa779116f0 122 ret[0] = v0;
Jing_Qiu 0:95aa779116f0 123 }
Jing_Qiu 0:95aa779116f0 124
Jing_Qiu 0:95aa779116f0 125 void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
Jing_Qiu 0:95aa779116f0 126 U32 *ret;
Jing_Qiu 0:95aa779116f0 127
Jing_Qiu 0:95aa779116f0 128 ret = rt_ret_regs(p_TCB);
Jing_Qiu 0:95aa779116f0 129 ret[0] = v0;
Jing_Qiu 0:95aa779116f0 130 ret[1] = v1;
Jing_Qiu 0:95aa779116f0 131 }
Jing_Qiu 0:95aa779116f0 132
Jing_Qiu 0:95aa779116f0 133
Jing_Qiu 0:95aa779116f0 134 /*--------------------------- dbg_init --------------------------------------*/
Jing_Qiu 0:95aa779116f0 135
Jing_Qiu 0:95aa779116f0 136 #ifdef DBG_MSG
Jing_Qiu 0:95aa779116f0 137 void dbg_init (void) {
Jing_Qiu 0:95aa779116f0 138 if ((DEMCR & DEMCR_TRCENA) &&
Jing_Qiu 0:95aa779116f0 139 (ITM_CONTROL & ITM_ITMENA) &&
Jing_Qiu 0:95aa779116f0 140 (ITM_ENABLE & (1UL << 31))) {
Jing_Qiu 0:95aa779116f0 141 dbg_msg = __TRUE;
Jing_Qiu 0:95aa779116f0 142 }
Jing_Qiu 0:95aa779116f0 143 }
Jing_Qiu 0:95aa779116f0 144 #endif
Jing_Qiu 0:95aa779116f0 145
Jing_Qiu 0:95aa779116f0 146 /*--------------------------- dbg_task_notify -------------------------------*/
Jing_Qiu 0:95aa779116f0 147
Jing_Qiu 0:95aa779116f0 148 #ifdef DBG_MSG
Jing_Qiu 0:95aa779116f0 149 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
Jing_Qiu 0:95aa779116f0 150 while (ITM_PORT31_U32 == 0);
Jing_Qiu 0:95aa779116f0 151 ITM_PORT31_U32 = (U32)p_tcb->ptask;
Jing_Qiu 0:95aa779116f0 152 while (ITM_PORT31_U32 == 0);
Jing_Qiu 0:95aa779116f0 153 ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
Jing_Qiu 0:95aa779116f0 154 }
Jing_Qiu 0:95aa779116f0 155 #endif
Jing_Qiu 0:95aa779116f0 156
Jing_Qiu 0:95aa779116f0 157 /*--------------------------- dbg_task_switch -------------------------------*/
Jing_Qiu 0:95aa779116f0 158
Jing_Qiu 0:95aa779116f0 159 #ifdef DBG_MSG
Jing_Qiu 0:95aa779116f0 160 void dbg_task_switch (U32 task_id) {
Jing_Qiu 0:95aa779116f0 161 while (ITM_PORT31_U32 == 0);
Jing_Qiu 0:95aa779116f0 162 ITM_PORT31_U8 = task_id;
Jing_Qiu 0:95aa779116f0 163 }
Jing_Qiu 0:95aa779116f0 164 #endif
Jing_Qiu 0:95aa779116f0 165
Jing_Qiu 0:95aa779116f0 166
Jing_Qiu 0:95aa779116f0 167 /*----------------------------------------------------------------------------
Jing_Qiu 0:95aa779116f0 168 * end of file
Jing_Qiu 0:95aa779116f0 169 *---------------------------------------------------------------------------*/
Jing_Qiu 0:95aa779116f0 170