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targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_IAR/startup_VKRZA1H.s@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
119:3921aeca8633 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 119:3921aeca8633 1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mbed_official 119:3921aeca8633 2 ;;
mbed_official 119:3921aeca8633 3 ;; Part one of the system initialization code,
mbed_official 119:3921aeca8633 4 ;; contains low-level
mbed_official 119:3921aeca8633 5 ;; initialization.
mbed_official 119:3921aeca8633 6 ;;
mbed_official 119:3921aeca8633 7 ;; Copyright 2007 IAR Systems. All rights reserved.
mbed_official 119:3921aeca8633 8 ;;
mbed_official 119:3921aeca8633 9 ;; $Revision: 49919 $
mbed_official 119:3921aeca8633 10 ;;
mbed_official 119:3921aeca8633 11
mbed_official 119:3921aeca8633 12 MODULE ?cstartup
mbed_official 119:3921aeca8633 13
mbed_official 119:3921aeca8633 14 ;; Forward declaration of sections.
mbed_official 119:3921aeca8633 15 SECTION SVC_STACK:DATA:NOROOT(3)
mbed_official 119:3921aeca8633 16 SECTION IRQ_STACK:DATA:NOROOT(3)
mbed_official 119:3921aeca8633 17 SECTION ABT_STACK:DATA:NOROOT(3)
mbed_official 119:3921aeca8633 18 SECTION FIQ_STACK:DATA:NOROOT(3)
mbed_official 119:3921aeca8633 19 SECTION UND_STACK:DATA:NOROOT(3)
mbed_official 119:3921aeca8633 20 SECTION CSTACK:DATA:NOROOT(3)
mbed_official 119:3921aeca8633 21
mbed_official 119:3921aeca8633 22 ;
mbed_official 119:3921aeca8633 23 ; The module in this file are included in the libraries, and may be
mbed_official 119:3921aeca8633 24 ; replaced by any user-defined modules that define the PUBLIC symbol
mbed_official 119:3921aeca8633 25 ; __iar_program_start or a user defined start symbol.
mbed_official 119:3921aeca8633 26 ;
mbed_official 119:3921aeca8633 27 ; To override the cstartup defined in the library, simply add your
mbed_official 119:3921aeca8633 28 ; modified version to the workbench project.
mbed_official 119:3921aeca8633 29
mbed_official 119:3921aeca8633 30 SECTION .intvec:CODE:NOROOT(2)
mbed_official 119:3921aeca8633 31
<> 144:ef7eb2e8f9f7 32 PUBLIC __vector_core_a9
<> 144:ef7eb2e8f9f7 33 PUBWEAK __iar_program_start
mbed_official 119:3921aeca8633 34 PUBLIC Undefined_Handler
mbed_official 119:3921aeca8633 35 EXTERN SWI_Handler
mbed_official 119:3921aeca8633 36 PUBLIC Prefetch_Handler
mbed_official 119:3921aeca8633 37 PUBLIC Abort_Handler
mbed_official 119:3921aeca8633 38 PUBLIC IRQ_Handler
mbed_official 119:3921aeca8633 39 PUBLIC FIQ_Handler
mbed_official 119:3921aeca8633 40 EXTERN VbarInit
mbed_official 119:3921aeca8633 41 EXTERN SetLowVectors
mbed_official 119:3921aeca8633 42 EXTERN init_TTB
mbed_official 119:3921aeca8633 43 EXTERN enable_mmu
mbed_official 119:3921aeca8633 44 EXTERN Peripheral_BasicInit
mbed_official 119:3921aeca8633 45 EXTERN initsct
mbed_official 119:3921aeca8633 46 EXTERN PowerON_Reset
mbed_official 119:3921aeca8633 47 PUBLIC FPUEnable
mbed_official 119:3921aeca8633 48
mbed_official 119:3921aeca8633 49
mbed_official 119:3921aeca8633 50 DATA
mbed_official 119:3921aeca8633 51
mbed_official 119:3921aeca8633 52 __iar_init$$done: ; The vector table is not needed
mbed_official 119:3921aeca8633 53 ; until after copy initialization is done
mbed_official 119:3921aeca8633 54
<> 144:ef7eb2e8f9f7 55 __vector_core_a9: ; Make this a DATA label, so that stack usage
mbed_official 119:3921aeca8633 56 ; analysis doesn't consider it an uncalled fun
mbed_official 119:3921aeca8633 57
mbed_official 119:3921aeca8633 58 ARM
mbed_official 119:3921aeca8633 59
mbed_official 119:3921aeca8633 60 ; All default exception handlers (except reset) are
mbed_official 119:3921aeca8633 61 ; defined as weak symbol definitions.
mbed_official 119:3921aeca8633 62 ; If a handler is defined by the application it will take precedence.
mbed_official 119:3921aeca8633 63 LDR PC,Reset_Addr ; Reset
mbed_official 119:3921aeca8633 64 LDR PC,Undefined_Addr ; Undefined instructions
mbed_official 119:3921aeca8633 65 LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
mbed_official 119:3921aeca8633 66 LDR PC,Prefetch_Addr ; Prefetch abort
mbed_official 119:3921aeca8633 67 LDR PC,Abort_Addr ; Data abort
mbed_official 119:3921aeca8633 68 DCD 0 ; RESERVED
mbed_official 119:3921aeca8633 69 LDR PC,IRQ_Addr ; IRQ
mbed_official 119:3921aeca8633 70 LDR PC,FIQ_Addr ; FIQ
mbed_official 119:3921aeca8633 71
mbed_official 119:3921aeca8633 72 DATA
mbed_official 119:3921aeca8633 73
mbed_official 119:3921aeca8633 74 Reset_Addr: DCD __iar_program_start
mbed_official 119:3921aeca8633 75 Undefined_Addr: DCD Undefined_Handler
mbed_official 119:3921aeca8633 76 SWI_Addr: DCD SWI_Handler
mbed_official 119:3921aeca8633 77 Prefetch_Addr: DCD Prefetch_Handler
mbed_official 119:3921aeca8633 78 Abort_Addr: DCD Abort_Handler
mbed_official 119:3921aeca8633 79 IRQ_Addr: DCD IRQ_Handler
mbed_official 119:3921aeca8633 80 FIQ_Addr: DCD FIQ_Handler
mbed_official 119:3921aeca8633 81
mbed_official 119:3921aeca8633 82
mbed_official 119:3921aeca8633 83 ; --------------------------------------------------
mbed_official 119:3921aeca8633 84 ; ?cstartup -- low-level system initialization code.
mbed_official 119:3921aeca8633 85 ;
mbed_official 119:3921aeca8633 86 ; After a reset execution starts here, the mode is ARM, supervisor
mbed_official 119:3921aeca8633 87 ; with interrupts disabled.
mbed_official 119:3921aeca8633 88 ;
mbed_official 119:3921aeca8633 89
mbed_official 119:3921aeca8633 90
mbed_official 119:3921aeca8633 91
mbed_official 119:3921aeca8633 92 SECTION .text:CODE:NOROOT(2)
mbed_official 119:3921aeca8633 93 EXTERN RZ_A1_SetSramWriteEnable
mbed_official 119:3921aeca8633 94 EXTERN create_translation_table
mbed_official 119:3921aeca8633 95 EXTERN SystemInit
mbed_official 119:3921aeca8633 96 EXTERN InitMemorySubsystem
mbed_official 119:3921aeca8633 97 EXTERN __cmain
<> 144:ef7eb2e8f9f7 98 REQUIRE __vector_core_a9
mbed_official 119:3921aeca8633 99 EXTWEAK __iar_init_core
mbed_official 119:3921aeca8633 100 EXTWEAK __iar_init_vfp
mbed_official 119:3921aeca8633 101
mbed_official 119:3921aeca8633 102
mbed_official 119:3921aeca8633 103 ARM
mbed_official 119:3921aeca8633 104
mbed_official 119:3921aeca8633 105 __iar_program_start:
mbed_official 119:3921aeca8633 106 ?cstartup:
mbed_official 119:3921aeca8633 107
mbed_official 119:3921aeca8633 108
mbed_official 119:3921aeca8633 109 ;;; @ Put any cores other than 0 to sleep
mbed_official 119:3921aeca8633 110 mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR
mbed_official 119:3921aeca8633 111 ands r0, r0, #3
mbed_official 119:3921aeca8633 112
mbed_official 119:3921aeca8633 113 goToSleep:
mbed_official 119:3921aeca8633 114 wfine
mbed_official 119:3921aeca8633 115 bne goToSleep
mbed_official 119:3921aeca8633 116
mbed_official 119:3921aeca8633 117
mbed_official 119:3921aeca8633 118 //@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
mbed_official 119:3921aeca8633 119 //@ Enables Full Access i.e. in both privileged and non privileged modes
mbed_official 119:3921aeca8633 120 mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR)
mbed_official 119:3921aeca8633 121 orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11
mbed_official 119:3921aeca8633 122 mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR)
mbed_official 119:3921aeca8633 123 isb
mbed_official 119:3921aeca8633 124
mbed_official 119:3921aeca8633 125
mbed_official 119:3921aeca8633 126 ;; Switch on the VFP and NEON hardware
mbed_official 119:3921aeca8633 127 mov r0, #0x40000000
mbed_official 119:3921aeca8633 128 vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set
mbed_official 119:3921aeca8633 129
mbed_official 119:3921aeca8633 130 mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register
mbed_official 119:3921aeca8633 131 bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache
mbed_official 119:3921aeca8633 132 bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache
mbed_official 119:3921aeca8633 133 bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU
mbed_official 119:3921aeca8633 134 bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction
mbed_official 119:3921aeca8633 135 bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs
mbed_official 119:3921aeca8633 136 mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register
mbed_official 119:3921aeca8633 137 isb
mbed_official 119:3921aeca8633 138
mbed_official 119:3921aeca8633 139
mbed_official 119:3921aeca8633 140 ;; Set Vector Base Address Register (VBAR) to point to this application's vector table
<> 144:ef7eb2e8f9f7 141 ldr r0, =__vector_core_a9
mbed_official 119:3921aeca8633 142 mcr p15, 0, r0, c12, c0, 0
mbed_official 119:3921aeca8633 143
mbed_official 119:3921aeca8633 144
mbed_official 119:3921aeca8633 145 ;
mbed_official 119:3921aeca8633 146 ; Add initialization needed before setup of stackpointers here.
mbed_official 119:3921aeca8633 147 ;
mbed_official 119:3921aeca8633 148
mbed_official 119:3921aeca8633 149 ;
mbed_official 119:3921aeca8633 150 ; Initialize the stack pointers.
mbed_official 119:3921aeca8633 151 ; The pattern below can be used for any of the exception stacks:
mbed_official 119:3921aeca8633 152 ; FIQ, IRQ, SVC, ABT, UND, SYS.
mbed_official 119:3921aeca8633 153 ; The USR mode uses the same stack as SYS.
mbed_official 119:3921aeca8633 154 ; The stack segments must be defined in the linker command file,
mbed_official 119:3921aeca8633 155 ; and be declared above.
mbed_official 119:3921aeca8633 156 ;
mbed_official 119:3921aeca8633 157
mbed_official 119:3921aeca8633 158
mbed_official 119:3921aeca8633 159 ; --------------------
mbed_official 119:3921aeca8633 160 ; Mode, correspords to bits 0-5 in CPSR
mbed_official 119:3921aeca8633 161
mbed_official 119:3921aeca8633 162 #define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR
mbed_official 119:3921aeca8633 163
mbed_official 119:3921aeca8633 164 #define USR_MODE 0x10 ; User mode
mbed_official 119:3921aeca8633 165 #define FIQ_MODE 0x11 ; Fast Interrupt Request mode
mbed_official 119:3921aeca8633 166 #define IRQ_MODE 0x12 ; Interrupt Request mode
mbed_official 119:3921aeca8633 167 #define SVC_MODE 0x13 ; Supervisor mode
mbed_official 119:3921aeca8633 168 #define ABT_MODE 0x17 ; Abort mode
mbed_official 119:3921aeca8633 169 #define UND_MODE 0x1B ; Undefined Instruction mode
mbed_official 119:3921aeca8633 170 #define SYS_MODE 0x1F ; System mode
mbed_official 119:3921aeca8633 171
mbed_official 119:3921aeca8633 172 #define Mode_SVC 0x13
mbed_official 119:3921aeca8633 173 #define Mode_ABT 0x17
mbed_official 119:3921aeca8633 174 #define Mode_UND 0x1B
mbed_official 119:3921aeca8633 175 #define GICI_BASE 0xe8202000
mbed_official 119:3921aeca8633 176 #define ICCIAR_OFFSET 0x0000000C
mbed_official 119:3921aeca8633 177 #define ICCEOIR_OFFSET 0x00000010
mbed_official 119:3921aeca8633 178 #define ICCHPIR_OFFSET 0x00000018
mbed_official 119:3921aeca8633 179 #define GICD_BASE 0xe8201000
mbed_official 119:3921aeca8633 180 #define GIC_ERRATA_CHECK_1 0x000003FE
mbed_official 119:3921aeca8633 181 #define GIC_ERRATA_CHECK_2 0x000003FF
mbed_official 119:3921aeca8633 182 #define ICDABR0_OFFSET 0x00000300
mbed_official 119:3921aeca8633 183 #define ICDIPR0_OFFSET 0x00000400
mbed_official 119:3921aeca8633 184 #define T_Bit 0x20 ; when T bit is set, core is in Thumb state
mbed_official 119:3921aeca8633 185
mbed_official 119:3921aeca8633 186 MRS r0, cpsr ; Original PSR value
mbed_official 119:3921aeca8633 187
mbed_official 119:3921aeca8633 188 ;; Set up the SVC stack pointer.
mbed_official 119:3921aeca8633 189 BIC r0, r0, #MODE_MSK ; Clear the mode bits
mbed_official 119:3921aeca8633 190 ORR r0, r0, #SVC_MODE ; Set SVC mode bits
mbed_official 119:3921aeca8633 191 MSR cpsr_c, r0 ; Change the mode
mbed_official 119:3921aeca8633 192 LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK
mbed_official 119:3921aeca8633 193 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
mbed_official 119:3921aeca8633 194
mbed_official 119:3921aeca8633 195 ;; Set up the interrupt stack pointer.
mbed_official 119:3921aeca8633 196
mbed_official 119:3921aeca8633 197 BIC r0, r0, #MODE_MSK ; Clear the mode bits
mbed_official 119:3921aeca8633 198 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
mbed_official 119:3921aeca8633 199 MSR cpsr_c, r0 ; Change the mode
mbed_official 119:3921aeca8633 200 LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
mbed_official 119:3921aeca8633 201 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
mbed_official 119:3921aeca8633 202
mbed_official 119:3921aeca8633 203 ;; Set up the fast interrupt stack pointer.
mbed_official 119:3921aeca8633 204
mbed_official 119:3921aeca8633 205 BIC r0, r0, #MODE_MSK ; Clear the mode bits
mbed_official 119:3921aeca8633 206 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
mbed_official 119:3921aeca8633 207 MSR cpsr_c, r0 ; Change the mode
mbed_official 119:3921aeca8633 208 LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
mbed_official 119:3921aeca8633 209 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
mbed_official 119:3921aeca8633 210
mbed_official 119:3921aeca8633 211
mbed_official 119:3921aeca8633 212 ;; Set up the ABT stack pointer.
mbed_official 119:3921aeca8633 213
mbed_official 119:3921aeca8633 214 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
mbed_official 119:3921aeca8633 215 ORR r0 ,r0, #ABT_MODE ; Set System mode bits
mbed_official 119:3921aeca8633 216 MSR cpsr_c, r0 ; Change the mode
mbed_official 119:3921aeca8633 217 LDR sp, =SFE(ABT_STACK) ; End of CSTACK
mbed_official 119:3921aeca8633 218 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
mbed_official 119:3921aeca8633 219
mbed_official 119:3921aeca8633 220
mbed_official 119:3921aeca8633 221 ;; Set up the UDF stack pointer.
mbed_official 119:3921aeca8633 222
mbed_official 119:3921aeca8633 223 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
mbed_official 119:3921aeca8633 224 ORR r0 ,r0, #UND_MODE ; Set System mode bits
mbed_official 119:3921aeca8633 225 MSR cpsr_c, r0 ; Change the mode
mbed_official 119:3921aeca8633 226 LDR sp, =SFE(UND_STACK) ; End of CSTACK
mbed_official 119:3921aeca8633 227 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
mbed_official 119:3921aeca8633 228
mbed_official 119:3921aeca8633 229 ;; Set up the normal stack pointer.
mbed_official 119:3921aeca8633 230
mbed_official 119:3921aeca8633 231 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
mbed_official 119:3921aeca8633 232 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
mbed_official 119:3921aeca8633 233 MSR cpsr_c, r0 ; Change the mode
mbed_official 119:3921aeca8633 234 LDR sp, =SFE(CSTACK) ; End of CSTACK
mbed_official 119:3921aeca8633 235 BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
mbed_official 119:3921aeca8633 236
mbed_official 119:3921aeca8633 237 ;;;
mbed_official 119:3921aeca8633 238
mbed_official 119:3921aeca8633 239 isb
mbed_official 119:3921aeca8633 240 ldr r0, =RZ_A1_SetSramWriteEnable
mbed_official 119:3921aeca8633 241 blx r0
mbed_official 119:3921aeca8633 242
mbed_official 119:3921aeca8633 243 bl create_translation_table
mbed_official 119:3921aeca8633 244
mbed_official 119:3921aeca8633 245 ; USR/SYS stack pointer will be set during kernel init
mbed_official 119:3921aeca8633 246 ldr r0, =SystemInit
mbed_official 119:3921aeca8633 247 blx r0
mbed_official 119:3921aeca8633 248 ldr r0, =InitMemorySubsystem
mbed_official 119:3921aeca8633 249 blx r0
mbed_official 119:3921aeca8633 250
mbed_official 119:3921aeca8633 251 ; fp_init
mbed_official 119:3921aeca8633 252 mov r0, #0x3000000
mbed_official 119:3921aeca8633 253 vmsr fpscr, r0
mbed_official 119:3921aeca8633 254
mbed_official 119:3921aeca8633 255
mbed_official 119:3921aeca8633 256
mbed_official 119:3921aeca8633 257 ;;; Continue to __cmain for C-level initialization.
mbed_official 119:3921aeca8633 258
mbed_official 119:3921aeca8633 259 FUNCALL __iar_program_start, __cmain
mbed_official 119:3921aeca8633 260 B __cmain
mbed_official 119:3921aeca8633 261
mbed_official 119:3921aeca8633 262
mbed_official 119:3921aeca8633 263 ldr r0, sf_boot ;@ dummy to keep boot loader area
mbed_official 119:3921aeca8633 264 loop_here:
mbed_official 119:3921aeca8633 265 b loop_here
mbed_official 119:3921aeca8633 266
mbed_official 119:3921aeca8633 267 sf_boot:
mbed_official 119:3921aeca8633 268 DC32 0x00000001
mbed_official 119:3921aeca8633 269
mbed_official 119:3921aeca8633 270 Undefined_Handler:
mbed_official 119:3921aeca8633 271 EXTERN CUndefHandler
mbed_official 119:3921aeca8633 272 SRSDB SP!, #Mode_UND
mbed_official 119:3921aeca8633 273 PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
mbed_official 119:3921aeca8633 274
mbed_official 119:3921aeca8633 275 MRS R0, SPSR
mbed_official 119:3921aeca8633 276 TST R0, #T_Bit /* Check mode */
mbed_official 119:3921aeca8633 277 MOVEQ R1, #4 /* R1 = 4 ARM mode */
mbed_official 119:3921aeca8633 278 MOVNE R1, #2 /* R1 = 2 Thumb mode */
mbed_official 119:3921aeca8633 279 SUB R0, LR, R1
mbed_official 119:3921aeca8633 280 LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
mbed_official 119:3921aeca8633 281 BEQ undef_cont
mbed_official 119:3921aeca8633 282
mbed_official 119:3921aeca8633 283 /* Thumb instruction */
mbed_official 119:3921aeca8633 284 /* Determine if it is a 32-bit Thumb instruction */
mbed_official 119:3921aeca8633 285 LDRH R0, [R0]
mbed_official 119:3921aeca8633 286 MOV R2, #0x1c
mbed_official 119:3921aeca8633 287 CMP R2, R0, LSR #11
mbed_official 119:3921aeca8633 288 BHS undef_cont /* 16-bit Thumb instruction */
mbed_official 119:3921aeca8633 289
mbed_official 119:3921aeca8633 290 /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
mbed_official 119:3921aeca8633 291 LDRH R2, [LR]
mbed_official 119:3921aeca8633 292 ORR R0, R2, R0, LSL #16
mbed_official 119:3921aeca8633 293 undef_cont:
mbed_official 119:3921aeca8633 294 MOV R2, LR /* Set LR to third argument */
mbed_official 119:3921aeca8633 295
mbed_official 119:3921aeca8633 296 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 297 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 298 AND R12, R3, #4
mbed_official 119:3921aeca8633 299 SUB SP, SP, R12 /* Adjust stack */
mbed_official 119:3921aeca8633 300 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
mbed_official 119:3921aeca8633 301
mbed_official 119:3921aeca8633 302 /* R0 Offending instruction */
mbed_official 119:3921aeca8633 303 /* R1 =2 (Thumb) or =4 (ARM) */
mbed_official 119:3921aeca8633 304 BL CUndefHandler
mbed_official 119:3921aeca8633 305
mbed_official 119:3921aeca8633 306 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
mbed_official 119:3921aeca8633 307 ADD SP, SP, R12 /* Unadjust stack */
mbed_official 119:3921aeca8633 308
mbed_official 119:3921aeca8633 309 LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
mbed_official 119:3921aeca8633 310 SUB LR, LR, R0
mbed_official 119:3921aeca8633 311 LDR R0, [SP, #28] /* Restore stacked SPSR */
mbed_official 119:3921aeca8633 312 MSR SPSR_cxsf, R0
mbed_official 119:3921aeca8633 313 POP {R0-R4, R12} /* Restore stacked APCS registers */
mbed_official 119:3921aeca8633 314 ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
mbed_official 119:3921aeca8633 315 MOVS PC, LR
mbed_official 119:3921aeca8633 316
mbed_official 119:3921aeca8633 317 Prefetch_Handler:
mbed_official 119:3921aeca8633 318 EXTERN CPAbtHandler
mbed_official 119:3921aeca8633 319 SUB LR, LR, #4 /* Pre-adjust LR */
mbed_official 119:3921aeca8633 320 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
mbed_official 119:3921aeca8633 321 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
mbed_official 119:3921aeca8633 322 MRC p15, 0, R0, c5, c0, 1 /* IFSR */
mbed_official 119:3921aeca8633 323 MRC p15, 0, R1, c6, c0, 2 /* IFAR */
mbed_official 119:3921aeca8633 324
mbed_official 119:3921aeca8633 325 MOV R2, LR /* Set LR to third argument */
mbed_official 119:3921aeca8633 326
mbed_official 119:3921aeca8633 327 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 328 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 329 AND R12, R3, #4
mbed_official 119:3921aeca8633 330 SUB SP, SP, R12 /* Adjust stack */
mbed_official 119:3921aeca8633 331 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
mbed_official 119:3921aeca8633 332
mbed_official 119:3921aeca8633 333 BL CPAbtHandler
mbed_official 119:3921aeca8633 334
mbed_official 119:3921aeca8633 335 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
mbed_official 119:3921aeca8633 336 ADD SP, SP, R12 /* Unadjust stack */
mbed_official 119:3921aeca8633 337
mbed_official 119:3921aeca8633 338 POP {R0-R4, R12} /* Restore stack APCS registers */
mbed_official 119:3921aeca8633 339 RFEFD SP! /* Return from exception */
mbed_official 119:3921aeca8633 340
mbed_official 119:3921aeca8633 341 Abort_Handler:
mbed_official 119:3921aeca8633 342 EXTERN CDAbtHandler
mbed_official 119:3921aeca8633 343 SUB LR, LR, #8 /* Pre-adjust LR */
mbed_official 119:3921aeca8633 344 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
mbed_official 119:3921aeca8633 345 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
mbed_official 119:3921aeca8633 346 CLREX /* State of exclusive monitors unknown after taken data abort */
mbed_official 119:3921aeca8633 347 MRC p15, 0, R0, c5, c0, 0 /* DFSR */
mbed_official 119:3921aeca8633 348 MRC p15, 0, R1, c6, c0, 0 /* DFAR */
mbed_official 119:3921aeca8633 349
mbed_official 119:3921aeca8633 350 MOV R2, LR /* Set LR to third argument */
mbed_official 119:3921aeca8633 351
mbed_official 119:3921aeca8633 352 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 353 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 354 AND R12, R3, #4
mbed_official 119:3921aeca8633 355 SUB SP, SP, R12 /* Adjust stack */
mbed_official 119:3921aeca8633 356 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
mbed_official 119:3921aeca8633 357
mbed_official 119:3921aeca8633 358 BL CDAbtHandler
mbed_official 119:3921aeca8633 359
mbed_official 119:3921aeca8633 360 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
mbed_official 119:3921aeca8633 361 ADD SP, SP, R12 /* Unadjust stack */
mbed_official 119:3921aeca8633 362
mbed_official 119:3921aeca8633 363 POP {R0-R4, R12} /* Restore stacked APCS registers */
mbed_official 119:3921aeca8633 364 RFEFD SP! /* Return from exception */
mbed_official 119:3921aeca8633 365
mbed_official 119:3921aeca8633 366 FIQ_Handler:
mbed_official 119:3921aeca8633 367 /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
mbed_official 119:3921aeca8633 368 * so if a real FIQ Handler is implemented, this will be needed before returning:
mbed_official 119:3921aeca8633 369 */
mbed_official 119:3921aeca8633 370 /* LDR R1, =GICI_BASE
mbed_official 119:3921aeca8633 371 LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
mbed_official 119:3921aeca8633 372 */
mbed_official 119:3921aeca8633 373 B .
mbed_official 119:3921aeca8633 374
mbed_official 119:3921aeca8633 375 EXTERN SVC_Handler /* refer RTX function */
mbed_official 119:3921aeca8633 376
mbed_official 119:3921aeca8633 377 IRQ_Handler:
mbed_official 119:3921aeca8633 378 EXTERN IRQCount
mbed_official 119:3921aeca8633 379 EXTERN IRQTable
mbed_official 119:3921aeca8633 380 EXTERN IRQNestLevel
mbed_official 119:3921aeca8633 381
mbed_official 119:3921aeca8633 382 /* prologue */
mbed_official 119:3921aeca8633 383 SUB LR, LR, #4 /* Pre-adjust LR */
mbed_official 119:3921aeca8633 384 SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
mbed_official 119:3921aeca8633 385 CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
mbed_official 119:3921aeca8633 386 PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
mbed_official 119:3921aeca8633 387
mbed_official 119:3921aeca8633 388 /* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 389 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 119:3921aeca8633 390 AND R1, R3, #4
mbed_official 119:3921aeca8633 391 SUB SP, SP, R1 /* Adjust stack */
mbed_official 119:3921aeca8633 392 PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
mbed_official 119:3921aeca8633 393
mbed_official 119:3921aeca8633 394 LDR R0, =IRQNestLevel /* Get address of nesting counter */
mbed_official 119:3921aeca8633 395 LDR R1, [R0]
mbed_official 119:3921aeca8633 396 ADD R1, R1, #1 /* Increment nesting counter */
mbed_official 119:3921aeca8633 397 STR R1, [R0]
mbed_official 119:3921aeca8633 398
mbed_official 119:3921aeca8633 399 /* identify and acknowledge interrupt */
mbed_official 119:3921aeca8633 400 LDR R1, =GICI_BASE
mbed_official 119:3921aeca8633 401 LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
mbed_official 119:3921aeca8633 402 LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
mbed_official 119:3921aeca8633 403 DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
mbed_official 119:3921aeca8633 404
mbed_official 119:3921aeca8633 405 /* Workaround GIC 390 errata 733075
mbed_official 119:3921aeca8633 406 * If the ID is not 0, then service the interrupt as normal.
mbed_official 119:3921aeca8633 407 * If the ID is 0 and active, then service interrupt ID 0 as normal.
mbed_official 119:3921aeca8633 408 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
mbed_official 119:3921aeca8633 409 * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
mbed_official 119:3921aeca8633 410 */
mbed_official 119:3921aeca8633 411 LDR R2, =GICD_BASE
mbed_official 119:3921aeca8633 412 LDR R3, =GIC_ERRATA_CHECK_1
mbed_official 119:3921aeca8633 413 CMP R0, R3
mbed_official 119:3921aeca8633 414 BEQ unlock_cpu
mbed_official 119:3921aeca8633 415 LDR R3, =GIC_ERRATA_CHECK_2
mbed_official 119:3921aeca8633 416 CMP R0, R3
mbed_official 119:3921aeca8633 417 BEQ unlock_cpu
mbed_official 119:3921aeca8633 418 CMP R0, #0
mbed_official 119:3921aeca8633 419 BNE int_active /* If the ID is not 0, then service the interrupt */
mbed_official 119:3921aeca8633 420 LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
mbed_official 119:3921aeca8633 421 TST R3, #1
mbed_official 119:3921aeca8633 422 BNE int_active /* If active, then service the interrupt */
mbed_official 119:3921aeca8633 423 unlock_cpu:
mbed_official 119:3921aeca8633 424 LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
mbed_official 119:3921aeca8633 425 STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
mbed_official 119:3921aeca8633 426 DSB /* Ensure the write completes before continuing */
mbed_official 119:3921aeca8633 427 B ret_irq /* Do not service the spurious interrupt */
mbed_official 119:3921aeca8633 428 /* End workaround */
mbed_official 119:3921aeca8633 429
mbed_official 119:3921aeca8633 430 int_active:
mbed_official 119:3921aeca8633 431 LDR R2, =IRQCount /* Read number of IRQs */
mbed_official 119:3921aeca8633 432 LDR R2, [R2]
mbed_official 119:3921aeca8633 433 CMP R0, R2 /* Clean up and return if no handler */
mbed_official 119:3921aeca8633 434 BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
mbed_official 119:3921aeca8633 435 LDR R2, =IRQTable /* Get address of handler */
mbed_official 119:3921aeca8633 436 LDR R2, [R2, R0, LSL #2]
mbed_official 119:3921aeca8633 437 CMP R2, #0 /* Clean up and return if handler address is 0 */
mbed_official 119:3921aeca8633 438 BEQ ret_irq
mbed_official 119:3921aeca8633 439 PUSH {R0,R1}
mbed_official 119:3921aeca8633 440
mbed_official 119:3921aeca8633 441 CPSIE i /* Now safe to re-enable interrupts */
mbed_official 119:3921aeca8633 442 BLX R2 /* Call handler. R0 will be IRQ number */
mbed_official 119:3921aeca8633 443 CPSID i /* Disable interrupts again */
mbed_official 119:3921aeca8633 444
mbed_official 119:3921aeca8633 445 /* write EOIR (GIC CPU Interface register) */
mbed_official 119:3921aeca8633 446 POP {R0,R1}
mbed_official 119:3921aeca8633 447 DSB /* Ensure that interrupt source is cleared before we write the EOIR */
mbed_official 119:3921aeca8633 448 ret_irq:
mbed_official 119:3921aeca8633 449 /* epilogue */
mbed_official 119:3921aeca8633 450 STR R0, [R1, #ICCEOIR_OFFSET]
mbed_official 119:3921aeca8633 451
mbed_official 119:3921aeca8633 452 LDR R0, =IRQNestLevel /* Get address of nesting counter */
mbed_official 119:3921aeca8633 453 LDR R1, [R0]
mbed_official 119:3921aeca8633 454 SUB R1, R1, #1 /* Decrement nesting counter */
mbed_official 119:3921aeca8633 455 STR R1, [R0]
mbed_official 119:3921aeca8633 456
mbed_official 119:3921aeca8633 457 POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
mbed_official 119:3921aeca8633 458 ADD SP, SP, R1 /* Unadjust stack */
mbed_official 119:3921aeca8633 459
mbed_official 119:3921aeca8633 460 POP {R0-R3,R12} /* Restore stacked APCS registers */
mbed_official 119:3921aeca8633 461 RFEFD SP! /* Return from exception */
mbed_official 119:3921aeca8633 462 ;;;
mbed_official 119:3921aeca8633 463 ;;; Add more initialization here
mbed_official 119:3921aeca8633 464 ;;;
mbed_official 119:3921aeca8633 465 FPUEnable:
mbed_official 119:3921aeca8633 466 ARM
mbed_official 119:3921aeca8633 467
mbed_official 119:3921aeca8633 468 //Permit access to VFP registers by modifying CPACR
mbed_official 119:3921aeca8633 469 MRC p15,0,R1,c1,c0,2
mbed_official 119:3921aeca8633 470 ORR R1,R1,#0x00F00000
mbed_official 119:3921aeca8633 471 MCR p15,0,R1,c1,c0,2
mbed_official 119:3921aeca8633 472
mbed_official 119:3921aeca8633 473 //Enable VFP
mbed_official 119:3921aeca8633 474 VMRS R1,FPEXC
mbed_official 119:3921aeca8633 475 ORR R1,R1,#0x40000000
mbed_official 119:3921aeca8633 476 VMSR FPEXC,R1
mbed_official 119:3921aeca8633 477
mbed_official 119:3921aeca8633 478 //Initialise VFP registers to 0
mbed_official 119:3921aeca8633 479 MOV R2,#0
mbed_official 119:3921aeca8633 480 VMOV D0, R2,R2
mbed_official 119:3921aeca8633 481 VMOV D1, R2,R2
mbed_official 119:3921aeca8633 482 VMOV D2, R2,R2
mbed_official 119:3921aeca8633 483 VMOV D3, R2,R2
mbed_official 119:3921aeca8633 484 VMOV D4, R2,R2
mbed_official 119:3921aeca8633 485 VMOV D5, R2,R2
mbed_official 119:3921aeca8633 486 VMOV D6, R2,R2
mbed_official 119:3921aeca8633 487 VMOV D7, R2,R2
mbed_official 119:3921aeca8633 488 VMOV D8, R2,R2
mbed_official 119:3921aeca8633 489 VMOV D9, R2,R2
mbed_official 119:3921aeca8633 490 VMOV D10,R2,R2
mbed_official 119:3921aeca8633 491 VMOV D11,R2,R2
mbed_official 119:3921aeca8633 492 VMOV D12,R2,R2
mbed_official 119:3921aeca8633 493 VMOV D13,R2,R2
mbed_official 119:3921aeca8633 494 VMOV D14,R2,R2
mbed_official 119:3921aeca8633 495 VMOV D15,R2,R2
mbed_official 119:3921aeca8633 496
mbed_official 119:3921aeca8633 497 //Initialise FPSCR to a known state
mbed_official 119:3921aeca8633 498 VMRS R2,FPSCR
mbed_official 119:3921aeca8633 499 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
mbed_official 119:3921aeca8633 500 AND R2,R2,R3
mbed_official 119:3921aeca8633 501 VMSR FPSCR,R2
mbed_official 119:3921aeca8633 502
mbed_official 119:3921aeca8633 503 BX LR
mbed_official 119:3921aeca8633 504
mbed_official 119:3921aeca8633 505 END