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Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h@161:bd0311f1ad86, 2017-05-27 (annotated)

Committer:
tonnyleonard
Date:
Sat May 27 01:26:18 2017 +0000
Revision:
161:bd0311f1ad86
Parent:
150:02e0a0aed4ec 
Testing ADC with shunt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32pg1b_idac.h
<> 150:02e0a0aed4ec 3 * @brief EFM32PG1B_IDAC register and bit field definitions
<> 150:02e0a0aed4ec 4 * @version 5.0.0
<> 150:02e0a0aed4ec 5 ******************************************************************************
<> 150:02e0a0aed4ec 6 * @section License
<> 150:02e0a0aed4ec 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 8 ******************************************************************************
<> 150:02e0a0aed4ec 9 *
<> 150:02e0a0aed4ec 10 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 11 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 12 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 15 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 17 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 18 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 19 *
<> 150:02e0a0aed4ec 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 23 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 24 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 25 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 28 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 29 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 *****************************************************************************/
<> 150:02e0a0aed4ec 32 /**************************************************************************//**
<> 150:02e0a0aed4ec 33 * @addtogroup Parts
<> 150:02e0a0aed4ec 34 * @{
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36 /**************************************************************************//**
<> 150:02e0a0aed4ec 37 * @defgroup EFM32PG1B_IDAC
<> 150:02e0a0aed4ec 38 * @{
<> 150:02e0a0aed4ec 39 * @brief EFM32PG1B_IDAC Register Declaration
<> 150:02e0a0aed4ec 40 *****************************************************************************/
<> 150:02e0a0aed4ec 41 typedef struct
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 __IOM uint32_t CTRL; /**< Control Register */
<> 150:02e0a0aed4ec 44 __IOM uint32_t CURPROG; /**< Current Programming Register */
<> 150:02e0a0aed4ec 45 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 46 __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */
<> 150:02e0a0aed4ec 47
<> 150:02e0a0aed4ec 48 uint32_t RESERVED1[2]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 49 __IM uint32_t STATUS; /**< Status Register */
<> 150:02e0a0aed4ec 50 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 51 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 150:02e0a0aed4ec 52 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 150:02e0a0aed4ec 53 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 150:02e0a0aed4ec 54 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 150:02e0a0aed4ec 55 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 150:02e0a0aed4ec 56 __IM uint32_t APORTREQ; /**< APORT Request Status Register */
<> 150:02e0a0aed4ec 57 __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
<> 150:02e0a0aed4ec 58 } IDAC_TypeDef; /** @} */
<> 150:02e0a0aed4ec 59
<> 150:02e0a0aed4ec 60 /**************************************************************************//**
<> 150:02e0a0aed4ec 61 * @defgroup EFM32PG1B_IDAC_BitFields
<> 150:02e0a0aed4ec 62 * @{
<> 150:02e0a0aed4ec 63 *****************************************************************************/
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 /* Bit fields for IDAC CTRL */
<> 150:02e0a0aed4ec 66 #define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
<> 150:02e0a0aed4ec 67 #define _IDAC_CTRL_MASK 0x00F17FFFUL /**< Mask for IDAC_CTRL */
<> 150:02e0a0aed4ec 68 #define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
<> 150:02e0a0aed4ec 69 #define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
<> 150:02e0a0aed4ec 70 #define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
<> 150:02e0a0aed4ec 71 #define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 72 #define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 73 #define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
<> 150:02e0a0aed4ec 74 #define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
<> 150:02e0a0aed4ec 75 #define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
<> 150:02e0a0aed4ec 76 #define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 77 #define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 78 #define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
<> 150:02e0a0aed4ec 79 #define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
<> 150:02e0a0aed4ec 80 #define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
<> 150:02e0a0aed4ec 81 #define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 82 #define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 83 #define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */
<> 150:02e0a0aed4ec 84 #define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */
<> 150:02e0a0aed4ec 85 #define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */
<> 150:02e0a0aed4ec 86 #define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 87 #define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 88 #define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */
<> 150:02e0a0aed4ec 89 #define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */
<> 150:02e0a0aed4ec 90 #define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 91 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */
<> 150:02e0a0aed4ec 92 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */
<> 150:02e0a0aed4ec 93 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */
<> 150:02e0a0aed4ec 94 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */
<> 150:02e0a0aed4ec 95 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */
<> 150:02e0a0aed4ec 96 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */
<> 150:02e0a0aed4ec 97 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */
<> 150:02e0a0aed4ec 98 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */
<> 150:02e0a0aed4ec 99 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */
<> 150:02e0a0aed4ec 100 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */
<> 150:02e0a0aed4ec 101 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */
<> 150:02e0a0aed4ec 102 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */
<> 150:02e0a0aed4ec 103 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */
<> 150:02e0a0aed4ec 104 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */
<> 150:02e0a0aed4ec 105 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */
<> 150:02e0a0aed4ec 106 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */
<> 150:02e0a0aed4ec 107 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */
<> 150:02e0a0aed4ec 108 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */
<> 150:02e0a0aed4ec 109 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */
<> 150:02e0a0aed4ec 110 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */
<> 150:02e0a0aed4ec 111 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */
<> 150:02e0a0aed4ec 112 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */
<> 150:02e0a0aed4ec 113 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */
<> 150:02e0a0aed4ec 114 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */
<> 150:02e0a0aed4ec 115 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */
<> 150:02e0a0aed4ec 116 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */
<> 150:02e0a0aed4ec 117 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */
<> 150:02e0a0aed4ec 118 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */
<> 150:02e0a0aed4ec 119 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */
<> 150:02e0a0aed4ec 120 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */
<> 150:02e0a0aed4ec 121 #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */
<> 150:02e0a0aed4ec 122 #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */
<> 150:02e0a0aed4ec 123 #define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 124 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */
<> 150:02e0a0aed4ec 125 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */
<> 150:02e0a0aed4ec 126 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */
<> 150:02e0a0aed4ec 127 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */
<> 150:02e0a0aed4ec 128 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */
<> 150:02e0a0aed4ec 129 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */
<> 150:02e0a0aed4ec 130 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */
<> 150:02e0a0aed4ec 131 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */
<> 150:02e0a0aed4ec 132 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */
<> 150:02e0a0aed4ec 133 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */
<> 150:02e0a0aed4ec 134 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */
<> 150:02e0a0aed4ec 135 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */
<> 150:02e0a0aed4ec 136 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */
<> 150:02e0a0aed4ec 137 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */
<> 150:02e0a0aed4ec 138 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */
<> 150:02e0a0aed4ec 139 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */
<> 150:02e0a0aed4ec 140 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */
<> 150:02e0a0aed4ec 141 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */
<> 150:02e0a0aed4ec 142 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */
<> 150:02e0a0aed4ec 143 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */
<> 150:02e0a0aed4ec 144 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */
<> 150:02e0a0aed4ec 145 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */
<> 150:02e0a0aed4ec 146 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */
<> 150:02e0a0aed4ec 147 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */
<> 150:02e0a0aed4ec 148 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */
<> 150:02e0a0aed4ec 149 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */
<> 150:02e0a0aed4ec 150 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */
<> 150:02e0a0aed4ec 151 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */
<> 150:02e0a0aed4ec 152 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */
<> 150:02e0a0aed4ec 153 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */
<> 150:02e0a0aed4ec 154 #define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */
<> 150:02e0a0aed4ec 155 #define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */
<> 150:02e0a0aed4ec 156 #define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */
<> 150:02e0a0aed4ec 157 #define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */
<> 150:02e0a0aed4ec 158 #define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */
<> 150:02e0a0aed4ec 159 #define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 160 #define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */
<> 150:02e0a0aed4ec 161 #define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */
<> 150:02e0a0aed4ec 162 #define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 163 #define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */
<> 150:02e0a0aed4ec 164 #define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */
<> 150:02e0a0aed4ec 165 #define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */
<> 150:02e0a0aed4ec 166 #define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */
<> 150:02e0a0aed4ec 167 #define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */
<> 150:02e0a0aed4ec 168 #define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 169 #define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 170 #define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */
<> 150:02e0a0aed4ec 171 #define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */
<> 150:02e0a0aed4ec 172 #define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */
<> 150:02e0a0aed4ec 173 #define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 174 #define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 175 #define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */
<> 150:02e0a0aed4ec 176 #define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */
<> 150:02e0a0aed4ec 177 #define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */
<> 150:02e0a0aed4ec 178 #define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 179 #define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 180 #define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
<> 150:02e0a0aed4ec 181 #define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */
<> 150:02e0a0aed4ec 182 #define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 183 #define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
<> 150:02e0a0aed4ec 184 #define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
<> 150:02e0a0aed4ec 185 #define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
<> 150:02e0a0aed4ec 186 #define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
<> 150:02e0a0aed4ec 187 #define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */
<> 150:02e0a0aed4ec 188 #define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */
<> 150:02e0a0aed4ec 189 #define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */
<> 150:02e0a0aed4ec 190 #define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */
<> 150:02e0a0aed4ec 191 #define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */
<> 150:02e0a0aed4ec 192 #define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */
<> 150:02e0a0aed4ec 193 #define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */
<> 150:02e0a0aed4ec 194 #define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */
<> 150:02e0a0aed4ec 195 #define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
<> 150:02e0a0aed4ec 196 #define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
<> 150:02e0a0aed4ec 197 #define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
<> 150:02e0a0aed4ec 198 #define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
<> 150:02e0a0aed4ec 199 #define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
<> 150:02e0a0aed4ec 200 #define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */
<> 150:02e0a0aed4ec 201 #define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */
<> 150:02e0a0aed4ec 202 #define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */
<> 150:02e0a0aed4ec 203 #define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */
<> 150:02e0a0aed4ec 204 #define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */
<> 150:02e0a0aed4ec 205 #define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */
<> 150:02e0a0aed4ec 206 #define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */
<> 150:02e0a0aed4ec 207 #define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */
<> 150:02e0a0aed4ec 208
<> 150:02e0a0aed4ec 209 /* Bit fields for IDAC CURPROG */
<> 150:02e0a0aed4ec 210 #define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */
<> 150:02e0a0aed4ec 211 #define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */
<> 150:02e0a0aed4ec 212 #define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
<> 150:02e0a0aed4ec 213 #define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
<> 150:02e0a0aed4ec 214 #define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
<> 150:02e0a0aed4ec 215 #define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 216 #define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 217 #define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 218 #define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 219 #define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
<> 150:02e0a0aed4ec 220 #define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 221 #define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 222 #define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 223 #define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
<> 150:02e0a0aed4ec 224 #define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
<> 150:02e0a0aed4ec 225 #define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
<> 150:02e0a0aed4ec 226 #define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
<> 150:02e0a0aed4ec 227 #define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
<> 150:02e0a0aed4ec 228 #define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */
<> 150:02e0a0aed4ec 229 #define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */
<> 150:02e0a0aed4ec 230 #define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */
<> 150:02e0a0aed4ec 231 #define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */
<> 150:02e0a0aed4ec 232
<> 150:02e0a0aed4ec 233 /* Bit fields for IDAC DUTYCONFIG */
<> 150:02e0a0aed4ec 234 #define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
<> 150:02e0a0aed4ec 235 #define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
<> 150:02e0a0aed4ec 236 #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */
<> 150:02e0a0aed4ec 237 #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
<> 150:02e0a0aed4ec 238 #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
<> 150:02e0a0aed4ec 239 #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
<> 150:02e0a0aed4ec 240 #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
<> 150:02e0a0aed4ec 241
<> 150:02e0a0aed4ec 242 /* Bit fields for IDAC STATUS */
<> 150:02e0a0aed4ec 243 #define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */
<> 150:02e0a0aed4ec 244 #define _IDAC_STATUS_MASK 0x00000002UL /**< Mask for IDAC_STATUS */
<> 150:02e0a0aed4ec 245 #define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */
<> 150:02e0a0aed4ec 246 #define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 247 #define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 248 #define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
<> 150:02e0a0aed4ec 249 #define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */
<> 150:02e0a0aed4ec 250
<> 150:02e0a0aed4ec 251 /* Bit fields for IDAC IF */
<> 150:02e0a0aed4ec 252 #define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */
<> 150:02e0a0aed4ec 253 #define _IDAC_IF_MASK 0x00000002UL /**< Mask for IDAC_IF */
<> 150:02e0a0aed4ec 254 #define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */
<> 150:02e0a0aed4ec 255 #define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 256 #define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 257 #define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
<> 150:02e0a0aed4ec 258 #define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */
<> 150:02e0a0aed4ec 259
<> 150:02e0a0aed4ec 260 /* Bit fields for IDAC IFS */
<> 150:02e0a0aed4ec 261 #define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */
<> 150:02e0a0aed4ec 262 #define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */
<> 150:02e0a0aed4ec 263 #define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */
<> 150:02e0a0aed4ec 264 #define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
<> 150:02e0a0aed4ec 265 #define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
<> 150:02e0a0aed4ec 266 #define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
<> 150:02e0a0aed4ec 267 #define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */
<> 150:02e0a0aed4ec 268 #define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */
<> 150:02e0a0aed4ec 269 #define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 270 #define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 271 #define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
<> 150:02e0a0aed4ec 272 #define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */
<> 150:02e0a0aed4ec 273
<> 150:02e0a0aed4ec 274 /* Bit fields for IDAC IFC */
<> 150:02e0a0aed4ec 275 #define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */
<> 150:02e0a0aed4ec 276 #define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */
<> 150:02e0a0aed4ec 277 #define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */
<> 150:02e0a0aed4ec 278 #define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
<> 150:02e0a0aed4ec 279 #define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
<> 150:02e0a0aed4ec 280 #define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
<> 150:02e0a0aed4ec 281 #define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */
<> 150:02e0a0aed4ec 282 #define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */
<> 150:02e0a0aed4ec 283 #define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 284 #define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 285 #define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
<> 150:02e0a0aed4ec 286 #define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */
<> 150:02e0a0aed4ec 287
<> 150:02e0a0aed4ec 288 /* Bit fields for IDAC IEN */
<> 150:02e0a0aed4ec 289 #define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */
<> 150:02e0a0aed4ec 290 #define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */
<> 150:02e0a0aed4ec 291 #define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */
<> 150:02e0a0aed4ec 292 #define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
<> 150:02e0a0aed4ec 293 #define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
<> 150:02e0a0aed4ec 294 #define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
<> 150:02e0a0aed4ec 295 #define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */
<> 150:02e0a0aed4ec 296 #define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */
<> 150:02e0a0aed4ec 297 #define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 298 #define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 299 #define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
<> 150:02e0a0aed4ec 300 #define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */
<> 150:02e0a0aed4ec 301
<> 150:02e0a0aed4ec 302 /* Bit fields for IDAC APORTREQ */
<> 150:02e0a0aed4ec 303 #define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
<> 150:02e0a0aed4ec 304 #define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
<> 150:02e0a0aed4ec 305 #define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */
<> 150:02e0a0aed4ec 306 #define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
<> 150:02e0a0aed4ec 307 #define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
<> 150:02e0a0aed4ec 308 #define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
<> 150:02e0a0aed4ec 309 #define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
<> 150:02e0a0aed4ec 310 #define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */
<> 150:02e0a0aed4ec 311 #define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
<> 150:02e0a0aed4ec 312 #define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
<> 150:02e0a0aed4ec 313 #define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
<> 150:02e0a0aed4ec 314 #define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
<> 150:02e0a0aed4ec 315
<> 150:02e0a0aed4ec 316 /* Bit fields for IDAC APORTCONFLICT */
<> 150:02e0a0aed4ec 317 #define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 318 #define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 319 #define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
<> 150:02e0a0aed4ec 320 #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
<> 150:02e0a0aed4ec 321 #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
<> 150:02e0a0aed4ec 322 #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 323 #define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 324 #define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
<> 150:02e0a0aed4ec 325 #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
<> 150:02e0a0aed4ec 326 #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
<> 150:02e0a0aed4ec 327 #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 328 #define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
<> 150:02e0a0aed4ec 329
<> 150:02e0a0aed4ec 330 /** @} End of group EFM32PG1B_IDAC */
<> 150:02e0a0aed4ec 331 /** @} End of group Parts */
<> 150:02e0a0aed4ec 332