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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_smc.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_smc.h"
<> 154:37f96f9d4de2 32 #include "fsl_flash.h"
<> 154:37f96f9d4de2 33
<> 154:37f96f9d4de2 34 #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
<> 154:37f96f9d4de2 35 void SMC_GetParam(SMC_Type *base, smc_param_t *param)
<> 154:37f96f9d4de2 36 {
<> 154:37f96f9d4de2 37 uint32_t reg = base->PARAM;
<> 154:37f96f9d4de2 38 param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK);
<> 154:37f96f9d4de2 39 param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK);
<> 154:37f96f9d4de2 40 param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK);
<> 154:37f96f9d4de2 41 param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK);
<> 154:37f96f9d4de2 42 }
<> 154:37f96f9d4de2 43 #endif /* FSL_FEATURE_SMC_HAS_PARAM */
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 void SMC_PreEnterStopModes(void)
<> 154:37f96f9d4de2 46 {
<> 154:37f96f9d4de2 47 flash_prefetch_speculation_status_t speculationStatus =
<> 154:37f96f9d4de2 48 {
<> 154:37f96f9d4de2 49 kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/
<> 154:37f96f9d4de2 50 kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/
<> 154:37f96f9d4de2 51 };
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 __disable_irq();
<> 154:37f96f9d4de2 54 __ISB();
<> 154:37f96f9d4de2 55
<> 154:37f96f9d4de2 56 /*
<> 154:37f96f9d4de2 57 * Before enter stop modes, the flash cache prefetch should be disabled.
<> 154:37f96f9d4de2 58 * Otherwise the prefetch might be interrupted by stop, then the data and
<> 154:37f96f9d4de2 59 * and instruction from flash are wrong.
<> 154:37f96f9d4de2 60 */
<> 154:37f96f9d4de2 61 FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
<> 154:37f96f9d4de2 62 }
<> 154:37f96f9d4de2 63
<> 154:37f96f9d4de2 64 void SMC_PostExitStopModes(void)
<> 154:37f96f9d4de2 65 {
<> 154:37f96f9d4de2 66 flash_prefetch_speculation_status_t speculationStatus =
<> 154:37f96f9d4de2 67 {
<> 154:37f96f9d4de2 68 kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/
<> 154:37f96f9d4de2 69 kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/
<> 154:37f96f9d4de2 70 };
<> 154:37f96f9d4de2 71
<> 154:37f96f9d4de2 72 FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
<> 154:37f96f9d4de2 73
<> 154:37f96f9d4de2 74 __enable_irq();
<> 154:37f96f9d4de2 75 __ISB();
<> 154:37f96f9d4de2 76 }
<> 154:37f96f9d4de2 77
<> 154:37f96f9d4de2 78 status_t SMC_SetPowerModeRun(SMC_Type *base)
<> 154:37f96f9d4de2 79 {
<> 154:37f96f9d4de2 80 uint8_t reg;
<> 154:37f96f9d4de2 81
<> 154:37f96f9d4de2 82 reg = base->PMCTRL;
<> 154:37f96f9d4de2 83 /* configure Normal RUN mode */
<> 154:37f96f9d4de2 84 reg &= ~SMC_PMCTRL_RUNM_MASK;
<> 154:37f96f9d4de2 85 reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
<> 154:37f96f9d4de2 86 base->PMCTRL = reg;
<> 154:37f96f9d4de2 87
<> 154:37f96f9d4de2 88 return kStatus_Success;
<> 154:37f96f9d4de2 89 }
<> 154:37f96f9d4de2 90
<> 154:37f96f9d4de2 91 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
<> 154:37f96f9d4de2 92 status_t SMC_SetPowerModeHsrun(SMC_Type *base)
<> 154:37f96f9d4de2 93 {
<> 154:37f96f9d4de2 94 uint8_t reg;
<> 154:37f96f9d4de2 95
<> 154:37f96f9d4de2 96 reg = base->PMCTRL;
<> 154:37f96f9d4de2 97 /* configure High Speed RUN mode */
<> 154:37f96f9d4de2 98 reg &= ~SMC_PMCTRL_RUNM_MASK;
<> 154:37f96f9d4de2 99 reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
<> 154:37f96f9d4de2 100 base->PMCTRL = reg;
<> 154:37f96f9d4de2 101
<> 154:37f96f9d4de2 102 return kStatus_Success;
<> 154:37f96f9d4de2 103 }
<> 154:37f96f9d4de2 104 #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
<> 154:37f96f9d4de2 105
<> 154:37f96f9d4de2 106 status_t SMC_SetPowerModeWait(SMC_Type *base)
<> 154:37f96f9d4de2 107 {
<> 154:37f96f9d4de2 108 /* configure Normal Wait mode */
<> 154:37f96f9d4de2 109 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 154:37f96f9d4de2 110 __DSB();
<> 154:37f96f9d4de2 111 __WFI();
<> 154:37f96f9d4de2 112 __ISB();
<> 154:37f96f9d4de2 113
<> 154:37f96f9d4de2 114 return kStatus_Success;
<> 154:37f96f9d4de2 115 }
<> 154:37f96f9d4de2 116
<> 154:37f96f9d4de2 117 status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
<> 154:37f96f9d4de2 118 {
<> 154:37f96f9d4de2 119 uint8_t reg;
<> 154:37f96f9d4de2 120
<> 154:37f96f9d4de2 121 #if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO)
<> 154:37f96f9d4de2 122 /* configure the Partial Stop mode in Noraml Stop mode */
<> 154:37f96f9d4de2 123 reg = base->STOPCTRL;
<> 154:37f96f9d4de2 124 reg &= ~SMC_STOPCTRL_PSTOPO_MASK;
<> 154:37f96f9d4de2 125 reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT);
<> 154:37f96f9d4de2 126 base->STOPCTRL = reg;
<> 154:37f96f9d4de2 127 #endif
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 /* configure Normal Stop mode */
<> 154:37f96f9d4de2 130 reg = base->PMCTRL;
<> 154:37f96f9d4de2 131 reg &= ~SMC_PMCTRL_STOPM_MASK;
<> 154:37f96f9d4de2 132 reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
<> 154:37f96f9d4de2 133 base->PMCTRL = reg;
<> 154:37f96f9d4de2 134
<> 154:37f96f9d4de2 135 /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
<> 154:37f96f9d4de2 136 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 154:37f96f9d4de2 137
<> 154:37f96f9d4de2 138 /* read back to make sure the configuration valid before enter stop mode */
<> 154:37f96f9d4de2 139 (void)base->PMCTRL;
<> 154:37f96f9d4de2 140 __DSB();
<> 154:37f96f9d4de2 141 __WFI();
<> 154:37f96f9d4de2 142 __ISB();
<> 154:37f96f9d4de2 143
<> 154:37f96f9d4de2 144 /* check whether the power mode enter Stop mode succeed */
<> 154:37f96f9d4de2 145 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
<> 154:37f96f9d4de2 146 {
<> 154:37f96f9d4de2 147 return kStatus_SMC_StopAbort;
<> 154:37f96f9d4de2 148 }
<> 154:37f96f9d4de2 149 else
<> 154:37f96f9d4de2 150 {
<> 154:37f96f9d4de2 151 return kStatus_Success;
<> 154:37f96f9d4de2 152 }
<> 154:37f96f9d4de2 153 }
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 status_t SMC_SetPowerModeVlpr(SMC_Type *base
<> 154:37f96f9d4de2 156 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
<> 154:37f96f9d4de2 157 ,
<> 154:37f96f9d4de2 158 bool wakeupMode
<> 154:37f96f9d4de2 159 #endif
<> 154:37f96f9d4de2 160 )
<> 154:37f96f9d4de2 161 {
<> 154:37f96f9d4de2 162 uint8_t reg;
<> 154:37f96f9d4de2 163
<> 154:37f96f9d4de2 164 reg = base->PMCTRL;
<> 154:37f96f9d4de2 165 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
<> 154:37f96f9d4de2 166 /* configure whether the system remains in VLP mode on an interrupt */
<> 154:37f96f9d4de2 167 if (wakeupMode)
<> 154:37f96f9d4de2 168 {
<> 154:37f96f9d4de2 169 /* exits to RUN mode on an interrupt */
<> 154:37f96f9d4de2 170 reg |= SMC_PMCTRL_LPWUI_MASK;
<> 154:37f96f9d4de2 171 }
<> 154:37f96f9d4de2 172 else
<> 154:37f96f9d4de2 173 {
<> 154:37f96f9d4de2 174 /* remains in VLP mode on an interrupt */
<> 154:37f96f9d4de2 175 reg &= ~SMC_PMCTRL_LPWUI_MASK;
<> 154:37f96f9d4de2 176 }
<> 154:37f96f9d4de2 177 #endif /* FSL_FEATURE_SMC_HAS_LPWUI */
<> 154:37f96f9d4de2 178
<> 154:37f96f9d4de2 179 /* configure VLPR mode */
<> 154:37f96f9d4de2 180 reg &= ~SMC_PMCTRL_RUNM_MASK;
<> 154:37f96f9d4de2 181 reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
<> 154:37f96f9d4de2 182 base->PMCTRL = reg;
<> 154:37f96f9d4de2 183
<> 154:37f96f9d4de2 184 return kStatus_Success;
<> 154:37f96f9d4de2 185 }
<> 154:37f96f9d4de2 186
<> 154:37f96f9d4de2 187 status_t SMC_SetPowerModeVlpw(SMC_Type *base)
<> 154:37f96f9d4de2 188 {
<> 154:37f96f9d4de2 189 /* configure VLPW mode */
<> 154:37f96f9d4de2 190 /* Set the SLEEPDEEP bit to enable deep sleep mode */
<> 154:37f96f9d4de2 191 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 154:37f96f9d4de2 192 __DSB();
<> 154:37f96f9d4de2 193 __WFI();
<> 154:37f96f9d4de2 194 __ISB();
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 return kStatus_Success;
<> 154:37f96f9d4de2 197 }
<> 154:37f96f9d4de2 198
<> 154:37f96f9d4de2 199 status_t SMC_SetPowerModeVlps(SMC_Type *base)
<> 154:37f96f9d4de2 200 {
<> 154:37f96f9d4de2 201 uint8_t reg;
<> 154:37f96f9d4de2 202
<> 154:37f96f9d4de2 203 /* configure VLPS mode */
<> 154:37f96f9d4de2 204 reg = base->PMCTRL;
<> 154:37f96f9d4de2 205 reg &= ~SMC_PMCTRL_STOPM_MASK;
<> 154:37f96f9d4de2 206 reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
<> 154:37f96f9d4de2 207 base->PMCTRL = reg;
<> 154:37f96f9d4de2 208
<> 154:37f96f9d4de2 209 /* Set the SLEEPDEEP bit to enable deep sleep mode */
<> 154:37f96f9d4de2 210 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 154:37f96f9d4de2 211
<> 154:37f96f9d4de2 212 /* read back to make sure the configuration valid before enter stop mode */
<> 154:37f96f9d4de2 213 (void)base->PMCTRL;
<> 154:37f96f9d4de2 214 __DSB();
<> 154:37f96f9d4de2 215 __WFI();
<> 154:37f96f9d4de2 216 __ISB();
<> 154:37f96f9d4de2 217
<> 154:37f96f9d4de2 218 /* check whether the power mode enter VLPS mode succeed */
<> 154:37f96f9d4de2 219 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
<> 154:37f96f9d4de2 220 {
<> 154:37f96f9d4de2 221 return kStatus_SMC_StopAbort;
<> 154:37f96f9d4de2 222 }
<> 154:37f96f9d4de2 223 else
<> 154:37f96f9d4de2 224 {
<> 154:37f96f9d4de2 225 return kStatus_Success;
<> 154:37f96f9d4de2 226 }
<> 154:37f96f9d4de2 227 }
<> 154:37f96f9d4de2 228
<> 154:37f96f9d4de2 229 #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
<> 154:37f96f9d4de2 230 status_t SMC_SetPowerModeLls(SMC_Type *base
<> 154:37f96f9d4de2 231 #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
<> 154:37f96f9d4de2 232 (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
<> 154:37f96f9d4de2 233 ,
<> 154:37f96f9d4de2 234 const smc_power_mode_lls_config_t *config
<> 154:37f96f9d4de2 235 #endif
<> 154:37f96f9d4de2 236 )
<> 154:37f96f9d4de2 237 {
<> 154:37f96f9d4de2 238 uint8_t reg;
<> 154:37f96f9d4de2 239
<> 154:37f96f9d4de2 240 /* configure to LLS mode */
<> 154:37f96f9d4de2 241 reg = base->PMCTRL;
<> 154:37f96f9d4de2 242 reg &= ~SMC_PMCTRL_STOPM_MASK;
<> 154:37f96f9d4de2 243 reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
<> 154:37f96f9d4de2 244 base->PMCTRL = reg;
<> 154:37f96f9d4de2 245
<> 154:37f96f9d4de2 246 /* configure LLS sub-mode*/
<> 154:37f96f9d4de2 247 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
<> 154:37f96f9d4de2 248 reg = base->STOPCTRL;
<> 154:37f96f9d4de2 249 reg &= ~SMC_STOPCTRL_LLSM_MASK;
<> 154:37f96f9d4de2 250 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
<> 154:37f96f9d4de2 251 base->STOPCTRL = reg;
<> 154:37f96f9d4de2 252 #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
<> 154:37f96f9d4de2 253
<> 154:37f96f9d4de2 254 #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
<> 154:37f96f9d4de2 255 if (config->enableLpoClock)
<> 154:37f96f9d4de2 256 {
<> 154:37f96f9d4de2 257 base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
<> 154:37f96f9d4de2 258 }
<> 154:37f96f9d4de2 259 else
<> 154:37f96f9d4de2 260 {
<> 154:37f96f9d4de2 261 base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
<> 154:37f96f9d4de2 262 }
<> 154:37f96f9d4de2 263 #endif /* FSL_FEATURE_SMC_HAS_LPOPO */
<> 154:37f96f9d4de2 264
<> 154:37f96f9d4de2 265 /* Set the SLEEPDEEP bit to enable deep sleep mode */
<> 154:37f96f9d4de2 266 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 154:37f96f9d4de2 267
<> 154:37f96f9d4de2 268 /* read back to make sure the configuration valid before enter stop mode */
<> 154:37f96f9d4de2 269 (void)base->PMCTRL;
<> 154:37f96f9d4de2 270 __DSB();
<> 154:37f96f9d4de2 271 __WFI();
<> 154:37f96f9d4de2 272 __ISB();
<> 154:37f96f9d4de2 273
<> 154:37f96f9d4de2 274 /* check whether the power mode enter LLS mode succeed */
<> 154:37f96f9d4de2 275 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
<> 154:37f96f9d4de2 276 {
<> 154:37f96f9d4de2 277 return kStatus_SMC_StopAbort;
<> 154:37f96f9d4de2 278 }
<> 154:37f96f9d4de2 279 else
<> 154:37f96f9d4de2 280 {
<> 154:37f96f9d4de2 281 return kStatus_Success;
<> 154:37f96f9d4de2 282 }
<> 154:37f96f9d4de2 283 }
<> 154:37f96f9d4de2 284 #endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
<> 154:37f96f9d4de2 285
<> 154:37f96f9d4de2 286 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
<> 154:37f96f9d4de2 287 status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config)
<> 154:37f96f9d4de2 288 {
<> 154:37f96f9d4de2 289 uint8_t reg;
<> 154:37f96f9d4de2 290
<> 154:37f96f9d4de2 291 #if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
<> 154:37f96f9d4de2 292 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \
<> 154:37f96f9d4de2 293 (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
<> 154:37f96f9d4de2 294 (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
<> 154:37f96f9d4de2 295 if (config->subMode == kSMC_StopSub0)
<> 154:37f96f9d4de2 296 #endif
<> 154:37f96f9d4de2 297 {
<> 154:37f96f9d4de2 298 /* configure whether the Por Detect work in Vlls0 mode */
<> 154:37f96f9d4de2 299 if (config->enablePorDetectInVlls0)
<> 154:37f96f9d4de2 300 {
<> 154:37f96f9d4de2 301 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
<> 154:37f96f9d4de2 302 base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK;
<> 154:37f96f9d4de2 303 #else
<> 154:37f96f9d4de2 304 base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK;
<> 154:37f96f9d4de2 305 #endif
<> 154:37f96f9d4de2 306 }
<> 154:37f96f9d4de2 307 else
<> 154:37f96f9d4de2 308 {
<> 154:37f96f9d4de2 309 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
<> 154:37f96f9d4de2 310 base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK;
<> 154:37f96f9d4de2 311 #else
<> 154:37f96f9d4de2 312 base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK;
<> 154:37f96f9d4de2 313 #endif
<> 154:37f96f9d4de2 314 }
<> 154:37f96f9d4de2 315 }
<> 154:37f96f9d4de2 316 #endif /* FSL_FEATURE_SMC_HAS_PORPO */
<> 154:37f96f9d4de2 317
<> 154:37f96f9d4de2 318 #if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
<> 154:37f96f9d4de2 319 else if (config->subMode == kSMC_StopSub2)
<> 154:37f96f9d4de2 320 {
<> 154:37f96f9d4de2 321 /* configure whether the Por Detect work in Vlls0 mode */
<> 154:37f96f9d4de2 322 if (config->enableRam2InVlls2)
<> 154:37f96f9d4de2 323 {
<> 154:37f96f9d4de2 324 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
<> 154:37f96f9d4de2 325 base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK;
<> 154:37f96f9d4de2 326 #else
<> 154:37f96f9d4de2 327 base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK;
<> 154:37f96f9d4de2 328 #endif
<> 154:37f96f9d4de2 329 }
<> 154:37f96f9d4de2 330 else
<> 154:37f96f9d4de2 331 {
<> 154:37f96f9d4de2 332 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
<> 154:37f96f9d4de2 333 base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK;
<> 154:37f96f9d4de2 334 #else
<> 154:37f96f9d4de2 335 base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK;
<> 154:37f96f9d4de2 336 #endif
<> 154:37f96f9d4de2 337 }
<> 154:37f96f9d4de2 338 }
<> 154:37f96f9d4de2 339 else
<> 154:37f96f9d4de2 340 {
<> 154:37f96f9d4de2 341 }
<> 154:37f96f9d4de2 342 #endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */
<> 154:37f96f9d4de2 343
<> 154:37f96f9d4de2 344 /* configure to VLLS mode */
<> 154:37f96f9d4de2 345 reg = base->PMCTRL;
<> 154:37f96f9d4de2 346 reg &= ~SMC_PMCTRL_STOPM_MASK;
<> 154:37f96f9d4de2 347 reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
<> 154:37f96f9d4de2 348 base->PMCTRL = reg;
<> 154:37f96f9d4de2 349
<> 154:37f96f9d4de2 350 /* configure the VLLS sub-mode */
<> 154:37f96f9d4de2 351 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
<> 154:37f96f9d4de2 352 reg = base->VLLSCTRL;
<> 154:37f96f9d4de2 353 reg &= ~SMC_VLLSCTRL_VLLSM_MASK;
<> 154:37f96f9d4de2 354 reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT);
<> 154:37f96f9d4de2 355 base->VLLSCTRL = reg;
<> 154:37f96f9d4de2 356 #else
<> 154:37f96f9d4de2 357 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
<> 154:37f96f9d4de2 358 reg = base->STOPCTRL;
<> 154:37f96f9d4de2 359 reg &= ~SMC_STOPCTRL_LLSM_MASK;
<> 154:37f96f9d4de2 360 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
<> 154:37f96f9d4de2 361 base->STOPCTRL = reg;
<> 154:37f96f9d4de2 362 #else
<> 154:37f96f9d4de2 363 reg = base->STOPCTRL;
<> 154:37f96f9d4de2 364 reg &= ~SMC_STOPCTRL_VLLSM_MASK;
<> 154:37f96f9d4de2 365 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT);
<> 154:37f96f9d4de2 366 base->STOPCTRL = reg;
<> 154:37f96f9d4de2 367 #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
<> 154:37f96f9d4de2 368 #endif
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
<> 154:37f96f9d4de2 371 if (config->enableLpoClock)
<> 154:37f96f9d4de2 372 {
<> 154:37f96f9d4de2 373 base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
<> 154:37f96f9d4de2 374 }
<> 154:37f96f9d4de2 375 else
<> 154:37f96f9d4de2 376 {
<> 154:37f96f9d4de2 377 base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
<> 154:37f96f9d4de2 378 }
<> 154:37f96f9d4de2 379 #endif /* FSL_FEATURE_SMC_HAS_LPOPO */
<> 154:37f96f9d4de2 380
<> 154:37f96f9d4de2 381 /* Set the SLEEPDEEP bit to enable deep sleep mode */
<> 154:37f96f9d4de2 382 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 154:37f96f9d4de2 383
<> 154:37f96f9d4de2 384 /* read back to make sure the configuration valid before enter stop mode */
<> 154:37f96f9d4de2 385 (void)base->PMCTRL;
<> 154:37f96f9d4de2 386 __DSB();
<> 154:37f96f9d4de2 387 __WFI();
<> 154:37f96f9d4de2 388 __ISB();
<> 154:37f96f9d4de2 389
<> 154:37f96f9d4de2 390 /* check whether the power mode enter LLS mode succeed */
<> 154:37f96f9d4de2 391 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
<> 154:37f96f9d4de2 392 {
<> 154:37f96f9d4de2 393 return kStatus_SMC_StopAbort;
<> 154:37f96f9d4de2 394 }
<> 154:37f96f9d4de2 395 else
<> 154:37f96f9d4de2 396 {
<> 154:37f96f9d4de2 397 return kStatus_Success;
<> 154:37f96f9d4de2 398 }
<> 154:37f96f9d4de2 399 }
<> 154:37f96f9d4de2 400 #endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */