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targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * DISCLAIMER
<> 144:ef7eb2e8f9f7 3 * This software is supplied by Renesas Electronics Corporation and is only
<> 144:ef7eb2e8f9f7 4 * intended for use with Renesas products. No other uses are authorized. This
<> 144:ef7eb2e8f9f7 5 * software is owned by Renesas Electronics Corporation and is protected under
<> 144:ef7eb2e8f9f7 6 * all applicable laws, including copyright laws.
<> 144:ef7eb2e8f9f7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
<> 144:ef7eb2e8f9f7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
<> 144:ef7eb2e8f9f7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
<> 144:ef7eb2e8f9f7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
<> 144:ef7eb2e8f9f7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
<> 144:ef7eb2e8f9f7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
<> 144:ef7eb2e8f9f7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
<> 144:ef7eb2e8f9f7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
<> 144:ef7eb2e8f9f7 16 * Renesas reserves the right, without notice, to make changes to this software
<> 144:ef7eb2e8f9f7 17 * and to discontinue the availability of this software. By using this software,
<> 144:ef7eb2e8f9f7 18 * you agree to the additional terms and conditions found by accessing the
<> 144:ef7eb2e8f9f7 19 * following link:
<> 144:ef7eb2e8f9f7 20 * http://www.renesas.com/disclaimer
<> 144:ef7eb2e8f9f7 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
<> 144:ef7eb2e8f9f7 22 *******************************************************************************/
<> 144:ef7eb2e8f9f7 23 /*******************************************************************************
<> 144:ef7eb2e8f9f7 24 * File Name : ostm_iobitmask.h
<> 144:ef7eb2e8f9f7 25 * $Rev: 1115 $
<> 144:ef7eb2e8f9f7 26 * $Date:: 2014-07-09 15:35:02 +0900#$
<> 144:ef7eb2e8f9f7 27 * Description : OSTM register define header
<> 144:ef7eb2e8f9f7 28 *******************************************************************************/
<> 144:ef7eb2e8f9f7 29 #ifndef OSTM_IOBITMASK_H
<> 144:ef7eb2e8f9f7 30 #define OSTM_IOBITMASK_H
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /* ==== Mask values for IO registers ==== */
<> 144:ef7eb2e8f9f7 34 /* ---- OSTM0 ---- */
<> 144:ef7eb2e8f9f7 35 #define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #define OSTM0_OSTMnTE_OSTMnTE (0x01u)
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #define OSTM0_OSTMnTS_OSTMnTS (0x01u)
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #define OSTM0_OSTMnTT_OSTMnTT (0x01u)
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #define OSTM0_OSTMnCTL_MD0 (0x00000001uL)
<> 144:ef7eb2e8f9f7 46 #define OSTM0_OSTMnCTL_MD1 (0x00000002uL)
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* ---- OSTM1 ---- */
<> 144:ef7eb2e8f9f7 49 #define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #define OSTM1_OSTMnTE_OSTMnTE (0x01u)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #define OSTM1_OSTMnTS_OSTMnTS (0x01u)
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 #define OSTM1_OSTMnTT_OSTMnTT (0x01u)
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 #define OSTM1_OSTMnCTL_MD0 (0x00000001uL)
<> 144:ef7eb2e8f9f7 60 #define OSTM1_OSTMnCTL_MD1 (0x00000002uL)
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* ---- OSTMn ---- */
<> 144:ef7eb2e8f9f7 63 #define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 #define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 #define OSTMn_OSTMnTE_OSTMnTE (0x01u)
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #define OSTMn_OSTMnTS_OSTMnTS (0x01u)
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 #define OSTMn_OSTMnTT_OSTMnTT (0x01u)
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #define OSTMn_OSTMnCTL_MD0 (0x00000001uL)
<> 144:ef7eb2e8f9f7 74 #define OSTMn_OSTMnCTL_MD1 (0x00000002uL)
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* ==== Shift values for IO registers ==== */
<> 144:ef7eb2e8f9f7 78 /* ---- OSTM0 ---- */
<> 144:ef7eb2e8f9f7 79 #define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u)
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u)
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u)
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u)
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u)
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #define OSTM0_OSTMnCTL_MD0_SHIFT (0u)
<> 144:ef7eb2e8f9f7 90 #define OSTM0_OSTMnCTL_MD1_SHIFT (1u)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* ---- OSTM1 ---- */
<> 144:ef7eb2e8f9f7 93 #define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u)
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u)
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u)
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u)
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u)
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #define OSTM1_OSTMnCTL_MD0_SHIFT (0u)
<> 144:ef7eb2e8f9f7 104 #define OSTM1_OSTMnCTL_MD1_SHIFT (1u)
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* ---- OSTMn ---- */
<> 144:ef7eb2e8f9f7 107 #define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u)
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 #define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u)
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u)
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u)
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u)
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #define OSTMn_OSTMnCTL_MD0_SHIFT (0u)
<> 144:ef7eb2e8f9f7 118 #define OSTMn_OSTMnCTL_MD1_SHIFT (1u)
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #endif /* OSTM_IOBITMASK_H */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* End of File */