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Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC176X/i2c_api.c@37:e784a2d7291a, 2015-12-14 (annotated)

Committer:
mbed_official
Date:
Mon Dec 14 08:45:10 2015 +0000
Revision:
37:e784a2d7291a
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision eed91bce3bf5c845b4e99272116989b82f7bea99



Full URL: https://github.com/mbedmicro/mbed/commit/eed91bce3bf5c845b4e99272116989b82f7bea99/



Issue #666  LPC1768 i2c_slave_read fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 17 #include "i2c_api.h"
bogdanm 0:9b334a45a8ff 18 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 19 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 static const PinMap PinMap_I2C_SDA[] = {
bogdanm 0:9b334a45a8ff 22 {P0_0 , I2C_1, 3},
bogdanm 0:9b334a45a8ff 23 {P0_10, I2C_2, 2},
bogdanm 0:9b334a45a8ff 24 {P0_19, I2C_1, 3},
bogdanm 0:9b334a45a8ff 25 {P0_27, I2C_0, 1},
bogdanm 0:9b334a45a8ff 26 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 27 };
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 static const PinMap PinMap_I2C_SCL[] = {
bogdanm 0:9b334a45a8ff 30 {P0_1 , I2C_1, 3},
bogdanm 0:9b334a45a8ff 31 {P0_11, I2C_2, 2},
bogdanm 0:9b334a45a8ff 32 {P0_20, I2C_1, 3},
bogdanm 0:9b334a45a8ff 33 {P0_28, I2C_0, 1},
bogdanm 0:9b334a45a8ff 34 {NC , NC, 0}
bogdanm 0:9b334a45a8ff 35 };
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #define I2C_CONSET(x) (x->i2c->I2CONSET)
bogdanm 0:9b334a45a8ff 38 #define I2C_CONCLR(x) (x->i2c->I2CONCLR)
bogdanm 0:9b334a45a8ff 39 #define I2C_STAT(x) (x->i2c->I2STAT)
bogdanm 0:9b334a45a8ff 40 #define I2C_DAT(x) (x->i2c->I2DAT)
bogdanm 0:9b334a45a8ff 41 #define I2C_SCLL(x, val) (x->i2c->I2SCLL = val)
bogdanm 0:9b334a45a8ff 42 #define I2C_SCLH(x, val) (x->i2c->I2SCLH = val)
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 static const uint32_t I2C_addr_offset[2][4] = {
bogdanm 0:9b334a45a8ff 45 {0x0C, 0x20, 0x24, 0x28},
bogdanm 0:9b334a45a8ff 46 {0x30, 0x34, 0x38, 0x3C}
bogdanm 0:9b334a45a8ff 47 };
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
bogdanm 0:9b334a45a8ff 50 I2C_CONCLR(obj) = (start << 5)
bogdanm 0:9b334a45a8ff 51 | (stop << 4)
bogdanm 0:9b334a45a8ff 52 | (interrupt << 3)
bogdanm 0:9b334a45a8ff 53 | (acknowledge << 2);
bogdanm 0:9b334a45a8ff 54 }
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
bogdanm 0:9b334a45a8ff 57 I2C_CONSET(obj) = (start << 5)
bogdanm 0:9b334a45a8ff 58 | (stop << 4)
bogdanm 0:9b334a45a8ff 59 | (interrupt << 3)
bogdanm 0:9b334a45a8ff 60 | (acknowledge << 2);
bogdanm 0:9b334a45a8ff 61 }
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 // Clear the Serial Interrupt (SI)
bogdanm 0:9b334a45a8ff 64 static inline void i2c_clear_SI(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 65 i2c_conclr(obj, 0, 0, 1, 0);
bogdanm 0:9b334a45a8ff 66 }
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 static inline int i2c_status(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 69 return I2C_STAT(obj);
bogdanm 0:9b334a45a8ff 70 }
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 // Wait until the Serial Interrupt (SI) is set
bogdanm 0:9b334a45a8ff 73 static int i2c_wait_SI(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 74 int timeout = 0;
bogdanm 0:9b334a45a8ff 75 while (!(I2C_CONSET(obj) & (1 << 3))) {
bogdanm 0:9b334a45a8ff 76 timeout++;
bogdanm 0:9b334a45a8ff 77 if (timeout > 100000) return -1;
bogdanm 0:9b334a45a8ff 78 }
bogdanm 0:9b334a45a8ff 79 return 0;
bogdanm 0:9b334a45a8ff 80 }
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 static inline void i2c_interface_enable(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 83 I2C_CONSET(obj) = 0x40;
bogdanm 0:9b334a45a8ff 84 }
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 static inline void i2c_power_enable(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 87 switch ((int)obj->i2c) {
bogdanm 0:9b334a45a8ff 88 case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
bogdanm 0:9b334a45a8ff 89 case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
bogdanm 0:9b334a45a8ff 90 case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
bogdanm 0:9b334a45a8ff 91 }
bogdanm 0:9b334a45a8ff 92 }
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
bogdanm 0:9b334a45a8ff 95 // determine the SPI to use
bogdanm 0:9b334a45a8ff 96 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
bogdanm 0:9b334a45a8ff 97 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
bogdanm 0:9b334a45a8ff 98 obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
bogdanm 0:9b334a45a8ff 99 MBED_ASSERT((int)obj->i2c != NC);
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 // enable power
bogdanm 0:9b334a45a8ff 102 i2c_power_enable(obj);
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 // set default frequency at 100k
bogdanm 0:9b334a45a8ff 105 i2c_frequency(obj, 100000);
bogdanm 0:9b334a45a8ff 106 i2c_conclr(obj, 1, 1, 1, 1);
bogdanm 0:9b334a45a8ff 107 i2c_interface_enable(obj);
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 pinmap_pinout(sda, PinMap_I2C_SDA);
bogdanm 0:9b334a45a8ff 110 pinmap_pinout(scl, PinMap_I2C_SCL);
bogdanm 0:9b334a45a8ff 111 }
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 inline int i2c_start(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 114 int status = 0;
bogdanm 0:9b334a45a8ff 115 // 8.1 Before master mode can be entered, I2CON must be initialised to:
bogdanm 0:9b334a45a8ff 116 // - I2EN STA STO SI AA - -
bogdanm 0:9b334a45a8ff 117 // - 1 0 0 0 x - -
bogdanm 0:9b334a45a8ff 118 // if AA = 0, it can't enter slave mode
bogdanm 0:9b334a45a8ff 119 i2c_conclr(obj, 1, 1, 1, 1);
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 // The master mode may now be entered by setting the STA bit
bogdanm 0:9b334a45a8ff 122 // this will generate a start condition when the bus becomes free
bogdanm 0:9b334a45a8ff 123 i2c_conset(obj, 1, 0, 0, 1);
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 i2c_wait_SI(obj);
bogdanm 0:9b334a45a8ff 126 status = i2c_status(obj);
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 // Clear start bit now transmitted, and interrupt bit
bogdanm 0:9b334a45a8ff 129 i2c_conclr(obj, 1, 0, 0, 0);
bogdanm 0:9b334a45a8ff 130 return status;
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 inline int i2c_stop(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 134 int timeout = 0;
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 // write the stop bit
bogdanm 0:9b334a45a8ff 137 i2c_conset(obj, 0, 1, 0, 0);
bogdanm 0:9b334a45a8ff 138 i2c_clear_SI(obj);
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 // wait for STO bit to reset
bogdanm 0:9b334a45a8ff 141 while(I2C_CONSET(obj) & (1 << 4)) {
bogdanm 0:9b334a45a8ff 142 timeout ++;
bogdanm 0:9b334a45a8ff 143 if (timeout > 100000) return 1;
bogdanm 0:9b334a45a8ff 144 }
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 return 0;
bogdanm 0:9b334a45a8ff 147 }
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
bogdanm 0:9b334a45a8ff 150 // write the data
bogdanm 0:9b334a45a8ff 151 I2C_DAT(obj) = value;
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 // clear SI to init a send
bogdanm 0:9b334a45a8ff 154 i2c_clear_SI(obj);
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 // wait and return status
bogdanm 0:9b334a45a8ff 157 i2c_wait_SI(obj);
bogdanm 0:9b334a45a8ff 158 return i2c_status(obj);
bogdanm 0:9b334a45a8ff 159 }
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 static inline int i2c_do_read(i2c_t *obj, int last) {
bogdanm 0:9b334a45a8ff 162 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
bogdanm 0:9b334a45a8ff 163 if(last) {
bogdanm 0:9b334a45a8ff 164 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
bogdanm 0:9b334a45a8ff 165 } else {
bogdanm 0:9b334a45a8ff 166 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
bogdanm 0:9b334a45a8ff 167 }
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 // accept byte
bogdanm 0:9b334a45a8ff 170 i2c_clear_SI(obj);
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 // wait for it to arrive
bogdanm 0:9b334a45a8ff 173 i2c_wait_SI(obj);
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 // return the data
bogdanm 0:9b334a45a8ff 176 return (I2C_DAT(obj) & 0xFF);
bogdanm 0:9b334a45a8ff 177 }
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 void i2c_frequency(i2c_t *obj, int hz) {
bogdanm 0:9b334a45a8ff 180 // [TODO] set pclk to /4
bogdanm 0:9b334a45a8ff 181 uint32_t PCLK = SystemCoreClock / 4;
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 uint32_t pulse = PCLK / (hz * 2);
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 // I2C Rate
bogdanm 0:9b334a45a8ff 186 I2C_SCLL(obj, pulse);
bogdanm 0:9b334a45a8ff 187 I2C_SCLH(obj, pulse);
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 // The I2C does a read or a write as a whole operation
bogdanm 0:9b334a45a8ff 191 // There are two types of error conditions it can encounter
bogdanm 0:9b334a45a8ff 192 // 1) it can not obtain the bus
bogdanm 0:9b334a45a8ff 193 // 2) it gets error responses at part of the transmission
bogdanm 0:9b334a45a8ff 194 //
bogdanm 0:9b334a45a8ff 195 // We tackle them as follows:
bogdanm 0:9b334a45a8ff 196 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
bogdanm 0:9b334a45a8ff 197 // which basically turns it in to a 2)
bogdanm 0:9b334a45a8ff 198 // 2) on error, we use the standard error mechanisms to report/debug
bogdanm 0:9b334a45a8ff 199 //
bogdanm 0:9b334a45a8ff 200 // Therefore an I2C transaction should always complete. If it doesn't it is usually
bogdanm 0:9b334a45a8ff 201 // because something is setup wrong (e.g. wiring), and we don't need to programatically
bogdanm 0:9b334a45a8ff 202 // check for that
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
bogdanm 0:9b334a45a8ff 205 int count, status;
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 status = i2c_start(obj);
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 if ((status != 0x10) && (status != 0x08)) {
bogdanm 0:9b334a45a8ff 210 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 211 return I2C_ERROR_BUS_BUSY;
bogdanm 0:9b334a45a8ff 212 }
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 status = i2c_do_write(obj, (address | 0x01), 1);
bogdanm 0:9b334a45a8ff 215 if (status != 0x40) {
bogdanm 0:9b334a45a8ff 216 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 217 return I2C_ERROR_NO_SLAVE;
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 // Read in all except last byte
bogdanm 0:9b334a45a8ff 221 for (count = 0; count < (length - 1); count++) {
bogdanm 0:9b334a45a8ff 222 int value = i2c_do_read(obj, 0);
bogdanm 0:9b334a45a8ff 223 status = i2c_status(obj);
bogdanm 0:9b334a45a8ff 224 if (status != 0x50) {
bogdanm 0:9b334a45a8ff 225 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 226 return count;
bogdanm 0:9b334a45a8ff 227 }
bogdanm 0:9b334a45a8ff 228 data[count] = (char) value;
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 // read in last byte
bogdanm 0:9b334a45a8ff 232 int value = i2c_do_read(obj, 1);
bogdanm 0:9b334a45a8ff 233 status = i2c_status(obj);
bogdanm 0:9b334a45a8ff 234 if (status != 0x58) {
bogdanm 0:9b334a45a8ff 235 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 236 return length - 1;
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 data[count] = (char) value;
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 // If not repeated start, send stop.
bogdanm 0:9b334a45a8ff 242 if (stop) {
bogdanm 0:9b334a45a8ff 243 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 244 }
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 return length;
bogdanm 0:9b334a45a8ff 247 }
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
bogdanm 0:9b334a45a8ff 250 int i, status;
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 status = i2c_start(obj);
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 if ((status != 0x10) && (status != 0x08)) {
bogdanm 0:9b334a45a8ff 255 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 256 return I2C_ERROR_BUS_BUSY;
bogdanm 0:9b334a45a8ff 257 }
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 status = i2c_do_write(obj, (address & 0xFE), 1);
bogdanm 0:9b334a45a8ff 260 if (status != 0x18) {
bogdanm 0:9b334a45a8ff 261 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 262 return I2C_ERROR_NO_SLAVE;
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 for (i=0; i<length; i++) {
bogdanm 0:9b334a45a8ff 266 status = i2c_do_write(obj, data[i], 0);
bogdanm 0:9b334a45a8ff 267 if(status != 0x28) {
bogdanm 0:9b334a45a8ff 268 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 269 return i;
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271 }
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
bogdanm 0:9b334a45a8ff 274 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
bogdanm 0:9b334a45a8ff 275 // i2c_clear_SI(obj);
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 // If not repeated start, send stop.
bogdanm 0:9b334a45a8ff 278 if (stop) {
bogdanm 0:9b334a45a8ff 279 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 return length;
bogdanm 0:9b334a45a8ff 283 }
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 void i2c_reset(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 286 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 int i2c_byte_read(i2c_t *obj, int last) {
bogdanm 0:9b334a45a8ff 290 return (i2c_do_read(obj, last) & 0xFF);
bogdanm 0:9b334a45a8ff 291 }
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 int i2c_byte_write(i2c_t *obj, int data) {
bogdanm 0:9b334a45a8ff 294 int ack;
bogdanm 0:9b334a45a8ff 295 int status = i2c_do_write(obj, (data & 0xFF), 0);
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 switch(status) {
bogdanm 0:9b334a45a8ff 298 case 0x18: case 0x28: // Master transmit ACKs
bogdanm 0:9b334a45a8ff 299 ack = 1;
bogdanm 0:9b334a45a8ff 300 break;
bogdanm 0:9b334a45a8ff 301 case 0x40: // Master receive address transmitted ACK
bogdanm 0:9b334a45a8ff 302 ack = 1;
bogdanm 0:9b334a45a8ff 303 break;
bogdanm 0:9b334a45a8ff 304 case 0xB8: // Slave transmit ACK
bogdanm 0:9b334a45a8ff 305 ack = 1;
bogdanm 0:9b334a45a8ff 306 break;
bogdanm 0:9b334a45a8ff 307 default:
bogdanm 0:9b334a45a8ff 308 ack = 0;
bogdanm 0:9b334a45a8ff 309 break;
bogdanm 0:9b334a45a8ff 310 }
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 return ack;
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
bogdanm 0:9b334a45a8ff 316 if (enable_slave != 0) {
bogdanm 0:9b334a45a8ff 317 i2c_conclr(obj, 1, 1, 1, 0);
bogdanm 0:9b334a45a8ff 318 i2c_conset(obj, 0, 0, 0, 1);
bogdanm 0:9b334a45a8ff 319 } else {
bogdanm 0:9b334a45a8ff 320 i2c_conclr(obj, 1, 1, 1, 1);
bogdanm 0:9b334a45a8ff 321 }
bogdanm 0:9b334a45a8ff 322 }
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 int i2c_slave_receive(i2c_t *obj) {
bogdanm 0:9b334a45a8ff 325 int status;
bogdanm 0:9b334a45a8ff 326 int retval;
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 status = i2c_status(obj);
bogdanm 0:9b334a45a8ff 329 switch(status) {
bogdanm 0:9b334a45a8ff 330 case 0x60: retval = 3; break;
bogdanm 0:9b334a45a8ff 331 case 0x70: retval = 2; break;
bogdanm 0:9b334a45a8ff 332 case 0xA8: retval = 1; break;
bogdanm 0:9b334a45a8ff 333 default : retval = 0; break;
bogdanm 0:9b334a45a8ff 334 }
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 return(retval);
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 int i2c_slave_read(i2c_t *obj, char *data, int length) {
bogdanm 0:9b334a45a8ff 340 int count = 0;
bogdanm 0:9b334a45a8ff 341 int status;
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 do {
bogdanm 0:9b334a45a8ff 344 i2c_clear_SI(obj);
bogdanm 0:9b334a45a8ff 345 i2c_wait_SI(obj);
bogdanm 0:9b334a45a8ff 346 status = i2c_status(obj);
bogdanm 0:9b334a45a8ff 347 if((status == 0x80) || (status == 0x90)) {
bogdanm 0:9b334a45a8ff 348 data[count] = I2C_DAT(obj) & 0xFF;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350 count++;
bogdanm 0:9b334a45a8ff 351 } while (((status == 0x80) || (status == 0x90) ||
bogdanm 0:9b334a45a8ff 352 (status == 0x060) || (status == 0x70)) && (count < length));
mbed_official 37:e784a2d7291a 353
mbed_official 37:e784a2d7291a 354 // Clear old status and wait for Serial Interrupt.
mbed_official 37:e784a2d7291a 355 i2c_clear_SI(obj);
mbed_official 37:e784a2d7291a 356 i2c_wait_SI(obj);
mbed_official 37:e784a2d7291a 357
mbed_official 37:e784a2d7291a 358 // Obtain new status.
mbed_official 37:e784a2d7291a 359 status = i2c_status(obj);
mbed_official 37:e784a2d7291a 360
bogdanm 0:9b334a45a8ff 361 if(status != 0xA0) {
bogdanm 0:9b334a45a8ff 362 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 363 }
mbed_official 37:e784a2d7291a 364
bogdanm 0:9b334a45a8ff 365 i2c_clear_SI(obj);
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 return count;
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
bogdanm 0:9b334a45a8ff 371 int count = 0;
bogdanm 0:9b334a45a8ff 372 int status;
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 if(length <= 0) {
bogdanm 0:9b334a45a8ff 375 return(0);
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 do {
bogdanm 0:9b334a45a8ff 379 status = i2c_do_write(obj, data[count], 0);
bogdanm 0:9b334a45a8ff 380 count++;
bogdanm 0:9b334a45a8ff 381 } while ((count < length) && (status == 0xB8));
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 if ((status != 0xC0) && (status != 0xC8)) {
bogdanm 0:9b334a45a8ff 384 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 i2c_clear_SI(obj);
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 return(count);
bogdanm 0:9b334a45a8ff 390 }
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
bogdanm 0:9b334a45a8ff 393 uint32_t addr;
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 if ((idx >= 0) && (idx <= 3)) {
bogdanm 0:9b334a45a8ff 396 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
bogdanm 0:9b334a45a8ff 397 *((uint32_t *) addr) = address & 0xFF;
bogdanm 0:9b334a45a8ff 398 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
bogdanm 0:9b334a45a8ff 399 *((uint32_t *) addr) = mask & 0xFE;
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401 }