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Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h@161:bd0311f1ad86, 2017-05-27 (annotated)

Committer:
tonnyleonard
Date:
Sat May 27 01:26:18 2017 +0000
Revision:
161:bd0311f1ad86
Parent:
150:02e0a0aed4ec 
Testing ADC with shunt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**************************************************************************//**
<> 150:02e0a0aed4ec 2 * @file efm32zg222f16.h
<> 150:02e0a0aed4ec 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 150:02e0a0aed4ec 4 * for EFM32ZG222F16
<> 150:02e0a0aed4ec 5 * @version 5.0.0
<> 150:02e0a0aed4ec 6 ******************************************************************************
<> 150:02e0a0aed4ec 7 * @section License
<> 150:02e0a0aed4ec 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 150:02e0a0aed4ec 9 ******************************************************************************
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * Permission is granted to anyone to use this software for any purpose,
<> 150:02e0a0aed4ec 12 * including commercial applications, and to alter it and redistribute it
<> 150:02e0a0aed4ec 13 * freely, subject to the following restrictions:
<> 150:02e0a0aed4ec 14 *
<> 150:02e0a0aed4ec 15 * 1. The origin of this software must not be misrepresented; you must not
<> 150:02e0a0aed4ec 16 * claim that you wrote the original software.@n
<> 150:02e0a0aed4ec 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 150:02e0a0aed4ec 18 * misrepresented as being the original software.@n
<> 150:02e0a0aed4ec 19 * 3. This notice may not be removed or altered from any source distribution.
<> 150:02e0a0aed4ec 20 *
<> 150:02e0a0aed4ec 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 150:02e0a0aed4ec 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 150:02e0a0aed4ec 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 150:02e0a0aed4ec 24 * kind, including, but not limited to, any implied warranties of
<> 150:02e0a0aed4ec 25 * merchantability or fitness for any particular purpose or warranties against
<> 150:02e0a0aed4ec 26 * infringement of any proprietary rights of a third party.
<> 150:02e0a0aed4ec 27 *
<> 150:02e0a0aed4ec 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 150:02e0a0aed4ec 29 * incidental, or special damages, or any other relief, or for any claim by
<> 150:02e0a0aed4ec 30 * any third party, arising from your use of this Software.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 *****************************************************************************/
<> 150:02e0a0aed4ec 33
<> 150:02e0a0aed4ec 34 #ifndef EFM32ZG222F16_H
<> 150:02e0a0aed4ec 35 #define EFM32ZG222F16_H
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 #ifdef __cplusplus
<> 150:02e0a0aed4ec 38 extern "C" {
<> 150:02e0a0aed4ec 39 #endif
<> 150:02e0a0aed4ec 40
<> 150:02e0a0aed4ec 41 /**************************************************************************//**
<> 150:02e0a0aed4ec 42 * @addtogroup Parts
<> 150:02e0a0aed4ec 43 * @{
<> 150:02e0a0aed4ec 44 *****************************************************************************/
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 /**************************************************************************//**
<> 150:02e0a0aed4ec 47 * @defgroup EFM32ZG222F16 EFM32ZG222F16
<> 150:02e0a0aed4ec 48 * @{
<> 150:02e0a0aed4ec 49 *****************************************************************************/
<> 150:02e0a0aed4ec 50
<> 150:02e0a0aed4ec 51 /** Interrupt Number Definition */
<> 150:02e0a0aed4ec 52 typedef enum IRQn
<> 150:02e0a0aed4ec 53 {
<> 150:02e0a0aed4ec 54 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
<> 150:02e0a0aed4ec 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */
<> 150:02e0a0aed4ec 56 HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */
<> 150:02e0a0aed4ec 57 SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */
<> 150:02e0a0aed4ec 58 PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */
<> 150:02e0a0aed4ec 59 SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */
<> 150:02e0a0aed4ec 60
<> 150:02e0a0aed4ec 61 /****** EFM32ZG Peripheral Interrupt Numbers ********************************************/
<> 150:02e0a0aed4ec 62 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
<> 150:02e0a0aed4ec 63 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
<> 150:02e0a0aed4ec 64 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
<> 150:02e0a0aed4ec 65 ACMP0_IRQn = 3, /*!< 3 EFM32 ACMP0 Interrupt */
<> 150:02e0a0aed4ec 66 ADC0_IRQn = 4, /*!< 4 EFM32 ADC0 Interrupt */
<> 150:02e0a0aed4ec 67 I2C0_IRQn = 5, /*!< 5 EFM32 I2C0 Interrupt */
<> 150:02e0a0aed4ec 68 GPIO_ODD_IRQn = 6, /*!< 6 EFM32 GPIO_ODD Interrupt */
<> 150:02e0a0aed4ec 69 TIMER1_IRQn = 7, /*!< 7 EFM32 TIMER1 Interrupt */
<> 150:02e0a0aed4ec 70 USART1_RX_IRQn = 8, /*!< 8 EFM32 USART1_RX Interrupt */
<> 150:02e0a0aed4ec 71 USART1_TX_IRQn = 9, /*!< 9 EFM32 USART1_TX Interrupt */
<> 150:02e0a0aed4ec 72 LEUART0_IRQn = 10, /*!< 10 EFM32 LEUART0 Interrupt */
<> 150:02e0a0aed4ec 73 PCNT0_IRQn = 11, /*!< 11 EFM32 PCNT0 Interrupt */
<> 150:02e0a0aed4ec 74 RTC_IRQn = 12, /*!< 12 EFM32 RTC Interrupt */
<> 150:02e0a0aed4ec 75 CMU_IRQn = 13, /*!< 13 EFM32 CMU Interrupt */
<> 150:02e0a0aed4ec 76 VCMP_IRQn = 14, /*!< 14 EFM32 VCMP Interrupt */
<> 150:02e0a0aed4ec 77 MSC_IRQn = 15, /*!< 15 EFM32 MSC Interrupt */
<> 150:02e0a0aed4ec 78 AES_IRQn = 16, /*!< 16 EFM32 AES Interrupt */
<> 150:02e0a0aed4ec 79 } IRQn_Type;
<> 150:02e0a0aed4ec 80
<> 150:02e0a0aed4ec 81 /**************************************************************************//**
<> 150:02e0a0aed4ec 82 * @defgroup EFM32ZG222F16_Core EFM32ZG222F16 Core
<> 150:02e0a0aed4ec 83 * @{
<> 150:02e0a0aed4ec 84 * @brief Processor and Core Peripheral Section
<> 150:02e0a0aed4ec 85 *****************************************************************************/
<> 150:02e0a0aed4ec 86 #define __MPU_PRESENT 0 /**< MPU not present */
<> 150:02e0a0aed4ec 87 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 150:02e0a0aed4ec 88 #define __NVIC_PRIO_BITS 2 /**< NVIC interrupt priority bits */
<> 150:02e0a0aed4ec 89 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 150:02e0a0aed4ec 90
<> 150:02e0a0aed4ec 91 /** @} End of group EFM32ZG222F16_Core */
<> 150:02e0a0aed4ec 92
<> 150:02e0a0aed4ec 93 /**************************************************************************//**
<> 150:02e0a0aed4ec 94 * @defgroup EFM32ZG222F16_Part EFM32ZG222F16 Part
<> 150:02e0a0aed4ec 95 * @{
<> 150:02e0a0aed4ec 96 ******************************************************************************/
<> 150:02e0a0aed4ec 97
<> 150:02e0a0aed4ec 98 /** Part family */
<> 150:02e0a0aed4ec 99 #define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */
<> 150:02e0a0aed4ec 100 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 150:02e0a0aed4ec 101 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 102 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
<> 150:02e0a0aed4ec 103 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 104 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
<> 150:02e0a0aed4ec 105
<> 150:02e0a0aed4ec 106 /* If part number is not defined as compiler option, define it */
<> 150:02e0a0aed4ec 107 #if !defined(EFM32ZG222F16)
<> 150:02e0a0aed4ec 108 #define EFM32ZG222F16 1 /**< Zero Gecko Part */
<> 150:02e0a0aed4ec 109 #endif
<> 150:02e0a0aed4ec 110
<> 150:02e0a0aed4ec 111 /** Configure part number */
<> 150:02e0a0aed4ec 112 #define PART_NUMBER "EFM32ZG222F16" /**< Part Number */
<> 150:02e0a0aed4ec 113
<> 150:02e0a0aed4ec 114 /** Memory Base addresses and limits */
<> 150:02e0a0aed4ec 115 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
<> 150:02e0a0aed4ec 116 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 150:02e0a0aed4ec 117 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
<> 150:02e0a0aed4ec 118 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 150:02e0a0aed4ec 119 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 120 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
<> 150:02e0a0aed4ec 121 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
<> 150:02e0a0aed4ec 122 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
<> 150:02e0a0aed4ec 123 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 150:02e0a0aed4ec 124 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
<> 150:02e0a0aed4ec 125 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
<> 150:02e0a0aed4ec 126 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 150:02e0a0aed4ec 127 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 150:02e0a0aed4ec 128 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
<> 150:02e0a0aed4ec 129 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
<> 150:02e0a0aed4ec 130 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
<> 150:02e0a0aed4ec 131 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 150:02e0a0aed4ec 132 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
<> 150:02e0a0aed4ec 133 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
<> 150:02e0a0aed4ec 134 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
<> 150:02e0a0aed4ec 135
<> 150:02e0a0aed4ec 136 /** Flash and SRAM limits for EFM32ZG222F16 */
<> 150:02e0a0aed4ec 137 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 150:02e0a0aed4ec 138 #define FLASH_SIZE (0x00004000UL) /**< Available Flash Memory */
<> 150:02e0a0aed4ec 139 #define FLASH_PAGE_SIZE 1024 /**< Flash Memory page size */
<> 150:02e0a0aed4ec 140 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 150:02e0a0aed4ec 141 #define SRAM_SIZE (0x00001000UL) /**< Available SRAM Memory */
<> 150:02e0a0aed4ec 142 #define __CM0PLUS_REV 0x001 /**< Cortex-M0+ Core revision r0p1 */
<> 150:02e0a0aed4ec 143 #define PRS_CHAN_COUNT 4 /**< Number of PRS channels */
<> 150:02e0a0aed4ec 144 #define DMA_CHAN_COUNT 4 /**< Number of DMA channels */
<> 150:02e0a0aed4ec 145 #define EXT_IRQ_COUNT 19 /**< Number of External (NVIC) interrupts */
<> 150:02e0a0aed4ec 146
<> 150:02e0a0aed4ec 147 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 150:02e0a0aed4ec 148 #define AFCHAN_MAX 33
<> 150:02e0a0aed4ec 149 #define AFCHANLOC_MAX 7
<> 150:02e0a0aed4ec 150 /** Analog AF channels */
<> 150:02e0a0aed4ec 151 #define AFACHAN_MAX 25
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 /* Part number capabilities */
<> 150:02e0a0aed4ec 154
<> 150:02e0a0aed4ec 155 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 150:02e0a0aed4ec 156 #define TIMER_COUNT 2 /**< 2 TIMERs available */
<> 150:02e0a0aed4ec 157 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 150:02e0a0aed4ec 158 #define ACMP_COUNT 1 /**< 1 ACMPs available */
<> 150:02e0a0aed4ec 159 #define USART_PRESENT /**< USART is available in this part */
<> 150:02e0a0aed4ec 160 #define USART_COUNT 1 /**< 1 USARTs available */
<> 150:02e0a0aed4ec 161 #define IDAC_PRESENT /**< IDAC is available in this part */
<> 150:02e0a0aed4ec 162 #define IDAC_COUNT 1 /**< 1 IDACs available */
<> 150:02e0a0aed4ec 163 #define ADC_PRESENT /**< ADC is available in this part */
<> 150:02e0a0aed4ec 164 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 150:02e0a0aed4ec 165 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 150:02e0a0aed4ec 166 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
<> 150:02e0a0aed4ec 167 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 150:02e0a0aed4ec 168 #define PCNT_COUNT 1 /**< 1 PCNTs available */
<> 150:02e0a0aed4ec 169 #define I2C_PRESENT /**< I2C is available in this part */
<> 150:02e0a0aed4ec 170 #define I2C_COUNT 1 /**< 1 I2Cs available */
<> 150:02e0a0aed4ec 171 #define AES_PRESENT
<> 150:02e0a0aed4ec 172 #define AES_COUNT 1
<> 150:02e0a0aed4ec 173 #define DMA_PRESENT
<> 150:02e0a0aed4ec 174 #define DMA_COUNT 1
<> 150:02e0a0aed4ec 175 #define LE_PRESENT
<> 150:02e0a0aed4ec 176 #define LE_COUNT 1
<> 150:02e0a0aed4ec 177 #define MSC_PRESENT
<> 150:02e0a0aed4ec 178 #define MSC_COUNT 1
<> 150:02e0a0aed4ec 179 #define EMU_PRESENT
<> 150:02e0a0aed4ec 180 #define EMU_COUNT 1
<> 150:02e0a0aed4ec 181 #define RMU_PRESENT
<> 150:02e0a0aed4ec 182 #define RMU_COUNT 1
<> 150:02e0a0aed4ec 183 #define CMU_PRESENT
<> 150:02e0a0aed4ec 184 #define CMU_COUNT 1
<> 150:02e0a0aed4ec 185 #define PRS_PRESENT
<> 150:02e0a0aed4ec 186 #define PRS_COUNT 1
<> 150:02e0a0aed4ec 187 #define GPIO_PRESENT
<> 150:02e0a0aed4ec 188 #define GPIO_COUNT 1
<> 150:02e0a0aed4ec 189 #define VCMP_PRESENT
<> 150:02e0a0aed4ec 190 #define VCMP_COUNT 1
<> 150:02e0a0aed4ec 191 #define RTC_PRESENT
<> 150:02e0a0aed4ec 192 #define RTC_COUNT 1
<> 150:02e0a0aed4ec 193 #define HFXTAL_PRESENT
<> 150:02e0a0aed4ec 194 #define HFXTAL_COUNT 1
<> 150:02e0a0aed4ec 195 #define LFXTAL_PRESENT
<> 150:02e0a0aed4ec 196 #define LFXTAL_COUNT 1
<> 150:02e0a0aed4ec 197 #define WDOG_PRESENT
<> 150:02e0a0aed4ec 198 #define WDOG_COUNT 1
<> 150:02e0a0aed4ec 199 #define DBG_PRESENT
<> 150:02e0a0aed4ec 200 #define DBG_COUNT 1
<> 150:02e0a0aed4ec 201 #define BOOTLOADER_PRESENT
<> 150:02e0a0aed4ec 202 #define BOOTLOADER_COUNT 1
<> 150:02e0a0aed4ec 203 #define ANALOG_PRESENT
<> 150:02e0a0aed4ec 204 #define ANALOG_COUNT 1
<> 150:02e0a0aed4ec 205
<> 150:02e0a0aed4ec 206 /** @} End of group EFM32ZG222F16_Part */
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208 #define ARM_MATH_CM0PLUS
<> 150:02e0a0aed4ec 209 #include "arm_math.h" /* To get __CLZ definitions etc. */
<> 150:02e0a0aed4ec 210 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
<> 150:02e0a0aed4ec 211 #include "system_efm32zg.h" /* System Header */
<> 150:02e0a0aed4ec 212
<> 150:02e0a0aed4ec 213 /**************************************************************************//**
<> 150:02e0a0aed4ec 214 * @defgroup EFM32ZG222F16_Peripheral_TypeDefs EFM32ZG222F16 Peripheral TypeDefs
<> 150:02e0a0aed4ec 215 * @{
<> 150:02e0a0aed4ec 216 * @brief Device Specific Peripheral Register Structures
<> 150:02e0a0aed4ec 217 *****************************************************************************/
<> 150:02e0a0aed4ec 218
<> 150:02e0a0aed4ec 219 #include "efm32zg_aes.h"
<> 150:02e0a0aed4ec 220 #include "efm32zg_dma_ch.h"
<> 150:02e0a0aed4ec 221 #include "efm32zg_dma.h"
<> 150:02e0a0aed4ec 222 #include "efm32zg_msc.h"
<> 150:02e0a0aed4ec 223 #include "efm32zg_emu.h"
<> 150:02e0a0aed4ec 224 #include "efm32zg_rmu.h"
<> 150:02e0a0aed4ec 225 #include "efm32zg_cmu.h"
<> 150:02e0a0aed4ec 226 #include "efm32zg_timer_cc.h"
<> 150:02e0a0aed4ec 227 #include "efm32zg_timer.h"
<> 150:02e0a0aed4ec 228 #include "efm32zg_acmp.h"
<> 150:02e0a0aed4ec 229 #include "efm32zg_usart.h"
<> 150:02e0a0aed4ec 230 #include "efm32zg_prs_ch.h"
<> 150:02e0a0aed4ec 231 #include "efm32zg_prs.h"
<> 150:02e0a0aed4ec 232 #include "efm32zg_idac.h"
<> 150:02e0a0aed4ec 233 #include "efm32zg_gpio_p.h"
<> 150:02e0a0aed4ec 234 #include "efm32zg_gpio.h"
<> 150:02e0a0aed4ec 235 #include "efm32zg_vcmp.h"
<> 150:02e0a0aed4ec 236 #include "efm32zg_adc.h"
<> 150:02e0a0aed4ec 237 #include "efm32zg_leuart.h"
<> 150:02e0a0aed4ec 238 #include "efm32zg_pcnt.h"
<> 150:02e0a0aed4ec 239 #include "efm32zg_i2c.h"
<> 150:02e0a0aed4ec 240 #include "efm32zg_rtc.h"
<> 150:02e0a0aed4ec 241 #include "efm32zg_wdog.h"
<> 150:02e0a0aed4ec 242 #include "efm32zg_dma_descriptor.h"
<> 150:02e0a0aed4ec 243 #include "efm32zg_devinfo.h"
<> 150:02e0a0aed4ec 244 #include "efm32zg_romtable.h"
<> 150:02e0a0aed4ec 245 #include "efm32zg_calibrate.h"
<> 150:02e0a0aed4ec 246
<> 150:02e0a0aed4ec 247 /** @} End of group EFM32ZG222F16_Peripheral_TypeDefs */
<> 150:02e0a0aed4ec 248
<> 150:02e0a0aed4ec 249 /**************************************************************************//**
<> 150:02e0a0aed4ec 250 * @defgroup EFM32ZG222F16_Peripheral_Base EFM32ZG222F16 Peripheral Memory Map
<> 150:02e0a0aed4ec 251 * @{
<> 150:02e0a0aed4ec 252 *****************************************************************************/
<> 150:02e0a0aed4ec 253
<> 150:02e0a0aed4ec 254 #define AES_BASE (0x400E0000UL) /**< AES base address */
<> 150:02e0a0aed4ec 255 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
<> 150:02e0a0aed4ec 256 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
<> 150:02e0a0aed4ec 257 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
<> 150:02e0a0aed4ec 258 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
<> 150:02e0a0aed4ec 259 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
<> 150:02e0a0aed4ec 260 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
<> 150:02e0a0aed4ec 261 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
<> 150:02e0a0aed4ec 262 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
<> 150:02e0a0aed4ec 263 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
<> 150:02e0a0aed4ec 264 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
<> 150:02e0a0aed4ec 265 #define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */
<> 150:02e0a0aed4ec 266 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
<> 150:02e0a0aed4ec 267 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
<> 150:02e0a0aed4ec 268 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 150:02e0a0aed4ec 269 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
<> 150:02e0a0aed4ec 270 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
<> 150:02e0a0aed4ec 271 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
<> 150:02e0a0aed4ec 272 #define RTC_BASE (0x40080000UL) /**< RTC base address */
<> 150:02e0a0aed4ec 273 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
<> 150:02e0a0aed4ec 274 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
<> 150:02e0a0aed4ec 275 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 150:02e0a0aed4ec 276 #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */
<> 150:02e0a0aed4ec 277 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 150:02e0a0aed4ec 278 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 150:02e0a0aed4ec 279
<> 150:02e0a0aed4ec 280 /** @} End of group EFM32ZG222F16_Peripheral_Base */
<> 150:02e0a0aed4ec 281
<> 150:02e0a0aed4ec 282 /**************************************************************************//**
<> 150:02e0a0aed4ec 283 * @defgroup EFM32ZG222F16_Peripheral_Declaration EFM32ZG222F16 Peripheral Declarations
<> 150:02e0a0aed4ec 284 * @{
<> 150:02e0a0aed4ec 285 *****************************************************************************/
<> 150:02e0a0aed4ec 286
<> 150:02e0a0aed4ec 287 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
<> 150:02e0a0aed4ec 288 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
<> 150:02e0a0aed4ec 289 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 150:02e0a0aed4ec 290 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 150:02e0a0aed4ec 291 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 150:02e0a0aed4ec 292 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 150:02e0a0aed4ec 293 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 150:02e0a0aed4ec 294 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 150:02e0a0aed4ec 295 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 150:02e0a0aed4ec 296 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 150:02e0a0aed4ec 297 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 150:02e0a0aed4ec 298 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
<> 150:02e0a0aed4ec 299 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 150:02e0a0aed4ec 300 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
<> 150:02e0a0aed4ec 301 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 150:02e0a0aed4ec 302 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 150:02e0a0aed4ec 303 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 150:02e0a0aed4ec 304 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 150:02e0a0aed4ec 305 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
<> 150:02e0a0aed4ec 306 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
<> 150:02e0a0aed4ec 307 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
<> 150:02e0a0aed4ec 308 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 150:02e0a0aed4ec 309 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 150:02e0a0aed4ec 310
<> 150:02e0a0aed4ec 311 /** @} End of group EFM32ZG222F16_Peripheral_Declaration */
<> 150:02e0a0aed4ec 312
<> 150:02e0a0aed4ec 313 /**************************************************************************//**
<> 150:02e0a0aed4ec 314 * @defgroup EFM32ZG222F16_BitFields EFM32ZG222F16 Bit Fields
<> 150:02e0a0aed4ec 315 * @{
<> 150:02e0a0aed4ec 316 *****************************************************************************/
<> 150:02e0a0aed4ec 317
<> 150:02e0a0aed4ec 318 #include "efm32zg_prs_signals.h"
<> 150:02e0a0aed4ec 319 #include "efm32zg_dmareq.h"
<> 150:02e0a0aed4ec 320 #include "efm32zg_dmactrl.h"
<> 150:02e0a0aed4ec 321
<> 150:02e0a0aed4ec 322 /**************************************************************************//**
<> 150:02e0a0aed4ec 323 * @defgroup EFM32ZG222F16_UNLOCK EFM32ZG222F16 Unlock Codes
<> 150:02e0a0aed4ec 324 * @{
<> 150:02e0a0aed4ec 325 *****************************************************************************/
<> 150:02e0a0aed4ec 326 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 150:02e0a0aed4ec 327 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 150:02e0a0aed4ec 328 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 150:02e0a0aed4ec 329 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 150:02e0a0aed4ec 330 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 150:02e0a0aed4ec 331
<> 150:02e0a0aed4ec 332 /** @} End of group EFM32ZG222F16_UNLOCK */
<> 150:02e0a0aed4ec 333
<> 150:02e0a0aed4ec 334 /** @} End of group EFM32ZG222F16_BitFields */
<> 150:02e0a0aed4ec 335
<> 150:02e0a0aed4ec 336 /**************************************************************************//**
<> 150:02e0a0aed4ec 337 * @defgroup EFM32ZG222F16_Alternate_Function EFM32ZG222F16 Alternate Function
<> 150:02e0a0aed4ec 338 * @{
<> 150:02e0a0aed4ec 339 *****************************************************************************/
<> 150:02e0a0aed4ec 340
<> 150:02e0a0aed4ec 341 #include "efm32zg_af_ports.h"
<> 150:02e0a0aed4ec 342 #include "efm32zg_af_pins.h"
<> 150:02e0a0aed4ec 343
<> 150:02e0a0aed4ec 344 /** @} End of group EFM32ZG222F16_Alternate_Function */
<> 150:02e0a0aed4ec 345
<> 150:02e0a0aed4ec 346 /**************************************************************************//**
<> 150:02e0a0aed4ec 347 * @brief Set the value of a bit field within a register.
<> 150:02e0a0aed4ec 348 *
<> 150:02e0a0aed4ec 349 * @param REG
<> 150:02e0a0aed4ec 350 * The register to update
<> 150:02e0a0aed4ec 351 * @param MASK
<> 150:02e0a0aed4ec 352 * The mask for the bit field to update
<> 150:02e0a0aed4ec 353 * @param VALUE
<> 150:02e0a0aed4ec 354 * The value to write to the bit field
<> 150:02e0a0aed4ec 355 * @param OFFSET
<> 150:02e0a0aed4ec 356 * The number of bits that the field is offset within the register.
<> 150:02e0a0aed4ec 357 * 0 (zero) means LSB.
<> 150:02e0a0aed4ec 358 *****************************************************************************/
<> 150:02e0a0aed4ec 359 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 150:02e0a0aed4ec 360 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 150:02e0a0aed4ec 361
<> 150:02e0a0aed4ec 362 /** @} End of group EFM32ZG222F16 */
<> 150:02e0a0aed4ec 363
<> 150:02e0a0aed4ec 364 /** @} End of group Parts */
<> 150:02e0a0aed4ec 365
<> 150:02e0a0aed4ec 366 #ifdef __cplusplus
<> 150:02e0a0aed4ec 367 }
<> 150:02e0a0aed4ec 368 #endif
<> 150:02e0a0aed4ec 369 #endif /* EFM32ZG222F16_H */