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targets/TARGET_Maxim/TARGET_MAX32620/device/i2cs_regs.h@161:bd0311f1ad86, 2017-05-27 (annotated)

Committer:
tonnyleonard
Date:
Sat May 27 01:26:18 2017 +0000
Revision:
161:bd0311f1ad86
Parent:
149:156823d33999 
Testing ADC with shunt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_I2CS_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_I2CS_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*
<> 144:ef7eb2e8f9f7 44 If types are not defined elsewhere (CMSIS) define them here
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 #ifndef __IO
<> 144:ef7eb2e8f9f7 47 #define __IO volatile
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #ifndef __I
<> 144:ef7eb2e8f9f7 50 #define __I volatile const
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52 #ifndef __O
<> 144:ef7eb2e8f9f7 53 #define __O volatile
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 144:ef7eb2e8f9f7 59 access to each register in module.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Offset Register Description
<> 144:ef7eb2e8f9f7 63 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t clk_div; /* 0x0000 I2C Slave Clock Divisor Control */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t dev_id; /* 0x0004 I2C Slave Device ID Register */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t intfl; /* 0x0008 I2CS Interrupt Flags */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t inten; /* 0x000C I2CS Interrupt Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t data_byte[32]; /* 0x0010-0x008C I2CS Data Byte */
<> 144:ef7eb2e8f9f7 70 } mxc_i2cs_regs_t;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /*
<> 144:ef7eb2e8f9f7 74 Register offsets for module I2CS.
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 78 #define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 79 #define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 80 #define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 81 #define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*
<> 144:ef7eb2e8f9f7 85 Field positions and masks for module I2CS.
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0
<> 144:ef7eb2e8f9f7 89 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS))
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0
<> 144:ef7eb2e8f9f7 92 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS))
<> 144:ef7eb2e8f9f7 93 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12
<> 144:ef7eb2e8f9f7 94 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS))
<> 144:ef7eb2e8f9f7 95 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14
<> 144:ef7eb2e8f9f7 96 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS))
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #define MXC_F_I2CS_INTFL_BYTE0_POS 0
<> 144:ef7eb2e8f9f7 99 #define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS))
<> 144:ef7eb2e8f9f7 100 #define MXC_F_I2CS_INTFL_BYTE1_POS 1
<> 144:ef7eb2e8f9f7 101 #define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS))
<> 144:ef7eb2e8f9f7 102 #define MXC_F_I2CS_INTFL_BYTE2_POS 2
<> 144:ef7eb2e8f9f7 103 #define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS))
<> 144:ef7eb2e8f9f7 104 #define MXC_F_I2CS_INTFL_BYTE3_POS 3
<> 144:ef7eb2e8f9f7 105 #define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS))
<> 144:ef7eb2e8f9f7 106 #define MXC_F_I2CS_INTFL_BYTE4_POS 4
<> 144:ef7eb2e8f9f7 107 #define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS))
<> 144:ef7eb2e8f9f7 108 #define MXC_F_I2CS_INTFL_BYTE5_POS 5
<> 144:ef7eb2e8f9f7 109 #define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS))
<> 144:ef7eb2e8f9f7 110 #define MXC_F_I2CS_INTFL_BYTE6_POS 6
<> 144:ef7eb2e8f9f7 111 #define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS))
<> 144:ef7eb2e8f9f7 112 #define MXC_F_I2CS_INTFL_BYTE7_POS 7
<> 144:ef7eb2e8f9f7 113 #define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS))
<> 144:ef7eb2e8f9f7 114 #define MXC_F_I2CS_INTFL_BYTE8_POS 8
<> 144:ef7eb2e8f9f7 115 #define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS))
<> 144:ef7eb2e8f9f7 116 #define MXC_F_I2CS_INTFL_BYTE9_POS 9
<> 144:ef7eb2e8f9f7 117 #define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS))
<> 144:ef7eb2e8f9f7 118 #define MXC_F_I2CS_INTFL_BYTE10_POS 10
<> 144:ef7eb2e8f9f7 119 #define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS))
<> 144:ef7eb2e8f9f7 120 #define MXC_F_I2CS_INTFL_BYTE11_POS 11
<> 144:ef7eb2e8f9f7 121 #define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS))
<> 144:ef7eb2e8f9f7 122 #define MXC_F_I2CS_INTFL_BYTE12_POS 12
<> 144:ef7eb2e8f9f7 123 #define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS))
<> 144:ef7eb2e8f9f7 124 #define MXC_F_I2CS_INTFL_BYTE13_POS 13
<> 144:ef7eb2e8f9f7 125 #define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS))
<> 144:ef7eb2e8f9f7 126 #define MXC_F_I2CS_INTFL_BYTE14_POS 14
<> 144:ef7eb2e8f9f7 127 #define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS))
<> 144:ef7eb2e8f9f7 128 #define MXC_F_I2CS_INTFL_BYTE15_POS 15
<> 144:ef7eb2e8f9f7 129 #define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS))
<> 144:ef7eb2e8f9f7 130 #define MXC_F_I2CS_INTFL_BYTE16_POS 16
<> 144:ef7eb2e8f9f7 131 #define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS))
<> 144:ef7eb2e8f9f7 132 #define MXC_F_I2CS_INTFL_BYTE17_POS 17
<> 144:ef7eb2e8f9f7 133 #define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS))
<> 144:ef7eb2e8f9f7 134 #define MXC_F_I2CS_INTFL_BYTE18_POS 18
<> 144:ef7eb2e8f9f7 135 #define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS))
<> 144:ef7eb2e8f9f7 136 #define MXC_F_I2CS_INTFL_BYTE19_POS 19
<> 144:ef7eb2e8f9f7 137 #define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS))
<> 144:ef7eb2e8f9f7 138 #define MXC_F_I2CS_INTFL_BYTE20_POS 20
<> 144:ef7eb2e8f9f7 139 #define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS))
<> 144:ef7eb2e8f9f7 140 #define MXC_F_I2CS_INTFL_BYTE21_POS 21
<> 144:ef7eb2e8f9f7 141 #define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS))
<> 144:ef7eb2e8f9f7 142 #define MXC_F_I2CS_INTFL_BYTE22_POS 22
<> 144:ef7eb2e8f9f7 143 #define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS))
<> 144:ef7eb2e8f9f7 144 #define MXC_F_I2CS_INTFL_BYTE23_POS 23
<> 144:ef7eb2e8f9f7 145 #define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS))
<> 144:ef7eb2e8f9f7 146 #define MXC_F_I2CS_INTFL_BYTE24_POS 24
<> 144:ef7eb2e8f9f7 147 #define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_F_I2CS_INTFL_BYTE25_POS 25
<> 144:ef7eb2e8f9f7 149 #define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS))
<> 144:ef7eb2e8f9f7 150 #define MXC_F_I2CS_INTFL_BYTE26_POS 26
<> 144:ef7eb2e8f9f7 151 #define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS))
<> 144:ef7eb2e8f9f7 152 #define MXC_F_I2CS_INTFL_BYTE27_POS 27
<> 144:ef7eb2e8f9f7 153 #define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS))
<> 144:ef7eb2e8f9f7 154 #define MXC_F_I2CS_INTFL_BYTE28_POS 28
<> 144:ef7eb2e8f9f7 155 #define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS))
<> 144:ef7eb2e8f9f7 156 #define MXC_F_I2CS_INTFL_BYTE29_POS 29
<> 144:ef7eb2e8f9f7 157 #define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS))
<> 144:ef7eb2e8f9f7 158 #define MXC_F_I2CS_INTFL_BYTE30_POS 30
<> 144:ef7eb2e8f9f7 159 #define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_I2CS_INTFL_BYTE31_POS 31
<> 144:ef7eb2e8f9f7 161 #define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS))
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 #define MXC_F_I2CS_INTEN_BYTE0_POS 0
<> 144:ef7eb2e8f9f7 164 #define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS))
<> 144:ef7eb2e8f9f7 165 #define MXC_F_I2CS_INTEN_BYTE1_POS 1
<> 144:ef7eb2e8f9f7 166 #define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS))
<> 144:ef7eb2e8f9f7 167 #define MXC_F_I2CS_INTEN_BYTE2_POS 2
<> 144:ef7eb2e8f9f7 168 #define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS))
<> 144:ef7eb2e8f9f7 169 #define MXC_F_I2CS_INTEN_BYTE3_POS 3
<> 144:ef7eb2e8f9f7 170 #define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS))
<> 144:ef7eb2e8f9f7 171 #define MXC_F_I2CS_INTEN_BYTE4_POS 4
<> 144:ef7eb2e8f9f7 172 #define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS))
<> 144:ef7eb2e8f9f7 173 #define MXC_F_I2CS_INTEN_BYTE5_POS 5
<> 144:ef7eb2e8f9f7 174 #define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_F_I2CS_INTEN_BYTE6_POS 6
<> 144:ef7eb2e8f9f7 176 #define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS))
<> 144:ef7eb2e8f9f7 177 #define MXC_F_I2CS_INTEN_BYTE7_POS 7
<> 144:ef7eb2e8f9f7 178 #define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS))
<> 144:ef7eb2e8f9f7 179 #define MXC_F_I2CS_INTEN_BYTE8_POS 8
<> 144:ef7eb2e8f9f7 180 #define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS))
<> 144:ef7eb2e8f9f7 181 #define MXC_F_I2CS_INTEN_BYTE9_POS 9
<> 144:ef7eb2e8f9f7 182 #define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS))
<> 144:ef7eb2e8f9f7 183 #define MXC_F_I2CS_INTEN_BYTE10_POS 10
<> 144:ef7eb2e8f9f7 184 #define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS))
<> 144:ef7eb2e8f9f7 185 #define MXC_F_I2CS_INTEN_BYTE11_POS 11
<> 144:ef7eb2e8f9f7 186 #define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS))
<> 144:ef7eb2e8f9f7 187 #define MXC_F_I2CS_INTEN_BYTE12_POS 12
<> 144:ef7eb2e8f9f7 188 #define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS))
<> 144:ef7eb2e8f9f7 189 #define MXC_F_I2CS_INTEN_BYTE13_POS 13
<> 144:ef7eb2e8f9f7 190 #define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS))
<> 144:ef7eb2e8f9f7 191 #define MXC_F_I2CS_INTEN_BYTE14_POS 14
<> 144:ef7eb2e8f9f7 192 #define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS))
<> 144:ef7eb2e8f9f7 193 #define MXC_F_I2CS_INTEN_BYTE15_POS 15
<> 144:ef7eb2e8f9f7 194 #define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS))
<> 144:ef7eb2e8f9f7 195 #define MXC_F_I2CS_INTEN_BYTE16_POS 16
<> 144:ef7eb2e8f9f7 196 #define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS))
<> 144:ef7eb2e8f9f7 197 #define MXC_F_I2CS_INTEN_BYTE17_POS 17
<> 144:ef7eb2e8f9f7 198 #define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS))
<> 144:ef7eb2e8f9f7 199 #define MXC_F_I2CS_INTEN_BYTE18_POS 18
<> 144:ef7eb2e8f9f7 200 #define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS))
<> 144:ef7eb2e8f9f7 201 #define MXC_F_I2CS_INTEN_BYTE19_POS 19
<> 144:ef7eb2e8f9f7 202 #define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS))
<> 144:ef7eb2e8f9f7 203 #define MXC_F_I2CS_INTEN_BYTE20_POS 20
<> 144:ef7eb2e8f9f7 204 #define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS))
<> 144:ef7eb2e8f9f7 205 #define MXC_F_I2CS_INTEN_BYTE21_POS 21
<> 144:ef7eb2e8f9f7 206 #define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS))
<> 144:ef7eb2e8f9f7 207 #define MXC_F_I2CS_INTEN_BYTE22_POS 22
<> 144:ef7eb2e8f9f7 208 #define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS))
<> 144:ef7eb2e8f9f7 209 #define MXC_F_I2CS_INTEN_BYTE23_POS 23
<> 144:ef7eb2e8f9f7 210 #define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS))
<> 144:ef7eb2e8f9f7 211 #define MXC_F_I2CS_INTEN_BYTE24_POS 24
<> 144:ef7eb2e8f9f7 212 #define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS))
<> 144:ef7eb2e8f9f7 213 #define MXC_F_I2CS_INTEN_BYTE25_POS 25
<> 144:ef7eb2e8f9f7 214 #define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS))
<> 144:ef7eb2e8f9f7 215 #define MXC_F_I2CS_INTEN_BYTE26_POS 26
<> 144:ef7eb2e8f9f7 216 #define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS))
<> 144:ef7eb2e8f9f7 217 #define MXC_F_I2CS_INTEN_BYTE27_POS 27
<> 144:ef7eb2e8f9f7 218 #define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS))
<> 144:ef7eb2e8f9f7 219 #define MXC_F_I2CS_INTEN_BYTE28_POS 28
<> 144:ef7eb2e8f9f7 220 #define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS))
<> 144:ef7eb2e8f9f7 221 #define MXC_F_I2CS_INTEN_BYTE29_POS 29
<> 144:ef7eb2e8f9f7 222 #define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS))
<> 144:ef7eb2e8f9f7 223 #define MXC_F_I2CS_INTEN_BYTE30_POS 30
<> 144:ef7eb2e8f9f7 224 #define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS))
<> 144:ef7eb2e8f9f7 225 #define MXC_F_I2CS_INTEN_BYTE31_POS 31
<> 144:ef7eb2e8f9f7 226 #define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS))
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0
<> 144:ef7eb2e8f9f7 229 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS))
<> 144:ef7eb2e8f9f7 230 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8
<> 144:ef7eb2e8f9f7 231 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS))
<> 144:ef7eb2e8f9f7 232 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9
<> 144:ef7eb2e8f9f7 233 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS))
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239 #endif
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #endif /* _MXC_I2CS_REGS_H_ */
<> 144:ef7eb2e8f9f7 242