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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/drivers/fsl_adc16.c@161:bd0311f1ad86, 2017-05-27 (annotated)

Committer:
tonnyleonard
Date:
Sat May 27 01:26:18 2017 +0000
Revision:
161:bd0311f1ad86
Parent:
154:37f96f9d4de2 
Testing ADC with shunt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_adc16.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 /*******************************************************************************
<> 154:37f96f9d4de2 34 * Prototypes
<> 154:37f96f9d4de2 35 ******************************************************************************/
<> 154:37f96f9d4de2 36 /*!
<> 154:37f96f9d4de2 37 * @brief Get instance number for ADC16 module.
<> 154:37f96f9d4de2 38 *
<> 154:37f96f9d4de2 39 * @param base ADC16 peripheral base address
<> 154:37f96f9d4de2 40 */
<> 154:37f96f9d4de2 41 static uint32_t ADC16_GetInstance(ADC_Type *base);
<> 154:37f96f9d4de2 42
<> 154:37f96f9d4de2 43 /*******************************************************************************
<> 154:37f96f9d4de2 44 * Variables
<> 154:37f96f9d4de2 45 ******************************************************************************/
<> 154:37f96f9d4de2 46 /*! @brief Pointers to ADC16 bases for each instance. */
<> 154:37f96f9d4de2 47 static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
<> 154:37f96f9d4de2 48
<> 154:37f96f9d4de2 49 /*! @brief Pointers to ADC16 clocks for each instance. */
<> 154:37f96f9d4de2 50 const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
<> 154:37f96f9d4de2 51
<> 154:37f96f9d4de2 52 /*******************************************************************************
<> 154:37f96f9d4de2 53 * Code
<> 154:37f96f9d4de2 54 ******************************************************************************/
<> 154:37f96f9d4de2 55 static uint32_t ADC16_GetInstance(ADC_Type *base)
<> 154:37f96f9d4de2 56 {
<> 154:37f96f9d4de2 57 uint32_t instance;
<> 154:37f96f9d4de2 58
<> 154:37f96f9d4de2 59 /* Find the instance index from base address mappings. */
<> 154:37f96f9d4de2 60 for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++)
<> 154:37f96f9d4de2 61 {
<> 154:37f96f9d4de2 62 if (s_adc16Bases[instance] == base)
<> 154:37f96f9d4de2 63 {
<> 154:37f96f9d4de2 64 break;
<> 154:37f96f9d4de2 65 }
<> 154:37f96f9d4de2 66 }
<> 154:37f96f9d4de2 67
<> 154:37f96f9d4de2 68 assert(instance < FSL_FEATURE_SOC_ADC16_COUNT);
<> 154:37f96f9d4de2 69
<> 154:37f96f9d4de2 70 return instance;
<> 154:37f96f9d4de2 71 }
<> 154:37f96f9d4de2 72
<> 154:37f96f9d4de2 73 void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
<> 154:37f96f9d4de2 74 {
<> 154:37f96f9d4de2 75 assert(NULL != config);
<> 154:37f96f9d4de2 76
<> 154:37f96f9d4de2 77 uint32_t tmp32;
<> 154:37f96f9d4de2 78
<> 154:37f96f9d4de2 79 /* Enable the clock. */
<> 154:37f96f9d4de2 80 CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
<> 154:37f96f9d4de2 81
<> 154:37f96f9d4de2 82 /* ADCx_CFG1. */
<> 154:37f96f9d4de2 83 tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
<> 154:37f96f9d4de2 84 if (kADC16_LongSampleDisabled != config->longSampleMode)
<> 154:37f96f9d4de2 85 {
<> 154:37f96f9d4de2 86 tmp32 |= ADC_CFG1_ADLSMP_MASK;
<> 154:37f96f9d4de2 87 }
<> 154:37f96f9d4de2 88 tmp32 |= ADC_CFG1_ADIV(config->clockDivider);
<> 154:37f96f9d4de2 89 if (config->enableLowPower)
<> 154:37f96f9d4de2 90 {
<> 154:37f96f9d4de2 91 tmp32 |= ADC_CFG1_ADLPC_MASK;
<> 154:37f96f9d4de2 92 }
<> 154:37f96f9d4de2 93 base->CFG1 = tmp32;
<> 154:37f96f9d4de2 94
<> 154:37f96f9d4de2 95 /* ADCx_CFG2. */
<> 154:37f96f9d4de2 96 tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK);
<> 154:37f96f9d4de2 97 if (kADC16_LongSampleDisabled != config->longSampleMode)
<> 154:37f96f9d4de2 98 {
<> 154:37f96f9d4de2 99 tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode);
<> 154:37f96f9d4de2 100 }
<> 154:37f96f9d4de2 101 if (config->enableHighSpeed)
<> 154:37f96f9d4de2 102 {
<> 154:37f96f9d4de2 103 tmp32 |= ADC_CFG2_ADHSC_MASK;
<> 154:37f96f9d4de2 104 }
<> 154:37f96f9d4de2 105 if (config->enableAsynchronousClock)
<> 154:37f96f9d4de2 106 {
<> 154:37f96f9d4de2 107 tmp32 |= ADC_CFG2_ADACKEN_MASK;
<> 154:37f96f9d4de2 108 }
<> 154:37f96f9d4de2 109 base->CFG2 = tmp32;
<> 154:37f96f9d4de2 110
<> 154:37f96f9d4de2 111 /* ADCx_SC2. */
<> 154:37f96f9d4de2 112 tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK);
<> 154:37f96f9d4de2 113 tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource);
<> 154:37f96f9d4de2 114 base->SC2 = tmp32;
<> 154:37f96f9d4de2 115
<> 154:37f96f9d4de2 116 /* ADCx_SC3. */
<> 154:37f96f9d4de2 117 if (config->enableContinuousConversion)
<> 154:37f96f9d4de2 118 {
<> 154:37f96f9d4de2 119 base->SC3 |= ADC_SC3_ADCO_MASK;
<> 154:37f96f9d4de2 120 }
<> 154:37f96f9d4de2 121 else
<> 154:37f96f9d4de2 122 {
<> 154:37f96f9d4de2 123 base->SC3 &= ~ADC_SC3_ADCO_MASK;
<> 154:37f96f9d4de2 124 }
<> 154:37f96f9d4de2 125 }
<> 154:37f96f9d4de2 126
<> 154:37f96f9d4de2 127 void ADC16_Deinit(ADC_Type *base)
<> 154:37f96f9d4de2 128 {
<> 154:37f96f9d4de2 129 /* Disable the clock. */
<> 154:37f96f9d4de2 130 CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
<> 154:37f96f9d4de2 131 }
<> 154:37f96f9d4de2 132
<> 154:37f96f9d4de2 133 void ADC16_GetDefaultConfig(adc16_config_t *config)
<> 154:37f96f9d4de2 134 {
<> 154:37f96f9d4de2 135 assert(NULL != config);
<> 154:37f96f9d4de2 136
<> 154:37f96f9d4de2 137 config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
<> 154:37f96f9d4de2 138 config->clockSource = kADC16_ClockSourceAsynchronousClock;
<> 154:37f96f9d4de2 139 config->enableAsynchronousClock = true;
<> 154:37f96f9d4de2 140 config->clockDivider = kADC16_ClockDivider8;
<> 154:37f96f9d4de2 141 config->resolution = kADC16_ResolutionSE12Bit;
<> 154:37f96f9d4de2 142 config->longSampleMode = kADC16_LongSampleDisabled;
<> 154:37f96f9d4de2 143 config->enableHighSpeed = false;
<> 154:37f96f9d4de2 144 config->enableLowPower = false;
<> 154:37f96f9d4de2 145 config->enableContinuousConversion = false;
<> 154:37f96f9d4de2 146 }
<> 154:37f96f9d4de2 147
<> 154:37f96f9d4de2 148 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 154:37f96f9d4de2 149 status_t ADC16_DoAutoCalibration(ADC_Type *base)
<> 154:37f96f9d4de2 150 {
<> 154:37f96f9d4de2 151 bool bHWTrigger = false;
<> 154:37f96f9d4de2 152 uint32_t tmp32;
<> 154:37f96f9d4de2 153 status_t status = kStatus_Success;
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 /* The calibration would be failed when in hardwar mode.
<> 154:37f96f9d4de2 156 * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
<> 154:37f96f9d4de2 157 if (0U != (ADC_SC2_ADTRG_MASK & base->SC2))
<> 154:37f96f9d4de2 158 {
<> 154:37f96f9d4de2 159 bHWTrigger = true;
<> 154:37f96f9d4de2 160 base->SC2 &= ~ADC_SC2_ADTRG_MASK;
<> 154:37f96f9d4de2 161 }
<> 154:37f96f9d4de2 162
<> 154:37f96f9d4de2 163 /* Clear the CALF and launch the calibration. */
<> 154:37f96f9d4de2 164 base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK;
<> 154:37f96f9d4de2 165 while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U)))
<> 154:37f96f9d4de2 166 {
<> 154:37f96f9d4de2 167 /* Check the CALF when the calibration is active. */
<> 154:37f96f9d4de2 168 if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
<> 154:37f96f9d4de2 169 {
<> 154:37f96f9d4de2 170 status = kStatus_Fail;
<> 154:37f96f9d4de2 171 break;
<> 154:37f96f9d4de2 172 }
<> 154:37f96f9d4de2 173 }
<> 154:37f96f9d4de2 174
<> 154:37f96f9d4de2 175 /* Restore the hardware trigger setting if it was enabled before. */
<> 154:37f96f9d4de2 176 if (bHWTrigger)
<> 154:37f96f9d4de2 177 {
<> 154:37f96f9d4de2 178 base->SC2 |= ADC_SC2_ADTRG_MASK;
<> 154:37f96f9d4de2 179 }
<> 154:37f96f9d4de2 180 /* Check the CALF at the end of calibration. */
<> 154:37f96f9d4de2 181 if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
<> 154:37f96f9d4de2 182 {
<> 154:37f96f9d4de2 183 status = kStatus_Fail;
<> 154:37f96f9d4de2 184 }
<> 154:37f96f9d4de2 185 if (kStatus_Success != status) /* Check if the calibration process is succeed. */
<> 154:37f96f9d4de2 186 {
<> 154:37f96f9d4de2 187 return status;
<> 154:37f96f9d4de2 188 }
<> 154:37f96f9d4de2 189
<> 154:37f96f9d4de2 190 /* Calculate the calibration values. */
<> 154:37f96f9d4de2 191 tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS;
<> 154:37f96f9d4de2 192 tmp32 = 0x8000U | (tmp32 >> 1U);
<> 154:37f96f9d4de2 193 base->PG = tmp32;
<> 154:37f96f9d4de2 194
<> 154:37f96f9d4de2 195 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 154:37f96f9d4de2 196 tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS;
<> 154:37f96f9d4de2 197 tmp32 = 0x8000U | (tmp32 >> 1U);
<> 154:37f96f9d4de2 198 base->MG = tmp32;
<> 154:37f96f9d4de2 199 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 154:37f96f9d4de2 200
<> 154:37f96f9d4de2 201 return kStatus_Success;
<> 154:37f96f9d4de2 202 }
<> 154:37f96f9d4de2 203 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 154:37f96f9d4de2 204
<> 154:37f96f9d4de2 205 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
<> 154:37f96f9d4de2 206 void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode)
<> 154:37f96f9d4de2 207 {
<> 154:37f96f9d4de2 208 if (kADC16_ChannelMuxA == mode)
<> 154:37f96f9d4de2 209 {
<> 154:37f96f9d4de2 210 base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK;
<> 154:37f96f9d4de2 211 }
<> 154:37f96f9d4de2 212 else /* kADC16_ChannelMuxB. */
<> 154:37f96f9d4de2 213 {
<> 154:37f96f9d4de2 214 base->CFG2 |= ADC_CFG2_MUXSEL_MASK;
<> 154:37f96f9d4de2 215 }
<> 154:37f96f9d4de2 216 }
<> 154:37f96f9d4de2 217 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
<> 154:37f96f9d4de2 218
<> 154:37f96f9d4de2 219 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config)
<> 154:37f96f9d4de2 220 {
<> 154:37f96f9d4de2 221 uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK);
<> 154:37f96f9d4de2 222
<> 154:37f96f9d4de2 223 if (!config) /* Pass "NULL" to disable the feature. */
<> 154:37f96f9d4de2 224 {
<> 154:37f96f9d4de2 225 base->SC2 = tmp32;
<> 154:37f96f9d4de2 226 return;
<> 154:37f96f9d4de2 227 }
<> 154:37f96f9d4de2 228 /* Enable the feature. */
<> 154:37f96f9d4de2 229 tmp32 |= ADC_SC2_ACFE_MASK;
<> 154:37f96f9d4de2 230
<> 154:37f96f9d4de2 231 /* Select the hardware compare working mode. */
<> 154:37f96f9d4de2 232 switch (config->hardwareCompareMode)
<> 154:37f96f9d4de2 233 {
<> 154:37f96f9d4de2 234 case kADC16_HardwareCompareMode0:
<> 154:37f96f9d4de2 235 break;
<> 154:37f96f9d4de2 236 case kADC16_HardwareCompareMode1:
<> 154:37f96f9d4de2 237 tmp32 |= ADC_SC2_ACFGT_MASK;
<> 154:37f96f9d4de2 238 break;
<> 154:37f96f9d4de2 239 case kADC16_HardwareCompareMode2:
<> 154:37f96f9d4de2 240 tmp32 |= ADC_SC2_ACREN_MASK;
<> 154:37f96f9d4de2 241 break;
<> 154:37f96f9d4de2 242 case kADC16_HardwareCompareMode3:
<> 154:37f96f9d4de2 243 tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK;
<> 154:37f96f9d4de2 244 break;
<> 154:37f96f9d4de2 245 default:
<> 154:37f96f9d4de2 246 break;
<> 154:37f96f9d4de2 247 }
<> 154:37f96f9d4de2 248 base->SC2 = tmp32;
<> 154:37f96f9d4de2 249
<> 154:37f96f9d4de2 250 /* Load the compare values. */
<> 154:37f96f9d4de2 251 base->CV1 = ADC_CV1_CV(config->value1);
<> 154:37f96f9d4de2 252 base->CV2 = ADC_CV2_CV(config->value2);
<> 154:37f96f9d4de2 253 }
<> 154:37f96f9d4de2 254
<> 154:37f96f9d4de2 255 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
<> 154:37f96f9d4de2 256 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode)
<> 154:37f96f9d4de2 257 {
<> 154:37f96f9d4de2 258 uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
<> 154:37f96f9d4de2 259
<> 154:37f96f9d4de2 260 if (kADC16_HardwareAverageDisabled != mode)
<> 154:37f96f9d4de2 261 {
<> 154:37f96f9d4de2 262 tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode);
<> 154:37f96f9d4de2 263 }
<> 154:37f96f9d4de2 264 base->SC3 = tmp32;
<> 154:37f96f9d4de2 265 }
<> 154:37f96f9d4de2 266 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
<> 154:37f96f9d4de2 267
<> 154:37f96f9d4de2 268 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
<> 154:37f96f9d4de2 269 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config)
<> 154:37f96f9d4de2 270 {
<> 154:37f96f9d4de2 271 uint32_t tmp32;
<> 154:37f96f9d4de2 272
<> 154:37f96f9d4de2 273 if (!config) /* Passing "NULL" is to disable the feature. */
<> 154:37f96f9d4de2 274 {
<> 154:37f96f9d4de2 275 base->PGA = 0U;
<> 154:37f96f9d4de2 276 return;
<> 154:37f96f9d4de2 277 }
<> 154:37f96f9d4de2 278
<> 154:37f96f9d4de2 279 /* Enable the PGA and set the gain value. */
<> 154:37f96f9d4de2 280 tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain);
<> 154:37f96f9d4de2 281
<> 154:37f96f9d4de2 282 /* Configure the misc features for PGA. */
<> 154:37f96f9d4de2 283 if (config->enableRunInNormalMode)
<> 154:37f96f9d4de2 284 {
<> 154:37f96f9d4de2 285 tmp32 |= ADC_PGA_PGALPb_MASK;
<> 154:37f96f9d4de2 286 }
<> 154:37f96f9d4de2 287 #if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
<> 154:37f96f9d4de2 288 if (config->disablePgaChopping)
<> 154:37f96f9d4de2 289 {
<> 154:37f96f9d4de2 290 tmp32 |= ADC_PGA_PGACHPb_MASK;
<> 154:37f96f9d4de2 291 }
<> 154:37f96f9d4de2 292 #endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
<> 154:37f96f9d4de2 293 #if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
<> 154:37f96f9d4de2 294 if (config->enableRunInOffsetMeasurement)
<> 154:37f96f9d4de2 295 {
<> 154:37f96f9d4de2 296 tmp32 |= ADC_PGA_PGAOFSM_MASK;
<> 154:37f96f9d4de2 297 }
<> 154:37f96f9d4de2 298 #endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
<> 154:37f96f9d4de2 299 base->PGA = tmp32;
<> 154:37f96f9d4de2 300 }
<> 154:37f96f9d4de2 301 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
<> 154:37f96f9d4de2 302
<> 154:37f96f9d4de2 303 uint32_t ADC16_GetStatusFlags(ADC_Type *base)
<> 154:37f96f9d4de2 304 {
<> 154:37f96f9d4de2 305 uint32_t ret = 0;
<> 154:37f96f9d4de2 306
<> 154:37f96f9d4de2 307 if (0U != (base->SC2 & ADC_SC2_ADACT_MASK))
<> 154:37f96f9d4de2 308 {
<> 154:37f96f9d4de2 309 ret |= kADC16_ActiveFlag;
<> 154:37f96f9d4de2 310 }
<> 154:37f96f9d4de2 311 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 154:37f96f9d4de2 312 if (0U != (base->SC3 & ADC_SC3_CALF_MASK))
<> 154:37f96f9d4de2 313 {
<> 154:37f96f9d4de2 314 ret |= kADC16_CalibrationFailedFlag;
<> 154:37f96f9d4de2 315 }
<> 154:37f96f9d4de2 316 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 154:37f96f9d4de2 317 return ret;
<> 154:37f96f9d4de2 318 }
<> 154:37f96f9d4de2 319
<> 154:37f96f9d4de2 320 void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 321 {
<> 154:37f96f9d4de2 322 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
<> 154:37f96f9d4de2 323 if (0U != (mask & kADC16_CalibrationFailedFlag))
<> 154:37f96f9d4de2 324 {
<> 154:37f96f9d4de2 325 base->SC3 |= ADC_SC3_CALF_MASK;
<> 154:37f96f9d4de2 326 }
<> 154:37f96f9d4de2 327 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
<> 154:37f96f9d4de2 328 }
<> 154:37f96f9d4de2 329
<> 154:37f96f9d4de2 330 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config)
<> 154:37f96f9d4de2 331 {
<> 154:37f96f9d4de2 332 assert(channelGroup < ADC_SC1_COUNT);
<> 154:37f96f9d4de2 333 assert(NULL != config);
<> 154:37f96f9d4de2 334
<> 154:37f96f9d4de2 335 uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */
<> 154:37f96f9d4de2 336
<> 154:37f96f9d4de2 337 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
<> 154:37f96f9d4de2 338 /* Enable the differential conversion. */
<> 154:37f96f9d4de2 339 if (config->enableDifferentialConversion)
<> 154:37f96f9d4de2 340 {
<> 154:37f96f9d4de2 341 sc1 |= ADC_SC1_DIFF_MASK;
<> 154:37f96f9d4de2 342 }
<> 154:37f96f9d4de2 343 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
<> 154:37f96f9d4de2 344 /* Enable the interrupt when the conversion is done. */
<> 154:37f96f9d4de2 345 if (config->enableInterruptOnConversionCompleted)
<> 154:37f96f9d4de2 346 {
<> 154:37f96f9d4de2 347 sc1 |= ADC_SC1_AIEN_MASK;
<> 154:37f96f9d4de2 348 }
<> 154:37f96f9d4de2 349 base->SC1[channelGroup] = sc1;
<> 154:37f96f9d4de2 350 }
<> 154:37f96f9d4de2 351
<> 154:37f96f9d4de2 352 uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
<> 154:37f96f9d4de2 353 {
<> 154:37f96f9d4de2 354 assert(channelGroup < ADC_SC1_COUNT);
<> 154:37f96f9d4de2 355
<> 154:37f96f9d4de2 356 uint32_t ret = 0U;
<> 154:37f96f9d4de2 357
<> 154:37f96f9d4de2 358 if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK))
<> 154:37f96f9d4de2 359 {
<> 154:37f96f9d4de2 360 ret |= kADC16_ChannelConversionDoneFlag;
<> 154:37f96f9d4de2 361 }
<> 154:37f96f9d4de2 362 return ret;
<> 154:37f96f9d4de2 363 }