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Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f410rx.h@158:b23ee177fd68, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 14:44:10 2017 +0000
Revision:
158:b23ee177fd68
Parent:
targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/device/stm32f410rx.h@149:156823d33999 
This updates the lib to the mbed lib v136

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 25:ac5b0a371348 1 /**
mbed_official 25:ac5b0a371348 2 ******************************************************************************
mbed_official 25:ac5b0a371348 3 * @file stm32f410rx.h
mbed_official 25:ac5b0a371348 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.5.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
mbed_official 25:ac5b0a371348 7 * @brief CMSIS STM32F410Rx Device Peripheral Access Layer Header File.
mbed_official 25:ac5b0a371348 8 *
mbed_official 25:ac5b0a371348 9 * This file contains:
mbed_official 25:ac5b0a371348 10 * - Data structures and the address mapping for all peripherals
<> 144:ef7eb2e8f9f7 11 * - peripherals registers declarations and bits definition
mbed_official 25:ac5b0a371348 12 * - Macros to access peripheral’s registers hardware
mbed_official 25:ac5b0a371348 13 *
mbed_official 25:ac5b0a371348 14 ******************************************************************************
mbed_official 25:ac5b0a371348 15 * @attention
mbed_official 25:ac5b0a371348 16 *
<> 144:ef7eb2e8f9f7 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
mbed_official 25:ac5b0a371348 18 *
mbed_official 25:ac5b0a371348 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 25:ac5b0a371348 20 * are permitted provided that the following conditions are met:
mbed_official 25:ac5b0a371348 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 25:ac5b0a371348 22 * this list of conditions and the following disclaimer.
mbed_official 25:ac5b0a371348 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 25:ac5b0a371348 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 25:ac5b0a371348 25 * and/or other materials provided with the distribution.
mbed_official 25:ac5b0a371348 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 25:ac5b0a371348 27 * may be used to endorse or promote products derived from this software
mbed_official 25:ac5b0a371348 28 * without specific prior written permission.
mbed_official 25:ac5b0a371348 29 *
mbed_official 25:ac5b0a371348 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 25:ac5b0a371348 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 25:ac5b0a371348 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 25:ac5b0a371348 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 25:ac5b0a371348 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 25:ac5b0a371348 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 25:ac5b0a371348 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 25:ac5b0a371348 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 25:ac5b0a371348 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 25:ac5b0a371348 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 25:ac5b0a371348 40 *
mbed_official 25:ac5b0a371348 41 ******************************************************************************
mbed_official 25:ac5b0a371348 42 */
mbed_official 25:ac5b0a371348 43
mbed_official 25:ac5b0a371348 44 /** @addtogroup CMSIS
mbed_official 25:ac5b0a371348 45 * @{
mbed_official 25:ac5b0a371348 46 */
mbed_official 25:ac5b0a371348 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup stm32f410rx
mbed_official 25:ac5b0a371348 49 * @{
mbed_official 25:ac5b0a371348 50 */
mbed_official 25:ac5b0a371348 51
<> 144:ef7eb2e8f9f7 52 #ifndef __STM32F410Rx_H
<> 144:ef7eb2e8f9f7 53 #define __STM32F410Rx_H
mbed_official 25:ac5b0a371348 54
mbed_official 25:ac5b0a371348 55 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 56 extern "C" {
mbed_official 25:ac5b0a371348 57 #endif /* __cplusplus */
mbed_official 25:ac5b0a371348 58
mbed_official 25:ac5b0a371348 59
mbed_official 25:ac5b0a371348 60 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 25:ac5b0a371348 61 * @{
mbed_official 25:ac5b0a371348 62 */
mbed_official 25:ac5b0a371348 63
mbed_official 25:ac5b0a371348 64 /**
mbed_official 25:ac5b0a371348 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 25:ac5b0a371348 66 */
<> 144:ef7eb2e8f9f7 67 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
<> 144:ef7eb2e8f9f7 68 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
<> 144:ef7eb2e8f9f7 69 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
<> 144:ef7eb2e8f9f7 70 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 71 #ifndef __FPU_PRESENT
<> 144:ef7eb2e8f9f7 72 #define __FPU_PRESENT 1U /*!< FPU present */
<> 144:ef7eb2e8f9f7 73 #endif /* __FPU_PRESENT */
mbed_official 25:ac5b0a371348 74
mbed_official 25:ac5b0a371348 75 /**
mbed_official 25:ac5b0a371348 76 * @}
mbed_official 25:ac5b0a371348 77 */
mbed_official 25:ac5b0a371348 78
mbed_official 25:ac5b0a371348 79 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 25:ac5b0a371348 80 * @{
mbed_official 25:ac5b0a371348 81 */
mbed_official 25:ac5b0a371348 82
mbed_official 25:ac5b0a371348 83 /**
mbed_official 25:ac5b0a371348 84 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
mbed_official 25:ac5b0a371348 85 * in @ref Library_configuration_section
mbed_official 25:ac5b0a371348 86 */
mbed_official 25:ac5b0a371348 87 typedef enum
mbed_official 25:ac5b0a371348 88 {
mbed_official 25:ac5b0a371348 89 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 25:ac5b0a371348 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 25:ac5b0a371348 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 25:ac5b0a371348 92 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 25:ac5b0a371348 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 25:ac5b0a371348 94 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 25:ac5b0a371348 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 25:ac5b0a371348 96 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 25:ac5b0a371348 97 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 25:ac5b0a371348 98 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 25:ac5b0a371348 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 25:ac5b0a371348 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 25:ac5b0a371348 101 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 25:ac5b0a371348 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 25:ac5b0a371348 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 25:ac5b0a371348 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 25:ac5b0a371348 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 25:ac5b0a371348 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 25:ac5b0a371348 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 25:ac5b0a371348 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 25:ac5b0a371348 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 25:ac5b0a371348 110 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 25:ac5b0a371348 111 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 25:ac5b0a371348 112 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 25:ac5b0a371348 113 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 25:ac5b0a371348 114 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 25:ac5b0a371348 115 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 25:ac5b0a371348 116 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 25:ac5b0a371348 117 ADC_IRQn = 18, /*!< ADC1 global Interrupts */
mbed_official 25:ac5b0a371348 118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 25:ac5b0a371348 119 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 25:ac5b0a371348 120 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
mbed_official 25:ac5b0a371348 121 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 25:ac5b0a371348 122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 25:ac5b0a371348 123 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 25:ac5b0a371348 124 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 25:ac5b0a371348 125 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 25:ac5b0a371348 126 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 25:ac5b0a371348 127 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 25:ac5b0a371348 128 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 25:ac5b0a371348 129 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 25:ac5b0a371348 130 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 25:ac5b0a371348 131 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 25:ac5b0a371348 132 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 25:ac5b0a371348 133 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 25:ac5b0a371348 134 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 25:ac5b0a371348 135 TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
mbed_official 25:ac5b0a371348 136 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 25:ac5b0a371348 137 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 25:ac5b0a371348 138 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 25:ac5b0a371348 139 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 25:ac5b0a371348 140 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 25:ac5b0a371348 141 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 25:ac5b0a371348 142 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 25:ac5b0a371348 143 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 25:ac5b0a371348 144 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 25:ac5b0a371348 145 RNG_IRQn = 80, /*!< RNG global Interrupt */
mbed_official 25:ac5b0a371348 146 FPU_IRQn = 81, /*!< FPU global interrupt */
mbed_official 25:ac5b0a371348 147 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
mbed_official 25:ac5b0a371348 148 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
mbed_official 25:ac5b0a371348 149 FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
mbed_official 25:ac5b0a371348 150 LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
mbed_official 25:ac5b0a371348 151 } IRQn_Type;
mbed_official 25:ac5b0a371348 152
mbed_official 25:ac5b0a371348 153 /**
mbed_official 25:ac5b0a371348 154 * @}
mbed_official 25:ac5b0a371348 155 */
mbed_official 25:ac5b0a371348 156
mbed_official 25:ac5b0a371348 157 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 25:ac5b0a371348 158 #include "system_stm32f4xx.h"
mbed_official 25:ac5b0a371348 159 #include <stdint.h>
mbed_official 25:ac5b0a371348 160
mbed_official 25:ac5b0a371348 161 /** @addtogroup Peripheral_registers_structures
mbed_official 25:ac5b0a371348 162 * @{
mbed_official 25:ac5b0a371348 163 */
mbed_official 25:ac5b0a371348 164
mbed_official 25:ac5b0a371348 165 /**
mbed_official 25:ac5b0a371348 166 * @brief Analog to Digital Converter
mbed_official 25:ac5b0a371348 167 */
mbed_official 25:ac5b0a371348 168
mbed_official 25:ac5b0a371348 169 typedef struct
mbed_official 25:ac5b0a371348 170 {
mbed_official 25:ac5b0a371348 171 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 172 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 173 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 174 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 175 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 176 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 177 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 178 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 179 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 180 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 181 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 182 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 183 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 184 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 185 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 25:ac5b0a371348 186 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 25:ac5b0a371348 187 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 188 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 189 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 25:ac5b0a371348 190 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 25:ac5b0a371348 191 } ADC_TypeDef;
mbed_official 25:ac5b0a371348 192
mbed_official 25:ac5b0a371348 193 typedef struct
mbed_official 25:ac5b0a371348 194 {
mbed_official 25:ac5b0a371348 195 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 25:ac5b0a371348 196 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 25:ac5b0a371348 197 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 25:ac5b0a371348 198 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 25:ac5b0a371348 199 } ADC_Common_TypeDef;
mbed_official 25:ac5b0a371348 200
mbed_official 25:ac5b0a371348 201 /**
mbed_official 25:ac5b0a371348 202 * @brief CRC calculation unit
mbed_official 25:ac5b0a371348 203 */
mbed_official 25:ac5b0a371348 204
mbed_official 25:ac5b0a371348 205 typedef struct
mbed_official 25:ac5b0a371348 206 {
mbed_official 25:ac5b0a371348 207 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 208 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 209 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 25:ac5b0a371348 210 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 25:ac5b0a371348 211 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 212 } CRC_TypeDef;
mbed_official 25:ac5b0a371348 213
mbed_official 25:ac5b0a371348 214 /**
mbed_official 25:ac5b0a371348 215 * @brief Digital to Analog Converter
mbed_official 25:ac5b0a371348 216 */
mbed_official 25:ac5b0a371348 217
mbed_official 25:ac5b0a371348 218 typedef struct
mbed_official 25:ac5b0a371348 219 {
mbed_official 25:ac5b0a371348 220 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 221 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 222 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 223 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 224 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 225 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 226 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 227 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 228 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 229 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 230 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 231 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 232 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 233 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 234 } DAC_TypeDef;
mbed_official 25:ac5b0a371348 235
mbed_official 25:ac5b0a371348 236 /**
mbed_official 25:ac5b0a371348 237 * @brief Debug MCU
mbed_official 25:ac5b0a371348 238 */
mbed_official 25:ac5b0a371348 239
mbed_official 25:ac5b0a371348 240 typedef struct
mbed_official 25:ac5b0a371348 241 {
mbed_official 25:ac5b0a371348 242 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 243 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 244 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 245 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 246 }DBGMCU_TypeDef;
mbed_official 25:ac5b0a371348 247
mbed_official 25:ac5b0a371348 248
mbed_official 25:ac5b0a371348 249 /**
mbed_official 25:ac5b0a371348 250 * @brief DMA Controller
mbed_official 25:ac5b0a371348 251 */
mbed_official 25:ac5b0a371348 252
mbed_official 25:ac5b0a371348 253 typedef struct
mbed_official 25:ac5b0a371348 254 {
mbed_official 25:ac5b0a371348 255 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 25:ac5b0a371348 256 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 25:ac5b0a371348 257 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 25:ac5b0a371348 258 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 25:ac5b0a371348 259 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 25:ac5b0a371348 260 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 25:ac5b0a371348 261 } DMA_Stream_TypeDef;
mbed_official 25:ac5b0a371348 262
mbed_official 25:ac5b0a371348 263 typedef struct
mbed_official 25:ac5b0a371348 264 {
mbed_official 25:ac5b0a371348 265 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 266 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 267 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 268 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 269 } DMA_TypeDef;
mbed_official 25:ac5b0a371348 270
mbed_official 25:ac5b0a371348 271
mbed_official 25:ac5b0a371348 272 /**
mbed_official 25:ac5b0a371348 273 * @brief External Interrupt/Event Controller
mbed_official 25:ac5b0a371348 274 */
mbed_official 25:ac5b0a371348 275
mbed_official 25:ac5b0a371348 276 typedef struct
mbed_official 25:ac5b0a371348 277 {
mbed_official 25:ac5b0a371348 278 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 279 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 280 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 281 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 282 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 283 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 284 } EXTI_TypeDef;
mbed_official 25:ac5b0a371348 285
mbed_official 25:ac5b0a371348 286 /**
mbed_official 25:ac5b0a371348 287 * @brief FLASH Registers
mbed_official 25:ac5b0a371348 288 */
mbed_official 25:ac5b0a371348 289
mbed_official 25:ac5b0a371348 290 typedef struct
mbed_official 25:ac5b0a371348 291 {
mbed_official 25:ac5b0a371348 292 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 293 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 294 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 295 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 296 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 297 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 25:ac5b0a371348 298 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 299 } FLASH_TypeDef;
mbed_official 25:ac5b0a371348 300
mbed_official 25:ac5b0a371348 301 /**
mbed_official 25:ac5b0a371348 302 * @brief General Purpose I/O
mbed_official 25:ac5b0a371348 303 */
mbed_official 25:ac5b0a371348 304
mbed_official 25:ac5b0a371348 305 typedef struct
mbed_official 25:ac5b0a371348 306 {
mbed_official 25:ac5b0a371348 307 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 308 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 309 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 310 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 311 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 312 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 313 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 314 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 315 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 25:ac5b0a371348 316 } GPIO_TypeDef;
mbed_official 25:ac5b0a371348 317
mbed_official 25:ac5b0a371348 318 /**
mbed_official 25:ac5b0a371348 319 * @brief System configuration controller
mbed_official 25:ac5b0a371348 320 */
mbed_official 25:ac5b0a371348 321
mbed_official 25:ac5b0a371348 322 typedef struct
mbed_official 25:ac5b0a371348 323 {
mbed_official 25:ac5b0a371348 324 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 325 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 326 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 25:ac5b0a371348 327 uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 25:ac5b0a371348 328 uint32_t CFGR2; /*!< Reserved, 0x1C */
mbed_official 25:ac5b0a371348 329 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 330 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
mbed_official 25:ac5b0a371348 331 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 332 } SYSCFG_TypeDef;
mbed_official 25:ac5b0a371348 333
mbed_official 25:ac5b0a371348 334 /**
mbed_official 25:ac5b0a371348 335 * @brief Inter-integrated Circuit Interface
mbed_official 25:ac5b0a371348 336 */
mbed_official 25:ac5b0a371348 337
mbed_official 25:ac5b0a371348 338 typedef struct
mbed_official 25:ac5b0a371348 339 {
mbed_official 25:ac5b0a371348 340 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 341 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 342 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 343 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 344 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 345 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 346 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 347 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 348 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 349 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 350 } I2C_TypeDef;
mbed_official 25:ac5b0a371348 351
mbed_official 25:ac5b0a371348 352 /**
mbed_official 25:ac5b0a371348 353 * @brief Inter-integrated Circuit Interface
mbed_official 25:ac5b0a371348 354 */
mbed_official 25:ac5b0a371348 355
mbed_official 25:ac5b0a371348 356 typedef struct
mbed_official 25:ac5b0a371348 357 {
mbed_official 25:ac5b0a371348 358 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 359 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 360 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 361 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 362 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 363 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 364 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 365 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 366 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 367 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 368 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 369 } FMPI2C_TypeDef;
mbed_official 25:ac5b0a371348 370
mbed_official 25:ac5b0a371348 371 /**
mbed_official 25:ac5b0a371348 372 * @brief Independent WATCHDOG
mbed_official 25:ac5b0a371348 373 */
mbed_official 25:ac5b0a371348 374
mbed_official 25:ac5b0a371348 375 typedef struct
mbed_official 25:ac5b0a371348 376 {
mbed_official 25:ac5b0a371348 377 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 378 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 379 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 380 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 381 } IWDG_TypeDef;
mbed_official 25:ac5b0a371348 382
mbed_official 25:ac5b0a371348 383 /**
mbed_official 25:ac5b0a371348 384 * @brief Power Control
mbed_official 25:ac5b0a371348 385 */
mbed_official 25:ac5b0a371348 386
mbed_official 25:ac5b0a371348 387 typedef struct
mbed_official 25:ac5b0a371348 388 {
mbed_official 25:ac5b0a371348 389 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 390 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 391 } PWR_TypeDef;
mbed_official 25:ac5b0a371348 392
mbed_official 25:ac5b0a371348 393 /**
mbed_official 25:ac5b0a371348 394 * @brief Reset and Clock Control
mbed_official 25:ac5b0a371348 395 */
mbed_official 25:ac5b0a371348 396
mbed_official 25:ac5b0a371348 397 typedef struct
mbed_official 25:ac5b0a371348 398 {
mbed_official 25:ac5b0a371348 399 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 400 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 401 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 402 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 403 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 404 uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
mbed_official 25:ac5b0a371348 405 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 406 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 407 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 25:ac5b0a371348 408 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 409 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
mbed_official 25:ac5b0a371348 410 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 411 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 412 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 25:ac5b0a371348 413 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 25:ac5b0a371348 414 uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
mbed_official 25:ac5b0a371348 415 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 25:ac5b0a371348 416 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 25:ac5b0a371348 417 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 25:ac5b0a371348 418 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 25:ac5b0a371348 419 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 25:ac5b0a371348 420 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 25:ac5b0a371348 421 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 25:ac5b0a371348 422 uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
mbed_official 25:ac5b0a371348 423 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
mbed_official 25:ac5b0a371348 424 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
mbed_official 25:ac5b0a371348 425 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
mbed_official 25:ac5b0a371348 426
mbed_official 25:ac5b0a371348 427 } RCC_TypeDef;
mbed_official 25:ac5b0a371348 428
mbed_official 25:ac5b0a371348 429 /**
mbed_official 25:ac5b0a371348 430 * @brief Real-Time Clock
mbed_official 25:ac5b0a371348 431 */
mbed_official 25:ac5b0a371348 432
mbed_official 25:ac5b0a371348 433 typedef struct
mbed_official 25:ac5b0a371348 434 {
mbed_official 25:ac5b0a371348 435 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 436 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 437 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 438 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 439 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 440 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 441 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 442 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 443 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 444 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 445 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 446 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 447 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 448 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 449 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 25:ac5b0a371348 450 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 25:ac5b0a371348 451 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 452 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 453 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 25:ac5b0a371348 454 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 25:ac5b0a371348 455 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
mbed_official 25:ac5b0a371348 456 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 25:ac5b0a371348 457 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 25:ac5b0a371348 458 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 25:ac5b0a371348 459 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 25:ac5b0a371348 460 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 25:ac5b0a371348 461 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 25:ac5b0a371348 462 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 25:ac5b0a371348 463 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 25:ac5b0a371348 464 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 25:ac5b0a371348 465 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 25:ac5b0a371348 466 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 25:ac5b0a371348 467 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 25:ac5b0a371348 468 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 25:ac5b0a371348 469 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 25:ac5b0a371348 470 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 25:ac5b0a371348 471 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 25:ac5b0a371348 472 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 25:ac5b0a371348 473 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 25:ac5b0a371348 474 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 25:ac5b0a371348 475 } RTC_TypeDef;
mbed_official 25:ac5b0a371348 476
mbed_official 25:ac5b0a371348 477 /**
mbed_official 25:ac5b0a371348 478 * @brief Serial Peripheral Interface
mbed_official 25:ac5b0a371348 479 */
mbed_official 25:ac5b0a371348 480
mbed_official 25:ac5b0a371348 481 typedef struct
mbed_official 25:ac5b0a371348 482 {
mbed_official 25:ac5b0a371348 483 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 25:ac5b0a371348 484 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 485 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 486 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 487 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 25:ac5b0a371348 488 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 25:ac5b0a371348 489 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 25:ac5b0a371348 490 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 491 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 492 } SPI_TypeDef;
mbed_official 25:ac5b0a371348 493
mbed_official 25:ac5b0a371348 494 /**
mbed_official 25:ac5b0a371348 495 * @brief TIM
mbed_official 25:ac5b0a371348 496 */
mbed_official 25:ac5b0a371348 497
mbed_official 25:ac5b0a371348 498 typedef struct
mbed_official 25:ac5b0a371348 499 {
mbed_official 25:ac5b0a371348 500 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 501 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 502 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 503 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 504 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 505 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 506 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 507 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 508 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 509 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 25:ac5b0a371348 510 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 25:ac5b0a371348 511 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 25:ac5b0a371348 512 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 25:ac5b0a371348 513 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 25:ac5b0a371348 514 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 25:ac5b0a371348 515 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 25:ac5b0a371348 516 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 25:ac5b0a371348 517 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 25:ac5b0a371348 518 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 25:ac5b0a371348 519 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 25:ac5b0a371348 520 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 25:ac5b0a371348 521 } TIM_TypeDef;
mbed_official 25:ac5b0a371348 522
mbed_official 25:ac5b0a371348 523 /**
mbed_official 25:ac5b0a371348 524 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 25:ac5b0a371348 525 */
mbed_official 25:ac5b0a371348 526
mbed_official 25:ac5b0a371348 527 typedef struct
mbed_official 25:ac5b0a371348 528 {
mbed_official 25:ac5b0a371348 529 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 530 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 531 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 532 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 533 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 534 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 535 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 536 } USART_TypeDef;
mbed_official 25:ac5b0a371348 537
mbed_official 25:ac5b0a371348 538 /**
mbed_official 25:ac5b0a371348 539 * @brief Window WATCHDOG
mbed_official 25:ac5b0a371348 540 */
mbed_official 25:ac5b0a371348 541
mbed_official 25:ac5b0a371348 542 typedef struct
mbed_official 25:ac5b0a371348 543 {
mbed_official 25:ac5b0a371348 544 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 545 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 546 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 547 } WWDG_TypeDef;
mbed_official 25:ac5b0a371348 548
mbed_official 25:ac5b0a371348 549
mbed_official 25:ac5b0a371348 550 /**
mbed_official 25:ac5b0a371348 551 * @brief RNG
mbed_official 25:ac5b0a371348 552 */
mbed_official 25:ac5b0a371348 553
mbed_official 25:ac5b0a371348 554 typedef struct
mbed_official 25:ac5b0a371348 555 {
mbed_official 25:ac5b0a371348 556 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 557 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 558 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 559 } RNG_TypeDef;
mbed_official 25:ac5b0a371348 560
mbed_official 25:ac5b0a371348 561
mbed_official 25:ac5b0a371348 562 /**
mbed_official 25:ac5b0a371348 563 * @brief LPTIMER
mbed_official 25:ac5b0a371348 564 */
mbed_official 25:ac5b0a371348 565 typedef struct
mbed_official 25:ac5b0a371348 566 {
mbed_official 25:ac5b0a371348 567 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
mbed_official 25:ac5b0a371348 568 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
mbed_official 25:ac5b0a371348 569 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
mbed_official 25:ac5b0a371348 570 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
mbed_official 25:ac5b0a371348 571 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
mbed_official 25:ac5b0a371348 572 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
mbed_official 25:ac5b0a371348 573 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
mbed_official 25:ac5b0a371348 574 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
mbed_official 25:ac5b0a371348 575 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
mbed_official 25:ac5b0a371348 576 } LPTIM_TypeDef;
mbed_official 25:ac5b0a371348 577
mbed_official 25:ac5b0a371348 578 /**
mbed_official 25:ac5b0a371348 579 * @brief Peripheral_memory_map
mbed_official 25:ac5b0a371348 580 */
<> 144:ef7eb2e8f9f7 581 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
<> 144:ef7eb2e8f9f7 582 #define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 583 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
<> 144:ef7eb2e8f9f7 584 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */
<> 144:ef7eb2e8f9f7 585 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
<> 144:ef7eb2e8f9f7 586 #define FLASH_END 0x0801FFFFU /*!< FLASH end address */
mbed_official 25:ac5b0a371348 587
mbed_official 25:ac5b0a371348 588 /* Legacy defines */
mbed_official 25:ac5b0a371348 589 #define SRAM_BASE SRAM1_BASE
mbed_official 25:ac5b0a371348 590 #define SRAM_BB_BASE SRAM1_BB_BASE
mbed_official 25:ac5b0a371348 591
mbed_official 25:ac5b0a371348 592 /*!< Peripheral memory map */
mbed_official 25:ac5b0a371348 593 #define APB1PERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 594 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 144:ef7eb2e8f9f7 595 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
mbed_official 25:ac5b0a371348 596
mbed_official 25:ac5b0a371348 597 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 598 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 599 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 600 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
<> 144:ef7eb2e8f9f7 601 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 602 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 603 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 604 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 605 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 606 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 607 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 608 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 609 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 610 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 144:ef7eb2e8f9f7 611 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
mbed_official 25:ac5b0a371348 612 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 613 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 614 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 615 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 616 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 617 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
<> 144:ef7eb2e8f9f7 618 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 619 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 620 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 621 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 622 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 623 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
mbed_official 25:ac5b0a371348 624
mbed_official 25:ac5b0a371348 625 /*!< AHB1 peripherals */
<> 144:ef7eb2e8f9f7 626 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 627 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 628 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 629 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 630 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 631 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 632 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 633 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 634 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 635 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 636 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 637 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 638 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 639 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 640 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 641 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 642 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 643 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 644 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 645 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 646 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 647 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 648 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 649 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 650 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 651 #define RNG_BASE (PERIPH_BASE + 0x80000U)
mbed_official 25:ac5b0a371348 652
mbed_official 25:ac5b0a371348 653 /* Debug MCU registers base address */
<> 144:ef7eb2e8f9f7 654 #define DBGMCU_BASE 0xE0042000U
mbed_official 25:ac5b0a371348 655
mbed_official 25:ac5b0a371348 656 /**
mbed_official 25:ac5b0a371348 657 * @}
mbed_official 25:ac5b0a371348 658 */
mbed_official 25:ac5b0a371348 659
mbed_official 25:ac5b0a371348 660 /** @addtogroup Peripheral_declaration
mbed_official 25:ac5b0a371348 661 * @{
mbed_official 25:ac5b0a371348 662 */
mbed_official 25:ac5b0a371348 663 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 25:ac5b0a371348 664 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 25:ac5b0a371348 665 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 25:ac5b0a371348 666 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 25:ac5b0a371348 667 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 25:ac5b0a371348 668 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 25:ac5b0a371348 669 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 25:ac5b0a371348 670 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 25:ac5b0a371348 671 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 25:ac5b0a371348 672 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
mbed_official 25:ac5b0a371348 673 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
mbed_official 25:ac5b0a371348 674 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 25:ac5b0a371348 675 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 25:ac5b0a371348 676 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 25:ac5b0a371348 677 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 25:ac5b0a371348 678 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 25:ac5b0a371348 679 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 25:ac5b0a371348 680 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 25:ac5b0a371348 681 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 25:ac5b0a371348 682 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 25:ac5b0a371348 683 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 25:ac5b0a371348 684 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 25:ac5b0a371348 685 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 25:ac5b0a371348 686 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
mbed_official 25:ac5b0a371348 687 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 25:ac5b0a371348 688 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 25:ac5b0a371348 689 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 25:ac5b0a371348 690 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 25:ac5b0a371348 691 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 25:ac5b0a371348 692 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 25:ac5b0a371348 693 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 25:ac5b0a371348 694 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 25:ac5b0a371348 695 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 25:ac5b0a371348 696 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 25:ac5b0a371348 697 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 25:ac5b0a371348 698 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 25:ac5b0a371348 699 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 25:ac5b0a371348 700 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 25:ac5b0a371348 701 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 25:ac5b0a371348 702 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 25:ac5b0a371348 703 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 25:ac5b0a371348 704 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 25:ac5b0a371348 705 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 25:ac5b0a371348 706 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 25:ac5b0a371348 707 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 25:ac5b0a371348 708 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 25:ac5b0a371348 709 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 25:ac5b0a371348 710 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 25:ac5b0a371348 711 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 25:ac5b0a371348 712 #define RNG ((RNG_TypeDef *) RNG_BASE)
mbed_official 25:ac5b0a371348 713
mbed_official 25:ac5b0a371348 714 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 25:ac5b0a371348 715
mbed_official 25:ac5b0a371348 716 /**
mbed_official 25:ac5b0a371348 717 * @}
mbed_official 25:ac5b0a371348 718 */
mbed_official 25:ac5b0a371348 719
mbed_official 25:ac5b0a371348 720 /** @addtogroup Exported_constants
mbed_official 25:ac5b0a371348 721 * @{
mbed_official 25:ac5b0a371348 722 */
mbed_official 25:ac5b0a371348 723
mbed_official 25:ac5b0a371348 724 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 25:ac5b0a371348 725 * @{
mbed_official 25:ac5b0a371348 726 */
mbed_official 25:ac5b0a371348 727
mbed_official 25:ac5b0a371348 728 /******************************************************************************/
mbed_official 25:ac5b0a371348 729 /* Peripheral Registers_Bits_Definition */
mbed_official 25:ac5b0a371348 730 /******************************************************************************/
mbed_official 25:ac5b0a371348 731
mbed_official 25:ac5b0a371348 732 /******************************************************************************/
mbed_official 25:ac5b0a371348 733 /* */
mbed_official 25:ac5b0a371348 734 /* Analog to Digital Converter */
mbed_official 25:ac5b0a371348 735 /* */
mbed_official 25:ac5b0a371348 736 /******************************************************************************/
mbed_official 25:ac5b0a371348 737 /******************** Bit definition for ADC_SR register ********************/
<> 144:ef7eb2e8f9f7 738 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
<> 144:ef7eb2e8f9f7 739 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
<> 144:ef7eb2e8f9f7 740 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 741 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
<> 144:ef7eb2e8f9f7 742 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
<> 144:ef7eb2e8f9f7 743 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
mbed_official 25:ac5b0a371348 744
mbed_official 25:ac5b0a371348 745 /******************* Bit definition for ADC_CR1 register ********************/
<> 144:ef7eb2e8f9f7 746 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 144:ef7eb2e8f9f7 747 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 748 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 749 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 750 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 751 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 752 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
<> 144:ef7eb2e8f9f7 753 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
<> 144:ef7eb2e8f9f7 754 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
<> 144:ef7eb2e8f9f7 755 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
<> 144:ef7eb2e8f9f7 756 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
<> 144:ef7eb2e8f9f7 757 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
<> 144:ef7eb2e8f9f7 758 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
<> 144:ef7eb2e8f9f7 759 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
<> 144:ef7eb2e8f9f7 760 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
<> 144:ef7eb2e8f9f7 761 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 762 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 763 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 764 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
<> 144:ef7eb2e8f9f7 765 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
<> 144:ef7eb2e8f9f7 766 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
<> 144:ef7eb2e8f9f7 767 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 768 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 769 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
mbed_official 25:ac5b0a371348 770
mbed_official 25:ac5b0a371348 771 /******************* Bit definition for ADC_CR2 register ********************/
<> 144:ef7eb2e8f9f7 772 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
<> 144:ef7eb2e8f9f7 773 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
<> 144:ef7eb2e8f9f7 774 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
<> 144:ef7eb2e8f9f7 775 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
<> 144:ef7eb2e8f9f7 776 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
<> 144:ef7eb2e8f9f7 777 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
<> 144:ef7eb2e8f9f7 778 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
<> 144:ef7eb2e8f9f7 779 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 780 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 781 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 782 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 783 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
<> 144:ef7eb2e8f9f7 784 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 785 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 786 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
<> 144:ef7eb2e8f9f7 787 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
<> 144:ef7eb2e8f9f7 788 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 789 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 790 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 791 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 792 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
<> 144:ef7eb2e8f9f7 793 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 794 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 795 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
mbed_official 25:ac5b0a371348 796
mbed_official 25:ac5b0a371348 797 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 144:ef7eb2e8f9f7 798 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
<> 144:ef7eb2e8f9f7 799 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 800 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 801 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 802 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
<> 144:ef7eb2e8f9f7 803 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 804 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 805 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 806 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
<> 144:ef7eb2e8f9f7 807 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 808 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 809 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 810 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
<> 144:ef7eb2e8f9f7 811 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 812 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 813 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 814 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
<> 144:ef7eb2e8f9f7 815 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 816 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 817 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 818 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
<> 144:ef7eb2e8f9f7 819 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 820 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 821 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 822 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
<> 144:ef7eb2e8f9f7 823 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 824 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 825 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 826 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
<> 144:ef7eb2e8f9f7 827 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 828 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 829 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 830 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
<> 144:ef7eb2e8f9f7 831 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 832 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 833 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
mbed_official 25:ac5b0a371348 834
mbed_official 25:ac5b0a371348 835 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 144:ef7eb2e8f9f7 836 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
<> 144:ef7eb2e8f9f7 837 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 838 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 839 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 840 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
<> 144:ef7eb2e8f9f7 841 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 842 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 843 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 844 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
<> 144:ef7eb2e8f9f7 845 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 846 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 847 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 848 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
<> 144:ef7eb2e8f9f7 849 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 850 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 851 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 852 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
<> 144:ef7eb2e8f9f7 853 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 854 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 855 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 856 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
<> 144:ef7eb2e8f9f7 857 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 858 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 859 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 860 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
<> 144:ef7eb2e8f9f7 861 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 862 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 863 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 864 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
<> 144:ef7eb2e8f9f7 865 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 866 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 867 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 868 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
<> 144:ef7eb2e8f9f7 869 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 870 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 871 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 872 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
<> 144:ef7eb2e8f9f7 873 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 874 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 875 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
mbed_official 25:ac5b0a371348 876
mbed_official 25:ac5b0a371348 877 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 144:ef7eb2e8f9f7 878 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
mbed_official 25:ac5b0a371348 879
mbed_official 25:ac5b0a371348 880 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 144:ef7eb2e8f9f7 881 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
mbed_official 25:ac5b0a371348 882
mbed_official 25:ac5b0a371348 883 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 144:ef7eb2e8f9f7 884 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
mbed_official 25:ac5b0a371348 885
mbed_official 25:ac5b0a371348 886 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 144:ef7eb2e8f9f7 887 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
mbed_official 25:ac5b0a371348 888
mbed_official 25:ac5b0a371348 889 /******************* Bit definition for ADC_HTR register ********************/
<> 144:ef7eb2e8f9f7 890 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
mbed_official 25:ac5b0a371348 891
mbed_official 25:ac5b0a371348 892 /******************* Bit definition for ADC_LTR register ********************/
<> 144:ef7eb2e8f9f7 893 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
mbed_official 25:ac5b0a371348 894
mbed_official 25:ac5b0a371348 895 /******************* Bit definition for ADC_SQR1 register *******************/
<> 144:ef7eb2e8f9f7 896 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 897 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 898 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 899 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 900 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 901 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 902 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 903 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 904 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 905 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 906 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 907 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 908 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 909 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 910 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 911 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 912 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 913 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 914 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 915 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 916 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 917 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 918 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 919 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 920 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
<> 144:ef7eb2e8f9f7 921 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 922 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 923 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 924 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
mbed_official 25:ac5b0a371348 925
mbed_official 25:ac5b0a371348 926 /******************* Bit definition for ADC_SQR2 register *******************/
<> 144:ef7eb2e8f9f7 927 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 928 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 929 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 930 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 931 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 932 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 933 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 934 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 935 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 936 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 937 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 938 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 939 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 940 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 941 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 942 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 943 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 944 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 945 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 946 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 947 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 948 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 949 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 950 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 951 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 952 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 953 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 954 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 955 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 956 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 957 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 958 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 959 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 960 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 961 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 962 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
mbed_official 25:ac5b0a371348 963
mbed_official 25:ac5b0a371348 964 /******************* Bit definition for ADC_SQR3 register *******************/
<> 144:ef7eb2e8f9f7 965 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 966 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 967 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 968 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 969 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 970 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 971 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 972 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 973 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 974 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 975 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 976 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 977 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 978 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 979 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 980 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 981 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 982 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 983 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 984 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 985 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 986 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 987 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 988 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 989 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 990 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 991 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 992 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 993 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 994 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 995 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 996 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 997 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 998 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 999 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1000 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
mbed_official 25:ac5b0a371348 1001
mbed_official 25:ac5b0a371348 1002 /******************* Bit definition for ADC_JSQR register *******************/
<> 144:ef7eb2e8f9f7 1003 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1004 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1005 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1006 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1007 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1008 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1009 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1010 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1011 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1012 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1013 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1014 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1015 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1016 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1017 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1018 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1019 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1020 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1021 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1022 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1023 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1024 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1025 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1026 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1027 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
<> 144:ef7eb2e8f9f7 1028 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1029 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
mbed_official 25:ac5b0a371348 1030
mbed_official 25:ac5b0a371348 1031 /******************* Bit definition for ADC_JDR1 register *******************/
<> 144:ef7eb2e8f9f7 1032 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
mbed_official 25:ac5b0a371348 1033
mbed_official 25:ac5b0a371348 1034 /******************* Bit definition for ADC_JDR2 register *******************/
<> 144:ef7eb2e8f9f7 1035 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
mbed_official 25:ac5b0a371348 1036
mbed_official 25:ac5b0a371348 1037 /******************* Bit definition for ADC_JDR3 register *******************/
<> 144:ef7eb2e8f9f7 1038 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
mbed_official 25:ac5b0a371348 1039
mbed_official 25:ac5b0a371348 1040 /******************* Bit definition for ADC_JDR4 register *******************/
<> 144:ef7eb2e8f9f7 1041 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
mbed_official 25:ac5b0a371348 1042
mbed_official 25:ac5b0a371348 1043 /******************** Bit definition for ADC_DR register ********************/
<> 144:ef7eb2e8f9f7 1044 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
<> 144:ef7eb2e8f9f7 1045 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
mbed_official 25:ac5b0a371348 1046
mbed_official 25:ac5b0a371348 1047 /******************* Bit definition for ADC_CSR register ********************/
<> 144:ef7eb2e8f9f7 1048 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1049 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
<> 144:ef7eb2e8f9f7 1050 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1051 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1052 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1053 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1054 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1055 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
<> 144:ef7eb2e8f9f7 1056 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1057 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1058 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1059 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1060 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1061 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
<> 144:ef7eb2e8f9f7 1062 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1063 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1064 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1065 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1068 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 144:ef7eb2e8f9f7 1069 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 144:ef7eb2e8f9f7 1070 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
mbed_official 25:ac5b0a371348 1071
mbed_official 25:ac5b0a371348 1072 /******************* Bit definition for ADC_CCR register ********************/
<> 144:ef7eb2e8f9f7 1073 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
<> 144:ef7eb2e8f9f7 1074 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1075 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1076 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1077 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1078 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1079 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
<> 144:ef7eb2e8f9f7 1080 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1081 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1082 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1083 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1084 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
<> 144:ef7eb2e8f9f7 1085 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
<> 144:ef7eb2e8f9f7 1086 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1087 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1088 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
<> 144:ef7eb2e8f9f7 1089 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1090 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1091 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
<> 144:ef7eb2e8f9f7 1092 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
mbed_official 25:ac5b0a371348 1093
mbed_official 25:ac5b0a371348 1094 /******************* Bit definition for ADC_CDR register ********************/
<> 144:ef7eb2e8f9f7 1095 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
<> 144:ef7eb2e8f9f7 1096 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
mbed_official 25:ac5b0a371348 1097
mbed_official 25:ac5b0a371348 1098 /******************************************************************************/
mbed_official 25:ac5b0a371348 1099 /* */
mbed_official 25:ac5b0a371348 1100 /* CRC calculation unit */
mbed_official 25:ac5b0a371348 1101 /* */
mbed_official 25:ac5b0a371348 1102 /******************************************************************************/
mbed_official 25:ac5b0a371348 1103 /******************* Bit definition for CRC_DR register *********************/
<> 144:ef7eb2e8f9f7 1104 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
mbed_official 25:ac5b0a371348 1105
mbed_official 25:ac5b0a371348 1106
mbed_official 25:ac5b0a371348 1107 /******************* Bit definition for CRC_IDR register ********************/
<> 144:ef7eb2e8f9f7 1108 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
mbed_official 25:ac5b0a371348 1109
mbed_official 25:ac5b0a371348 1110
mbed_official 25:ac5b0a371348 1111 /******************** Bit definition for CRC_CR register ********************/
<> 144:ef7eb2e8f9f7 1112 #define CRC_CR_RESET 0x01U /*!< RESET bit */
mbed_official 25:ac5b0a371348 1113
mbed_official 25:ac5b0a371348 1114 /******************************************************************************/
mbed_official 25:ac5b0a371348 1115 /* */
mbed_official 25:ac5b0a371348 1116 /* Debug MCU */
mbed_official 25:ac5b0a371348 1117 /* */
mbed_official 25:ac5b0a371348 1118 /******************************************************************************/
mbed_official 25:ac5b0a371348 1119
mbed_official 25:ac5b0a371348 1120 /******************************************************************************/
mbed_official 25:ac5b0a371348 1121 /* */
mbed_official 25:ac5b0a371348 1122 /* DMA Controller */
mbed_official 25:ac5b0a371348 1123 /* */
mbed_official 25:ac5b0a371348 1124 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1125 /******************** Bits definition for DMA_SxCR register *****************/
<> 144:ef7eb2e8f9f7 1126 #define DMA_SxCR_CHSEL 0x0E000000U
<> 144:ef7eb2e8f9f7 1127 #define DMA_SxCR_CHSEL_0 0x02000000U
<> 144:ef7eb2e8f9f7 1128 #define DMA_SxCR_CHSEL_1 0x04000000U
<> 144:ef7eb2e8f9f7 1129 #define DMA_SxCR_CHSEL_2 0x08000000U
<> 144:ef7eb2e8f9f7 1130 #define DMA_SxCR_MBURST 0x01800000U
<> 144:ef7eb2e8f9f7 1131 #define DMA_SxCR_MBURST_0 0x00800000U
<> 144:ef7eb2e8f9f7 1132 #define DMA_SxCR_MBURST_1 0x01000000U
<> 144:ef7eb2e8f9f7 1133 #define DMA_SxCR_PBURST 0x00600000U
<> 144:ef7eb2e8f9f7 1134 #define DMA_SxCR_PBURST_0 0x00200000U
<> 144:ef7eb2e8f9f7 1135 #define DMA_SxCR_PBURST_1 0x00400000U
<> 144:ef7eb2e8f9f7 1136 #define DMA_SxCR_CT 0x00080000U
<> 144:ef7eb2e8f9f7 1137 #define DMA_SxCR_DBM 0x00040000U
<> 144:ef7eb2e8f9f7 1138 #define DMA_SxCR_PL 0x00030000U
<> 144:ef7eb2e8f9f7 1139 #define DMA_SxCR_PL_0 0x00010000U
<> 144:ef7eb2e8f9f7 1140 #define DMA_SxCR_PL_1 0x00020000U
<> 144:ef7eb2e8f9f7 1141 #define DMA_SxCR_PINCOS 0x00008000U
<> 144:ef7eb2e8f9f7 1142 #define DMA_SxCR_MSIZE 0x00006000U
<> 144:ef7eb2e8f9f7 1143 #define DMA_SxCR_MSIZE_0 0x00002000U
<> 144:ef7eb2e8f9f7 1144 #define DMA_SxCR_MSIZE_1 0x00004000U
<> 144:ef7eb2e8f9f7 1145 #define DMA_SxCR_PSIZE 0x00001800U
<> 144:ef7eb2e8f9f7 1146 #define DMA_SxCR_PSIZE_0 0x00000800U
<> 144:ef7eb2e8f9f7 1147 #define DMA_SxCR_PSIZE_1 0x00001000U
<> 144:ef7eb2e8f9f7 1148 #define DMA_SxCR_MINC 0x00000400U
<> 144:ef7eb2e8f9f7 1149 #define DMA_SxCR_PINC 0x00000200U
<> 144:ef7eb2e8f9f7 1150 #define DMA_SxCR_CIRC 0x00000100U
<> 144:ef7eb2e8f9f7 1151 #define DMA_SxCR_DIR 0x000000C0U
<> 144:ef7eb2e8f9f7 1152 #define DMA_SxCR_DIR_0 0x00000040U
<> 144:ef7eb2e8f9f7 1153 #define DMA_SxCR_DIR_1 0x00000080U
<> 144:ef7eb2e8f9f7 1154 #define DMA_SxCR_PFCTRL 0x00000020U
<> 144:ef7eb2e8f9f7 1155 #define DMA_SxCR_TCIE 0x00000010U
<> 144:ef7eb2e8f9f7 1156 #define DMA_SxCR_HTIE 0x00000008U
<> 144:ef7eb2e8f9f7 1157 #define DMA_SxCR_TEIE 0x00000004U
<> 144:ef7eb2e8f9f7 1158 #define DMA_SxCR_DMEIE 0x00000002U
<> 144:ef7eb2e8f9f7 1159 #define DMA_SxCR_EN 0x00000001U
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1162 #define DMA_SxCR_ACK 0x00100000U
mbed_official 25:ac5b0a371348 1163
mbed_official 25:ac5b0a371348 1164 /******************** Bits definition for DMA_SxCNDTR register **************/
<> 144:ef7eb2e8f9f7 1165 #define DMA_SxNDT 0x0000FFFFU
<> 144:ef7eb2e8f9f7 1166 #define DMA_SxNDT_0 0x00000001U
<> 144:ef7eb2e8f9f7 1167 #define DMA_SxNDT_1 0x00000002U
<> 144:ef7eb2e8f9f7 1168 #define DMA_SxNDT_2 0x00000004U
<> 144:ef7eb2e8f9f7 1169 #define DMA_SxNDT_3 0x00000008U
<> 144:ef7eb2e8f9f7 1170 #define DMA_SxNDT_4 0x00000010U
<> 144:ef7eb2e8f9f7 1171 #define DMA_SxNDT_5 0x00000020U
<> 144:ef7eb2e8f9f7 1172 #define DMA_SxNDT_6 0x00000040U
<> 144:ef7eb2e8f9f7 1173 #define DMA_SxNDT_7 0x00000080U
<> 144:ef7eb2e8f9f7 1174 #define DMA_SxNDT_8 0x00000100U
<> 144:ef7eb2e8f9f7 1175 #define DMA_SxNDT_9 0x00000200U
<> 144:ef7eb2e8f9f7 1176 #define DMA_SxNDT_10 0x00000400U
<> 144:ef7eb2e8f9f7 1177 #define DMA_SxNDT_11 0x00000800U
<> 144:ef7eb2e8f9f7 1178 #define DMA_SxNDT_12 0x00001000U
<> 144:ef7eb2e8f9f7 1179 #define DMA_SxNDT_13 0x00002000U
<> 144:ef7eb2e8f9f7 1180 #define DMA_SxNDT_14 0x00004000U
<> 144:ef7eb2e8f9f7 1181 #define DMA_SxNDT_15 0x00008000U
mbed_official 25:ac5b0a371348 1182
mbed_official 25:ac5b0a371348 1183 /******************** Bits definition for DMA_SxFCR register ****************/
<> 144:ef7eb2e8f9f7 1184 #define DMA_SxFCR_FEIE 0x00000080U
<> 144:ef7eb2e8f9f7 1185 #define DMA_SxFCR_FS 0x00000038U
<> 144:ef7eb2e8f9f7 1186 #define DMA_SxFCR_FS_0 0x00000008U
<> 144:ef7eb2e8f9f7 1187 #define DMA_SxFCR_FS_1 0x00000010U
<> 144:ef7eb2e8f9f7 1188 #define DMA_SxFCR_FS_2 0x00000020U
<> 144:ef7eb2e8f9f7 1189 #define DMA_SxFCR_DMDIS 0x00000004U
<> 144:ef7eb2e8f9f7 1190 #define DMA_SxFCR_FTH 0x00000003U
<> 144:ef7eb2e8f9f7 1191 #define DMA_SxFCR_FTH_0 0x00000001U
<> 144:ef7eb2e8f9f7 1192 #define DMA_SxFCR_FTH_1 0x00000002U
mbed_official 25:ac5b0a371348 1193
mbed_official 25:ac5b0a371348 1194 /******************** Bits definition for DMA_LISR register *****************/
<> 144:ef7eb2e8f9f7 1195 #define DMA_LISR_TCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 1196 #define DMA_LISR_HTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 1197 #define DMA_LISR_TEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 1198 #define DMA_LISR_DMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 1199 #define DMA_LISR_FEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 1200 #define DMA_LISR_TCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 1201 #define DMA_LISR_HTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 1202 #define DMA_LISR_TEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 1203 #define DMA_LISR_DMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 1204 #define DMA_LISR_FEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 1205 #define DMA_LISR_TCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 1206 #define DMA_LISR_HTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 1207 #define DMA_LISR_TEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 1208 #define DMA_LISR_DMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 1209 #define DMA_LISR_FEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 1210 #define DMA_LISR_TCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 1211 #define DMA_LISR_HTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 1212 #define DMA_LISR_TEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 1213 #define DMA_LISR_DMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 1214 #define DMA_LISR_FEIF0 0x00000001U
mbed_official 25:ac5b0a371348 1215
mbed_official 25:ac5b0a371348 1216 /******************** Bits definition for DMA_HISR register *****************/
<> 144:ef7eb2e8f9f7 1217 #define DMA_HISR_TCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 1218 #define DMA_HISR_HTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 1219 #define DMA_HISR_TEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 1220 #define DMA_HISR_DMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 1221 #define DMA_HISR_FEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 1222 #define DMA_HISR_TCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 1223 #define DMA_HISR_HTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 1224 #define DMA_HISR_TEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 1225 #define DMA_HISR_DMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 1226 #define DMA_HISR_FEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 1227 #define DMA_HISR_TCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 1228 #define DMA_HISR_HTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 1229 #define DMA_HISR_TEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 1230 #define DMA_HISR_DMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 1231 #define DMA_HISR_FEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 1232 #define DMA_HISR_TCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 1233 #define DMA_HISR_HTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 1234 #define DMA_HISR_TEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 1235 #define DMA_HISR_DMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 1236 #define DMA_HISR_FEIF4 0x00000001U
mbed_official 25:ac5b0a371348 1237
mbed_official 25:ac5b0a371348 1238 /******************** Bits definition for DMA_LIFCR register ****************/
<> 144:ef7eb2e8f9f7 1239 #define DMA_LIFCR_CTCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 1240 #define DMA_LIFCR_CHTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 1241 #define DMA_LIFCR_CTEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 1242 #define DMA_LIFCR_CDMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 1243 #define DMA_LIFCR_CFEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 1244 #define DMA_LIFCR_CTCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 1245 #define DMA_LIFCR_CHTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 1246 #define DMA_LIFCR_CTEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 1247 #define DMA_LIFCR_CDMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 1248 #define DMA_LIFCR_CFEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 1249 #define DMA_LIFCR_CTCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 1250 #define DMA_LIFCR_CHTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 1251 #define DMA_LIFCR_CTEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 1252 #define DMA_LIFCR_CDMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 1253 #define DMA_LIFCR_CFEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 1254 #define DMA_LIFCR_CTCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 1255 #define DMA_LIFCR_CHTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 1256 #define DMA_LIFCR_CTEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 1257 #define DMA_LIFCR_CDMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 1258 #define DMA_LIFCR_CFEIF0 0x00000001U
mbed_official 25:ac5b0a371348 1259
mbed_official 25:ac5b0a371348 1260 /******************** Bits definition for DMA_HIFCR register ****************/
<> 144:ef7eb2e8f9f7 1261 #define DMA_HIFCR_CTCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 1262 #define DMA_HIFCR_CHTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 1263 #define DMA_HIFCR_CTEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 1264 #define DMA_HIFCR_CDMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 1265 #define DMA_HIFCR_CFEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 1266 #define DMA_HIFCR_CTCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 1267 #define DMA_HIFCR_CHTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 1268 #define DMA_HIFCR_CTEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 1269 #define DMA_HIFCR_CDMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 1270 #define DMA_HIFCR_CFEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 1271 #define DMA_HIFCR_CTCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 1272 #define DMA_HIFCR_CHTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 1273 #define DMA_HIFCR_CTEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 1274 #define DMA_HIFCR_CDMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 1275 #define DMA_HIFCR_CFEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 1276 #define DMA_HIFCR_CTCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 1277 #define DMA_HIFCR_CHTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 1278 #define DMA_HIFCR_CTEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 1279 #define DMA_HIFCR_CDMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 1280 #define DMA_HIFCR_CFEIF4 0x00000001U
mbed_official 25:ac5b0a371348 1281
mbed_official 25:ac5b0a371348 1282
mbed_official 25:ac5b0a371348 1283 /******************************************************************************/
mbed_official 25:ac5b0a371348 1284 /* */
mbed_official 25:ac5b0a371348 1285 /* External Interrupt/Event Controller */
mbed_official 25:ac5b0a371348 1286 /* */
mbed_official 25:ac5b0a371348 1287 /******************************************************************************/
mbed_official 25:ac5b0a371348 1288 /******************* Bit definition for EXTI_IMR register *******************/
<> 144:ef7eb2e8f9f7 1289 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
<> 144:ef7eb2e8f9f7 1290 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
<> 144:ef7eb2e8f9f7 1291 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
<> 144:ef7eb2e8f9f7 1292 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
<> 144:ef7eb2e8f9f7 1293 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
<> 144:ef7eb2e8f9f7 1294 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
<> 144:ef7eb2e8f9f7 1295 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
<> 144:ef7eb2e8f9f7 1296 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
<> 144:ef7eb2e8f9f7 1297 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
<> 144:ef7eb2e8f9f7 1298 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
<> 144:ef7eb2e8f9f7 1299 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
<> 144:ef7eb2e8f9f7 1300 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
<> 144:ef7eb2e8f9f7 1301 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
<> 144:ef7eb2e8f9f7 1302 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
<> 144:ef7eb2e8f9f7 1303 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
<> 144:ef7eb2e8f9f7 1304 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
<> 144:ef7eb2e8f9f7 1305 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
<> 144:ef7eb2e8f9f7 1306 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
<> 144:ef7eb2e8f9f7 1307 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
<> 144:ef7eb2e8f9f7 1308 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
<> 144:ef7eb2e8f9f7 1309 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
<> 144:ef7eb2e8f9f7 1310 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
<> 144:ef7eb2e8f9f7 1311 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
<> 144:ef7eb2e8f9f7 1312 #define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
mbed_official 25:ac5b0a371348 1313
mbed_official 25:ac5b0a371348 1314 /******************* Bit definition for EXTI_EMR register *******************/
<> 144:ef7eb2e8f9f7 1315 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
<> 144:ef7eb2e8f9f7 1316 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
<> 144:ef7eb2e8f9f7 1317 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
<> 144:ef7eb2e8f9f7 1318 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
<> 144:ef7eb2e8f9f7 1319 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
<> 144:ef7eb2e8f9f7 1320 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
<> 144:ef7eb2e8f9f7 1321 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
<> 144:ef7eb2e8f9f7 1322 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
<> 144:ef7eb2e8f9f7 1323 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
<> 144:ef7eb2e8f9f7 1324 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
<> 144:ef7eb2e8f9f7 1325 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
<> 144:ef7eb2e8f9f7 1326 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
<> 144:ef7eb2e8f9f7 1327 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
<> 144:ef7eb2e8f9f7 1328 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
<> 144:ef7eb2e8f9f7 1329 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
<> 144:ef7eb2e8f9f7 1330 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
<> 144:ef7eb2e8f9f7 1331 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
<> 144:ef7eb2e8f9f7 1332 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
<> 144:ef7eb2e8f9f7 1333 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
<> 144:ef7eb2e8f9f7 1334 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
<> 144:ef7eb2e8f9f7 1335 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
<> 144:ef7eb2e8f9f7 1336 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
<> 144:ef7eb2e8f9f7 1337 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
<> 144:ef7eb2e8f9f7 1338 #define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
mbed_official 25:ac5b0a371348 1339
mbed_official 25:ac5b0a371348 1340 /****************** Bit definition for EXTI_RTSR register *******************/
<> 144:ef7eb2e8f9f7 1341 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 1342 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 1343 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 1344 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 1345 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 1346 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 1347 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 1348 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 1349 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 1350 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 1351 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 1352 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 1353 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 1354 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 1355 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 1356 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 1357 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 1358 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 1359 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 1360 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 1361 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 1362 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 1363 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 1364 #define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
mbed_official 25:ac5b0a371348 1365
mbed_official 25:ac5b0a371348 1366 /****************** Bit definition for EXTI_FTSR register *******************/
<> 144:ef7eb2e8f9f7 1367 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 1368 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 1369 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 1370 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 1371 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 1372 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 1373 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 1374 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 1375 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 1376 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 1377 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 1378 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 1379 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 1380 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 1381 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 1382 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 1383 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 1384 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 1385 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 1386 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 1387 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 1388 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 1389 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 1390 #define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
mbed_official 25:ac5b0a371348 1391
mbed_official 25:ac5b0a371348 1392 /****************** Bit definition for EXTI_SWIER register ******************/
<> 144:ef7eb2e8f9f7 1393 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
<> 144:ef7eb2e8f9f7 1394 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
<> 144:ef7eb2e8f9f7 1395 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
<> 144:ef7eb2e8f9f7 1396 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
<> 144:ef7eb2e8f9f7 1397 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
<> 144:ef7eb2e8f9f7 1398 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
<> 144:ef7eb2e8f9f7 1399 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
<> 144:ef7eb2e8f9f7 1400 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
<> 144:ef7eb2e8f9f7 1401 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
<> 144:ef7eb2e8f9f7 1402 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
<> 144:ef7eb2e8f9f7 1403 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
<> 144:ef7eb2e8f9f7 1404 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
<> 144:ef7eb2e8f9f7 1405 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
<> 144:ef7eb2e8f9f7 1406 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
<> 144:ef7eb2e8f9f7 1407 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
<> 144:ef7eb2e8f9f7 1408 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
<> 144:ef7eb2e8f9f7 1409 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
<> 144:ef7eb2e8f9f7 1410 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
<> 144:ef7eb2e8f9f7 1411 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
<> 144:ef7eb2e8f9f7 1412 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
<> 144:ef7eb2e8f9f7 1413 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
<> 144:ef7eb2e8f9f7 1414 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
<> 144:ef7eb2e8f9f7 1415 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
<> 144:ef7eb2e8f9f7 1416 #define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
mbed_official 25:ac5b0a371348 1417
mbed_official 25:ac5b0a371348 1418 /******************* Bit definition for EXTI_PR register ********************/
<> 144:ef7eb2e8f9f7 1419 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
<> 144:ef7eb2e8f9f7 1420 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
<> 144:ef7eb2e8f9f7 1421 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
<> 144:ef7eb2e8f9f7 1422 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
<> 144:ef7eb2e8f9f7 1423 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
<> 144:ef7eb2e8f9f7 1424 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
<> 144:ef7eb2e8f9f7 1425 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
<> 144:ef7eb2e8f9f7 1426 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
<> 144:ef7eb2e8f9f7 1427 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
<> 144:ef7eb2e8f9f7 1428 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
<> 144:ef7eb2e8f9f7 1429 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
<> 144:ef7eb2e8f9f7 1430 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
<> 144:ef7eb2e8f9f7 1431 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
<> 144:ef7eb2e8f9f7 1432 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
<> 144:ef7eb2e8f9f7 1433 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
<> 144:ef7eb2e8f9f7 1434 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
<> 144:ef7eb2e8f9f7 1435 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
<> 144:ef7eb2e8f9f7 1436 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
<> 144:ef7eb2e8f9f7 1437 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
<> 144:ef7eb2e8f9f7 1438 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
<> 144:ef7eb2e8f9f7 1439 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
<> 144:ef7eb2e8f9f7 1440 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
<> 144:ef7eb2e8f9f7 1441 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
<> 144:ef7eb2e8f9f7 1442 #define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
mbed_official 25:ac5b0a371348 1443
mbed_official 25:ac5b0a371348 1444 /******************************************************************************/
mbed_official 25:ac5b0a371348 1445 /* */
mbed_official 25:ac5b0a371348 1446 /* FLASH */
mbed_official 25:ac5b0a371348 1447 /* */
mbed_official 25:ac5b0a371348 1448 /******************************************************************************/
mbed_official 25:ac5b0a371348 1449 /******************* Bits definition for FLASH_ACR register *****************/
<> 144:ef7eb2e8f9f7 1450 #define FLASH_ACR_LATENCY 0x0000000FU
<> 144:ef7eb2e8f9f7 1451 #define FLASH_ACR_LATENCY_0WS 0x00000000U
<> 144:ef7eb2e8f9f7 1452 #define FLASH_ACR_LATENCY_1WS 0x00000001U
<> 144:ef7eb2e8f9f7 1453 #define FLASH_ACR_LATENCY_2WS 0x00000002U
<> 144:ef7eb2e8f9f7 1454 #define FLASH_ACR_LATENCY_3WS 0x00000003U
<> 144:ef7eb2e8f9f7 1455 #define FLASH_ACR_LATENCY_4WS 0x00000004U
<> 144:ef7eb2e8f9f7 1456 #define FLASH_ACR_LATENCY_5WS 0x00000005U
<> 144:ef7eb2e8f9f7 1457 #define FLASH_ACR_LATENCY_6WS 0x00000006U
<> 144:ef7eb2e8f9f7 1458 #define FLASH_ACR_LATENCY_7WS 0x00000007U
<> 144:ef7eb2e8f9f7 1459
<> 144:ef7eb2e8f9f7 1460 #define FLASH_ACR_PRFTEN 0x00000100U
<> 144:ef7eb2e8f9f7 1461 #define FLASH_ACR_ICEN 0x00000200U
<> 144:ef7eb2e8f9f7 1462 #define FLASH_ACR_DCEN 0x00000400U
<> 144:ef7eb2e8f9f7 1463 #define FLASH_ACR_ICRST 0x00000800U
<> 144:ef7eb2e8f9f7 1464 #define FLASH_ACR_DCRST 0x00001000U
<> 144:ef7eb2e8f9f7 1465 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
<> 144:ef7eb2e8f9f7 1466 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
mbed_official 25:ac5b0a371348 1467
mbed_official 25:ac5b0a371348 1468 /******************* Bits definition for FLASH_SR register ******************/
<> 144:ef7eb2e8f9f7 1469 #define FLASH_SR_EOP 0x00000001U
<> 144:ef7eb2e8f9f7 1470 #define FLASH_SR_SOP 0x00000002U
<> 144:ef7eb2e8f9f7 1471 #define FLASH_SR_WRPERR 0x00000010U
<> 144:ef7eb2e8f9f7 1472 #define FLASH_SR_PGAERR 0x00000020U
<> 144:ef7eb2e8f9f7 1473 #define FLASH_SR_PGPERR 0x00000040U
<> 144:ef7eb2e8f9f7 1474 #define FLASH_SR_PGSERR 0x00000080U
<> 144:ef7eb2e8f9f7 1475 #define FLASH_SR_BSY 0x00010000U
mbed_official 25:ac5b0a371348 1476
mbed_official 25:ac5b0a371348 1477 /******************* Bits definition for FLASH_CR register ******************/
<> 144:ef7eb2e8f9f7 1478 #define FLASH_CR_PG 0x00000001U
<> 144:ef7eb2e8f9f7 1479 #define FLASH_CR_SER 0x00000002U
<> 144:ef7eb2e8f9f7 1480 #define FLASH_CR_MER 0x00000004U
<> 144:ef7eb2e8f9f7 1481 #define FLASH_CR_SNB 0x000000F8U
<> 144:ef7eb2e8f9f7 1482 #define FLASH_CR_SNB_0 0x00000008U
<> 144:ef7eb2e8f9f7 1483 #define FLASH_CR_SNB_1 0x00000010U
<> 144:ef7eb2e8f9f7 1484 #define FLASH_CR_SNB_2 0x00000020U
<> 144:ef7eb2e8f9f7 1485 #define FLASH_CR_SNB_3 0x00000040U
<> 144:ef7eb2e8f9f7 1486 #define FLASH_CR_SNB_4 0x00000080U
<> 144:ef7eb2e8f9f7 1487 #define FLASH_CR_PSIZE 0x00000300U
<> 144:ef7eb2e8f9f7 1488 #define FLASH_CR_PSIZE_0 0x00000100U
<> 144:ef7eb2e8f9f7 1489 #define FLASH_CR_PSIZE_1 0x00000200U
<> 144:ef7eb2e8f9f7 1490 #define FLASH_CR_STRT 0x00010000U
<> 144:ef7eb2e8f9f7 1491 #define FLASH_CR_EOPIE 0x01000000U
<> 144:ef7eb2e8f9f7 1492 #define FLASH_CR_LOCK 0x80000000U
mbed_official 25:ac5b0a371348 1493
mbed_official 25:ac5b0a371348 1494 /******************* Bits definition for FLASH_OPTCR register ***************/
<> 144:ef7eb2e8f9f7 1495 #define FLASH_OPTCR_OPTLOCK 0x00000001U
<> 144:ef7eb2e8f9f7 1496 #define FLASH_OPTCR_OPTSTRT 0x00000002U
<> 144:ef7eb2e8f9f7 1497 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
<> 144:ef7eb2e8f9f7 1498 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
<> 144:ef7eb2e8f9f7 1499 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 #define FLASH_OPTCR_WDG_SW 0x00000020U
<> 144:ef7eb2e8f9f7 1502 #define FLASH_OPTCR_nRST_STOP 0x00000040U
<> 144:ef7eb2e8f9f7 1503 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
<> 144:ef7eb2e8f9f7 1504 #define FLASH_OPTCR_RDP 0x0000FF00U
<> 144:ef7eb2e8f9f7 1505 #define FLASH_OPTCR_RDP_0 0x00000100U
<> 144:ef7eb2e8f9f7 1506 #define FLASH_OPTCR_RDP_1 0x00000200U
<> 144:ef7eb2e8f9f7 1507 #define FLASH_OPTCR_RDP_2 0x00000400U
<> 144:ef7eb2e8f9f7 1508 #define FLASH_OPTCR_RDP_3 0x00000800U
<> 144:ef7eb2e8f9f7 1509 #define FLASH_OPTCR_RDP_4 0x00001000U
<> 144:ef7eb2e8f9f7 1510 #define FLASH_OPTCR_RDP_5 0x00002000U
<> 144:ef7eb2e8f9f7 1511 #define FLASH_OPTCR_RDP_6 0x00004000U
<> 144:ef7eb2e8f9f7 1512 #define FLASH_OPTCR_RDP_7 0x00008000U
<> 144:ef7eb2e8f9f7 1513 #define FLASH_OPTCR_nWRP 0x0FFF0000U
<> 144:ef7eb2e8f9f7 1514 #define FLASH_OPTCR_nWRP_0 0x00010000U
<> 144:ef7eb2e8f9f7 1515 #define FLASH_OPTCR_nWRP_1 0x00020000U
<> 144:ef7eb2e8f9f7 1516 #define FLASH_OPTCR_nWRP_2 0x00040000U
<> 144:ef7eb2e8f9f7 1517 #define FLASH_OPTCR_nWRP_3 0x00080000U
<> 144:ef7eb2e8f9f7 1518 #define FLASH_OPTCR_nWRP_4 0x00100000U
<> 144:ef7eb2e8f9f7 1519 #define FLASH_OPTCR_nWRP_5 0x00200000U
<> 144:ef7eb2e8f9f7 1520 #define FLASH_OPTCR_nWRP_6 0x00400000U
<> 144:ef7eb2e8f9f7 1521 #define FLASH_OPTCR_nWRP_7 0x00800000U
<> 144:ef7eb2e8f9f7 1522 #define FLASH_OPTCR_nWRP_8 0x01000000U
<> 144:ef7eb2e8f9f7 1523 #define FLASH_OPTCR_nWRP_9 0x02000000U
<> 144:ef7eb2e8f9f7 1524 #define FLASH_OPTCR_nWRP_10 0x04000000U
<> 144:ef7eb2e8f9f7 1525 #define FLASH_OPTCR_nWRP_11 0x08000000U
mbed_official 25:ac5b0a371348 1526
mbed_official 25:ac5b0a371348 1527 /****************** Bits definition for FLASH_OPTCR1 register ***************/
<> 144:ef7eb2e8f9f7 1528 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
<> 144:ef7eb2e8f9f7 1529 #define FLASH_OPTCR1_nWRP_0 0x00010000U
<> 144:ef7eb2e8f9f7 1530 #define FLASH_OPTCR1_nWRP_1 0x00020000U
<> 144:ef7eb2e8f9f7 1531 #define FLASH_OPTCR1_nWRP_2 0x00040000U
<> 144:ef7eb2e8f9f7 1532 #define FLASH_OPTCR1_nWRP_3 0x00080000U
<> 144:ef7eb2e8f9f7 1533 #define FLASH_OPTCR1_nWRP_4 0x00100000U
<> 144:ef7eb2e8f9f7 1534 #define FLASH_OPTCR1_nWRP_5 0x00200000U
<> 144:ef7eb2e8f9f7 1535 #define FLASH_OPTCR1_nWRP_6 0x00400000U
<> 144:ef7eb2e8f9f7 1536 #define FLASH_OPTCR1_nWRP_7 0x00800000U
<> 144:ef7eb2e8f9f7 1537 #define FLASH_OPTCR1_nWRP_8 0x01000000U
<> 144:ef7eb2e8f9f7 1538 #define FLASH_OPTCR1_nWRP_9 0x02000000U
<> 144:ef7eb2e8f9f7 1539 #define FLASH_OPTCR1_nWRP_10 0x04000000U
<> 144:ef7eb2e8f9f7 1540 #define FLASH_OPTCR1_nWRP_11 0x08000000U
mbed_official 25:ac5b0a371348 1541
mbed_official 25:ac5b0a371348 1542 /******************************************************************************/
mbed_official 25:ac5b0a371348 1543 /* */
mbed_official 25:ac5b0a371348 1544 /* General Purpose I/O */
mbed_official 25:ac5b0a371348 1545 /* */
mbed_official 25:ac5b0a371348 1546 /******************************************************************************/
mbed_official 25:ac5b0a371348 1547 /****************** Bits definition for GPIO_MODER register *****************/
<> 144:ef7eb2e8f9f7 1548 #define GPIO_MODER_MODER0 0x00000003U
<> 144:ef7eb2e8f9f7 1549 #define GPIO_MODER_MODER0_0 0x00000001U
<> 144:ef7eb2e8f9f7 1550 #define GPIO_MODER_MODER0_1 0x00000002U
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 #define GPIO_MODER_MODER1 0x0000000CU
<> 144:ef7eb2e8f9f7 1553 #define GPIO_MODER_MODER1_0 0x00000004U
<> 144:ef7eb2e8f9f7 1554 #define GPIO_MODER_MODER1_1 0x00000008U
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 #define GPIO_MODER_MODER2 0x00000030U
<> 144:ef7eb2e8f9f7 1557 #define GPIO_MODER_MODER2_0 0x00000010U
<> 144:ef7eb2e8f9f7 1558 #define GPIO_MODER_MODER2_1 0x00000020U
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 #define GPIO_MODER_MODER3 0x000000C0U
<> 144:ef7eb2e8f9f7 1561 #define GPIO_MODER_MODER3_0 0x00000040U
<> 144:ef7eb2e8f9f7 1562 #define GPIO_MODER_MODER3_1 0x00000080U
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 #define GPIO_MODER_MODER4 0x00000300U
<> 144:ef7eb2e8f9f7 1565 #define GPIO_MODER_MODER4_0 0x00000100U
<> 144:ef7eb2e8f9f7 1566 #define GPIO_MODER_MODER4_1 0x00000200U
<> 144:ef7eb2e8f9f7 1567
<> 144:ef7eb2e8f9f7 1568 #define GPIO_MODER_MODER5 0x00000C00U
<> 144:ef7eb2e8f9f7 1569 #define GPIO_MODER_MODER5_0 0x00000400U
<> 144:ef7eb2e8f9f7 1570 #define GPIO_MODER_MODER5_1 0x00000800U
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 #define GPIO_MODER_MODER6 0x00003000U
<> 144:ef7eb2e8f9f7 1573 #define GPIO_MODER_MODER6_0 0x00001000U
<> 144:ef7eb2e8f9f7 1574 #define GPIO_MODER_MODER6_1 0x00002000U
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 #define GPIO_MODER_MODER7 0x0000C000U
<> 144:ef7eb2e8f9f7 1577 #define GPIO_MODER_MODER7_0 0x00004000U
<> 144:ef7eb2e8f9f7 1578 #define GPIO_MODER_MODER7_1 0x00008000U
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 #define GPIO_MODER_MODER8 0x00030000U
<> 144:ef7eb2e8f9f7 1581 #define GPIO_MODER_MODER8_0 0x00010000U
<> 144:ef7eb2e8f9f7 1582 #define GPIO_MODER_MODER8_1 0x00020000U
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 #define GPIO_MODER_MODER9 0x000C0000U
<> 144:ef7eb2e8f9f7 1585 #define GPIO_MODER_MODER9_0 0x00040000U
<> 144:ef7eb2e8f9f7 1586 #define GPIO_MODER_MODER9_1 0x00080000U
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 #define GPIO_MODER_MODER10 0x00300000U
<> 144:ef7eb2e8f9f7 1589 #define GPIO_MODER_MODER10_0 0x00100000U
<> 144:ef7eb2e8f9f7 1590 #define GPIO_MODER_MODER10_1 0x00200000U
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 #define GPIO_MODER_MODER11 0x00C00000U
<> 144:ef7eb2e8f9f7 1593 #define GPIO_MODER_MODER11_0 0x00400000U
<> 144:ef7eb2e8f9f7 1594 #define GPIO_MODER_MODER11_1 0x00800000U
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 #define GPIO_MODER_MODER12 0x03000000U
<> 144:ef7eb2e8f9f7 1597 #define GPIO_MODER_MODER12_0 0x01000000U
<> 144:ef7eb2e8f9f7 1598 #define GPIO_MODER_MODER12_1 0x02000000U
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 #define GPIO_MODER_MODER13 0x0C000000U
<> 144:ef7eb2e8f9f7 1601 #define GPIO_MODER_MODER13_0 0x04000000U
<> 144:ef7eb2e8f9f7 1602 #define GPIO_MODER_MODER13_1 0x08000000U
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 #define GPIO_MODER_MODER14 0x30000000U
<> 144:ef7eb2e8f9f7 1605 #define GPIO_MODER_MODER14_0 0x10000000U
<> 144:ef7eb2e8f9f7 1606 #define GPIO_MODER_MODER14_1 0x20000000U
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 #define GPIO_MODER_MODER15 0xC0000000U
<> 144:ef7eb2e8f9f7 1609 #define GPIO_MODER_MODER15_0 0x40000000U
<> 144:ef7eb2e8f9f7 1610 #define GPIO_MODER_MODER15_1 0x80000000U
mbed_official 25:ac5b0a371348 1611
mbed_official 25:ac5b0a371348 1612 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 144:ef7eb2e8f9f7 1613 #define GPIO_OTYPER_OT_0 0x00000001U
<> 144:ef7eb2e8f9f7 1614 #define GPIO_OTYPER_OT_1 0x00000002U
<> 144:ef7eb2e8f9f7 1615 #define GPIO_OTYPER_OT_2 0x00000004U
<> 144:ef7eb2e8f9f7 1616 #define GPIO_OTYPER_OT_3 0x00000008U
<> 144:ef7eb2e8f9f7 1617 #define GPIO_OTYPER_OT_4 0x00000010U
<> 144:ef7eb2e8f9f7 1618 #define GPIO_OTYPER_OT_5 0x00000020U
<> 144:ef7eb2e8f9f7 1619 #define GPIO_OTYPER_OT_6 0x00000040U
<> 144:ef7eb2e8f9f7 1620 #define GPIO_OTYPER_OT_7 0x00000080U
<> 144:ef7eb2e8f9f7 1621 #define GPIO_OTYPER_OT_8 0x00000100U
<> 144:ef7eb2e8f9f7 1622 #define GPIO_OTYPER_OT_9 0x00000200U
<> 144:ef7eb2e8f9f7 1623 #define GPIO_OTYPER_OT_10 0x00000400U
<> 144:ef7eb2e8f9f7 1624 #define GPIO_OTYPER_OT_11 0x00000800U
<> 144:ef7eb2e8f9f7 1625 #define GPIO_OTYPER_OT_12 0x00001000U
<> 144:ef7eb2e8f9f7 1626 #define GPIO_OTYPER_OT_13 0x00002000U
<> 144:ef7eb2e8f9f7 1627 #define GPIO_OTYPER_OT_14 0x00004000U
<> 144:ef7eb2e8f9f7 1628 #define GPIO_OTYPER_OT_15 0x00008000U
mbed_official 25:ac5b0a371348 1629
mbed_official 25:ac5b0a371348 1630 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 144:ef7eb2e8f9f7 1631 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
<> 144:ef7eb2e8f9f7 1632 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
<> 144:ef7eb2e8f9f7 1633 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
<> 144:ef7eb2e8f9f7 1634
<> 144:ef7eb2e8f9f7 1635 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
<> 144:ef7eb2e8f9f7 1636 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
<> 144:ef7eb2e8f9f7 1637 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
<> 144:ef7eb2e8f9f7 1640 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
<> 144:ef7eb2e8f9f7 1641 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
<> 144:ef7eb2e8f9f7 1644 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
<> 144:ef7eb2e8f9f7 1645 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
<> 144:ef7eb2e8f9f7 1648 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
<> 144:ef7eb2e8f9f7 1649 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
<> 144:ef7eb2e8f9f7 1652 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
<> 144:ef7eb2e8f9f7 1653 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
<> 144:ef7eb2e8f9f7 1656 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
<> 144:ef7eb2e8f9f7 1657 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
<> 144:ef7eb2e8f9f7 1660 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
<> 144:ef7eb2e8f9f7 1661 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
<> 144:ef7eb2e8f9f7 1664 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
<> 144:ef7eb2e8f9f7 1665 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
<> 144:ef7eb2e8f9f7 1666
<> 144:ef7eb2e8f9f7 1667 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
<> 144:ef7eb2e8f9f7 1668 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
<> 144:ef7eb2e8f9f7 1669 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
<> 144:ef7eb2e8f9f7 1670
<> 144:ef7eb2e8f9f7 1671 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
<> 144:ef7eb2e8f9f7 1672 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
<> 144:ef7eb2e8f9f7 1673 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
<> 144:ef7eb2e8f9f7 1674
<> 144:ef7eb2e8f9f7 1675 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
<> 144:ef7eb2e8f9f7 1676 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
<> 144:ef7eb2e8f9f7 1677 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
<> 144:ef7eb2e8f9f7 1680 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
<> 144:ef7eb2e8f9f7 1681 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
<> 144:ef7eb2e8f9f7 1684 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
<> 144:ef7eb2e8f9f7 1685 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
<> 144:ef7eb2e8f9f7 1688 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
<> 144:ef7eb2e8f9f7 1689 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
<> 144:ef7eb2e8f9f7 1692 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
<> 144:ef7eb2e8f9f7 1693 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
mbed_official 25:ac5b0a371348 1694
mbed_official 25:ac5b0a371348 1695 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 144:ef7eb2e8f9f7 1696 #define GPIO_PUPDR_PUPDR0 0x00000003U
<> 144:ef7eb2e8f9f7 1697 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
<> 144:ef7eb2e8f9f7 1698 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 #define GPIO_PUPDR_PUPDR1 0x0000000CU
<> 144:ef7eb2e8f9f7 1701 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
<> 144:ef7eb2e8f9f7 1702 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 #define GPIO_PUPDR_PUPDR2 0x00000030U
<> 144:ef7eb2e8f9f7 1705 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
<> 144:ef7eb2e8f9f7 1706 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 #define GPIO_PUPDR_PUPDR3 0x000000C0U
<> 144:ef7eb2e8f9f7 1709 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
<> 144:ef7eb2e8f9f7 1710 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 #define GPIO_PUPDR_PUPDR4 0x00000300U
<> 144:ef7eb2e8f9f7 1713 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
<> 144:ef7eb2e8f9f7 1714 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 #define GPIO_PUPDR_PUPDR5 0x00000C00U
<> 144:ef7eb2e8f9f7 1717 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
<> 144:ef7eb2e8f9f7 1718 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720 #define GPIO_PUPDR_PUPDR6 0x00003000U
<> 144:ef7eb2e8f9f7 1721 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
<> 144:ef7eb2e8f9f7 1722 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
<> 144:ef7eb2e8f9f7 1723
<> 144:ef7eb2e8f9f7 1724 #define GPIO_PUPDR_PUPDR7 0x0000C000U
<> 144:ef7eb2e8f9f7 1725 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
<> 144:ef7eb2e8f9f7 1726 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 #define GPIO_PUPDR_PUPDR8 0x00030000U
<> 144:ef7eb2e8f9f7 1729 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
<> 144:ef7eb2e8f9f7 1730 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732 #define GPIO_PUPDR_PUPDR9 0x000C0000U
<> 144:ef7eb2e8f9f7 1733 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
<> 144:ef7eb2e8f9f7 1734 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
<> 144:ef7eb2e8f9f7 1735
<> 144:ef7eb2e8f9f7 1736 #define GPIO_PUPDR_PUPDR10 0x00300000U
<> 144:ef7eb2e8f9f7 1737 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
<> 144:ef7eb2e8f9f7 1738 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 #define GPIO_PUPDR_PUPDR11 0x00C00000U
<> 144:ef7eb2e8f9f7 1741 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
<> 144:ef7eb2e8f9f7 1742 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
<> 144:ef7eb2e8f9f7 1743
<> 144:ef7eb2e8f9f7 1744 #define GPIO_PUPDR_PUPDR12 0x03000000U
<> 144:ef7eb2e8f9f7 1745 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
<> 144:ef7eb2e8f9f7 1746 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 #define GPIO_PUPDR_PUPDR13 0x0C000000U
<> 144:ef7eb2e8f9f7 1749 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
<> 144:ef7eb2e8f9f7 1750 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
<> 144:ef7eb2e8f9f7 1751
<> 144:ef7eb2e8f9f7 1752 #define GPIO_PUPDR_PUPDR14 0x30000000U
<> 144:ef7eb2e8f9f7 1753 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
<> 144:ef7eb2e8f9f7 1754 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
<> 144:ef7eb2e8f9f7 1755
<> 144:ef7eb2e8f9f7 1756 #define GPIO_PUPDR_PUPDR15 0xC0000000U
<> 144:ef7eb2e8f9f7 1757 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
<> 144:ef7eb2e8f9f7 1758 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
mbed_official 25:ac5b0a371348 1759
mbed_official 25:ac5b0a371348 1760 /****************** Bits definition for GPIO_IDR register *******************/
<> 144:ef7eb2e8f9f7 1761 #define GPIO_IDR_IDR_0 0x00000001U
<> 144:ef7eb2e8f9f7 1762 #define GPIO_IDR_IDR_1 0x00000002U
<> 144:ef7eb2e8f9f7 1763 #define GPIO_IDR_IDR_2 0x00000004U
<> 144:ef7eb2e8f9f7 1764 #define GPIO_IDR_IDR_3 0x00000008U
<> 144:ef7eb2e8f9f7 1765 #define GPIO_IDR_IDR_4 0x00000010U
<> 144:ef7eb2e8f9f7 1766 #define GPIO_IDR_IDR_5 0x00000020U
<> 144:ef7eb2e8f9f7 1767 #define GPIO_IDR_IDR_6 0x00000040U
<> 144:ef7eb2e8f9f7 1768 #define GPIO_IDR_IDR_7 0x00000080U
<> 144:ef7eb2e8f9f7 1769 #define GPIO_IDR_IDR_8 0x00000100U
<> 144:ef7eb2e8f9f7 1770 #define GPIO_IDR_IDR_9 0x00000200U
<> 144:ef7eb2e8f9f7 1771 #define GPIO_IDR_IDR_10 0x00000400U
<> 144:ef7eb2e8f9f7 1772 #define GPIO_IDR_IDR_11 0x00000800U
<> 144:ef7eb2e8f9f7 1773 #define GPIO_IDR_IDR_12 0x00001000U
<> 144:ef7eb2e8f9f7 1774 #define GPIO_IDR_IDR_13 0x00002000U
<> 144:ef7eb2e8f9f7 1775 #define GPIO_IDR_IDR_14 0x00004000U
<> 144:ef7eb2e8f9f7 1776 #define GPIO_IDR_IDR_15 0x00008000U
mbed_official 25:ac5b0a371348 1777
mbed_official 25:ac5b0a371348 1778 /****************** Bits definition for GPIO_ODR register *******************/
<> 144:ef7eb2e8f9f7 1779 #define GPIO_ODR_ODR_0 0x00000001U
<> 144:ef7eb2e8f9f7 1780 #define GPIO_ODR_ODR_1 0x00000002U
<> 144:ef7eb2e8f9f7 1781 #define GPIO_ODR_ODR_2 0x00000004U
<> 144:ef7eb2e8f9f7 1782 #define GPIO_ODR_ODR_3 0x00000008U
<> 144:ef7eb2e8f9f7 1783 #define GPIO_ODR_ODR_4 0x00000010U
<> 144:ef7eb2e8f9f7 1784 #define GPIO_ODR_ODR_5 0x00000020U
<> 144:ef7eb2e8f9f7 1785 #define GPIO_ODR_ODR_6 0x00000040U
<> 144:ef7eb2e8f9f7 1786 #define GPIO_ODR_ODR_7 0x00000080U
<> 144:ef7eb2e8f9f7 1787 #define GPIO_ODR_ODR_8 0x00000100U
<> 144:ef7eb2e8f9f7 1788 #define GPIO_ODR_ODR_9 0x00000200U
<> 144:ef7eb2e8f9f7 1789 #define GPIO_ODR_ODR_10 0x00000400U
<> 144:ef7eb2e8f9f7 1790 #define GPIO_ODR_ODR_11 0x00000800U
<> 144:ef7eb2e8f9f7 1791 #define GPIO_ODR_ODR_12 0x00001000U
<> 144:ef7eb2e8f9f7 1792 #define GPIO_ODR_ODR_13 0x00002000U
<> 144:ef7eb2e8f9f7 1793 #define GPIO_ODR_ODR_14 0x00004000U
<> 144:ef7eb2e8f9f7 1794 #define GPIO_ODR_ODR_15 0x00008000U
mbed_official 25:ac5b0a371348 1795
mbed_official 25:ac5b0a371348 1796 /****************** Bits definition for GPIO_BSRR register ******************/
<> 144:ef7eb2e8f9f7 1797 #define GPIO_BSRR_BS_0 0x00000001U
<> 144:ef7eb2e8f9f7 1798 #define GPIO_BSRR_BS_1 0x00000002U
<> 144:ef7eb2e8f9f7 1799 #define GPIO_BSRR_BS_2 0x00000004U
<> 144:ef7eb2e8f9f7 1800 #define GPIO_BSRR_BS_3 0x00000008U
<> 144:ef7eb2e8f9f7 1801 #define GPIO_BSRR_BS_4 0x00000010U
<> 144:ef7eb2e8f9f7 1802 #define GPIO_BSRR_BS_5 0x00000020U
<> 144:ef7eb2e8f9f7 1803 #define GPIO_BSRR_BS_6 0x00000040U
<> 144:ef7eb2e8f9f7 1804 #define GPIO_BSRR_BS_7 0x00000080U
<> 144:ef7eb2e8f9f7 1805 #define GPIO_BSRR_BS_8 0x00000100U
<> 144:ef7eb2e8f9f7 1806 #define GPIO_BSRR_BS_9 0x00000200U
<> 144:ef7eb2e8f9f7 1807 #define GPIO_BSRR_BS_10 0x00000400U
<> 144:ef7eb2e8f9f7 1808 #define GPIO_BSRR_BS_11 0x00000800U
<> 144:ef7eb2e8f9f7 1809 #define GPIO_BSRR_BS_12 0x00001000U
<> 144:ef7eb2e8f9f7 1810 #define GPIO_BSRR_BS_13 0x00002000U
<> 144:ef7eb2e8f9f7 1811 #define GPIO_BSRR_BS_14 0x00004000U
<> 144:ef7eb2e8f9f7 1812 #define GPIO_BSRR_BS_15 0x00008000U
<> 144:ef7eb2e8f9f7 1813 #define GPIO_BSRR_BR_0 0x00010000U
<> 144:ef7eb2e8f9f7 1814 #define GPIO_BSRR_BR_1 0x00020000U
<> 144:ef7eb2e8f9f7 1815 #define GPIO_BSRR_BR_2 0x00040000U
<> 144:ef7eb2e8f9f7 1816 #define GPIO_BSRR_BR_3 0x00080000U
<> 144:ef7eb2e8f9f7 1817 #define GPIO_BSRR_BR_4 0x00100000U
<> 144:ef7eb2e8f9f7 1818 #define GPIO_BSRR_BR_5 0x00200000U
<> 144:ef7eb2e8f9f7 1819 #define GPIO_BSRR_BR_6 0x00400000U
<> 144:ef7eb2e8f9f7 1820 #define GPIO_BSRR_BR_7 0x00800000U
<> 144:ef7eb2e8f9f7 1821 #define GPIO_BSRR_BR_8 0x01000000U
<> 144:ef7eb2e8f9f7 1822 #define GPIO_BSRR_BR_9 0x02000000U
<> 144:ef7eb2e8f9f7 1823 #define GPIO_BSRR_BR_10 0x04000000U
<> 144:ef7eb2e8f9f7 1824 #define GPIO_BSRR_BR_11 0x08000000U
<> 144:ef7eb2e8f9f7 1825 #define GPIO_BSRR_BR_12 0x10000000U
<> 144:ef7eb2e8f9f7 1826 #define GPIO_BSRR_BR_13 0x20000000U
<> 144:ef7eb2e8f9f7 1827 #define GPIO_BSRR_BR_14 0x40000000U
<> 144:ef7eb2e8f9f7 1828 #define GPIO_BSRR_BR_15 0x80000000U
mbed_official 25:ac5b0a371348 1829
mbed_official 25:ac5b0a371348 1830 /****************** Bit definition for GPIO_LCKR register *********************/
<> 144:ef7eb2e8f9f7 1831 #define GPIO_LCKR_LCK0 0x00000001U
<> 144:ef7eb2e8f9f7 1832 #define GPIO_LCKR_LCK1 0x00000002U
<> 144:ef7eb2e8f9f7 1833 #define GPIO_LCKR_LCK2 0x00000004U
<> 144:ef7eb2e8f9f7 1834 #define GPIO_LCKR_LCK3 0x00000008U
<> 144:ef7eb2e8f9f7 1835 #define GPIO_LCKR_LCK4 0x00000010U
<> 144:ef7eb2e8f9f7 1836 #define GPIO_LCKR_LCK5 0x00000020U
<> 144:ef7eb2e8f9f7 1837 #define GPIO_LCKR_LCK6 0x00000040U
<> 144:ef7eb2e8f9f7 1838 #define GPIO_LCKR_LCK7 0x00000080U
<> 144:ef7eb2e8f9f7 1839 #define GPIO_LCKR_LCK8 0x00000100U
<> 144:ef7eb2e8f9f7 1840 #define GPIO_LCKR_LCK9 0x00000200U
<> 144:ef7eb2e8f9f7 1841 #define GPIO_LCKR_LCK10 0x00000400U
<> 144:ef7eb2e8f9f7 1842 #define GPIO_LCKR_LCK11 0x00000800U
<> 144:ef7eb2e8f9f7 1843 #define GPIO_LCKR_LCK12 0x00001000U
<> 144:ef7eb2e8f9f7 1844 #define GPIO_LCKR_LCK13 0x00002000U
<> 144:ef7eb2e8f9f7 1845 #define GPIO_LCKR_LCK14 0x00004000U
<> 144:ef7eb2e8f9f7 1846 #define GPIO_LCKR_LCK15 0x00008000U
<> 144:ef7eb2e8f9f7 1847 #define GPIO_LCKR_LCKK 0x00010000U
mbed_official 25:ac5b0a371348 1848
mbed_official 25:ac5b0a371348 1849 /******************************************************************************/
mbed_official 25:ac5b0a371348 1850 /* */
mbed_official 25:ac5b0a371348 1851 /* Inter-integrated Circuit Interface */
mbed_official 25:ac5b0a371348 1852 /* */
mbed_official 25:ac5b0a371348 1853 /******************************************************************************/
mbed_official 25:ac5b0a371348 1854 /******************* Bit definition for I2C_CR1 register ********************/
<> 144:ef7eb2e8f9f7 1855 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
<> 144:ef7eb2e8f9f7 1856 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
<> 144:ef7eb2e8f9f7 1857 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
<> 144:ef7eb2e8f9f7 1858 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
<> 144:ef7eb2e8f9f7 1859 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
<> 144:ef7eb2e8f9f7 1860 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
<> 144:ef7eb2e8f9f7 1861 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
<> 144:ef7eb2e8f9f7 1862 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
<> 144:ef7eb2e8f9f7 1863 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
<> 144:ef7eb2e8f9f7 1864 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
<> 144:ef7eb2e8f9f7 1865 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
<> 144:ef7eb2e8f9f7 1866 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
<> 144:ef7eb2e8f9f7 1867 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
<> 144:ef7eb2e8f9f7 1868 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
mbed_official 25:ac5b0a371348 1869
mbed_official 25:ac5b0a371348 1870 /******************* Bit definition for I2C_CR2 register ********************/
<> 144:ef7eb2e8f9f7 1871 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
<> 144:ef7eb2e8f9f7 1872 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1873 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1874 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1875 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1876 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1877 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 1878
<> 144:ef7eb2e8f9f7 1879 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 1880 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
<> 144:ef7eb2e8f9f7 1881 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
<> 144:ef7eb2e8f9f7 1882 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
<> 144:ef7eb2e8f9f7 1883 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
mbed_official 25:ac5b0a371348 1884
mbed_official 25:ac5b0a371348 1885 /******************* Bit definition for I2C_OAR1 register *******************/
<> 144:ef7eb2e8f9f7 1886 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
<> 144:ef7eb2e8f9f7 1887 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
<> 144:ef7eb2e8f9f7 1888
<> 144:ef7eb2e8f9f7 1889 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1890 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1891 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1892 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1893 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1894 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 1895 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 1896 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 1897 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 1898 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
mbed_official 25:ac5b0a371348 1901
mbed_official 25:ac5b0a371348 1902 /******************* Bit definition for I2C_OAR2 register *******************/
<> 144:ef7eb2e8f9f7 1903 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
<> 144:ef7eb2e8f9f7 1904 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
mbed_official 25:ac5b0a371348 1905
mbed_official 25:ac5b0a371348 1906 /******************** Bit definition for I2C_DR register ********************/
<> 144:ef7eb2e8f9f7 1907 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
mbed_official 25:ac5b0a371348 1908
mbed_official 25:ac5b0a371348 1909 /******************* Bit definition for I2C_SR1 register ********************/
<> 144:ef7eb2e8f9f7 1910 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
<> 144:ef7eb2e8f9f7 1911 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
<> 144:ef7eb2e8f9f7 1912 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
<> 144:ef7eb2e8f9f7 1913 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
<> 144:ef7eb2e8f9f7 1914 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
<> 144:ef7eb2e8f9f7 1915 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
<> 144:ef7eb2e8f9f7 1916 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
<> 144:ef7eb2e8f9f7 1917 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
<> 144:ef7eb2e8f9f7 1918 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
<> 144:ef7eb2e8f9f7 1919 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
<> 144:ef7eb2e8f9f7 1920 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
<> 144:ef7eb2e8f9f7 1921 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
<> 144:ef7eb2e8f9f7 1922 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
<> 144:ef7eb2e8f9f7 1923 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
mbed_official 25:ac5b0a371348 1924
mbed_official 25:ac5b0a371348 1925 /******************* Bit definition for I2C_SR2 register ********************/
<> 144:ef7eb2e8f9f7 1926 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
<> 144:ef7eb2e8f9f7 1927 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
<> 144:ef7eb2e8f9f7 1928 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
<> 144:ef7eb2e8f9f7 1929 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
<> 144:ef7eb2e8f9f7 1930 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
<> 144:ef7eb2e8f9f7 1931 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
<> 144:ef7eb2e8f9f7 1932 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
<> 144:ef7eb2e8f9f7 1933 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
mbed_official 25:ac5b0a371348 1934
mbed_official 25:ac5b0a371348 1935 /******************* Bit definition for I2C_CCR register ********************/
<> 144:ef7eb2e8f9f7 1936 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
<> 144:ef7eb2e8f9f7 1937 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
<> 144:ef7eb2e8f9f7 1938 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
mbed_official 25:ac5b0a371348 1939
mbed_official 25:ac5b0a371348 1940 /****************** Bit definition for I2C_TRISE register *******************/
<> 144:ef7eb2e8f9f7 1941 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 25:ac5b0a371348 1942
mbed_official 25:ac5b0a371348 1943 /****************** Bit definition for I2C_FLTR register *******************/
<> 144:ef7eb2e8f9f7 1944 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
<> 144:ef7eb2e8f9f7 1945 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
mbed_official 25:ac5b0a371348 1946
mbed_official 25:ac5b0a371348 1947 /******************************************************************************/
mbed_official 25:ac5b0a371348 1948 /* */
mbed_official 25:ac5b0a371348 1949 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
mbed_official 25:ac5b0a371348 1950 /* */
mbed_official 25:ac5b0a371348 1951 /******************************************************************************/
mbed_official 25:ac5b0a371348 1952 /******************* Bit definition for I2C_CR1 register *******************/
<> 144:ef7eb2e8f9f7 1953 #define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
<> 144:ef7eb2e8f9f7 1954 #define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
<> 144:ef7eb2e8f9f7 1955 #define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
<> 144:ef7eb2e8f9f7 1956 #define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
<> 144:ef7eb2e8f9f7 1957 #define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
<> 144:ef7eb2e8f9f7 1958 #define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
<> 144:ef7eb2e8f9f7 1959 #define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
<> 144:ef7eb2e8f9f7 1960 #define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
<> 144:ef7eb2e8f9f7 1961 #define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
<> 144:ef7eb2e8f9f7 1962 #define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
<> 144:ef7eb2e8f9f7 1963 #define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
<> 144:ef7eb2e8f9f7 1964 #define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
<> 144:ef7eb2e8f9f7 1965 #define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
<> 144:ef7eb2e8f9f7 1966 #define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
<> 144:ef7eb2e8f9f7 1967 #define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
<> 144:ef7eb2e8f9f7 1968 #define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
<> 144:ef7eb2e8f9f7 1969 #define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
<> 144:ef7eb2e8f9f7 1970 #define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
<> 144:ef7eb2e8f9f7 1971 #define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
mbed_official 25:ac5b0a371348 1972
mbed_official 25:ac5b0a371348 1973 /****************** Bit definition for I2C_CR2 register ********************/
<> 144:ef7eb2e8f9f7 1974 #define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
<> 144:ef7eb2e8f9f7 1975 #define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
<> 144:ef7eb2e8f9f7 1976 #define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
<> 144:ef7eb2e8f9f7 1977 #define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
<> 144:ef7eb2e8f9f7 1978 #define FMPI2C_CR2_START 0x00002000U /*!< START generation */
<> 144:ef7eb2e8f9f7 1979 #define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
<> 144:ef7eb2e8f9f7 1980 #define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
<> 144:ef7eb2e8f9f7 1981 #define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
<> 144:ef7eb2e8f9f7 1982 #define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
<> 144:ef7eb2e8f9f7 1983 #define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
<> 144:ef7eb2e8f9f7 1984 #define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
mbed_official 25:ac5b0a371348 1985
mbed_official 25:ac5b0a371348 1986 /******************* Bit definition for I2C_OAR1 register ******************/
<> 144:ef7eb2e8f9f7 1987 #define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
<> 144:ef7eb2e8f9f7 1988 #define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
<> 144:ef7eb2e8f9f7 1989 #define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
mbed_official 25:ac5b0a371348 1990
mbed_official 25:ac5b0a371348 1991 /******************* Bit definition for I2C_OAR2 register ******************/
<> 144:ef7eb2e8f9f7 1992 #define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
<> 144:ef7eb2e8f9f7 1993 #define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
<> 144:ef7eb2e8f9f7 1994 #define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
mbed_official 25:ac5b0a371348 1995
mbed_official 25:ac5b0a371348 1996 /******************* Bit definition for I2C_TIMINGR register *******************/
<> 144:ef7eb2e8f9f7 1997 #define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
<> 144:ef7eb2e8f9f7 1998 #define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
<> 144:ef7eb2e8f9f7 1999 #define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
<> 144:ef7eb2e8f9f7 2000 #define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
<> 144:ef7eb2e8f9f7 2001 #define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
mbed_official 25:ac5b0a371348 2002
mbed_official 25:ac5b0a371348 2003 /******************* Bit definition for I2C_TIMEOUTR register *******************/
<> 144:ef7eb2e8f9f7 2004 #define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
<> 144:ef7eb2e8f9f7 2005 #define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
<> 144:ef7eb2e8f9f7 2006 #define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
<> 144:ef7eb2e8f9f7 2007 #define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
<> 144:ef7eb2e8f9f7 2008 #define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
mbed_official 25:ac5b0a371348 2009
mbed_official 25:ac5b0a371348 2010 /****************** Bit definition for I2C_ISR register *********************/
<> 144:ef7eb2e8f9f7 2011 #define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
<> 144:ef7eb2e8f9f7 2012 #define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
<> 144:ef7eb2e8f9f7 2013 #define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
<> 144:ef7eb2e8f9f7 2014 #define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
<> 144:ef7eb2e8f9f7 2015 #define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
<> 144:ef7eb2e8f9f7 2016 #define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
<> 144:ef7eb2e8f9f7 2017 #define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
<> 144:ef7eb2e8f9f7 2018 #define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
<> 144:ef7eb2e8f9f7 2019 #define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
<> 144:ef7eb2e8f9f7 2020 #define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
<> 144:ef7eb2e8f9f7 2021 #define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
<> 144:ef7eb2e8f9f7 2022 #define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
<> 144:ef7eb2e8f9f7 2023 #define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
<> 144:ef7eb2e8f9f7 2024 #define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
<> 144:ef7eb2e8f9f7 2025 #define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
<> 144:ef7eb2e8f9f7 2026 #define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
<> 144:ef7eb2e8f9f7 2027 #define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
mbed_official 25:ac5b0a371348 2028
mbed_official 25:ac5b0a371348 2029 /****************** Bit definition for I2C_ICR register *********************/
<> 144:ef7eb2e8f9f7 2030 #define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
<> 144:ef7eb2e8f9f7 2031 #define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
<> 144:ef7eb2e8f9f7 2032 #define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
<> 144:ef7eb2e8f9f7 2033 #define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
<> 144:ef7eb2e8f9f7 2034 #define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
<> 144:ef7eb2e8f9f7 2035 #define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
<> 144:ef7eb2e8f9f7 2036 #define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
<> 144:ef7eb2e8f9f7 2037 #define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
<> 144:ef7eb2e8f9f7 2038 #define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
mbed_official 25:ac5b0a371348 2039
mbed_official 25:ac5b0a371348 2040 /****************** Bit definition for I2C_PECR register *********************/
<> 144:ef7eb2e8f9f7 2041 #define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
mbed_official 25:ac5b0a371348 2042
mbed_official 25:ac5b0a371348 2043 /****************** Bit definition for I2C_RXDR register *********************/
<> 144:ef7eb2e8f9f7 2044 #define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
mbed_official 25:ac5b0a371348 2045
mbed_official 25:ac5b0a371348 2046 /****************** Bit definition for I2C_TXDR register *********************/
<> 144:ef7eb2e8f9f7 2047 #define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
mbed_official 25:ac5b0a371348 2048
mbed_official 25:ac5b0a371348 2049 /******************************************************************************/
mbed_official 25:ac5b0a371348 2050 /* */
mbed_official 25:ac5b0a371348 2051 /* Independent WATCHDOG */
mbed_official 25:ac5b0a371348 2052 /* */
mbed_official 25:ac5b0a371348 2053 /******************************************************************************/
mbed_official 25:ac5b0a371348 2054 /******************* Bit definition for IWDG_KR register ********************/
<> 144:ef7eb2e8f9f7 2055 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
mbed_official 25:ac5b0a371348 2056
mbed_official 25:ac5b0a371348 2057 /******************* Bit definition for IWDG_PR register ********************/
<> 144:ef7eb2e8f9f7 2058 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
<> 144:ef7eb2e8f9f7 2059 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2060 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2061 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
mbed_official 25:ac5b0a371348 2062
mbed_official 25:ac5b0a371348 2063 /******************* Bit definition for IWDG_RLR register *******************/
<> 144:ef7eb2e8f9f7 2064 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
mbed_official 25:ac5b0a371348 2065
mbed_official 25:ac5b0a371348 2066 /******************* Bit definition for IWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 2067 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
<> 144:ef7eb2e8f9f7 2068 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
mbed_official 25:ac5b0a371348 2069
mbed_official 25:ac5b0a371348 2070
mbed_official 25:ac5b0a371348 2071 /******************************************************************************/
mbed_official 25:ac5b0a371348 2072 /* */
mbed_official 25:ac5b0a371348 2073 /* Power Control */
mbed_official 25:ac5b0a371348 2074 /* */
mbed_official 25:ac5b0a371348 2075 /******************************************************************************/
mbed_official 25:ac5b0a371348 2076 /******************** Bit definition for PWR_CR register ********************/
<> 144:ef7eb2e8f9f7 2077 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
<> 144:ef7eb2e8f9f7 2078 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
<> 144:ef7eb2e8f9f7 2079 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
<> 144:ef7eb2e8f9f7 2080 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
<> 144:ef7eb2e8f9f7 2081 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
<> 144:ef7eb2e8f9f7 2082
<> 144:ef7eb2e8f9f7 2083 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
<> 144:ef7eb2e8f9f7 2084 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2085 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2086 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
mbed_official 25:ac5b0a371348 2087
mbed_official 25:ac5b0a371348 2088 /*!< PVD level configuration */
<> 144:ef7eb2e8f9f7 2089 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
<> 144:ef7eb2e8f9f7 2090 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
<> 144:ef7eb2e8f9f7 2091 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
<> 144:ef7eb2e8f9f7 2092 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
<> 144:ef7eb2e8f9f7 2093 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
<> 144:ef7eb2e8f9f7 2094 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
<> 144:ef7eb2e8f9f7 2095 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
<> 144:ef7eb2e8f9f7 2096 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
<> 144:ef7eb2e8f9f7 2097
<> 144:ef7eb2e8f9f7 2098 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
<> 144:ef7eb2e8f9f7 2099 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
<> 144:ef7eb2e8f9f7 2100 #define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
<> 144:ef7eb2e8f9f7 2101 #define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
<> 144:ef7eb2e8f9f7 2102 #define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 2103
<> 144:ef7eb2e8f9f7 2104 #define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
<> 144:ef7eb2e8f9f7 2105 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2106 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2107
<> 144:ef7eb2e8f9f7 2108 #define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
<> 144:ef7eb2e8f9f7 2109 #define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
mbed_official 25:ac5b0a371348 2110 /* Legacy define */
mbed_official 25:ac5b0a371348 2111 #define PWR_CR_PMODE PWR_CR_VOS
mbed_official 25:ac5b0a371348 2112
mbed_official 25:ac5b0a371348 2113 /******************* Bit definition for PWR_CSR register ********************/
<> 144:ef7eb2e8f9f7 2114 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
<> 144:ef7eb2e8f9f7 2115 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
<> 144:ef7eb2e8f9f7 2116 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
<> 144:ef7eb2e8f9f7 2117 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
<> 144:ef7eb2e8f9f7 2118 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
<> 144:ef7eb2e8f9f7 2119 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
<> 144:ef7eb2e8f9f7 2120 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
mbed_official 25:ac5b0a371348 2121
mbed_official 25:ac5b0a371348 2122 /* Legacy define */
mbed_official 25:ac5b0a371348 2123 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
mbed_official 25:ac5b0a371348 2124
mbed_official 25:ac5b0a371348 2125 /******************************************************************************/
mbed_official 25:ac5b0a371348 2126 /* */
mbed_official 25:ac5b0a371348 2127 /* Reset and Clock Control */
mbed_official 25:ac5b0a371348 2128 /* */
mbed_official 25:ac5b0a371348 2129 /******************************************************************************/
mbed_official 25:ac5b0a371348 2130 /******************** Bit definition for RCC_CR register ********************/
<> 144:ef7eb2e8f9f7 2131 #define RCC_CR_HSION 0x00000001U
<> 144:ef7eb2e8f9f7 2132 #define RCC_CR_HSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 2133
<> 144:ef7eb2e8f9f7 2134 #define RCC_CR_HSITRIM 0x000000F8U
<> 144:ef7eb2e8f9f7 2135 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2136 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2137 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2138 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2139 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
<> 144:ef7eb2e8f9f7 2140
<> 144:ef7eb2e8f9f7 2141 #define RCC_CR_HSICAL 0x0000FF00U
<> 144:ef7eb2e8f9f7 2142 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2143 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2144 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2145 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2146 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
<> 144:ef7eb2e8f9f7 2147 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
<> 144:ef7eb2e8f9f7 2148 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
<> 144:ef7eb2e8f9f7 2149 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
<> 144:ef7eb2e8f9f7 2150
<> 144:ef7eb2e8f9f7 2151 #define RCC_CR_HSEON 0x00010000U
<> 144:ef7eb2e8f9f7 2152 #define RCC_CR_HSERDY 0x00020000U
<> 144:ef7eb2e8f9f7 2153 #define RCC_CR_HSEBYP 0x00040000U
<> 144:ef7eb2e8f9f7 2154 #define RCC_CR_CSSON 0x00080000U
<> 144:ef7eb2e8f9f7 2155 #define RCC_CR_PLLON 0x01000000U
<> 144:ef7eb2e8f9f7 2156 #define RCC_CR_PLLRDY 0x02000000U
mbed_official 25:ac5b0a371348 2157
mbed_official 25:ac5b0a371348 2158 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 144:ef7eb2e8f9f7 2159 #define RCC_PLLCFGR_PLLM 0x0000003FU
<> 144:ef7eb2e8f9f7 2160 #define RCC_PLLCFGR_PLLM_0 0x00000001U
<> 144:ef7eb2e8f9f7 2161 #define RCC_PLLCFGR_PLLM_1 0x00000002U
<> 144:ef7eb2e8f9f7 2162 #define RCC_PLLCFGR_PLLM_2 0x00000004U
<> 144:ef7eb2e8f9f7 2163 #define RCC_PLLCFGR_PLLM_3 0x00000008U
<> 144:ef7eb2e8f9f7 2164 #define RCC_PLLCFGR_PLLM_4 0x00000010U
<> 144:ef7eb2e8f9f7 2165 #define RCC_PLLCFGR_PLLM_5 0x00000020U
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 #define RCC_PLLCFGR_PLLN 0x00007FC0U
<> 144:ef7eb2e8f9f7 2168 #define RCC_PLLCFGR_PLLN_0 0x00000040U
<> 144:ef7eb2e8f9f7 2169 #define RCC_PLLCFGR_PLLN_1 0x00000080U
<> 144:ef7eb2e8f9f7 2170 #define RCC_PLLCFGR_PLLN_2 0x00000100U
<> 144:ef7eb2e8f9f7 2171 #define RCC_PLLCFGR_PLLN_3 0x00000200U
<> 144:ef7eb2e8f9f7 2172 #define RCC_PLLCFGR_PLLN_4 0x00000400U
<> 144:ef7eb2e8f9f7 2173 #define RCC_PLLCFGR_PLLN_5 0x00000800U
<> 144:ef7eb2e8f9f7 2174 #define RCC_PLLCFGR_PLLN_6 0x00001000U
<> 144:ef7eb2e8f9f7 2175 #define RCC_PLLCFGR_PLLN_7 0x00002000U
<> 144:ef7eb2e8f9f7 2176 #define RCC_PLLCFGR_PLLN_8 0x00004000U
<> 144:ef7eb2e8f9f7 2177
<> 144:ef7eb2e8f9f7 2178 #define RCC_PLLCFGR_PLLP 0x00030000U
<> 144:ef7eb2e8f9f7 2179 #define RCC_PLLCFGR_PLLP_0 0x00010000U
<> 144:ef7eb2e8f9f7 2180 #define RCC_PLLCFGR_PLLP_1 0x00020000U
<> 144:ef7eb2e8f9f7 2181
<> 144:ef7eb2e8f9f7 2182 #define RCC_PLLCFGR_PLLSRC 0x00400000U
<> 144:ef7eb2e8f9f7 2183 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
<> 144:ef7eb2e8f9f7 2184 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
<> 144:ef7eb2e8f9f7 2185
<> 144:ef7eb2e8f9f7 2186 #define RCC_PLLCFGR_PLLQ 0x0F000000U
<> 144:ef7eb2e8f9f7 2187 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
<> 144:ef7eb2e8f9f7 2188 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
<> 144:ef7eb2e8f9f7 2189 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
<> 144:ef7eb2e8f9f7 2190 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
<> 144:ef7eb2e8f9f7 2191
<> 144:ef7eb2e8f9f7 2192 #define RCC_PLLCFGR_PLLR 0x70000000U
<> 144:ef7eb2e8f9f7 2193 #define RCC_PLLCFGR_PLLR_0 0x10000000U
<> 144:ef7eb2e8f9f7 2194 #define RCC_PLLCFGR_PLLR_1 0x20000000U
<> 144:ef7eb2e8f9f7 2195 #define RCC_PLLCFGR_PLLR_2 0x40000000U
mbed_official 25:ac5b0a371348 2196 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 25:ac5b0a371348 2197 /*!< SW configuration */
<> 144:ef7eb2e8f9f7 2198 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
<> 144:ef7eb2e8f9f7 2199 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2200 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2201
<> 144:ef7eb2e8f9f7 2202 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
<> 144:ef7eb2e8f9f7 2203 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
<> 144:ef7eb2e8f9f7 2204 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
mbed_official 25:ac5b0a371348 2205
mbed_official 25:ac5b0a371348 2206 /*!< SWS configuration */
<> 144:ef7eb2e8f9f7 2207 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 144:ef7eb2e8f9f7 2208 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2209 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2210
<> 144:ef7eb2e8f9f7 2211 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
<> 144:ef7eb2e8f9f7 2212 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
<> 144:ef7eb2e8f9f7 2213 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
mbed_official 25:ac5b0a371348 2214
mbed_official 25:ac5b0a371348 2215 /*!< HPRE configuration */
<> 144:ef7eb2e8f9f7 2216 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
<> 144:ef7eb2e8f9f7 2217 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2218 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2219 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2220 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
<> 144:ef7eb2e8f9f7 2223 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2224 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2225 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2226 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
<> 144:ef7eb2e8f9f7 2227 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
<> 144:ef7eb2e8f9f7 2228 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
<> 144:ef7eb2e8f9f7 2229 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
<> 144:ef7eb2e8f9f7 2230 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
mbed_official 25:ac5b0a371348 2231
mbed_official 25:ac5b0a371348 2232 /*!< MCO1EN configuration */
<> 144:ef7eb2e8f9f7 2233 #define RCC_CFGR_MCO1EN 0x00000100U /*!< MCO1EN bit */
mbed_official 25:ac5b0a371348 2234
mbed_official 25:ac5b0a371348 2235 /*!< MCO2EN configuration */
<> 144:ef7eb2e8f9f7 2236 #define RCC_CFGR_MCO2EN 0x00000200U /*!< MCO2EN bit */
mbed_official 25:ac5b0a371348 2237
mbed_official 25:ac5b0a371348 2238 /*!< PPRE1 configuration */
<> 144:ef7eb2e8f9f7 2239 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 144:ef7eb2e8f9f7 2240 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2241 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2242 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2243
<> 144:ef7eb2e8f9f7 2244 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 2245 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2246 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2247 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2248 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
mbed_official 25:ac5b0a371348 2249
mbed_official 25:ac5b0a371348 2250 /*!< PPRE2 configuration */
<> 144:ef7eb2e8f9f7 2251 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 144:ef7eb2e8f9f7 2252 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2253 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2254 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2255
<> 144:ef7eb2e8f9f7 2256 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 2257 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2258 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2259 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2260 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
mbed_official 25:ac5b0a371348 2261
mbed_official 25:ac5b0a371348 2262 /*!< RTCPRE configuration */
<> 144:ef7eb2e8f9f7 2263 #define RCC_CFGR_RTCPRE 0x001F0000U
<> 144:ef7eb2e8f9f7 2264 #define RCC_CFGR_RTCPRE_0 0x00010000U
<> 144:ef7eb2e8f9f7 2265 #define RCC_CFGR_RTCPRE_1 0x00020000U
<> 144:ef7eb2e8f9f7 2266 #define RCC_CFGR_RTCPRE_2 0x00040000U
<> 144:ef7eb2e8f9f7 2267 #define RCC_CFGR_RTCPRE_3 0x00080000U
<> 144:ef7eb2e8f9f7 2268 #define RCC_CFGR_RTCPRE_4 0x00100000U
mbed_official 25:ac5b0a371348 2269
mbed_official 25:ac5b0a371348 2270 /*!< MCO1 configuration */
<> 144:ef7eb2e8f9f7 2271 #define RCC_CFGR_MCO1 0x00600000U
<> 144:ef7eb2e8f9f7 2272 #define RCC_CFGR_MCO1_0 0x00200000U
<> 144:ef7eb2e8f9f7 2273 #define RCC_CFGR_MCO1_1 0x00400000U
<> 144:ef7eb2e8f9f7 2274
<> 144:ef7eb2e8f9f7 2275 #define RCC_CFGR_MCO1PRE 0x07000000U
<> 144:ef7eb2e8f9f7 2276 #define RCC_CFGR_MCO1PRE_0 0x01000000U
<> 144:ef7eb2e8f9f7 2277 #define RCC_CFGR_MCO1PRE_1 0x02000000U
<> 144:ef7eb2e8f9f7 2278 #define RCC_CFGR_MCO1PRE_2 0x04000000U
<> 144:ef7eb2e8f9f7 2279
<> 144:ef7eb2e8f9f7 2280 #define RCC_CFGR_MCO2PRE 0x38000000U
<> 144:ef7eb2e8f9f7 2281 #define RCC_CFGR_MCO2PRE_0 0x08000000U
<> 144:ef7eb2e8f9f7 2282 #define RCC_CFGR_MCO2PRE_1 0x10000000U
<> 144:ef7eb2e8f9f7 2283 #define RCC_CFGR_MCO2PRE_2 0x20000000U
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 #define RCC_CFGR_MCO2 0xC0000000U
<> 144:ef7eb2e8f9f7 2286 #define RCC_CFGR_MCO2_0 0x40000000U
<> 144:ef7eb2e8f9f7 2287 #define RCC_CFGR_MCO2_1 0x80000000U
mbed_official 25:ac5b0a371348 2288
mbed_official 25:ac5b0a371348 2289 /******************** Bit definition for RCC_CIR register *******************/
<> 144:ef7eb2e8f9f7 2290 #define RCC_CIR_LSIRDYF 0x00000001U
<> 144:ef7eb2e8f9f7 2291 #define RCC_CIR_LSERDYF 0x00000002U
<> 144:ef7eb2e8f9f7 2292 #define RCC_CIR_HSIRDYF 0x00000004U
<> 144:ef7eb2e8f9f7 2293 #define RCC_CIR_HSERDYF 0x00000008U
<> 144:ef7eb2e8f9f7 2294 #define RCC_CIR_PLLRDYF 0x00000010U
<> 144:ef7eb2e8f9f7 2295
<> 144:ef7eb2e8f9f7 2296 #define RCC_CIR_CSSF 0x00000080U
<> 144:ef7eb2e8f9f7 2297 #define RCC_CIR_LSIRDYIE 0x00000100U
<> 144:ef7eb2e8f9f7 2298 #define RCC_CIR_LSERDYIE 0x00000200U
<> 144:ef7eb2e8f9f7 2299 #define RCC_CIR_HSIRDYIE 0x00000400U
<> 144:ef7eb2e8f9f7 2300 #define RCC_CIR_HSERDYIE 0x00000800U
<> 144:ef7eb2e8f9f7 2301 #define RCC_CIR_PLLRDYIE 0x00001000U
<> 144:ef7eb2e8f9f7 2302
<> 144:ef7eb2e8f9f7 2303 #define RCC_CIR_LSIRDYC 0x00010000U
<> 144:ef7eb2e8f9f7 2304 #define RCC_CIR_LSERDYC 0x00020000U
<> 144:ef7eb2e8f9f7 2305 #define RCC_CIR_HSIRDYC 0x00040000U
<> 144:ef7eb2e8f9f7 2306 #define RCC_CIR_HSERDYC 0x00080000U
<> 144:ef7eb2e8f9f7 2307 #define RCC_CIR_PLLRDYC 0x00100000U
<> 144:ef7eb2e8f9f7 2308
<> 144:ef7eb2e8f9f7 2309 #define RCC_CIR_CSSC 0x00800000U
mbed_official 25:ac5b0a371348 2310
mbed_official 25:ac5b0a371348 2311 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 144:ef7eb2e8f9f7 2312 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
<> 144:ef7eb2e8f9f7 2313 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
<> 144:ef7eb2e8f9f7 2314 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
<> 144:ef7eb2e8f9f7 2315 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
<> 144:ef7eb2e8f9f7 2316 #define RCC_AHB1RSTR_CRCRST 0x00001000U
<> 144:ef7eb2e8f9f7 2317 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
<> 144:ef7eb2e8f9f7 2318 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
<> 144:ef7eb2e8f9f7 2319 #define RCC_AHB1RSTR_RNGRST 0x80000000U
mbed_official 25:ac5b0a371348 2320
mbed_official 25:ac5b0a371348 2321 /******************** Bit definition for RCC_APB1RSTR register **************/
<> 144:ef7eb2e8f9f7 2322 #define RCC_APB1RSTR_TIM5RST 0x00000008U
<> 144:ef7eb2e8f9f7 2323 #define RCC_APB1RSTR_TIM6RST 0x00000010U
<> 144:ef7eb2e8f9f7 2324 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
<> 144:ef7eb2e8f9f7 2325 #define RCC_APB1RSTR_WWDGRST 0x00000800U
<> 144:ef7eb2e8f9f7 2326 #define RCC_APB1RSTR_SPI2RST 0x00004000U
<> 144:ef7eb2e8f9f7 2327 #define RCC_APB1RSTR_USART2RST 0x00020000U
<> 144:ef7eb2e8f9f7 2328 #define RCC_APB1RSTR_I2C1RST 0x00200000U
<> 144:ef7eb2e8f9f7 2329 #define RCC_APB1RSTR_I2C2RST 0x00400000U
<> 144:ef7eb2e8f9f7 2330 #define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
<> 144:ef7eb2e8f9f7 2331 #define RCC_APB1RSTR_PWRRST 0x10000000U
<> 144:ef7eb2e8f9f7 2332 #define RCC_APB1RSTR_DACRST 0x20000000U
mbed_official 25:ac5b0a371348 2333
mbed_official 25:ac5b0a371348 2334 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 144:ef7eb2e8f9f7 2335 #define RCC_APB2RSTR_TIM1RST 0x00000001U
<> 144:ef7eb2e8f9f7 2336 #define RCC_APB2RSTR_USART1RST 0x00000010U
<> 144:ef7eb2e8f9f7 2337 #define RCC_APB2RSTR_USART6RST 0x00000020U
<> 144:ef7eb2e8f9f7 2338 #define RCC_APB2RSTR_ADCRST 0x00000100U
<> 144:ef7eb2e8f9f7 2339 #define RCC_APB2RSTR_SPI1RST 0x00001000U
<> 144:ef7eb2e8f9f7 2340 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
<> 144:ef7eb2e8f9f7 2341 #define RCC_APB2RSTR_TIM9RST 0x00010000U
<> 144:ef7eb2e8f9f7 2342 #define RCC_APB2RSTR_TIM11RST 0x00040000U
<> 144:ef7eb2e8f9f7 2343 #define RCC_APB2RSTR_SPI5RST 0x00100000U
mbed_official 25:ac5b0a371348 2344
mbed_official 25:ac5b0a371348 2345 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 144:ef7eb2e8f9f7 2346 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
<> 144:ef7eb2e8f9f7 2347 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
<> 144:ef7eb2e8f9f7 2348 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
<> 144:ef7eb2e8f9f7 2349 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
<> 144:ef7eb2e8f9f7 2350 #define RCC_AHB1ENR_CRCEN 0x00001000U
<> 144:ef7eb2e8f9f7 2351 #define RCC_AHB1ENR_DMA1EN 0x00200000U
<> 144:ef7eb2e8f9f7 2352 #define RCC_AHB1ENR_DMA2EN 0x00400000U
<> 144:ef7eb2e8f9f7 2353 #define RCC_AHB1ENR_RNGEN 0x80000000U
mbed_official 25:ac5b0a371348 2354
mbed_official 25:ac5b0a371348 2355 /******************** Bit definition for RCC_APB1ENR register ***************/
<> 144:ef7eb2e8f9f7 2356 #define RCC_APB1ENR_TIM5EN 0x00000008U
<> 144:ef7eb2e8f9f7 2357 #define RCC_APB1ENR_TIM6EN 0x00000010U
<> 144:ef7eb2e8f9f7 2358 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
<> 144:ef7eb2e8f9f7 2359 #define RCC_APB1ENR_RTCAPBEN 0x00000400U
<> 144:ef7eb2e8f9f7 2360 #define RCC_APB1ENR_WWDGEN 0x00000800U
<> 144:ef7eb2e8f9f7 2361 #define RCC_APB1ENR_SPI2EN 0x00004000U
<> 144:ef7eb2e8f9f7 2362 #define RCC_APB1ENR_USART2EN 0x00020000U
<> 144:ef7eb2e8f9f7 2363 #define RCC_APB1ENR_I2C1EN 0x00200000U
<> 144:ef7eb2e8f9f7 2364 #define RCC_APB1ENR_I2C2EN 0x00400000U
<> 144:ef7eb2e8f9f7 2365 #define RCC_APB1ENR_FMPI2C1EN 0x01000000U
<> 144:ef7eb2e8f9f7 2366 #define RCC_APB1ENR_PWREN 0x10000000U
<> 144:ef7eb2e8f9f7 2367 #define RCC_APB1ENR_DACEN 0x20000000U
mbed_official 25:ac5b0a371348 2368
mbed_official 25:ac5b0a371348 2369 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 144:ef7eb2e8f9f7 2370 #define RCC_APB2ENR_TIM1EN 0x00000001U
<> 144:ef7eb2e8f9f7 2371 #define RCC_APB2ENR_USART1EN 0x00000010U
<> 144:ef7eb2e8f9f7 2372 #define RCC_APB2ENR_USART6EN 0x00000020U
<> 144:ef7eb2e8f9f7 2373 #define RCC_APB2ENR_ADC1EN 0x00000100U
<> 144:ef7eb2e8f9f7 2374 #define RCC_APB2ENR_SPI1EN 0x00001000U
<> 144:ef7eb2e8f9f7 2375 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
<> 144:ef7eb2e8f9f7 2376 #define RCC_APB2ENR_EXTITEN 0x00008000U
<> 144:ef7eb2e8f9f7 2377 #define RCC_APB2ENR_TIM9EN 0x00010000U
<> 144:ef7eb2e8f9f7 2378 #define RCC_APB2ENR_TIM11EN 0x00040000U
<> 144:ef7eb2e8f9f7 2379 #define RCC_APB2ENR_SPI5EN 0x00100000U
mbed_official 25:ac5b0a371348 2380
mbed_official 25:ac5b0a371348 2381 /******************** Bit definition for RCC_AHB1LPENR register *************/
<> 144:ef7eb2e8f9f7 2382 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
<> 144:ef7eb2e8f9f7 2383 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
<> 144:ef7eb2e8f9f7 2384 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
<> 144:ef7eb2e8f9f7 2385 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
<> 144:ef7eb2e8f9f7 2386 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
<> 144:ef7eb2e8f9f7 2387 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
<> 144:ef7eb2e8f9f7 2388 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 2389 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 2390 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 2391 #define RCC_AHB1LPENR_RNGLPEN 0x80000000U
mbed_official 25:ac5b0a371348 2392
mbed_official 25:ac5b0a371348 2393 /******************** Bit definition for RCC_APB1LPENR register *************/
<> 144:ef7eb2e8f9f7 2394 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
<> 144:ef7eb2e8f9f7 2395 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
<> 144:ef7eb2e8f9f7 2396 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
<> 144:ef7eb2e8f9f7 2397 #define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
<> 144:ef7eb2e8f9f7 2398 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
<> 144:ef7eb2e8f9f7 2399 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
<> 144:ef7eb2e8f9f7 2400 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 2401 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 2402 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 2403 #define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
<> 144:ef7eb2e8f9f7 2404 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
<> 144:ef7eb2e8f9f7 2405 #define RCC_APB1LPENR_DACLPEN 0x20000000U
mbed_official 25:ac5b0a371348 2406
mbed_official 25:ac5b0a371348 2407 /******************** Bit definition for RCC_APB2LPENR register *************/
<> 144:ef7eb2e8f9f7 2408 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
<> 144:ef7eb2e8f9f7 2409 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
<> 144:ef7eb2e8f9f7 2410 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
<> 144:ef7eb2e8f9f7 2411 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
<> 144:ef7eb2e8f9f7 2412 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
<> 144:ef7eb2e8f9f7 2413 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
<> 144:ef7eb2e8f9f7 2414 #define RCC_APB2LPENR_EXTITLPEN 0x00008000U
<> 144:ef7eb2e8f9f7 2415 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 2416 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
<> 144:ef7eb2e8f9f7 2417 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
mbed_official 25:ac5b0a371348 2418
mbed_official 25:ac5b0a371348 2419 /******************** Bit definition for RCC_BDCR register ******************/
<> 144:ef7eb2e8f9f7 2420 #define RCC_BDCR_LSEON 0x00000001U
<> 144:ef7eb2e8f9f7 2421 #define RCC_BDCR_LSERDY 0x00000002U
<> 144:ef7eb2e8f9f7 2422 #define RCC_BDCR_LSEBYP 0x00000004U
<> 144:ef7eb2e8f9f7 2423 #define RCC_BDCR_LSEMOD 0x00000008U
<> 144:ef7eb2e8f9f7 2424
<> 144:ef7eb2e8f9f7 2425 #define RCC_BDCR_RTCSEL 0x00000300U
<> 144:ef7eb2e8f9f7 2426 #define RCC_BDCR_RTCSEL_0 0x00000100U
<> 144:ef7eb2e8f9f7 2427 #define RCC_BDCR_RTCSEL_1 0x00000200U
<> 144:ef7eb2e8f9f7 2428
<> 144:ef7eb2e8f9f7 2429 #define RCC_BDCR_RTCEN 0x00008000U
<> 144:ef7eb2e8f9f7 2430 #define RCC_BDCR_BDRST 0x00010000U
mbed_official 25:ac5b0a371348 2431
mbed_official 25:ac5b0a371348 2432 /******************** Bit definition for RCC_CSR register *******************/
<> 144:ef7eb2e8f9f7 2433 #define RCC_CSR_LSION 0x00000001U
<> 144:ef7eb2e8f9f7 2434 #define RCC_CSR_LSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 2435 #define RCC_CSR_RMVF 0x01000000U
<> 144:ef7eb2e8f9f7 2436 #define RCC_CSR_BORRSTF 0x02000000U
<> 144:ef7eb2e8f9f7 2437 #define RCC_CSR_PADRSTF 0x04000000U
<> 144:ef7eb2e8f9f7 2438 #define RCC_CSR_PORRSTF 0x08000000U
<> 144:ef7eb2e8f9f7 2439 #define RCC_CSR_SFTRSTF 0x10000000U
<> 144:ef7eb2e8f9f7 2440 #define RCC_CSR_WDGRSTF 0x20000000U
<> 144:ef7eb2e8f9f7 2441 #define RCC_CSR_WWDGRSTF 0x40000000U
<> 144:ef7eb2e8f9f7 2442 #define RCC_CSR_LPWRRSTF 0x80000000U
mbed_official 25:ac5b0a371348 2443
mbed_official 25:ac5b0a371348 2444 /******************** Bit definition for RCC_SSCGR register *****************/
<> 144:ef7eb2e8f9f7 2445 #define RCC_SSCGR_MODPER 0x00001FFFU
<> 144:ef7eb2e8f9f7 2446 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
<> 144:ef7eb2e8f9f7 2447 #define RCC_SSCGR_SPREADSEL 0x40000000U
<> 144:ef7eb2e8f9f7 2448 #define RCC_SSCGR_SSCGEN 0x80000000U
mbed_official 25:ac5b0a371348 2449
mbed_official 25:ac5b0a371348 2450 /******************** Bit definition for RCC_DCKCFGR register ***************/
<> 144:ef7eb2e8f9f7 2451 #define RCC_DCKCFGR_TIMPRE 0x01000000U
<> 144:ef7eb2e8f9f7 2452 #define RCC_DCKCFGR_I2SSRC 0x06000000U
<> 144:ef7eb2e8f9f7 2453 #define RCC_DCKCFGR_I2SSRC_0 0x02000000U
<> 144:ef7eb2e8f9f7 2454 #define RCC_DCKCFGR_I2SSRC_1 0x04000000U
mbed_official 25:ac5b0a371348 2455
mbed_official 25:ac5b0a371348 2456 /******************** Bit definition for RCC_CKGATENR register **************/
<> 144:ef7eb2e8f9f7 2457 #define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
<> 144:ef7eb2e8f9f7 2458 #define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
<> 144:ef7eb2e8f9f7 2459 #define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
<> 144:ef7eb2e8f9f7 2460 #define RCC_CKGATENR_SPARE_CKEN 0x00000008U
<> 144:ef7eb2e8f9f7 2461 #define RCC_CKGATENR_SRAM_CKEN 0x00000010U
<> 144:ef7eb2e8f9f7 2462 #define RCC_CKGATENR_FLITF_CKEN 0x00000020U
<> 144:ef7eb2e8f9f7 2463 #define RCC_CKGATENR_RCC_CKEN 0x00000040U
mbed_official 25:ac5b0a371348 2464
mbed_official 25:ac5b0a371348 2465 /******************** Bit definition for RCC_DCKCFGR2 register **************/
<> 144:ef7eb2e8f9f7 2466 #define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
<> 144:ef7eb2e8f9f7 2467 #define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
<> 144:ef7eb2e8f9f7 2468 #define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
<> 144:ef7eb2e8f9f7 2469 #define RCC_DCKCFGR2_LPTIM1SEL 0xC0000000U
<> 144:ef7eb2e8f9f7 2470 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x40000000U
<> 144:ef7eb2e8f9f7 2471 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x80000000U
mbed_official 25:ac5b0a371348 2472
mbed_official 25:ac5b0a371348 2473 /******************************************************************************/
mbed_official 25:ac5b0a371348 2474 /* */
mbed_official 25:ac5b0a371348 2475 /* RNG */
mbed_official 25:ac5b0a371348 2476 /* */
mbed_official 25:ac5b0a371348 2477 /******************************************************************************/
mbed_official 25:ac5b0a371348 2478 /******************** Bits definition for RNG_CR register *******************/
<> 144:ef7eb2e8f9f7 2479 #define RNG_CR_RNGEN 0x00000004U
<> 144:ef7eb2e8f9f7 2480 #define RNG_CR_IE 0x00000008U
mbed_official 25:ac5b0a371348 2481
mbed_official 25:ac5b0a371348 2482 /******************** Bits definition for RNG_SR register *******************/
<> 144:ef7eb2e8f9f7 2483 #define RNG_SR_DRDY 0x00000001U
<> 144:ef7eb2e8f9f7 2484 #define RNG_SR_CECS 0x00000002U
<> 144:ef7eb2e8f9f7 2485 #define RNG_SR_SECS 0x00000004U
<> 144:ef7eb2e8f9f7 2486 #define RNG_SR_CEIS 0x00000020U
<> 144:ef7eb2e8f9f7 2487 #define RNG_SR_SEIS 0x00000040U
mbed_official 25:ac5b0a371348 2488
mbed_official 25:ac5b0a371348 2489 /******************************************************************************/
mbed_official 25:ac5b0a371348 2490 /* */
mbed_official 25:ac5b0a371348 2491 /* Real-Time Clock (RTC) */
mbed_official 25:ac5b0a371348 2492 /* */
mbed_official 25:ac5b0a371348 2493 /******************************************************************************/
mbed_official 25:ac5b0a371348 2494 /******************** Bits definition for RTC_TR register *******************/
<> 144:ef7eb2e8f9f7 2495 #define RTC_TR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2496 #define RTC_TR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2497 #define RTC_TR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2498 #define RTC_TR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2499 #define RTC_TR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2500 #define RTC_TR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2501 #define RTC_TR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2502 #define RTC_TR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2503 #define RTC_TR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2504 #define RTC_TR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2505 #define RTC_TR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2506 #define RTC_TR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2507 #define RTC_TR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2508 #define RTC_TR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2509 #define RTC_TR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2510 #define RTC_TR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2511 #define RTC_TR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2512 #define RTC_TR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2513 #define RTC_TR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2514 #define RTC_TR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2515 #define RTC_TR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2516 #define RTC_TR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2517 #define RTC_TR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2518 #define RTC_TR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2519 #define RTC_TR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2520 #define RTC_TR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2521 #define RTC_TR_SU_3 0x00000008U
mbed_official 25:ac5b0a371348 2522
mbed_official 25:ac5b0a371348 2523 /******************** Bits definition for RTC_DR register *******************/
<> 144:ef7eb2e8f9f7 2524 #define RTC_DR_YT 0x00F00000U
<> 144:ef7eb2e8f9f7 2525 #define RTC_DR_YT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2526 #define RTC_DR_YT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2527 #define RTC_DR_YT_2 0x00400000U
<> 144:ef7eb2e8f9f7 2528 #define RTC_DR_YT_3 0x00800000U
<> 144:ef7eb2e8f9f7 2529 #define RTC_DR_YU 0x000F0000U
<> 144:ef7eb2e8f9f7 2530 #define RTC_DR_YU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2531 #define RTC_DR_YU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2532 #define RTC_DR_YU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2533 #define RTC_DR_YU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2534 #define RTC_DR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 2535 #define RTC_DR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 2536 #define RTC_DR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 2537 #define RTC_DR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 2538 #define RTC_DR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 2539 #define RTC_DR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 2540 #define RTC_DR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2541 #define RTC_DR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2542 #define RTC_DR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2543 #define RTC_DR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2544 #define RTC_DR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 2545 #define RTC_DR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 2546 #define RTC_DR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 2547 #define RTC_DR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 2548 #define RTC_DR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2549 #define RTC_DR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2550 #define RTC_DR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2551 #define RTC_DR_DU_3 0x00000008U
mbed_official 25:ac5b0a371348 2552
mbed_official 25:ac5b0a371348 2553 /******************** Bits definition for RTC_CR register *******************/
<> 144:ef7eb2e8f9f7 2554 #define RTC_CR_COE 0x00800000U
<> 144:ef7eb2e8f9f7 2555 #define RTC_CR_OSEL 0x00600000U
<> 144:ef7eb2e8f9f7 2556 #define RTC_CR_OSEL_0 0x00200000U
<> 144:ef7eb2e8f9f7 2557 #define RTC_CR_OSEL_1 0x00400000U
<> 144:ef7eb2e8f9f7 2558 #define RTC_CR_POL 0x00100000U
<> 144:ef7eb2e8f9f7 2559 #define RTC_CR_COSEL 0x00080000U
<> 144:ef7eb2e8f9f7 2560 #define RTC_CR_BCK 0x00040000U
<> 144:ef7eb2e8f9f7 2561 #define RTC_CR_SUB1H 0x00020000U
<> 144:ef7eb2e8f9f7 2562 #define RTC_CR_ADD1H 0x00010000U
<> 144:ef7eb2e8f9f7 2563 #define RTC_CR_TSIE 0x00008000U
<> 144:ef7eb2e8f9f7 2564 #define RTC_CR_WUTIE 0x00004000U
<> 144:ef7eb2e8f9f7 2565 #define RTC_CR_ALRBIE 0x00002000U
<> 144:ef7eb2e8f9f7 2566 #define RTC_CR_ALRAIE 0x00001000U
<> 144:ef7eb2e8f9f7 2567 #define RTC_CR_TSE 0x00000800U
<> 144:ef7eb2e8f9f7 2568 #define RTC_CR_WUTE 0x00000400U
<> 144:ef7eb2e8f9f7 2569 #define RTC_CR_ALRBE 0x00000200U
<> 144:ef7eb2e8f9f7 2570 #define RTC_CR_ALRAE 0x00000100U
<> 144:ef7eb2e8f9f7 2571 #define RTC_CR_DCE 0x00000080U
<> 144:ef7eb2e8f9f7 2572 #define RTC_CR_FMT 0x00000040U
<> 144:ef7eb2e8f9f7 2573 #define RTC_CR_BYPSHAD 0x00000020U
<> 144:ef7eb2e8f9f7 2574 #define RTC_CR_REFCKON 0x00000010U
<> 144:ef7eb2e8f9f7 2575 #define RTC_CR_TSEDGE 0x00000008U
<> 144:ef7eb2e8f9f7 2576 #define RTC_CR_WUCKSEL 0x00000007U
<> 144:ef7eb2e8f9f7 2577 #define RTC_CR_WUCKSEL_0 0x00000001U
<> 144:ef7eb2e8f9f7 2578 #define RTC_CR_WUCKSEL_1 0x00000002U
<> 144:ef7eb2e8f9f7 2579 #define RTC_CR_WUCKSEL_2 0x00000004U
mbed_official 25:ac5b0a371348 2580
mbed_official 25:ac5b0a371348 2581 /******************** Bits definition for RTC_ISR register ******************/
<> 144:ef7eb2e8f9f7 2582 #define RTC_ISR_RECALPF 0x00010000U
<> 144:ef7eb2e8f9f7 2583 #define RTC_ISR_TAMP1F 0x00002000U
<> 144:ef7eb2e8f9f7 2584 #define RTC_ISR_TAMP2F 0x00004000U
<> 144:ef7eb2e8f9f7 2585 #define RTC_ISR_TSOVF 0x00001000U
<> 144:ef7eb2e8f9f7 2586 #define RTC_ISR_TSF 0x00000800U
<> 144:ef7eb2e8f9f7 2587 #define RTC_ISR_WUTF 0x00000400U
<> 144:ef7eb2e8f9f7 2588 #define RTC_ISR_ALRBF 0x00000200U
<> 144:ef7eb2e8f9f7 2589 #define RTC_ISR_ALRAF 0x00000100U
<> 144:ef7eb2e8f9f7 2590 #define RTC_ISR_INIT 0x00000080U
<> 144:ef7eb2e8f9f7 2591 #define RTC_ISR_INITF 0x00000040U
<> 144:ef7eb2e8f9f7 2592 #define RTC_ISR_RSF 0x00000020U
<> 144:ef7eb2e8f9f7 2593 #define RTC_ISR_INITS 0x00000010U
<> 144:ef7eb2e8f9f7 2594 #define RTC_ISR_SHPF 0x00000008U
<> 144:ef7eb2e8f9f7 2595 #define RTC_ISR_WUTWF 0x00000004U
<> 144:ef7eb2e8f9f7 2596 #define RTC_ISR_ALRBWF 0x00000002U
<> 144:ef7eb2e8f9f7 2597 #define RTC_ISR_ALRAWF 0x00000001U
mbed_official 25:ac5b0a371348 2598
mbed_official 25:ac5b0a371348 2599 /******************** Bits definition for RTC_PRER register *****************/
<> 144:ef7eb2e8f9f7 2600 #define RTC_PRER_PREDIV_A 0x007F0000U
<> 144:ef7eb2e8f9f7 2601 #define RTC_PRER_PREDIV_S 0x00007FFFU
mbed_official 25:ac5b0a371348 2602
mbed_official 25:ac5b0a371348 2603 /******************** Bits definition for RTC_WUTR register *****************/
<> 144:ef7eb2e8f9f7 2604 #define RTC_WUTR_WUT 0x0000FFFFU
mbed_official 25:ac5b0a371348 2605
mbed_official 25:ac5b0a371348 2606 /******************** Bits definition for RTC_CALIBR register ***************/
<> 144:ef7eb2e8f9f7 2607 #define RTC_CALIBR_DCS 0x00000080U
<> 144:ef7eb2e8f9f7 2608 #define RTC_CALIBR_DC 0x0000001FU
mbed_official 25:ac5b0a371348 2609
mbed_official 25:ac5b0a371348 2610 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 144:ef7eb2e8f9f7 2611 #define RTC_ALRMAR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 2612 #define RTC_ALRMAR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 2613 #define RTC_ALRMAR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 2614 #define RTC_ALRMAR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 2615 #define RTC_ALRMAR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 2616 #define RTC_ALRMAR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 2617 #define RTC_ALRMAR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 2618 #define RTC_ALRMAR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 2619 #define RTC_ALRMAR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 2620 #define RTC_ALRMAR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 2621 #define RTC_ALRMAR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 2622 #define RTC_ALRMAR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2623 #define RTC_ALRMAR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2624 #define RTC_ALRMAR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2625 #define RTC_ALRMAR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2626 #define RTC_ALRMAR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2627 #define RTC_ALRMAR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2628 #define RTC_ALRMAR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2629 #define RTC_ALRMAR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2630 #define RTC_ALRMAR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2631 #define RTC_ALRMAR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 2632 #define RTC_ALRMAR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2633 #define RTC_ALRMAR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2634 #define RTC_ALRMAR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2635 #define RTC_ALRMAR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2636 #define RTC_ALRMAR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2637 #define RTC_ALRMAR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2638 #define RTC_ALRMAR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2639 #define RTC_ALRMAR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2640 #define RTC_ALRMAR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2641 #define RTC_ALRMAR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 2642 #define RTC_ALRMAR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2643 #define RTC_ALRMAR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2644 #define RTC_ALRMAR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2645 #define RTC_ALRMAR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2646 #define RTC_ALRMAR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2647 #define RTC_ALRMAR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2648 #define RTC_ALRMAR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2649 #define RTC_ALRMAR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2650 #define RTC_ALRMAR_SU_3 0x00000008U
mbed_official 25:ac5b0a371348 2651
mbed_official 25:ac5b0a371348 2652 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 144:ef7eb2e8f9f7 2653 #define RTC_ALRMBR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 2654 #define RTC_ALRMBR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 2655 #define RTC_ALRMBR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 2656 #define RTC_ALRMBR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 2657 #define RTC_ALRMBR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 2658 #define RTC_ALRMBR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 2659 #define RTC_ALRMBR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 2660 #define RTC_ALRMBR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 2661 #define RTC_ALRMBR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 2662 #define RTC_ALRMBR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 2663 #define RTC_ALRMBR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 2664 #define RTC_ALRMBR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2665 #define RTC_ALRMBR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2666 #define RTC_ALRMBR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2667 #define RTC_ALRMBR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2668 #define RTC_ALRMBR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2669 #define RTC_ALRMBR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2670 #define RTC_ALRMBR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2671 #define RTC_ALRMBR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2672 #define RTC_ALRMBR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2673 #define RTC_ALRMBR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 2674 #define RTC_ALRMBR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2675 #define RTC_ALRMBR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2676 #define RTC_ALRMBR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2677 #define RTC_ALRMBR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2678 #define RTC_ALRMBR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2679 #define RTC_ALRMBR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2680 #define RTC_ALRMBR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2681 #define RTC_ALRMBR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2682 #define RTC_ALRMBR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2683 #define RTC_ALRMBR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 2684 #define RTC_ALRMBR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2685 #define RTC_ALRMBR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2686 #define RTC_ALRMBR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2687 #define RTC_ALRMBR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2688 #define RTC_ALRMBR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2689 #define RTC_ALRMBR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2690 #define RTC_ALRMBR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2691 #define RTC_ALRMBR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2692 #define RTC_ALRMBR_SU_3 0x00000008U
mbed_official 25:ac5b0a371348 2693
mbed_official 25:ac5b0a371348 2694 /******************** Bits definition for RTC_WPR register ******************/
<> 144:ef7eb2e8f9f7 2695 #define RTC_WPR_KEY 0x000000FFU
mbed_official 25:ac5b0a371348 2696
mbed_official 25:ac5b0a371348 2697 /******************** Bits definition for RTC_SSR register ******************/
<> 144:ef7eb2e8f9f7 2698 #define RTC_SSR_SS 0x0000FFFFU
mbed_official 25:ac5b0a371348 2699
mbed_official 25:ac5b0a371348 2700 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 144:ef7eb2e8f9f7 2701 #define RTC_SHIFTR_SUBFS 0x00007FFFU
<> 144:ef7eb2e8f9f7 2702 #define RTC_SHIFTR_ADD1S 0x80000000U
mbed_official 25:ac5b0a371348 2703
mbed_official 25:ac5b0a371348 2704 /******************** Bits definition for RTC_TSTR register *****************/
<> 144:ef7eb2e8f9f7 2705 #define RTC_TSTR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2706 #define RTC_TSTR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2707 #define RTC_TSTR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2708 #define RTC_TSTR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2709 #define RTC_TSTR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2710 #define RTC_TSTR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2711 #define RTC_TSTR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2712 #define RTC_TSTR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2713 #define RTC_TSTR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2714 #define RTC_TSTR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2715 #define RTC_TSTR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2716 #define RTC_TSTR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2717 #define RTC_TSTR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2718 #define RTC_TSTR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2719 #define RTC_TSTR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2720 #define RTC_TSTR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2721 #define RTC_TSTR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2722 #define RTC_TSTR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2723 #define RTC_TSTR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2724 #define RTC_TSTR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2725 #define RTC_TSTR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2726 #define RTC_TSTR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2727 #define RTC_TSTR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2728 #define RTC_TSTR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2729 #define RTC_TSTR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2730 #define RTC_TSTR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2731 #define RTC_TSTR_SU_3 0x00000008U
mbed_official 25:ac5b0a371348 2732
mbed_official 25:ac5b0a371348 2733 /******************** Bits definition for RTC_TSDR register *****************/
<> 144:ef7eb2e8f9f7 2734 #define RTC_TSDR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 2735 #define RTC_TSDR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 2736 #define RTC_TSDR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 2737 #define RTC_TSDR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 2738 #define RTC_TSDR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 2739 #define RTC_TSDR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 2740 #define RTC_TSDR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2741 #define RTC_TSDR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2742 #define RTC_TSDR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2743 #define RTC_TSDR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2744 #define RTC_TSDR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 2745 #define RTC_TSDR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 2746 #define RTC_TSDR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 2747 #define RTC_TSDR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 2748 #define RTC_TSDR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2749 #define RTC_TSDR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2750 #define RTC_TSDR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2751 #define RTC_TSDR_DU_3 0x00000008U
mbed_official 25:ac5b0a371348 2752
mbed_official 25:ac5b0a371348 2753 /******************** Bits definition for RTC_TSSSR register ****************/
<> 144:ef7eb2e8f9f7 2754 #define RTC_TSSSR_SS 0x0000FFFFU
mbed_official 25:ac5b0a371348 2755
mbed_official 25:ac5b0a371348 2756 /******************** Bits definition for RTC_CAL register *****************/
<> 144:ef7eb2e8f9f7 2757 #define RTC_CALR_CALP 0x00008000U
<> 144:ef7eb2e8f9f7 2758 #define RTC_CALR_CALW8 0x00004000U
<> 144:ef7eb2e8f9f7 2759 #define RTC_CALR_CALW16 0x00002000U
<> 144:ef7eb2e8f9f7 2760 #define RTC_CALR_CALM 0x000001FFU
<> 144:ef7eb2e8f9f7 2761 #define RTC_CALR_CALM_0 0x00000001U
<> 144:ef7eb2e8f9f7 2762 #define RTC_CALR_CALM_1 0x00000002U
<> 144:ef7eb2e8f9f7 2763 #define RTC_CALR_CALM_2 0x00000004U
<> 144:ef7eb2e8f9f7 2764 #define RTC_CALR_CALM_3 0x00000008U
<> 144:ef7eb2e8f9f7 2765 #define RTC_CALR_CALM_4 0x00000010U
<> 144:ef7eb2e8f9f7 2766 #define RTC_CALR_CALM_5 0x00000020U
<> 144:ef7eb2e8f9f7 2767 #define RTC_CALR_CALM_6 0x00000040U
<> 144:ef7eb2e8f9f7 2768 #define RTC_CALR_CALM_7 0x00000080U
<> 144:ef7eb2e8f9f7 2769 #define RTC_CALR_CALM_8 0x00000100U
mbed_official 25:ac5b0a371348 2770
mbed_official 25:ac5b0a371348 2771 /******************** Bits definition for RTC_TAFCR register ****************/
<> 144:ef7eb2e8f9f7 2772 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
<> 144:ef7eb2e8f9f7 2773 #define RTC_TAFCR_TSINSEL 0x00020000U
<> 144:ef7eb2e8f9f7 2774 #define RTC_TAFCR_TAMPINSEL 0x00010000U
<> 144:ef7eb2e8f9f7 2775 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
<> 144:ef7eb2e8f9f7 2776 #define RTC_TAFCR_TAMPPRCH 0x00006000U
<> 144:ef7eb2e8f9f7 2777 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
<> 144:ef7eb2e8f9f7 2778 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
<> 144:ef7eb2e8f9f7 2779 #define RTC_TAFCR_TAMPFLT 0x00001800U
<> 144:ef7eb2e8f9f7 2780 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
<> 144:ef7eb2e8f9f7 2781 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
<> 144:ef7eb2e8f9f7 2782 #define RTC_TAFCR_TAMPFREQ 0x00000700U
<> 144:ef7eb2e8f9f7 2783 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
<> 144:ef7eb2e8f9f7 2784 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
<> 144:ef7eb2e8f9f7 2785 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
<> 144:ef7eb2e8f9f7 2786 #define RTC_TAFCR_TAMPTS 0x00000080U
<> 144:ef7eb2e8f9f7 2787 #define RTC_TAFCR_TAMP2TRG 0x00000010U
<> 144:ef7eb2e8f9f7 2788 #define RTC_TAFCR_TAMP2E 0x00000008U
<> 144:ef7eb2e8f9f7 2789 #define RTC_TAFCR_TAMPIE 0x00000004U
<> 144:ef7eb2e8f9f7 2790 #define RTC_TAFCR_TAMP1TRG 0x00000002U
<> 144:ef7eb2e8f9f7 2791 #define RTC_TAFCR_TAMP1E 0x00000001U
mbed_official 25:ac5b0a371348 2792
mbed_official 25:ac5b0a371348 2793 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 144:ef7eb2e8f9f7 2794 #define RTC_ALRMASSR_MASKSS 0x0F000000U
<> 144:ef7eb2e8f9f7 2795 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
<> 144:ef7eb2e8f9f7 2796 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
<> 144:ef7eb2e8f9f7 2797 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
<> 144:ef7eb2e8f9f7 2798 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
<> 144:ef7eb2e8f9f7 2799 #define RTC_ALRMASSR_SS 0x00007FFFU
mbed_official 25:ac5b0a371348 2800
mbed_official 25:ac5b0a371348 2801 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 144:ef7eb2e8f9f7 2802 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
<> 144:ef7eb2e8f9f7 2803 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
<> 144:ef7eb2e8f9f7 2804 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
<> 144:ef7eb2e8f9f7 2805 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
<> 144:ef7eb2e8f9f7 2806 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
<> 144:ef7eb2e8f9f7 2807 #define RTC_ALRMBSSR_SS 0x00007FFFU
mbed_official 25:ac5b0a371348 2808
mbed_official 25:ac5b0a371348 2809 /******************** Bits definition for RTC_BKP0R register ****************/
<> 144:ef7eb2e8f9f7 2810 #define RTC_BKP0R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2811
mbed_official 25:ac5b0a371348 2812 /******************** Bits definition for RTC_BKP1R register ****************/
<> 144:ef7eb2e8f9f7 2813 #define RTC_BKP1R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2814
mbed_official 25:ac5b0a371348 2815 /******************** Bits definition for RTC_BKP2R register ****************/
<> 144:ef7eb2e8f9f7 2816 #define RTC_BKP2R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2817
mbed_official 25:ac5b0a371348 2818 /******************** Bits definition for RTC_BKP3R register ****************/
<> 144:ef7eb2e8f9f7 2819 #define RTC_BKP3R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2820
mbed_official 25:ac5b0a371348 2821 /******************** Bits definition for RTC_BKP4R register ****************/
<> 144:ef7eb2e8f9f7 2822 #define RTC_BKP4R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2823
mbed_official 25:ac5b0a371348 2824 /******************** Bits definition for RTC_BKP5R register ****************/
<> 144:ef7eb2e8f9f7 2825 #define RTC_BKP5R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2826
mbed_official 25:ac5b0a371348 2827 /******************** Bits definition for RTC_BKP6R register ****************/
<> 144:ef7eb2e8f9f7 2828 #define RTC_BKP6R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2829
mbed_official 25:ac5b0a371348 2830 /******************** Bits definition for RTC_BKP7R register ****************/
<> 144:ef7eb2e8f9f7 2831 #define RTC_BKP7R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2832
mbed_official 25:ac5b0a371348 2833 /******************** Bits definition for RTC_BKP8R register ****************/
<> 144:ef7eb2e8f9f7 2834 #define RTC_BKP8R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2835
mbed_official 25:ac5b0a371348 2836 /******************** Bits definition for RTC_BKP9R register ****************/
<> 144:ef7eb2e8f9f7 2837 #define RTC_BKP9R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2838
mbed_official 25:ac5b0a371348 2839 /******************** Bits definition for RTC_BKP10R register ***************/
<> 144:ef7eb2e8f9f7 2840 #define RTC_BKP10R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2841
mbed_official 25:ac5b0a371348 2842 /******************** Bits definition for RTC_BKP11R register ***************/
<> 144:ef7eb2e8f9f7 2843 #define RTC_BKP11R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2844
mbed_official 25:ac5b0a371348 2845 /******************** Bits definition for RTC_BKP12R register ***************/
<> 144:ef7eb2e8f9f7 2846 #define RTC_BKP12R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2847
mbed_official 25:ac5b0a371348 2848 /******************** Bits definition for RTC_BKP13R register ***************/
<> 144:ef7eb2e8f9f7 2849 #define RTC_BKP13R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2850
mbed_official 25:ac5b0a371348 2851 /******************** Bits definition for RTC_BKP14R register ***************/
<> 144:ef7eb2e8f9f7 2852 #define RTC_BKP14R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2853
mbed_official 25:ac5b0a371348 2854 /******************** Bits definition for RTC_BKP15R register ***************/
<> 144:ef7eb2e8f9f7 2855 #define RTC_BKP15R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2856
mbed_official 25:ac5b0a371348 2857 /******************** Bits definition for RTC_BKP16R register ***************/
<> 144:ef7eb2e8f9f7 2858 #define RTC_BKP16R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2859
mbed_official 25:ac5b0a371348 2860 /******************** Bits definition for RTC_BKP17R register ***************/
<> 144:ef7eb2e8f9f7 2861 #define RTC_BKP17R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2862
mbed_official 25:ac5b0a371348 2863 /******************** Bits definition for RTC_BKP18R register ***************/
<> 144:ef7eb2e8f9f7 2864 #define RTC_BKP18R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2865
mbed_official 25:ac5b0a371348 2866 /******************** Bits definition for RTC_BKP19R register ***************/
<> 144:ef7eb2e8f9f7 2867 #define RTC_BKP19R 0xFFFFFFFFU
mbed_official 25:ac5b0a371348 2868
mbed_official 25:ac5b0a371348 2869 /******************************************************************************/
mbed_official 25:ac5b0a371348 2870 /* */
mbed_official 25:ac5b0a371348 2871 /* Serial Peripheral Interface */
mbed_official 25:ac5b0a371348 2872 /* */
mbed_official 25:ac5b0a371348 2873 /******************************************************************************/
mbed_official 25:ac5b0a371348 2874 /******************* Bit definition for SPI_CR1 register ********************/
<> 144:ef7eb2e8f9f7 2875 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
<> 144:ef7eb2e8f9f7 2876 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
<> 144:ef7eb2e8f9f7 2877 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
<> 144:ef7eb2e8f9f7 2878
<> 144:ef7eb2e8f9f7 2879 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
<> 144:ef7eb2e8f9f7 2880 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2881 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2882 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2883
<> 144:ef7eb2e8f9f7 2884 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
<> 144:ef7eb2e8f9f7 2885 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
<> 144:ef7eb2e8f9f7 2886 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
<> 144:ef7eb2e8f9f7 2887 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
<> 144:ef7eb2e8f9f7 2888 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
<> 144:ef7eb2e8f9f7 2889 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
<> 144:ef7eb2e8f9f7 2890 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
<> 144:ef7eb2e8f9f7 2891 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
<> 144:ef7eb2e8f9f7 2892 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
<> 144:ef7eb2e8f9f7 2893 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
mbed_official 25:ac5b0a371348 2894
mbed_official 25:ac5b0a371348 2895 /******************* Bit definition for SPI_CR2 register ********************/
<> 144:ef7eb2e8f9f7 2896 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 2897 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 2898 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
<> 144:ef7eb2e8f9f7 2899 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
<> 144:ef7eb2e8f9f7 2900 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 2901 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 2902 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
mbed_official 25:ac5b0a371348 2903
mbed_official 25:ac5b0a371348 2904 /******************** Bit definition for SPI_SR register ********************/
<> 144:ef7eb2e8f9f7 2905 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
<> 144:ef7eb2e8f9f7 2906 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
<> 144:ef7eb2e8f9f7 2907 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
<> 144:ef7eb2e8f9f7 2908 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
<> 144:ef7eb2e8f9f7 2909 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
<> 144:ef7eb2e8f9f7 2910 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
<> 144:ef7eb2e8f9f7 2911 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
<> 144:ef7eb2e8f9f7 2912 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
<> 144:ef7eb2e8f9f7 2913 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
mbed_official 25:ac5b0a371348 2914
mbed_official 25:ac5b0a371348 2915 /******************** Bit definition for SPI_DR register ********************/
<> 144:ef7eb2e8f9f7 2916 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
mbed_official 25:ac5b0a371348 2917
mbed_official 25:ac5b0a371348 2918 /******************* Bit definition for SPI_CRCPR register ******************/
<> 144:ef7eb2e8f9f7 2919 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
mbed_official 25:ac5b0a371348 2920
mbed_official 25:ac5b0a371348 2921 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 144:ef7eb2e8f9f7 2922 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
mbed_official 25:ac5b0a371348 2923
mbed_official 25:ac5b0a371348 2924 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 144:ef7eb2e8f9f7 2925 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
mbed_official 25:ac5b0a371348 2926
mbed_official 25:ac5b0a371348 2927 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 144:ef7eb2e8f9f7 2928 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
<> 144:ef7eb2e8f9f7 2929
<> 144:ef7eb2e8f9f7 2930 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 144:ef7eb2e8f9f7 2931 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2932 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2933
<> 144:ef7eb2e8f9f7 2934 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
<> 144:ef7eb2e8f9f7 2935
<> 144:ef7eb2e8f9f7 2936 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 144:ef7eb2e8f9f7 2937 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2938 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2939
<> 144:ef7eb2e8f9f7 2940 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
<> 144:ef7eb2e8f9f7 2941
<> 144:ef7eb2e8f9f7 2942 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 144:ef7eb2e8f9f7 2943 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2944 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2945
<> 144:ef7eb2e8f9f7 2946 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
<> 144:ef7eb2e8f9f7 2947 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
mbed_official 25:ac5b0a371348 2948
mbed_official 25:ac5b0a371348 2949 /****************** Bit definition for SPI_I2SPR register *******************/
<> 144:ef7eb2e8f9f7 2950 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
<> 144:ef7eb2e8f9f7 2951 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
<> 144:ef7eb2e8f9f7 2952 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
mbed_official 25:ac5b0a371348 2953
mbed_official 25:ac5b0a371348 2954 /******************************************************************************/
mbed_official 25:ac5b0a371348 2955 /* */
mbed_official 25:ac5b0a371348 2956 /* SYSCFG */
mbed_official 25:ac5b0a371348 2957 /* */
mbed_official 25:ac5b0a371348 2958 /******************************************************************************/
mbed_official 25:ac5b0a371348 2959 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 144:ef7eb2e8f9f7 2960 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
<> 144:ef7eb2e8f9f7 2961 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
<> 144:ef7eb2e8f9f7 2962 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
<> 144:ef7eb2e8f9f7 2963 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
mbed_official 25:ac5b0a371348 2964
mbed_official 25:ac5b0a371348 2965 /****************** Bit definition for SYSCFG_PMC register ******************/
<> 144:ef7eb2e8f9f7 2966 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
mbed_official 25:ac5b0a371348 2967
mbed_official 25:ac5b0a371348 2968 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 144:ef7eb2e8f9f7 2969 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
<> 144:ef7eb2e8f9f7 2970 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
<> 144:ef7eb2e8f9f7 2971 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
<> 144:ef7eb2e8f9f7 2972 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
mbed_official 25:ac5b0a371348 2973 /**
mbed_official 25:ac5b0a371348 2974 * @brief EXTI0 configuration
mbed_official 25:ac5b0a371348 2975 */
<> 144:ef7eb2e8f9f7 2976 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
<> 144:ef7eb2e8f9f7 2977 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
<> 144:ef7eb2e8f9f7 2978 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
<> 144:ef7eb2e8f9f7 2979 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
mbed_official 25:ac5b0a371348 2980
mbed_official 25:ac5b0a371348 2981 /**
mbed_official 25:ac5b0a371348 2982 * @brief EXTI1 configuration
mbed_official 25:ac5b0a371348 2983 */
<> 144:ef7eb2e8f9f7 2984 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
<> 144:ef7eb2e8f9f7 2985 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
<> 144:ef7eb2e8f9f7 2986 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
<> 144:ef7eb2e8f9f7 2987 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
mbed_official 25:ac5b0a371348 2988
mbed_official 25:ac5b0a371348 2989 /**
mbed_official 25:ac5b0a371348 2990 * @brief EXTI2 configuration
mbed_official 25:ac5b0a371348 2991 */
<> 144:ef7eb2e8f9f7 2992 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
<> 144:ef7eb2e8f9f7 2993 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
<> 144:ef7eb2e8f9f7 2994 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
<> 144:ef7eb2e8f9f7 2995 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
mbed_official 25:ac5b0a371348 2996
mbed_official 25:ac5b0a371348 2997 /**
mbed_official 25:ac5b0a371348 2998 * @brief EXTI3 configuration
mbed_official 25:ac5b0a371348 2999 */
<> 144:ef7eb2e8f9f7 3000 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
<> 144:ef7eb2e8f9f7 3001 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
<> 144:ef7eb2e8f9f7 3002 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
<> 144:ef7eb2e8f9f7 3003 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
mbed_official 25:ac5b0a371348 3004
mbed_official 25:ac5b0a371348 3005 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 144:ef7eb2e8f9f7 3006 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
<> 144:ef7eb2e8f9f7 3007 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
<> 144:ef7eb2e8f9f7 3008 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
<> 144:ef7eb2e8f9f7 3009 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
mbed_official 25:ac5b0a371348 3010 /**
mbed_official 25:ac5b0a371348 3011 * @brief EXTI4 configuration
mbed_official 25:ac5b0a371348 3012 */
<> 144:ef7eb2e8f9f7 3013 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
<> 144:ef7eb2e8f9f7 3014 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
<> 144:ef7eb2e8f9f7 3015 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
<> 144:ef7eb2e8f9f7 3016 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
mbed_official 25:ac5b0a371348 3017
mbed_official 25:ac5b0a371348 3018 /**
mbed_official 25:ac5b0a371348 3019 * @brief EXTI5 configuration
mbed_official 25:ac5b0a371348 3020 */
<> 144:ef7eb2e8f9f7 3021 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
<> 144:ef7eb2e8f9f7 3022 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
<> 144:ef7eb2e8f9f7 3023 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
<> 144:ef7eb2e8f9f7 3024 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
mbed_official 25:ac5b0a371348 3025
mbed_official 25:ac5b0a371348 3026 /**
mbed_official 25:ac5b0a371348 3027 * @brief EXTI6 configuration
mbed_official 25:ac5b0a371348 3028 */
<> 144:ef7eb2e8f9f7 3029 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
<> 144:ef7eb2e8f9f7 3030 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
<> 144:ef7eb2e8f9f7 3031 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
<> 144:ef7eb2e8f9f7 3032 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
mbed_official 25:ac5b0a371348 3033
mbed_official 25:ac5b0a371348 3034 /**
mbed_official 25:ac5b0a371348 3035 * @brief EXTI7 configuration
mbed_official 25:ac5b0a371348 3036 */
<> 144:ef7eb2e8f9f7 3037 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
<> 144:ef7eb2e8f9f7 3038 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
<> 144:ef7eb2e8f9f7 3039 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
<> 144:ef7eb2e8f9f7 3040 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
mbed_official 25:ac5b0a371348 3041
mbed_official 25:ac5b0a371348 3042
mbed_official 25:ac5b0a371348 3043 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 144:ef7eb2e8f9f7 3044 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
<> 144:ef7eb2e8f9f7 3045 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
<> 144:ef7eb2e8f9f7 3046 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
<> 144:ef7eb2e8f9f7 3047 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
mbed_official 25:ac5b0a371348 3048
mbed_official 25:ac5b0a371348 3049 /**
mbed_official 25:ac5b0a371348 3050 * @brief EXTI8 configuration
mbed_official 25:ac5b0a371348 3051 */
<> 144:ef7eb2e8f9f7 3052 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
<> 144:ef7eb2e8f9f7 3053 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
<> 144:ef7eb2e8f9f7 3054 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
<> 144:ef7eb2e8f9f7 3055 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
mbed_official 25:ac5b0a371348 3056
mbed_official 25:ac5b0a371348 3057 /**
mbed_official 25:ac5b0a371348 3058 * @brief EXTI9 configuration
mbed_official 25:ac5b0a371348 3059 */
<> 144:ef7eb2e8f9f7 3060 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
<> 144:ef7eb2e8f9f7 3061 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
<> 144:ef7eb2e8f9f7 3062 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
<> 144:ef7eb2e8f9f7 3063 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
mbed_official 25:ac5b0a371348 3064
mbed_official 25:ac5b0a371348 3065 /**
mbed_official 25:ac5b0a371348 3066 * @brief EXTI10 configuration
mbed_official 25:ac5b0a371348 3067 */
<> 144:ef7eb2e8f9f7 3068 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
<> 144:ef7eb2e8f9f7 3069 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
<> 144:ef7eb2e8f9f7 3070 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
<> 144:ef7eb2e8f9f7 3071 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
mbed_official 25:ac5b0a371348 3072
mbed_official 25:ac5b0a371348 3073 /**
mbed_official 25:ac5b0a371348 3074 * @brief EXTI11 configuration
mbed_official 25:ac5b0a371348 3075 */
<> 144:ef7eb2e8f9f7 3076 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
<> 144:ef7eb2e8f9f7 3077 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
<> 144:ef7eb2e8f9f7 3078 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
<> 144:ef7eb2e8f9f7 3079 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
mbed_official 25:ac5b0a371348 3080
mbed_official 25:ac5b0a371348 3081 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 144:ef7eb2e8f9f7 3082 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
<> 144:ef7eb2e8f9f7 3083 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
<> 144:ef7eb2e8f9f7 3084 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
<> 144:ef7eb2e8f9f7 3085 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
mbed_official 25:ac5b0a371348 3086 /**
mbed_official 25:ac5b0a371348 3087 * @brief EXTI12 configuration
mbed_official 25:ac5b0a371348 3088 */
<> 144:ef7eb2e8f9f7 3089 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
<> 144:ef7eb2e8f9f7 3090 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
<> 144:ef7eb2e8f9f7 3091 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
<> 144:ef7eb2e8f9f7 3092 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
mbed_official 25:ac5b0a371348 3093
mbed_official 25:ac5b0a371348 3094 /**
mbed_official 25:ac5b0a371348 3095 * @brief EXTI13 configuration
mbed_official 25:ac5b0a371348 3096 */
<> 144:ef7eb2e8f9f7 3097 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
<> 144:ef7eb2e8f9f7 3098 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
<> 144:ef7eb2e8f9f7 3099 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
<> 144:ef7eb2e8f9f7 3100 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
mbed_official 25:ac5b0a371348 3101
mbed_official 25:ac5b0a371348 3102 /**
mbed_official 25:ac5b0a371348 3103 * @brief EXTI14 configuration
mbed_official 25:ac5b0a371348 3104 */
<> 144:ef7eb2e8f9f7 3105 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
<> 144:ef7eb2e8f9f7 3106 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
<> 144:ef7eb2e8f9f7 3107 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
<> 144:ef7eb2e8f9f7 3108 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
mbed_official 25:ac5b0a371348 3109
mbed_official 25:ac5b0a371348 3110 /**
mbed_official 25:ac5b0a371348 3111 * @brief EXTI15 configuration
mbed_official 25:ac5b0a371348 3112 */
<> 144:ef7eb2e8f9f7 3113 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
<> 144:ef7eb2e8f9f7 3114 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
<> 144:ef7eb2e8f9f7 3115 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
<> 144:ef7eb2e8f9f7 3116 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
mbed_official 25:ac5b0a371348 3117
mbed_official 25:ac5b0a371348 3118 /****************** Bit definition for SYSCFG_CMPCR register ****************/
<> 144:ef7eb2e8f9f7 3119 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
<> 144:ef7eb2e8f9f7 3120 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
mbed_official 25:ac5b0a371348 3121
mbed_official 25:ac5b0a371348 3122 /****************** Bit definition for SYSCFG_CFGR register *****************/
<> 144:ef7eb2e8f9f7 3123 #define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
<> 144:ef7eb2e8f9f7 3124 #define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
mbed_official 25:ac5b0a371348 3125
mbed_official 25:ac5b0a371348 3126 /****************** Bit definition for SYSCFG_CFGR2 register *****************/
<> 144:ef7eb2e8f9f7 3127 #define SYSCFG_CFGR2_LOCKUP_LOCK 0x00000001U /*!<Core Lockup lock */
<> 144:ef7eb2e8f9f7 3128 #define SYSCFG_CFGR2_PVD_LOCK 0x00000004U /*!<PVD Lock */
mbed_official 25:ac5b0a371348 3129
mbed_official 25:ac5b0a371348 3130 /******************************************************************************/
mbed_official 25:ac5b0a371348 3131 /* */
mbed_official 25:ac5b0a371348 3132 /* TIM */
mbed_official 25:ac5b0a371348 3133 /* */
mbed_official 25:ac5b0a371348 3134 /******************************************************************************/
mbed_official 25:ac5b0a371348 3135 /******************* Bit definition for TIM_CR1 register ********************/
<> 144:ef7eb2e8f9f7 3136 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
<> 144:ef7eb2e8f9f7 3137 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
<> 144:ef7eb2e8f9f7 3138 #define TIM_CR1_URS 0x0004U /*!<Update request source */
<> 144:ef7eb2e8f9f7 3139 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
<> 144:ef7eb2e8f9f7 3140 #define TIM_CR1_DIR 0x0010U /*!<Direction */
<> 144:ef7eb2e8f9f7 3141
<> 144:ef7eb2e8f9f7 3142 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 144:ef7eb2e8f9f7 3143 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3144 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3145
<> 144:ef7eb2e8f9f7 3146 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
<> 144:ef7eb2e8f9f7 3147
<> 144:ef7eb2e8f9f7 3148 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
<> 144:ef7eb2e8f9f7 3149 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3150 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3151
mbed_official 25:ac5b0a371348 3152 /******************* Bit definition for TIM_CR2 register ********************/
<> 144:ef7eb2e8f9f7 3153 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
<> 144:ef7eb2e8f9f7 3154 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
<> 144:ef7eb2e8f9f7 3155 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
<> 144:ef7eb2e8f9f7 3156
<> 144:ef7eb2e8f9f7 3157 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 144:ef7eb2e8f9f7 3158 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3159 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3160 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3161
<> 144:ef7eb2e8f9f7 3162 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
<> 144:ef7eb2e8f9f7 3163 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
<> 144:ef7eb2e8f9f7 3164 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
<> 144:ef7eb2e8f9f7 3165 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
<> 144:ef7eb2e8f9f7 3166 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
<> 144:ef7eb2e8f9f7 3167 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
<> 144:ef7eb2e8f9f7 3168 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
<> 144:ef7eb2e8f9f7 3169 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
mbed_official 25:ac5b0a371348 3170
mbed_official 25:ac5b0a371348 3171 /******************* Bit definition for TIM_SMCR register *******************/
<> 144:ef7eb2e8f9f7 3172 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
<> 144:ef7eb2e8f9f7 3173 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3174 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3175 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3176
<> 144:ef7eb2e8f9f7 3177 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
<> 144:ef7eb2e8f9f7 3178 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3179 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3180 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3181
<> 144:ef7eb2e8f9f7 3182 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
<> 144:ef7eb2e8f9f7 3183
<> 144:ef7eb2e8f9f7 3184 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
<> 144:ef7eb2e8f9f7 3185 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3186 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3187 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3188 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3189
<> 144:ef7eb2e8f9f7 3190 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 144:ef7eb2e8f9f7 3191 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3192 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3193
<> 144:ef7eb2e8f9f7 3194 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
<> 144:ef7eb2e8f9f7 3195 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
mbed_official 25:ac5b0a371348 3196
mbed_official 25:ac5b0a371348 3197 /******************* Bit definition for TIM_DIER register *******************/
<> 144:ef7eb2e8f9f7 3198 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
<> 144:ef7eb2e8f9f7 3199 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
<> 144:ef7eb2e8f9f7 3200 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
<> 144:ef7eb2e8f9f7 3201 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
<> 144:ef7eb2e8f9f7 3202 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
<> 144:ef7eb2e8f9f7 3203 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
<> 144:ef7eb2e8f9f7 3204 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
<> 144:ef7eb2e8f9f7 3205 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
<> 144:ef7eb2e8f9f7 3206 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
<> 144:ef7eb2e8f9f7 3207 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
<> 144:ef7eb2e8f9f7 3208 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
<> 144:ef7eb2e8f9f7 3209 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
<> 144:ef7eb2e8f9f7 3210 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
<> 144:ef7eb2e8f9f7 3211 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
<> 144:ef7eb2e8f9f7 3212 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
mbed_official 25:ac5b0a371348 3213
mbed_official 25:ac5b0a371348 3214 /******************** Bit definition for TIM_SR register ********************/
<> 144:ef7eb2e8f9f7 3215 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
<> 144:ef7eb2e8f9f7 3216 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
<> 144:ef7eb2e8f9f7 3217 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
<> 144:ef7eb2e8f9f7 3218 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
<> 144:ef7eb2e8f9f7 3219 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
<> 144:ef7eb2e8f9f7 3220 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
<> 144:ef7eb2e8f9f7 3221 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
<> 144:ef7eb2e8f9f7 3222 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
<> 144:ef7eb2e8f9f7 3223 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
<> 144:ef7eb2e8f9f7 3224 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
<> 144:ef7eb2e8f9f7 3225 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
<> 144:ef7eb2e8f9f7 3226 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 25:ac5b0a371348 3227
mbed_official 25:ac5b0a371348 3228 /******************* Bit definition for TIM_EGR register ********************/
<> 144:ef7eb2e8f9f7 3229 #define TIM_EGR_UG 0x01U /*!<Update Generation */
<> 144:ef7eb2e8f9f7 3230 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
<> 144:ef7eb2e8f9f7 3231 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
<> 144:ef7eb2e8f9f7 3232 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
<> 144:ef7eb2e8f9f7 3233 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
<> 144:ef7eb2e8f9f7 3234 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
<> 144:ef7eb2e8f9f7 3235 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
<> 144:ef7eb2e8f9f7 3236 #define TIM_EGR_BG 0x80U /*!<Break Generation */
mbed_official 25:ac5b0a371348 3237
mbed_official 25:ac5b0a371348 3238 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 144:ef7eb2e8f9f7 3239 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 144:ef7eb2e8f9f7 3240 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3241 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3242
<> 144:ef7eb2e8f9f7 3243 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
<> 144:ef7eb2e8f9f7 3244 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
<> 144:ef7eb2e8f9f7 3245
<> 144:ef7eb2e8f9f7 3246 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 144:ef7eb2e8f9f7 3247 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3248 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3249 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3250
<> 144:ef7eb2e8f9f7 3251 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
<> 144:ef7eb2e8f9f7 3252
<> 144:ef7eb2e8f9f7 3253 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 144:ef7eb2e8f9f7 3254 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3255 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3256
<> 144:ef7eb2e8f9f7 3257 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
<> 144:ef7eb2e8f9f7 3258 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
<> 144:ef7eb2e8f9f7 3259
<> 144:ef7eb2e8f9f7 3260 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 144:ef7eb2e8f9f7 3261 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3262 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3263 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3264
<> 144:ef7eb2e8f9f7 3265 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
mbed_official 25:ac5b0a371348 3266
mbed_official 25:ac5b0a371348 3267 /*----------------------------------------------------------------------------*/
mbed_official 25:ac5b0a371348 3268
<> 144:ef7eb2e8f9f7 3269 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 144:ef7eb2e8f9f7 3270 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3271 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3272
<> 144:ef7eb2e8f9f7 3273 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 144:ef7eb2e8f9f7 3274 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3275 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3276 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3277 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3278
<> 144:ef7eb2e8f9f7 3279 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 144:ef7eb2e8f9f7 3280 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3281 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3282
<> 144:ef7eb2e8f9f7 3283 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 144:ef7eb2e8f9f7 3284 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3285 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3286 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3287 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3288
mbed_official 25:ac5b0a371348 3289 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 144:ef7eb2e8f9f7 3290 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 144:ef7eb2e8f9f7 3291 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3292 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3293
<> 144:ef7eb2e8f9f7 3294 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
<> 144:ef7eb2e8f9f7 3295 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
<> 144:ef7eb2e8f9f7 3296
<> 144:ef7eb2e8f9f7 3297 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 144:ef7eb2e8f9f7 3298 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3299 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3300 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3301
<> 144:ef7eb2e8f9f7 3302 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
<> 144:ef7eb2e8f9f7 3303
<> 144:ef7eb2e8f9f7 3304 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 144:ef7eb2e8f9f7 3305 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3306 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3307
<> 144:ef7eb2e8f9f7 3308 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
<> 144:ef7eb2e8f9f7 3309 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
<> 144:ef7eb2e8f9f7 3310
<> 144:ef7eb2e8f9f7 3311 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 144:ef7eb2e8f9f7 3312 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3313 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3314 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3315
<> 144:ef7eb2e8f9f7 3316 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
mbed_official 25:ac5b0a371348 3317
mbed_official 25:ac5b0a371348 3318 /*----------------------------------------------------------------------------*/
mbed_official 25:ac5b0a371348 3319
<> 144:ef7eb2e8f9f7 3320 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 144:ef7eb2e8f9f7 3321 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3322 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3323
<> 144:ef7eb2e8f9f7 3324 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 144:ef7eb2e8f9f7 3325 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3326 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3327 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3328 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3329
<> 144:ef7eb2e8f9f7 3330 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 144:ef7eb2e8f9f7 3331 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3332 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3333
<> 144:ef7eb2e8f9f7 3334 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 144:ef7eb2e8f9f7 3335 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3336 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3337 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3338 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
mbed_official 25:ac5b0a371348 3339
mbed_official 25:ac5b0a371348 3340 /******************* Bit definition for TIM_CCER register *******************/
<> 144:ef7eb2e8f9f7 3341 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
<> 144:ef7eb2e8f9f7 3342 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
<> 144:ef7eb2e8f9f7 3343 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
<> 144:ef7eb2e8f9f7 3344 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 3345 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
<> 144:ef7eb2e8f9f7 3346 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
<> 144:ef7eb2e8f9f7 3347 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
<> 144:ef7eb2e8f9f7 3348 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 3349 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
<> 144:ef7eb2e8f9f7 3350 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
<> 144:ef7eb2e8f9f7 3351 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
<> 144:ef7eb2e8f9f7 3352 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 3353 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
<> 144:ef7eb2e8f9f7 3354 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
<> 144:ef7eb2e8f9f7 3355 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 25:ac5b0a371348 3356
mbed_official 25:ac5b0a371348 3357 /******************* Bit definition for TIM_CNT register ********************/
<> 144:ef7eb2e8f9f7 3358 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
mbed_official 25:ac5b0a371348 3359
mbed_official 25:ac5b0a371348 3360 /******************* Bit definition for TIM_PSC register ********************/
<> 144:ef7eb2e8f9f7 3361 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
mbed_official 25:ac5b0a371348 3362
mbed_official 25:ac5b0a371348 3363 /******************* Bit definition for TIM_ARR register ********************/
<> 144:ef7eb2e8f9f7 3364 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
mbed_official 25:ac5b0a371348 3365
mbed_official 25:ac5b0a371348 3366 /******************* Bit definition for TIM_RCR register ********************/
<> 144:ef7eb2e8f9f7 3367 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
mbed_official 25:ac5b0a371348 3368
mbed_official 25:ac5b0a371348 3369 /******************* Bit definition for TIM_CCR1 register *******************/
<> 144:ef7eb2e8f9f7 3370 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
mbed_official 25:ac5b0a371348 3371
mbed_official 25:ac5b0a371348 3372 /******************* Bit definition for TIM_CCR2 register *******************/
<> 144:ef7eb2e8f9f7 3373 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
mbed_official 25:ac5b0a371348 3374
mbed_official 25:ac5b0a371348 3375 /******************* Bit definition for TIM_CCR3 register *******************/
<> 144:ef7eb2e8f9f7 3376 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
mbed_official 25:ac5b0a371348 3377
mbed_official 25:ac5b0a371348 3378 /******************* Bit definition for TIM_CCR4 register *******************/
<> 144:ef7eb2e8f9f7 3379 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
mbed_official 25:ac5b0a371348 3380
mbed_official 25:ac5b0a371348 3381 /******************* Bit definition for TIM_BDTR register *******************/
<> 144:ef7eb2e8f9f7 3382 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 144:ef7eb2e8f9f7 3383 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3384 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3385 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3386 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3387 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3388 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3389 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3390 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3391
<> 144:ef7eb2e8f9f7 3392 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
<> 144:ef7eb2e8f9f7 3393 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3394 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3395
<> 144:ef7eb2e8f9f7 3396 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
<> 144:ef7eb2e8f9f7 3397 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
<> 144:ef7eb2e8f9f7 3398 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
<> 144:ef7eb2e8f9f7 3399 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
<> 144:ef7eb2e8f9f7 3400 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
<> 144:ef7eb2e8f9f7 3401 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
mbed_official 25:ac5b0a371348 3402
mbed_official 25:ac5b0a371348 3403 /******************* Bit definition for TIM_DCR register ********************/
<> 144:ef7eb2e8f9f7 3404 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
<> 144:ef7eb2e8f9f7 3405 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3406 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3407 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3408 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3409 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3410
<> 144:ef7eb2e8f9f7 3411 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
<> 144:ef7eb2e8f9f7 3412 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3413 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3414 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3415 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3416 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
mbed_official 25:ac5b0a371348 3417
mbed_official 25:ac5b0a371348 3418 /******************* Bit definition for TIM_DMAR register *******************/
<> 144:ef7eb2e8f9f7 3419 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
mbed_official 25:ac5b0a371348 3420
mbed_official 25:ac5b0a371348 3421 /******************* Bit definition for TIM_OR register *********************/
<> 144:ef7eb2e8f9f7 3422 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
<> 144:ef7eb2e8f9f7 3423 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3424 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
mbed_official 25:ac5b0a371348 3425
mbed_official 25:ac5b0a371348 3426 /******************************************************************************/
mbed_official 25:ac5b0a371348 3427 /* */
mbed_official 25:ac5b0a371348 3428 /* Low Power Timer (LPTIM) */
mbed_official 25:ac5b0a371348 3429 /* */
mbed_official 25:ac5b0a371348 3430 /******************************************************************************/
mbed_official 25:ac5b0a371348 3431 /****************** Bit definition for LPTIM_ISR register *******************/
<> 144:ef7eb2e8f9f7 3432 #define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
<> 144:ef7eb2e8f9f7 3433 #define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
<> 144:ef7eb2e8f9f7 3434 #define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
<> 144:ef7eb2e8f9f7 3435 #define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
<> 144:ef7eb2e8f9f7 3436 #define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
<> 144:ef7eb2e8f9f7 3437 #define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
<> 144:ef7eb2e8f9f7 3438 #define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
mbed_official 25:ac5b0a371348 3439
mbed_official 25:ac5b0a371348 3440 /****************** Bit definition for LPTIM_ICR register *******************/
<> 144:ef7eb2e8f9f7 3441 #define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
<> 144:ef7eb2e8f9f7 3442 #define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
<> 144:ef7eb2e8f9f7 3443 #define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
<> 144:ef7eb2e8f9f7 3444 #define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
<> 144:ef7eb2e8f9f7 3445 #define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
<> 144:ef7eb2e8f9f7 3446 #define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
<> 144:ef7eb2e8f9f7 3447 #define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
mbed_official 25:ac5b0a371348 3448
mbed_official 25:ac5b0a371348 3449 /****************** Bit definition for LPTIM_IER register ********************/
<> 144:ef7eb2e8f9f7 3450 #define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
<> 144:ef7eb2e8f9f7 3451 #define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
<> 144:ef7eb2e8f9f7 3452 #define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
<> 144:ef7eb2e8f9f7 3453 #define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
<> 144:ef7eb2e8f9f7 3454 #define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
<> 144:ef7eb2e8f9f7 3455 #define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
<> 144:ef7eb2e8f9f7 3456 #define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
mbed_official 25:ac5b0a371348 3457
mbed_official 25:ac5b0a371348 3458 /****************** Bit definition for LPTIM_CFGR register *******************/
<> 144:ef7eb2e8f9f7 3459 #define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
<> 144:ef7eb2e8f9f7 3460
<> 144:ef7eb2e8f9f7 3461 #define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
<> 144:ef7eb2e8f9f7 3462 #define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3463 #define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3464
<> 144:ef7eb2e8f9f7 3465 #define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
<> 144:ef7eb2e8f9f7 3466 #define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3467 #define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3468
<> 144:ef7eb2e8f9f7 3469 #define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
<> 144:ef7eb2e8f9f7 3470 #define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3471 #define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3472
<> 144:ef7eb2e8f9f7 3473 #define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
<> 144:ef7eb2e8f9f7 3474 #define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3475 #define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3476 #define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3477
<> 144:ef7eb2e8f9f7 3478 #define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
<> 144:ef7eb2e8f9f7 3479 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3480 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3481 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 3482
<> 144:ef7eb2e8f9f7 3483 #define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
<> 144:ef7eb2e8f9f7 3484 #define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3485 #define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3486
<> 144:ef7eb2e8f9f7 3487 #define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
<> 144:ef7eb2e8f9f7 3488 #define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
<> 144:ef7eb2e8f9f7 3489 #define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
<> 144:ef7eb2e8f9f7 3490 #define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
<> 144:ef7eb2e8f9f7 3491 #define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
<> 144:ef7eb2e8f9f7 3492 #define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
mbed_official 25:ac5b0a371348 3493
mbed_official 25:ac5b0a371348 3494 /****************** Bit definition for LPTIM_CR register ********************/
<> 144:ef7eb2e8f9f7 3495 #define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
<> 144:ef7eb2e8f9f7 3496 #define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
<> 144:ef7eb2e8f9f7 3497 #define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
mbed_official 25:ac5b0a371348 3498
mbed_official 25:ac5b0a371348 3499 /****************** Bit definition for LPTIM_CMP register *******************/
<> 144:ef7eb2e8f9f7 3500 #define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
mbed_official 25:ac5b0a371348 3501
mbed_official 25:ac5b0a371348 3502 /****************** Bit definition for LPTIM_ARR register *******************/
<> 144:ef7eb2e8f9f7 3503 #define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
mbed_official 25:ac5b0a371348 3504
mbed_official 25:ac5b0a371348 3505 /****************** Bit definition for LPTIM_CNT register *******************/
<> 144:ef7eb2e8f9f7 3506 #define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
mbed_official 25:ac5b0a371348 3507
mbed_official 25:ac5b0a371348 3508 /****************** Bit definition for LPTIM_OR register *******************/
<> 144:ef7eb2e8f9f7 3509 #define LPTIM_OR_OR 0x00000003U /*!< LPTIMER[1:0] bits (Remap selection) */
<> 144:ef7eb2e8f9f7 3510 #define LPTIM_OR_OR_0 0x00000001U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3511 #define LPTIM_OR_OR_1 0x00000002U /*!< Bit 1 */
mbed_official 25:ac5b0a371348 3512
mbed_official 25:ac5b0a371348 3513 /******************************************************************************/
mbed_official 25:ac5b0a371348 3514 /* */
mbed_official 25:ac5b0a371348 3515 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 25:ac5b0a371348 3516 /* */
mbed_official 25:ac5b0a371348 3517 /******************************************************************************/
mbed_official 25:ac5b0a371348 3518 /******************* Bit definition for USART_SR register *******************/
<> 144:ef7eb2e8f9f7 3519 #define USART_SR_PE 0x0001U /*!<Parity Error */
<> 144:ef7eb2e8f9f7 3520 #define USART_SR_FE 0x0002U /*!<Framing Error */
<> 144:ef7eb2e8f9f7 3521 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
<> 144:ef7eb2e8f9f7 3522 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
<> 144:ef7eb2e8f9f7 3523 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
<> 144:ef7eb2e8f9f7 3524 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
<> 144:ef7eb2e8f9f7 3525 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
<> 144:ef7eb2e8f9f7 3526 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
<> 144:ef7eb2e8f9f7 3527 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
<> 144:ef7eb2e8f9f7 3528 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
mbed_official 25:ac5b0a371348 3529
mbed_official 25:ac5b0a371348 3530 /******************* Bit definition for USART_DR register *******************/
<> 144:ef7eb2e8f9f7 3531 #define USART_DR_DR 0x01FFU /*!<Data value */
mbed_official 25:ac5b0a371348 3532
mbed_official 25:ac5b0a371348 3533 /****************** Bit definition for USART_BRR register *******************/
<> 144:ef7eb2e8f9f7 3534 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
<> 144:ef7eb2e8f9f7 3535 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
mbed_official 25:ac5b0a371348 3536
mbed_official 25:ac5b0a371348 3537 /****************** Bit definition for USART_CR1 register *******************/
<> 144:ef7eb2e8f9f7 3538 #define USART_CR1_SBK 0x0001U /*!<Send Break */
<> 144:ef7eb2e8f9f7 3539 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
<> 144:ef7eb2e8f9f7 3540 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
<> 144:ef7eb2e8f9f7 3541 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
<> 144:ef7eb2e8f9f7 3542 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3543 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3544 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 3545 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3546 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3547 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
<> 144:ef7eb2e8f9f7 3548 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
<> 144:ef7eb2e8f9f7 3549 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
<> 144:ef7eb2e8f9f7 3550 #define USART_CR1_M 0x1000U /*!<Word length */
<> 144:ef7eb2e8f9f7 3551 #define USART_CR1_UE 0x2000U /*!<USART Enable */
<> 144:ef7eb2e8f9f7 3552 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
mbed_official 25:ac5b0a371348 3553
mbed_official 25:ac5b0a371348 3554 /****************** Bit definition for USART_CR2 register *******************/
<> 144:ef7eb2e8f9f7 3555 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
<> 144:ef7eb2e8f9f7 3556 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
<> 144:ef7eb2e8f9f7 3557 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
<> 144:ef7eb2e8f9f7 3558 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
<> 144:ef7eb2e8f9f7 3559 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
<> 144:ef7eb2e8f9f7 3560 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
<> 144:ef7eb2e8f9f7 3561 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
<> 144:ef7eb2e8f9f7 3562
<> 144:ef7eb2e8f9f7 3563 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
<> 144:ef7eb2e8f9f7 3564 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3565 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3566
<> 144:ef7eb2e8f9f7 3567 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
mbed_official 25:ac5b0a371348 3568
mbed_official 25:ac5b0a371348 3569 /****************** Bit definition for USART_CR3 register *******************/
<> 144:ef7eb2e8f9f7 3570 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3571 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
<> 144:ef7eb2e8f9f7 3572 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
<> 144:ef7eb2e8f9f7 3573 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
<> 144:ef7eb2e8f9f7 3574 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
<> 144:ef7eb2e8f9f7 3575 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
<> 144:ef7eb2e8f9f7 3576 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
<> 144:ef7eb2e8f9f7 3577 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
<> 144:ef7eb2e8f9f7 3578 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
<> 144:ef7eb2e8f9f7 3579 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
<> 144:ef7eb2e8f9f7 3580 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
<> 144:ef7eb2e8f9f7 3581 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
mbed_official 25:ac5b0a371348 3582
mbed_official 25:ac5b0a371348 3583 /****************** Bit definition for USART_GTPR register ******************/
<> 144:ef7eb2e8f9f7 3584 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
<> 144:ef7eb2e8f9f7 3585 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3586 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3587 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3588 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3589 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3590 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3591 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3592 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3593
<> 144:ef7eb2e8f9f7 3594 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
mbed_official 25:ac5b0a371348 3595
mbed_official 25:ac5b0a371348 3596 /******************************************************************************/
mbed_official 25:ac5b0a371348 3597 /* */
mbed_official 25:ac5b0a371348 3598 /* Window WATCHDOG */
mbed_official 25:ac5b0a371348 3599 /* */
mbed_official 25:ac5b0a371348 3600 /******************************************************************************/
mbed_official 25:ac5b0a371348 3601 /******************* Bit definition for WWDG_CR register ********************/
<> 144:ef7eb2e8f9f7 3602 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 144:ef7eb2e8f9f7 3603 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3604 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3605 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3606 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3607 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3608 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3609 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3610 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3611 #define WWDG_CR_T0 WWDG_CR_T_0
<> 144:ef7eb2e8f9f7 3612 #define WWDG_CR_T1 WWDG_CR_T_1
<> 144:ef7eb2e8f9f7 3613 #define WWDG_CR_T2 WWDG_CR_T_2
<> 144:ef7eb2e8f9f7 3614 #define WWDG_CR_T3 WWDG_CR_T_3
<> 144:ef7eb2e8f9f7 3615 #define WWDG_CR_T4 WWDG_CR_T_4
<> 144:ef7eb2e8f9f7 3616 #define WWDG_CR_T5 WWDG_CR_T_5
<> 144:ef7eb2e8f9f7 3617 #define WWDG_CR_T6 WWDG_CR_T_6
<> 144:ef7eb2e8f9f7 3618
<> 144:ef7eb2e8f9f7 3619 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
mbed_official 25:ac5b0a371348 3620
mbed_official 25:ac5b0a371348 3621 /******************* Bit definition for WWDG_CFR register *******************/
<> 144:ef7eb2e8f9f7 3622 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
<> 144:ef7eb2e8f9f7 3623 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3624 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3625 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3626 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3627 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3628 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3629 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3630 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3631 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 144:ef7eb2e8f9f7 3632 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 144:ef7eb2e8f9f7 3633 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 144:ef7eb2e8f9f7 3634 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 144:ef7eb2e8f9f7 3635 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 144:ef7eb2e8f9f7 3636 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 144:ef7eb2e8f9f7 3637 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 144:ef7eb2e8f9f7 3638
<> 144:ef7eb2e8f9f7 3639 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
<> 144:ef7eb2e8f9f7 3640 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3641 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3642 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3643 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 144:ef7eb2e8f9f7 3644 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 144:ef7eb2e8f9f7 3645
<> 144:ef7eb2e8f9f7 3646 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
mbed_official 25:ac5b0a371348 3647
mbed_official 25:ac5b0a371348 3648 /******************* Bit definition for WWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 3649 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
mbed_official 25:ac5b0a371348 3650
mbed_official 25:ac5b0a371348 3651 /******************************************************************************/
mbed_official 25:ac5b0a371348 3652 /* */
mbed_official 25:ac5b0a371348 3653 /* Digital to Analog Converter */
mbed_official 25:ac5b0a371348 3654 /* */
mbed_official 25:ac5b0a371348 3655 /******************************************************************************/
mbed_official 25:ac5b0a371348 3656 /******************** Bit definition for DAC_CR register ********************/
<> 144:ef7eb2e8f9f7 3657 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
<> 144:ef7eb2e8f9f7 3658 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
<> 144:ef7eb2e8f9f7 3659 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
<> 144:ef7eb2e8f9f7 3660
<> 144:ef7eb2e8f9f7 3661 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 144:ef7eb2e8f9f7 3662 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3663 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3664 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3665
<> 144:ef7eb2e8f9f7 3666 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 3667 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3668 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3669
<> 144:ef7eb2e8f9f7 3670 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 3671 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3672 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3673 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3674 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3675
<> 144:ef7eb2e8f9f7 3676 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
<> 144:ef7eb2e8f9f7 3677 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
<> 144:ef7eb2e8f9f7 3678 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
<> 144:ef7eb2e8f9f7 3679 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
<> 144:ef7eb2e8f9f7 3680 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
<> 144:ef7eb2e8f9f7 3681
<> 144:ef7eb2e8f9f7 3682 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 144:ef7eb2e8f9f7 3683 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3684 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3685 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3686
<> 144:ef7eb2e8f9f7 3687 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 3688 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3689 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3690
<> 144:ef7eb2e8f9f7 3691 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 3692 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3693 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3694 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3695 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3696
<> 144:ef7eb2e8f9f7 3697 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
<> 144:ef7eb2e8f9f7 3698 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
mbed_official 25:ac5b0a371348 3699
mbed_official 25:ac5b0a371348 3700 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 144:ef7eb2e8f9f7 3701 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
<> 144:ef7eb2e8f9f7 3702 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
mbed_official 25:ac5b0a371348 3703
mbed_official 25:ac5b0a371348 3704 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 144:ef7eb2e8f9f7 3705 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
mbed_official 25:ac5b0a371348 3706
mbed_official 25:ac5b0a371348 3707 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 144:ef7eb2e8f9f7 3708 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
mbed_official 25:ac5b0a371348 3709
mbed_official 25:ac5b0a371348 3710 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 144:ef7eb2e8f9f7 3711 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
mbed_official 25:ac5b0a371348 3712
mbed_official 25:ac5b0a371348 3713 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 144:ef7eb2e8f9f7 3714 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
mbed_official 25:ac5b0a371348 3715
mbed_official 25:ac5b0a371348 3716 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 144:ef7eb2e8f9f7 3717 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
mbed_official 25:ac5b0a371348 3718
mbed_official 25:ac5b0a371348 3719 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 144:ef7eb2e8f9f7 3720 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
mbed_official 25:ac5b0a371348 3721
mbed_official 25:ac5b0a371348 3722 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 144:ef7eb2e8f9f7 3723 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 3724 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
mbed_official 25:ac5b0a371348 3725
mbed_official 25:ac5b0a371348 3726 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 144:ef7eb2e8f9f7 3727 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 3728 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
mbed_official 25:ac5b0a371348 3729
mbed_official 25:ac5b0a371348 3730 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 144:ef7eb2e8f9f7 3731 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 3732 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
mbed_official 25:ac5b0a371348 3733
mbed_official 25:ac5b0a371348 3734 /******************* Bit definition for DAC_DOR1 register *******************/
<> 144:ef7eb2e8f9f7 3735 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
mbed_official 25:ac5b0a371348 3736
mbed_official 25:ac5b0a371348 3737 /******************* Bit definition for DAC_DOR2 register *******************/
<> 144:ef7eb2e8f9f7 3738 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
mbed_official 25:ac5b0a371348 3739
mbed_official 25:ac5b0a371348 3740 /******************** Bit definition for DAC_SR register ********************/
<> 144:ef7eb2e8f9f7 3741 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
<> 144:ef7eb2e8f9f7 3742 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
mbed_official 25:ac5b0a371348 3743 /******************************************************************************/
mbed_official 25:ac5b0a371348 3744 /* */
mbed_official 25:ac5b0a371348 3745 /* DBG */
mbed_official 25:ac5b0a371348 3746 /* */
mbed_official 25:ac5b0a371348 3747 /******************************************************************************/
mbed_official 25:ac5b0a371348 3748 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 144:ef7eb2e8f9f7 3749 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
<> 144:ef7eb2e8f9f7 3750 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
mbed_official 25:ac5b0a371348 3751
mbed_official 25:ac5b0a371348 3752 /******************** Bit definition for DBGMCU_CR register *****************/
<> 144:ef7eb2e8f9f7 3753 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
<> 144:ef7eb2e8f9f7 3754 #define DBGMCU_CR_DBG_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 3755 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
<> 144:ef7eb2e8f9f7 3756 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
<> 144:ef7eb2e8f9f7 3757
<> 144:ef7eb2e8f9f7 3758 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
<> 144:ef7eb2e8f9f7 3759 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3760 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
mbed_official 25:ac5b0a371348 3761
mbed_official 25:ac5b0a371348 3762 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 144:ef7eb2e8f9f7 3763 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
<> 144:ef7eb2e8f9f7 3764 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
<> 144:ef7eb2e8f9f7 3765 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
<> 144:ef7eb2e8f9f7 3766 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
<> 144:ef7eb2e8f9f7 3767 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
<> 144:ef7eb2e8f9f7 3768 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
<> 144:ef7eb2e8f9f7 3769 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
<> 144:ef7eb2e8f9f7 3770 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
<> 144:ef7eb2e8f9f7 3771 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
mbed_official 25:ac5b0a371348 3772
mbed_official 25:ac5b0a371348 3773 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 144:ef7eb2e8f9f7 3774 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
<> 144:ef7eb2e8f9f7 3775 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
<> 144:ef7eb2e8f9f7 3776 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
mbed_official 25:ac5b0a371348 3777
mbed_official 25:ac5b0a371348 3778 /**
mbed_official 25:ac5b0a371348 3779 * @}
mbed_official 25:ac5b0a371348 3780 */
mbed_official 25:ac5b0a371348 3781
mbed_official 25:ac5b0a371348 3782 /**
mbed_official 25:ac5b0a371348 3783 * @}
mbed_official 25:ac5b0a371348 3784 */
mbed_official 25:ac5b0a371348 3785
mbed_official 25:ac5b0a371348 3786 /** @addtogroup Exported_macros
mbed_official 25:ac5b0a371348 3787 * @{
mbed_official 25:ac5b0a371348 3788 */
mbed_official 25:ac5b0a371348 3789
mbed_official 25:ac5b0a371348 3790 /******************************* ADC Instances ********************************/
mbed_official 25:ac5b0a371348 3791 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 25:ac5b0a371348 3792
mbed_official 25:ac5b0a371348 3793 /******************************* CRC Instances ********************************/
mbed_official 25:ac5b0a371348 3794 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 25:ac5b0a371348 3795
mbed_official 25:ac5b0a371348 3796 /******************************* DAC Instances ********************************/
mbed_official 25:ac5b0a371348 3797 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 25:ac5b0a371348 3798
mbed_official 25:ac5b0a371348 3799 /******************************** DMA Instances *******************************/
mbed_official 25:ac5b0a371348 3800 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
mbed_official 25:ac5b0a371348 3801 ((INSTANCE) == DMA1_Stream1) || \
mbed_official 25:ac5b0a371348 3802 ((INSTANCE) == DMA1_Stream2) || \
mbed_official 25:ac5b0a371348 3803 ((INSTANCE) == DMA1_Stream3) || \
mbed_official 25:ac5b0a371348 3804 ((INSTANCE) == DMA1_Stream4) || \
mbed_official 25:ac5b0a371348 3805 ((INSTANCE) == DMA1_Stream5) || \
mbed_official 25:ac5b0a371348 3806 ((INSTANCE) == DMA1_Stream6) || \
mbed_official 25:ac5b0a371348 3807 ((INSTANCE) == DMA1_Stream7) || \
mbed_official 25:ac5b0a371348 3808 ((INSTANCE) == DMA2_Stream0) || \
mbed_official 25:ac5b0a371348 3809 ((INSTANCE) == DMA2_Stream1) || \
mbed_official 25:ac5b0a371348 3810 ((INSTANCE) == DMA2_Stream2) || \
mbed_official 25:ac5b0a371348 3811 ((INSTANCE) == DMA2_Stream3) || \
mbed_official 25:ac5b0a371348 3812 ((INSTANCE) == DMA2_Stream4) || \
mbed_official 25:ac5b0a371348 3813 ((INSTANCE) == DMA2_Stream5) || \
mbed_official 25:ac5b0a371348 3814 ((INSTANCE) == DMA2_Stream6) || \
mbed_official 25:ac5b0a371348 3815 ((INSTANCE) == DMA2_Stream7))
mbed_official 25:ac5b0a371348 3816
mbed_official 25:ac5b0a371348 3817 /******************************* GPIO Instances *******************************/
mbed_official 25:ac5b0a371348 3818 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 25:ac5b0a371348 3819 ((INSTANCE) == GPIOB) || \
mbed_official 25:ac5b0a371348 3820 ((INSTANCE) == GPIOC) || \
mbed_official 25:ac5b0a371348 3821 ((INSTANCE) == GPIOH))
mbed_official 25:ac5b0a371348 3822
mbed_official 25:ac5b0a371348 3823 /******************************** I2C Instances *******************************/
mbed_official 25:ac5b0a371348 3824 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 25:ac5b0a371348 3825 ((INSTANCE) == I2C2))
mbed_official 25:ac5b0a371348 3826 /******************************** I2S Instances *******************************/
mbed_official 25:ac5b0a371348 3827 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 25:ac5b0a371348 3828 ((INSTANCE) == SPI2) || \
mbed_official 25:ac5b0a371348 3829 ((INSTANCE) == SPI5))
mbed_official 25:ac5b0a371348 3830
mbed_official 25:ac5b0a371348 3831 /******************************* LPTIM Instances ******************************/
mbed_official 25:ac5b0a371348 3832 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
mbed_official 25:ac5b0a371348 3833
mbed_official 25:ac5b0a371348 3834 /******************************* RNG Instances ********************************/
mbed_official 25:ac5b0a371348 3835 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
mbed_official 25:ac5b0a371348 3836
mbed_official 25:ac5b0a371348 3837 /****************************** RTC Instances *********************************/
mbed_official 25:ac5b0a371348 3838 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 25:ac5b0a371348 3839
mbed_official 25:ac5b0a371348 3840 /******************************** SPI Instances *******************************/
mbed_official 25:ac5b0a371348 3841 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 25:ac5b0a371348 3842 ((INSTANCE) == SPI2) || \
mbed_official 25:ac5b0a371348 3843 ((INSTANCE) == SPI5))
mbed_official 25:ac5b0a371348 3844 /*************************** SPI Extended Instances ***************************/
mbed_official 25:ac5b0a371348 3845 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 25:ac5b0a371348 3846 ((INSTANCE) == SPI2) || \
mbed_official 25:ac5b0a371348 3847 ((INSTANCE) == SPI5))
mbed_official 25:ac5b0a371348 3848
mbed_official 25:ac5b0a371348 3849 /****************** TIM Instances : All supported instances *******************/
mbed_official 25:ac5b0a371348 3850 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3851 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3852 ((INSTANCE) == TIM6) || \
mbed_official 25:ac5b0a371348 3853 ((INSTANCE) == TIM9) || \
mbed_official 25:ac5b0a371348 3854 ((INSTANCE) == TIM11))
mbed_official 25:ac5b0a371348 3855
mbed_official 25:ac5b0a371348 3856 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 25:ac5b0a371348 3857 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3858 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3859 ((INSTANCE) == TIM9) || \
mbed_official 25:ac5b0a371348 3860 ((INSTANCE) == TIM11))
mbed_official 25:ac5b0a371348 3861
mbed_official 25:ac5b0a371348 3862 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 25:ac5b0a371348 3863 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3864 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3865 ((INSTANCE) == TIM9))
mbed_official 25:ac5b0a371348 3866
mbed_official 25:ac5b0a371348 3867 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 25:ac5b0a371348 3868 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3869 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3870
mbed_official 25:ac5b0a371348 3871 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 25:ac5b0a371348 3872 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3873 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3874
mbed_official 25:ac5b0a371348 3875 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 25:ac5b0a371348 3876 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
mbed_official 25:ac5b0a371348 3877
mbed_official 25:ac5b0a371348 3878 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 25:ac5b0a371348 3879 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3880 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3881
mbed_official 25:ac5b0a371348 3882 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 25:ac5b0a371348 3883 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3884 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3885 ((INSTANCE) == TIM6))
mbed_official 25:ac5b0a371348 3886
mbed_official 25:ac5b0a371348 3887 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 25:ac5b0a371348 3888 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3889 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3890
mbed_official 25:ac5b0a371348 3891 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 25:ac5b0a371348 3892 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3893 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3894
mbed_official 25:ac5b0a371348 3895 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 25:ac5b0a371348 3896 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3897 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3898
mbed_official 25:ac5b0a371348 3899 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 25:ac5b0a371348 3900 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3901 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3902 ((INSTANCE) == TIM6) || \
mbed_official 25:ac5b0a371348 3903 ((INSTANCE) == TIM9))
mbed_official 25:ac5b0a371348 3904
mbed_official 25:ac5b0a371348 3905 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 25:ac5b0a371348 3906 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3907 ((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3908 ((INSTANCE) == TIM9))
mbed_official 25:ac5b0a371348 3909
mbed_official 25:ac5b0a371348 3910 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 25:ac5b0a371348 3911 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3912
mbed_official 25:ac5b0a371348 3913 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 25:ac5b0a371348 3914 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 25:ac5b0a371348 3915 ((INSTANCE) == TIM5))
mbed_official 25:ac5b0a371348 3916
mbed_official 25:ac5b0a371348 3917 /****************** TIM Instances : remapping capability **********************/
mbed_official 25:ac5b0a371348 3918 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
mbed_official 25:ac5b0a371348 3919 ((INSTANCE) == TIM11))
mbed_official 25:ac5b0a371348 3920
mbed_official 25:ac5b0a371348 3921 /******************* TIM Instances : output(s) available **********************/
mbed_official 25:ac5b0a371348 3922 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 25:ac5b0a371348 3923 ((((INSTANCE) == TIM1) && \
mbed_official 25:ac5b0a371348 3924 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3925 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 25:ac5b0a371348 3926 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 25:ac5b0a371348 3927 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 25:ac5b0a371348 3928 || \
mbed_official 25:ac5b0a371348 3929 (((INSTANCE) == TIM5) && \
mbed_official 25:ac5b0a371348 3930 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3931 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 25:ac5b0a371348 3932 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 25:ac5b0a371348 3933 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 25:ac5b0a371348 3934 || \
mbed_official 25:ac5b0a371348 3935 (((INSTANCE) == TIM9) && \
mbed_official 25:ac5b0a371348 3936 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3937 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 25:ac5b0a371348 3938 || \
mbed_official 25:ac5b0a371348 3939 (((INSTANCE) == TIM11) && \
mbed_official 25:ac5b0a371348 3940 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 25:ac5b0a371348 3941
mbed_official 25:ac5b0a371348 3942 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 25:ac5b0a371348 3943 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 25:ac5b0a371348 3944 ((((INSTANCE) == TIM1) && \
mbed_official 25:ac5b0a371348 3945 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 25:ac5b0a371348 3946 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 25:ac5b0a371348 3947 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 25:ac5b0a371348 3948
mbed_official 25:ac5b0a371348 3949 /******************** USART Instances : Synchronous mode **********************/
mbed_official 25:ac5b0a371348 3950 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3951 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3952 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3953
mbed_official 25:ac5b0a371348 3954 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 25:ac5b0a371348 3955 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3956 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3957 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3958
mbed_official 25:ac5b0a371348 3959 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 25:ac5b0a371348 3960 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3961 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3962 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3963
mbed_official 25:ac5b0a371348 3964 /********************* UART Instances : Smard card mode ***********************/
mbed_official 25:ac5b0a371348 3965 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3966 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3967 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3968
mbed_official 25:ac5b0a371348 3969 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 25:ac5b0a371348 3970 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 25:ac5b0a371348 3971 ((INSTANCE) == USART2) || \
mbed_official 25:ac5b0a371348 3972 ((INSTANCE) == USART6))
mbed_official 25:ac5b0a371348 3973
mbed_official 25:ac5b0a371348 3974 /****************************** IWDG Instances ********************************/
mbed_official 25:ac5b0a371348 3975 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 25:ac5b0a371348 3976
mbed_official 25:ac5b0a371348 3977 /****************************** WWDG Instances ********************************/
mbed_official 25:ac5b0a371348 3978 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 25:ac5b0a371348 3979
mbed_official 25:ac5b0a371348 3980 /***************************** FMPI2C Instances *******************************/
mbed_official 25:ac5b0a371348 3981 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
mbed_official 25:ac5b0a371348 3982
mbed_official 25:ac5b0a371348 3983 /**
mbed_official 25:ac5b0a371348 3984 * @}
mbed_official 25:ac5b0a371348 3985 */
mbed_official 25:ac5b0a371348 3986
mbed_official 25:ac5b0a371348 3987 /**
mbed_official 25:ac5b0a371348 3988 * @}
mbed_official 25:ac5b0a371348 3989 */
mbed_official 25:ac5b0a371348 3990
mbed_official 25:ac5b0a371348 3991 /**
mbed_official 25:ac5b0a371348 3992 * @}
mbed_official 25:ac5b0a371348 3993 */
mbed_official 25:ac5b0a371348 3994
mbed_official 25:ac5b0a371348 3995 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 3996 }
mbed_official 25:ac5b0a371348 3997 #endif /* __cplusplus */
mbed_official 25:ac5b0a371348 3998
<> 144:ef7eb2e8f9f7 3999 #endif /* __STM32F410Rx_H */
mbed_official 25:ac5b0a371348 4000
mbed_official 25:ac5b0a371348 4001
mbed_official 25:ac5b0a371348 4002
mbed_official 25:ac5b0a371348 4003 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/