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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_flexio_spi.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_flexio_spi.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 /*******************************************************************************
<> 154:37f96f9d4de2 34 * Definitions
<> 154:37f96f9d4de2 35 ******************************************************************************/
<> 154:37f96f9d4de2 36
<> 154:37f96f9d4de2 37 /*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
<> 154:37f96f9d4de2 38 enum _flexio_spi_transfer_states
<> 154:37f96f9d4de2 39 {
<> 154:37f96f9d4de2 40 kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */
<> 154:37f96f9d4de2 41 kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */
<> 154:37f96f9d4de2 42 };
<> 154:37f96f9d4de2 43
<> 154:37f96f9d4de2 44 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 45 extern const clock_ip_name_t s_flexioClocks[];
<> 154:37f96f9d4de2 46 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 extern FLEXIO_Type *const s_flexioBases[];
<> 154:37f96f9d4de2 49
<> 154:37f96f9d4de2 50 /*******************************************************************************
<> 154:37f96f9d4de2 51 * Prototypes
<> 154:37f96f9d4de2 52 ******************************************************************************/
<> 154:37f96f9d4de2 53
<> 154:37f96f9d4de2 54 /*!
<> 154:37f96f9d4de2 55 * @brief Send a piece of data for SPI.
<> 154:37f96f9d4de2 56 *
<> 154:37f96f9d4de2 57 * This function computes the number of data to be written into D register or Tx FIFO,
<> 154:37f96f9d4de2 58 * and write the data into it. At the same time, this function updates the values in
<> 154:37f96f9d4de2 59 * master handle structure.
<> 154:37f96f9d4de2 60 *
<> 154:37f96f9d4de2 61 * @param base pointer to FLEXIO_SPI_Type structure
<> 154:37f96f9d4de2 62 * @param handle Pointer to SPI master handle structure.
<> 154:37f96f9d4de2 63 */
<> 154:37f96f9d4de2 64 static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
<> 154:37f96f9d4de2 65
<> 154:37f96f9d4de2 66 /*!
<> 154:37f96f9d4de2 67 * @brief Receive a piece of data for SPI master.
<> 154:37f96f9d4de2 68 *
<> 154:37f96f9d4de2 69 * This function computes the number of data to receive from D register or Rx FIFO,
<> 154:37f96f9d4de2 70 * and write the data to destination address. At the same time, this function updates
<> 154:37f96f9d4de2 71 * the values in master handle structure.
<> 154:37f96f9d4de2 72 *
<> 154:37f96f9d4de2 73 * @param base pointer to FLEXIO_SPI_Type structure
<> 154:37f96f9d4de2 74 * @param handle Pointer to SPI master handle structure.
<> 154:37f96f9d4de2 75 */
<> 154:37f96f9d4de2 76 static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
<> 154:37f96f9d4de2 77
<> 154:37f96f9d4de2 78 /*******************************************************************************
<> 154:37f96f9d4de2 79 * Variables
<> 154:37f96f9d4de2 80 ******************************************************************************/
<> 154:37f96f9d4de2 81
<> 154:37f96f9d4de2 82 /*******************************************************************************
<> 154:37f96f9d4de2 83 * Codes
<> 154:37f96f9d4de2 84 ******************************************************************************/
<> 154:37f96f9d4de2 85
<> 154:37f96f9d4de2 86 uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base)
<> 154:37f96f9d4de2 87 {
<> 154:37f96f9d4de2 88 uint32_t instance;
<> 154:37f96f9d4de2 89 FLEXIO_Type *flexioBase = base->flexioBase;
<> 154:37f96f9d4de2 90
<> 154:37f96f9d4de2 91 /* Find the instance index from base address mappings. */
<> 154:37f96f9d4de2 92 for (instance = 0; instance < FSL_FEATURE_SOC_FLEXIO_COUNT; instance++)
<> 154:37f96f9d4de2 93 {
<> 154:37f96f9d4de2 94 if (s_flexioBases[instance] == flexioBase)
<> 154:37f96f9d4de2 95 {
<> 154:37f96f9d4de2 96 break;
<> 154:37f96f9d4de2 97 }
<> 154:37f96f9d4de2 98 }
<> 154:37f96f9d4de2 99
<> 154:37f96f9d4de2 100 assert(instance < FSL_FEATURE_SOC_FLEXIO_COUNT);
<> 154:37f96f9d4de2 101
<> 154:37f96f9d4de2 102 return instance;
<> 154:37f96f9d4de2 103 }
<> 154:37f96f9d4de2 104
<> 154:37f96f9d4de2 105 static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
<> 154:37f96f9d4de2 106 {
<> 154:37f96f9d4de2 107 uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
<> 154:37f96f9d4de2 108
<> 154:37f96f9d4de2 109 if (handle->txData != NULL)
<> 154:37f96f9d4de2 110 {
<> 154:37f96f9d4de2 111 /* Transmit data and update tx size/buff. */
<> 154:37f96f9d4de2 112 if (handle->bytePerFrame == 1U)
<> 154:37f96f9d4de2 113 {
<> 154:37f96f9d4de2 114 tmpData = *(handle->txData);
<> 154:37f96f9d4de2 115 handle->txData++;
<> 154:37f96f9d4de2 116 }
<> 154:37f96f9d4de2 117 else
<> 154:37f96f9d4de2 118 {
<> 154:37f96f9d4de2 119 if (handle->direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 120 {
<> 154:37f96f9d4de2 121 tmpData = (uint32_t)(handle->txData[0]) << 8U;
<> 154:37f96f9d4de2 122 tmpData += handle->txData[1];
<> 154:37f96f9d4de2 123 }
<> 154:37f96f9d4de2 124 else
<> 154:37f96f9d4de2 125 {
<> 154:37f96f9d4de2 126 tmpData = (uint32_t)(handle->txData[1]) << 8U;
<> 154:37f96f9d4de2 127 tmpData += handle->txData[0];
<> 154:37f96f9d4de2 128 }
<> 154:37f96f9d4de2 129 handle->txData += 2U;
<> 154:37f96f9d4de2 130 }
<> 154:37f96f9d4de2 131 }
<> 154:37f96f9d4de2 132 else
<> 154:37f96f9d4de2 133 {
<> 154:37f96f9d4de2 134 tmpData = FLEXIO_SPI_DUMMYDATA;
<> 154:37f96f9d4de2 135 }
<> 154:37f96f9d4de2 136
<> 154:37f96f9d4de2 137 handle->txRemainingBytes -= handle->bytePerFrame;
<> 154:37f96f9d4de2 138
<> 154:37f96f9d4de2 139 FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
<> 154:37f96f9d4de2 140
<> 154:37f96f9d4de2 141 if (!handle->txRemainingBytes)
<> 154:37f96f9d4de2 142 {
<> 154:37f96f9d4de2 143 FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
<> 154:37f96f9d4de2 144 }
<> 154:37f96f9d4de2 145 }
<> 154:37f96f9d4de2 146
<> 154:37f96f9d4de2 147 static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
<> 154:37f96f9d4de2 148 {
<> 154:37f96f9d4de2 149 uint16_t tmpData;
<> 154:37f96f9d4de2 150
<> 154:37f96f9d4de2 151 tmpData = FLEXIO_SPI_ReadData(base, handle->direction);
<> 154:37f96f9d4de2 152
<> 154:37f96f9d4de2 153 if (handle->rxData != NULL)
<> 154:37f96f9d4de2 154 {
<> 154:37f96f9d4de2 155 if (handle->bytePerFrame == 1U)
<> 154:37f96f9d4de2 156 {
<> 154:37f96f9d4de2 157 *handle->rxData = tmpData;
<> 154:37f96f9d4de2 158 handle->rxData++;
<> 154:37f96f9d4de2 159 }
<> 154:37f96f9d4de2 160 else
<> 154:37f96f9d4de2 161 {
<> 154:37f96f9d4de2 162 if (handle->direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 163 {
<> 154:37f96f9d4de2 164 *((uint16_t *)(handle->rxData)) = tmpData;
<> 154:37f96f9d4de2 165 }
<> 154:37f96f9d4de2 166 else
<> 154:37f96f9d4de2 167 {
<> 154:37f96f9d4de2 168 *((uint16_t *)(handle->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU));
<> 154:37f96f9d4de2 169 }
<> 154:37f96f9d4de2 170 handle->rxData += 2U;
<> 154:37f96f9d4de2 171 }
<> 154:37f96f9d4de2 172 }
<> 154:37f96f9d4de2 173 handle->rxRemainingBytes -= handle->bytePerFrame;
<> 154:37f96f9d4de2 174 }
<> 154:37f96f9d4de2 175
<> 154:37f96f9d4de2 176 void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
<> 154:37f96f9d4de2 177 {
<> 154:37f96f9d4de2 178 assert(base);
<> 154:37f96f9d4de2 179 assert(masterConfig);
<> 154:37f96f9d4de2 180
<> 154:37f96f9d4de2 181 flexio_shifter_config_t shifterConfig;
<> 154:37f96f9d4de2 182 flexio_timer_config_t timerConfig;
<> 154:37f96f9d4de2 183 uint32_t ctrlReg = 0;
<> 154:37f96f9d4de2 184 uint16_t timerDiv = 0;
<> 154:37f96f9d4de2 185 uint16_t timerCmp = 0;
<> 154:37f96f9d4de2 186
<> 154:37f96f9d4de2 187 /* Clear the shifterConfig & timerConfig struct. */
<> 154:37f96f9d4de2 188 memset(&shifterConfig, 0, sizeof(shifterConfig));
<> 154:37f96f9d4de2 189 memset(&timerConfig, 0, sizeof(timerConfig));
<> 154:37f96f9d4de2 190
<> 154:37f96f9d4de2 191 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 192 /* Ungate flexio clock. */
<> 154:37f96f9d4de2 193 CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]);
<> 154:37f96f9d4de2 194 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 /* Configure FLEXIO SPI Master */
<> 154:37f96f9d4de2 197 ctrlReg = base->flexioBase->CTRL;
<> 154:37f96f9d4de2 198 ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
<> 154:37f96f9d4de2 199 ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
<> 154:37f96f9d4de2 200 FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
<> 154:37f96f9d4de2 201 if (!masterConfig->enableInDoze)
<> 154:37f96f9d4de2 202 {
<> 154:37f96f9d4de2 203 ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
<> 154:37f96f9d4de2 204 }
<> 154:37f96f9d4de2 205
<> 154:37f96f9d4de2 206 base->flexioBase->CTRL = ctrlReg;
<> 154:37f96f9d4de2 207
<> 154:37f96f9d4de2 208 /* Do hardware configuration. */
<> 154:37f96f9d4de2 209 /* 1. Configure the shifter 0 for tx. */
<> 154:37f96f9d4de2 210 shifterConfig.timerSelect = base->timerIndex[0];
<> 154:37f96f9d4de2 211 shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
<> 154:37f96f9d4de2 212 shifterConfig.pinSelect = base->SDOPinIndex;
<> 154:37f96f9d4de2 213 shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 154:37f96f9d4de2 214 shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
<> 154:37f96f9d4de2 215 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
<> 154:37f96f9d4de2 216 if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
<> 154:37f96f9d4de2 217 {
<> 154:37f96f9d4de2 218 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
<> 154:37f96f9d4de2 219 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
<> 154:37f96f9d4de2 220 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
<> 154:37f96f9d4de2 221 }
<> 154:37f96f9d4de2 222 else
<> 154:37f96f9d4de2 223 {
<> 154:37f96f9d4de2 224 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
<> 154:37f96f9d4de2 225 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
<> 154:37f96f9d4de2 226 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
<> 154:37f96f9d4de2 227 }
<> 154:37f96f9d4de2 228
<> 154:37f96f9d4de2 229 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
<> 154:37f96f9d4de2 230
<> 154:37f96f9d4de2 231 /* 2. Configure the shifter 1 for rx. */
<> 154:37f96f9d4de2 232 shifterConfig.timerSelect = base->timerIndex[0];
<> 154:37f96f9d4de2 233 shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
<> 154:37f96f9d4de2 234 shifterConfig.pinSelect = base->SDIPinIndex;
<> 154:37f96f9d4de2 235 shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 154:37f96f9d4de2 236 shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
<> 154:37f96f9d4de2 237 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
<> 154:37f96f9d4de2 238 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
<> 154:37f96f9d4de2 239 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
<> 154:37f96f9d4de2 240 if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
<> 154:37f96f9d4de2 241 {
<> 154:37f96f9d4de2 242 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
<> 154:37f96f9d4de2 243 }
<> 154:37f96f9d4de2 244 else
<> 154:37f96f9d4de2 245 {
<> 154:37f96f9d4de2 246 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
<> 154:37f96f9d4de2 247 }
<> 154:37f96f9d4de2 248
<> 154:37f96f9d4de2 249 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
<> 154:37f96f9d4de2 250
<> 154:37f96f9d4de2 251 /*3. Configure the timer 0 for SCK. */
<> 154:37f96f9d4de2 252 timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
<> 154:37f96f9d4de2 253 timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
<> 154:37f96f9d4de2 254 timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
<> 154:37f96f9d4de2 255 timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
<> 154:37f96f9d4de2 256 timerConfig.pinSelect = base->SCKPinIndex;
<> 154:37f96f9d4de2 257 timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 154:37f96f9d4de2 258 timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
<> 154:37f96f9d4de2 259 timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
<> 154:37f96f9d4de2 260 timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
<> 154:37f96f9d4de2 261 timerConfig.timerReset = kFLEXIO_TimerResetNever;
<> 154:37f96f9d4de2 262 timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
<> 154:37f96f9d4de2 263 timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
<> 154:37f96f9d4de2 264 timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
<> 154:37f96f9d4de2 265 timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
<> 154:37f96f9d4de2 266
<> 154:37f96f9d4de2 267 timerDiv = srcClock_Hz / masterConfig->baudRate_Bps;
<> 154:37f96f9d4de2 268 timerDiv = timerDiv / 2 - 1;
<> 154:37f96f9d4de2 269
<> 154:37f96f9d4de2 270 timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U;
<> 154:37f96f9d4de2 271 timerCmp |= timerDiv;
<> 154:37f96f9d4de2 272
<> 154:37f96f9d4de2 273 timerConfig.timerCompare = timerCmp;
<> 154:37f96f9d4de2 274
<> 154:37f96f9d4de2 275 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
<> 154:37f96f9d4de2 276
<> 154:37f96f9d4de2 277 /* 4. Configure the timer 1 for CSn. */
<> 154:37f96f9d4de2 278 timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
<> 154:37f96f9d4de2 279 timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
<> 154:37f96f9d4de2 280 timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
<> 154:37f96f9d4de2 281 timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
<> 154:37f96f9d4de2 282 timerConfig.pinSelect = base->CSnPinIndex;
<> 154:37f96f9d4de2 283 timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
<> 154:37f96f9d4de2 284 timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
<> 154:37f96f9d4de2 285 timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
<> 154:37f96f9d4de2 286 timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
<> 154:37f96f9d4de2 287 timerConfig.timerReset = kFLEXIO_TimerResetNever;
<> 154:37f96f9d4de2 288 timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
<> 154:37f96f9d4de2 289 timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
<> 154:37f96f9d4de2 290 timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
<> 154:37f96f9d4de2 291 timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
<> 154:37f96f9d4de2 292
<> 154:37f96f9d4de2 293 timerConfig.timerCompare = 0xFFFFU;
<> 154:37f96f9d4de2 294
<> 154:37f96f9d4de2 295 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
<> 154:37f96f9d4de2 296 }
<> 154:37f96f9d4de2 297
<> 154:37f96f9d4de2 298 void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
<> 154:37f96f9d4de2 299 {
<> 154:37f96f9d4de2 300 /* Disable FLEXIO SPI module. */
<> 154:37f96f9d4de2 301 FLEXIO_SPI_Enable(base, false);
<> 154:37f96f9d4de2 302
<> 154:37f96f9d4de2 303 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 304 /* Gate flexio clock. */
<> 154:37f96f9d4de2 305 CLOCK_DisableClock(kCLOCK_Flexio0);
<> 154:37f96f9d4de2 306 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 307 }
<> 154:37f96f9d4de2 308
<> 154:37f96f9d4de2 309 void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
<> 154:37f96f9d4de2 310 {
<> 154:37f96f9d4de2 311 assert(masterConfig);
<> 154:37f96f9d4de2 312
<> 154:37f96f9d4de2 313 masterConfig->enableMaster = true;
<> 154:37f96f9d4de2 314 masterConfig->enableInDoze = false;
<> 154:37f96f9d4de2 315 masterConfig->enableInDebug = true;
<> 154:37f96f9d4de2 316 masterConfig->enableFastAccess = false;
<> 154:37f96f9d4de2 317 /* Default baud rate 500kbps. */
<> 154:37f96f9d4de2 318 masterConfig->baudRate_Bps = 500000U;
<> 154:37f96f9d4de2 319 /* Default CPHA = 0. */
<> 154:37f96f9d4de2 320 masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
<> 154:37f96f9d4de2 321 /* Default bit count at 8. */
<> 154:37f96f9d4de2 322 masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
<> 154:37f96f9d4de2 323 }
<> 154:37f96f9d4de2 324
<> 154:37f96f9d4de2 325 void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
<> 154:37f96f9d4de2 326 {
<> 154:37f96f9d4de2 327 assert(base && slaveConfig);
<> 154:37f96f9d4de2 328
<> 154:37f96f9d4de2 329 flexio_shifter_config_t shifterConfig;
<> 154:37f96f9d4de2 330 flexio_timer_config_t timerConfig;
<> 154:37f96f9d4de2 331 uint32_t ctrlReg = 0;
<> 154:37f96f9d4de2 332
<> 154:37f96f9d4de2 333 /* Clear the shifterConfig & timerConfig struct. */
<> 154:37f96f9d4de2 334 memset(&shifterConfig, 0, sizeof(shifterConfig));
<> 154:37f96f9d4de2 335 memset(&timerConfig, 0, sizeof(timerConfig));
<> 154:37f96f9d4de2 336
<> 154:37f96f9d4de2 337 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 338 /* Ungate flexio clock. */
<> 154:37f96f9d4de2 339 CLOCK_EnableClock(kCLOCK_Flexio0);
<> 154:37f96f9d4de2 340 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 341
<> 154:37f96f9d4de2 342 /* Configure FLEXIO SPI Slave */
<> 154:37f96f9d4de2 343 ctrlReg = base->flexioBase->CTRL;
<> 154:37f96f9d4de2 344 ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
<> 154:37f96f9d4de2 345 ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) |
<> 154:37f96f9d4de2 346 FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave));
<> 154:37f96f9d4de2 347 if (!slaveConfig->enableInDoze)
<> 154:37f96f9d4de2 348 {
<> 154:37f96f9d4de2 349 ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
<> 154:37f96f9d4de2 350 }
<> 154:37f96f9d4de2 351
<> 154:37f96f9d4de2 352 base->flexioBase->CTRL = ctrlReg;
<> 154:37f96f9d4de2 353
<> 154:37f96f9d4de2 354 /* Do hardware configuration. */
<> 154:37f96f9d4de2 355 /* 1. Configure the shifter 0 for tx. */
<> 154:37f96f9d4de2 356 shifterConfig.timerSelect = base->timerIndex[0];
<> 154:37f96f9d4de2 357 shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
<> 154:37f96f9d4de2 358 shifterConfig.pinSelect = base->SDOPinIndex;
<> 154:37f96f9d4de2 359 shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 154:37f96f9d4de2 360 shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
<> 154:37f96f9d4de2 361 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
<> 154:37f96f9d4de2 362 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
<> 154:37f96f9d4de2 363 if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
<> 154:37f96f9d4de2 364 {
<> 154:37f96f9d4de2 365 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
<> 154:37f96f9d4de2 366 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
<> 154:37f96f9d4de2 367 }
<> 154:37f96f9d4de2 368 else
<> 154:37f96f9d4de2 369 {
<> 154:37f96f9d4de2 370 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
<> 154:37f96f9d4de2 371 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
<> 154:37f96f9d4de2 372 }
<> 154:37f96f9d4de2 373
<> 154:37f96f9d4de2 374 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
<> 154:37f96f9d4de2 375
<> 154:37f96f9d4de2 376 /* 2. Configure the shifter 1 for rx. */
<> 154:37f96f9d4de2 377 shifterConfig.timerSelect = base->timerIndex[0];
<> 154:37f96f9d4de2 378 shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
<> 154:37f96f9d4de2 379 shifterConfig.pinSelect = base->SDIPinIndex;
<> 154:37f96f9d4de2 380 shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 154:37f96f9d4de2 381 shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
<> 154:37f96f9d4de2 382 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
<> 154:37f96f9d4de2 383 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
<> 154:37f96f9d4de2 384 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
<> 154:37f96f9d4de2 385 if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
<> 154:37f96f9d4de2 386 {
<> 154:37f96f9d4de2 387 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
<> 154:37f96f9d4de2 388 }
<> 154:37f96f9d4de2 389 else
<> 154:37f96f9d4de2 390 {
<> 154:37f96f9d4de2 391 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
<> 154:37f96f9d4de2 392 }
<> 154:37f96f9d4de2 393
<> 154:37f96f9d4de2 394 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
<> 154:37f96f9d4de2 395
<> 154:37f96f9d4de2 396 /*3. Configure the timer 0 for shift clock. */
<> 154:37f96f9d4de2 397 timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
<> 154:37f96f9d4de2 398 timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
<> 154:37f96f9d4de2 399 timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
<> 154:37f96f9d4de2 400 timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
<> 154:37f96f9d4de2 401 timerConfig.pinSelect = base->SCKPinIndex;
<> 154:37f96f9d4de2 402 timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
<> 154:37f96f9d4de2 403 timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
<> 154:37f96f9d4de2 404 timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
<> 154:37f96f9d4de2 405 timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
<> 154:37f96f9d4de2 406 timerConfig.timerReset = kFLEXIO_TimerResetNever;
<> 154:37f96f9d4de2 407 timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
<> 154:37f96f9d4de2 408 timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
<> 154:37f96f9d4de2 409 if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
<> 154:37f96f9d4de2 410 {
<> 154:37f96f9d4de2 411 /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous
<> 154:37f96f9d4de2 412 PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */
<> 154:37f96f9d4de2 413 timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
<> 154:37f96f9d4de2 414 timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
<> 154:37f96f9d4de2 415 }
<> 154:37f96f9d4de2 416 else
<> 154:37f96f9d4de2 417 {
<> 154:37f96f9d4de2 418 timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
<> 154:37f96f9d4de2 419 timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
<> 154:37f96f9d4de2 420 }
<> 154:37f96f9d4de2 421
<> 154:37f96f9d4de2 422 timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U;
<> 154:37f96f9d4de2 423
<> 154:37f96f9d4de2 424 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
<> 154:37f96f9d4de2 425 }
<> 154:37f96f9d4de2 426
<> 154:37f96f9d4de2 427 void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
<> 154:37f96f9d4de2 428 {
<> 154:37f96f9d4de2 429 FLEXIO_SPI_MasterDeinit(base);
<> 154:37f96f9d4de2 430 }
<> 154:37f96f9d4de2 431
<> 154:37f96f9d4de2 432 void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
<> 154:37f96f9d4de2 433 {
<> 154:37f96f9d4de2 434 assert(slaveConfig);
<> 154:37f96f9d4de2 435
<> 154:37f96f9d4de2 436 slaveConfig->enableSlave = true;
<> 154:37f96f9d4de2 437 slaveConfig->enableInDoze = false;
<> 154:37f96f9d4de2 438 slaveConfig->enableInDebug = true;
<> 154:37f96f9d4de2 439 slaveConfig->enableFastAccess = false;
<> 154:37f96f9d4de2 440 /* Default CPHA = 0. */
<> 154:37f96f9d4de2 441 slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
<> 154:37f96f9d4de2 442 /* Default bit count at 8. */
<> 154:37f96f9d4de2 443 slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
<> 154:37f96f9d4de2 444 }
<> 154:37f96f9d4de2 445
<> 154:37f96f9d4de2 446 void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 447 {
<> 154:37f96f9d4de2 448 if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
<> 154:37f96f9d4de2 449 {
<> 154:37f96f9d4de2 450 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]);
<> 154:37f96f9d4de2 451 }
<> 154:37f96f9d4de2 452 if (mask & kFLEXIO_SPI_RxFullInterruptEnable)
<> 154:37f96f9d4de2 453 {
<> 154:37f96f9d4de2 454 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]);
<> 154:37f96f9d4de2 455 }
<> 154:37f96f9d4de2 456 }
<> 154:37f96f9d4de2 457
<> 154:37f96f9d4de2 458 void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 459 {
<> 154:37f96f9d4de2 460 if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
<> 154:37f96f9d4de2 461 {
<> 154:37f96f9d4de2 462 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]);
<> 154:37f96f9d4de2 463 }
<> 154:37f96f9d4de2 464 if (mask & kFLEXIO_SPI_RxFullInterruptEnable)
<> 154:37f96f9d4de2 465 {
<> 154:37f96f9d4de2 466 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]);
<> 154:37f96f9d4de2 467 }
<> 154:37f96f9d4de2 468 }
<> 154:37f96f9d4de2 469
<> 154:37f96f9d4de2 470 void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
<> 154:37f96f9d4de2 471 {
<> 154:37f96f9d4de2 472 if (mask & kFLEXIO_SPI_TxDmaEnable)
<> 154:37f96f9d4de2 473 {
<> 154:37f96f9d4de2 474 FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable);
<> 154:37f96f9d4de2 475 }
<> 154:37f96f9d4de2 476
<> 154:37f96f9d4de2 477 if (mask & kFLEXIO_SPI_RxDmaEnable)
<> 154:37f96f9d4de2 478 {
<> 154:37f96f9d4de2 479 FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable);
<> 154:37f96f9d4de2 480 }
<> 154:37f96f9d4de2 481 }
<> 154:37f96f9d4de2 482
<> 154:37f96f9d4de2 483 uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
<> 154:37f96f9d4de2 484 {
<> 154:37f96f9d4de2 485 uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
<> 154:37f96f9d4de2 486 uint32_t status = 0;
<> 154:37f96f9d4de2 487
<> 154:37f96f9d4de2 488 status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
<> 154:37f96f9d4de2 489 status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U);
<> 154:37f96f9d4de2 490
<> 154:37f96f9d4de2 491 return status;
<> 154:37f96f9d4de2 492 }
<> 154:37f96f9d4de2 493
<> 154:37f96f9d4de2 494 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 495 {
<> 154:37f96f9d4de2 496 if (mask & kFLEXIO_SPI_TxBufferEmptyFlag)
<> 154:37f96f9d4de2 497 {
<> 154:37f96f9d4de2 498 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
<> 154:37f96f9d4de2 499 }
<> 154:37f96f9d4de2 500 if (mask & kFLEXIO_SPI_RxBufferFullFlag)
<> 154:37f96f9d4de2 501 {
<> 154:37f96f9d4de2 502 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
<> 154:37f96f9d4de2 503 }
<> 154:37f96f9d4de2 504 }
<> 154:37f96f9d4de2 505
<> 154:37f96f9d4de2 506 void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
<> 154:37f96f9d4de2 507 {
<> 154:37f96f9d4de2 508 uint16_t timerDiv = 0;
<> 154:37f96f9d4de2 509 uint16_t timerCmp = 0;
<> 154:37f96f9d4de2 510 FLEXIO_Type *flexioBase = base->flexioBase;
<> 154:37f96f9d4de2 511
<> 154:37f96f9d4de2 512 /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
<> 154:37f96f9d4de2 513 timerDiv = srcClockHz / baudRate_Bps;
<> 154:37f96f9d4de2 514 timerDiv = timerDiv / 2 - 1U;
<> 154:37f96f9d4de2 515
<> 154:37f96f9d4de2 516 timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
<> 154:37f96f9d4de2 517 timerCmp &= 0xFF00U;
<> 154:37f96f9d4de2 518 timerCmp |= timerDiv;
<> 154:37f96f9d4de2 519
<> 154:37f96f9d4de2 520 flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
<> 154:37f96f9d4de2 521 }
<> 154:37f96f9d4de2 522
<> 154:37f96f9d4de2 523 void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 524 flexio_spi_shift_direction_t direction,
<> 154:37f96f9d4de2 525 const uint8_t *buffer,
<> 154:37f96f9d4de2 526 size_t size)
<> 154:37f96f9d4de2 527 {
<> 154:37f96f9d4de2 528 assert(buffer);
<> 154:37f96f9d4de2 529 assert(size);
<> 154:37f96f9d4de2 530
<> 154:37f96f9d4de2 531 while (size--)
<> 154:37f96f9d4de2 532 {
<> 154:37f96f9d4de2 533 /* Wait until data transfer complete. */
<> 154:37f96f9d4de2 534 while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag))
<> 154:37f96f9d4de2 535 {
<> 154:37f96f9d4de2 536 }
<> 154:37f96f9d4de2 537 FLEXIO_SPI_WriteData(base, direction, *buffer++);
<> 154:37f96f9d4de2 538 }
<> 154:37f96f9d4de2 539 }
<> 154:37f96f9d4de2 540
<> 154:37f96f9d4de2 541 void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 542 flexio_spi_shift_direction_t direction,
<> 154:37f96f9d4de2 543 uint8_t *buffer,
<> 154:37f96f9d4de2 544 size_t size)
<> 154:37f96f9d4de2 545 {
<> 154:37f96f9d4de2 546 assert(buffer);
<> 154:37f96f9d4de2 547 assert(size);
<> 154:37f96f9d4de2 548
<> 154:37f96f9d4de2 549 while (size--)
<> 154:37f96f9d4de2 550 {
<> 154:37f96f9d4de2 551 /* Wait until data transfer complete. */
<> 154:37f96f9d4de2 552 while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag))
<> 154:37f96f9d4de2 553 {
<> 154:37f96f9d4de2 554 }
<> 154:37f96f9d4de2 555 *buffer++ = FLEXIO_SPI_ReadData(base, direction);
<> 154:37f96f9d4de2 556 }
<> 154:37f96f9d4de2 557 }
<> 154:37f96f9d4de2 558
<> 154:37f96f9d4de2 559 void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
<> 154:37f96f9d4de2 560 {
<> 154:37f96f9d4de2 561 flexio_spi_shift_direction_t direction;
<> 154:37f96f9d4de2 562 uint8_t bytesPerFrame;
<> 154:37f96f9d4de2 563 uint32_t dataMode = 0;
<> 154:37f96f9d4de2 564 uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
<> 154:37f96f9d4de2 565 uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
<> 154:37f96f9d4de2 566
<> 154:37f96f9d4de2 567 timerCmp &= 0x00FFU;
<> 154:37f96f9d4de2 568 /* Configure the values in handle. */
<> 154:37f96f9d4de2 569 switch (xfer->flags)
<> 154:37f96f9d4de2 570 {
<> 154:37f96f9d4de2 571 case kFLEXIO_SPI_8bitMsb:
<> 154:37f96f9d4de2 572 dataMode = (8 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 573 bytesPerFrame = 1;
<> 154:37f96f9d4de2 574 direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 575 break;
<> 154:37f96f9d4de2 576
<> 154:37f96f9d4de2 577 case kFLEXIO_SPI_8bitLsb:
<> 154:37f96f9d4de2 578 dataMode = (8 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 579 bytesPerFrame = 1;
<> 154:37f96f9d4de2 580 direction = kFLEXIO_SPI_LsbFirst;
<> 154:37f96f9d4de2 581 break;
<> 154:37f96f9d4de2 582
<> 154:37f96f9d4de2 583 case kFLEXIO_SPI_16bitMsb:
<> 154:37f96f9d4de2 584 dataMode = (16 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 585 bytesPerFrame = 2;
<> 154:37f96f9d4de2 586 direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 587 break;
<> 154:37f96f9d4de2 588
<> 154:37f96f9d4de2 589 case kFLEXIO_SPI_16bitLsb:
<> 154:37f96f9d4de2 590 dataMode = (16 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 591 bytesPerFrame = 2;
<> 154:37f96f9d4de2 592 direction = kFLEXIO_SPI_LsbFirst;
<> 154:37f96f9d4de2 593 break;
<> 154:37f96f9d4de2 594
<> 154:37f96f9d4de2 595 default:
<> 154:37f96f9d4de2 596 dataMode = (8 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 597 bytesPerFrame = 1;
<> 154:37f96f9d4de2 598 direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 599 assert(true);
<> 154:37f96f9d4de2 600 break;
<> 154:37f96f9d4de2 601 }
<> 154:37f96f9d4de2 602
<> 154:37f96f9d4de2 603 dataMode |= timerCmp;
<> 154:37f96f9d4de2 604
<> 154:37f96f9d4de2 605 /* Configure transfer size. */
<> 154:37f96f9d4de2 606 base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
<> 154:37f96f9d4de2 607
<> 154:37f96f9d4de2 608 while (xfer->dataSize)
<> 154:37f96f9d4de2 609 {
<> 154:37f96f9d4de2 610 /* Wait until data transfer complete. */
<> 154:37f96f9d4de2 611 while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag))
<> 154:37f96f9d4de2 612 {
<> 154:37f96f9d4de2 613 }
<> 154:37f96f9d4de2 614 if (xfer->txData != NULL)
<> 154:37f96f9d4de2 615 {
<> 154:37f96f9d4de2 616 /* Transmit data and update tx size/buff. */
<> 154:37f96f9d4de2 617 if (bytesPerFrame == 1U)
<> 154:37f96f9d4de2 618 {
<> 154:37f96f9d4de2 619 tmpData = *(xfer->txData);
<> 154:37f96f9d4de2 620 xfer->txData++;
<> 154:37f96f9d4de2 621 }
<> 154:37f96f9d4de2 622 else
<> 154:37f96f9d4de2 623 {
<> 154:37f96f9d4de2 624 if (direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 625 {
<> 154:37f96f9d4de2 626 tmpData = (uint32_t)(xfer->txData[0]) << 8U;
<> 154:37f96f9d4de2 627 tmpData += xfer->txData[1];
<> 154:37f96f9d4de2 628 }
<> 154:37f96f9d4de2 629 else
<> 154:37f96f9d4de2 630 {
<> 154:37f96f9d4de2 631 tmpData = (uint32_t)(xfer->txData[1]) << 8U;
<> 154:37f96f9d4de2 632 tmpData += xfer->txData[0];
<> 154:37f96f9d4de2 633 }
<> 154:37f96f9d4de2 634 xfer->txData += 2U;
<> 154:37f96f9d4de2 635 }
<> 154:37f96f9d4de2 636 }
<> 154:37f96f9d4de2 637 else
<> 154:37f96f9d4de2 638 {
<> 154:37f96f9d4de2 639 tmpData = FLEXIO_SPI_DUMMYDATA;
<> 154:37f96f9d4de2 640 }
<> 154:37f96f9d4de2 641
<> 154:37f96f9d4de2 642 xfer->dataSize -= bytesPerFrame;
<> 154:37f96f9d4de2 643
<> 154:37f96f9d4de2 644 FLEXIO_SPI_WriteData(base, direction, tmpData);
<> 154:37f96f9d4de2 645
<> 154:37f96f9d4de2 646 while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag))
<> 154:37f96f9d4de2 647 {
<> 154:37f96f9d4de2 648 }
<> 154:37f96f9d4de2 649 tmpData = FLEXIO_SPI_ReadData(base, direction);
<> 154:37f96f9d4de2 650
<> 154:37f96f9d4de2 651 if (xfer->rxData != NULL)
<> 154:37f96f9d4de2 652 {
<> 154:37f96f9d4de2 653 if (bytesPerFrame == 1U)
<> 154:37f96f9d4de2 654 {
<> 154:37f96f9d4de2 655 *xfer->rxData = tmpData;
<> 154:37f96f9d4de2 656 xfer->rxData++;
<> 154:37f96f9d4de2 657 }
<> 154:37f96f9d4de2 658 else
<> 154:37f96f9d4de2 659 {
<> 154:37f96f9d4de2 660 if (direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 661 {
<> 154:37f96f9d4de2 662 *((uint16_t *)(xfer->rxData)) = tmpData;
<> 154:37f96f9d4de2 663 }
<> 154:37f96f9d4de2 664 else
<> 154:37f96f9d4de2 665 {
<> 154:37f96f9d4de2 666 *((uint16_t *)(xfer->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU));
<> 154:37f96f9d4de2 667 }
<> 154:37f96f9d4de2 668 xfer->rxData += 2U;
<> 154:37f96f9d4de2 669 }
<> 154:37f96f9d4de2 670 }
<> 154:37f96f9d4de2 671 }
<> 154:37f96f9d4de2 672 }
<> 154:37f96f9d4de2 673
<> 154:37f96f9d4de2 674 status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 675 flexio_spi_master_handle_t *handle,
<> 154:37f96f9d4de2 676 flexio_spi_master_transfer_callback_t callback,
<> 154:37f96f9d4de2 677 void *userData)
<> 154:37f96f9d4de2 678 {
<> 154:37f96f9d4de2 679 assert(handle);
<> 154:37f96f9d4de2 680
<> 154:37f96f9d4de2 681 IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
<> 154:37f96f9d4de2 682
<> 154:37f96f9d4de2 683 /* Zero the handle. */
<> 154:37f96f9d4de2 684 memset(handle, 0, sizeof(*handle));
<> 154:37f96f9d4de2 685
<> 154:37f96f9d4de2 686 /* Register callback and userData. */
<> 154:37f96f9d4de2 687 handle->callback = callback;
<> 154:37f96f9d4de2 688 handle->userData = userData;
<> 154:37f96f9d4de2 689
<> 154:37f96f9d4de2 690 /* Enable interrupt in NVIC. */
<> 154:37f96f9d4de2 691 EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
<> 154:37f96f9d4de2 692
<> 154:37f96f9d4de2 693 /* Save the context in global variables to support the double weak mechanism. */
<> 154:37f96f9d4de2 694 return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
<> 154:37f96f9d4de2 695 }
<> 154:37f96f9d4de2 696
<> 154:37f96f9d4de2 697 status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 698 flexio_spi_master_handle_t *handle,
<> 154:37f96f9d4de2 699 flexio_spi_transfer_t *xfer)
<> 154:37f96f9d4de2 700 {
<> 154:37f96f9d4de2 701 assert(handle);
<> 154:37f96f9d4de2 702 assert(xfer);
<> 154:37f96f9d4de2 703
<> 154:37f96f9d4de2 704 uint32_t dataMode = 0;
<> 154:37f96f9d4de2 705 uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
<> 154:37f96f9d4de2 706 uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
<> 154:37f96f9d4de2 707
<> 154:37f96f9d4de2 708 timerCmp &= 0x00FFU;
<> 154:37f96f9d4de2 709
<> 154:37f96f9d4de2 710 /* Check if SPI is busy. */
<> 154:37f96f9d4de2 711 if (handle->state == kFLEXIO_SPI_Busy)
<> 154:37f96f9d4de2 712 {
<> 154:37f96f9d4de2 713 return kStatus_FLEXIO_SPI_Busy;
<> 154:37f96f9d4de2 714 }
<> 154:37f96f9d4de2 715
<> 154:37f96f9d4de2 716 /* Check if the argument is legal. */
<> 154:37f96f9d4de2 717 if ((xfer->txData == NULL) && (xfer->rxData == NULL))
<> 154:37f96f9d4de2 718 {
<> 154:37f96f9d4de2 719 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 720 }
<> 154:37f96f9d4de2 721
<> 154:37f96f9d4de2 722 /* Configure the values in handle */
<> 154:37f96f9d4de2 723 switch (xfer->flags)
<> 154:37f96f9d4de2 724 {
<> 154:37f96f9d4de2 725 case kFLEXIO_SPI_8bitMsb:
<> 154:37f96f9d4de2 726 dataMode = (8 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 727 handle->bytePerFrame = 1U;
<> 154:37f96f9d4de2 728 handle->direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 729 break;
<> 154:37f96f9d4de2 730 case kFLEXIO_SPI_8bitLsb:
<> 154:37f96f9d4de2 731 dataMode = (8 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 732 handle->bytePerFrame = 1U;
<> 154:37f96f9d4de2 733 handle->direction = kFLEXIO_SPI_LsbFirst;
<> 154:37f96f9d4de2 734 break;
<> 154:37f96f9d4de2 735 case kFLEXIO_SPI_16bitMsb:
<> 154:37f96f9d4de2 736 dataMode = (16 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 737 handle->bytePerFrame = 2U;
<> 154:37f96f9d4de2 738 handle->direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 739 break;
<> 154:37f96f9d4de2 740 case kFLEXIO_SPI_16bitLsb:
<> 154:37f96f9d4de2 741 dataMode = (16 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 742 handle->bytePerFrame = 2U;
<> 154:37f96f9d4de2 743 handle->direction = kFLEXIO_SPI_LsbFirst;
<> 154:37f96f9d4de2 744 break;
<> 154:37f96f9d4de2 745 default:
<> 154:37f96f9d4de2 746 dataMode = (8 * 2 - 1U) << 8U;
<> 154:37f96f9d4de2 747 handle->bytePerFrame = 1U;
<> 154:37f96f9d4de2 748 handle->direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 749 assert(true);
<> 154:37f96f9d4de2 750 break;
<> 154:37f96f9d4de2 751 }
<> 154:37f96f9d4de2 752
<> 154:37f96f9d4de2 753 dataMode |= timerCmp;
<> 154:37f96f9d4de2 754
<> 154:37f96f9d4de2 755 /* Configure transfer size. */
<> 154:37f96f9d4de2 756 base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
<> 154:37f96f9d4de2 757
<> 154:37f96f9d4de2 758 handle->state = kFLEXIO_SPI_Busy;
<> 154:37f96f9d4de2 759 handle->txData = xfer->txData;
<> 154:37f96f9d4de2 760 handle->rxData = xfer->rxData;
<> 154:37f96f9d4de2 761 handle->rxRemainingBytes = xfer->dataSize;
<> 154:37f96f9d4de2 762
<> 154:37f96f9d4de2 763 /* Save total transfer size. */
<> 154:37f96f9d4de2 764 handle->transferSize = xfer->dataSize;
<> 154:37f96f9d4de2 765
<> 154:37f96f9d4de2 766 /* Send first byte of data to trigger the rx interrupt. */
<> 154:37f96f9d4de2 767 if (handle->txData != NULL)
<> 154:37f96f9d4de2 768 {
<> 154:37f96f9d4de2 769 /* Transmit data and update tx size/buff. */
<> 154:37f96f9d4de2 770 if (handle->bytePerFrame == 1U)
<> 154:37f96f9d4de2 771 {
<> 154:37f96f9d4de2 772 tmpData = *(handle->txData);
<> 154:37f96f9d4de2 773 handle->txData++;
<> 154:37f96f9d4de2 774 }
<> 154:37f96f9d4de2 775 else
<> 154:37f96f9d4de2 776 {
<> 154:37f96f9d4de2 777 if (handle->direction == kFLEXIO_SPI_MsbFirst)
<> 154:37f96f9d4de2 778 {
<> 154:37f96f9d4de2 779 tmpData = (uint32_t)(handle->txData[0]) << 8U;
<> 154:37f96f9d4de2 780 tmpData += handle->txData[1];
<> 154:37f96f9d4de2 781 }
<> 154:37f96f9d4de2 782 else
<> 154:37f96f9d4de2 783 {
<> 154:37f96f9d4de2 784 tmpData = (uint32_t)(handle->txData[1]) << 8U;
<> 154:37f96f9d4de2 785 tmpData += handle->txData[0];
<> 154:37f96f9d4de2 786 }
<> 154:37f96f9d4de2 787 handle->txData += 2U;
<> 154:37f96f9d4de2 788 }
<> 154:37f96f9d4de2 789 }
<> 154:37f96f9d4de2 790 else
<> 154:37f96f9d4de2 791 {
<> 154:37f96f9d4de2 792 tmpData = FLEXIO_SPI_DUMMYDATA;
<> 154:37f96f9d4de2 793 }
<> 154:37f96f9d4de2 794
<> 154:37f96f9d4de2 795 handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame;
<> 154:37f96f9d4de2 796
<> 154:37f96f9d4de2 797 FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
<> 154:37f96f9d4de2 798
<> 154:37f96f9d4de2 799 /* Enable transmit and receive interrupt to handle rx. */
<> 154:37f96f9d4de2 800 FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
<> 154:37f96f9d4de2 801
<> 154:37f96f9d4de2 802 return kStatus_Success;
<> 154:37f96f9d4de2 803 }
<> 154:37f96f9d4de2 804
<> 154:37f96f9d4de2 805 status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
<> 154:37f96f9d4de2 806 {
<> 154:37f96f9d4de2 807 assert(handle);
<> 154:37f96f9d4de2 808
<> 154:37f96f9d4de2 809 if (!count)
<> 154:37f96f9d4de2 810 {
<> 154:37f96f9d4de2 811 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 812 }
<> 154:37f96f9d4de2 813
<> 154:37f96f9d4de2 814 /* Return remaing bytes in different cases. */
<> 154:37f96f9d4de2 815 if (handle->rxData)
<> 154:37f96f9d4de2 816 {
<> 154:37f96f9d4de2 817 *count = handle->transferSize - handle->rxRemainingBytes;
<> 154:37f96f9d4de2 818 }
<> 154:37f96f9d4de2 819 else
<> 154:37f96f9d4de2 820 {
<> 154:37f96f9d4de2 821 *count = handle->transferSize - handle->txRemainingBytes;
<> 154:37f96f9d4de2 822 }
<> 154:37f96f9d4de2 823
<> 154:37f96f9d4de2 824 return kStatus_Success;
<> 154:37f96f9d4de2 825 }
<> 154:37f96f9d4de2 826
<> 154:37f96f9d4de2 827 void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
<> 154:37f96f9d4de2 828 {
<> 154:37f96f9d4de2 829 assert(handle);
<> 154:37f96f9d4de2 830
<> 154:37f96f9d4de2 831 FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
<> 154:37f96f9d4de2 832 FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
<> 154:37f96f9d4de2 833
<> 154:37f96f9d4de2 834 /* Transfer finished, set the state to idle. */
<> 154:37f96f9d4de2 835 handle->state = kFLEXIO_SPI_Idle;
<> 154:37f96f9d4de2 836
<> 154:37f96f9d4de2 837 /* Clear the internal state. */
<> 154:37f96f9d4de2 838 handle->rxRemainingBytes = 0;
<> 154:37f96f9d4de2 839 handle->txRemainingBytes = 0;
<> 154:37f96f9d4de2 840 }
<> 154:37f96f9d4de2 841
<> 154:37f96f9d4de2 842 void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
<> 154:37f96f9d4de2 843 {
<> 154:37f96f9d4de2 844 assert(spiHandle);
<> 154:37f96f9d4de2 845
<> 154:37f96f9d4de2 846 flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
<> 154:37f96f9d4de2 847 FLEXIO_SPI_Type *base;
<> 154:37f96f9d4de2 848 uint32_t status;
<> 154:37f96f9d4de2 849
<> 154:37f96f9d4de2 850 if (handle->state == kFLEXIO_SPI_Idle)
<> 154:37f96f9d4de2 851 {
<> 154:37f96f9d4de2 852 return;
<> 154:37f96f9d4de2 853 }
<> 154:37f96f9d4de2 854
<> 154:37f96f9d4de2 855 base = (FLEXIO_SPI_Type *)spiType;
<> 154:37f96f9d4de2 856 status = FLEXIO_SPI_GetStatusFlags(base);
<> 154:37f96f9d4de2 857
<> 154:37f96f9d4de2 858 /* Handle rx. */
<> 154:37f96f9d4de2 859 if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes))
<> 154:37f96f9d4de2 860 {
<> 154:37f96f9d4de2 861 FLEXIO_SPI_TransferReceiveTransaction(base, handle);
<> 154:37f96f9d4de2 862 }
<> 154:37f96f9d4de2 863
<> 154:37f96f9d4de2 864 /* Handle tx. */
<> 154:37f96f9d4de2 865 if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes))
<> 154:37f96f9d4de2 866 {
<> 154:37f96f9d4de2 867 FLEXIO_SPI_TransferSendTransaction(base, handle);
<> 154:37f96f9d4de2 868 }
<> 154:37f96f9d4de2 869
<> 154:37f96f9d4de2 870 /* All the transfer finished. */
<> 154:37f96f9d4de2 871 if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
<> 154:37f96f9d4de2 872 {
<> 154:37f96f9d4de2 873 FLEXIO_SPI_MasterTransferAbort(base, handle);
<> 154:37f96f9d4de2 874 if (handle->callback)
<> 154:37f96f9d4de2 875 {
<> 154:37f96f9d4de2 876 (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
<> 154:37f96f9d4de2 877 }
<> 154:37f96f9d4de2 878 }
<> 154:37f96f9d4de2 879 }
<> 154:37f96f9d4de2 880
<> 154:37f96f9d4de2 881 status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 882 flexio_spi_slave_handle_t *handle,
<> 154:37f96f9d4de2 883 flexio_spi_slave_transfer_callback_t callback,
<> 154:37f96f9d4de2 884 void *userData)
<> 154:37f96f9d4de2 885 {
<> 154:37f96f9d4de2 886 assert(handle);
<> 154:37f96f9d4de2 887
<> 154:37f96f9d4de2 888 IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
<> 154:37f96f9d4de2 889
<> 154:37f96f9d4de2 890 /* Zero the handle. */
<> 154:37f96f9d4de2 891 memset(handle, 0, sizeof(*handle));
<> 154:37f96f9d4de2 892
<> 154:37f96f9d4de2 893 /* Register callback and userData. */
<> 154:37f96f9d4de2 894 handle->callback = callback;
<> 154:37f96f9d4de2 895 handle->userData = userData;
<> 154:37f96f9d4de2 896
<> 154:37f96f9d4de2 897 /* Enable interrupt in NVIC. */
<> 154:37f96f9d4de2 898 EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
<> 154:37f96f9d4de2 899
<> 154:37f96f9d4de2 900 /* Save the context in global variables to support the double weak mechanism. */
<> 154:37f96f9d4de2 901 return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
<> 154:37f96f9d4de2 902 }
<> 154:37f96f9d4de2 903
<> 154:37f96f9d4de2 904 status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
<> 154:37f96f9d4de2 905 flexio_spi_slave_handle_t *handle,
<> 154:37f96f9d4de2 906 flexio_spi_transfer_t *xfer)
<> 154:37f96f9d4de2 907 {
<> 154:37f96f9d4de2 908 assert(handle);
<> 154:37f96f9d4de2 909 assert(xfer);
<> 154:37f96f9d4de2 910
<> 154:37f96f9d4de2 911 uint32_t dataMode = 0;
<> 154:37f96f9d4de2 912
<> 154:37f96f9d4de2 913 /* Check if SPI is busy. */
<> 154:37f96f9d4de2 914 if (handle->state == kFLEXIO_SPI_Busy)
<> 154:37f96f9d4de2 915 {
<> 154:37f96f9d4de2 916 return kStatus_FLEXIO_SPI_Busy;
<> 154:37f96f9d4de2 917 }
<> 154:37f96f9d4de2 918
<> 154:37f96f9d4de2 919 /* Check if the argument is legal. */
<> 154:37f96f9d4de2 920 if ((xfer->txData == NULL) && (xfer->rxData == NULL))
<> 154:37f96f9d4de2 921 {
<> 154:37f96f9d4de2 922 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 923 }
<> 154:37f96f9d4de2 924
<> 154:37f96f9d4de2 925 /* Configure the values in handle */
<> 154:37f96f9d4de2 926 switch (xfer->flags)
<> 154:37f96f9d4de2 927 {
<> 154:37f96f9d4de2 928 case kFLEXIO_SPI_8bitMsb:
<> 154:37f96f9d4de2 929 dataMode = 8 * 2 - 1U;
<> 154:37f96f9d4de2 930 handle->bytePerFrame = 1U;
<> 154:37f96f9d4de2 931 handle->direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 932 break;
<> 154:37f96f9d4de2 933 case kFLEXIO_SPI_8bitLsb:
<> 154:37f96f9d4de2 934 dataMode = 8 * 2 - 1U;
<> 154:37f96f9d4de2 935 handle->bytePerFrame = 1U;
<> 154:37f96f9d4de2 936 handle->direction = kFLEXIO_SPI_LsbFirst;
<> 154:37f96f9d4de2 937 break;
<> 154:37f96f9d4de2 938 case kFLEXIO_SPI_16bitMsb:
<> 154:37f96f9d4de2 939 dataMode = 16 * 2 - 1U;
<> 154:37f96f9d4de2 940 handle->bytePerFrame = 2U;
<> 154:37f96f9d4de2 941 handle->direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 942 break;
<> 154:37f96f9d4de2 943 case kFLEXIO_SPI_16bitLsb:
<> 154:37f96f9d4de2 944 dataMode = 16 * 2 - 1U;
<> 154:37f96f9d4de2 945 handle->bytePerFrame = 2U;
<> 154:37f96f9d4de2 946 handle->direction = kFLEXIO_SPI_LsbFirst;
<> 154:37f96f9d4de2 947 break;
<> 154:37f96f9d4de2 948 default:
<> 154:37f96f9d4de2 949 dataMode = 8 * 2 - 1U;
<> 154:37f96f9d4de2 950 handle->bytePerFrame = 1U;
<> 154:37f96f9d4de2 951 handle->direction = kFLEXIO_SPI_MsbFirst;
<> 154:37f96f9d4de2 952 assert(true);
<> 154:37f96f9d4de2 953 break;
<> 154:37f96f9d4de2 954 }
<> 154:37f96f9d4de2 955
<> 154:37f96f9d4de2 956 /* Configure transfer size. */
<> 154:37f96f9d4de2 957 base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
<> 154:37f96f9d4de2 958
<> 154:37f96f9d4de2 959 handle->state = kFLEXIO_SPI_Busy;
<> 154:37f96f9d4de2 960 handle->txData = xfer->txData;
<> 154:37f96f9d4de2 961 handle->rxData = xfer->rxData;
<> 154:37f96f9d4de2 962 handle->txRemainingBytes = xfer->dataSize;
<> 154:37f96f9d4de2 963 handle->rxRemainingBytes = xfer->dataSize;
<> 154:37f96f9d4de2 964
<> 154:37f96f9d4de2 965 /* Save total transfer size. */
<> 154:37f96f9d4de2 966 handle->transferSize = xfer->dataSize;
<> 154:37f96f9d4de2 967
<> 154:37f96f9d4de2 968 /* Enable transmit and receive interrupt to handle tx and rx. */
<> 154:37f96f9d4de2 969 FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
<> 154:37f96f9d4de2 970 FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
<> 154:37f96f9d4de2 971
<> 154:37f96f9d4de2 972 return kStatus_Success;
<> 154:37f96f9d4de2 973 }
<> 154:37f96f9d4de2 974
<> 154:37f96f9d4de2 975 void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
<> 154:37f96f9d4de2 976 {
<> 154:37f96f9d4de2 977 assert(spiHandle);
<> 154:37f96f9d4de2 978
<> 154:37f96f9d4de2 979 flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
<> 154:37f96f9d4de2 980 FLEXIO_SPI_Type *base;
<> 154:37f96f9d4de2 981 uint32_t status;
<> 154:37f96f9d4de2 982
<> 154:37f96f9d4de2 983 if (handle->state == kFLEXIO_SPI_Idle)
<> 154:37f96f9d4de2 984 {
<> 154:37f96f9d4de2 985 return;
<> 154:37f96f9d4de2 986 }
<> 154:37f96f9d4de2 987
<> 154:37f96f9d4de2 988 base = (FLEXIO_SPI_Type *)spiType;
<> 154:37f96f9d4de2 989 status = FLEXIO_SPI_GetStatusFlags(base);
<> 154:37f96f9d4de2 990
<> 154:37f96f9d4de2 991 /* Handle tx. */
<> 154:37f96f9d4de2 992 if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes))
<> 154:37f96f9d4de2 993 {
<> 154:37f96f9d4de2 994 FLEXIO_SPI_TransferSendTransaction(base, handle);
<> 154:37f96f9d4de2 995 }
<> 154:37f96f9d4de2 996
<> 154:37f96f9d4de2 997 /* Handle rx. */
<> 154:37f96f9d4de2 998 if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes))
<> 154:37f96f9d4de2 999 {
<> 154:37f96f9d4de2 1000 FLEXIO_SPI_TransferReceiveTransaction(base, handle);
<> 154:37f96f9d4de2 1001 }
<> 154:37f96f9d4de2 1002
<> 154:37f96f9d4de2 1003 /* All the transfer finished. */
<> 154:37f96f9d4de2 1004 if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
<> 154:37f96f9d4de2 1005 {
<> 154:37f96f9d4de2 1006 FLEXIO_SPI_SlaveTransferAbort(base, handle);
<> 154:37f96f9d4de2 1007 if (handle->callback)
<> 154:37f96f9d4de2 1008 {
<> 154:37f96f9d4de2 1009 (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
<> 154:37f96f9d4de2 1010 }
<> 154:37f96f9d4de2 1011 }
<> 154:37f96f9d4de2 1012 }