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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_port.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30 #ifndef _FSL_PORT_H_
<> 154:37f96f9d4de2 31 #define _FSL_PORT_H_
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 #include "fsl_common.h"
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*!
<> 154:37f96f9d4de2 36 * @addtogroup port_driver
<> 154:37f96f9d4de2 37 * @{
<> 154:37f96f9d4de2 38 */
<> 154:37f96f9d4de2 39
<> 154:37f96f9d4de2 40 /*! @file */
<> 154:37f96f9d4de2 41
<> 154:37f96f9d4de2 42 /*******************************************************************************
<> 154:37f96f9d4de2 43 * Definitions
<> 154:37f96f9d4de2 44 ******************************************************************************/
<> 154:37f96f9d4de2 45
<> 154:37f96f9d4de2 46 /*! @name Driver version */
<> 154:37f96f9d4de2 47 /*@{*/
<> 154:37f96f9d4de2 48 /*! Version 2.0.1. */
<> 154:37f96f9d4de2 49 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
<> 154:37f96f9d4de2 50 /*@}*/
<> 154:37f96f9d4de2 51
<> 154:37f96f9d4de2 52 /*! @brief Internal resistor pull feature selection */
<> 154:37f96f9d4de2 53 enum _port_pull
<> 154:37f96f9d4de2 54 {
<> 154:37f96f9d4de2 55 kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */
<> 154:37f96f9d4de2 56 kPORT_PullDown = 2U, /*!< internal pull-down resistor is enabled. */
<> 154:37f96f9d4de2 57 kPORT_PullUp = 3U, /*!< internal pull-up resistor is enabled. */
<> 154:37f96f9d4de2 58 };
<> 154:37f96f9d4de2 59
<> 154:37f96f9d4de2 60 /*! @brief Slew rate selection */
<> 154:37f96f9d4de2 61 enum _port_slew_rate
<> 154:37f96f9d4de2 62 {
<> 154:37f96f9d4de2 63 kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */
<> 154:37f96f9d4de2 64 kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */
<> 154:37f96f9d4de2 65 };
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
<> 154:37f96f9d4de2 68 /*! @brief Internal resistor pull feature enable/disable */
<> 154:37f96f9d4de2 69 enum _port_open_drain_enable
<> 154:37f96f9d4de2 70 {
<> 154:37f96f9d4de2 71 kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */
<> 154:37f96f9d4de2 72 kPORT_OpenDrainEnable = 1U, /*!< internal pull-up resistor is enabled. */
<> 154:37f96f9d4de2 73 };
<> 154:37f96f9d4de2 74 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
<> 154:37f96f9d4de2 75
<> 154:37f96f9d4de2 76 /*! @brief Passive filter feature enable/disable */
<> 154:37f96f9d4de2 77 enum _port_passive_filter_enable
<> 154:37f96f9d4de2 78 {
<> 154:37f96f9d4de2 79 kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */
<> 154:37f96f9d4de2 80 kPORT_PassiveFilterEnable = 1U, /*!< slow slew rate is configured. */
<> 154:37f96f9d4de2 81 };
<> 154:37f96f9d4de2 82
<> 154:37f96f9d4de2 83 /*! @brief Configures the drive strength. */
<> 154:37f96f9d4de2 84 enum _port_drive_strength
<> 154:37f96f9d4de2 85 {
<> 154:37f96f9d4de2 86 kPORT_LowDriveStrength = 0U, /*!< low drive strength is configured. */
<> 154:37f96f9d4de2 87 kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */
<> 154:37f96f9d4de2 88 };
<> 154:37f96f9d4de2 89
<> 154:37f96f9d4de2 90 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
<> 154:37f96f9d4de2 91 /*! @brief Unlock/lock the pin control register field[15:0] */
<> 154:37f96f9d4de2 92 enum _port_lock_register
<> 154:37f96f9d4de2 93 {
<> 154:37f96f9d4de2 94 kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
<> 154:37f96f9d4de2 95 kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
<> 154:37f96f9d4de2 96 };
<> 154:37f96f9d4de2 97 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
<> 154:37f96f9d4de2 98
<> 154:37f96f9d4de2 99 /*! @brief Pin mux selection */
<> 154:37f96f9d4de2 100 typedef enum _port_mux
<> 154:37f96f9d4de2 101 {
<> 154:37f96f9d4de2 102 kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */
<> 154:37f96f9d4de2 103 kPORT_MuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO. */
<> 154:37f96f9d4de2 104 kPORT_MuxAlt2 = 2U, /*!< chip-specific */
<> 154:37f96f9d4de2 105 kPORT_MuxAlt3 = 3U, /*!< chip-specific */
<> 154:37f96f9d4de2 106 kPORT_MuxAlt4 = 4U, /*!< chip-specific */
<> 154:37f96f9d4de2 107 kPORT_MuxAlt5 = 5U, /*!< chip-specific */
<> 154:37f96f9d4de2 108 kPORT_MuxAlt6 = 6U, /*!< chip-specific */
<> 154:37f96f9d4de2 109 kPORT_MuxAlt7 = 7U, /*!< chip-specific */
<> 154:37f96f9d4de2 110 } port_mux_t;
<> 154:37f96f9d4de2 111
<> 154:37f96f9d4de2 112 /*! @brief Configures the interrupt generation condition. */
<> 154:37f96f9d4de2 113 typedef enum _port_interrupt
<> 154:37f96f9d4de2 114 {
<> 154:37f96f9d4de2 115 kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
<> 154:37f96f9d4de2 116 #if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
<> 154:37f96f9d4de2 117 kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
<> 154:37f96f9d4de2 118 kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
<> 154:37f96f9d4de2 119 kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
<> 154:37f96f9d4de2 120 #endif
<> 154:37f96f9d4de2 121 #if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
<> 154:37f96f9d4de2 122 kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
<> 154:37f96f9d4de2 123 kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
<> 154:37f96f9d4de2 124 kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
<> 154:37f96f9d4de2 125 #endif
<> 154:37f96f9d4de2 126 kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
<> 154:37f96f9d4de2 127 kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
<> 154:37f96f9d4de2 128 kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
<> 154:37f96f9d4de2 129 kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
<> 154:37f96f9d4de2 130 kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
<> 154:37f96f9d4de2 131 #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
<> 154:37f96f9d4de2 132 kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */
<> 154:37f96f9d4de2 133 kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low trigger output. */
<> 154:37f96f9d4de2 134 #endif
<> 154:37f96f9d4de2 135 } port_interrupt_t;
<> 154:37f96f9d4de2 136
<> 154:37f96f9d4de2 137 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
<> 154:37f96f9d4de2 138 /*! @brief Digital filter clock source selection */
<> 154:37f96f9d4de2 139 typedef enum _port_digital_filter_clock_source
<> 154:37f96f9d4de2 140 {
<> 154:37f96f9d4de2 141 kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
<> 154:37f96f9d4de2 142 kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
<> 154:37f96f9d4de2 143 } port_digital_filter_clock_source_t;
<> 154:37f96f9d4de2 144
<> 154:37f96f9d4de2 145 /*! @brief PORT digital filter feature configuration definition */
<> 154:37f96f9d4de2 146 typedef struct _port_digital_filter_config
<> 154:37f96f9d4de2 147 {
<> 154:37f96f9d4de2 148 uint32_t digitalFilterWidth; /*!< Set digital filter width */
<> 154:37f96f9d4de2 149 port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
<> 154:37f96f9d4de2 150 } port_digital_filter_config_t;
<> 154:37f96f9d4de2 151 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
<> 154:37f96f9d4de2 152
<> 154:37f96f9d4de2 153 /*! @brief PORT pin config structure */
<> 154:37f96f9d4de2 154 typedef struct _port_pin_config
<> 154:37f96f9d4de2 155 {
<> 154:37f96f9d4de2 156 uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */
<> 154:37f96f9d4de2 157 uint16_t slewRate : 1; /*!< fast/slow slew rate Configure */
<> 154:37f96f9d4de2 158 uint16_t : 1;
<> 154:37f96f9d4de2 159 uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */
<> 154:37f96f9d4de2 160 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
<> 154:37f96f9d4de2 161 uint16_t openDrainEnable : 1; /*!< open drain enable/disable */
<> 154:37f96f9d4de2 162 #else
<> 154:37f96f9d4de2 163 uint16_t : 1;
<> 154:37f96f9d4de2 164 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
<> 154:37f96f9d4de2 165 uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */
<> 154:37f96f9d4de2 166 uint16_t : 1;
<> 154:37f96f9d4de2 167 uint16_t mux : 3; /*!< pin mux Configure */
<> 154:37f96f9d4de2 168 uint16_t : 4;
<> 154:37f96f9d4de2 169 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
<> 154:37f96f9d4de2 170 uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */
<> 154:37f96f9d4de2 171 #else
<> 154:37f96f9d4de2 172 uint16_t : 1;
<> 154:37f96f9d4de2 173 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
<> 154:37f96f9d4de2 174 } port_pin_config_t;
<> 154:37f96f9d4de2 175
<> 154:37f96f9d4de2 176 /*******************************************************************************
<> 154:37f96f9d4de2 177 * API
<> 154:37f96f9d4de2 178 ******************************************************************************/
<> 154:37f96f9d4de2 179
<> 154:37f96f9d4de2 180 #if defined(__cplusplus)
<> 154:37f96f9d4de2 181 extern "C" {
<> 154:37f96f9d4de2 182 #endif
<> 154:37f96f9d4de2 183
<> 154:37f96f9d4de2 184 /*! @name Configuration */
<> 154:37f96f9d4de2 185 /*@{*/
<> 154:37f96f9d4de2 186
<> 154:37f96f9d4de2 187 /*!
<> 154:37f96f9d4de2 188 * @brief Sets the port PCR register.
<> 154:37f96f9d4de2 189 *
<> 154:37f96f9d4de2 190 * This is an example to define an input pin or output pin PCR configuration:
<> 154:37f96f9d4de2 191 * @code
<> 154:37f96f9d4de2 192 * // Define a digital input pin PCR configuration
<> 154:37f96f9d4de2 193 * port_pin_config_t config = {
<> 154:37f96f9d4de2 194 * kPORT_PullUp,
<> 154:37f96f9d4de2 195 * kPORT_FastSlewRate,
<> 154:37f96f9d4de2 196 * kPORT_PassiveFilterDisable,
<> 154:37f96f9d4de2 197 * kPORT_OpenDrainDisable,
<> 154:37f96f9d4de2 198 * kPORT_LowDriveStrength,
<> 154:37f96f9d4de2 199 * kPORT_MuxAsGpio,
<> 154:37f96f9d4de2 200 * kPORT_UnLockRegister,
<> 154:37f96f9d4de2 201 * };
<> 154:37f96f9d4de2 202 * @endcode
<> 154:37f96f9d4de2 203 *
<> 154:37f96f9d4de2 204 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 205 * @param pin PORT pin number.
<> 154:37f96f9d4de2 206 * @param config PORT PCR register configure structure.
<> 154:37f96f9d4de2 207 */
<> 154:37f96f9d4de2 208 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
<> 154:37f96f9d4de2 209 {
<> 154:37f96f9d4de2 210 assert(config);
<> 154:37f96f9d4de2 211 uint32_t addr = (uint32_t)&base->PCR[pin];
<> 154:37f96f9d4de2 212 *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
<> 154:37f96f9d4de2 213 }
<> 154:37f96f9d4de2 214
<> 154:37f96f9d4de2 215 /*!
<> 154:37f96f9d4de2 216 * @brief Sets the port PCR register for multiple pins.
<> 154:37f96f9d4de2 217 *
<> 154:37f96f9d4de2 218 * This is an example to define input pins or output pins PCR configuration:
<> 154:37f96f9d4de2 219 * @code
<> 154:37f96f9d4de2 220 * // Define a digital input pin PCR configuration
<> 154:37f96f9d4de2 221 * port_pin_config_t config = {
<> 154:37f96f9d4de2 222 * kPORT_PullUp ,
<> 154:37f96f9d4de2 223 * kPORT_PullEnable,
<> 154:37f96f9d4de2 224 * kPORT_FastSlewRate,
<> 154:37f96f9d4de2 225 * kPORT_PassiveFilterDisable,
<> 154:37f96f9d4de2 226 * kPORT_OpenDrainDisable,
<> 154:37f96f9d4de2 227 * kPORT_LowDriveStrength,
<> 154:37f96f9d4de2 228 * kPORT_MuxAsGpio,
<> 154:37f96f9d4de2 229 * kPORT_UnlockRegister,
<> 154:37f96f9d4de2 230 * };
<> 154:37f96f9d4de2 231 * @endcode
<> 154:37f96f9d4de2 232 *
<> 154:37f96f9d4de2 233 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 234 * @param mask PORT pins' numbers macro.
<> 154:37f96f9d4de2 235 * @param config PORT PCR register configure structure.
<> 154:37f96f9d4de2 236 */
<> 154:37f96f9d4de2 237 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
<> 154:37f96f9d4de2 238 {
<> 154:37f96f9d4de2 239 assert(config);
<> 154:37f96f9d4de2 240
<> 154:37f96f9d4de2 241 uint16_t pcrl = *((const uint16_t *)config);
<> 154:37f96f9d4de2 242
<> 154:37f96f9d4de2 243 if (mask & 0xffffU)
<> 154:37f96f9d4de2 244 {
<> 154:37f96f9d4de2 245 base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
<> 154:37f96f9d4de2 246 }
<> 154:37f96f9d4de2 247 if (mask >> 16)
<> 154:37f96f9d4de2 248 {
<> 154:37f96f9d4de2 249 base->GPCHR = (mask & 0xffff0000U) | pcrl;
<> 154:37f96f9d4de2 250 }
<> 154:37f96f9d4de2 251 }
<> 154:37f96f9d4de2 252
<> 154:37f96f9d4de2 253 /*!
<> 154:37f96f9d4de2 254 * @brief Configures the pin muxing.
<> 154:37f96f9d4de2 255 *
<> 154:37f96f9d4de2 256 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 257 * @param pin PORT pin number.
<> 154:37f96f9d4de2 258 * @param mux pin muxing slot selection.
<> 154:37f96f9d4de2 259 * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
<> 154:37f96f9d4de2 260 * - #kPORT_MuxAsGpio : Set as GPIO.
<> 154:37f96f9d4de2 261 * - #kPORT_MuxAlt2 : chip-specific.
<> 154:37f96f9d4de2 262 * - #kPORT_MuxAlt3 : chip-specific.
<> 154:37f96f9d4de2 263 * - #kPORT_MuxAlt4 : chip-specific.
<> 154:37f96f9d4de2 264 * - #kPORT_MuxAlt5 : chip-specific.
<> 154:37f96f9d4de2 265 * - #kPORT_MuxAlt6 : chip-specific.
<> 154:37f96f9d4de2 266 * - #kPORT_MuxAlt7 : chip-specific.
<> 154:37f96f9d4de2 267 * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
<> 154:37f96f9d4de2 268 * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will
<> 154:37f96f9d4de2 269 * be reset to zero : kPORT_PinDisabledOrAnalog).
<> 154:37f96f9d4de2 270 * This function is recommended to use in the case you just need to reset the pin mux
<> 154:37f96f9d4de2 271 *
<> 154:37f96f9d4de2 272 */
<> 154:37f96f9d4de2 273 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
<> 154:37f96f9d4de2 274 {
<> 154:37f96f9d4de2 275 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
<> 154:37f96f9d4de2 276 }
<> 154:37f96f9d4de2 277
<> 154:37f96f9d4de2 278 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
<> 154:37f96f9d4de2 279
<> 154:37f96f9d4de2 280 /*!
<> 154:37f96f9d4de2 281 * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
<> 154:37f96f9d4de2 282 *
<> 154:37f96f9d4de2 283 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 284 * @param mask PORT pins' numbers macro.
<> 154:37f96f9d4de2 285 */
<> 154:37f96f9d4de2 286 static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
<> 154:37f96f9d4de2 287 {
<> 154:37f96f9d4de2 288 if (enable == true)
<> 154:37f96f9d4de2 289 {
<> 154:37f96f9d4de2 290 base->DFER |= mask;
<> 154:37f96f9d4de2 291 }
<> 154:37f96f9d4de2 292 else
<> 154:37f96f9d4de2 293 {
<> 154:37f96f9d4de2 294 base->DFER &= ~mask;
<> 154:37f96f9d4de2 295 }
<> 154:37f96f9d4de2 296 }
<> 154:37f96f9d4de2 297
<> 154:37f96f9d4de2 298 /*!
<> 154:37f96f9d4de2 299 * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
<> 154:37f96f9d4de2 300 *
<> 154:37f96f9d4de2 301 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 302 * @param config PORT digital filter configuration structure.
<> 154:37f96f9d4de2 303 */
<> 154:37f96f9d4de2 304 static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
<> 154:37f96f9d4de2 305 {
<> 154:37f96f9d4de2 306 assert(config);
<> 154:37f96f9d4de2 307
<> 154:37f96f9d4de2 308 base->DFCR = PORT_DFCR_CS(config->clockSource);
<> 154:37f96f9d4de2 309 base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
<> 154:37f96f9d4de2 310 }
<> 154:37f96f9d4de2 311
<> 154:37f96f9d4de2 312 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
<> 154:37f96f9d4de2 313
<> 154:37f96f9d4de2 314 /*@}*/
<> 154:37f96f9d4de2 315
<> 154:37f96f9d4de2 316 /*! @name Interrupt */
<> 154:37f96f9d4de2 317 /*@{*/
<> 154:37f96f9d4de2 318
<> 154:37f96f9d4de2 319 /*!
<> 154:37f96f9d4de2 320 * @brief Configures the port pin interrupt/DMA request.
<> 154:37f96f9d4de2 321 *
<> 154:37f96f9d4de2 322 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 323 * @param pin PORT pin number.
<> 154:37f96f9d4de2 324 * @param config PORT pin interrupt configuration.
<> 154:37f96f9d4de2 325 * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
<> 154:37f96f9d4de2 326 * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
<> 154:37f96f9d4de2 327 * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
<> 154:37f96f9d4de2 328 * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
<> 154:37f96f9d4de2 329 * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
<> 154:37f96f9d4de2 330 * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
<> 154:37f96f9d4de2 331 * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
<> 154:37f96f9d4de2 332 * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
<> 154:37f96f9d4de2 333 * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
<> 154:37f96f9d4de2 334 * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
<> 154:37f96f9d4de2 335 * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
<> 154:37f96f9d4de2 336 * - #kPORT_InterruptLogicOne : Interrupt when logic one.
<> 154:37f96f9d4de2 337 * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit).
<> 154:37f96f9d4de2 338 * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low trigger output(if the trigger states exit).
<> 154:37f96f9d4de2 339 */
<> 154:37f96f9d4de2 340 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
<> 154:37f96f9d4de2 341 {
<> 154:37f96f9d4de2 342 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
<> 154:37f96f9d4de2 343 }
<> 154:37f96f9d4de2 344
<> 154:37f96f9d4de2 345 /*!
<> 154:37f96f9d4de2 346 * @brief Reads the whole port status flag.
<> 154:37f96f9d4de2 347 *
<> 154:37f96f9d4de2 348 * If a pin is configured to generate the DMA request, the corresponding flag
<> 154:37f96f9d4de2 349 * is cleared automatically at the completion of the requested DMA transfer.
<> 154:37f96f9d4de2 350 * Otherwise, the flag remains set until a logic one is written to that flag.
<> 154:37f96f9d4de2 351 * If configured for a level sensitive interrupt that remains asserted, the flag
<> 154:37f96f9d4de2 352 * is set again immediately.
<> 154:37f96f9d4de2 353 *
<> 154:37f96f9d4de2 354 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 355 * @return Current port interrupt status flags, for example, 0x00010001 means the
<> 154:37f96f9d4de2 356 * pin 0 and 17 have the interrupt.
<> 154:37f96f9d4de2 357 */
<> 154:37f96f9d4de2 358 static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
<> 154:37f96f9d4de2 359 {
<> 154:37f96f9d4de2 360 return base->ISFR;
<> 154:37f96f9d4de2 361 }
<> 154:37f96f9d4de2 362
<> 154:37f96f9d4de2 363 /*!
<> 154:37f96f9d4de2 364 * @brief Clears the multiple pins' interrupt status flag.
<> 154:37f96f9d4de2 365 *
<> 154:37f96f9d4de2 366 * @param base PORT peripheral base pointer.
<> 154:37f96f9d4de2 367 * @param mask PORT pins' numbers macro.
<> 154:37f96f9d4de2 368 */
<> 154:37f96f9d4de2 369 static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 370 {
<> 154:37f96f9d4de2 371 base->ISFR = mask;
<> 154:37f96f9d4de2 372 }
<> 154:37f96f9d4de2 373
<> 154:37f96f9d4de2 374 /*@}*/
<> 154:37f96f9d4de2 375
<> 154:37f96f9d4de2 376 #if defined(__cplusplus)
<> 154:37f96f9d4de2 377 }
<> 154:37f96f9d4de2 378 #endif
<> 154:37f96f9d4de2 379
<> 154:37f96f9d4de2 380 /*! @}*/
<> 154:37f96f9d4de2 381
<> 154:37f96f9d4de2 382 #endif /* _FSL_PORT_H_ */